repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
tgingold/ghdl | libraries/openieee/v93/numeric_std.vhdl | 2 | 10556 | -- This -*- vhdl -*- file is part of GHDL.
-- IEEE 1076.3 compliant numeric std package.
-- Copyright (C) 2015 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING2. If not see
-- <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package NUMERIC_STD is
type UNSIGNED is array (natural range <>) of STD_LOGIC;
type SIGNED is array (natural range <>) of STD_LOGIC;
function TO_01 (S : SIGNED; XMAP : STD_LOGIC := '0') return SIGNED;
function TO_01 (S : UNSIGNED; XMAP : STD_LOGIC := '0') return UNSIGNED;
-- Convert 'H' and '1' to '1', 'L' and '0' to '0'.
-- If any other value is present, return (others => XMAP)
-- Issue a warning in that case, and if S is a null array.
-- Result index range is S'Length - 1 downto 0.
function std_match (l, r : std_ulogic) return boolean;
function std_match (l, r : std_ulogic_vector) return boolean;
function std_match (l, r : std_logic_vector) return boolean;
function std_match (l, r : UNSIGNED) return boolean;
function std_match (l, r : SIGNED) return boolean;
-- Return True iff L and R matches.
function TO_INTEGER (ARG : UNSIGNED) return NATURAL;
function TO_INTEGER (ARG : SIGNED) return INTEGER;
-- Convert ARG to an integer.
-- Simulation is aborted in case of overflow.
-- Issue a warning in case of non-logical value.
function TO_UNSIGNED (ARG, SIZE : NATURAL) return UNSIGNED;
-- Convert ARG to unsigned.
-- Result index range is SIZE - 1 downto 0.
-- Issue a warning if value is truncated.
function TO_SIGNED (ARG : INTEGER; SIZE : NATURAL) return SIGNED;
-- Convert ARG to signed.
-- Result index range is SIZE - 1 downto 0.
-- Issue a warning if value is truncated.
function resize (ARG : UNSIGNED; NEW_SIZE: natural) return UNSIGNED;
function resize (ARG : SIGNED; NEW_SIZE: natural) return SIGNED;
-- Result index range is NEW_SIZE - 1 downto 0 (unless null array).
-- For SIGNED, the sign of the result is the sign of ARG.
function "=" (L, R : UNSIGNED) return BOOLEAN;
function "=" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
function "=" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
function "/=" (L, R : UNSIGNED) return BOOLEAN;
function "/=" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
function "/=" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
function "<" (L, R : UNSIGNED) return BOOLEAN;
function "<" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
function "<" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
function "<=" (L, R : UNSIGNED) return BOOLEAN;
function "<=" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
function "<=" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
function ">" (L, R : UNSIGNED) return BOOLEAN;
function ">" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
function ">" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
function ">=" (L, R : UNSIGNED) return BOOLEAN;
function ">=" (L : UNSIGNED; R : NATURAL) return BOOLEAN;
function ">=" (L : NATURAL; R : UNSIGNED) return BOOLEAN;
function "=" (L, R : SIGNED) return BOOLEAN;
function "=" (L : SIGNED; R : INTEGER) return BOOLEAN;
function "=" (L : INTEGER; R : SIGNED) return BOOLEAN;
function "/=" (L, R : SIGNED) return BOOLEAN;
function "/=" (L : SIGNED; R : INTEGER) return BOOLEAN;
function "/=" (L : INTEGER; R : SIGNED) return BOOLEAN;
function "<" (L, R : SIGNED) return BOOLEAN;
function "<" (L : SIGNED; R : INTEGER) return BOOLEAN;
function "<" (L : INTEGER; R : SIGNED) return BOOLEAN;
function "<=" (L, R : SIGNED) return BOOLEAN;
function "<=" (L : SIGNED; R : INTEGER) return BOOLEAN;
function "<=" (L : INTEGER; R : SIGNED) return BOOLEAN;
function ">" (L, R : SIGNED) return BOOLEAN;
function ">" (L : SIGNED; R : INTEGER) return BOOLEAN;
function ">" (L : INTEGER; R : SIGNED) return BOOLEAN;
function ">=" (L, R : SIGNED) return BOOLEAN;
function ">=" (L : SIGNED; R : INTEGER) return BOOLEAN;
function ">=" (L : INTEGER; R : SIGNED) return BOOLEAN;
-- Issue a warning in case of non-logical value.
function "-" (ARG : SIGNED) return SIGNED;
-- Compute -ARG.
-- Result index range is Arg'length - 1 downto 0.
function "abs" (ARG : SIGNED) return SIGNED;
-- Compute abs ARG.
-- Result index range is Arg'length - 1 downto 0.
function "+" (L, R : UNSIGNED) return UNSIGNED;
function "+" (L, R : SIGNED) return SIGNED;
function "-" (L, R : UNSIGNED) return UNSIGNED;
function "-" (L, R : SIGNED) return SIGNED;
-- Compute L +/- R.
-- Result index range is max (L'Length, R'Length) - 1 downto 0.
-- Issue a warning in case of non-logical value.
function "+" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
function "+" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
function "+" (L : SIGNED; R : INTEGER) return SIGNED;
function "+" (L : INTEGER; R : SIGNED) return SIGNED;
function "-" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
function "-" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
function "-" (L : SIGNED; R : INTEGER) return SIGNED;
function "-" (L : INTEGER; R : SIGNED) return SIGNED;
-- Compute L +/- R.
-- Result index range is V'Length - 1 downto 0, where V is the vector
-- parameter.
-- Issue a warning in case of non-logical value.
-- Issue a warning if value is truncated.
function "*" (L, R : UNSIGNED) return UNSIGNED;
function "*" (L, R : SIGNED) return SIGNED;
-- Compute L * R
-- Result index range is L'Length + R'Length - 1 downto 0.
function "*" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
function "*" (L : SIGNED; R : INTEGER) return SIGNED;
-- Compute L * R
-- R is converted to a vector of length L'length
function "*" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
function "*" (L : INTEGER; R : SIGNED) return SIGNED;
-- Compute L * R
-- L is converted to a vector of length R'length
function "/" (L, R : UNSIGNED) return UNSIGNED;
function "/" (L, R : SIGNED) return SIGNED;
function "rem" (L, R : UNSIGNED) return UNSIGNED;
function "rem" (L, R : SIGNED) return SIGNED;
function "mod" (L, R : UNSIGNED) return UNSIGNED;
function "mod" (L, R : SIGNED) return SIGNED;
-- Compute L op R
-- Result index range is L'Length - 1 downto 0.
-- Issue a warning in case of non-logical value.
-- Issue an error if R is 0.
function "/" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
function "/" (L : SIGNED; R : INTEGER) return SIGNED;
function "rem" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
function "rem" (L : SIGNED; R : INTEGER) return SIGNED;
function "mod" (L : UNSIGNED; R : NATURAL) return UNSIGNED;
function "mod" (L : SIGNED; R : INTEGER) return SIGNED;
-- Compute L op R.
-- Result index range is L'Length - 1 downto 0.
-- Issue a warning in case of non-logical value.
-- Issue an error if R is 0.
function "/" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
function "/" (L : INTEGER; R : SIGNED) return SIGNED;
function "rem" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
function "rem" (L : INTEGER; R : SIGNED) return SIGNED;
function "mod" (L : NATURAL; R : UNSIGNED) return UNSIGNED;
function "mod" (L : INTEGER; R : SIGNED) return SIGNED;
-- Compute L op R.
-- Result index range is R'Length - 1 downto 0.
-- Issue a warning in case of non-logical value.
-- Issue an error if R is 0.
-- Result may be truncated.
function "not" (l : UNSIGNED) return UNSIGNED;
function "not" (l : SIGNED) return SIGNED;
function "and" (l, r : UNSIGNED) return UNSIGNED;
function "and" (l, r : SIGNED) return SIGNED;
function "nand" (l, r : UNSIGNED) return UNSIGNED;
function "nand" (l, r : SIGNED) return SIGNED;
function "or" (l, r : UNSIGNED) return UNSIGNED;
function "or" (l, r : SIGNED) return SIGNED;
function "nor" (l, r : UNSIGNED) return UNSIGNED;
function "nor" (l, r : SIGNED) return SIGNED;
function "xor" (l, r : UNSIGNED) return UNSIGNED;
function "xor" (l, r : SIGNED) return SIGNED;
function "xnor" (l, r : UNSIGNED) return UNSIGNED;
function "xnor" (l, r : SIGNED) return SIGNED;
-- Compute L OP R.
-- Result index range is L'Length - 1 downto 0.
-- No specific handling of null array: the index range of the result
-- would be -1 downto 0 (without warning). This it not what is specified
-- in 1076.3, but corresponds to the standard implementation.
-- No specific handling of non-logical values. Behaviour is compatible
-- with std_logic_1164.
function shift_left (ARG : UNSIGNED; COUNT: NATURAL) return UNSIGNED;
function shift_left (ARG : SIGNED; COUNT: NATURAL) return SIGNED;
function shift_right (ARG : UNSIGNED; COUNT: NATURAL) return UNSIGNED;
function shift_right (ARG : SIGNED; COUNT: NATURAL) return SIGNED;
-- Result index range is ARG'Length - 1 downto 0.
function rotate_left (ARG : UNSIGNED; COUNT: NATURAL) return UNSIGNED;
function rotate_left (ARG : SIGNED; COUNT: NATURAL) return SIGNED;
function rotate_right (ARG : UNSIGNED; COUNT: NATURAL) return UNSIGNED;
function rotate_right (ARG : SIGNED; COUNT: NATURAL) return SIGNED;
-- Result index range is ARG'Length - 1 downto 0.
function "sll" (ARG : UNSIGNED; COUNT: INTEGER) return UNSIGNED;
function "sll" (ARG : SIGNED; COUNT: INTEGER) return SIGNED;
function "srl" (ARG : UNSIGNED; COUNT: INTEGER) return UNSIGNED;
function "srl" (ARG : SIGNED; COUNT: INTEGER) return SIGNED;
-- Result index range is ARG'Length - 1 downto 0.
function "rol" (ARG : UNSIGNED; COUNT: INTEGER) return UNSIGNED;
function "rol" (ARG : SIGNED; COUNT: INTEGER) return SIGNED;
function "ror" (ARG : UNSIGNED; COUNT: INTEGER) return UNSIGNED;
function "ror" (ARG : SIGNED; COUNT: INTEGER) return SIGNED;
-- Result index range is ARG'Length - 1 downto 0.
end NUMERIC_STD;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1938.vhd | 4 | 1943 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1938.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n04i01938ent IS
END c07s02b01x00p01n04i01938ent;
ARCHITECTURE c07s02b01x00p01n04i01938arch OF c07s02b01x00p01n04i01938ent IS
BEGIN
TESTING: PROCESS
type array_one is array (positive range <>) of boolean;
variable x : array_one( 1 to 10);
variable y : array_one(1 to 5);
variable z : array_one(1 to 10);
type array_two is array (positive range <>) of bit;
variable a : array_two( 1 to 10);
variable b : array_two(1 to 5);
variable c : array_two(1 to 10);
BEGIN
c := (a or b); -- Failure_here
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n04i01938 - Operands should be arrays of the same length."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n04i01938arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2672.vhd | 4 | 1676 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2672.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02672ent IS
END c13s03b01x00p02n01i02672ent;
ARCHITECTURE c13s03b01x00p02n01i02672arch OF c13s03b01x00p02n01i02672ent IS
BEGIN
TESTING: PROCESS
variable {k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02672 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02672arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/dff02/tb_dff06.vhdl | 1 | 872 | entity tb_dff06 is
end tb_dff06;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff06 is
signal clk : std_logic;
signal rst : std_logic;
signal din : std_logic_vector (7 downto 0);
signal dout : std_logic_vector (7 downto 0);
begin
dut: entity work.dff06
port map (
q => dout,
d => din,
clk => clk,
rst => rst);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rst <= '0';
din <= x"7e";
pulse;
assert dout = x"7e" severity failure;
din <= x"38";
pulse;
assert dout = x"38" severity failure;
rst <= '1';
din <= x"af";
pulse;
assert dout = x"38" severity failure;
rst <= '0';
pulse;
assert dout = x"af" severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc896.vhd | 4 | 1749 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc896.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s02b00x00p02n02i00896ent IS
generic ( x : integer := 2 );
END c10s02b00x00p02n02i00896ent;
ARCHITECTURE c10s02b00x00p02n02i00896arch OF c10s02b00x00p02n02i00896ent IS
BEGIN
-- extended use of declared generic.
assert NOT( x = 2 )
report "***PASSED TEST: c10s02b00x00p02n02i00896"
severity NOTE;
assert ( x = 2 )
report "***FAILED TEST: c10s02b00x00p02n02i00896 - The scope of the declaration that occurs immediately within a formal generic declaration extends beyond the immediate scope."
severity ERROR;
END c10s02b00x00p02n02i00896arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3012.vhd | 4 | 1977 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3012.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s06b00x00p08n01i03012pkg is
constant X1 : integer;
constant X2 : integer;
end c02s06b00x00p08n01i03012pkg;
package body c02s06b00x00p08n01i03012pkg is
constant X1: integer := X2; --Failure_here
constant X2: integer := 1;
end c02s06b00x00p08n01i03012pkg;
ENTITY c02s06b00x00p08n01i03012ent IS
END c02s06b00x00p08n01i03012ent;
ARCHITECTURE c02s06b00x00p08n01i03012arch OF c02s06b00x00p08n01i03012ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s06b00x00p08n01i03012 - A name that denotes the name of a deferred constant can appear, before the full declaration only in the default expression for a local generic, local port, or a formal parameter."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s06b00x00p08n01i03012arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS2_Mixed_Tech/tb_CS2_S_Domain.vhd | 4 | 14843 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
use IEEE.MATH_REAL.all;
library IEEE_proposed;
use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
entity v_sine is
generic (
freq : real; -- frequency [Hertz]
amplitude : voltage; -- amplitude [Volts]
phase : real := 0.0; -- initial phase [Degrees]
offset : voltage := 0.0; -- DC value [Volts]
df : real := 0.0; -- damping factor [1/second]
ac_mag : voltage := 1.0; -- AC magnitude [Volts]
ac_phase : real := 0.0); -- AC phase [Degrees]
port (
terminal pos, neg : electrical);
end entity v_sine;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of v_sine is
-- Declare Branch Quantities
quantity v across i through pos to neg;
-- Declare Quantity for Phase in radians (calculated below)
quantity phase_rad : real;
-- Declare Quantity in frequency domain for AC analysis
quantity ac_spec : real spectrum ac_mag, math_2_pi*ac_phase/360.0;
begin
-- Convert phase to radians
phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
if domain = quiescent_domain or domain = time_domain use
v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
else
v == ac_spec; -- used for Frequency (AC) analysis
end use;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
library IEEE;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.fluidic_systems.all;
use IEEE_proposed.thermal_systems.all;
use IEEE_proposed.radiant_systems.all;
entity sum2_e is
generic (k1, k2: real := 1.0); -- Gain multipliers
port ( terminal in1, in2: electrical;
terminal output: electrical);
end entity sum2_e;
architecture simple of sum2_e is
QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF;
QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
begin
vout == k1*vin1 + k2*vin2;
end architecture simple;
--
-------------------------------------------------------------------------------
-- Lead-Lag Filter
--
-- Transfer Function:
--
-- (s + w1)
-- H(s) = k * ----------
-- (s + w2)
--
-- DC Gain = k*w1/w2
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE; use ieee.math_real.all;
entity lead_lag_e is
generic (
k: real := 1.0; -- Gain multiplier
f1: real := 10.0; -- First break frequency (zero)
f2: real := 100.0); -- Second break frequency (pole)
port ( terminal input: electrical;
terminal output: electrical);
end entity lead_lag_e;
architecture simple of lead_lag_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
quantity vin_temp : real;
constant w1 : real := f1*math_2_pi;
constant w2 : real := f2*math_2_pi;
constant num : real_vector := (w1, 1.0);
constant den : real_vector := (w2, 1.0);
begin
vin_temp == vin;
vout == k*vin_temp'ltf(num, den);
end architecture simple;
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
entity gain_e is
generic (
k: REAL := 1.0); -- Gain multiplier
port ( terminal input : electrical;
terminal output: electrical);
end entity gain_e;
architecture simple of gain_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
begin
vout == k*vin;
end architecture simple;
--
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE;
use ieee.math_real.all;
entity limiter_2_e is
generic (
limit_high : real := 4.8; -- upper limit
limit_low : real := -4.8); -- lower limit
port (
terminal input: electrical;
terminal output: electrical);
end entity limiter_2_e;
architecture simple of limiter_2_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
constant slope : real := 1.0e-4;
begin
if vin > limit_high use -- Upper limit exceeded, so limit input signal
vout == limit_high + slope*(vin - limit_high);
elsif vin < limit_low use -- Lower limit exceeded, so limit input signal
vout == limit_low + slope*(vin - limit_low);
else -- No limit exceeded, so pass input signal as is
vout == vin;
end use;
break on vin'above(limit_high), vin'above(limit_low);
end architecture simple;
--
-------------------------------------------------------------------------------
-- Control Horn for Rudder Control
--
-- Transfer Function:
--
-- pos_t_out = R*sin(theta)
--
-- Where pos_t = output translational position,
-- R = horn radius,
-- theta_in = input rotational angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE;
use ieee.math_real.all;
entity ctl_horn_e is
generic (
R : real := 1.0); -- horn radius
port (
terminal theta_in : electrical; -- input port
terminal pos_t_out : electrical); -- output port
end entity ctl_horn_e;
architecture bhv of ctl_horn_e is
quantity vin across theta_in to electrical_ref;
quantity vout across iout through pos_t_out to electrical_ref;
begin -- bhv
vout == R*sin(vin);
end bhv;
--
-------------------------------------------------------------------------------
-- Rudder Model
--
-- Transfer Function:
--
-- theta_out = arcsin(pos_t_in/R)
--
-- Where pos_t_in = input translational position,
-- R = horn radius,
-- theta_out = output rotational angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity rudder_horn_e is
generic (
R : real := 1.0); -- Rudder horn radius
port (
terminal pos_t_in : electrical; -- input port
terminal theta_out : electrical); -- output port
end entity rudder_horn_e;
architecture bhv of rudder_horn_e is
quantity vin across pos_t_in to electrical_ref;
quantity vout across iout through theta_out to electrical_ref;
begin -- bhv
vout == arcsin(vin/R);
end bhv;
--
-------------------------------------------------------------------------------
-- Integrator
--
-- Transfer Function:
--
-- k
-- H(s) = ---------
-- s
--
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE;
use ieee.math_real.all;
entity integ_1_e is
generic (
k: real := 1.0; -- Gain
init: real := 0.0); -- Initial value of output
port (terminal input: electrical;
terminal output: electrical);
end entity integ_1_e;
architecture simple of integ_1_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
quantity vin_temp : real;
begin
vin_temp == vin;
IF domain = QUIESCENT_DOMAIN AND init /= 0.0 USE
vout == init;
ELSE
vout == k*vin_temp'INTEG;
END USE;
end architecture simple;
--
-------------------------------------------------------------------------------
-- Second Order Lowpass filter
--
-- Transfer Function:
--
-- w1*w2
-- H(s) = k * ----------------
-- (s + w1)(s + w2)
--
-- DC Gain = k
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE; use ieee.math_real.all;
entity lpf_1_e is
generic (
fp : real; -- pole freq
gain : real := 1.0); -- filter gain
port ( terminal input: electrical;
terminal output: electrical);
end entity lpf_1_e;
architecture simple of lpf_1_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
constant wp : real := math_2_pi*fp;
constant num : real_vector := (0 => wp*gain); -- 0=> is needed to give
-- index when only a single
-- element is used.
constant den : real_vector := (wp, 1.0);
quantity vin_temp : real;
begin
vin_temp == vin; -- intermediate variable (vin) req'd for now
vout == vin_temp'ltf(num, den);
end architecture simple;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity TB_CS2_S_Domain is
end TB_CS2_S_Domain;
architecture TB_CS2_S_Domain of TB_CS2_S_Domain is
-- Component declarations
-- Signal declarations
terminal comp_in : electrical;
terminal ctl_horn_out : electrical;
terminal err_limit_in : electrical;
terminal error : electrical;
terminal gear_out : electrical;
terminal integ_out : electrical;
terminal load_trq : electrical;
terminal mtr_fb : electrical;
terminal mtr_gen_trq : electrical;
terminal mtr_in : electrical;
terminal mtr_out : electrical;
terminal pos_fb : electrical;
terminal rudder : electrical;
terminal rudder_in : electrical;
terminal src_in : electrical;
terminal XSIG010043 : electrical;
terminal XSIG010044 : electrical;
terminal XSIG010046 : electrical;
terminal XSIG010050 : electrical;
begin
-- Signal assignments
-- Component instances
v_source : entity work.v_sine(ideal)
generic map(
amplitude => 4.8,
freq => 1.0
)
port map(
pos => src_in,
neg => ELECTRICAL_REF
);
sum_pos : entity work.sum2_e(simple)
port map(
in1 => src_in,
in2 => pos_fb,
output => error
);
loop_comp : entity work.lead_lag_e(simple)
generic map(
f1 => 5.0,
k => 4000.0,
f2 => 20000.0
)
port map(
input => comp_in,
output => err_limit_in
);
pos_fb_gain : entity work.gain_e(simple)
generic map(
k => -4.57
)
port map(
input => rudder_in,
output => pos_fb
);
mech_limit : entity work.limiter_2_e(simple)
generic map(
limit_high => 1.05,
limit_low => -1.05
)
port map(
input => integ_out,
output => rudder_in
);
gear_box_horn : entity work.ctl_horn_e(bhv)
port map(
theta_in => rudder_in,
pos_t_out => ctl_horn_out
);
rudder_horn : entity work.rudder_horn_e(bhv)
port map(
pos_t_in => ctl_horn_out,
theta_out => rudder
);
mtr_Kt : entity work.gain_e(simple)
generic map(
k => 3.43e-3
)
port map(
input => XSIG010044,
output => mtr_gen_trq
);
gear_box : entity work.gain_e(simple)
generic map(
k => 0.01
)
port map(
input => mtr_out,
output => gear_out
);
mtr_Ke : entity work.gain_e(simple)
generic map(
k => -3.43e-3
)
port map(
input => mtr_out,
output => mtr_fb
);
sum_mtr_in : entity work.sum2_e(simple)
port map(
in1 => mtr_in,
in2 => mtr_fb,
output => XSIG010043
);
sum_load_trq : entity work.sum2_e(simple)
port map(
in1 => mtr_gen_trq,
in2 => load_trq,
output => XSIG010046
);
integrator : entity work.integ_1_e(simple)
generic map(
k => 1.0
)
port map(
input => gear_out,
output => integ_out
);
rudder_trq : entity work.gain_e(simple)
generic map(
k => -0.2
)
port map(
input => XSIG010050,
output => load_trq
);
trq_fb_gain : entity work.gain_e(simple)
generic map(
k => 0.01
)
port map(
input => rudder_in,
output => XSIG010050
);
mtr_elec_pole : entity work.lpf_1_e(simple)
generic map(
gain => 0.4545,
fp => 172.48
)
port map(
input => XSIG010043,
output => XSIG010044
);
mtr_mech_pole : entity work.lpf_1_e(simple)
generic map(
gain => 177.67e3,
fp => 5.33
)
port map(
input => XSIG010046,
output => mtr_out
);
loop_gain : entity work.gain_e(simple)
generic map(
k => 100.0
)
port map(
input => error,
output => comp_in
);
err_limit : entity work.limiter_2_e(simple)
generic map(
limit_high => 4.8,
limit_low => -4.8
)
port map(
input => err_limit_in,
output => mtr_in
);
end TB_CS2_S_Domain;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue817/repro1.vhdl | 1 | 276 | library ieee;
use ieee.std_logic_1164.all;
entity ent is
end entity;
architecture arch of ent is
begin
process
variable valid_tmp : std_logic_vector := (others => '0');
begin
valid_tmp := (others => '0');
wait;
end process;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_20.vhd | 4 | 1886 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_20_fg_20_20.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
package constraints is
-- code from book (in text)
group port_pair is ( signal, signal );
attribute max_prop_delay : time;
-- end code from book
end package constraints;
-- code from book
library ieee; use ieee.std_logic_1164.all;
use work.constraints.port_pair, work.constraints.max_prop_delay;
entity clock_buffer is
port ( clock_in : in std_logic;
clock_out1, clock_out2, clock_out3 : out std_logic );
group clock_to_out1 : port_pair ( clock_in, clock_out1 );
group clock_to_out2 : port_pair ( clock_in, clock_out2 );
group clock_to_out3 : port_pair ( clock_in, clock_out3 );
attribute max_prop_delay of clock_to_out1 : group is 2 ns;
attribute max_prop_delay of clock_to_out2 : group is 2 ns;
attribute max_prop_delay of clock_to_out3 : group is 2 ns;
end entity clock_buffer;
-- end code from book
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/mux4.vhd | 4 | 1527 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- test code:
package mux4_types is
-- code from book:
type sel_range is range 0 to 3;
-- end of code from book
end package mux4_types;
use work.mux4_types.all;
-- end test code
library ieee; use ieee.std_logic_1164.all;
entity mux4 is
port ( sel : in sel_range;
d0, d1, d2, d3 : in std_ulogic;
z : out std_ulogic );
end entity mux4;
--------------------------------------------------
architecture demo of mux4 is
begin
out_select : process (sel, d0, d1, d2, d3) is
begin
case sel is
when 0 =>
z <= d0;
when 1 =>
z <= d1;
when 2 =>
z <= d2;
when 3 =>
z <= d3;
end case;
end process out_select;
end architecture demo;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue40/test.vhdl | 2 | 446 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity a is
port
(
foo : in std_ulogic_vector
);
end a;
architecture rtl of a is
begin
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity b is
port
(
bar : inout std_logic_vector(7 downto 0)
);
end b;
architecture rtl of b is
begin
i_a: entity work.a
port map
(
foo => std_ulogic_vector(bar)
);
end rtl;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/sr3217/tests.vhd | 2 | 394 | use std.textio.all; -- Imports the standard textio package.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- Defines a design entity, without any ports.
entity tests is
end tests;
architecture behaviour of tests is
begin
process
variable l : line;
variable a : natural := 1;
begin
report "a = " & natural'simple_name(a);
wait;
end process;
end behaviour;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1540.vhd | 4 | 1842 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1540.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p10n01i01540ent IS
END c08s09b00x00p10n01i01540ent;
ARCHITECTURE c08s09b00x00p10n01i01540arch OF c08s09b00x00p10n01i01540ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
for j in 1 to 100 loop
for i in 1 to 5 loop
k := k + 1;
end loop;
end loop;
assert NOT( k=500 )
report "***PASSED TEST: c08s09b00x00p10n01i01540"
severity NOTE;
assert ( k=500 )
report "***FAILED TEST: c08s09b00x00p10n01i01540 - The sequence of statements is executed once for each value of the discrete range"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p10n01i01540arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc286.vhd | 4 | 1950 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc286.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x00p12n01i00286ent IS
END c03s01b03x00p12n01i00286ent;
ARCHITECTURE c03s01b03x00p12n01i00286arch OF c03s01b03x00p12n01i00286ent IS
type time is range 0 to 1E8 units
fs;
ps = 10 fs;
end units;
BEGIN
TESTING: PROCESS
variable i : integer;
BEGIN
i:=time'pos(3 ps);
assert NOT(i=30)
report "***PASSED TEST: c03s01b03x00p12n01i00286"
severity NOTE;
assert (i=30)
report "***FAILED TEST: c03s01b03x00p12n01i00286 - The position number of the value corresponding to a unit name is the number of the base units represented by that unit name."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x00p12n01i00286arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug017/call10.vhdl | 2 | 439 | entity call10 is
end;
architecture behav of call10 is
procedure check2 (msg : string) is
begin
assert msg = "checking: abcedfghijklmnopqrstuvwxyz"
severity failure;
report "SUCCESS" severity note;
end check2;
procedure check1 (msg : string) is
begin
check2 ("checking: " & msg);
end check1;
begin
process
begin
check1 ("abcedfghijklmnopqrstuvwxyz");
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2469.vhd | 4 | 2018 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2469.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02469ent IS
END c07s03b02x02p03n02i02469ent;
ARCHITECTURE c07s03b02x02p03n02i02469arch OF c07s03b02x02p03n02i02469ent IS
BEGIN
TESTING: PROCESS
type B_ARRAY is array ( boolean range <> ) of real;
subtype B_CON is B_ARRAY ( FALSE to TRUE );
function F_B ( PAR : B_CON ) return B_CON is
begin
return (1.0,2.0);
end F_B;
variable V_B : B_CON ;
BEGIN
V_B := F_B( B_ARRAY'(1.0,others=>2.0) ); -- Failure_here
-- SEMANTIC ERROR: "others" used in aggregate in qualified expression
-- whose type mark denotes an unconstrained array type.
assert FALSE
report "***FAILED TEST: c07s03b02x02p03n02i02469 - Others cannot be used with an unconstrained array type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02469arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1414.vhd | 4 | 1833 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1414.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b01x00p01n01i01414ent IS
END c08s05b01x00p01n01i01414ent;
ARCHITECTURE c08s05b01x00p01n01i01414arch OF c08s05b01x00p01n01i01414ent IS
BEGIN
TESTING: PROCESS
type array_type is array (1 to 10) of integer;
variable v1 : array_type;
BEGIN
v1 (1) := integer'(12);
assert NOT(v1(1)=12)
report "***PASSED TEST: c08s05b01x00p01n01i01414"
severity NOTE;
assert (v1(1)=12)
report "***FAILED TEST: c08s05b01x00p01n01i01414 - Each element of the array variable there is a matching element on the right hand side."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b01x00p01n01i01414arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_15_ire.vhd | 4 | 1477 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_ire.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
use work.dlx_types.all;
entity ir_extender is
generic ( Tpd : delay_length );
port ( d : in dlx_word;
q : out dlx_word;
immed_size_26 : in std_logic;
immed_unsigned : in std_logic;
immed_en : in std_logic );
end entity ir_extender;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc203.vhd | 4 | 1765 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc203.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b00x00p07n01i00203ent IS
END c03s01b00x00p07n01i00203ent;
ARCHITECTURE c03s01b00x00p07n01i00203arch OF c03s01b00x00p07n01i00203ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
loop1:
for J in 1 downto 30 loop
k := k + J;
end loop LOOP1;
assert NOT( k=0 )
report "***PASSED TEST: c03s01b00x00p07n01i00203"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c03s01b00x00p07n01i00203 - It is valid to have a null range."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b00x00p07n01i00203arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/idct.d/cmp_204.vhd | 2 | 338 | library ieee;
use ieee.std_logic_1164.all;
entity cmp_204 is
port (
eq : out std_logic;
in0 : in std_logic;
in1 : in std_logic
);
end cmp_204;
architecture augh of cmp_204 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue1325/rotate_testcase.vhdl | 1 | 383 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity rotate_testcase is
Port (in_vec: in UNSIGNED(31 downto 0);
out_vecl: out UNSIGNED(31 downto 0);
out_vecr: out UNSIGNED(31 downto 0));
end entity;
architecture RTL of rotate_testcase is
begin
out_vecl <= rotate_left(in_vec,1);
out_vecr <= rotate_right(in_vec,1);
end RTL;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/generators/memory_board.vhd | 4 | 2490 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
library ieee; use ieee.std_logic_1164.all;
entity DRAM is
port ( a : in std_logic_vector(0 to 10);
d : inout std_logic_vector(0 to 3);
cs, we, ras, cas : in std_logic );
end entity DRAM;
architecture empty of DRAM is
begin
d <= (others => 'Z');
end architecture empty;
library ieee; use ieee.std_logic_1164.all;
entity memory_board is
end entity memory_board;
-- end not in book
architecture chip_level of memory_board is
component DRAM is
port ( a : in std_logic_vector(0 to 10);
d : inout std_logic_vector(0 to 3);
cs, we, ras, cas : in std_logic );
end component DRAM;
signal buffered_address : std_logic_vector(0 to 10);
signal DRAM_data : std_logic_vector(0 to 31);
signal bank_select : std_logic_vector(0 to 3);
signal buffered_we, buffered_ras, buffered_cas : std_logic;
-- . . . -- other declarations
begin
bank_array : for bank_index in 0 to 3 generate
begin
nibble_array : for nibble_index in 0 to 7 generate
constant data_lo : natural := nibble_index * 4;
constant data_hi : natural := nibble_index * 4 + 3;
begin
a_DRAM : component DRAM
port map ( a => buffered_address,
d => DRAM_data(data_lo to data_hi),
cs => bank_select(bank_index),
we => buffered_we,
ras => buffered_ras,
cas => buffered_cas );
end generate nibble_array;
end generate bank_array;
-- . . . -- other component instances, etc
-- not in book
buffered_address <= "01010101010";
DRAM_data <= X"01234567";
-- end not in book
end architecture chip_level;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc813.vhd | 4 | 1522 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc813.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ARCHITECTURE c01s02b00x00p04n02i00813arch OF c01s02b00x00p04n02i00813ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s02b00x00p04n02i00813 - Entity declaration and architecture body must reside in the same library."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s02b00x00p04n02i00813arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/memmux01/tb_memmux07.vhdl | 1 | 929 | entity tb_memmux07 is
end tb_memmux07;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_memmux07 is
signal ad : std_logic;
signal val : std_logic_vector (1 downto 0);
signal dat, res : std_logic_vector (7 downto 0);
begin
dut : entity work.memmux07
port map (
ad => ad,
val => val,
dat => dat,
res => res);
process
begin
dat <= x"de";
ad <= '0';
val <= "00";
wait for 1 ns;
assert res = x"dc" severity failure;
ad <= '1';
val <= "00";
wait for 1 ns;
assert res = x"ce" severity failure;
ad <= '0';
val <= "01";
wait for 1 ns;
assert res = x"dd" severity failure;
ad <= '0';
val <= "10";
wait for 1 ns;
assert res = x"de" severity failure;
ad <= '1';
val <= "10";
wait for 1 ns;
assert res = x"ee" severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1840.vhd | 4 | 1862 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1840.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01840ent IS
type small_int is range 0 to 7;
END c07s01b00x00p08n01i01840ent;
ARCHITECTURE c07s01b00x00p08n01i01840arch OF c07s01b00x00p08n01i01840ent IS
signal s_int : small_int := 0;
BEGIN
TESTING : PROCESS
BEGIN
assert s_int > c07s01b00x00p08n01i01840arch -- body name illegal here
report "architecture body name accepted as primary in a condition."
severity note ;
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01840 - Architecture body names are not permitted as primaries in a condition expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01840arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug010/FIFO.vhdl | 3 | 1641 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity FIFO is
generic(Depth : integer := 3);
port(
iClk : in std_logic;
iReset : in std_logic;
-- write port
iWrEn : in std_logic;
iData : in std_logic_vector(7 downto 0);
oHasSpace : out std_logic;
-- read port
iRdEn : in std_logic;
oData : out std_logic_vector(7 downto 0);
oHasData : out std_logic
);
end FIFO;
architecture behaviour of FIFO is
constant DMSB : integer := Depth - 1;
constant Size : integer := 2 ** DEPTH;
type regArrayT is array(0 to Size-1) of std_logic_vector(7 downto 0);
signal free : unsigned(Depth downto 0) := (others => '0');
signal rIdx, wIdx : unsigned(DMSB downto 0) := (others => '0');
signal regArray : regArrayT;
signal rdEn, wrEn : std_logic;
signal hasData, hasSpace : std_logic;
begin
oData <= regArray(to_integer(rIdx));
hasData <= '0' when free = Size else '1';
oHasData <= hasData;
hasSpace <= '0' when free = to_unsigned(0, Depth) else '1';
oHasSpace <= hasSpace;
rdEn <= iRdEn and hasData;
wrEn <= iWrEn and hasSpace;
main: process(iClk) begin
if iClk'event and iClk = '1' then
if iReset = '1' then
free <= to_unsigned(Size, Depth + 1);
rIdx <= (others => '0');
wIdx <= (others => '0');
elsif wrEn = '1' and rdEn = '1' then
rIdx <= rIdx + 1;
regArray(to_integer(wIdx)) <= iData;
wIdx <= wIdx + 1;
elsif rdEn = '1' then
rIdx <= rIdx + 1;
free <= free + 1;
elsif wrEn = '1' then
regArray(to_integer(wIdx)) <= iData;
wIdx <= wIdx + 1;
free <= free - 1;
end if;
end if;
end process;
end behaviour;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/ticket48/ref.vhdl | 3 | 76 | entity ent is
end entity;
architecture a of ent is
begin
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2971.vhd | 4 | 1696 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2971.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s03b01x00p02n02i02971ent IS
END c02s03b01x00p02n02i02971ent;
ARCHITECTURE c02s03b01x00p02n02i02971arch OF c02s03b01x00p02n02i02971ent IS
function "and" (a1 : real) return integer is --Failure here
begin
return 12;
end "and";
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s03b01x00p02n02i02971 - The subprogram specification of a binary operator must have two parameters."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s03b01x00p02n02i02971arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/ticket14/repro.vhdl | 3 | 489 | entity repro is
generic (
BUS_WIDTH : integer := 8;
ARRAY_WIDTH : integer := 2);
end entity repro;
architecture behavioural of repro is
type test_array_type is array (ARRAY_WIDTH-1 downto 0) of
bit_vector (BUS_WIDTH-1 downto 0);
signal s : test_array_type := (others => (others => '0'));
begin
failing_process : process
begin
assert s'left = 1;
assert s'right = 0;
wait;
end process failing_process;
end architecture behavioural;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc450.vhd | 4 | 3091 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc450.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00450ent IS
END c03s02b01x01p19n01i00450ent;
ARCHITECTURE c03s02b01x01p19n01i00450arch OF c03s02b01x01p19n01i00450ent IS
type four_value is ('Z','0','1','X'); --enumerated type
constant C77 : four_value := 'Z';
function complex_scalar(s : four_value) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return four_value is
begin
return C77;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : four_value;
signal S2 : four_value;
signal S3 : four_value := C77;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C77) and (S2 = C77))
report "***PASSED TEST: c03s02b01x01p19n01i00450"
severity NOTE;
assert ((S1 = C77) and (S2 = C77))
report "***FAILED TEST: c03s02b01x01p19n01i00450 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00450arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/clifton-labs/compliant/functional/components/integer-default-binding.vhdl | 4 | 722 | entity forty_two is
port (
int_out : out integer);
end forty_two;
architecture only of forty_two is
begin -- only
process
begin -- process
int_out <= 42;
wait;
end process;
end only;
entity test_bench is
end test_bench;
architecture only of test_bench is
component forty_two
port (
int_out : out integer);
end component;
signal int_signal : integer;
begin -- only
ft0 : component forty_two
port map (
int_out => int_signal );
test: process
begin -- process test
wait for 1 ms;
assert int_signal = 42 report "TEST FAILED" severity ERROR;
assert not(int_signal = 42) report "TEST PASSED" severity NOTE;
wait;
end process test;
end only;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc464.vhd | 4 | 3395 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc464.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00464ent IS
END c03s02b01x01p19n01i00464ent;
ARCHITECTURE c03s02b01x01p19n01i00464arch OF c03s02b01x01p19n01i00464ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
subtype boolean_vector_range is boolean_vector(hi_to_low_range);
constant C66: boolean_vector_range := (others => true);
function complex_scalar(s : boolean_vector_range) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return boolean_vector_range is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : boolean_vector_range;
signal S2 : boolean_vector_range;
signal S3 : boolean_vector_range:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00464"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00464 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00464arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2806.vhd | 4 | 1605 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2806.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity INOUT is
end INOUT;
ENTITY c13s09b00x00p99n01i02806ent IS
END c13s09b00x00p99n01i02806ent;
ARCHITECTURE c13s09b00x00p99n01i02806arch OF c13s09b00x00p99n01i02806ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02806 - Reserved word INOUT can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02806arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug090/hang8.vhdl | 1 | 1182 | library ieee;
use ieee.s_1164.all;
entity clkgen is
generic (period : time := 10 ns);
port (signal clk : out std_logic := '0');
end clkgen;
architecture behav of clkgen is
begin
process
begin
clk <= not clk;
wait for period / 2;
end process;
end behav;
entity hello is
end hello;
architecture behav of hello is
signal clk : std_logic;
signal rst_n : std_logic;
signal din, dout, dout2 : std_logic_vector (7 downto 0);
component clkgen is
generic (period : time := 10 ns);
port (signal clk : out std_logic);
end component;
begin
cclk : clkgen
generic map (period => 20 ns)
port map (clk => clk);
rst_n <= '0' after 0 ns, '1' after 4 ns;
p: process (clk)
begin
if rising_edge (clk) then
if rst_n then
q <= (others => '0');
else q <= d;
end if;
end if;
end process p;
process
variable v : natural := 0;
begin
wait until rst_n = '1';
wait until clk = '0';
report 2start of tb" severity note;
for i in 0 to 10 loop
group i is
when 0 | 3 =>
for i in din'range loop
din(i) <= '0';
end loop;
when 1 => din <= b"00110011";
when 2 =>ehav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc296.vhd | 4 | 1785 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc296.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x01p01n04i00296ent IS
END c03s01b03x01p01n04i00296ent;
ARCHITECTURE c03s01b03x01p01n04i00296arch OF c03s01b03x01p01n04i00296ent IS
type some_time is range 1 to 100
units
fs; -- base unit
x = 10 fs;
y = 10 x;
end units;
constant z : some_time := 10 y;
signal S : integer;
BEGIN
TESTING: PROCESS
BEGIN
S <= 10 after z;
wait for 20 ns;
assert FALSE
report "***FAILED TEST: c03s01b03x01p01n04i00296 - The delay specification is not of type TIME."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x01p01n04i00296arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug057/tb2.vhdl | 4 | 329 | entity tb2 is
end tb2;
architecture behav of tb2 is
package pkg1 is
generic (c : natural);
generic map (c => 5);
function f return natural;
end pkg1;
package body pkg1 is
function f return natural is
begin
return c;
end f;
end pkg1;
begin
assert pkg1.f = 5 severity failure;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug029/repro1.vhdl | 2 | 1006 | package foo is
function some_foo return integer;
function some_fum return integer;
function some_foe (x, y, w: integer) return integer;
function some_fee (x, y, w: integer) return integer;
end package;
package body foo is
function some_foo return integer is
begin
return -1;
return 0;
end function;
function some_fum return integer is
variable a: integer := -1;
variable b: integer := 0;
begin
return a;
return b;
end function;
function some_foe (x, y, w: integer) return integer is
variable a: integer := -1;
variable b: integer := 0;
begin
return a;
return b;
end function;
function some_fee (x, y, w: integer) return integer is
variable a: integer := -1;
variable b: integer := 0;
begin
a := x + w;
b := y + w;
return a;
return b;
end function;
end package body;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/range01/tb_revrng01.vhdl | 1 | 352 | entity tb_revrng01 is
end tb_revrng01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_revrng01 is
signal a, z : std_logic_vector (7 downto 0);
begin
dut: entity work.revrng01
port map (a, z);
process
begin
a <= x"a1";
wait for 1 ns;
assert z = x"85" severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug065/repro.vhdl | 2 | 342 | package gen is
generic (type t);
end gen;
entity e is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture a of e is
subtype T_DATA is std_logic_vector(31 downto 0);
type T_DATA_VECTOR is array(natural range <>) of T_DATA;
package pkg is new work.gen generic map (t => t_data_vector);
begin
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1165.vhd | 4 | 1861 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1165.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s06b00x00p02n01i01165ent IS
END c06s06b00x00p02n01i01165ent;
ARCHITECTURE c06s06b00x00p02n01i01165arch OF c06s06b00x00p02n01i01165ent IS
BEGIN
TESTING: PROCESS
type A1 is array (1 to 2) of BOOLEAN;
type A2 is array (1 to 2) of A1;
variable V : A2;
variable k : integer := 0;
BEGIN
if V(1)'LOW = 1 then
k := 5;
end if;
assert NOT( k=5 )
report "***PASSED TEST: c06s06b00x00p02n01i01165"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c06s06b00x00p02n01i01165 - The prefix of an attribute name may be an indexed name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s06b00x00p02n01i01165arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/asgn01/asgn02.vhdl | 1 | 305 | library ieee;
use ieee.std_logic_1164.all;
entity asgn02 is
port (s0 : std_logic;
r : out std_logic_vector (2 downto 0));
end asgn02;
architecture behav of asgn02 is
begin
process (s0) is
begin
r <= "000";
if s0 = '1' then
r (1) <= '1';
end if;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/psl02/assert1.vhdl | 1 | 545 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity assert1 is
port (clk, rst: std_logic;
cnt : out unsigned(3 downto 0));
end assert1;
architecture behav of assert1 is
signal val : unsigned (3 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
val <= (others => '0');
else
val <= val + 1;
end if;
end if;
end process;
cnt <= val;
end behav;
vunit verif1 (assert1)
{
default clock is rising_edge(clk);
assert always cnt /= 5 abort rst;
}
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_ch_05_17.vhd | 4 | 1914 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_05_ch_05_17.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity ch_05_17 is
end entity ch_05_17;
----------------------------------------------------------------
architecture test of ch_05_17 is
signal s, r, q, q_n : bit := '0';
begin
q <= '1' when s = '1' else
'0' when r = '1';
q_n <= '0' when s = '1' else
'1' when r = '1';
-- code from book:
check : process is
begin
assert not (s = '1' and r = '1')
report "Incorrect use of S_R_flip_flop: s and r both '1'";
wait on s, r;
end process check;
-- end of code from book
stimulus : process is
begin
wait for 10 ns;
s <= '1'; wait for 10 ns;
s <= '0'; wait for 10 ns;
r <= '1'; wait for 10 ns;
r <= '0'; wait for 10 ns;
s <= '1'; wait for 10 ns;
r <= '1'; wait for 10 ns;
s <= '0'; wait for 10 ns;
r <= '0'; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_07_ch_07_05.vhd | 4 | 2243 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_ch_07_05.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ch_07_05 is
end entity ch_07_05;
library bv_utilities;
use bv_utilities.bv_arithmetic.all;
architecture test of ch_07_05 is
begin
process_07_5_a : process is
-- code from book:
procedure increment ( a : inout integer; n : in integer := 1 ) is -- . . .
-- not in book
begin
a := a + n;
end procedure increment;
-- end not in book;
procedure increment ( a : inout bit_vector; n : in bit_vector := B"1" ) is -- . . .
-- not in book
begin
a := a + n;
end procedure increment;
-- end not in book;
procedure increment ( a : inout bit_vector; n : in integer := 1 ) is -- . . .
-- not in book
begin
a := a + integer_to_bv(n, a'length);
end procedure increment;
-- end not in book;
variable count_int : integer := 2;
variable count_bv : bit_vector (15 downto 0) := X"0002";
-- end of code from book
begin
-- code from book:
increment ( count_int, 2 );
increment ( count_int );
increment ( count_bv, X"0002");
increment ( count_bv, 1 );
-- increment ( count_bv );
-- end of code from book
wait;
end process process_07_5_a;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2609.vhd | 4 | 1589 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2609.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02609ent IS
END c13s03b01x00p02n01i02609ent;
ARCHITECTURE c13s03b01x00p02n01i02609arch OF c13s03b01x00p02n01i02609ent IS
BEGIN
TESTING: PROCESS
variable 01k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02609 - Identifier can not begin with a digit."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02609arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug040/p_jinfo_comps_info_dc_tbl_no.vhd | 2 | 1425 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_comps_info_dc_tbl_no is
port (
wa0_data : in std_logic;
wa0_addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(1 downto 0);
ra0_data : out std_logic;
wa0_en : in std_logic
);
end p_jinfo_comps_info_dc_tbl_no;
architecture augh of p_jinfo_comps_info_dc_tbl_no is
-- Embedded RAM
type ram_type is array (0 to 2) of std_logic;
signal ram : ram_type := (others => '0');
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 3 else '-';
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc403.vhd | 4 | 2099 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc403.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p18n01i00403ent IS
END c03s02b01x01p18n01i00403ent;
ARCHITECTURE c03s02b01x01p18n01i00403arch OF c03s02b01x01p18n01i00403ent IS
type MEM is array (positive range <>) of BIT;
type ME1 is array (natural range <>) of Integer;
subtype ME2 is ME1(0 to 3);
subtype M1 is MEM (1 to 5) ;
function WR_OR(Input : ME1) return M1 is
begin
for I in Input'Range loop
if Input(I) = 20 then
return "11111" ;
end if;
end loop;
end WR_OR;
procedure F2 (X1 : in MEM) is
begin
assert NOT(X1="11111")
report "***PASSED TEST: c03s02b01x01p18n01i00403"
severity NOTE;
assert (X1="11111")
report "***FAILED TEST: c03s02b01x01p18n01i00403 - "
severity ERROR;
end F2;
BEGIN
TESTING: PROCESS
variable V1 :ME2 := (10, 20, 30, 40);
BEGIN
F2(WR_OR(V1)) ; -- No_failure_here
wait;
END PROCESS TESTING;
END c03s02b01x01p18n01i00403arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1624.vhd | 4 | 1738 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1624.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c08s12b00x00p03n01i01624pkg is
return true; -- illegal in package spec
end c08s12b00x00p03n01i01624pkg;
ENTITY c08s12b00x00p03n01i01624ent IS
END c08s12b00x00p03n01i01624ent;
ARCHITECTURE c08s12b00x00p03n01i01624arch OF c08s12b00x00p03n01i01624ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c08s12b00x00p03n01i01624 - Return statement only allowed within the body of a function or procedure."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p03n01i01624arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc252.vhd | 4 | 1736 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc252.vhd,v 1.2 2001-10-26 16:30:19 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p04n01i00252ent IS
END c03s01b02x00p04n01i00252ent;
ARCHITECTURE c03s01b02x00p04n01i00252arch OF c03s01b02x00p04n01i00252ent IS
-- Failure_here: 1.0E-8 is an error, because it is not an integer
type time is range 0 to 1.0E-8 units
fs;
end units;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s01b02x00p04n01i00252 - Bound not of type integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p04n01i00252arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_03_ch_03_03.vhd | 4 | 2599 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_ch_03_03.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ch_03_03 is
end entity ch_03_03;
architecture test of ch_03_03 is
begin
process_3_1_c : process is
type mode_type is (immediate, other_mode);
type opcode_type is (load, add, subtract, other_opcode);
variable mode : mode_type;
variable opcode : opcode_type;
constant immed_operand : integer := 1;
constant memory_operand : integer := 2;
constant address_operand : integer := 3;
variable operand : integer;
procedure procedure_3_1_c is
begin
-- code from book:
if mode = immediate then
operand := immed_operand;
elsif opcode = load or opcode = add or opcode = subtract then
operand := memory_operand;
else
operand := address_operand;
end if;
-- end of code from book
end procedure_3_1_c;
begin
mode := immediate;
procedure_3_1_c;
mode := other_mode;
opcode := load;
procedure_3_1_c;
opcode := add;
procedure_3_1_c;
opcode := subtract;
procedure_3_1_c;
opcode := other_opcode;
procedure_3_1_c;
wait;
end process process_3_1_c;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc701.vhd | 4 | 3130 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc701.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:07 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:41 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:45 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00701ent IS
END c03s04b01x00p23n01i00701ent;
ARCHITECTURE c03s04b01x00p23n01i00701arch OF c03s04b01x00p23n01i00701ent IS
BEGIN
TESTING: PROCESS
-- Declare the type and the file.
type FT is file of NATURAL;
-- Declare the actual file to read.
file FILEV : FT open read_mode is "iofile.08";
-- Declare a variable into which we will read.
constant CON : NATURAL := 1;
variable VAR : NATURAL;
variable k : integer := 0;
BEGIN
-- Read in the file.
for I in 1 to 100 loop
if (ENDFILE( FILEV ) /= FALSE) then
k := 1;
end if;
assert( (ENDFILE( FILEV ) = FALSE) )
report "Hit the end of file too soon.";
READ( FILEV,VAR );
if (VAR /= CON) then
k := 1;
end if;
end loop;
-- Verify that we are at the end.
if (ENDFILE( FILEV ) /= TRUE) then
k := 1;
end if;
assert( ENDFILE( FILEV ) = TRUE )
report "Have not reached end of file yet."
severity ERROR;
assert NOT( k = 0 )
report "***PASSED TEST: c03s04b01x00p23n01i00701"
severity NOTE;
assert( k = 0 )
report "***FAILED TEST: c03s04b01x00p23n01i00701 - The variables don't equal the constants."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00701arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/oper01/tb_cmp01.vhdl | 1 | 1416 | entity tb_cmp01 is
end tb_cmp01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_cmp01 is
signal l : std_logic_vector(3 downto 0);
signal r : std_logic_vector(3 downto 0);
signal eq : std_logic;
signal ne : std_logic;
signal lt : std_logic;
signal le : std_logic;
signal ge : std_logic;
signal gt : std_logic;
begin
cmp01_1: entity work.cmp01
port map (
l => l,
r => r,
eq => eq,
ne => ne,
lt => lt,
le => le,
ge => ge,
gt => gt);
process
begin
l <= x"5";
r <= x"7";
wait for 1 ns;
assert eq = '0' severity failure;
assert ne = '1' severity failure;
assert lt = '1' severity failure;
assert le = '1' severity failure;
assert ge = '0' severity failure;
assert gt = '0' severity failure;
l <= x"a";
r <= x"7";
wait for 1 ns;
assert eq = '0' severity failure;
assert ne = '1' severity failure;
assert lt = '0' severity failure;
assert le = '0' severity failure;
assert ge = '1' severity failure;
assert gt = '1' severity failure;
l <= x"9";
r <= x"9";
wait for 1 ns;
assert eq = '1' severity failure;
assert ne = '0' severity failure;
assert lt = '0' severity failure;
assert le = '1' severity failure;
assert ge = '1' severity failure;
assert gt = '0' severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/bv_arithmetic.vhd | 4 | 4517 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: bv_arithmetic.vhd,v 1.2 2001-10-25 01:24:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
--------------------------------------------------------------------------
--
-- Bit-vector arithmetic package interface.
--
-- Does arithmetic and logical operations on bit vectors, treating them
-- as either unsigned or signed (two's complement) integers. Leftmost bit
-- is most-significant or sign bit, rightmost bit is least-significant
-- bit. Dyadic operations need the two arguments to be of the same
-- length; however, their index ranges and directions may differ. Results
-- must be of the same length as the operands.
--
--------------------------------------------------------------------------
package bv_arithmetic is
function bv_to_natural ( bv : in bit_vector ) return natural;
function natural_to_bv ( nat : in natural;
length : in natural ) return bit_vector;
function bv_to_integer ( bv : in bit_vector ) return integer;
function integer_to_bv ( int : in integer;
length : in natural ) return bit_vector;
procedure bv_add ( bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean );
function "+" ( bv1, bv2 : in bit_vector ) return bit_vector;
procedure bv_sub ( bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean );
function "-" ( bv1, bv2 : in bit_vector ) return bit_vector;
procedure bv_addu ( bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean );
function bv_addu ( bv1, bv2 : in bit_vector ) return bit_vector;
procedure bv_subu ( bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean );
function bv_subu ( bv1, bv2 : in bit_vector ) return bit_vector;
procedure bv_neg ( bv : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean );
function "-" ( bv : in bit_vector ) return bit_vector;
procedure bv_mult ( bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean );
function "*" ( bv1, bv2 : in bit_vector ) return bit_vector;
procedure bv_multu ( bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
overflow : out boolean );
function bv_multu ( bv1, bv2 : in bit_vector ) return bit_vector;
procedure bv_div ( bv1, bv2 : in bit_vector;
bv_result : out bit_vector;
div_by_zero : out boolean;
overflow : out boolean );
function "/" ( bv1, bv2 : in bit_vector ) return bit_vector;
procedure bv_divu ( bv1, bv2 : in bit_vector;
bv_quotient : out bit_vector;
bv_remainder : out bit_vector;
div_by_zero : out boolean );
procedure bv_divu ( bv1, bv2 : in bit_vector;
bv_quotient : out bit_vector;
div_by_zero : out boolean );
function bv_divu ( bv1, bv2 : in bit_vector ) return bit_vector;
function bv_lt ( bv1, bv2 : in bit_vector ) return boolean;
function bv_le ( bv1, bv2 : in bit_vector ) return boolean;
function bv_gt ( bv1, bv2 : in bit_vector ) return boolean;
function bv_ge ( bv1, bv2 : in bit_vector ) return boolean;
function bv_sext ( bv : in bit_vector;
length : in natural ) return bit_vector;
function bv_zext ( bv : in bit_vector;
length : in natural ) return bit_vector;
end package bv_arithmetic;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1524.vhd | 4 | 1849 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1524.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p08n01i01524ent IS
END c08s09b00x00p08n01i01524ent;
ARCHITECTURE c08s09b00x00p08n01i01524arch OF c08s09b00x00p08n01i01524ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
while k > 3 loop
k := k + 1;
end loop;
assert NOT( k=0 )
report "***PASSED TEST: c08s09b00x00p08n01i01524"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s09b00x00p08n01i01524 - For a loop statement with a while iteration scheme, if the condition is evaluated to be FALSE, the execution of the loop statement is complete"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p08n01i01524arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/sequential-statements/tb_max3.vhd | 4 | 1361 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_max3 is
end entity tb_max3;
----------------------------------------------------------------
architecture test_check_error of tb_max3 is
signal a, b, c, z : integer := 0;
begin
dut : entity work.max3(check_error)
port map ( a => a, b => b, c => c, z => z );
stumulus : process is
begin
wait for 10 ns;
a <= 7; wait for 10 ns;
b <= 10; wait for 10 ns;
c <= 15; wait for 10 ns;
a <= 12; wait for 10 ns;
a <= 20; wait for 10 ns;
wait;
end process stumulus;
end architecture test_check_error;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue542/write.vhd | 1 | 450 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity write is
port(
clk : in std_logic;
reset : in std_logic;
write : in std_logic;
ack : out std_logic
);
end write;
architecture a of write is
begin
process (clk, reset) is
begin
if reset = '1' then
ack <= '0';
elsif rising_edge(clk) then
if write = '1' then
ack <= '1';
else
ack <= '0';
end if;
end if;
end process;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2330.vhd | 4 | 1752 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2330.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p02n02i02330ent IS
END c07s02b07x00p02n02i02330ent;
ARCHITECTURE c07s02b07x00p02n02i02330arch OF c07s02b07x00p02n02i02330ent IS
BEGIN
TESTING: PROCESS
type NEW_INT is range INTEGER'LOW to INTEGER'HIGH;
variable k : NEW_INT := 2 ** 5;
BEGIN
assert NOT(k=32)
report "***PASSED TEST: c07s02b07x00p02n02i02330"
severity NOTE;
assert (k=32)
report "***FAILED TEST: c07s02b07x00p02n02i02330 - Exponent can only be of type Integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p02n02i02330arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1155.vhd | 4 | 1890 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1155.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s06b00x00p02n01i01155ent IS
END c06s06b00x00p02n01i01155ent;
ARCHITECTURE c06s06b00x00p02n01i01155arch OF c06s06b00x00p02n01i01155ent IS
BEGIN
TESTING: PROCESS
type ABASE is array (INTEGER range <>) of BOOLEAN;
subtype A1 is ABASE(1 to 5);
variable V : A1;
variable k : integer := 0;
BEGIN
if V(2 to 4)'LOW = 2 then
k := 5;
end if;
assert NOT( k=5 )
report "***PASSED TEST: c06s06b00x00p02n01i01155"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c06s06b00x00p02n01i01155 - The prefix of an attribute name may be a slice name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s06b00x00p02n01i01155arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc719.vhd | 4 | 1598 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc719.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b00x00p04n01i00719ent IS
BEGIN
END; -- No_Failure_Here
ENTITY c01s01b00x00p04n01i00719ent IS
END c01s01b00x00p04n01i00719ent;
ARCHITECTURE c01s01b00x00p04n01i00719arch OF c01s01b00x00p04n01i00719ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s01b00x00p04n01i00719"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s01b00x00p04n01i00719arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue238/test.vhdl | 2 | 262 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY test IS
TYPE foo_t IS RECORD
bar : unsigned;
END RECORD foo_t;
END ENTITY test;
ARCHITECTURE bar OF test IS
SIGNAL baz : foo_t(bar(1 DOWNTO 0));
BEGIN
END ARCHITECTURE bar;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/oper01/tb_snum05.vhdl | 1 | 297 | entity tb_snum05 is
end tb_snum05;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_snum05 is
signal r : boolean;
begin
cmp05_1: entity work.snum05
port map (r);
process
begin
wait for 1 ns;
assert r severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/var01/tb_var04.vhdl | 1 | 746 | entity tb_var04 is
end tb_var04;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_var04 is
signal clk : std_logic;
signal mask : std_logic_vector (1 downto 0);
signal val : std_logic_vector (15 downto 0);
signal res : std_logic_vector (15 downto 0);
begin
dut: entity work.var04
port map (
mask => mask,
val => val,
res => res);
process
begin
mask <= "11";
val <= x"aa_bb";
wait for 1 ns;
assert res = x"aa_bb" severity failure;
mask <= "00";
val <= x"12_34";
wait for 1 ns;
assert res = x"00_00" severity failure;
mask <= "10";
val <= x"12_34";
wait for 1 ns;
assert res = x"12_00" severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_19_tkfifo.vhd | 4 | 1965 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_tkfifo.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library qsim;
package token_fifo_adt is
alias element_type is qsim.qsim_types.token_type;
type fifo_record;
type fifo_type is access fifo_record;
function new_fifo return fifo_type;
procedure test_empty ( variable fifo : in fifo_type;
variable is_empty : out boolean );
procedure insert ( fifo : inout fifo_type;
element : in element_type );
procedure remove ( fifo : inout fifo_type;
element : out element_type );
-- private types
type fifo_entry_record;
type fifo_entry is access fifo_entry_record;
type fifo_entry_record is record
next_entry : fifo_entry;
element : element_type;
end record;
type fifo_record is record
head_entry, tail_entry : fifo_entry;
end record;
end package token_fifo_adt;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1960.vhd | 4 | 1771 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1960.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p02n02i01960ent IS
END c07s02b01x00p02n02i01960ent;
ARCHITECTURE c07s02b01x00p02n02i01960arch OF c07s02b01x00p02n02i01960ent IS
BEGIN
TESTING: PROCESS
variable a : boolean := TRUE;
variable b : boolean := TRUE;
variable c : boolean;
BEGIN
c := a xor b;
assert NOT(c=FALSE)
report "***PASSED TEST: c07s02b01x00p02n02i01960"
severity NOTE;
assert ( c=FALSE )
report "***FAILED TEST: c07s02b01x00p02n02i01960 - Logical operation of 'XOR'."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p02n02i01960arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2413.vhd | 4 | 1692 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2413.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p09n01i02413ent IS
END c07s03b02x00p09n01i02413ent;
ARCHITECTURE c07s03b02x00p09n01i02413arch OF c07s03b02x00p09n01i02413ent IS
signal err : bit_vector(0 to 1) := (0 => '1', 1 => '0', 1 => '1');
BEGIN
TESTING: PROCESS
BEGIN
wait for 2 ns;
assert FALSE
report "***FAILED TEST: c07s03b02x00p09n01i02413 - Each element of aggregate must be represented once and only once in the aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p09n01i02413arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1560.vhd | 4 | 1876 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1560.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p03n01i01560ent IS
END c08s10b00x00p03n01i01560ent;
ARCHITECTURE c08s10b00x00p03n01i01560arch OF c08s10b00x00p03n01i01560ent IS
BEGIN
TESTING: PROCESS
variable s : integer := 0;
BEGIN
K : for j in 1 to 10 loop
L : for i in 1 to 10 loop
next K when ( (j = 3) and (i = 1) );
s := s + 1;
end loop L;
end loop K;
assert NOT(s = 90)
report "***PASSED TEST: c08s10b00x00p03n01i01560"
severity NOTE;
assert (s = 90)
report "***FAILED TEST: c08s10b00x00p03n01i01560 - A next statement with a loop label inside a labeled loop"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p03n01i01560arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug040/p_jinfo_ac_dhuff_tbl_maxcode.vhd | 2 | 1460 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_ac_dhuff_tbl_maxcode is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end p_jinfo_ac_dhuff_tbl_maxcode;
architecture augh of p_jinfo_ac_dhuff_tbl_maxcode is
-- Embedded RAM
type ram_type is array (0 to 127) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/analog-modeling/bit_to_analog.vhd | 4 | 1359 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity bit_to_analog is
port ( d : in bit;
terminal a : electrical );
end entity bit_to_analog;
----------------------------------------------------------------
architecture ideal of bit_to_analog is
constant v_low : real := 0.0;
constant v_high : real := 5.0;
signal v_in : real := 0.0;
quantity v_out across i_out through a to electrical_ref;
begin
v_in <= v_high when d = '1' else v_low;
v_out == v_in'ramp(1.0e-9);
end architecture ideal;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/psl02/verif1.vhdl | 1 | 100 | vunit verif1 (assert2)
{
default clock is rising_edge(clk);
assert always cnt /= 5 abort rst;
}
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue301/packages/pkg_trellis.vhd | 7 | 6801 | --!
--! Copyright (C) 2011 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Trellis parameter calculations (e.g., transitions, init values).
--! @author Markus Fehrenz
--! @date 2011/07/27
--!
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library dec_viterbi;
use dec_viterbi.pkg_param.all;
use dec_viterbi.pkg_param_derived.all;
use dec_viterbi.pkg_types.all;
package pkg_trellis is
type t_prev_base is array (1 downto 0) of std_logic_vector(BW_TRELLIS_STATES - 1 downto 0);
type t_previous_states is array (NUMBER_TRELLIS_STATES - 1 downto 0) of t_prev_base;
type t_trans_base is array (1 downto 0) of std_logic_vector(NUMBER_PARITY_BITS - 1 downto 0);
type t_transitions is array (NUMBER_TRELLIS_STATES - 1 downto 0) of t_trans_base;
type t_trans_base_signed is array (1 downto 0) of std_logic_vector(NUMBER_PARITY_BITS downto 0);
type t_transitions_signed is array (NUMBER_TRELLIS_STATES - 1 downto 0) of t_trans_base_signed;
--
-- This function calculates the previous states of each state.
-- The values are used to connect the ACS units.
--
function calc_previous_states return t_previous_states;
--
-- This function calculates corresponding transitions to a trellis sate.
-- The values are used to connect branch units to ACS units.
--
function calc_transitions return t_transitions;
--
-- This function calculates the initialization values for trellis metrics.
-- The values are used as a constant and written to the ACS unit, every time a new block arrives.
--
function calc_initialize return t_node_s;
constant PREVIOUS_STATES : t_previous_states;
constant TRANSITIONS : t_transitions;
constant INITIALIZE_TRELLIS : t_node_s;
end package pkg_trellis;
package body pkg_trellis is
function calc_previous_states return t_previous_states is
variable v_prev_states : t_previous_states := (others=>(others=>(others => '0')));
variable v_state0, v_state1 : std_logic_vector(BW_TRELLIS_STATES - 1 downto 0);
begin
for i in NUMBER_TRELLIS_STATES - 1 downto 0 loop
v_state0 := std_logic_vector(to_unsigned(i,BW_TRELLIS_STATES));
v_state1 := v_state0(BW_TRELLIS_STATES - 2 downto 0) & '0';
v_prev_states(i)(0) := v_state1;
v_state1 := v_state0(BW_TRELLIS_STATES - 2 downto 0) & '1';
v_prev_states(i)(1) := v_state1;
end loop;
return v_prev_states;
end function calc_previous_states;
function calc_transitions return t_transitions is
variable v_transitions : t_transitions_signed := (others => (others => (others => '0')));
variable v_transitions_out : t_transitions := (others => (others => (others => '0')));
variable v_one_transition : std_logic_vector(NUMBER_PARITY_BITS - 1 downto 0);
variable v_next_state : unsigned(ENCODER_MEMORY_DEPTH - 1 downto 0) := (others => '0');
variable v_state, v_states : unsigned(ENCODER_MEMORY_DEPTH downto 0);
variable v_bit : std_logic := '0';
begin
--
-- It is possible to reduce code size at this stage, if feedback is handled differently,
-- but the complexity will increase.
--
for i in NUMBER_TRELLIS_STATES - 1 downto 0 loop
--
-- for input : 0
-- determine correct input with feedback
--
v_next_state := to_unsigned(i,ENCODER_MEMORY_DEPTH) and to_unsigned(FEEDBACK_POLYNOMIAL, ENCODER_MEMORY_DEPTH);
for k in ENCODER_MEMORY_DEPTH - 1 downto 0 loop
v_bit := v_bit xor v_next_state(k);
end loop;
v_state(ENCODER_MEMORY_DEPTH) := v_bit;
v_state(ENCODER_MEMORY_DEPTH - 1 downto 0) := to_unsigned(i,ENCODER_MEMORY_DEPTH);
v_next_state := v_state(ENCODER_MEMORY_DEPTH downto 1);
v_bit := '0';
-- determine paritybits
for j in NUMBER_PARITY_BITS - 1 downto 0 loop
v_states := v_state and to_unsigned(PARITY_POLYNOMIALS(j), ENCODER_MEMORY_DEPTH + 1);
for k in ENCODER_MEMORY_DEPTH downto 0 loop
v_bit := v_bit xor v_states(k);
end loop;
v_one_transition(j) := v_bit;
v_bit := '0';
end loop;
-- decide where to save the parity result
if v_transitions(to_integer(v_next_state))(1)(NUMBER_PARITY_BITS) = '0' then
v_transitions(to_integer(v_next_state))(1)(NUMBER_PARITY_BITS) := '1';
v_transitions(to_integer(v_next_state))(1)(NUMBER_PARITY_BITS - 1 downto 0) := v_one_transition;
else
v_transitions(to_integer(v_next_state))(0)(NUMBER_PARITY_BITS - 1 downto 0) := v_one_transition;
end if;
--
-- for input: 1
-- determine correct input with feedback
--
v_next_state := to_unsigned(i,ENCODER_MEMORY_DEPTH) and to_unsigned(FEEDBACK_POLYNOMIAL, ENCODER_MEMORY_DEPTH);
for k in ENCODER_MEMORY_DEPTH - 1 downto 0 loop
v_bit := v_bit xor v_next_state(k);
end loop;
v_state(ENCODER_MEMORY_DEPTH) := '1' xor v_bit;
v_state(ENCODER_MEMORY_DEPTH - 1 downto 0) := to_unsigned(i,ENCODER_MEMORY_DEPTH);
v_next_state := v_state(ENCODER_MEMORY_DEPTH downto 1);
v_bit := '0';
-- determine paritybits
for j in NUMBER_PARITY_BITS - 1 downto 0 loop
v_states := v_state and to_unsigned(PARITY_POLYNOMIALS(j), ENCODER_MEMORY_DEPTH + 1);
for k in ENCODER_MEMORY_DEPTH downto 0 loop
v_bit := v_bit xor v_states(k);
end loop;
v_one_transition(j) := v_bit;
v_bit := '0';
end loop;
-- decide where to save parity result
if v_transitions(to_integer(v_next_state))(1)(NUMBER_PARITY_BITS) = '0' then
v_transitions(to_integer(v_next_state))(1)(NUMBER_PARITY_BITS) := '1';
v_transitions(to_integer(v_next_state))(1)(NUMBER_PARITY_BITS - 1 downto 0) := v_one_transition;
else
v_transitions(to_integer(v_next_state))(0)(NUMBER_PARITY_BITS - 1 downto 0) := v_one_transition;
end if;
end loop;
-- truncate, the bit, used to decide where to save parity result
for i in NUMBER_TRELLIS_STATES - 1 downto 0 loop
v_transitions_out(i)(1) := v_transitions(i)(1)(NUMBER_PARITY_BITS - 1 downto 0);
v_transitions_out(i)(0) := v_transitions(i)(0)(NUMBER_PARITY_BITS - 1 downto 0);
end loop;
return v_transitions_out;
end function calc_transitions;
function calc_initialize return t_node_s is
variable v_initialize : t_node_s;
begin
v_initialize(0) := to_signed(0, BW_MAX_PROBABILITY);
for i in NUMBER_TRELLIS_STATES - 1 downto 1 loop
v_initialize(i) := to_signed(- 2 ** (BW_MAX_PROBABILITY - 2), BW_MAX_PROBABILITY);
end loop;
return v_initialize;
end function calc_initialize;
constant PREVIOUS_STATES : t_previous_states := calc_previous_states;
constant TRANSITIONS : t_transitions := calc_transitions;
constant INITIALIZE_TRELLIS : t_node_s := calc_initialize;
end package body pkg_trellis;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2605.vhd | 4 | 1587 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2605.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02605ent IS
END c13s03b01x00p02n01i02605ent;
ARCHITECTURE c13s03b01x00p02n01i02605arch OF c13s03b01x00p02n01i02605ent IS
BEGIN
TESTING: PROCESS
variable k< : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02605 - Identifier can not end with '<'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02605arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2842.vhd | 4 | 1602 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2842.vhd,v 1.2 2001-10-26 16:30:23 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity TYPE is
end TYPE;
ENTITY c13s09b00x00p99n01i02842ent IS
END c13s09b00x00p99n01i02842ent;
ARCHITECTURE c13s09b00x00p99n01i02842arch OF c13s09b00x00p99n01i02842ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02842 - Reserved word TYPE can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02842arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue613/t87.vhdl | 2 | 323 | entity t87 is
end;
architecture behav of t87 is
constant t1 : time := 1 ns;
constant t2 : natural := time'pos (t1);
begin
assert t1 = 1000 ps;
process
variable v : natural;
begin
-- Time resolution must be ps
v := time'pos(ps);
assert v = 1 severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/idct.d/add_276.vhd | 2 | 800 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_276 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end add_276;
architecture augh of add_276 is
signal carry_inA : std_logic_vector(28 downto 0);
signal carry_inB : std_logic_vector(28 downto 0);
signal carry_res : std_logic_vector(28 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(27 downto 1);
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/automotive_valve.vhd | 4 | 1087 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
use work.automotive_valve_defs.all;
entity automotive_valve is
port ( terminal p1, p2 : valve_fluidic;
terminal control : valve_translational );
end entity automotive_valve;
-- not in book
architecture test of automotive_valve is
begin
end architecture test;
-- end not in book
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue877/tb2.vhdl | 1 | 256 | entity tb is
end tb;
architecture behav of tb is
constant msg : string := "hello world";
procedure chk (b : natural)
is
subtype my_rng is natural range 1 to b;
begin
assert msg (chk.my_rng) = "hello";
end chk;
begin
chk(5);
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc720.vhd | 3 | 1568 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc720.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b00x00p04n01i00720ent IS
END c01s01b00x00p04n01i00720ent;
ARCHITECTURE c01s01b00x00p04n01i00720arch OF c01s01b00x00p04n01i00720ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b00x00p04n01i00720 - Entity_simple_name differs from identifier."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b00x00p04n01i00720arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue547/repro.vhdl | 1 | 90 | use work.ghdl_bug;
entity repro is
end;
architecture behav of repro is
begin
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2209.vhd | 4 | 1835 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2209.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02209ent IS
END c07s02b06x00p01n01i02209ent;
ARCHITECTURE c07s02b06x00p01n01i02209arch OF c07s02b06x00p01n01i02209ent IS
BEGIN
TESTING: PROCESS
-- All different non-numeric type declarations.
-- enumerated types.
type SWITCH_LEVEL is ('0', '1', 'X');
-- Local declarations.
variable SWITCHV : SWITCH_LEVEL := '0';
variable k : integer;
BEGIN
k := SWITCHV mod '1';
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02209 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02209arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug03/wor_std.vhdl | 3 | 3481 | library ieee;
use ieee.std_logic_1164.all;
package wor_std is
subtype rddata_o_range is integer range 3 downto 0;
type rddata_o_array is array (natural range <>) of std_logic_vector(rddata_o_range);
function rddata_o_resolv (s: rddata_o_array) return std_logic_vector;
function wor_trior (s: std_logic_vector) return std_logic;
function slv_image(inp: std_logic_vector) return string;
end package;
package body wor_std is
type wor_table is array (X01Z, X01Z) of std_ulogic;
constant resolution_table : wor_table := (
-- --------------------------------
-- | X 0 1 Z | |
-- --------------------------------
('X', 'X', '1', 'X'), -- | X |
('X', '0', '1', '0'), -- | 0 |
('1', '1', '1', '1'), -- | 1 |
('X', '0', '1', 'Z') -- | Z |
);
function wor_trior ( s: std_logic_vector ) return std_logic is
variable result: std_logic := 'Z';
begin
if (s'length = 1) then return (To_X01Z(s(s'low)));
else
for i in s'range loop
result := resolution_table(result, To_X01Z(s(i)));
end loop;
end if;
return result;
end wor_trior;
function rddata_o_resolv (s: rddata_o_array) return std_logic_vector is
variable wor: std_logic_vector (s'range);
variable result: std_logic_vector (rddata_o_range);
begin
for i in result'range loop
for j in s'range loop
wor(j) := s(j)(i);
end loop;
-- report "wor = " & slv_image(wor);
result(i) := wor_trior(wor);
end loop;
return result;
end function;
function slv_image(inp: std_logic_vector) return string is
variable image_str: string (1 to inp'length);
alias input_str: std_logic_vector (1 to inp'length) is inp;
begin
for i in input_str'range loop
image_str(i) := character'VALUE(std_ulogic'IMAGE(input_str(i)));
end loop;
return image_str;
end;
end package body;
library ieee;
use ieee.std_logic_1164.all;
use work.wor_std.all;
entity cpu_reg_dummy is
generic ( value: std_logic_vector(3 downto 0) := (others => 'Z') );
port ( rddata_o: out std_logic_vector(3 downto 0) );
end entity;
architecture foo of cpu_reg_dummy is
begin
rddata_o <= value after 0.5 ns;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use work.wor_std.all;
entity foe is
end entity;
architecture fum of foe is
component cpu_reg_dummy
generic ( value: std_logic_vector(rddata_o_range) := (others => 'Z') );
port ( rddata_o: out std_logic_vector(rddata_o_range) );
end component;
signal rddata_o: rddata_o_resolv std_logic_vector (rddata_o_range);
begin
CPU_REG1:
cpu_reg_dummy
generic map (value => "0000")
port map (rddata_o => rddata_o);
CPU_REG2:
cpu_reg_dummy
generic map (value => "1001")
port map (rddata_o => rddata_o);
CPU_REG3:
cpu_reg_dummy
generic map (value => "ZZZZ")
port map (rddata_o => rddata_o);
CPU_REG4:
cpu_reg_dummy
generic map (value => "ZZZX")
port map (rddata_o => rddata_o);
WHAT:
process
begin
wait for 0.6 ns;
report "rddata_o = " & slv_image(rddata_o);
wait;
end process;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1206.vhd | 4 | 1984 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1206.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s01b00x00p08n04i01206ent IS
END c08s01b00x00p08n04i01206ent;
ARCHITECTURE c08s01b00x00p08n04i01206arch OF c08s01b00x00p08n04i01206ent IS
signal cll : integer := 0;
signal del : integer := 0;
BEGIN
TESTING: PROCESS
BEGIN
cll <= 5 after 55 ns;
del <= 5 after 55 ns;
wait until (cll = 5 or del = 5);
assert NOT( cll=5 )
report "***PASSED TEST: c08s01b00x00p08n04i01206"
severity NOTE;
assert ( cll=5 )
report "***FAILED TEST: c08s01b00x00p08n04i01206 - if no sensitivity clause appears, the sensitivity set will contain the signals denoted by the longest static prefix of each signal name that appears as a primary in the condition of the condirion clause."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s01b00x00p08n04i01206arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2070.vhd | 4 | 1852 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2070.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n02i02070ent IS
END c07s02b04x00p01n02i02070ent;
ARCHITECTURE c07s02b04x00p01n02i02070arch OF c07s02b04x00p01n02i02070ent IS
BEGIN
TESTING: PROCESS
-- All different type declarations.
-- integer types.
type POSITIVE is range 0 to INTEGER'HIGH;
-- Local declarations.
variable POSV : POSITIVE := 0;
variable REALV : REAL := 0.0;
BEGIN
POSV := POSV + REALV;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n02i02070 - The operands of the operators + and - cannot be of different types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n02i02070arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc622.vhd | 4 | 2207 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc622.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:45 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00622ent IS
END c03s04b01x00p01n01i00622ent;
ARCHITECTURE c03s04b01x00p01n01i00622arch OF c03s04b01x00p01n01i00622ent IS
constant C4 : positive := 3 ;
type positive_vector is array (natural range <>) of positive;
subtype positive_vector_st is positive_vector(0 to 15);
type positive_vector_st_file is file of positive_vector_st;
constant C27 : positive_vector_st := (others => C4);
BEGIN
TESTING: PROCESS
file filein : positive_vector_st_file open write_mode is "iofile.30";
BEGIN
for i in 1 to 100 loop
write(filein, C27);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00622 - The output file will be verified by test s010268.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00622arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2558.vhd | 4 | 1959 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2558.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b06x00p03n02i02558ent IS
END c07s03b06x00p03n02i02558ent;
ARCHITECTURE c07s03b06x00p03n02i02558arch OF c07s03b06x00p03n02i02558ent IS
BEGIN
TESTING: PROCESS
type CELL;
type LINK is access CELL;
type CELL is
record
VALUE : Bit;
SUCC : Bit;
end record;
variable HEAD : LINK := new CELL ;
BEGIN
assert NOT(HEAD.VALUE='0')
report "***PASSED TEST: c07s03b06x00p03n02i02558"
severity NOTE;
assert (HEAD.VALUE='0')
report "***FAILED TEST: c07s03b06x00p03n02i02558 - The initial value of the created object is the same as the default initial value for an explicitly declared variable of the designated subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b06x00p03n02i02558arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1177.vhd | 4 | 1761 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1177.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s00b00x00p01n02i01177ent IS
END c08s00b00x00p01n02i01177ent;
ARCHITECTURE c08s00b00x00p01n02i01177arch OF c08s00b00x00p01n02i01177ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
if FALSE = FALSE then
end if;
k := 5;
assert NOT(k=5)
report "***PASSED TEST: c08s00b00x00p01n02i01177"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c08s00b00x00p01n02i01177 - Empty sequence of statement is permitted in 'if statement'."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s00b00x00p01n02i01177arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc3071.vhd | 4 | 4017 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3071.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c12s06b02x00p06n01i03071pkg is
type time_cons_vector is array (15 downto 0) of time;
constant C19 : time_cons_vector := (others => 3 ns);
end c12s06b02x00p06n01i03071pkg;
use work.c12s06b02x00p06n01i03071pkg.all;
ENTITY c12s06b02x00p06n01i03071ent_a IS
PORT
(
F1: OUT integer ;
F3: IN time_cons_vector;
FF: OUT integer := 0
);
END c12s06b02x00p06n01i03071ent_a;
ARCHITECTURE c12s06b02x00p06n01i03071arch_a OF c12s06b02x00p06n01i03071ent_a IS
BEGIN
TESTING: PROCESS
begin
F1 <= 3;
wait for 0 ns;
assert F3'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3'active = true)) then
F1 <= 11;
end if;
assert F3(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(0)'active = true)) then
F1 <= 11;
end if;
assert F3(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
if (not(F3(15)'active = true)) then
F1 <= 11;
end if;
wait;
END PROCESS;
END c12s06b02x00p06n01i03071arch_a;
use work.c12s06b02x00p06n01i03071pkg.all;
ENTITY c12s06b02x00p06n01i03071ent IS
END c12s06b02x00p06n01i03071ent;
ARCHITECTURE c12s06b02x00p06n01i03071arch OF c12s06b02x00p06n01i03071ent IS
function scalar_complex(s : integer) return time_cons_vector is
begin
return C19;
end scalar_complex;
component model
PORT
(
F1: OUT integer;
F3: IN time_cons_vector;
FF: OUT integer
);
end component;
for T1 : model use entity work.c12s06b02x00p06n01i03071ent_a(c12s06b02x00p06n01i03071arch_a);
signal S1 : time_cons_vector;
signal S3 : integer;
signal SS : integer := 0;
BEGIN
T1: model
port map (
scalar_complex(F1) => S1,
F3 => scalar_complex(S3),
FF => SS
);
TESTING: PROCESS
BEGIN
S3 <= 3;
wait for 0 ns;
assert S1'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(0)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert S1(15)'active = true
report"no activity on F3 when there is activity on actual"
severity failure;
assert NOT(S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***PASSED TEST: c12s06b02x00p06n01i03071"
severity NOTE;
assert (S1'active = true and S1(0)'active = true and S1(15)'active = true and SS = 0)
report "***FAILED TEST: c12s06b02x00p06n01i03071 - Not every scalar subelement is active if the source itself is active."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b02x00p06n01i03071arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/AMS_CS3_Power_Systems/sw_LoopCtrl_wa.vhd | 4 | 1499 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity sw_LoopCtrl_wa is
generic ( r_open : resistance := 1.0e6;
r_closed : resistance := 1.0e-3;
sw_state : integer := 1 );
port ( terminal c, p1, p2 : electrical );
end entity sw_LoopCtrl_wa;
----------------------------------------------------------------
architecture ideal of sw_LoopCtrl_wa is
quantity v1 across i1 through c to p1;
quantity v2 across i2 through c to p2;
quantity r1, r2 : resistance;
begin
if (sw_state = 2) use
r1 == r_open;
r2 == r_closed;
else
r1 == r_closed;
r2 == r_open;
end use;
v1 == r1 * i1;
v2 == r2 * i2;
end architecture ideal;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/synth109/ram1.vhdl | 1 | 941 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ram1 is
generic (
WIDTHB : integer := 32;
SIZEB : integer := 64;
ADDRWIDTHB : integer := 6
);
port (
clkB : in std_logic;
enB : in std_logic;
weB : in std_logic;
addrB : in std_logic_vector(ADDRWIDTHB-1 downto 0);
diB : in std_logic_vector(WIDTHB-1 downto 0);
doB : out std_logic_vector(WIDTHB-1 downto 0)
);
end ram1;
architecture behavioral of ram1 is
type ramType is array (0 to SIZEB-1) of std_logic_vector(WIDTHB-1 downto 0);
shared variable ram : ramType := (others => (others => '0'));
begin
process (clkB)
begin
if rising_edge(clkB) then
if enB = '1' then
if weB = '1' then
ram(to_integer(unsigned(addrB))) := diB;
end if;
doB <= ram(to_integer(unsigned(addrB)));
end if;
end if;
end process;
end behavioral;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug040/cmp_978.vhd | 2 | 383 | library ieee;
use ieee.std_logic_1164.all;
entity cmp_978 is
port (
ne : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_978;
architecture augh of cmp_978 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
ne <= not(tmp);
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc993.vhd | 4 | 2179 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc993.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c06s03b00x00p08n02i00993pkg is
type T1 is record
S1 : Bit ;
S2 : Integer;
end record;
type T2 is record
S11 : BIT ;
S12 : T1 ;
end record;
end c06s03b00x00p08n02i00993pkg;
use work.c06s03b00x00p08n02i00993pkg.all;
ENTITY c06s03b00x00p08n02i00993ent IS
END c06s03b00x00p08n02i00993ent;
ARCHITECTURE c06s03b00x00p08n02i00993arch OF c06s03b00x00p08n02i00993ent IS
BEGIN
TESTING: PROCESS
variable V1 : T2 ;
BEGIN
V1.S12.S2 := 10 ; -- No_Failure_here
wait for 10 ns;
assert NOT(V1.S12.S2 = 10)
report "***PASSED TEST: c06s03b00x00p08n02i00993"
severity NOTE;
assert (V1.S12.S2 = 10)
report "***FAILED TEST: c06s03b00x00p08n02i00993 - The expanded name denotes all primary units contained in a library if the prefix denotes the library and the suffix is the reserved word all."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p08n02i00993arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc659.vhd | 4 | 3116 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc659.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:55 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:23 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:34 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00659ent IS
END c03s04b01x00p01n01i00659ent;
ARCHITECTURE c03s04b01x00p01n01i00659arch OF c03s04b01x00p01n01i00659ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type time_vector is array (natural range <>) of time;
subtype time_vector_range is time_vector(hi_to_low_range);
constant C1 : time_vector_range := (others => 3 ns);
type time_vector_range_file is file of time_vector_range;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : time_vector_range_file open read_mode is "iofile.07";
variable v : time_vector_range := C1;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C1) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00659"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00659 - File reading of time_vector_range_file operation failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00659arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue467/eu_tb.vhdl | 1 | 523 | package unbound_rec is
type UnbRecType is record
writedata: bit_vector;
end record;
end package;
use work.unbound_rec.all;
entity eut is
port (
form_sig: out UnbRecType
);
end entity;
architecture foo of eut is
begin
end architecture;
use work.unbound_rec.all;
entity eu_tb is
end entity;
architecture fum of eu_tb is
signal act_sig: UnbRecType (writedata (7 downto 0));
begin
UUT:
entity work.eut
port map (
form_sig => act_sig
);
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue1076/ent2.vhdl | 1 | 1093 | library ieee;
use ieee.std_logic_1164.all;
entity ent2 is
-- This case works.
-- generic ( CONFIG_C1: boolean := false );
port (
i : in std_logic;
o : out std_logic;
q : out std_logic
);
constant CONFIG_C1 : boolean := false;
end;
architecture a of ent2 is
component c1 is
port (i: in std_logic; o : out std_logic);
end component;
component c2 is
port (i: in std_logic; o : out std_logic);
end component;
begin
gen: if false generate
o <= '1';
else generate
o <= '0';
end generate;
maybe_c1:
if CONFIG_C1 generate
c1_inst: c1 port map (i => i, o=> q);
end generate;
maybe_c2:
if not CONFIG_C1 generate
c2_inst: c2 port map (i => i, o=> q);
end generate;
end;
-- Added entities to satisfy simulation:
library ieee;
use ieee.std_logic_1164.all;
entity c1 is
port (i: in std_logic; o : out std_logic);
end entity;
architecture a of c1 is
begin
o <= i;
end a;
library ieee;
use ieee.std_logic_1164.all;
entity c2 is
port (i: in std_logic; o : out std_logic);
end entity;
architecture a of c2 is
begin
o <= i;
end a;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc501.vhd | 4 | 1942 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc501.vhd,v 1.2 2001-10-26 16:29:55 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b02x00p02n01i00501ent IS
END c03s02b02x00p02n01i00501ent;
ARCHITECTURE c03s02b02x00p02n01i00501arch OF c03s02b02x00p02n01i00501ent IS
type rec_type is
record
x : integer;
y : integer;
end record;
BEGIN
TESTING: PROCESS
variable v1 : rec_type;
BEGIN
v1.x := 12;
v1.y := v1.x * 111;
assert NOT(v1.x=12 and v1.y=1332)
report "***PASSED TEST: c03s02b02x00p02n01i00501"
severity NOTE;
assert (v1.x=12 and v1.y=1332)
report "***FAILED TEST: c03s02b02x00p02n01i00501 - The record type definition consists of the reserved word record, one or more element declarations, and the reserved words end record."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b02x00p02n01i00501arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug040/add_203.vhd | 2 | 800 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_203 is
port (
output : out std_logic_vector(38 downto 0);
in_b : in std_logic_vector(38 downto 0);
in_a : in std_logic_vector(38 downto 0)
);
end add_203;
architecture augh of add_203 is
signal carry_inA : std_logic_vector(40 downto 0);
signal carry_inB : std_logic_vector(40 downto 0);
signal carry_res : std_logic_vector(40 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
output <= carry_res(39 downto 1);
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc930.vhd | 4 | 2402 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc930.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c10s04b00x00p03n01i00930pkg is
constant x : integer := 2;
constant y : real := 5.0;
subtype register16 is bit_vector(15 downto 0);
function "+" (l,r : bit_vector) return bit_vector;
end c10s04b00x00p03n01i00930pkg;
package body c10s04b00x00p03n01i00930pkg is
function "+" (l,r : bit_vector) return bit_vector is
begin
return (B"1111010100101010");
end;
end c10s04b00x00p03n01i00930pkg;
use work.c10s04b00x00p03n01i00930pkg."+";
use work.c10s04b00x00p03n01i00930pkg.register16;
ENTITY c10s04b00x00p03n01i00930ent IS
END c10s04b00x00p03n01i00930ent;
ARCHITECTURE c10s04b00x00p03n01i00930arch OF c10s04b00x00p03n01i00930ent IS
signal i_sig : register16 := B"1010_1110_1010_0011";
BEGIN
TESTING: PROCESS
BEGIN
i_sig <= i_sig + i_sig after 10 ns;
wait for 11 ns;
assert NOT(i_sig = "1111010100101010")
report "***PASSED TEST: c10s04b00x00p03n01i00930"
severity NOTE;
assert (i_sig = "1111010100101010")
report "***FAILED TEST: c10s04b00x00p03n01i00930 - The operator is visible in the declaration region if the suffix of a selected name in a use clause is an operator."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s04b00x00p03n01i00930arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1764.vhd | 4 | 1718 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1764.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s05b02x00p02n01i01764ent IS
END c09s05b02x00p02n01i01764ent;
ARCHITECTURE c09s05b02x00p02n01i01764arch OF c09s05b02x00p02n01i01764ent IS
signal TS: integer;
signal B: bit;
BEGIN
with B
TS <= transport 1 when '0', -- Failure_here
-- the reserved word 'select' is missing
2 when '1';
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s05b02x00p02n01i01764 - the reserved word select is missing."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s05b02x00p02n01i01764arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/aggr03/conv01.vhdl | 1 | 362 | library ieee;
use ieee.std_logic_1164.all;
entity conv01 is
port (i : std_logic_vector (19 downto 0);
o : out std_logic_vector (31 downto 0));
end conv01;
architecture behav of conv01 is
begin
process (i)
variable v : std_logic_vector (31 downto 0);
begin
v := (i'left downto 0 => i, others => '0');
o <= v;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue797/pkg_c.vhdl | 1 | 1673 | package pkg_c is
type byte_vector_access_t is access string;
type extbuf_access_t is access string(1 to integer'high);
impure function
get_addr(
id : integer
) return extbuf_access_t;
attribute foreign of get_addr : function is "VHPIDIRECT get_addr";
impure function
get_baddr(
id : integer
) return byte_vector_access_t;
attribute foreign of get_baddr : function is "VHPIDIRECT get_baddr";
procedure
set(
index : natural;
value : natural
);
impure function
get(
index : natural
) return natural;
end pkg_c;
package body pkg_c is
impure function
get_addr(
id : integer
) return extbuf_access_t is begin
assert false report "VHPI get_addr" severity failure;
end;
impure function
get_baddr(
id : integer
) return byte_vector_access_t is begin
assert false report "VHPI get_baddr" severity failure;
end;
procedure
set(
index : natural;
value : natural
) is
variable a : extbuf_access_t := get_addr(0);
variable b : byte_vector_access_t := get_baddr(0);
variable c : byte_vector_access_t(1 to integer'high) := get_baddr(0);
begin
a(index+1) := character'val(value);
--b(index+1) := character'val(value);
c(index+1) := character'val(value);
end;
impure function
get(
index : natural
) return natural is
variable a : extbuf_access_t := get_addr(0);
variable b : byte_vector_access_t := get_baddr(0);
variable c : byte_vector_access_t(1 to integer'high) := get_baddr(0);
begin
return character'pos(a(index+1));
--return character'pos(b(index+1));
return character'pos(c(index+1));
end;
end pkg_c;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1180.vhd | 4 | 1793 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1180.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s00b00x00p02n01i01180ent IS
END c08s00b00x00p02n01i01180ent;
ARCHITECTURE c08s00b00x00p02n01i01180arch OF c08s00b00x00p02n01i01180ent IS
BEGIN
TESTING: PROCESS
procedure check (x : out boolean) is
begin
x := false;
end;
variable k : boolean;
BEGIN
check (k);
assert NOT( k=false )
report "***PASSED TEST: c08s00b00x00p02n01i01180"
severity NOTE;
assert ( k=false )
report "***FAILED TEST: c08s00b00x00p02n01i01180 - Procedure call is a sequential statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s00b00x00p02n01i01180arch;
| gpl-2.0 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.