repo_name
stringlengths 6
79
| path
stringlengths 5
236
| copies
stringclasses 54
values | size
stringlengths 1
8
| content
stringlengths 0
1.04M
⌀ | license
stringclasses 15
values |
|---|---|---|---|---|---|
6769/VHDL | Lab_5/__FromSaru/lab50/comparator.vhd | 1 | 449 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity comparator is
port(point:in std_logic_vector(3 downto 0);
sum:in std_logic_vector(3 downto 0);
eq:out bit);
end comparator;
architecture compare of comparator is
begin
--could be alternatived by MUX statements...3 lines...--
process(point,sum)
begin
if point=sum then
eq<='1';
else eq<='0';
end if;
end process;
end compare; | gpl-2.0 |
sorgelig/SAMCoupe_MIST | sid/sid_debug_pkg.vhd | 6 | 1235 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package sid_debug_pkg is
type t_voice_debug is record
state : unsigned(1 downto 0);
enveloppe : unsigned(7 downto 0);
pre15 : unsigned(14 downto 0);
pre5 : unsigned(4 downto 0);
presc : unsigned(14 downto 0);
gate : std_logic;
attack : std_logic_vector(3 downto 0);
decay : std_logic_vector(3 downto 0);
sustain : std_logic_vector(3 downto 0);
release : std_logic_vector(3 downto 0);
end record;
type t_voice_debug_array is array(natural range <>) of t_voice_debug;
end;
| gpl-2.0 |
6769/VHDL | Lab_4/Part1/clock_second.vhd | 1 | 783 | --Intertime clock
library ieee;
use ieee.numeric_bit.all;
entity clock_second is
port(clk:in bit ;
second:buffer bit);
end entity clock_second;
architecture Distribution of clock_second is
signal counter_for_osc_signal:unsigned(31 downto 0);
begin
process
begin
wait until clk'event and clk='1';
if counter_for_osc_signal < 25--*1000*1000
then
counter_for_osc_signal<=counter_for_osc_signal+1;
else counter_for_osc_signal<=(others=>'0');
second<=not second;
--here is the problem that second signal will result unflatten square wave,if using the commented mathod.
end if;
end process;
-- second<='1' when counter_for_osc_signal> 25*1000*1000 --High_percent_of_counter
-- else '0' ;
-- timing analysis here ...
end architecture Distribution;
| gpl-2.0 |
zzhou007/161lab | lab04/tb.vhd | 1 | 9455 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:18:41 02/16/2016
-- Design Name:
-- Module Name: /home/csmajs/jholl013/Desktop/lab4_control/main_tb.vhd
-- Project Name: lab4_control
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: main
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY main_tb IS
END main_tb;
ARCHITECTURE behavior OF main_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT main
PORT(
functionfield : IN std_logic_vector(5 downto 0);
instr_op_main : IN std_logic_vector(5 downto 0);
reg_dst : OUT std_logic;
branch : OUT std_logic;
mem_read : OUT std_logic;
mem_to_reg : OUT std_logic;
alu_output : OUT std_logic_vector(3 downto 0);
mem_write : OUT std_logic;
alu_src : OUT std_logic;
reg_write : OUT std_logic
);
END COMPONENT;
--Inputs
signal functionfield : std_logic_vector(5 downto 0) := (others => '0');
signal instr_op_main : std_logic_vector(5 downto 0) := (others => '0');
--Outputs
signal reg_dst : std_logic;
signal branch : std_logic;
signal mem_read : std_logic;
signal mem_to_reg : std_logic;
signal alu_output : std_logic_vector(3 downto 0);
signal mem_write : std_logic;
signal alu_src : std_logic;
signal reg_write : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: main PORT MAP (
functionfield => functionfield,
instr_op_main => instr_op_main,
reg_dst => reg_dst,
branch => branch,
mem_read => mem_read,
mem_to_reg => mem_to_reg,
alu_output => alu_output,
mem_write => mem_write,
alu_src => alu_src,
reg_write => reg_write
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- insert stimulus here
---------------------------------------
report "Testing r-type instructions";
instr_op_main <= "000000";
---------------------------------------
-- Test 1 (Add instruction)
functionfield <= "100000";
wait for 10 ns;
assert reg_dst = '1' report "Test 1 fail - reg_dst" severity Warning;
assert alu_src = '0' report "Test 1 fail - alu_src" severity Warning;
assert mem_to_reg = '0' report "Test 1 fail - mem_to_reg" severity Warning;
assert reg_write = '1' report "Test 1 fail - reg_write" severity Warning;
assert mem_read = '0' report "Test 1 fail - mem_read" severity Warning;
assert mem_write = '0' report "Test 1 fail - mem_write" severity Warning;
assert branch = '0' report "Test 1 fail - branch" severity Warning;
assert alu_output = "0010" report "Test 1 fail - alu_out" severity Warning;
-- Test 2 (Subtract)
functionfield <= "100010";
wait for 10 ns;
assert reg_dst = '1' report "Test 2 fail - reg_dst" severity Warning;
assert alu_src = '0' report "Test 2 fail - alu_src" severity Warning;
assert mem_to_reg = '0' report "Test 2 fail - mem_to_reg" severity Warning;
assert reg_write = '1' report "Test 2 fail - reg_write" severity Warning;
assert mem_read = '0' report "Test 2 fail - mem_read" severity Warning;
assert mem_write = '0' report "Test 2 fail - mem_write" severity Warning;
assert branch = '0' report "Test 2 fail - branch" severity Warning;
assert alu_output = "0110" report "Test 2 fail - alu_out" severity Warning;
-- Test 3 (AND)
functionfield <= "100100";
wait for 10 ns;
assert reg_dst = '1' report "Test 3 fail - reg_dst" severity Warning;
assert alu_src = '0' report "Test 3 fail - alu_src" severity Warning;
assert mem_to_reg = '0' report "Test 3 fail - mem_to_reg" severity Warning;
assert reg_write = '1' report "Test 3 fail - reg_write" severity Warning;
assert mem_read = '0' report "Test 3 fail - mem_read" severity Warning;
assert mem_write = '0' report "Test 3 fail - mem_write" severity Warning;
assert branch = '0' report "Test 3 fail - branch" severity Warning;
assert alu_output = "0000" report "Test 3 fail - alu_out" severity Warning;
-- Test 4 (OR)
functionfield <= "100101";
wait for 10 ns;
assert reg_dst = '1' report "Test 4 fail - reg_dst" severity Warning;
assert alu_src = '0' report "Test 4 fail - alu_src" severity Warning;
assert mem_to_reg = '0' report "Test 4 fail - mem_to_reg" severity Warning;
assert reg_write = '1' report "Test 4 fail - reg_write" severity Warning;
assert mem_read = '0' report "Test 4 fail - mem_read" severity Warning;
assert mem_write = '0' report "Test 4 fail - mem_write" severity Warning;
assert branch = '0' report "Test 4 fail - branch" severity Warning;
assert alu_output = "0001" report "Test 4 fail - alu_out" severity Warning;
-- Test 5 (set on less than)
functionfield <= "101010";
wait for 10 ns;
assert reg_dst = '1' report "Test 5 fail - reg_dst" severity Warning;
assert alu_src = '0' report "Test 5 fail - alu_src" severity Warning;
assert mem_to_reg = '0' report "Test 5 fail - mem_to_reg" severity Warning;
assert reg_write = '1' report "Test 5 fail - reg_write" severity Warning;
assert mem_read = '0' report "Test 5 fail - mem_read" severity Warning;
assert mem_write = '0' report "Test 5 fail - mem_write" severity Warning;
assert branch = '0' report "Test 5 fail - branch" severity Warning;
assert alu_output = "0111" report "Test 5 fail - alu_out" severity Warning;
-- Test 6 (NOR)
functionfield <= "100111";
wait for 10 ns;
assert reg_dst = '1' report "Test 6 fail - reg_dst" severity Warning;
assert alu_src = '0' report "Test 6 fail - alu_src" severity Warning;
assert mem_to_reg = '0' report "Test 6 fail - mem_to_reg" severity Warning;
assert reg_write = '1' report "Test 6 fail - reg_write" severity Warning;
assert mem_read = '0' report "Test 6 fail - mem_read" severity Warning;
assert mem_write = '0' report "Test 6 fail - mem_write" severity Warning;
assert branch = '0' report "Test 6 fail - branch" severity Warning;
assert alu_output = "1100" report "Test 6 fail - alu_out" severity Warning;
---------------------------------------
report "Testing load/store instructions";
---------------------------------------
-- Test 7 - (load word)
instr_op_main <= "100011";
wait for 10 ns;
assert reg_dst = '0' report "Test 7 fail - reg_dst" severity Warning;
assert alu_src = '1' report "Test 7 fail - alu_src" severity Warning;
assert mem_to_reg = '1' report "Test 7 fail - mem_to_reg" severity Warning;
assert reg_write = '1' report "Test 7 fail - reg_write" severity Warning;
assert mem_read = '1' report "Test 7 fail - mem_read" severity Warning;
assert mem_write = '0' report "Test 7 fail - mem_write" severity Warning;
assert branch = '0' report "Test 7 fail - branch" severity Warning;
assert alu_output = "0010" report "Test 7 fail - alu_out" severity Warning;
-- Test 8 - (store word)
instr_op_main <= "101011";
wait for 10 ns;
--assert reg_dst = '0' report "Test 8 fail - reg_dst" severity Warning;
assert alu_src = '1' report "Test 8 fail - alu_src" severity Warning;
--assert mem_to_reg = '1' report "Test 8 fail - mem_to_reg" severity Warning;
assert reg_write = '0' report "Test 8 fail - reg_write" severity Warning;
assert mem_read = '0' report "Test 8 fail - mem_read" severity Warning;
assert mem_write = '1' report "Test 8 fail - mem_write" severity Warning;
assert branch = '0' report "Test 8 fail - branch" severity Warning;
assert alu_output = "0010" report "Test 8 fail - alu_out" severity Warning;
------------------------------------
report "Testing beq instruction";
------------------------------------
-- Test 9 - (branch equals)
instr_op_main <= "000100";
wait for 10 ns;
--assert reg_dst = '0' report "Test 9 fail - reg_dst" severity Warning;
assert alu_src = '0' report "Test 9 fail - alu_src" severity Warning;
--assert mem_to_reg = '1' report "Test 9 fail - mem_to_reg" severity Warning;
assert reg_write = '0' report "Test 9 fail - reg_write" severity Warning;
assert mem_read = '0' report "Test 9 fail - mem_read" severity Warning;
assert mem_write = '0' report "Test 9 fail - mem_write" severity Warning;
assert branch = '1' report "Test 9 fail - branch" severity Warning;
assert alu_output = "0110" report "Test 9 fail - alu_out" severity Warning;
wait;
end process;
END;
| gpl-2.0 |
6769/VHDL | Lab_5/Compartor.vhd | 1 | 361 | entity Compartor is
port(
Sum,LockedSum:in integer range 2 to 12;
Eq,D7,D711,D2312:out bit
);
end entity Compartor;
architecture Behavior of Compartor is
begin
Eq<='1' when Sum=LockedSum else '0';
D7<='1' when Sum=7 else '0';
D711<='1' when Sum=7 or Sum=11 else '0';
D2312<='1' when Sum=2 or Sum=3 or Sum=12 else '0';
end architecture Behavior;
| gpl-2.0 |
6769/VHDL | Lab_1_partC/Segment7Decoder.vhd | 1 | 1085 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Segment7Decoder is
port (bcd : in std_logic_vector(3 downto 0); --BCD input
segment7 : out std_logic_vector(6 downto 0) -- 7 bit decoded output.
);
end Segment7Decoder;
--'a' corresponds to MSB of segment7 and g corresponds to LSB of segment7.
architecture Behavioral of Segment7Decoder is
begin
process (bcd)
BEGIN
case bcd is
when "0000"=> segment7 <="1000000"; -- '0'
when "0001"=> segment7 <="1111001"; -- '1'
when "0010"=> segment7 <="0100100"; -- '2'
when "0011"=> segment7 <="0110000"; -- '3'
when "0100"=> segment7 <="0011001"; -- '4'
when "0101"=> segment7 <="0010010"; -- '5'
when "0110"=> segment7 <="0000010"; -- '6'
when "0111"=> segment7 <="1111000"; -- '7'
when "1000"=> segment7 <="0000000"; -- '8'
when "1001"=> segment7 <="0010000"; -- '9'
--nothing is displayed when a number more than 9 is given as input.
when others=> segment7 <="1111111";
end case;
end process;
end Behavioral; | gpl-2.0 |
6769/VHDL | Lab_4/Part2/frequency.vhd | 1 | 544 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity frequency is
port(clk50M:in std_logic;
clk_1hz:out std_logic);
end entity frequency;
architecture behave of frequency is
signal t:std_logic_vector(24 downto 0);
signal clk:std_logic;
begin
process(clk50M)
begin
if rising_edge(clk50M) then
if t="1011111010111100000111111" then
t<="0000000000000000000000000";
clk<=not clk;
else t<=t+1;
end if;
end if;
end process;
clk_1hz<=clk;
end architecture behave;
| gpl-2.0 |
vzh/lepton-eda | tools/netlist/examples/vams/vhdl/new-vhdl/resistor.vhdl | 15 | 299 | LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY RESISTOR IS
GENERIC ( r : REAL := 10000.0 );
PORT ( terminal LT : electrical;
terminal RT : electrical );
END ENTITY RESISTOR;
| gpl-2.0 |
vzh/lepton-eda | tools/netlist/examples/vams/vhdl/basic-vhdl/transitest_arc.vhdl | 15 | 1201 | -- Structural VAMS generated by gnetlist
-- Secondary unit
ARCHITECTURE transistor_test OF top_entity IS
terminal unnamed_net5 : electrical;
terminal unnamed_net4 : electrical;
terminal unnamed_net3 : electrical;
terminal unnamed_net2 : electrical;
terminal unnamed_net1 : electrical;
BEGIN
-- Architecture statement part
BJT1 : ENTITY BJT_transistor_simple(simple_arc)
GENERIC MAP (
NEL => 5.0)
PORT MAP ( Base => unnamed_net2,
Collector => unnamed_net5,
Emitter => unnamed_net1);
VS_base : ENTITY VOLTAGE_SOURCE(sinusodial)
GENERIC MAP (
amplitude => 1.0,
k => 150.0)
PORT MAP ( LT => unnamed_net3,
RT => unnamed_net1);
VS_collector : ENTITY VOLTAGE_SOURCE(sinusodial)
GENERIC MAP (
amplitude => 2.0,
offset => 10.2,
k => 100.0)
PORT MAP ( LT => unnamed_net4,
RT => unnamed_net1);
RES_collecter : ENTITY RESISTOR
GENERIC MAP (
r => 60.0)
PORT MAP ( RT => unnamed_net4,
LT => unnamed_net5);
RES_base : ENTITY RESISTOR
GENERIC MAP (
r => 10000.0)
PORT MAP ( RT => unnamed_net2,
LT => unnamed_net3);
GND : ENTITY GROUND_NODE
PORT MAP ( T1 => unnamed_net1);
END ARCHITECTURE transistor_test;
| gpl-2.0 |
vzh/lepton-eda | tools/netlist/examples/vams/vhdl/basic-vhdl/transitest.vhdl | 15 | 192 | LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY top_entity IS
END ENTITY top_entity;
| gpl-2.0 |
vzh/lepton-eda | tools/netlist/examples/vams/vhdl/basic-vhdl/current_source.vhdl | 15 | 353 | LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY CURRENT_SOURCE IS
GENERIC ( N : REAL := 1.0;
VT : REAL := 25.85e-6;
ISS : REAL := 10.0e-14 );
PORT ( terminal RT : electrical;
terminal LT : electrical );
END ENTITY CURRENT_SOURCE;
| gpl-2.0 |
vzh/lepton-eda | tools/netlist/examples/vams/vhdl/basic-vhdl/bjt_transistor_simple_arc.vhdl | 15 | 1525 | -- Structural VAMS generated by gnetlist
-- Secondary unit
ARCHITECTURE simple_arc OF BJT_transistor_simple IS
terminal unnamed_net8 : electrical;
terminal unnamed_net7 : electrical;
terminal unnamed_net5 : electrical;
terminal unnamed_net4 : electrical;
terminal unnamed_net1 : electrical;
BEGIN
-- Architecture statement part
SP1 : ENTITY SP_DIODE(SPICE_Diode_Model)
GENERIC MAP (
VT => VT,
AF => AF,
KF => KF,
PT => PT,
EG => EG,
M => ME,
PB => PE,
TT => TF,
CJ0 => CJE,
ISS => ISS)
PORT MAP ( ANODE => unnamed_net8,
KATHODE => unnamed_net5);
CS2 : ENTITY SPICE_cs(current_controlled)
GENERIC MAP (
N => BF,
VT => VT,
ISS => ISS)
PORT MAP ( urt => unnamed_net4,
lrt => unnamed_net5,
ult => unnamed_net1,
llt => unnamed_net8);
CAP2 : ENTITY CAPACITOR
PORT MAP ( LT => unnamed_net5,
RT => unnamed_net1);
CAP1 : ENTITY CAPACITOR
PORT MAP ( LT => unnamed_net1,
RT => unnamed_net4);
GND1 : ENTITY GROUND_NODE
PORT MAP ( T1 => unnamed_net7);
CAP3 : ENTITY CAPACITOR
GENERIC MAP (
c => CCS)
PORT MAP ( LT => unnamed_net7,
RT => unnamed_net4);
RES_emitter : ENTITY RESISTOR
GENERIC MAP (
r => RE)
PORT MAP ( RT => unnamed_net5,
LT => emitter);
RES_collector : ENTITY RESISTOR
GENERIC MAP (
r => RC)
PORT MAP ( RT => collector,
LT => unnamed_net4);
RES_base : ENTITY RESISTOR
GENERIC MAP (
r => RB)
PORT MAP ( RT => unnamed_net1,
LT => base);
END ARCHITECTURE simple_arc;
| gpl-2.0 |
vzh/lepton-eda | tools/netlist/examples/vams/vhdl/basic-vhdl/bjt_transistor_simple.vhdl | 15 | 910 | LIBRARY ieee,disciplines;
USE ieee.math_real.all;
USE ieee.math_real.all;
USE work.electrical_system.all;
USE work.all;
-- Entity declaration --
ENTITY BJT_transistor_simple IS
GENERIC ( VT : REAL := 25.85e-3;
AF : REAL := 1.0;
KF : REAL := 0.0;
PT : REAL := 3.0;
EG : REAL := 1.11;
MC : REAL := 0.5;
PC : REAL := 1.0;
CJC : REAL := 2.5e-12;
ME : REAL := 0.5;
PE : REAL := 1.0;
CJE : REAL := 2.5e-12;
CCS : REAL := 2.5e-12;
TR : REAL := 4.0e-9;
TF : REAL := 4.0e-9;
NCL : REAL := 2.0;
C4 : REAL := 0.0;
NEL : REAL := 2.0;
C2 : REAL := 0.0;
RS : REAL := 1.0;
RE : REAL := 1.0;
RC : REAL := 1.0;
RB : REAL := 1.0;
ISS : REAL := 10.0e-14;
BR : REAL := 1.0;
BF : REAL := 100.0 );
PORT ( terminal Emitter : electrical;
terminal Collector : electrical;
terminal Base : electrical );
END ENTITY BJT_transistor_simple;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/var01/var01.vhdl | 1 | 589 | library ieee;
use ieee.std_logic_1164.all;
entity var01 is
port (clk : std_logic;
mask : std_logic_vector (3 downto 0);
val : std_logic_vector (31 downto 0);
res : out std_logic_vector (31 downto 0));
end var01;
architecture behav of var01 is
begin
process (clk)
variable hi, lo : natural;
begin
if rising_edge (clk) then
for i in 0 to 3 loop
if mask (i) = '1' then
lo := i * 8;
hi := lo + 7;
res (hi downto lo) <= val (hi downto lo);
end if;
end loop;
end if;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_06_tofp-b.vhd | 4 | 1796 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_06_tofp-b.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture behavioral of to_fp is
begin
behavior : process (vec) is
variable temp : bit_vector(vec'range);
variable negative : boolean;
variable int_result : integer;
begin
temp := to_bitvector(vec);
negative := temp(temp'left) = '1';
if negative then
temp := not temp;
end if;
int_result := 0;
for index in vec'range loop -- sign bit of temp = '0'
int_result := int_result * 2 + bit'pos(temp(index));
end loop;
if negative then
int_result := (-int_result) - 1;
end if;
-- convert to floating point and scale to [-1, +1)
r <= real(int_result) / real(2**15);
end process behavior;
end architecture behavioral;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1514.vhd | 4 | 1772 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1514.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p02n01i01514ent IS
END c08s09b00x00p02n01i01514ent;
ARCHITECTURE c08s09b00x00p02n01i01514arch OF c08s09b00x00p02n01i01514ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
for i in 1 to 5 loop
k := k + 1;
end loop;
assert NOT( k = 5 )
report "***PASSED TEST: c08s09b00x00p02n01i01514"
severity NOTE;
assert ( k = 5 )
report "***FAILED TEST: c08s09b00x00p02n01i01514 - Missing reserved word 'end loop' in a loop statement"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p02n01i01514arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc909.vhd | 4 | 1783 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc909.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s03b00x00p05n01i00909ent IS
END c10s03b00x00p05n01i00909ent;
ARCHITECTURE c10s03b00x00p05n01i00909arch OF c10s03b00x00p05n01i00909ent IS
BEGIN
TESTING: PROCESS
variable QQ : INTEGER;
BEGIN
for I in 1 to 30 loop
null;
end loop;
QQ := I; -- Failure_here
-- error: entity not within the region it is immediately declared
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c10s03b00x00p05n01i00909- Entity is not within the region it is immediately declared in."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s03b00x00p05n01i00909arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/issue1014/tb_record_test.vhdl | 1 | 323 | entity tb_record_test is
end tb_record_test;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_record_test is
signal v : integer;
begin
dut: entity work.record_test
port map (o => v);
process
begin
wait for 1 ns;
assert v = 333 severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug17202/test.vhdl | 3 | 128 | entity test_val is end test_val;
architecture test of test_val is
signal t : time := time'value("123 fs");
begin
end test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc528.vhd | 4 | 3263 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc528.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p03n04i00528ent IS
END c03s03b00x00p03n04i00528ent;
ARCHITECTURE c03s03b00x00p03n04i00528arch OF c03s03b00x00p03n04i00528ent IS
BEGIN
TESTING : PROCESS
type char_ptr is access character;
variable v_char_ptr1: char_ptr := new character'('a');
variable v_char_ptr2: char_ptr;
variable v_char_ptr3: char_ptr := v_char_ptr1;
variable v_char_ptr4: char_ptr := new character'('|');
variable OKtest : integer := 0;
BEGIN
assert v_char_ptr1.all = 'a';
if (v_char_ptr1.all = 'a') then
OKtest := Oktest + 1;
end if;
assert v_char_ptr2 = null;
if (v_char_ptr2 = null) then
OKtest := Oktest + 1;
end if;
assert v_char_ptr3.all = 'a';
if (v_char_ptr3.all = 'a') then
OKtest := Oktest + 1;
end if;
assert v_char_ptr4.all = '|';
if (v_char_ptr4.all = '|') then
OKtest := Oktest + 1;
end if;
v_char_ptr2 := new character'('K');
assert v_char_ptr2.all = 'K';
if (v_char_ptr2.all = 'K') then
OKtest := Oktest + 1;
end if;
assert (v_char_ptr1.all & v_char_ptr3.all) = "aa";
if ((v_char_ptr1.all & v_char_ptr3.all) = "aa") then
OKtest := Oktest + 1;
end if;
assert (v_char_ptr1.all & v_char_ptr2.all) = "aK";
if ((v_char_ptr1.all & v_char_ptr2.all) = "aK") then
OKtest := Oktest + 1;
end if;
assert (v_char_ptr1.all & v_char_ptr4.all) = "a|";
if ((v_char_ptr1.all & v_char_ptr4.all) = "a|") then
OKtest := Oktest + 1;
end if;
assert (v_char_ptr1.all /= v_char_ptr4.all) = true;
if ((v_char_ptr1.all /= v_char_ptr4.all) = true) then
OKtest := Oktest + 1;
end if;
deallocate(v_char_ptr1);
deallocate(v_char_ptr2);
deallocate(v_char_ptr4);
assert NOT(OKtest = 9)
report "***PASSED TEST: c03s03b00x00p03n04i00528"
severity NOTE;
assert (OKtest = 9)
report "***FAILED TEST: c03s03b00x00p03n04i00528 - Character type using as base for access type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p03n04i00528arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc511.vhd | 4 | 1833 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc511.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b02x00p06n03i00511ent IS
END c03s02b02x00p06n03i00511ent;
ARCHITECTURE c03s02b02x00p06n03i00511arch OF c03s02b02x00p06n03i00511ent IS
type R1 is record
RE1: I1;
RE2: RE1; -- Failure_here
-- ERROR - SEMANTIC ERROR: NAME OF RECORD ELEMENT CANNOT BE USED
-- WITHIN THE RECORD TYPE DEFINITION
end record;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b02x00p06n03i00511 - Name of record element cannot be used in the record type definition."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b02x00p06n03i00511arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/idct.d/mul_605.vhd | 2 | 503 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_605 is
port (
result : out std_logic_vector(30 downto 0);
in_a : in std_logic_vector(30 downto 0);
in_b : in std_logic_vector(14 downto 0)
);
end mul_605;
architecture augh of mul_605 is
signal tmp_res : signed(45 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
result <= std_logic_vector(tmp_res(30 downto 0));
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2292.vhd | 4 | 4155 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2292.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p32n01i02292ent IS
END c07s02b06x00p32n01i02292ent;
ARCHITECTURE c07s02b06x00p32n01i02292arch OF c07s02b06x00p32n01i02292ent IS
BEGIN
TESTING: PROCESS
-- user defined physical types.
type DISTANCE is range 0 to 1E9
units
-- Base units.
A; -- angstrom
-- Metric lengths.
nm = 10 A; -- nanometer
um = 1000 nm; -- micrometer (or micron)
mm = 1000 um; -- millimeter
cm = 10 mm; -- centimeter
-- English lengths.
mil = 254000 A; -- mil
inch = 1000 mil; -- inch
end units;
BEGIN
wait for 5 ns;
assert ((1 A * 10.0) > 1 A)
report "Assertion error.(1)";
assert ((1 nm * 1000.0) > 1 nm)
report "Assertion error.(2)";
assert ((1 um * 1000.0) > 1 um)
report "Assertion error.(3)";
assert ((1 mm * 10.0) > 1 mm)
report "Assertion error.(4)";
assert ((10.0 * 1 A) > 1 A)
report "Assertion error.(6)";
assert ((1000.0 * 1 nm) > 1 nm)
report "Assertion error.(7)";
assert ((1000.0 * 1 um) > 1 um)
report "Assertion error.(8)";
assert ((10.0 * 1 mm) > 1 mm)
report "Assertion error.(9)";
assert ((1 A * 254000.0) > 1 A)
report "Assertion error.(16)";
assert ((1 mil * 1000.0) > 1 mil)
report "Assertion error.(17)";
assert ((254000.0 * 1 A) > 1 A)
report "Assertion error.(20)";
assert ((1000.0 * 1 mil) > 1 mil)
report "Assertion error.(21)";
assert NOT( ((1 A * 10.0) > 1 A) and
((1 nm * 1000.0) > 1 nm)and
((1 um * 1000.0) > 1 um)and
((1 mm * 10.0) > 1 mm) and
((10.0 * 1 A) > 1 A) and
((1000.0 * 1 nm) > 1 nm)and
((1000.0 * 1 um) > 1 um)and
((10.0 * 1 mm) > 1 mm) and
((1 A * 254000.0) > 1 A) and
((1 mil * 1000.0) > 1 mil) and
((254000.0 * 1 A) > 1 A) and
((1000.0 * 1 mil) > 1 mil) )
report "***PASSED TEST: c07s02b06x00p32n01i02292"
severity NOTE;
assert ( ((1 A * 10.0) > 1 A) and
((1 nm * 1000.0) > 1 nm)and
((1 um * 1000.0) > 1 um)and
((1 mm * 10.0) > 1 mm) and
((10.0 * 1 A) > 1 A) and
((1000.0 * 1 nm) > 1 nm)and
((1000.0 * 1 um) > 1 um)and
((10.0 * 1 mm) > 1 mm) and
((1 A * 254000.0) > 1 A) and
((1 mil * 1000.0) > 1 mil) and
((254000.0 * 1 A) > 1 A) and
((1000.0 * 1 mil) > 1 mil) )
report "***FAILED TEST: c07s02b06x00p32n01i02292 - Multiplication of a physical type by an floating point test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p32n01i02292arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug040/mul_215.vhd | 2 | 503 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity mul_215 is
port (
output : out std_logic_vector(40 downto 0);
in_b : in std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0)
);
end mul_215;
architecture augh of mul_215 is
signal tmp_res : signed(63 downto 0);
begin
-- The actual multiplication
tmp_res <= signed(in_a) * signed(in_b);
-- Set the output
output <= std_logic_vector(tmp_res(40 downto 0));
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/components-and-configs/interlock_control_with_estimates.vhd | 4 | 1291 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
configuration interlock_control_with_estimates of interlock_control is
for detailed_timing
end for;
-- . . .
end configuration interlock_control_with_estimates;
--------------------------------------------------
configuration interlock_control_with_actual of interlock_control is
for detailed_timing
for ex_interlock_gate : nor_gate
generic map ( Tpd01 => 320 ps, Tpd10 => 230 ps );
end for;
-- . . .
end for;
end configuration interlock_control_with_actual;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/disputed/tc233.vhd | 4 | 1798 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc233.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p02n01i00233ent IS
END c03s01b02x00p02n01i00233ent;
ARCHITECTURE c03s01b02x00p02n01i00233arch OF c03s01b02x00p02n01i00233ent IS
type a is range (1 ns/1 fs) downto (1 fs/1 fs);
BEGIN
TESTING: PROCESS
variable k : a := 3;
BEGIN
k := 5;
assert NOT(k=5)
report "***PASSED TEST: c03s01b02x00p02n01i00233"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c03s01b02x00p02n01i00233 - The right bound in the range constraint is not a locally static expression of type integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p02n01i00233arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc352.vhd | 4 | 1668 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc352.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p02n01i00352ent IS
END c03s02b01x01p02n01i00352ent;
ARCHITECTURE c03s02b01x01p02n01i00352arch OF c03s02b01x01p02n01i00352ent IS
type bit_vctor is array (0 to 'B') of integer; --Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p02n01i00352 - Both bounds in the constrained array definition must have the same discrete type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p02n01i00352arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue209/main.vhdl | 2 | 380 | library work;
use work.all;
package ShiftReg is
procedure main(new_sample: integer);
end package;
package body ShiftReg is
procedure main(new_sample: integer) is
variable dummy: Util.integer_list_t(0 to 3); -- Here i use the type
begin
dummy := new_sample & dummy(0 to dummy'high-1); -- Error about missing &
end procedure;
end package body;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue2/sortnet_BitonicSort_tb.vhdl | 2 | 3680 | -- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Testbench: Sorting Network: Bitonic-Sort
--
-- Description:
-- ------------------------------------
-- TODO
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.packages.all;
entity sortnet_BitonicSort_tb is
end entity;
architecture tb of sortnet_BitonicSort_tb is
constant INPUTS : POSITIVE := 8;
constant KEY_BITS : POSITIVE := 8;
constant DATA_BITS : POSITIVE := 8;
subtype T_KEY is STD_LOGIC_VECTOR(KEY_BITS - 1 downto 0);
type T_KEY_VECTOR is array(NATURAL range <>) of T_KEY;
function to_kv(slm : T_SLM) return T_KEY_VECTOR is
variable Result : T_KEY_VECTOR(slm'range(1));
begin
for i in slm'high(1) downto slm'low(1) loop
for j in slm'high(2) downto slm'low(2) loop
Result(i)(j) := slm(i, j);
end loop;
end loop;
return Result;
end function;
function to_slm(kv : T_KEY_VECTOR) return T_SLM is
variable Result : T_SLM(kv'range, T_KEY'range);
begin
for i in kv'range loop
for j in T_KEY'range loop
Result(i, j) := kv(i)(j);
end loop;
end loop;
return Result;
end function;
constant CLOCK_PERIOD : TIME := 10 ns;
signal Clock : STD_LOGIC := '1';
signal KeyInputVector : T_KEY_VECTOR(INPUTS - 1 downto 0) := (others => (others => '0'));
signal DataInputMatrix : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0);
signal DataOutputMatrix : T_SLM(INPUTS - 1 downto 0, DATA_BITS - 1 downto 0);
signal KeyOutputVector : T_KEY_VECTOR(INPUTS - 1 downto 0);
signal StopSimulation : STD_LOGIC := '0';
begin
Clock <= Clock xnor StopSimulation after CLOCK_PERIOD;
process
begin
wait until rising_edge(Clock);
for i in 0 to 63 loop
wait until rising_edge(Clock);
for j in 0 to INPUTS - 1 loop
KeyInputVector(j) <= std_logic_vector(unsigned(KeyInputVector(j)) + i + j);
end loop;
end loop;
for i in 0 to 7 loop
wait until rising_edge(Clock);
end loop;
StopSimulation <= '1';
wait;
end process;
DataInputMatrix <= to_slm(KeyInputVector);
sort : entity work.sortnet_BitonicSort
generic map (
INPUTS => INPUTS,
KEY_BITS => KEY_BITS,
DATA_BITS => DATA_BITS
)
port map (
Clock => Clock,
Reset => '0',
DataInputs => DataInputMatrix,
DataOutputs => DataOutputMatrix
);
KeyOutputVector <= to_kv(DataOutputMatrix);
process
begin
wait;
end process;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2935.vhd | 4 | 1833 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2935.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s02b00x00p07n03i02935pkg is
procedure proc1 (i,l:integer; res: boolean);
end c02s02b00x00p07n03i02935pkg;
package body c02s02b00x00p07n03i02935pkg is
--ERROR : non-existent body for procedure proc1
end c02s02b00x00p07n03i02935pkg;
ENTITY c02s02b00x00p07n03i02935ent IS
END c02s02b00x00p07n03i02935ent;
ARCHITECTURE c02s02b00x00p07n03i02935arch OF c02s02b00x00p07n03i02935ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p07n03i02935 - Every subprogram declaration has to have a corresponding body."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p07n03i02935arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_14_fg_14_05.vhd | 4 | 5541 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_14_fg_14_05.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
entity master_slave_flipflop is
port ( phi1, phi2 : in std_logic;
d : in std_logic;
q : out std_logic );
end entity master_slave_flipflop;
architecture behavioral of master_slave_flipflop is
signal master_d : std_logic;
begin
master_d <= d when phi1 = '1';
q <= master_d when phi2 = '1';
end architecture behavioral;
-- code from book
library ieee; use ieee.std_logic_1164.all;
entity shift_reg is
port ( phi1, phi2 : in std_logic;
serial_data_in : in std_logic;
parallel_data : inout std_logic_vector );
end entity shift_reg;
--------------------------------------------------
architecture cell_level of shift_reg is
alias normalized_parallel_data :
std_logic_vector(0 to parallel_data'length - 1)
is parallel_data;
component master_slave_flipflop is
port ( phi1, phi2 : in std_logic;
d : in std_logic;
q : out std_logic );
end component master_slave_flipflop;
begin
reg_array : for index in normalized_parallel_data'range generate
begin
first_cell : if index = 0 generate
begin
cell : component master_slave_flipflop
port map ( phi1, phi2,
d => serial_data_in,
q => normalized_parallel_data(index) );
end generate first_cell;
other_cell : if index /= 0 generate
begin
cell : component master_slave_flipflop
port map ( phi1, phi2,
d => normalized_parallel_data(index - 1),
q => normalized_parallel_data(index) );
end generate other_cell;
end generate reg_array;
end architecture cell_level;
-- end code from book
library ieee; use ieee.std_logic_1164.all;
entity fg_14_05 is
end entity fg_14_05;
architecture test of fg_14_05 is
signal phi1, phi2, serial_data_in : std_logic := '0';
signal parallel_data : std_logic_vector(3 downto 0);
begin
dut : entity work.shift_reg(cell_level)
port map ( phi1 => phi1, phi2 => phi2,
serial_data_in => serial_data_in,
parallel_data => parallel_data );
clock_gen : process is
begin
phi1 <= '1', '0' after 4 ns;
phi2 <= '1' after 5 ns, '0' after 9 ns;
wait for 10 ns;
end process clock_gen;
stimulus : process is
begin
serial_data_in <= '0'; wait until phi2 = '1';
serial_data_in <= '1'; wait until phi2 = '1';
serial_data_in <= '1'; wait until phi2 = '1';
serial_data_in <= '0'; wait until phi2 = '1';
serial_data_in <= '1'; wait until phi2 = '1';
serial_data_in <= '1'; wait until phi2 = '1';
serial_data_in <= '0'; wait until phi2 = '1';
serial_data_in <= '1'; wait until phi2 = '1';
serial_data_in <= '1'; wait until phi2 = '1';
serial_data_in <= '0'; wait until phi2 = '1';
serial_data_in <= '1'; wait until phi2 = '1';
serial_data_in <= '1'; wait until phi2 = '1';
serial_data_in <= '0'; wait until phi2 = '1';
serial_data_in <= '1'; wait until phi2 = '1';
serial_data_in <= '1'; wait until phi2 = '1';
serial_data_in <= '0';
wait;
end process stimulus;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_21_ch_21_01.vhd | 4 | 1470 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_21_ch_21_01.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity ch_21_01 is
end entity ch_21_01;
----------------------------------------------------------------
architecture test of ch_21_01 is
type std_ulogic is (t1, t2, t3);
subtype std_logic is std_ulogic;
-- code from book:
type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
type std_logic_vector is array ( natural range <>) of std_logic;
-- end of code from book
begin
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1393.vhd | 4 | 2019 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1393.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p04n01i01393ent IS
END c08s05b00x00p04n01i01393ent;
ARCHITECTURE c08s05b00x00p04n01i01393arch OF c08s05b00x00p04n01i01393ent IS
BEGIN
TESTING: PROCESS
type RT is
record
a : CHARACTER;
b : CHARACTER;
end record;
variable v1, v2 : CHARACTER := NUL;
variable rv : RT := ('1', '2');
BEGIN
assert v1 = NUL;
assert v2 = NUL;
(v1, v2) := rv;
assert v1 = '1';
assert v2 = '2';
wait for 1 ns;
assert NOT( v1 = '1' and v2 = '2' )
report "***PASSED TEST: c08s05b00x00p04n01i01393"
severity NOTE;
assert ( v1 = '1' and v2 = '2' )
report "***FAILED TEST: c08s05b00x00p04n01i01393 - Aggregate (record type) assignment for variable test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p04n01i01393arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/dff02/tb_dff05.vhdl | 1 | 838 | entity tb_dff05 is
end tb_dff05;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff05 is
signal clk : std_logic;
signal din : std_logic_vector (7 downto 0);
signal dout : std_logic_vector (7 downto 0);
begin
dut: entity work.dff05
port map (
q => dout,
d => din,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
din <= b"1_00000_00";
pulse;
assert dout (0) = '0' severity failure;
din <= b"0_00001_00";
pulse;
assert dout (2) = '1' severity failure;
din <= b"0_00000_01";
pulse;
assert dout (2) = '0' severity failure;
din <= b"1_00000_01";
pulse;
assert dout (0) = '1' severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2954.vhd | 4 | 1938 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2954.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p02n01i02954ent IS
procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer);
procedure is --- Failure_here ; Missing subprogram specification
begin
assert (I1 /= '1')
report "No failure on test" ;
assert (I3 /= 5)
report "No failure on test" ;
end;
END c02s02b00x00p02n01i02954ent;
ARCHITECTURE c02s02b00x00p02n01i02954arch OF c02s02b00x00p02n01i02954ent IS
signal S1 : Bit := '1';
signal S2 : Integer := 5;
signal S3 : Bit;
BEGIN
TESTING: PROCESS
BEGIN
PX(S1,S3,S2);
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c02s02b00x00p02n01i02954 - Missing subprogram specification."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p02n01i02954arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1844.vhd | 4 | 1884 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1844.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01844ent IS
type small_int is range 0 to 7;
END c07s01b00x00p08n01i01844ent;
ARCHITECTURE c07s01b00x00p08n01i01844arch OF c07s01b00x00p08n01i01844ent IS
signal s_int : small_int := 0;
BEGIN
sig : s_int <= 5 after 5 ns;
TESTING : PROCESS
BEGIN
assert s_int > sig -- signal assignment label illegal here
report "signal assignment label accepted as primary in a condition."
severity note ;
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01844 - Signal assignment lables are not permitted as primaries in a condition expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01844arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_20_fg_20_06.vhd | 4 | 2191 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_20_fg_20_06.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
package mem_pkg is
subtype word is bit_vector(0 to 31);
type word_array is array (natural range <>) of word;
procedure load_array ( words : out word_array; file_name : string );
end package mem_pkg;
package body mem_pkg is
procedure load_array ( words : out word_array; file_name : string ) is
-- words'path_name = ":project:mem_pkg:load_array:words"
use std.textio.all;
file load_file : text open read_mode is file_name;
-- load_file'path_name = ":project:mem_pkg:load_array:load_file"
procedure read_line is
-- read_line'path_name = ":project:mem_pkg:load_array:read_line:"
variable current_line : line;
-- current_line'path_name =
-- ":project:mem_pkg:load_array:read_line:current_line"
begin
-- . . .
-- not in book
report current_line'path_name;
-- end not in book
end procedure read_line;
begin -- load_array
-- . . .
-- not in book
report mem_pkg'path_name;
report words'path_name;
report load_file'path_name;
report read_line'path_name;
read_line;
-- end not in book
end procedure load_array;
end package body mem_pkg;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1614.vhd | 4 | 2134 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1614.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p01n01i01614ent IS
END c08s12b00x00p01n01i01614ent;
ARCHITECTURE c08s12b00x00p01n01i01614arch OF c08s12b00x00p01n01i01614ent IS
--
-- Nested procedures to test return statement.
--
procedure two ( variable val : inout integer ) is
procedure one ( variable val : out integer ) is
begin
val := 1;
return;
val := 2; -- should never get here
end one;
begin
one(val);
val := val * 2;
return;
val := val * 2; -- should never get here
end two;
BEGIN
TESTING : PROCESS
variable v1 : integer;
BEGIN
two (v1);
assert NOT( v1=2 )
report "***PASSED TEST: c08s12b00x00p01n01i01614"
severity NOTE;
assert ( v1=2 )
report "***FAILED TEST: c08s12b00x00p01n01i01614 - Return statement applies to the innermost enclosing function."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p01n01i01614arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2880.vhd | 4 | 2086 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2880.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b00x00p07n01i02880ent IS
procedure proc1(constant flag:in integer; variable ret:inout integer);
procedure proc1(constant flag:in integer; variable ret:inout integer) is
begin
if (flag = 0) then
ret:= -1;
else
proc1((flag-1),ret);
end if;
ret:= ret + 1;
end proc1;
END c02s01b00x00p07n01i02880ent;
ARCHITECTURE c02s01b00x00p07n01i02880arch OF c02s01b00x00p07n01i02880ent IS
BEGIN
TESTING: PROCESS
variable x:integer;
BEGIN
x:=99;
assert (x=99) report "Initialization of integer variables incorrect"
severity failure;
proc1(3,x);
assert NOT( x=3 )
report "***PASSED TEST: c02s01b00x00p07n01i02880"
severity NOTE;
assert ( x=3 )
report "***FAILED TEST: c02s01b00x00p07n01i02880 - Procedure resursion call test incorrect."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b00x00p07n01i02880arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc370.vhd | 4 | 1846 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc370.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x01p03n02i00370ent IS
END c03s02b01x01p03n02i00370ent;
ARCHITECTURE c03s02b01x01p03n02i00370arch OF c03s02b01x01p03n02i00370ent IS
subtype BFALSE is BOOLEAN range FALSE to FALSE;
type ONETWO is range 1 to 2;
type A3 is array (1 to 2,
ONETWO range <>) of BFALSE; -- Failure_here
-- ERROR - SYNTAX ERROR: CONSTRAINED AND UNCONSTRAINED INDEX RANGES
-- CANNOT BE MIXED
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b01x01p03n02i00370 - Unconstrained and constrained index ranges cannot be mixed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p03n02i00370arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1695.vhd | 4 | 1741 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1695.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s02b00x00p03n01i01695ent IS
END c09s02b00x00p03n01i01695ent;
ARCHITECTURE c09s02b00x00p03n01i01695arch OF c09s02b00x00p03n01i01695ent IS
BEGIN
TEST_PROCESS: process
-- Illegal Disconnection specification. ERROR:
disconnect all : BIT after 0 ns;
begin
end process TEST_PROCESS;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s02b00x00p03n01i01695 - Disconnection specifications may not be declared inside a process."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s02b00x00p03n01i01695arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue332/irqc_pif.vhd | 1 | 4206 | --========================================================================================================================
-- Copyright (c) 2016 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- VHDL unit : Bitvis IRQC Library : irqc_pif
--
-- Description : See dedicated powerpoint presentation and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.irqc_pif_pkg.all;
entity irqc_pif is
port(
arst : in std_logic;
clk : in std_logic;
-- CPU interface
cs : in std_logic;
addr : in unsigned;
wr : in std_logic;
rd : in std_logic;
din : in std_logic_vector(7 downto 0);
dout : out std_logic_vector(7 downto 0) := (others => '0');
--
p2c : out t_p2c;
c2p : in t_c2p
);
end irqc_pif;
architecture rtl of irqc_pif is
signal p2c_i : t_p2c; -- internal version of output
signal dout_i : std_logic_vector(7 downto 0) := (others => '0');
begin
-- Assigning internally used signals to outputs
p2c <= p2c_i;
p_read_reg : process(cs, addr, rd, c2p, p2c_i)
begin
-- default values
dout_i <= (others => '0');
if cs = '1' and rd = '1' then
case to_integer(addr) is
when C_ADDR_IRR =>
dout_i(C_NUM_SOURCES-1 downto 0) <= c2p.aro_irr;
when C_ADDR_IER =>
dout_i(C_NUM_SOURCES-1 downto 0) <= p2c_i.rw_ier;
when C_ADDR_IPR =>
dout_i(C_NUM_SOURCES-1 downto 0) <= c2p.aro_ipr;
when C_ADDR_IRQ2CPU_ALLOWED =>
dout_i(0) <= c2p.aro_irq2cpu_allowed;
when others =>
null;
end case;
end if;
end process p_read_reg;
dout <= dout_i;
-- Writing to registers that are not functionally manipulated
p_write_reg : process(clk, arst)
begin
if arst = '1' then
p2c_i.rw_ier <= (others => '0');
elsif rising_edge(clk) then
if cs = '1' and wr = '1' then
case to_integer(addr) is
when C_ADDR_IER =>
p2c_i.rw_ier <= din(C_NUM_SOURCES-1 downto 0);
-- Auxiliary write (below)
when others =>
null;
end case;
end if;
end if;
end process p_write_reg;
-- Writing to registers that are functionally manipulated and/or located outside PIF (or dummy registers)
p_aux : process(wr, addr, din)
begin
-- Note that arst is not considered here, but must be considered in any clocked process in the core
-- Default - always to return to these values
p2c_i.awt_icr(C_NUM_SOURCES-1 downto 0) <= (others => '0');
p2c_i.awt_itr(C_NUM_SOURCES-1 downto 0) <= (others => '0');
p2c_i.awt_irq2cpu_ena <= '0';
p2c_i.awt_irq2cpu_disable <= '0';
if (cs = '1' and wr = '1') then
case to_integer(addr) is
when C_ADDR_ITR =>
p2c_i.awt_itr <= din(C_NUM_SOURCES-1 downto 0);
when C_ADDR_ICR =>
p2c_i.awt_icr <= din(C_NUM_SOURCES-1 downto 0);
when C_ADDR_IRQ2CPU_ENA =>
p2c_i.awt_irq2cpu_ena <= din(0);
when C_ADDR_IRQ2CPU_DISABLE =>
p2c_i.awt_irq2cpu_disable <= din(0);
when others =>
null;
end case;
end if;
end process p_aux;
end rtl;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1914.vhd | 4 | 1751 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1914.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n01i01914ent IS
END c07s02b01x00p01n01i01914ent;
ARCHITECTURE c07s02b01x00p01n01i01914arch OF c07s02b01x00p01n01i01914ent IS
BEGIN
TESTING: PROCESS
variable b1 : bit := '0';
BEGIN
b1 := not b1;
assert NOT(b1 = '1')
report "***PASSED TEST: c07s02b01x00p01n01i01914"
severity NOTE;
assert (b1 = '1')
report "***FAILED TEST: c07s02b01x00p01n01i01914 - Logical operators defined only for predefined types BIT and BOOLEAN."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n01i01914arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_02_tb_02_01.vhd | 4 | 1068 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_02_tb_02_01.vhd,v 1.1.1.1 2001-08-22 18:20:47 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
entity ent is
end entity ent;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug040/cmp_792.vhd | 2 | 378 | library ieee;
use ieee.std_logic_1164.all;
entity cmp_792 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_792;
architecture augh of cmp_792 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1541.vhd | 4 | 1691 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1541.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p10n01i01541ent IS
END c08s09b00x00p10n01i01541ent;
ARCHITECTURE c08s09b00x00p10n01i01541arch OF c08s09b00x00p10n01i01541ent IS
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
s : for j in 1 to 100 loop
s := 3;
end loop s;
s := 3;
assert FALSE
report "***FAILED TEST: c08s09b00x00p10n01i01541 - The target of the variable assignment statement is not declared"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p10n01i01541arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/subprograms/network_driver.vhd | 4 | 2117 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity network_driver is
end entity network_driver;
architecture test of network_driver is
constant target_host_id : natural := 10;
constant my_host_id : natural := 5;
type pkt_types is (control_pkt, other_pkt);
type pkt_header is record
dest, src : natural;
pkt_type : pkt_types;
seq : natural;
end record;
begin
-- code from book
network_driver : process is
constant seq_modulo : natural := 2**5;
subtype seq_number is natural range 0 to seq_modulo-1;
variable next_seq_number : seq_number := 0;
-- . . .
-- not in book
variable new_header : pkt_header;
-- end not in book
impure function generate_seq_number return seq_number is
variable number : seq_number;
begin
number := next_seq_number;
next_seq_number := (next_seq_number + 1) mod seq_modulo;
return number;
end function generate_seq_number;
begin -- network_driver
-- not in book
wait for 10 ns;
-- end not in book
-- . . .
new_header := pkt_header'( dest => target_host_id,
src => my_host_id,
pkt_type => control_pkt,
seq => generate_seq_number );
-- . . .
end process network_driver;
-- end code from book
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc825.vhd | 4 | 1661 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc825.vhd,v 1.2 2001-10-26 16:30:28 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s02b02x00p02n01i00825ent IS
END c01s02b02x00p02n01i00825ent;
ARCHITECTURE c01s02b02x00p02n01i00825arch OF c01s02b02x00p02n01i00825ent IS
BEGIN
exit; -- illegal location for exit statement
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s02b02x00p02n01i00825 - Architecture statement can only have concurrent statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s02b02x00p02n01i00825arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/synth76/tb_dff02.vhdl | 1 | 910 | entity tb_dff02 is
end tb_dff02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff02 is
signal clk : std_logic;
signal din : std_logic;
signal dout : std_logic;
signal en : std_logic := '0';
signal rst : std_logic := '0';
begin
dut: entity work.dff02
port map (
q => dout,
d => din,
en => en,
rst => rst,
clk => clk);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
din <= '0';
pulse;
assert dout = '1' severity failure;
en <= '1';
pulse;
assert dout = '0' severity failure;
en <= '1';
rst <= '1';
wait for 1 ns;
assert dout = '1' severity failure;
pulse;
assert dout = '1' severity failure;
rst <= '0';
pulse;
assert dout = '0' severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_08_ch_08_05.vhd | 4 | 1938 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_08_ch_08_05.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- code from book:
library std, work; use std.standard.all;
-- end of code from book
entity ch_08_05 is
end entity ch_08_05;
----------------------------------------------------------------
architecture test of ch_08_05 is
begin
process_08_4_a : process is
constant a : integer := 10;
constant b : integer := 20;
variable result : boolean;
begin
-- code from book:
result := std.standard."<" ( a, b );
-- end of code from book
wait;
end process process_08_4_a;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2879.vhd | 4 | 2080 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2879.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b00x00p07n01i02879ent IS
function func1(constant flag:in integer) return integer;
function func1(constant flag:in integer) return integer is
variable v1 : integer;
begin
if (flag = 0) then
return 0;
else
return ((func1(flag-1)) + 1);
end if;
end func1;
END c02s01b00x00p07n01i02879ent;
ARCHITECTURE c02s01b00x00p07n01i02879arch OF c02s01b00x00p07n01i02879ent IS
BEGIN
TESTING: PROCESS
variable x:integer;
BEGIN
x:=99;
assert (x=99) report "Initialization of integer variables incorrect"
severity failure;
x:= func1(3);
assert NOT( x=3 )
report "***PASSED TEST: c02s01b00x00p07n01i02879"
severity NOTE;
assert ( x=3 )
report "***FAILED TEST: c02s01b00x00p07n01i02879 - Functions resursion call test incorrect."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b00x00p07n01i02879arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2294.vhd | 4 | 2077 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2294.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p32n01i02294ent IS
END c07s02b06x00p32n01i02294ent;
ARCHITECTURE c07s02b06x00p32n01i02294arch OF c07s02b06x00p32n01i02294ent IS
BEGIN
TESTING: PROCESS
BEGIN
-- Test the predefined type TIME in this respect.
assert ((1 min * 60.0) > 1 min)
report "Assertion error.(34)";
assert ((60.0 * 1 min) > 1 min)
report "Assertion error.(41)";
wait for 5 ms;
assert NOT( ((1 min * 60.0) > 1 min) and
((60.0 * 1 min) > 1 min) )
report "***PASSED TEST: c07s02b06x00p32n01i02294"
severity NOTE;
assert ( ((1 min * 60.0) > 1 min) and
((60.0 * 1 min) > 1 min) )
report "***FAILED TEST: c07s02b06x00p32n01i02294 - Multiplication of a predefined physical type by an floating point test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p32n01i02294arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1075.vhd | 4 | 2265 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1075.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n02i01075ent IS
END c06s04b00x00p03n02i01075ent;
ARCHITECTURE c06s04b00x00p03n02i01075arch OF c06s04b00x00p03n02i01075ent IS
BEGIN
TESTING: PROCESS
type CSTRING is array (CHARACTER range <>) of CHARACTER;
constant C1 : CSTRING('A' to 'H') := "BCDEFGHA";
constant C2 : CSTRING('A' to 'H') := "CDEFGHAB";
constant C3 : CSTRING('A' to 'H') := "DEFGHABC";
variable V1 : CHARACTER;
variable V2 : CHARACTER;
variable V3 : CHARACTER;
BEGIN
V1 := C1('A'); -- A -> B
assert V1 = 'B';
V2 := C2(C1('A')); -- A -> B -> D
assert V2 = 'D';
V3 := C3(C2(C1('A'))); -- A -> B -> H
assert V3 = 'G';
wait for 5 ns;
assert NOT( V1 = 'B' and V2 = 'D' and V3 = 'G' )
report "***PASSED TEST: c06s04b00x00p03n02i01075"
severity NOTE;
assert ( V1 = 'B' and V2 = 'D' and V3 = 'G' )
report "***FAILED TEST: c06s04b00x00p03n02i01075 - The expresion for index name check test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n02i01075arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2439.vhd | 3 | 6443 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2439.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p01n01i02439ent IS
END c07s03b02x02p01n01i02439ent;
ARCHITECTURE c07s03b02x02p01n01i02439arch OF c07s03b02x02p01n01i02439ent IS
BEGIN
TESTING: PROCESS
-- Range types are all predefined enumerated types.
type CHAR_ARR is ARRAY( CHARACTER ) of BIT;
type BIT_ARR is ARRAY( BIT ) of BIT;
type BOOL_ARR is ARRAY( BOOLEAN ) of BIT;
type SEV_ARR is ARRAY( SEVERITY_LEVEL ) of BIT;
-- Declare variables of these types.
variable CHARV : CHAR_ARR;
variable BITV : BIT_ARR;
variable BOOLV : BOOL_ARR;
variable SEVV : SEV_ARR;
variable OKtest: integer := 0;
BEGIN
-- Assign each of these arrays using aggregates.
-- 1. Individual aggregates.
CHARV := CHAR_ARR'( 'a' => '1', 'b' => '0', NUL to '`' => '1',
'c' to character'high => '1' );
for C in CHARACTER loop
if (C = 'a') then
assert( CHARV( C ) = '1' );
if NOT( CHARV( C ) = '1' ) then
OKtest := 1;
end if;
elsif (C = 'b') then
assert( CHARV( C ) = '0' );
if NOT( CHARV( C ) = '0' ) then
OKtest := 1;
end if;
else
assert( CHARV( C ) = '1' );
if NOT( CHARV( C ) = '1' ) then
OKtest := 1;
end if;
end if;
end loop;
BITV := BIT_ARR'( '0' => '0', '1' => '1' );
assert( BITV( '0' ) = '0' );
if NOT( BITV( '0' ) = '0' ) then
OKtest := 1;
end if;
assert( BITV( '1' ) = '1' );
if NOT( BITV( '1' ) = '1' ) then
OKtest := 1;
end if;
BOOLV := BOOL_ARR'( FALSE => '0', TRUE => '1' );
assert( BOOLV( FALSE ) = '0' );
if NOT( BOOLV( FALSE ) = '0' ) then
OKtest := 1;
end if;
assert( BOOLV( TRUE ) = '1' );
if NOT( BOOLV( TRUE ) = '1' ) then
OKtest := 1;
end if;
SEVV := SEV_ARR'( NOTE => '0', WARNING => '1', ERROR => '0',
FAILURE => '1' );
assert( SEVV( NOTE ) = '0' );
assert( SEVV( WARNING ) = '1' );
assert( SEVV( ERROR ) = '0' );
assert( SEVV( FAILURE ) = '1' );
if NOT((SEVV(NOTE)='0')and(SEVV(WARNING) ='1')and(SEVV(ERROR)='0')and(SEVV(FAILURE)='1')) then
OKtest := 1;
end if;
-- 2. Groups of aggregates.
CHARV := CHAR_ARR'( 'a' | 'b' => '1', NUL to '`' => '0',
'c' to character'high => '0' );
for C in CHARACTER loop
if (C = 'a') then
assert( CHARV( C ) = '1' );
if NOT( CHARV( C ) = '1' ) then
OKtest := 1;
end if;
elsif (C = 'b') then
assert( CHARV( C ) = '1' );
if NOT( CHARV( C ) = '1' ) then
OKtest := 1;
end if;
else
assert( CHARV( C ) = '0' );
if NOT( CHARV( C ) = '0' ) then
OKtest := 1;
end if;
end if;
end loop;
BITV := BIT_ARR'( '0' | '1' => '0' );
assert( BITV( '0' ) = '0' );
assert( BITV( '1' ) = '0' );
if NOT((BITV('0')='0') and (BITV('1')='0')) then
OKtest := 1;
end if;
BOOLV := BOOL_ARR'( FALSE | TRUE => '1' );
assert( BOOLV( FALSE ) = '1' );
assert( BOOLV( TRUE ) = '1' );
if NOT((BOOLV(FALSE)='1') and (BOOLV(TRUE)='1')) then
OKtest := 1;
end if;
SEVV := SEV_ARR'( NOTE | ERROR => '0', WARNING | FAILURE => '1' );
assert( SEVV( NOTE ) = '0' );
assert( SEVV( WARNING ) = '1' );
assert( SEVV( ERROR ) = '0' );
assert( SEVV( FAILURE ) = '1' );
if NOT((SEVV(NOTE)='0')and(SEVV(WARNING) ='1')and(SEVV(ERROR)='0')and(SEVV(FAILURE)='1')) then
OKtest := 1;
end if;
-- 3. Use of 'others' in these aggregates.
CHARV := CHAR_ARR'( 'a' | 'b' => '0', others => '1' );
for C in CHARACTER loop
if (C = 'a') then
assert( CHARV( C ) = '0' );
if NOT( CHARV( C ) = '0' ) then
OKtest := 1;
end if;
elsif (C = 'b') then
assert( CHARV( C ) = '0' );
if NOT( CHARV( C ) = '0' ) then
OKtest := 1;
end if;
else
assert( CHARV( C ) = '1' );
if NOT( CHARV( C ) = '1' ) then
OKtest := 1;
end if;
end if;
end loop;
BITV := BIT_ARR'( others => '1' );
assert( BITV( '0' ) = '1' );
assert( BITV( '1' ) = '1' );
if NOT(( BITV( '0' ) = '1' )and( BITV( '1' ) = '1' ))then
OKtest := 1;
end if;
BOOLV := BOOL_ARR'( FALSE => '1', others => '0' );
assert( BOOLV( FALSE ) = '1' );
assert( BOOLV( TRUE ) = '0' );
if NOT(( BOOLV( FALSE ) = '1' )and( BOOLV( TRUE ) = '0' ))then
OKtest := 1;
end if;
SEVV := SEV_ARR'( NOTE | ERROR => '0', others => '1' );
assert( SEVV( NOTE ) = '0' );
assert( SEVV( WARNING ) = '1' );
assert( SEVV( ERROR ) = '0' );
assert( SEVV( FAILURE ) = '1' );
if NOT((SEVV(NOTE)='0')and(SEVV(WARNING) ='1')and(SEVV(ERROR)='0')and(SEVV(FAILURE)='1')) then
OKtest := 1;
end if;
wait for 5 ns;
assert NOT(OKtest = 0)
report "***PASSED TEST: c07s03b02x02p01n01i02439"
severity NOTE;
assert (OKtest = 0)
report "***FAILED TEST: c07s03b02x02p01n01i02439 - Aggregates with different range types test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p01n01i02439arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2331.vhd | 4 | 1762 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2331.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p02n02i02331ent IS
END c07s02b07x00p02n02i02331ent;
ARCHITECTURE c07s02b07x00p02n02i02331arch OF c07s02b07x00p02n02i02331ent IS
BEGIN
TESTING: PROCESS
type NEW_INT is range INTEGER'LOW to INTEGER'HIGH;
variable k : NEW_INT := 5;
BEGIN
k := 2 ** 2;
assert NOT(k=4)
report "***PASSED TEST: c07s02b07x00p02n02i02331"
severity NOTE;
assert (k=4)
report "***FAILED TEST: c07s02b07x00p02n02i02331 - Exponent can only be of type Integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p02n02i02331arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc972.vhd | 4 | 2047 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc972.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p05n01i00972ent IS
END c06s03b00x00p05n01i00972ent;
ARCHITECTURE c06s03b00x00p05n01i00972arch OF c06s03b00x00p05n01i00972ent IS
BEGIN
TESTING: PROCESS
type R1 is record
RE1: BOOLEAN;
RE2: INTEGER;
RE3: BIT;
RE4: SEVERITY_LEVEL;
RE5: REAL;
RE6: CHARACTER;
RE7: TIME;
end record;
variable V2 : R1;
BEGIN
V2.RE1 := RE1;
V2.RE2 := RE2;
V2.RE3 := RE3;
V2.RE4 := RE4;
V2.RE5 := RE5;
V2.RE6 := RE6;
V2.RE7 := RE7;
-- ERROR: RECORD ELEMENT NAME CANNOT BE USED BY ITSELF
assert FALSE
report "***FAILED TEST: c06s03b00x00p05n01i00972 - Record element name cannot be used by itself."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p05n01i00972arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1815.vhd | 4 | 1694 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1815.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01815ent IS
END c07s01b00x00p08n01i01815ent;
ARCHITECTURE c07s01b00x00p08n01i01815arch OF c07s01b00x00p08n01i01815ent IS
type small_int is range 0 to 7;
signal sm_int : small_int := 0;
BEGIN
B : block (sm_int = small_int) -- type name illegal
begin
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01815 - Type name are not permitted as primaries in a block guard expression."
severity ERROR;
end block B;
END c07s01b00x00p08n01i01815arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug07/repro.vhdl | 3 | 424 | entity repro is
end repro;
architecture behav of repro is
type int_vector is array (natural range <>) of integer;
constant c1 : int_vector (0 to 1) := 12 & 13;
constant c2 : int_vector (0 to 1) := 14 & 15;
constant p : boolean := c1 = c2;
constant p1 : boolean := c1 < c2;
begin
process
begin
case true is
when p => null;
when true => null;
end case;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug040/p_jinfo_ac_dhuff_tbl_mincode.vhd | 2 | 1457 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity p_jinfo_ac_dhuff_tbl_mincode is
port (
wa0_data : in std_logic_vector(8 downto 0);
wa0_addr : in std_logic_vector(6 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(6 downto 0);
ra0_data : out std_logic_vector(8 downto 0);
wa0_en : in std_logic
);
end p_jinfo_ac_dhuff_tbl_mincode;
architecture augh of p_jinfo_ac_dhuff_tbl_mincode is
-- Embedded RAM
type ram_type is array (0 to 127) of std_logic_vector(8 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/sr2903/boundcheck.vhdl | 3 | 925 | library IEEE;
use IEEE.numeric_std.all;
entity tb is
end tb;
architecture behavioral of tb is
subtype int31 is integer range -2**(31-1) to 2**(31-1)-1;
type array_7_int31 is array(0 to 6) of int31;
function ASR(v : integer; n : natural ; nv : natural; nres : natural) return integer is
variable tmp : signed(nv downto 0);
variable res : signed(nv downto 0);
begin
tmp := resize(to_signed(v,nv),nv+1);
res := shift_right(tmp,n);
return to_integer(res(nres-1 downto 0));
end;
begin
software_emulation : process
variable test : int31;
variable tmp : int31;
begin
report "Start" severity note;
tmp := 5965232;
-- test := test + ASR(((tmp * 119304647) + 268435456),29,57,31);
-- test := test + ASR(((tmp * 178956971) + 268435456),29,57,31);
test := test + ASR(((tmp * 59652324) + 268435456),29,57,31);
end process;
end behavioral;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/case01/case06.vhdl | 1 | 325 | library ieee;
use ieee.std_logic_1164.all;
entity case06 is
port (
a : in std_logic;
b : out std_logic
);
end entity;
architecture a of case06 is
begin
process(a)
begin
case a is
when '0' =>
b <= '0';
when 'L' =>
b <= '1';
when others =>
b <= 'Z';
end case;
end process;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc818.vhd | 4 | 1680 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc818.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s02b01x00p03n01i00818ent IS
END c01s02b01x00p03n01i00818ent;
ARCHITECTURE c01s02b01x00p03n01i00818arch OF c01s02b01x00p03n01i00818ent IS
variable err : boolean := true; -- illegal location for variable declaration
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s02b01x00p03n01i00818 - Variable declaration can not appear in the architecture declaration part."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s02b01x00p03n01i00818arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/access-types/ordered_collection_adt.vhd | 4 | 6074 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package «element_type_simple_name»_ordered_collection_adt is
-- template: fill in the placeholders to specialize for a particular type
alias element_type is «element_type»;
alias key_type is «key_type»;
alias key_of is «key_function» [ element_type return key_type ];
alias "<" is «less_than_function» [ key_type, key_type return boolean ];
-- types provided by the package
type ordered_collection_object; -- private
type position_object; -- private
type ordered_collection is access ordered_collection_object;
type position is access position_object;
-- operations on ordered collections
function new_ordered_collection return ordered_collection;
-- returns an empty ordered collection of element_type values
procedure insert ( c : inout ordered_collection; e : in element_type );
-- inserts e into c in position determined by key_of(e)
procedure get_element ( variable p : in position; e : out element_type );
-- returns the element value at position p in its collection
procedure test_null_position ( variable p : in position; is_null : out boolean );
-- test whether p refers to no position in its collection
procedure search ( variable c : in ordered_collection; k : in key_type;
p : out position );
-- searches for an element with key k in c, and returns the position of
-- that element, or, if not found, a position for which test_null_position
-- returns true
procedure find_first ( variable c : in ordered_collection; p : out position );
-- returns the position of the first element of c
procedure advance ( p : inout position );
-- advances p to the next element in its collection,
-- or if there are no more, sets p so that test_null_position returns true
procedure delete ( p : inout position );
-- deletes the element at position p from its collection, and advances p
-- private types: pretend these are not visible
type ordered_collection_object is
record
element : element_type;
next_element, prev_element : ordered_collection;
end record ordered_collection_object;
type position_object is
record
the_collection : ordered_collection;
current_element : ordered_collection;
end record position_object;
end package «element_type_simple_name»_ordered_collection_adt;
package body «element_type_simple_name»_ordered_collection_adt is
function new_ordered_collection return ordered_collection is
variable result : ordered_collection := new ordered_collection_object;
begin
result.next_element := result;
result.prev_element := result;
return result;
end function new_ordered_collection;
procedure insert ( c : inout ordered_collection; e : in element_type ) is
variable current_element : ordered_collection := c.next_element;
variable new_element : ordered_collection;
begin
while current_element /= c
and key_of(current_element.element) < key_of(e) loop
current_element := current_element.next_element;
end loop;
-- insert new element before current_element
new_element := new ordered_collection_object'(
element => e,
next_element => current_element,
prev_element => current_element.prev_element );
new_element.next_element.prev_element := new_element;
new_element.prev_element.next_element := new_element;
end procedure insert;
procedure get_element ( variable p : in position; e : out element_type ) is
begin
e := p.current_element.element;
end procedure get_element;
procedure test_null_position ( variable p : in position; is_null : out boolean ) is
begin
is_null := p.current_element = p.the_collection;
end procedure test_null_position;
procedure search ( variable c : in ordered_collection; k : in key_type;
p : out position ) is
variable current_element : ordered_collection := c.next_element;
begin
while current_element /= c
and key_of(current_element.element) < k loop
current_element := current_element.next_element;
end loop;
if current_element = c or k < key_of(current_element.element) then
p := new position_object'(c, c); -- null position
else
p := new position_object'(c, current_element);
end if;
end procedure search;
procedure find_first ( variable c : in ordered_collection; p : out position ) is
begin
p := new position_object'(c, c.next_element);
end procedure find_first;
procedure advance ( p : inout position ) is
variable is_null : boolean;
begin
test_null_position(p, is_null);
if not is_null then
p.current_element := p.current_element.next_element;
end if;
end procedure advance;
procedure delete ( p : inout position ) is
variable is_null : boolean;
begin
test_null_position(p, is_null);
if not is_null then
p.current_element.next_element.prev_element
:= p.current_element.prev_element;
p.current_element.prev_element.next_element
:= p.current_element.next_element;
p.current_element := p.current_element.next_element;
end if;
end procedure delete;
end package body «element_type_simple_name»_ordered_collection_adt;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1243.vhd | 4 | 1672 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1243.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p04n01i01243ent IS
END c08s02b00x00p04n01i01243ent;
ARCHITECTURE c08s02b00x00p04n01i01243arch OF c08s02b00x00p04n01i01243ent IS
BEGIN
TESTING: PROCESS
variable N2 : Character := 'R';
BEGIN
assert FALSE
report N2
severity NOTE;
assert FALSE
report "***FAILED TEST: c08s02b00x00p04n01i01243 - Expression type used in a report clause should be STRING"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s02b00x00p04n01i01243arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2629.vhd | 4 | 1587 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2629.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02629ent IS
END c13s03b01x00p02n01i02629ent;
ARCHITECTURE c13s03b01x00p02n01i02629arch OF c13s03b01x00p02n01i02629ent IS
BEGIN
TESTING: PROCESS
variable k'k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02629 - Identifier can not contain '''."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02629arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2047.vhd | 4 | 1671 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2047.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02047ent IS
END c07s02b04x00p01n01i02047ent;
ARCHITECTURE c07s02b04x00p01n01i02047arch OF c07s02b04x00p01n01i02047ent IS
BEGIN
TESTING: PROCESS
variable STRINGV : STRING( 1 to 8 );
BEGIN
STRINGV := STRINGV + "hello, world";
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02047 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02047arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/idct.d/fsm_23.vhd | 2 | 115488 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity fsm_23 is
port (
clock : in std_logic;
reset : in std_logic;
in0 : in std_logic;
out181 : out std_logic;
out182 : out std_logic;
out183 : out std_logic;
out184 : out std_logic;
out185 : out std_logic;
out8 : out std_logic;
out13 : out std_logic;
out14 : out std_logic;
out16 : out std_logic;
out18 : out std_logic;
out19 : out std_logic;
out20 : out std_logic;
out21 : out std_logic;
out22 : out std_logic;
in2 : in std_logic;
out23 : out std_logic;
out24 : out std_logic;
out25 : out std_logic;
out26 : out std_logic;
out27 : out std_logic;
out28 : out std_logic;
out29 : out std_logic;
out30 : out std_logic;
out31 : out std_logic;
out33 : out std_logic;
out35 : out std_logic;
out36 : out std_logic;
out38 : out std_logic;
out40 : out std_logic;
out42 : out std_logic;
in3 : in std_logic;
out44 : out std_logic;
out46 : out std_logic;
out48 : out std_logic;
out49 : out std_logic;
out50 : out std_logic;
out52 : out std_logic;
out54 : out std_logic;
out56 : out std_logic;
out57 : out std_logic;
out58 : out std_logic;
in4 : in std_logic;
out60 : out std_logic;
in5 : in std_logic;
out164 : out std_logic;
out165 : out std_logic;
out167 : out std_logic;
out168 : out std_logic;
out170 : out std_logic;
out171 : out std_logic;
out173 : out std_logic;
out174 : out std_logic;
out176 : out std_logic;
out178 : out std_logic;
out0 : out std_logic;
out1 : out std_logic;
out2 : out std_logic;
in1 : in std_logic;
out4 : out std_logic;
out90 : out std_logic;
out91 : out std_logic;
out97 : out std_logic;
out99 : out std_logic;
out101 : out std_logic;
in6 : in std_logic;
out103 : out std_logic;
out105 : out std_logic;
out106 : out std_logic;
out107 : out std_logic;
out108 : out std_logic;
out135 : out std_logic;
out136 : out std_logic;
out137 : out std_logic;
out138 : out std_logic;
in11 : in std_logic;
out140 : out std_logic;
out141 : out std_logic;
out142 : out std_logic;
out143 : out std_logic;
out145 : out std_logic;
out146 : out std_logic;
out148 : out std_logic;
out150 : out std_logic;
out153 : out std_logic;
out154 : out std_logic;
out155 : out std_logic;
out156 : out std_logic;
out157 : out std_logic;
out158 : out std_logic;
out159 : out std_logic;
out160 : out std_logic;
out161 : out std_logic;
out162 : out std_logic;
out111 : out std_logic;
out112 : out std_logic;
out114 : out std_logic;
out116 : out std_logic;
out118 : out std_logic;
out120 : out std_logic;
out121 : out std_logic;
out122 : out std_logic;
out123 : out std_logic;
out124 : out std_logic;
out125 : out std_logic;
out126 : out std_logic;
in7 : in std_logic;
out129 : out std_logic;
out130 : out std_logic;
in8 : in std_logic;
out131 : out std_logic;
in9 : in std_logic;
out132 : out std_logic;
out133 : out std_logic;
out134 : out std_logic;
in10 : in std_logic;
out186 : out std_logic;
out187 : out std_logic;
out190 : out std_logic;
out195 : out std_logic;
out197 : out std_logic;
out198 : out std_logic;
out199 : out std_logic;
out200 : out std_logic;
out201 : out std_logic;
out203 : out std_logic;
out204 : out std_logic;
out206 : out std_logic;
out207 : out std_logic;
out209 : out std_logic;
out210 : out std_logic;
out212 : out std_logic;
out213 : out std_logic;
out215 : out std_logic;
out217 : out std_logic;
out220 : out std_logic;
out221 : out std_logic;
out222 : out std_logic;
out223 : out std_logic;
out224 : out std_logic;
out225 : out std_logic;
out226 : out std_logic;
out227 : out std_logic;
out228 : out std_logic;
out229 : out std_logic;
out231 : out std_logic;
out232 : out std_logic;
out234 : out std_logic;
out235 : out std_logic;
out237 : out std_logic;
out238 : out std_logic;
out240 : out std_logic;
out241 : out std_logic;
out243 : out std_logic;
out245 : out std_logic;
out248 : out std_logic;
out249 : out std_logic;
out250 : out std_logic;
out251 : out std_logic;
out252 : out std_logic;
out253 : out std_logic;
out254 : out std_logic;
out255 : out std_logic;
out256 : out std_logic;
out257 : out std_logic;
out259 : out std_logic;
out260 : out std_logic;
out262 : out std_logic;
out263 : out std_logic;
out265 : out std_logic;
out266 : out std_logic;
out268 : out std_logic;
out269 : out std_logic;
out271 : out std_logic;
out273 : out std_logic;
out276 : out std_logic;
out277 : out std_logic;
out278 : out std_logic;
out279 : out std_logic;
out280 : out std_logic;
out281 : out std_logic;
out282 : out std_logic;
out283 : out std_logic;
out284 : out std_logic;
out285 : out std_logic;
out286 : out std_logic;
out287 : out std_logic;
out288 : out std_logic;
out289 : out std_logic;
out290 : out std_logic;
out291 : out std_logic;
out292 : out std_logic;
out293 : out std_logic;
out294 : out std_logic;
out295 : out std_logic;
out296 : out std_logic;
out297 : out std_logic;
out298 : out std_logic;
out311 : out std_logic;
out312 : out std_logic;
out313 : out std_logic;
out314 : out std_logic;
out315 : out std_logic;
out316 : out std_logic;
out318 : out std_logic;
out321 : out std_logic;
out322 : out std_logic;
out323 : out std_logic;
out324 : out std_logic;
out325 : out std_logic;
out326 : out std_logic;
out327 : out std_logic;
out328 : out std_logic;
out329 : out std_logic;
out333 : out std_logic;
out341 : out std_logic;
out342 : out std_logic;
out343 : out std_logic;
out344 : out std_logic;
out345 : out std_logic;
out346 : out std_logic;
out349 : out std_logic;
out350 : out std_logic;
out351 : out std_logic;
out352 : out std_logic;
out353 : out std_logic;
out354 : out std_logic;
out355 : out std_logic;
out357 : out std_logic;
out361 : out std_logic;
out362 : out std_logic;
out363 : out std_logic;
out364 : out std_logic;
out366 : out std_logic;
out367 : out std_logic;
out371 : out std_logic;
out372 : out std_logic;
out373 : out std_logic;
out382 : out std_logic;
out383 : out std_logic;
out385 : out std_logic;
out393 : out std_logic;
out394 : out std_logic;
out395 : out std_logic;
out396 : out std_logic;
out398 : out std_logic;
out400 : out std_logic;
out401 : out std_logic;
out402 : out std_logic;
out404 : out std_logic;
out406 : out std_logic;
out407 : out std_logic;
out408 : out std_logic;
out409 : out std_logic;
out410 : out std_logic;
out411 : out std_logic;
out412 : out std_logic;
out413 : out std_logic;
out414 : out std_logic;
out416 : out std_logic;
out417 : out std_logic;
out418 : out std_logic;
out419 : out std_logic;
out422 : out std_logic;
out423 : out std_logic;
out425 : out std_logic;
out426 : out std_logic;
out428 : out std_logic;
out429 : out std_logic;
out430 : out std_logic;
out431 : out std_logic;
out433 : out std_logic;
out434 : out std_logic;
out435 : out std_logic;
out436 : out std_logic;
out437 : out std_logic;
out438 : out std_logic;
out440 : out std_logic;
out441 : out std_logic;
out443 : out std_logic;
out444 : out std_logic;
out445 : out std_logic;
out446 : out std_logic;
out447 : out std_logic;
out450 : out std_logic;
out451 : out std_logic;
out454 : out std_logic;
out455 : out std_logic;
out457 : out std_logic;
out458 : out std_logic;
out459 : out std_logic;
out460 : out std_logic;
out461 : out std_logic;
out462 : out std_logic;
out463 : out std_logic;
out464 : out std_logic;
out465 : out std_logic;
out466 : out std_logic;
out467 : out std_logic;
out468 : out std_logic;
out469 : out std_logic;
out472 : out std_logic;
out475 : out std_logic;
out481 : out std_logic;
out482 : out std_logic;
out483 : out std_logic;
out484 : out std_logic;
out487 : out std_logic;
out488 : out std_logic;
out491 : out std_logic;
out495 : out std_logic;
out496 : out std_logic;
out497 : out std_logic;
out498 : out std_logic;
out499 : out std_logic;
out500 : out std_logic;
out501 : out std_logic;
out512 : out std_logic;
out513 : out std_logic;
out517 : out std_logic;
out518 : out std_logic;
out519 : out std_logic;
out521 : out std_logic;
out522 : out std_logic;
out524 : out std_logic;
out525 : out std_logic;
out526 : out std_logic;
out527 : out std_logic;
out528 : out std_logic;
out531 : out std_logic;
out540 : out std_logic;
out542 : out std_logic;
out544 : out std_logic;
out545 : out std_logic;
out554 : out std_logic;
out555 : out std_logic;
out559 : out std_logic;
out560 : out std_logic;
out561 : out std_logic;
out562 : out std_logic;
out563 : out std_logic;
out566 : out std_logic;
out567 : out std_logic;
out570 : out std_logic;
out572 : out std_logic;
out575 : out std_logic;
out577 : out std_logic;
out578 : out std_logic;
out580 : out std_logic;
out581 : out std_logic
);
end fsm_23;
architecture augh of fsm_23 is
signal state_cur : std_logic_vector(0 to 240) := (7 => '1', others => '0');
signal state_next : std_logic_vector(0 to 240) := (7 => '1', others => '0');
-- Buffers for outputs
signal out122_buf : std_logic := '0';
signal out122_bufn : std_logic;
signal out36_buf : std_logic := '0';
signal out36_bufn : std_logic;
signal out49_buf : std_logic := '0';
signal out49_bufn : std_logic;
signal out35_buf : std_logic := '0';
signal out35_bufn : std_logic;
signal out27_buf : std_logic := '0';
signal out27_bufn : std_logic;
signal out16_buf : std_logic := '0';
signal out16_bufn : std_logic;
signal out25_buf : std_logic := '0';
signal out25_bufn : std_logic;
signal out20_buf : std_logic := '0';
signal out20_bufn : std_logic;
signal out57_buf : std_logic := '0';
signal out57_bufn : std_logic;
signal out23_buf : std_logic := '0';
signal out23_bufn : std_logic;
signal out136_buf : std_logic := '0';
signal out136_bufn : std_logic;
signal out0_buf : std_logic := '0';
signal out0_bufn : std_logic;
signal out134_buf : std_logic := '0';
signal out134_bufn : std_logic;
signal out13_buf : std_logic := '0';
signal out13_bufn : std_logic;
signal out131_buf : std_logic := '0';
signal out131_bufn : std_logic;
signal out129_buf : std_logic := '0';
signal out129_bufn : std_logic;
signal out111_buf : std_logic := '0';
signal out111_bufn : std_logic;
signal out31_buf : std_logic := '0';
signal out31_bufn : std_logic;
signal out126_buf : std_logic := '0';
signal out126_bufn : std_logic;
signal out106_buf : std_logic := '0';
signal out106_bufn : std_logic;
signal out124_buf : std_logic := '0';
signal out124_bufn : std_logic;
signal out138_buf : std_logic := '0';
signal out138_bufn : std_logic;
signal out141_buf : std_logic := '0';
signal out141_bufn : std_logic;
signal out143_buf : std_logic := '0';
signal out143_bufn : std_logic;
signal out146_buf : std_logic := '0';
signal out146_bufn : std_logic;
signal out150_buf : std_logic := '0';
signal out150_bufn : std_logic;
signal out153_buf : std_logic := '0';
signal out153_bufn : std_logic;
signal out155_buf : std_logic := '0';
signal out155_bufn : std_logic;
signal out158_buf : std_logic := '0';
signal out158_bufn : std_logic;
signal out162_buf : std_logic := '0';
signal out162_bufn : std_logic;
signal out165_buf : std_logic := '0';
signal out165_bufn : std_logic;
signal out168_buf : std_logic := '0';
signal out168_bufn : std_logic;
signal out171_buf : std_logic := '0';
signal out171_bufn : std_logic;
signal out174_buf : std_logic := '0';
signal out174_bufn : std_logic;
signal out178_buf : std_logic := '0';
signal out178_bufn : std_logic;
signal out181_buf : std_logic := '0';
signal out181_bufn : std_logic;
signal out183_buf : std_logic := '0';
signal out183_bufn : std_logic;
signal out197_buf : std_logic := '0';
signal out197_bufn : std_logic;
signal out201_buf : std_logic := '0';
signal out201_bufn : std_logic;
signal out204_buf : std_logic := '0';
signal out204_bufn : std_logic;
signal out207_buf : std_logic := '0';
signal out207_bufn : std_logic;
signal out210_buf : std_logic := '0';
signal out210_bufn : std_logic;
signal out213_buf : std_logic := '0';
signal out213_bufn : std_logic;
signal out217_buf : std_logic := '0';
signal out217_bufn : std_logic;
signal out220_buf : std_logic := '0';
signal out220_bufn : std_logic;
signal out222_buf : std_logic := '0';
signal out222_bufn : std_logic;
signal out225_buf : std_logic := '0';
signal out225_bufn : std_logic;
signal out229_buf : std_logic := '0';
signal out229_bufn : std_logic;
signal out232_buf : std_logic := '0';
signal out232_bufn : std_logic;
signal out235_buf : std_logic := '0';
signal out235_bufn : std_logic;
signal out238_buf : std_logic := '0';
signal out238_bufn : std_logic;
signal out241_buf : std_logic := '0';
signal out241_bufn : std_logic;
signal out245_buf : std_logic := '0';
signal out245_bufn : std_logic;
signal out248_buf : std_logic := '0';
signal out248_bufn : std_logic;
signal out250_buf : std_logic := '0';
signal out250_bufn : std_logic;
signal out253_buf : std_logic := '0';
signal out253_bufn : std_logic;
signal out257_buf : std_logic := '0';
signal out257_bufn : std_logic;
signal out260_buf : std_logic := '0';
signal out260_bufn : std_logic;
signal out263_buf : std_logic := '0';
signal out263_bufn : std_logic;
signal out266_buf : std_logic := '0';
signal out266_bufn : std_logic;
signal out269_buf : std_logic := '0';
signal out269_bufn : std_logic;
signal out273_buf : std_logic := '0';
signal out273_bufn : std_logic;
signal out276_buf : std_logic := '0';
signal out276_bufn : std_logic;
signal out278_buf : std_logic := '0';
signal out278_bufn : std_logic;
signal out280_buf : std_logic := '0';
signal out280_bufn : std_logic;
signal out281_buf : std_logic := '0';
signal out281_bufn : std_logic;
signal out282_buf : std_logic := '0';
signal out282_bufn : std_logic;
signal out284_buf : std_logic := '0';
signal out284_bufn : std_logic;
signal out285_buf : std_logic := '0';
signal out285_bufn : std_logic;
signal out287_buf : std_logic := '0';
signal out287_bufn : std_logic;
signal out288_buf : std_logic := '0';
signal out288_bufn : std_logic;
signal out289_buf : std_logic := '0';
signal out289_bufn : std_logic;
signal out290_buf : std_logic := '0';
signal out290_bufn : std_logic;
signal out291_buf : std_logic := '0';
signal out291_bufn : std_logic;
signal out292_buf : std_logic := '0';
signal out292_bufn : std_logic;
signal out293_buf : std_logic := '0';
signal out293_bufn : std_logic;
signal out294_buf : std_logic := '0';
signal out294_bufn : std_logic;
signal out295_buf : std_logic := '0';
signal out295_bufn : std_logic;
signal out296_buf : std_logic := '0';
signal out296_bufn : std_logic;
signal out312_buf : std_logic := '0';
signal out312_bufn : std_logic;
signal out313_buf : std_logic := '0';
signal out313_bufn : std_logic;
signal out314_buf : std_logic := '0';
signal out314_bufn : std_logic;
signal out315_buf : std_logic := '0';
signal out315_bufn : std_logic;
signal out318_buf : std_logic := '0';
signal out318_bufn : std_logic;
signal out322_buf : std_logic := '0';
signal out322_bufn : std_logic;
signal out323_buf : std_logic := '0';
signal out323_bufn : std_logic;
signal out324_buf : std_logic := '0';
signal out324_bufn : std_logic;
signal out325_buf : std_logic := '0';
signal out325_bufn : std_logic;
signal out326_buf : std_logic := '0';
signal out326_bufn : std_logic;
signal out327_buf : std_logic := '0';
signal out327_bufn : std_logic;
signal out328_buf : std_logic := '0';
signal out328_bufn : std_logic;
signal out333_buf : std_logic := '0';
signal out333_bufn : std_logic;
signal out341_buf : std_logic := '0';
signal out341_bufn : std_logic;
signal out342_buf : std_logic := '0';
signal out342_bufn : std_logic;
signal out343_buf : std_logic := '0';
signal out343_bufn : std_logic;
signal out344_buf : std_logic := '0';
signal out344_bufn : std_logic;
signal out346_buf : std_logic := '0';
signal out346_bufn : std_logic;
signal out349_buf : std_logic := '0';
signal out349_bufn : std_logic;
signal out351_buf : std_logic := '0';
signal out351_bufn : std_logic;
signal out352_buf : std_logic := '0';
signal out352_bufn : std_logic;
signal out353_buf : std_logic := '0';
signal out353_bufn : std_logic;
signal out354_buf : std_logic := '0';
signal out354_bufn : std_logic;
signal out357_buf : std_logic := '0';
signal out357_bufn : std_logic;
signal out361_buf : std_logic := '0';
signal out361_bufn : std_logic;
signal out364_buf : std_logic := '0';
signal out364_bufn : std_logic;
signal out366_buf : std_logic := '0';
signal out366_bufn : std_logic;
signal out371_buf : std_logic := '0';
signal out371_bufn : std_logic;
signal out393_buf : std_logic := '0';
signal out393_bufn : std_logic;
signal out394_buf : std_logic := '0';
signal out394_bufn : std_logic;
signal out395_buf : std_logic := '0';
signal out395_bufn : std_logic;
signal out400_buf : std_logic := '0';
signal out400_bufn : std_logic;
signal out401_buf : std_logic := '0';
signal out401_bufn : std_logic;
signal out404_buf : std_logic := '0';
signal out404_bufn : std_logic;
signal out407_buf : std_logic := '0';
signal out407_bufn : std_logic;
signal out408_buf : std_logic := '0';
signal out408_bufn : std_logic;
signal out409_buf : std_logic := '0';
signal out409_bufn : std_logic;
signal out410_buf : std_logic := '0';
signal out410_bufn : std_logic;
signal out413_buf : std_logic := '0';
signal out413_bufn : std_logic;
signal out414_buf : std_logic := '0';
signal out414_bufn : std_logic;
signal out417_buf : std_logic := '0';
signal out417_bufn : std_logic;
signal out418_buf : std_logic := '0';
signal out418_bufn : std_logic;
signal out422_buf : std_logic := '0';
signal out422_bufn : std_logic;
signal out426_buf : std_logic := '0';
signal out426_bufn : std_logic;
signal out428_buf : std_logic := '0';
signal out428_bufn : std_logic;
signal out431_buf : std_logic := '0';
signal out431_bufn : std_logic;
signal out433_buf : std_logic := '0';
signal out433_bufn : std_logic;
signal out434_buf : std_logic := '0';
signal out434_bufn : std_logic;
signal out435_buf : std_logic := '0';
signal out435_bufn : std_logic;
signal out436_buf : std_logic := '0';
signal out436_bufn : std_logic;
signal out437_buf : std_logic := '0';
signal out437_bufn : std_logic;
signal out438_buf : std_logic := '0';
signal out438_bufn : std_logic;
signal out440_buf : std_logic := '0';
signal out440_bufn : std_logic;
signal out444_buf : std_logic := '0';
signal out444_bufn : std_logic;
signal out446_buf : std_logic := '0';
signal out446_bufn : std_logic;
signal out451_buf : std_logic := '0';
signal out451_bufn : std_logic;
signal out457_buf : std_logic := '0';
signal out457_bufn : std_logic;
signal out458_buf : std_logic := '0';
signal out458_bufn : std_logic;
signal out459_buf : std_logic := '0';
signal out459_bufn : std_logic;
signal out460_buf : std_logic := '0';
signal out460_bufn : std_logic;
signal out461_buf : std_logic := '0';
signal out461_bufn : std_logic;
signal out463_buf : std_logic := '0';
signal out463_bufn : std_logic;
signal out464_buf : std_logic := '0';
signal out464_bufn : std_logic;
signal out466_buf : std_logic := '0';
signal out466_bufn : std_logic;
signal out468_buf : std_logic := '0';
signal out468_bufn : std_logic;
signal out472_buf : std_logic := '0';
signal out472_bufn : std_logic;
signal out475_buf : std_logic := '0';
signal out475_bufn : std_logic;
signal out481_buf : std_logic := '0';
signal out481_bufn : std_logic;
signal out482_buf : std_logic := '0';
signal out482_bufn : std_logic;
signal out483_buf : std_logic := '0';
signal out483_bufn : std_logic;
signal out487_buf : std_logic := '0';
signal out487_bufn : std_logic;
signal out495_buf : std_logic := '0';
signal out495_bufn : std_logic;
signal out496_buf : std_logic := '0';
signal out496_bufn : std_logic;
signal out497_buf : std_logic := '0';
signal out497_bufn : std_logic;
signal out499_buf : std_logic := '0';
signal out499_bufn : std_logic;
signal out500_buf : std_logic := '0';
signal out500_bufn : std_logic;
signal out512_buf : std_logic := '0';
signal out512_bufn : std_logic;
signal out517_buf : std_logic := '0';
signal out517_bufn : std_logic;
signal out518_buf : std_logic := '0';
signal out518_bufn : std_logic;
signal out521_buf : std_logic := '0';
signal out521_bufn : std_logic;
signal out524_buf : std_logic := '0';
signal out524_bufn : std_logic;
signal out525_buf : std_logic := '0';
signal out525_bufn : std_logic;
signal out526_buf : std_logic := '0';
signal out526_bufn : std_logic;
signal out531_buf : std_logic := '0';
signal out531_bufn : std_logic;
signal out554_buf : std_logic := '0';
signal out554_bufn : std_logic;
signal out562_buf : std_logic := '0';
signal out562_bufn : std_logic;
signal out566_buf : std_logic := '0';
signal out566_bufn : std_logic;
-- Retiming: counters
signal rtmcounter0 : unsigned(4 downto 0) := (others => '0');
signal rtmcounter0_next : unsigned(4 downto 0);
-- Retiming: Output of comparators
signal rtmcmp90 : std_logic;
signal rtmcmp95 : std_logic;
signal rtmcmp98 : std_logic;
signal rtmcmp104 : std_logic;
signal rtmcmp148 : std_logic;
signal rtmcmp167 : std_logic;
signal rtmcmp174 : std_logic;
signal rtmcmp181 : std_logic;
signal rtmcmp183 : std_logic;
signal rtmcmp194 : std_logic;
signal rtmcmp197 : std_logic;
signal rtmcmp203 : std_logic;
signal rtmcmp205 : std_logic;
signal rtmcmp215 : std_logic;
-- Function calls: return IDs
begin
-- Sequential process
-- Set the current state
process (clock)
begin
if rising_edge(clock) then
-- Next state
state_cur <= state_next;
-- Buffers for outputs
out122_buf <= out122_bufn;
out36_buf <= out36_bufn;
out49_buf <= out49_bufn;
out35_buf <= out35_bufn;
out27_buf <= out27_bufn;
out16_buf <= out16_bufn;
out25_buf <= out25_bufn;
out20_buf <= out20_bufn;
out57_buf <= out57_bufn;
out23_buf <= out23_bufn;
out136_buf <= out136_bufn;
out0_buf <= out0_bufn;
out134_buf <= out134_bufn;
out13_buf <= out13_bufn;
out131_buf <= out131_bufn;
out129_buf <= out129_bufn;
out111_buf <= out111_bufn;
out31_buf <= out31_bufn;
out126_buf <= out126_bufn;
out106_buf <= out106_bufn;
out124_buf <= out124_bufn;
out138_buf <= out138_bufn;
out141_buf <= out141_bufn;
out143_buf <= out143_bufn;
out146_buf <= out146_bufn;
out150_buf <= out150_bufn;
out153_buf <= out153_bufn;
out155_buf <= out155_bufn;
out158_buf <= out158_bufn;
out162_buf <= out162_bufn;
out165_buf <= out165_bufn;
out168_buf <= out168_bufn;
out171_buf <= out171_bufn;
out174_buf <= out174_bufn;
out178_buf <= out178_bufn;
out181_buf <= out181_bufn;
out183_buf <= out183_bufn;
out197_buf <= out197_bufn;
out201_buf <= out201_bufn;
out204_buf <= out204_bufn;
out207_buf <= out207_bufn;
out210_buf <= out210_bufn;
out213_buf <= out213_bufn;
out217_buf <= out217_bufn;
out220_buf <= out220_bufn;
out222_buf <= out222_bufn;
out225_buf <= out225_bufn;
out229_buf <= out229_bufn;
out232_buf <= out232_bufn;
out235_buf <= out235_bufn;
out238_buf <= out238_bufn;
out241_buf <= out241_bufn;
out245_buf <= out245_bufn;
out248_buf <= out248_bufn;
out250_buf <= out250_bufn;
out253_buf <= out253_bufn;
out257_buf <= out257_bufn;
out260_buf <= out260_bufn;
out263_buf <= out263_bufn;
out266_buf <= out266_bufn;
out269_buf <= out269_bufn;
out273_buf <= out273_bufn;
out276_buf <= out276_bufn;
out278_buf <= out278_bufn;
out280_buf <= out280_bufn;
out281_buf <= out281_bufn;
out282_buf <= out282_bufn;
out284_buf <= out284_bufn;
out285_buf <= out285_bufn;
out287_buf <= out287_bufn;
out288_buf <= out288_bufn;
out289_buf <= out289_bufn;
out290_buf <= out290_bufn;
out291_buf <= out291_bufn;
out292_buf <= out292_bufn;
out293_buf <= out293_bufn;
out294_buf <= out294_bufn;
out295_buf <= out295_bufn;
out296_buf <= out296_bufn;
out312_buf <= out312_bufn;
out313_buf <= out313_bufn;
out314_buf <= out314_bufn;
out315_buf <= out315_bufn;
out318_buf <= out318_bufn;
out322_buf <= out322_bufn;
out323_buf <= out323_bufn;
out324_buf <= out324_bufn;
out325_buf <= out325_bufn;
out326_buf <= out326_bufn;
out327_buf <= out327_bufn;
out328_buf <= out328_bufn;
out333_buf <= out333_bufn;
out341_buf <= out341_bufn;
out342_buf <= out342_bufn;
out343_buf <= out343_bufn;
out344_buf <= out344_bufn;
out346_buf <= out346_bufn;
out349_buf <= out349_bufn;
out351_buf <= out351_bufn;
out352_buf <= out352_bufn;
out353_buf <= out353_bufn;
out354_buf <= out354_bufn;
out357_buf <= out357_bufn;
out361_buf <= out361_bufn;
out364_buf <= out364_bufn;
out366_buf <= out366_bufn;
out371_buf <= out371_bufn;
out393_buf <= out393_bufn;
out394_buf <= out394_bufn;
out395_buf <= out395_bufn;
out400_buf <= out400_bufn;
out401_buf <= out401_bufn;
out404_buf <= out404_bufn;
out407_buf <= out407_bufn;
out408_buf <= out408_bufn;
out409_buf <= out409_bufn;
out410_buf <= out410_bufn;
out413_buf <= out413_bufn;
out414_buf <= out414_bufn;
out417_buf <= out417_bufn;
out418_buf <= out418_bufn;
out422_buf <= out422_bufn;
out426_buf <= out426_bufn;
out428_buf <= out428_bufn;
out431_buf <= out431_bufn;
out433_buf <= out433_bufn;
out434_buf <= out434_bufn;
out435_buf <= out435_bufn;
out436_buf <= out436_bufn;
out437_buf <= out437_bufn;
out438_buf <= out438_bufn;
out440_buf <= out440_bufn;
out444_buf <= out444_bufn;
out446_buf <= out446_bufn;
out451_buf <= out451_bufn;
out457_buf <= out457_bufn;
out458_buf <= out458_bufn;
out459_buf <= out459_bufn;
out460_buf <= out460_bufn;
out461_buf <= out461_bufn;
out463_buf <= out463_bufn;
out464_buf <= out464_bufn;
out466_buf <= out466_bufn;
out468_buf <= out468_bufn;
out472_buf <= out472_bufn;
out475_buf <= out475_bufn;
out481_buf <= out481_bufn;
out482_buf <= out482_bufn;
out483_buf <= out483_bufn;
out487_buf <= out487_bufn;
out495_buf <= out495_bufn;
out496_buf <= out496_bufn;
out497_buf <= out497_bufn;
out499_buf <= out499_bufn;
out500_buf <= out500_bufn;
out512_buf <= out512_bufn;
out517_buf <= out517_bufn;
out518_buf <= out518_bufn;
out521_buf <= out521_bufn;
out524_buf <= out524_bufn;
out525_buf <= out525_bufn;
out526_buf <= out526_bufn;
out531_buf <= out531_bufn;
out554_buf <= out554_bufn;
out562_buf <= out562_bufn;
out566_buf <= out566_bufn;
-- Retiming: counters
rtmcounter0 <= rtmcounter0_next;
-- Function calls: return IDs
end if;
end process;
-- Combinatorial process
-- Compute the next state
-- Compute the outputs
process (
-- Inputs of the FSM
reset, in0, in2, in3, in4, in5, in1, in6, in11, in7, in8, in9, in10,
-- Retiming: outputs of the comparators
rtmcmp90, rtmcmp95, rtmcmp98, rtmcmp104, rtmcmp148, rtmcmp167, rtmcmp174, rtmcmp181, rtmcmp183, rtmcmp194, rtmcmp197, rtmcmp203, rtmcmp205, rtmcmp215,
-- Retiming: the counters
rtmcounter0,
-- Function calls: return IDs
-- Current state
state_cur
)
begin
-- Reset the next state value
state_next <= (others => '0');
-- Default value to the outputs or output buffers
out22 <= '0';
out4 <= '0';
out122_bufn <= '0';
out50 <= '0';
out121 <= '0';
out36_bufn <= '0';
out49_bufn <= '0';
out35_bufn <= '0';
out99 <= '0';
out52 <= '0';
out18 <= '0';
out33 <= '0';
out123 <= '0';
out101 <= '0';
out90 <= '0';
out91 <= '0';
out27_bufn <= '0';
out16_bufn <= '0';
out26 <= '0';
out21 <= '0';
out24 <= '0';
out54 <= '0';
out25_bufn <= '0';
out20_bufn <= '0';
out58 <= '0';
out30 <= '0';
out8 <= '0';
out57_bufn <= '0';
out48 <= '0';
out56 <= '0';
out23_bufn <= '0';
out29 <= '0';
out19 <= '0';
out136_bufn <= '0';
out2 <= '0';
out1 <= '0';
out46 <= '0';
out0_bufn <= '0';
out135 <= '0';
out118 <= '0';
out116 <= '0';
out14 <= '0';
out134_bufn <= '0';
out28 <= '0';
out13_bufn <= '0';
out133 <= '0';
out131_bufn <= '0';
out132 <= '0';
out114 <= '0';
out130 <= '0';
out112 <= '0';
out38 <= '0';
out44 <= '0';
out97 <= '0';
out129_bufn <= '0';
out111_bufn <= '0';
out31_bufn <= '0';
out126_bufn <= '0';
out107 <= '0';
out108 <= '0';
out105 <= '0';
out106_bufn <= '0';
out125 <= '0';
out120 <= '0';
out124_bufn <= '0';
out103 <= '0';
out42 <= '0';
out40 <= '0';
out60 <= '0';
out137 <= '0';
out138_bufn <= '0';
out140 <= '0';
out141_bufn <= '0';
out142 <= '0';
out143_bufn <= '0';
out145 <= '0';
out146_bufn <= '0';
out148 <= '0';
out150_bufn <= '0';
out153_bufn <= '0';
out154 <= '0';
out155_bufn <= '0';
out156 <= '0';
out157 <= '0';
out158_bufn <= '0';
out159 <= '0';
out160 <= '0';
out161 <= '0';
out162_bufn <= '0';
out164 <= '0';
out165_bufn <= '0';
out167 <= '0';
out168_bufn <= '0';
out170 <= '0';
out171_bufn <= '0';
out173 <= '0';
out174_bufn <= '0';
out176 <= '0';
out178_bufn <= '0';
out181_bufn <= '0';
out182 <= '0';
out183_bufn <= '0';
out184 <= '0';
out185 <= '0';
out186 <= '0';
out187 <= '0';
out190 <= '0';
out195 <= '0';
out197_bufn <= '0';
out198 <= '0';
out199 <= '0';
out200 <= '0';
out201_bufn <= '0';
out203 <= '0';
out204_bufn <= '0';
out206 <= '0';
out207_bufn <= '0';
out209 <= '0';
out210_bufn <= '0';
out212 <= '0';
out213_bufn <= '0';
out215 <= '0';
out217_bufn <= '0';
out220_bufn <= '0';
out221 <= '0';
out222_bufn <= '0';
out223 <= '0';
out224 <= '0';
out225_bufn <= '0';
out226 <= '0';
out227 <= '0';
out228 <= '0';
out229_bufn <= '0';
out231 <= '0';
out232_bufn <= '0';
out234 <= '0';
out235_bufn <= '0';
out237 <= '0';
out238_bufn <= '0';
out240 <= '0';
out241_bufn <= '0';
out243 <= '0';
out245_bufn <= '0';
out248_bufn <= '0';
out249 <= '0';
out250_bufn <= '0';
out251 <= '0';
out252 <= '0';
out253_bufn <= '0';
out254 <= '0';
out255 <= '0';
out256 <= '0';
out257_bufn <= '0';
out259 <= '0';
out260_bufn <= '0';
out262 <= '0';
out263_bufn <= '0';
out265 <= '0';
out266_bufn <= '0';
out268 <= '0';
out269_bufn <= '0';
out271 <= '0';
out273_bufn <= '0';
out276_bufn <= '0';
out277 <= '0';
out278_bufn <= '0';
out279 <= '0';
out280_bufn <= '0';
out281_bufn <= '0';
out282_bufn <= '0';
out283 <= '0';
out284_bufn <= '0';
out285_bufn <= '0';
out286 <= '0';
out287_bufn <= '0';
out288_bufn <= '0';
out289_bufn <= '0';
out290_bufn <= '0';
out291_bufn <= '0';
out292_bufn <= '0';
out293_bufn <= '0';
out294_bufn <= '0';
out295_bufn <= '0';
out296_bufn <= '0';
out297 <= '0';
out298 <= '0';
out311 <= '0';
out312_bufn <= '0';
out313_bufn <= '0';
out314_bufn <= '0';
out315_bufn <= '0';
out316 <= '0';
out318_bufn <= '0';
out321 <= '0';
out322_bufn <= '0';
out323_bufn <= '0';
out324_bufn <= '0';
out325_bufn <= '0';
out326_bufn <= '0';
out327_bufn <= '0';
out328_bufn <= '0';
out329 <= '0';
out333_bufn <= '0';
out341_bufn <= '0';
out342_bufn <= '0';
out343_bufn <= '0';
out344_bufn <= '0';
out345 <= '0';
out346_bufn <= '0';
out349_bufn <= '0';
out350 <= '0';
out351_bufn <= '0';
out352_bufn <= '0';
out353_bufn <= '0';
out354_bufn <= '0';
out355 <= '0';
out357_bufn <= '0';
out361_bufn <= '0';
out362 <= '0';
out363 <= '0';
out364_bufn <= '0';
out366_bufn <= '0';
out367 <= '0';
out371_bufn <= '0';
out372 <= '0';
out373 <= '0';
out382 <= '0';
out383 <= '0';
out385 <= '0';
out393_bufn <= '0';
out394_bufn <= '0';
out395_bufn <= '0';
out396 <= '0';
out398 <= '0';
out400_bufn <= '0';
out401_bufn <= '0';
out402 <= '0';
out404_bufn <= '0';
out406 <= '0';
out407_bufn <= '0';
out408_bufn <= '0';
out409_bufn <= '0';
out410_bufn <= '0';
out411 <= '0';
out412 <= '0';
out413_bufn <= '0';
out414_bufn <= '0';
out416 <= '0';
out417_bufn <= '0';
out418_bufn <= '0';
out419 <= '0';
out422_bufn <= '0';
out423 <= '0';
out425 <= '0';
out426_bufn <= '0';
out428_bufn <= '0';
out429 <= '0';
out430 <= '0';
out431_bufn <= '0';
out433_bufn <= '0';
out434_bufn <= '0';
out435_bufn <= '0';
out436_bufn <= '0';
out437_bufn <= '0';
out438_bufn <= '0';
out440_bufn <= '0';
out441 <= '0';
out443 <= '0';
out444_bufn <= '0';
out445 <= '0';
out446_bufn <= '0';
out447 <= '0';
out450 <= '0';
out451_bufn <= '0';
out454 <= '0';
out455 <= '0';
out457_bufn <= '0';
out458_bufn <= '0';
out459_bufn <= '0';
out460_bufn <= '0';
out461_bufn <= '0';
out462 <= '0';
out463_bufn <= '0';
out464_bufn <= '0';
out465 <= '0';
out466_bufn <= '0';
out467 <= '0';
out468_bufn <= '0';
out469 <= '0';
out472_bufn <= '0';
out475_bufn <= '0';
out481_bufn <= '0';
out482_bufn <= '0';
out483_bufn <= '0';
out484 <= '0';
out487_bufn <= '0';
out488 <= '0';
out491 <= '0';
out495_bufn <= '0';
out496_bufn <= '0';
out497_bufn <= '0';
out498 <= '0';
out499_bufn <= '0';
out500_bufn <= '0';
out501 <= '0';
out512_bufn <= '0';
out513 <= '0';
out517_bufn <= '0';
out518_bufn <= '0';
out519 <= '0';
out521_bufn <= '0';
out522 <= '0';
out524_bufn <= '0';
out525_bufn <= '0';
out526_bufn <= '0';
out527 <= '0';
out528 <= '0';
out531_bufn <= '0';
out540 <= '0';
out542 <= '0';
out544 <= '0';
out545 <= '0';
out554_bufn <= '0';
out555 <= '0';
out559 <= '0';
out560 <= '0';
out561 <= '0';
out562_bufn <= '0';
out563 <= '0';
out566_bufn <= '0';
out567 <= '0';
out570 <= '0';
out572 <= '0';
out575 <= '0';
out577 <= '0';
out578 <= '0';
out580 <= '0';
out581 <= '0';
-- Retiming: default value for counters
rtmcounter0_next <= (others => '0');
-- Function calls: default values (no change)
-- For all states, compute the next state bits
-- And the outputs, and the next value for buffered outputs
if state_cur(0) = '1' then
-- Next state
state_next(109) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out1 <= '1';
out2 <= '1';
end if;
if state_cur(1) = '1' then
-- Next state
if (in0) = '1' then
state_next(1) <= '1';
-- Next values for buffered outputs
out13_bufn <= '1';
else
-- Return from function: memextrct_0
state_next(88) <= '1';
-- Next values for buffered outputs
end if;
-- Assignment of non-buffered outputs
out14 <= '1';
out8 <= '1';
out4 <= '1';
end if;
if state_cur(2) = '1' then
-- Next state
state_next(1) <= '1';
-- Next values for buffered outputs
out13_bufn <= '1';
-- Assignment of non-buffered outputs
out18 <= '1';
end if;
if state_cur(3) = '1' then
-- Next state
state_next(0) <= '1';
-- Next values for buffered outputs
out0_bufn <= '1';
-- Assignment of non-buffered outputs
out21 <= '1';
out2 <= '1';
out19 <= '1';
end if;
if state_cur(4) = '1' then
-- Next state
state_next(3) <= '1';
-- Next values for buffered outputs
out20_bufn <= '1';
out0_bufn <= '1';
-- Assignment of non-buffered outputs
out21 <= '1';
out2 <= '1';
out22 <= '1';
end if;
if state_cur(5) = '1' then
-- Next state
state_next(4) <= '1';
-- Next values for buffered outputs
out23_bufn <= '1';
out0_bufn <= '1';
-- Assignment of non-buffered outputs
out21 <= '1';
out2 <= '1';
out24 <= '1';
end if;
if state_cur(6) = '1' then
-- Next state
state_next(5) <= '1';
-- Next values for buffered outputs
out25_bufn <= '1';
out0_bufn <= '1';
-- Assignment of non-buffered outputs
out21 <= '1';
out2 <= '1';
out26 <= '1';
end if;
-- Info: This is the init/reset state
if state_cur(7) = '1' then
-- Next state
if (not (in2)) = '1' then
state_next(7) <= '1';
-- Next values for buffered outputs
else
if (in1) = '1' then
state_next(60) <= '1';
-- Next values for buffered outputs
else
state_next(154) <= '1';
-- Next values for buffered outputs
end if;
end if;
-- Assignment of non-buffered outputs
out28 <= '1';
out29 <= '1';
end if;
if state_cur(8) = '1' then
-- Next state
state_next(6) <= '1';
-- Next values for buffered outputs
out27_bufn <= '1';
out0_bufn <= '1';
-- Assignment of non-buffered outputs
out21 <= '1';
out2 <= '1';
out30 <= '1';
end if;
if state_cur(9) = '1' then
-- Next state
state_next(9) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
end if;
if state_cur(10) = '1' then
-- Next state
state_next(8) <= '1';
-- Next values for buffered outputs
out31_bufn <= '1';
out0_bufn <= '1';
-- Assignment of non-buffered outputs
out21 <= '1';
out33 <= '1';
out2 <= '1';
end if;
if state_cur(11) = '1' then
-- Next state
state_next(10) <= '1';
-- Next values for buffered outputs
out0_bufn <= '1';
-- Assignment of non-buffered outputs
out21 <= '1';
out2 <= '1';
end if;
if state_cur(12) = '1' then
-- Next state
state_next(11) <= '1';
-- Next values for buffered outputs
out35_bufn <= '1';
out0_bufn <= '1';
-- Assignment of non-buffered outputs
out21 <= '1';
end if;
if state_cur(13) = '1' then
-- Next state
state_next(12) <= '1';
-- Next values for buffered outputs
out36_bufn <= '1';
-- Assignment of non-buffered outputs
out52 <= '1';
out50 <= '1';
out48 <= '1';
out46 <= '1';
out44 <= '1';
out42 <= '1';
out40 <= '1';
out38 <= '1';
end if;
if state_cur(14) = '1' then
-- Next state
state_next(13) <= '1';
-- Next values for buffered outputs
out49_bufn <= '1';
-- Assignment of non-buffered outputs
out60 <= '1';
out58 <= '1';
out56 <= '1';
out54 <= '1';
end if;
if state_cur(15) = '1' then
-- Next state
if (in3) = '1' then
state_next(15) <= '1';
-- Next values for buffered outputs
out13_bufn <= '1';
else
-- Return from function: memextrct_1
state_next(88) <= '1';
-- Next values for buffered outputs
end if;
-- Assignment of non-buffered outputs
out14 <= '1';
out91 <= '1';
out90 <= '1';
end if;
if state_cur(16) = '1' then
-- Next state
if (in5) = '1' then
-- Function call: memextrct_1
state_next(19) <= '1';
-- Next values for buffered outputs
out16_bufn <= '1';
else
if (in4) = '1' then
-- Function call: memextrct_0
state_next(2) <= '1';
-- Next values for buffered outputs
out16_bufn <= '1';
else
state_next(88) <= '1';
-- Next values for buffered outputs
end if;
end if;
-- Assignment of non-buffered outputs
out97 <= '1';
end if;
if state_cur(17) = '1' then
-- Next state
state_next(14) <= '1';
-- Next values for buffered outputs
out57_bufn <= '1';
-- Assignment of non-buffered outputs
out105 <= '1';
out103 <= '1';
out101 <= '1';
out99 <= '1';
end if;
if state_cur(18) = '1' then
-- Next state
state_next(17) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out120 <= '1';
out118 <= '1';
out116 <= '1';
out114 <= '1';
out112 <= '1';
out108 <= '1';
out107 <= '1';
end if;
if state_cur(19) = '1' then
-- Next state
state_next(15) <= '1';
-- Next values for buffered outputs
out13_bufn <= '1';
-- Assignment of non-buffered outputs
out18 <= '1';
end if;
if state_cur(20) = '1' then
-- Next state
state_next(18) <= '1';
-- Next values for buffered outputs
out111_bufn <= '1';
out106_bufn <= '1';
-- Assignment of non-buffered outputs
out52 <= '1';
out21 <= '1';
out125 <= '1';
out123 <= '1';
out108 <= '1';
out121 <= '1';
end if;
if state_cur(21) = '1' then
-- Next state
state_next(20) <= '1';
-- Next values for buffered outputs
out126_bufn <= '1';
out20_bufn <= '1';
out124_bufn <= '1';
out122_bufn <= '1';
out106_bufn <= '1';
-- Assignment of non-buffered outputs
out132 <= '1';
out50 <= '1';
out21 <= '1';
out130 <= '1';
out108 <= '1';
end if;
if state_cur(22) = '1' then
-- Next state
state_next(21) <= '1';
-- Next values for buffered outputs
out131_bufn <= '1';
out23_bufn <= '1';
out129_bufn <= '1';
out106_bufn <= '1';
-- Assignment of non-buffered outputs
out48 <= '1';
out21 <= '1';
out137 <= '1';
out135 <= '1';
out108 <= '1';
out133 <= '1';
end if;
if state_cur(23) = '1' then
-- Next state
state_next(22) <= '1';
-- Next values for buffered outputs
out138_bufn <= '1';
out25_bufn <= '1';
out136_bufn <= '1';
out134_bufn <= '1';
out106_bufn <= '1';
-- Assignment of non-buffered outputs
out46 <= '1';
out21 <= '1';
out142 <= '1';
out140 <= '1';
out108 <= '1';
end if;
if state_cur(24) = '1' then
-- Next state
state_next(23) <= '1';
-- Next values for buffered outputs
out143_bufn <= '1';
out27_bufn <= '1';
out141_bufn <= '1';
out106_bufn <= '1';
-- Assignment of non-buffered outputs
out44 <= '1';
out21 <= '1';
out145 <= '1';
out108 <= '1';
end if;
if state_cur(25) = '1' then
-- Next state
state_next(24) <= '1';
-- Next values for buffered outputs
out146_bufn <= '1';
out31_bufn <= '1';
out106_bufn <= '1';
-- Assignment of non-buffered outputs
out42 <= '1';
out21 <= '1';
out148 <= '1';
out108 <= '1';
end if;
if state_cur(26) = '1' then
-- Next state
state_next(25) <= '1';
-- Next values for buffered outputs
out150_bufn <= '1';
out106_bufn <= '1';
-- Assignment of non-buffered outputs
out154 <= '1';
out40 <= '1';
out21 <= '1';
out108 <= '1';
end if;
if state_cur(27) = '1' then
-- Next state
state_next(26) <= '1';
-- Next values for buffered outputs
out153_bufn <= '1';
out35_bufn <= '1';
out106_bufn <= '1';
-- Assignment of non-buffered outputs
out156 <= '1';
out38 <= '1';
out21 <= '1';
end if;
if state_cur(28) = '1' then
-- Next state
state_next(27) <= '1';
-- Next values for buffered outputs
out155_bufn <= '1';
out36_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out46 <= '1';
out52 <= '1';
out48 <= '1';
out44 <= '1';
out42 <= '1';
out40 <= '1';
out38 <= '1';
end if;
if state_cur(29) = '1' then
-- Next state
state_next(28) <= '1';
-- Next values for buffered outputs
out49_bufn <= '1';
-- Assignment of non-buffered outputs
out60 <= '1';
out157 <= '1';
out58 <= '1';
out56 <= '1';
out54 <= '1';
end if;
if state_cur(30) = '1' then
-- Next state
state_next(29) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out105 <= '1';
out103 <= '1';
out101 <= '1';
out99 <= '1';
end if;
if state_cur(31) = '1' then
-- Next state
state_next(30) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out120 <= '1';
out118 <= '1';
out116 <= '1';
out114 <= '1';
out112 <= '1';
out160 <= '1';
out159 <= '1';
end if;
if state_cur(32) = '1' then
-- Next state
state_next(31) <= '1';
-- Next values for buffered outputs
out111_bufn <= '1';
out158_bufn <= '1';
-- Assignment of non-buffered outputs
out52 <= '1';
out21 <= '1';
out125 <= '1';
out123 <= '1';
out161 <= '1';
out160 <= '1';
end if;
if state_cur(33) = '1' then
-- Next state
state_next(32) <= '1';
-- Next values for buffered outputs
out162_bufn <= '1';
out20_bufn <= '1';
out124_bufn <= '1';
out122_bufn <= '1';
out158_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out21 <= '1';
out130 <= '1';
out164 <= '1';
out160 <= '1';
end if;
if state_cur(34) = '1' then
-- Next state
state_next(33) <= '1';
-- Next values for buffered outputs
out165_bufn <= '1';
out23_bufn <= '1';
out129_bufn <= '1';
out158_bufn <= '1';
-- Assignment of non-buffered outputs
out48 <= '1';
out21 <= '1';
out137 <= '1';
out135 <= '1';
out167 <= '1';
out160 <= '1';
end if;
if state_cur(35) = '1' then
-- Next state
state_next(34) <= '1';
-- Next values for buffered outputs
out168_bufn <= '1';
out25_bufn <= '1';
out136_bufn <= '1';
out134_bufn <= '1';
out158_bufn <= '1';
-- Assignment of non-buffered outputs
out46 <= '1';
out21 <= '1';
out142 <= '1';
out170 <= '1';
out160 <= '1';
end if;
if state_cur(36) = '1' then
-- Next state
state_next(35) <= '1';
-- Next values for buffered outputs
out171_bufn <= '1';
out27_bufn <= '1';
out141_bufn <= '1';
out158_bufn <= '1';
-- Assignment of non-buffered outputs
out44 <= '1';
out21 <= '1';
out173 <= '1';
out160 <= '1';
end if;
if state_cur(37) = '1' then
-- Next state
state_next(36) <= '1';
-- Next values for buffered outputs
out174_bufn <= '1';
out31_bufn <= '1';
out158_bufn <= '1';
-- Assignment of non-buffered outputs
out42 <= '1';
out21 <= '1';
out176 <= '1';
out160 <= '1';
end if;
if state_cur(38) = '1' then
-- Next state
state_next(37) <= '1';
-- Next values for buffered outputs
out178_bufn <= '1';
out158_bufn <= '1';
-- Assignment of non-buffered outputs
out182 <= '1';
out40 <= '1';
out21 <= '1';
out160 <= '1';
end if;
if state_cur(39) = '1' then
-- Next state
state_next(38) <= '1';
-- Next values for buffered outputs
out181_bufn <= '1';
out35_bufn <= '1';
out158_bufn <= '1';
-- Assignment of non-buffered outputs
out184 <= '1';
out38 <= '1';
out21 <= '1';
end if;
if state_cur(40) = '1' then
-- Next state
state_next(39) <= '1';
-- Next values for buffered outputs
out183_bufn <= '1';
out36_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out46 <= '1';
out52 <= '1';
out48 <= '1';
out44 <= '1';
out42 <= '1';
out40 <= '1';
out38 <= '1';
end if;
if state_cur(41) = '1' then
-- Next state
state_next(40) <= '1';
-- Next values for buffered outputs
out49_bufn <= '1';
-- Assignment of non-buffered outputs
out60 <= '1';
out185 <= '1';
out58 <= '1';
out56 <= '1';
out54 <= '1';
end if;
if state_cur(42) = '1' then
-- Next state
state_next(41) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out105 <= '1';
out103 <= '1';
out101 <= '1';
out99 <= '1';
end if;
if state_cur(43) = '1' then
-- Next state
if (in7) = '1' then
state_next(60) <= '1';
-- Next values for buffered outputs
else
if (not (in6)) = '1' then
state_next(43) <= '1';
-- Next values for buffered outputs
else
state_next(108) <= '1';
-- Next values for buffered outputs
out371_bufn <= '1';
end if;
end if;
-- Assignment of non-buffered outputs
out190 <= '1';
out187 <= '1';
out186 <= '1';
end if;
if state_cur(44) = '1' then
-- Next state
if (in7) = '1' then
state_next(60) <= '1';
-- Next values for buffered outputs
else
if (not (in8)) = '1' then
state_next(44) <= '1';
-- Next values for buffered outputs
else
state_next(110) <= '1';
-- Next values for buffered outputs
out371_bufn <= '1';
end if;
end if;
-- Assignment of non-buffered outputs
out195 <= '1';
out187 <= '1';
end if;
if state_cur(45) = '1' then
-- Next state
state_next(42) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out120 <= '1';
out118 <= '1';
out116 <= '1';
out114 <= '1';
out112 <= '1';
out199 <= '1';
out198 <= '1';
end if;
if state_cur(46) = '1' then
-- Next state
state_next(45) <= '1';
-- Next values for buffered outputs
out111_bufn <= '1';
out197_bufn <= '1';
-- Assignment of non-buffered outputs
out52 <= '1';
out21 <= '1';
out125 <= '1';
out123 <= '1';
out200 <= '1';
out199 <= '1';
end if;
if state_cur(47) = '1' then
-- Next state
state_next(46) <= '1';
-- Next values for buffered outputs
out201_bufn <= '1';
out20_bufn <= '1';
out124_bufn <= '1';
out122_bufn <= '1';
out197_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out21 <= '1';
out130 <= '1';
out203 <= '1';
out199 <= '1';
end if;
if state_cur(48) = '1' then
-- Next state
state_next(47) <= '1';
-- Next values for buffered outputs
out204_bufn <= '1';
out23_bufn <= '1';
out129_bufn <= '1';
out197_bufn <= '1';
-- Assignment of non-buffered outputs
out48 <= '1';
out21 <= '1';
out137 <= '1';
out135 <= '1';
out206 <= '1';
out199 <= '1';
end if;
if state_cur(49) = '1' then
-- Next state
state_next(48) <= '1';
-- Next values for buffered outputs
out207_bufn <= '1';
out25_bufn <= '1';
out136_bufn <= '1';
out134_bufn <= '1';
out197_bufn <= '1';
-- Assignment of non-buffered outputs
out46 <= '1';
out21 <= '1';
out142 <= '1';
out209 <= '1';
out199 <= '1';
end if;
if state_cur(50) = '1' then
-- Next state
state_next(49) <= '1';
-- Next values for buffered outputs
out210_bufn <= '1';
out27_bufn <= '1';
out141_bufn <= '1';
out197_bufn <= '1';
-- Assignment of non-buffered outputs
out44 <= '1';
out21 <= '1';
out212 <= '1';
out199 <= '1';
end if;
if state_cur(51) = '1' then
-- Next state
state_next(50) <= '1';
-- Next values for buffered outputs
out213_bufn <= '1';
out31_bufn <= '1';
out197_bufn <= '1';
-- Assignment of non-buffered outputs
out42 <= '1';
out21 <= '1';
out215 <= '1';
out199 <= '1';
end if;
if state_cur(52) = '1' then
-- Next state
state_next(51) <= '1';
-- Next values for buffered outputs
out217_bufn <= '1';
out197_bufn <= '1';
-- Assignment of non-buffered outputs
out221 <= '1';
out40 <= '1';
out21 <= '1';
out199 <= '1';
end if;
if state_cur(53) = '1' then
-- Next state
state_next(52) <= '1';
-- Next values for buffered outputs
out220_bufn <= '1';
out35_bufn <= '1';
out197_bufn <= '1';
-- Assignment of non-buffered outputs
out223 <= '1';
out38 <= '1';
out21 <= '1';
end if;
if state_cur(54) = '1' then
-- Next state
state_next(53) <= '1';
-- Next values for buffered outputs
out222_bufn <= '1';
out36_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out46 <= '1';
out52 <= '1';
out48 <= '1';
out44 <= '1';
out42 <= '1';
out40 <= '1';
out38 <= '1';
end if;
if state_cur(55) = '1' then
-- Next state
state_next(54) <= '1';
-- Next values for buffered outputs
out49_bufn <= '1';
-- Assignment of non-buffered outputs
out60 <= '1';
out224 <= '1';
out58 <= '1';
out56 <= '1';
out54 <= '1';
end if;
if state_cur(56) = '1' then
-- Next state
state_next(55) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out105 <= '1';
out103 <= '1';
out101 <= '1';
out99 <= '1';
end if;
if state_cur(57) = '1' then
-- Next state
state_next(56) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out120 <= '1';
out118 <= '1';
out116 <= '1';
out114 <= '1';
out112 <= '1';
out227 <= '1';
out226 <= '1';
end if;
if state_cur(58) = '1' then
-- Next state
state_next(57) <= '1';
-- Next values for buffered outputs
out111_bufn <= '1';
out225_bufn <= '1';
-- Assignment of non-buffered outputs
out52 <= '1';
out21 <= '1';
out125 <= '1';
out123 <= '1';
out228 <= '1';
out227 <= '1';
end if;
if state_cur(59) = '1' then
-- Next state
state_next(58) <= '1';
-- Next values for buffered outputs
out229_bufn <= '1';
out20_bufn <= '1';
out124_bufn <= '1';
out122_bufn <= '1';
out225_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out21 <= '1';
out130 <= '1';
out231 <= '1';
out227 <= '1';
end if;
if state_cur(60) = '1' then
-- Next state
state_next(87) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out18 <= '1';
end if;
if state_cur(61) = '1' then
-- Next state
state_next(59) <= '1';
-- Next values for buffered outputs
out232_bufn <= '1';
out23_bufn <= '1';
out129_bufn <= '1';
out225_bufn <= '1';
-- Assignment of non-buffered outputs
out48 <= '1';
out21 <= '1';
out137 <= '1';
out135 <= '1';
out234 <= '1';
out227 <= '1';
end if;
if state_cur(62) = '1' then
-- Next state
state_next(61) <= '1';
-- Next values for buffered outputs
out235_bufn <= '1';
out25_bufn <= '1';
out136_bufn <= '1';
out134_bufn <= '1';
out225_bufn <= '1';
-- Assignment of non-buffered outputs
out46 <= '1';
out21 <= '1';
out142 <= '1';
out237 <= '1';
out227 <= '1';
end if;
if state_cur(63) = '1' then
-- Next state
state_next(62) <= '1';
-- Next values for buffered outputs
out238_bufn <= '1';
out27_bufn <= '1';
out141_bufn <= '1';
out225_bufn <= '1';
-- Assignment of non-buffered outputs
out44 <= '1';
out21 <= '1';
out240 <= '1';
out227 <= '1';
end if;
if state_cur(64) = '1' then
-- Next state
state_next(63) <= '1';
-- Next values for buffered outputs
out241_bufn <= '1';
out31_bufn <= '1';
out225_bufn <= '1';
-- Assignment of non-buffered outputs
out42 <= '1';
out21 <= '1';
out243 <= '1';
out227 <= '1';
end if;
if state_cur(65) = '1' then
-- Next state
state_next(64) <= '1';
-- Next values for buffered outputs
out245_bufn <= '1';
out225_bufn <= '1';
-- Assignment of non-buffered outputs
out249 <= '1';
out40 <= '1';
out21 <= '1';
out227 <= '1';
end if;
if state_cur(66) = '1' then
-- Next state
state_next(65) <= '1';
-- Next values for buffered outputs
out248_bufn <= '1';
out35_bufn <= '1';
out225_bufn <= '1';
-- Assignment of non-buffered outputs
out251 <= '1';
out38 <= '1';
out21 <= '1';
end if;
if state_cur(67) = '1' then
-- Next state
state_next(66) <= '1';
-- Next values for buffered outputs
out250_bufn <= '1';
out36_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out46 <= '1';
out52 <= '1';
out48 <= '1';
out44 <= '1';
out42 <= '1';
out40 <= '1';
out38 <= '1';
end if;
if state_cur(68) = '1' then
-- Next state
state_next(67) <= '1';
-- Next values for buffered outputs
out49_bufn <= '1';
-- Assignment of non-buffered outputs
out60 <= '1';
out252 <= '1';
out58 <= '1';
out56 <= '1';
out54 <= '1';
end if;
if state_cur(69) = '1' then
-- Next state
state_next(68) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out105 <= '1';
out103 <= '1';
out101 <= '1';
out99 <= '1';
end if;
if state_cur(70) = '1' then
-- Next state
state_next(69) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out120 <= '1';
out118 <= '1';
out116 <= '1';
out114 <= '1';
out112 <= '1';
out255 <= '1';
out254 <= '1';
end if;
if state_cur(71) = '1' then
-- Next state
state_next(70) <= '1';
-- Next values for buffered outputs
out111_bufn <= '1';
out253_bufn <= '1';
-- Assignment of non-buffered outputs
out52 <= '1';
out21 <= '1';
out125 <= '1';
out123 <= '1';
out256 <= '1';
out255 <= '1';
end if;
if state_cur(72) = '1' then
-- Next state
state_next(71) <= '1';
-- Next values for buffered outputs
out257_bufn <= '1';
out20_bufn <= '1';
out124_bufn <= '1';
out122_bufn <= '1';
out253_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out21 <= '1';
out130 <= '1';
out259 <= '1';
out255 <= '1';
end if;
if state_cur(73) = '1' then
-- Next state
state_next(72) <= '1';
-- Next values for buffered outputs
out260_bufn <= '1';
out23_bufn <= '1';
out129_bufn <= '1';
out253_bufn <= '1';
-- Assignment of non-buffered outputs
out48 <= '1';
out21 <= '1';
out137 <= '1';
out135 <= '1';
out262 <= '1';
out255 <= '1';
end if;
if state_cur(74) = '1' then
-- Next state
state_next(73) <= '1';
-- Next values for buffered outputs
out263_bufn <= '1';
out25_bufn <= '1';
out136_bufn <= '1';
out134_bufn <= '1';
out253_bufn <= '1';
-- Assignment of non-buffered outputs
out46 <= '1';
out21 <= '1';
out142 <= '1';
out265 <= '1';
out255 <= '1';
end if;
if state_cur(75) = '1' then
-- Next state
state_next(74) <= '1';
-- Next values for buffered outputs
out266_bufn <= '1';
out27_bufn <= '1';
out141_bufn <= '1';
out253_bufn <= '1';
-- Assignment of non-buffered outputs
out44 <= '1';
out21 <= '1';
out268 <= '1';
out255 <= '1';
end if;
if state_cur(76) = '1' then
-- Next state
state_next(75) <= '1';
-- Next values for buffered outputs
out269_bufn <= '1';
out31_bufn <= '1';
out253_bufn <= '1';
-- Assignment of non-buffered outputs
out42 <= '1';
out21 <= '1';
out271 <= '1';
out255 <= '1';
end if;
if state_cur(77) = '1' then
-- Next state
state_next(76) <= '1';
-- Next values for buffered outputs
out273_bufn <= '1';
out253_bufn <= '1';
-- Assignment of non-buffered outputs
out277 <= '1';
out40 <= '1';
out21 <= '1';
out255 <= '1';
end if;
if state_cur(78) = '1' then
-- Next state
state_next(77) <= '1';
-- Next values for buffered outputs
out276_bufn <= '1';
out35_bufn <= '1';
out253_bufn <= '1';
-- Assignment of non-buffered outputs
out279 <= '1';
out38 <= '1';
out21 <= '1';
end if;
if state_cur(79) = '1' then
-- Next state
state_next(80) <= '1';
-- Next values for buffered outputs
out285_bufn <= '1';
out284_bufn <= '1';
out269_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(80) = '1' then
-- Next state
state_next(113) <= '1';
-- Next values for buffered outputs
out395_bufn <= '1';
out284_bufn <= '1';
out146_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(81) = '1' then
-- Next state
state_next(82) <= '1';
-- Next values for buffered outputs
out290_bufn <= '1';
out289_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(82) = '1' then
-- Next state
state_next(83) <= '1';
-- Next values for buffered outputs
out57_bufn <= '1';
out292_bufn <= '1';
out291_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(83) = '1' then
-- Next state
state_next(85) <= '1';
-- Next values for buffered outputs
out295_bufn <= '1';
out294_bufn <= '1';
-- Assignment of non-buffered outputs
out58 <= '1';
out118 <= '1';
out286 <= '1';
end if;
if state_cur(84) = '1' then
-- Next state
state_next(89) <= '1';
-- Next values for buffered outputs
out313_bufn <= '1';
out281_bufn <= '1';
out312_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(85) = '1' then
-- Next state
state_next(86) <= '1';
-- Next values for buffered outputs
out296_bufn <= '1';
out291_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(86) = '1' then
-- Next state
state_next(90) <= '1';
-- Next values for buffered outputs
out318_bufn <= '1';
out280_bufn <= '1';
out315_bufn <= '1';
out314_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(87) = '1' then
-- Next state
if (in9) = '1' then
state_next(87) <= '1';
-- Next values for buffered outputs
else
state_next(16) <= '1';
-- Next values for buffered outputs
out16_bufn <= '1';
end if;
-- Assignment of non-buffered outputs
out14 <= '1';
out298 <= '1';
out297 <= '1';
end if;
if state_cur(88) = '1' then
-- Next state
if (in1) = '1' then
if (in5) = '1' then
state_next(43) <= '1';
-- Next values for buffered outputs
else
state_next(44) <= '1';
-- Next values for buffered outputs
end if;
else
state_next(9) <= '1';
-- Next values for buffered outputs
end if;
-- Assignment of non-buffered outputs
out311 <= '1';
end if;
if state_cur(89) = '1' then
-- Next state
state_next(112) <= '1';
-- Next values for buffered outputs
out394_bufn <= '1';
out284_bufn <= '1';
out393_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(90) = '1' then
if rtmcmp90 = '1' then
-- Next state
state_next(93) <= '1';
-- Next values for buffered outputs
out57_bufn <= '1';
out325_bufn <= '1';
out324_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out103 <= '1';
out105 <= '1';
out56 <= '1';
out137 <= '1';
out125 <= '1';
out116 <= '1';
out283 <= '1';
else -- Stay in the current state
state_next(90) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out318_bufn <= '1';
out280_bufn <= '1';
out315_bufn <= '1';
out314_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out316 <= '1';
end if;
if state_cur(91) = '1' then
-- Next state
state_next(170) <= '1';
-- Next values for buffered outputs
out487_bufn <= '1';
out284_bufn <= '1';
out266_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
out321 <= '1';
end if;
if state_cur(92) = '1' then
-- Next state
state_next(240) <= '1';
-- Next values for buffered outputs
out217_bufn <= '1';
out295_bufn <= '1';
out281_bufn <= '1';
out562_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(93) = '1' then
-- Next state
state_next(101) <= '1';
-- Next values for buffered outputs
out323_bufn <= '1';
out291_bufn <= '1';
-- Assignment of non-buffered outputs
out118 <= '1';
out58 <= '1';
out286 <= '1';
end if;
if state_cur(94) = '1' then
-- Next state
state_next(96) <= '1';
-- Next values for buffered outputs
out341_bufn <= '1';
out281_bufn <= '1';
out241_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(95) = '1' then
if rtmcmp95 = '1' then
-- Next state
state_next(210) <= '1';
-- Next values for buffered outputs
out418_bufn <= '1';
out351_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out130 <= '1';
out101 <= '1';
out142 <= '1';
out112 <= '1';
out99 <= '1';
out54 <= '1';
out123 <= '1';
out135 <= '1';
out114 <= '1';
out286 <= '1';
else -- Stay in the current state
state_next(95) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out333_bufn <= '1';
out245_bufn <= '1';
out318_bufn <= '1';
out328_bufn <= '1';
out327_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out329 <= '1';
end if;
if state_cur(96) = '1' then
-- Next state
state_next(91) <= '1';
-- Next values for buffered outputs
out322_bufn <= '1';
out281_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(97) = '1' then
-- Next state
state_next(95) <= '1';
-- Next values for buffered outputs
out333_bufn <= '1';
out245_bufn <= '1';
out318_bufn <= '1';
out328_bufn <= '1';
out327_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(98) = '1' then
if rtmcmp98 = '1' then
-- Next state
state_next(97) <= '1';
-- Next values for buffered outputs
out342_bufn <= '1';
out324_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out125 <= '1';
out137 <= '1';
out116 <= '1';
out56 <= '1';
out283 <= '1';
else -- Stay in the current state
state_next(98) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out346_bufn <= '1';
out344_bufn <= '1';
out312_bufn <= '1';
out343_bufn <= '1';
out314_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out345 <= '1';
end if;
if state_cur(99) = '1' then
-- Next state
state_next(119) <= '1';
-- Next values for buffered outputs
out36_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out46 <= '1';
out52 <= '1';
out48 <= '1';
out44 <= '1';
out42 <= '1';
out40 <= '1';
out38 <= '1';
end if;
if state_cur(100) = '1' then
-- Next state
state_next(233) <= '1';
-- Next values for buffered outputs
out566_bufn <= '1';
out289_bufn <= '1';
-- Assignment of non-buffered outputs
out125 <= '1';
out286 <= '1';
end if;
if state_cur(101) = '1' then
-- Next state
state_next(98) <= '1';
-- Next values for buffered outputs
out346_bufn <= '1';
out344_bufn <= '1';
out312_bufn <= '1';
out343_bufn <= '1';
out314_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(102) = '1' then
-- Next state
state_next(239) <= '1';
-- Next values for buffered outputs
out49_bufn <= '1';
-- Assignment of non-buffered outputs
out60 <= '1';
out350 <= '1';
out58 <= '1';
out56 <= '1';
out54 <= '1';
end if;
if state_cur(103) = '1' then
-- Next state
state_next(146) <= '1';
-- Next values for buffered outputs
out401_bufn <= '1';
out444_bufn <= '1';
out294_bufn <= '1';
-- Assignment of non-buffered outputs
out120 <= '1';
out60 <= '1';
out283 <= '1';
end if;
if state_cur(104) = '1' then
if rtmcmp104 = '1' then
-- Next state
state_next(103) <= '1';
-- Next values for buffered outputs
out352_bufn <= '1';
out351_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out142 <= '1';
out99 <= '1';
out130 <= '1';
out101 <= '1';
out54 <= '1';
out135 <= '1';
out123 <= '1';
out114 <= '1';
out286 <= '1';
else -- Stay in the current state
state_next(104) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out129_bufn <= '1';
out357_bufn <= '1';
out354_bufn <= '1';
out353_bufn <= '1';
out327_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out355 <= '1';
end if;
if state_cur(105) = '1' then
-- Next state
state_next(133) <= '1';
-- Next values for buffered outputs
out431_bufn <= '1';
out23_bufn <= '1';
out129_bufn <= '1';
out361_bufn <= '1';
-- Assignment of non-buffered outputs
out48 <= '1';
out21 <= '1';
out137 <= '1';
out135 <= '1';
out363 <= '1';
out362 <= '1';
end if;
if state_cur(106) = '1' then
-- Next state
state_next(186) <= '1';
-- Next values for buffered outputs
out518_bufn <= '1';
out284_bufn <= '1';
out153_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(107) = '1' then
-- Next state
state_next(148) <= '1';
-- Next values for buffered outputs
out446_bufn <= '1';
out413_bufn <= '1';
out281_bufn <= '1';
out250_bufn <= '1';
-- Assignment of non-buffered outputs
out112 <= '1';
out367 <= '1';
out283 <= '1';
end if;
if state_cur(108) = '1' then
-- Next state
if (in10) = '1' then
state_next(109) <= '1';
-- Next values for buffered outputs
else
state_next(154) <= '1';
-- Next values for buffered outputs
end if;
-- Assignment of non-buffered outputs
out372 <= '1';
end if;
if state_cur(109) = '1' then
-- Next state
state_next(43) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out382 <= '1';
out373 <= '1';
end if;
if state_cur(110) = '1' then
-- Next state
if (in11) = '1' then
state_next(44) <= '1';
-- Next values for buffered outputs
else
state_next(111) <= '1';
-- Next values for buffered outputs
out284_bufn <= '1';
end if;
-- Assignment of non-buffered outputs
out372 <= '1';
out385 <= '1';
out383 <= '1';
end if;
if state_cur(111) = '1' then
-- Next state
state_next(153) <= '1';
-- Next values for buffered outputs
out422_bufn <= '1';
out284_bufn <= '1';
out278_bufn <= '1';
-- Assignment of non-buffered outputs
out372 <= '1';
out286 <= '1';
end if;
if state_cur(112) = '1' then
-- Next state
state_next(94) <= '1';
-- Next values for buffered outputs
out326_bufn <= '1';
out284_bufn <= '1';
out210_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(113) = '1' then
-- Next state
state_next(160) <= '1';
-- Next values for buffered outputs
out461_bufn <= '1';
out281_bufn <= '1';
out178_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(114) = '1' then
-- Next state
state_next(196) <= '1';
-- Next values for buffered outputs
out328_bufn <= '1';
out284_bufn <= '1';
out155_bufn <= '1';
-- Assignment of non-buffered outputs
out142 <= '1';
out396 <= '1';
out286 <= '1';
end if;
if state_cur(115) = '1' then
-- Next state
state_next(105) <= '1';
-- Next values for buffered outputs
out364_bufn <= '1';
out25_bufn <= '1';
out136_bufn <= '1';
out134_bufn <= '1';
out361_bufn <= '1';
-- Assignment of non-buffered outputs
out46 <= '1';
out21 <= '1';
out142 <= '1';
out398 <= '1';
out363 <= '1';
end if;
if state_cur(116) = '1' then
-- Next state
state_next(120) <= '1';
-- Next values for buffered outputs
out407_bufn <= '1';
out281_bufn <= '1';
out168_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(117) = '1' then
-- Next state
state_next(211) <= '1';
-- Next values for buffered outputs
out458_bufn <= '1';
out475_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(118) = '1' then
-- Next state
state_next(151) <= '1';
-- Next values for buffered outputs
out333_bufn <= '1';
out31_bufn <= '1';
out361_bufn <= '1';
-- Assignment of non-buffered outputs
out42 <= '1';
out21 <= '1';
out402 <= '1';
out363 <= '1';
end if;
if state_cur(119) = '1' then
-- Next state
state_next(150) <= '1';
-- Next values for buffered outputs
out366_bufn <= '1';
out35_bufn <= '1';
out361_bufn <= '1';
-- Assignment of non-buffered outputs
out406 <= '1';
out38 <= '1';
out21 <= '1';
end if;
if state_cur(120) = '1' then
-- Next state
state_next(121) <= '1';
-- Next values for buffered outputs
out409_bufn <= '1';
out281_bufn <= '1';
out408_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(121) = '1' then
-- Next state
state_next(139) <= '1';
-- Next values for buffered outputs
out438_bufn <= '1';
out284_bufn <= '1';
out431_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(122) = '1' then
-- Next state
state_next(123) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out120 <= '1';
out118 <= '1';
out116 <= '1';
out114 <= '1';
out112 <= '1';
out412 <= '1';
out411 <= '1';
end if;
if state_cur(123) = '1' then
-- Next state
state_next(212) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out103 <= '1';
out105 <= '1';
out99 <= '1';
out101 <= '1';
end if;
if state_cur(124) = '1' then
-- Next state
state_next(81) <= '1';
-- Next values for buffered outputs
out288_bufn <= '1';
out287_bufn <= '1';
-- Assignment of non-buffered outputs
out120 <= '1';
out60 <= '1';
out283 <= '1';
end if;
if state_cur(125) = '1' then
-- Next state
state_next(128) <= '1';
-- Next values for buffered outputs
out422_bufn <= '1';
out287_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(126) = '1' then
-- Next state
state_next(125) <= '1';
-- Next values for buffered outputs
out414_bufn <= '1';
out294_bufn <= '1';
-- Assignment of non-buffered outputs
out416 <= '1';
out38 <= '1';
out286 <= '1';
end if;
if state_cur(127) = '1' then
-- Next state
state_next(169) <= '1';
-- Next values for buffered outputs
out417_bufn <= '1';
out483_bufn <= '1';
out482_bufn <= '1';
out318_bufn <= '1';
-- Assignment of non-buffered outputs
out112 <= '1';
out419 <= '1';
out283 <= '1';
end if;
if state_cur(128) = '1' then
-- Next state
state_next(124) <= '1';
-- Next values for buffered outputs
out413_bufn <= '1';
out289_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(129) = '1' then
-- Next state
state_next(130) <= '1';
-- Next values for buffered outputs
out426_bufn <= '1';
out27_bufn <= '1';
out141_bufn <= '1';
out410_bufn <= '1';
-- Assignment of non-buffered outputs
out44 <= '1';
out21 <= '1';
out423 <= '1';
out412 <= '1';
end if;
if state_cur(130) = '1' then
-- Next state
state_next(143) <= '1';
-- Next values for buffered outputs
out435_bufn <= '1';
out25_bufn <= '1';
out136_bufn <= '1';
out134_bufn <= '1';
out410_bufn <= '1';
-- Assignment of non-buffered outputs
out46 <= '1';
out21 <= '1';
out142 <= '1';
out425 <= '1';
out412 <= '1';
end if;
if state_cur(131) = '1' then
-- Next state
state_next(102) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out103 <= '1';
out105 <= '1';
out99 <= '1';
out101 <= '1';
end if;
if state_cur(132) = '1' then
-- Next state
state_next(144) <= '1';
-- Next values for buffered outputs
out111_bufn <= '1';
-- Assignment of non-buffered outputs
out114 <= '1';
out429 <= '1';
out52 <= '1';
out286 <= '1';
end if;
if state_cur(133) = '1' then
-- Next state
state_next(237) <= '1';
-- Next values for buffered outputs
out475_bufn <= '1';
out20_bufn <= '1';
out124_bufn <= '1';
out122_bufn <= '1';
out361_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out21 <= '1';
out130 <= '1';
out430 <= '1';
out363 <= '1';
end if;
if state_cur(134) = '1' then
-- Next state
state_next(227) <= '1';
-- Next values for buffered outputs
out496_bufn <= '1';
out284_bufn <= '1';
out263_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(135) = '1' then
-- Next state
state_next(117) <= '1';
-- Next values for buffered outputs
out352_bufn <= '1';
out281_bufn <= '1';
out401_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(136) = '1' then
-- Next state
state_next(135) <= '1';
-- Next values for buffered outputs
out434_bufn <= '1';
out281_bufn <= '1';
out165_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(137) = '1' then
-- Next state
state_next(228) <= '1';
-- Next values for buffered outputs
out463_bufn <= '1';
out284_bufn <= '1';
out260_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(138) = '1' then
-- Next state
state_next(137) <= '1';
-- Next values for buffered outputs
out436_bufn <= '1';
out281_bufn <= '1';
out435_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(139) = '1' then
-- Next state
state_next(229) <= '1';
-- Next values for buffered outputs
out495_bufn <= '1';
out284_bufn <= '1';
out204_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(140) = '1' then
-- Next state
state_next(126) <= '1';
-- Next values for buffered outputs
out324_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(141) = '1' then
-- Next state
state_next(142) <= '1';
-- Next values for buffered outputs
out122_bufn <= '1';
out134_bufn <= '1';
out400_bufn <= '1';
out327_bufn <= '1';
-- Assignment of non-buffered outputs
out116 <= '1';
out283 <= '1';
end if;
if state_cur(142) = '1' then
-- Next state
state_next(168) <= '1';
-- Next values for buffered outputs
out481_bufn <= '1';
out351_bufn <= '1';
-- Assignment of non-buffered outputs
out54 <= '1';
out123 <= '1';
out135 <= '1';
out114 <= '1';
out286 <= '1';
end if;
if state_cur(143) = '1' then
-- Next state
state_next(149) <= '1';
-- Next values for buffered outputs
out451_bufn <= '1';
out23_bufn <= '1';
out129_bufn <= '1';
out410_bufn <= '1';
-- Assignment of non-buffered outputs
out48 <= '1';
out21 <= '1';
out137 <= '1';
out135 <= '1';
out441 <= '1';
out412 <= '1';
end if;
if state_cur(144) = '1' then
-- Next state
state_next(178) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out112 <= '1';
end if;
if state_cur(145) = '1' then
-- Next state
state_next(99) <= '1';
-- Next values for buffered outputs
out49_bufn <= '1';
-- Assignment of non-buffered outputs
out60 <= '1';
out443 <= '1';
out58 <= '1';
out56 <= '1';
out54 <= '1';
end if;
if state_cur(146) = '1' then
-- Next state
state_next(100) <= '1';
-- Next values for buffered outputs
out124_bufn <= '1';
out349_bufn <= '1';
out287_bufn <= '1';
-- Assignment of non-buffered outputs
out445 <= '1';
out50 <= '1';
out283 <= '1';
end if;
if state_cur(147) = '1' then
-- Next state
state_next(78) <= '1';
-- Next values for buffered outputs
out278_bufn <= '1';
out36_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out46 <= '1';
out52 <= '1';
out48 <= '1';
out44 <= '1';
out42 <= '1';
out40 <= '1';
out38 <= '1';
end if;
if state_cur(148) = '1' then
if rtmcmp148 = '1' then
-- Next state
state_next(172) <= '1';
-- Next values for buffered outputs
out296_bufn <= '1';
out284_bufn <= '1';
out220_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out103 <= '1';
out125 <= '1';
out99 <= '1';
out123 <= '1';
out283 <= '1';
else -- Stay in the current state
state_next(148) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out446_bufn <= '1';
out413_bufn <= '1';
out281_bufn <= '1';
out250_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out447 <= '1';
end if;
if state_cur(149) = '1' then
-- Next state
state_next(226) <= '1';
-- Next values for buffered outputs
out354_bufn <= '1';
out20_bufn <= '1';
out124_bufn <= '1';
out122_bufn <= '1';
out410_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out21 <= '1';
out130 <= '1';
out450 <= '1';
out412 <= '1';
end if;
if state_cur(150) = '1' then
-- Next state
state_next(118) <= '1';
-- Next values for buffered outputs
out404_bufn <= '1';
out361_bufn <= '1';
-- Assignment of non-buffered outputs
out454 <= '1';
out40 <= '1';
out21 <= '1';
out363 <= '1';
end if;
if state_cur(151) = '1' then
-- Next state
state_next(115) <= '1';
-- Next values for buffered outputs
out393_bufn <= '1';
out27_bufn <= '1';
out141_bufn <= '1';
out361_bufn <= '1';
-- Assignment of non-buffered outputs
out44 <= '1';
out21 <= '1';
out455 <= '1';
out363 <= '1';
end if;
if state_cur(152) = '1' then
-- Next state
state_next(230) <= '1';
-- Next values for buffered outputs
out512_bufn <= '1';
out281_bufn <= '1';
out171_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(153) = '1' then
-- Next state
state_next(114) <= '1';
-- Next values for buffered outputs
out292_bufn <= '1';
out284_bufn <= '1';
out222_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(154) = '1' then
-- Next state
state_next(44) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out372 <= '1';
end if;
if state_cur(155) = '1' then
-- Next state
state_next(232) <= '1';
-- Next values for buffered outputs
out517_bufn <= '1';
out284_bufn <= '1';
out207_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(156) = '1' then
-- Next state
state_next(104) <= '1';
-- Next values for buffered outputs
out129_bufn <= '1';
out357_bufn <= '1';
out354_bufn <= '1';
out353_bufn <= '1';
out327_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(157) = '1' then
-- Next state
state_next(156) <= '1';
-- Next values for buffered outputs
out458_bufn <= '1';
out324_bufn <= '1';
-- Assignment of non-buffered outputs
out56 <= '1';
out137 <= '1';
out116 <= '1';
out283 <= '1';
end if;
if state_cur(158) = '1' then
-- Next state
state_next(157) <= '1';
-- Next values for buffered outputs
out136_bufn <= '1';
out434_bufn <= '1';
out314_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(159) = '1' then
-- Next state
state_next(158) <= '1';
-- Next values for buffered outputs
out459_bufn <= '1';
out291_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(160) = '1' then
-- Next state
state_next(189) <= '1';
-- Next values for buffered outputs
out525_bufn <= '1';
out281_bufn <= '1';
out245_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(161) = '1' then
-- Next state
state_next(106) <= '1';
-- Next values for buffered outputs
out288_bufn <= '1';
out284_bufn <= '1';
out276_bufn <= '1';
-- Assignment of non-buffered outputs
out60 <= '1';
out58 <= '1';
out56 <= '1';
out54 <= '1';
out462 <= '1';
out283 <= '1';
end if;
if state_cur(162) = '1' then
-- Next state
state_next(159) <= '1';
-- Next values for buffered outputs
out460_bufn <= '1';
out289_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(163) = '1' then
-- Next state
state_next(162) <= '1';
-- Next values for buffered outputs
out463_bufn <= '1';
out287_bufn <= '1';
-- Assignment of non-buffered outputs
out118 <= '1';
out58 <= '1';
out465 <= '1';
out48 <= '1';
out283 <= '1';
end if;
if state_cur(164) = '1' then
-- Next state
state_next(163) <= '1';
-- Next values for buffered outputs
out57_bufn <= '1';
out408_bufn <= '1';
out464_bufn <= '1';
out294_bufn <= '1';
-- Assignment of non-buffered outputs
out120 <= '1';
out60 <= '1';
out103 <= '1';
out105 <= '1';
out283 <= '1';
end if;
if state_cur(165) = '1' then
-- Next state
state_next(166) <= '1';
-- Next values for buffered outputs
out273_bufn <= '1';
out343_bufn <= '1';
out281_bufn <= '1';
out181_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(166) = '1' then
-- Next state
state_next(215) <= '1';
-- Next values for buffered outputs
out562_bufn <= '1';
out342_bufn <= '1';
out284_bufn <= '1';
out404_bufn <= '1';
-- Assignment of non-buffered outputs
out467 <= '1';
out142 <= '1';
out283 <= '1';
end if;
if state_cur(167) = '1' then
if rtmcmp167 = '1' then
-- Next state
state_next(164) <= '1';
-- Next values for buffered outputs
out409_bufn <= '1';
out351_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out130 <= '1';
out101 <= '1';
out112 <= '1';
out142 <= '1';
out99 <= '1';
out54 <= '1';
out135 <= '1';
out123 <= '1';
out114 <= '1';
out286 <= '1';
else -- Stay in the current state
state_next(167) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out475_bufn <= '1';
out257_bufn <= '1';
out472_bufn <= '1';
out451_bufn <= '1';
out468_bufn <= '1';
out327_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out469 <= '1';
end if;
if state_cur(168) = '1' then
-- Next state
state_next(132) <= '1';
-- Next values for buffered outputs
out357_bufn <= '1';
out428_bufn <= '1';
out327_bufn <= '1';
-- Assignment of non-buffered outputs
out120 <= '1';
out283 <= '1';
end if;
if state_cur(169) = '1' then
-- Next state
state_next(225) <= '1';
-- Next values for buffered outputs
out554_bufn <= '1';
out284_bufn <= '1';
out333_bufn <= '1';
-- Assignment of non-buffered outputs
out137 <= '1';
out135 <= '1';
out484 <= '1';
out283 <= '1';
end if;
if state_cur(170) = '1' then
-- Next state
state_next(152) <= '1';
-- Next values for buffered outputs
out353_bufn <= '1';
out284_bufn <= '1';
out138_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(171) = '1' then
-- Next state
state_next(167) <= '1';
-- Next values for buffered outputs
out475_bufn <= '1';
out257_bufn <= '1';
out472_bufn <= '1';
out451_bufn <= '1';
out468_bufn <= '1';
out327_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(172) = '1' then
-- Next state
state_next(187) <= '1';
-- Next values for buffered outputs
out521_bufn <= '1';
out284_bufn <= '1';
out150_bufn <= '1';
-- Assignment of non-buffered outputs
out137 <= '1';
out135 <= '1';
out488 <= '1';
out286 <= '1';
end if;
if state_cur(173) = '1' then
-- Next state
state_next(84) <= '1';
-- Next values for buffered outputs
out293_bufn <= '1';
out281_bufn <= '1';
out174_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(174) = '1' then
if rtmcmp174 = '1' then
-- Next state
state_next(171) <= '1';
-- Next values for buffered outputs
out438_bufn <= '1';
out324_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out125 <= '1';
out137 <= '1';
out116 <= '1';
out56 <= '1';
out283 <= '1';
else -- Stay in the current state
state_next(174) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out229_bufn <= '1';
out357_bufn <= '1';
out407_bufn <= '1';
out314_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out491 <= '1';
end if;
if state_cur(175) = '1' then
-- Next state
state_next(174) <= '1';
-- Next values for buffered outputs
out229_bufn <= '1';
out357_bufn <= '1';
out407_bufn <= '1';
out314_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(176) = '1' then
-- Next state
state_next(175) <= '1';
-- Next values for buffered outputs
out495_bufn <= '1';
out291_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(177) = '1' then
-- Next state
state_next(176) <= '1';
-- Next values for buffered outputs
out437_bufn <= '1';
out289_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(178) = '1' then
-- Next state
state_next(145) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out103 <= '1';
out105 <= '1';
out99 <= '1';
out101 <= '1';
end if;
if state_cur(179) = '1' then
-- Next state
state_next(177) <= '1';
-- Next values for buffered outputs
out496_bufn <= '1';
out287_bufn <= '1';
-- Assignment of non-buffered outputs
out58 <= '1';
out118 <= '1';
out498 <= '1';
out46 <= '1';
out283 <= '1';
end if;
if state_cur(180) = '1' then
-- Next state
state_next(179) <= '1';
-- Next values for buffered outputs
out57_bufn <= '1';
out497_bufn <= '1';
out436_bufn <= '1';
out294_bufn <= '1';
-- Assignment of non-buffered outputs
out120 <= '1';
out60 <= '1';
out103 <= '1';
out105 <= '1';
out283 <= '1';
end if;
if state_cur(181) = '1' then
if rtmcmp181 = '1' then
-- Next state
state_next(180) <= '1';
-- Next values for buffered outputs
out499_bufn <= '1';
out351_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out130 <= '1';
out101 <= '1';
out112 <= '1';
out142 <= '1';
out99 <= '1';
out54 <= '1';
out135 <= '1';
out123 <= '1';
out114 <= '1';
out286 <= '1';
else -- Stay in the current state
state_next(181) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out260_bufn <= '1';
out500_bufn <= '1';
out435_bufn <= '1';
out395_bufn <= '1';
out327_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out501 <= '1';
end if;
if state_cur(182) = '1' then
-- Next state
state_next(181) <= '1';
-- Next values for buffered outputs
out260_bufn <= '1';
out500_bufn <= '1';
out435_bufn <= '1';
out395_bufn <= '1';
out327_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(183) = '1' then
if rtmcmp183 = '1' then
-- Next state
state_next(182) <= '1';
-- Next values for buffered outputs
out457_bufn <= '1';
out324_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out125 <= '1';
out137 <= '1';
out116 <= '1';
out56 <= '1';
out283 <= '1';
else -- Stay in the current state
state_next(183) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out472_bufn <= '1';
out401_bufn <= '1';
out512_bufn <= '1';
out314_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out513 <= '1';
end if;
if state_cur(184) = '1' then
-- Next state
state_next(183) <= '1';
-- Next values for buffered outputs
out472_bufn <= '1';
out401_bufn <= '1';
out512_bufn <= '1';
out314_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(185) = '1' then
-- Next state
state_next(92) <= '1';
-- Next values for buffered outputs
out323_bufn <= '1';
out284_bufn <= '1';
out217_bufn <= '1';
-- Assignment of non-buffered outputs
out105 <= '1';
out101 <= '1';
out283 <= '1';
end if;
if state_cur(186) = '1' then
-- Next state
state_next(107) <= '1';
-- Next values for buffered outputs
out366_bufn <= '1';
out315_bufn <= '1';
out281_bufn <= '1';
out183_bufn <= '1';
-- Assignment of non-buffered outputs
out142 <= '1';
out519 <= '1';
out286 <= '1';
end if;
if state_cur(187) = '1' then
-- Next state
state_next(185) <= '1';
-- Next values for buffered outputs
out290_bufn <= '1';
out281_bufn <= '1';
out248_bufn <= '1';
-- Assignment of non-buffered outputs
out120 <= '1';
out118 <= '1';
out116 <= '1';
out114 <= '1';
out130 <= '1';
out522 <= '1';
out286 <= '1';
end if;
if state_cur(188) = '1' then
-- Next state
state_next(184) <= '1';
-- Next values for buffered outputs
out517_bufn <= '1';
out291_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(189) = '1' then
-- Next state
state_next(190) <= '1';
-- Next values for buffered outputs
out526_bufn <= '1';
out284_bufn <= '1';
out213_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(190) = '1' then
-- Next state
state_next(173) <= '1';
-- Next values for buffered outputs
out468_bufn <= '1';
out284_bufn <= '1';
out143_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(191) = '1' then
-- Next state
state_next(188) <= '1';
-- Next values for buffered outputs
out524_bufn <= '1';
out289_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(192) = '1' then
-- Next state
state_next(191) <= '1';
-- Next values for buffered outputs
out487_bufn <= '1';
out287_bufn <= '1';
-- Assignment of non-buffered outputs
out58 <= '1';
out118 <= '1';
out527 <= '1';
out44 <= '1';
out283 <= '1';
end if;
if state_cur(193) = '1' then
-- Next state
state_next(192) <= '1';
-- Next values for buffered outputs
out57_bufn <= '1';
out312_bufn <= '1';
out433_bufn <= '1';
out294_bufn <= '1';
-- Assignment of non-buffered outputs
out120 <= '1';
out60 <= '1';
out103 <= '1';
out105 <= '1';
out283 <= '1';
end if;
if state_cur(194) = '1' then
if rtmcmp194 = '1' then
-- Next state
state_next(193) <= '1';
-- Next values for buffered outputs
out351_bufn <= '1';
out313_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out130 <= '1';
out101 <= '1';
out112 <= '1';
out142 <= '1';
out99 <= '1';
out54 <= '1';
out123 <= '1';
out135 <= '1';
out114 <= '1';
out286 <= '1';
else -- Stay in the current state
state_next(194) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out263_bufn <= '1';
out531_bufn <= '1';
out497_bufn <= '1';
out521_bufn <= '1';
out327_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out528 <= '1';
end if;
if state_cur(195) = '1' then
-- Next state
state_next(194) <= '1';
-- Next values for buffered outputs
out263_bufn <= '1';
out531_bufn <= '1';
out497_bufn <= '1';
out521_bufn <= '1';
out327_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(196) = '1' then
-- Next state
state_next(221) <= '1';
-- Next values for buffered outputs
out281_bufn <= '1';
-- Assignment of non-buffered outputs
out130 <= '1';
out540 <= '1';
out286 <= '1';
end if;
if state_cur(197) = '1' then
if rtmcmp197 = '1' then
-- Next state
state_next(195) <= '1';
-- Next values for buffered outputs
out394_bufn <= '1';
out324_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out137 <= '1';
out125 <= '1';
out116 <= '1';
out56 <= '1';
out283 <= '1';
else -- Stay in the current state
state_next(197) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out500_bufn <= '1';
out435_bufn <= '1';
out314_bufn <= '1';
out293_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out542 <= '1';
end if;
if state_cur(198) = '1' then
-- Next state
state_next(197) <= '1';
-- Next values for buffered outputs
out500_bufn <= '1';
out435_bufn <= '1';
out314_bufn <= '1';
out293_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(199) = '1' then
-- Next state
state_next(198) <= '1';
-- Next values for buffered outputs
out326_bufn <= '1';
out291_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(200) = '1' then
-- Next state
state_next(199) <= '1';
-- Next values for buffered outputs
out341_bufn <= '1';
out289_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(201) = '1' then
-- Next state
state_next(200) <= '1';
-- Next values for buffered outputs
out287_bufn <= '1';
out285_bufn <= '1';
-- Assignment of non-buffered outputs
out58 <= '1';
out118 <= '1';
out544 <= '1';
out42 <= '1';
out283 <= '1';
end if;
if state_cur(202) = '1' then
-- Next state
state_next(201) <= '1';
-- Next values for buffered outputs
out57_bufn <= '1';
out318_bufn <= '1';
out322_bufn <= '1';
out294_bufn <= '1';
-- Assignment of non-buffered outputs
out120 <= '1';
out60 <= '1';
out103 <= '1';
out105 <= '1';
out283 <= '1';
end if;
if state_cur(203) = '1' then
if rtmcmp203 = '1' then
-- Next state
state_next(202) <= '1';
-- Next values for buffered outputs
out483_bufn <= '1';
out351_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out130 <= '1';
out101 <= '1';
out142 <= '1';
out112 <= '1';
out99 <= '1';
out54 <= '1';
out123 <= '1';
out135 <= '1';
out114 <= '1';
out286 <= '1';
else -- Stay in the current state
state_next(203) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out393_bufn <= '1';
out346_bufn <= '1';
out344_bufn <= '1';
out312_bufn <= '1';
out518_bufn <= '1';
out327_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out545 <= '1';
end if;
if state_cur(204) = '1' then
-- Next state
state_next(203) <= '1';
-- Next values for buffered outputs
out393_bufn <= '1';
out346_bufn <= '1';
out344_bufn <= '1';
out312_bufn <= '1';
out518_bufn <= '1';
out327_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(205) = '1' then
if rtmcmp205 = '1' then
-- Next state
state_next(204) <= '1';
-- Next values for buffered outputs
out554_bufn <= '1';
out324_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out137 <= '1';
out125 <= '1';
out116 <= '1';
out56 <= '1';
out283 <= '1';
else -- Stay in the current state
state_next(205) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out531_bufn <= '1';
out426_bufn <= '1';
out461_bufn <= '1';
out314_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out555 <= '1';
end if;
if state_cur(206) = '1' then
-- Next state
state_next(205) <= '1';
-- Next values for buffered outputs
out531_bufn <= '1';
out426_bufn <= '1';
out461_bufn <= '1';
out314_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(207) = '1' then
-- Next state
state_next(206) <= '1';
-- Next values for buffered outputs
out526_bufn <= '1';
out291_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(208) = '1' then
-- Next state
state_next(207) <= '1';
-- Next values for buffered outputs
out525_bufn <= '1';
out289_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(209) = '1' then
-- Next state
state_next(208) <= '1';
-- Next values for buffered outputs
out466_bufn <= '1';
out287_bufn <= '1';
-- Assignment of non-buffered outputs
out58 <= '1';
out118 <= '1';
out559 <= '1';
out40 <= '1';
out283 <= '1';
end if;
if state_cur(210) = '1' then
-- Next state
state_next(209) <= '1';
-- Next values for buffered outputs
out57_bufn <= '1';
out417_bufn <= '1';
out294_bufn <= '1';
out282_bufn <= '1';
-- Assignment of non-buffered outputs
out120 <= '1';
out60 <= '1';
out103 <= '1';
out105 <= '1';
out283 <= '1';
end if;
if state_cur(211) = '1' then
-- Next state
state_next(224) <= '1';
-- Next values for buffered outputs
out459_bufn <= '1';
out284_bufn <= '1';
out201_bufn <= '1';
-- Assignment of non-buffered outputs
out560 <= '1';
out286 <= '1';
end if;
if state_cur(212) = '1' then
-- Next state
state_next(147) <= '1';
-- Next values for buffered outputs
out49_bufn <= '1';
-- Assignment of non-buffered outputs
out60 <= '1';
out561 <= '1';
out58 <= '1';
out56 <= '1';
out54 <= '1';
end if;
if state_cur(213) = '1' then
-- Next state
state_next(134) <= '1';
-- Next values for buffered outputs
out433_bufn <= '1';
out281_bufn <= '1';
out426_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(214) = '1' then
-- Next state
state_next(140) <= '1';
-- Next values for buffered outputs
out351_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(215) = '1' then
if rtmcmp215 = '1' then
-- Next state
state_next(127) <= '1';
-- Next values for buffered outputs
out404_bufn <= '1';
out418_bufn <= '1';
out281_bufn <= '1';
out417_bufn <= '1';
-- Last cycle of current state: assignment of non-buffered outputs
out125 <= '1';
out123 <= '1';
out286 <= '1';
else -- Stay in the current state
state_next(215) <= '1';
rtmcounter0_next <= rtmcounter0 + 1;
-- Maintain buffered outputs
out562_bufn <= '1';
out342_bufn <= '1';
out284_bufn <= '1';
out404_bufn <= '1';
end if;
-- Assignment of non-buffered outputs;
out563 <= '1';
end if;
if state_cur(216) = '1' then
-- Next state
state_next(214) <= '1';
-- Next values for buffered outputs
out482_bufn <= '1';
out481_bufn <= '1';
out357_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(217) = '1' then
-- Next state
state_next(216) <= '1';
-- Next values for buffered outputs
out444_bufn <= '1';
out281_bufn <= '1';
out354_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(218) = '1' then
-- Next state
state_next(217) <= '1';
-- Next values for buffered outputs
out566_bufn <= '1';
out281_bufn <= '1';
out229_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(219) = '1' then
-- Next state
state_next(218) <= '1';
-- Next values for buffered outputs
out440_bufn <= '1';
out281_bufn <= '1';
out162_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(220) = '1' then
-- Next state
state_next(219) <= '1';
-- Next values for buffered outputs
out349_bufn <= '1';
out284_bufn <= '1';
out257_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(221) = '1' then
-- Next state
state_next(223) <= '1';
-- Next values for buffered outputs
out325_bufn <= '1';
out284_bufn <= '1';
out366_bufn <= '1';
-- Assignment of non-buffered outputs
out112 <= '1';
out567 <= '1';
out283 <= '1';
end if;
if state_cur(222) = '1' then
-- Next state
state_next(220) <= '1';
-- Next values for buffered outputs
out464_bufn <= '1';
out281_bufn <= '1';
out451_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(223) = '1' then
-- Next state
state_next(161) <= '1';
-- Next values for buffered outputs
out57_bufn <= '1';
out414_bufn <= '1';
out446_bufn <= '1';
-- Assignment of non-buffered outputs
out105 <= '1';
out103 <= '1';
out101 <= '1';
out99 <= '1';
out286 <= '1';
end if;
if state_cur(224) = '1' then
-- Next state
state_next(222) <= '1';
-- Next values for buffered outputs
out460_bufn <= '1';
out281_bufn <= '1';
out232_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(225) = '1' then
-- Next state
state_next(79) <= '1';
-- Next values for buffered outputs
out282_bufn <= '1';
out281_bufn <= '1';
out280_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(226) = '1' then
-- Next state
state_next(122) <= '1';
-- Next values for buffered outputs
out111_bufn <= '1';
out410_bufn <= '1';
-- Assignment of non-buffered outputs
out52 <= '1';
out21 <= '1';
out125 <= '1';
out123 <= '1';
out570 <= '1';
out412 <= '1';
end if;
if state_cur(227) = '1' then
-- Next state
state_next(116) <= '1';
-- Next values for buffered outputs
out400_bufn <= '1';
out284_bufn <= '1';
out131_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(228) = '1' then
-- Next state
state_next(136) <= '1';
-- Next values for buffered outputs
out428_bufn <= '1';
out284_bufn <= '1';
out126_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(229) = '1' then
-- Next state
state_next(138) <= '1';
-- Next values for buffered outputs
out437_bufn <= '1';
out281_bufn <= '1';
out235_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(230) = '1' then
-- Next state
state_next(231) <= '1';
-- Next values for buffered outputs
out499_bufn <= '1';
out281_bufn <= '1';
out497_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(231) = '1' then
-- Next state
state_next(155) <= '1';
-- Next values for buffered outputs
out457_bufn <= '1';
out284_bufn <= '1';
out364_bufn <= '1';
-- Assignment of non-buffered outputs
out283 <= '1';
end if;
if state_cur(232) = '1' then
-- Next state
state_next(213) <= '1';
-- Next values for buffered outputs
out524_bufn <= '1';
out281_bufn <= '1';
out238_bufn <= '1';
-- Assignment of non-buffered outputs
out286 <= '1';
end if;
if state_cur(233) = '1' then
-- Next state
state_next(141) <= '1';
-- Next values for buffered outputs
out440_bufn <= '1';
out314_bufn <= '1';
-- Assignment of non-buffered outputs
out118 <= '1';
out283 <= '1';
end if;
if state_cur(234) = '1' then
-- Next state
state_next(129) <= '1';
-- Next values for buffered outputs
out346_bufn <= '1';
out31_bufn <= '1';
out410_bufn <= '1';
-- Assignment of non-buffered outputs
out42 <= '1';
out21 <= '1';
out572 <= '1';
out412 <= '1';
end if;
if state_cur(235) = '1' then
-- Next state
state_next(131) <= '1';
-- Next values for buffered outputs
-- Assignment of non-buffered outputs
out120 <= '1';
out118 <= '1';
out116 <= '1';
out114 <= '1';
out112 <= '1';
out575 <= '1';
out363 <= '1';
end if;
if state_cur(236) = '1' then
-- Next state
state_next(234) <= '1';
-- Next values for buffered outputs
out280_bufn <= '1';
out410_bufn <= '1';
-- Assignment of non-buffered outputs
out577 <= '1';
out40 <= '1';
out21 <= '1';
out412 <= '1';
end if;
if state_cur(237) = '1' then
-- Next state
state_next(235) <= '1';
-- Next values for buffered outputs
out111_bufn <= '1';
out361_bufn <= '1';
-- Assignment of non-buffered outputs
out52 <= '1';
out21 <= '1';
out125 <= '1';
out123 <= '1';
out578 <= '1';
out363 <= '1';
end if;
if state_cur(238) = '1' then
-- Next state
state_next(236) <= '1';
-- Next values for buffered outputs
out562_bufn <= '1';
out35_bufn <= '1';
out410_bufn <= '1';
-- Assignment of non-buffered outputs
out580 <= '1';
out38 <= '1';
out21 <= '1';
end if;
if state_cur(239) = '1' then
-- Next state
state_next(238) <= '1';
-- Next values for buffered outputs
out446_bufn <= '1';
out36_bufn <= '1';
-- Assignment of non-buffered outputs
out50 <= '1';
out46 <= '1';
out52 <= '1';
out48 <= '1';
out44 <= '1';
out42 <= '1';
out40 <= '1';
out38 <= '1';
end if;
if state_cur(240) = '1' then
-- Next state
state_next(165) <= '1';
-- Next values for buffered outputs
out466_bufn <= '1';
out284_bufn <= '1';
out273_bufn <= '1';
-- Assignment of non-buffered outputs
out581 <= '1';
out130 <= '1';
out283 <= '1';
end if;
-- Reset input
if reset = '1' then
-- Set the reset state
state_next <= (7 => '1', others => '0');
-- Note: Resetting all buffers for outputs here is not necessary.
-- It would cost hardware. They will be reset at the next clock front.
-- Retiming: counters
rtmcounter0_next <= (others => '0');
-- Reset state: set the buffered outputs
end if;
end process;
-- Assignment of buffered outputs
out122 <= out122_buf;
out36 <= out36_buf;
out49 <= out49_buf;
out35 <= out35_buf;
out27 <= out27_buf;
out16 <= out16_buf;
out25 <= out25_buf;
out20 <= out20_buf;
out57 <= out57_buf;
out23 <= out23_buf;
out136 <= out136_buf;
out0 <= out0_buf;
out134 <= out134_buf;
out13 <= out13_buf;
out131 <= out131_buf;
out129 <= out129_buf;
out111 <= out111_buf;
out31 <= out31_buf;
out126 <= out126_buf;
out106 <= out106_buf;
out124 <= out124_buf;
out138 <= out138_buf;
out141 <= out141_buf;
out143 <= out143_buf;
out146 <= out146_buf;
out150 <= out150_buf;
out153 <= out153_buf;
out155 <= out155_buf;
out158 <= out158_buf;
out162 <= out162_buf;
out165 <= out165_buf;
out168 <= out168_buf;
out171 <= out171_buf;
out174 <= out174_buf;
out178 <= out178_buf;
out181 <= out181_buf;
out183 <= out183_buf;
out197 <= out197_buf;
out201 <= out201_buf;
out204 <= out204_buf;
out207 <= out207_buf;
out210 <= out210_buf;
out213 <= out213_buf;
out217 <= out217_buf;
out220 <= out220_buf;
out222 <= out222_buf;
out225 <= out225_buf;
out229 <= out229_buf;
out232 <= out232_buf;
out235 <= out235_buf;
out238 <= out238_buf;
out241 <= out241_buf;
out245 <= out245_buf;
out248 <= out248_buf;
out250 <= out250_buf;
out253 <= out253_buf;
out257 <= out257_buf;
out260 <= out260_buf;
out263 <= out263_buf;
out266 <= out266_buf;
out269 <= out269_buf;
out273 <= out273_buf;
out276 <= out276_buf;
out278 <= out278_buf;
out280 <= out280_buf;
out281 <= out281_buf;
out282 <= out282_buf;
out284 <= out284_buf;
out285 <= out285_buf;
out287 <= out287_buf;
out288 <= out288_buf;
out289 <= out289_buf;
out290 <= out290_buf;
out291 <= out291_buf;
out292 <= out292_buf;
out293 <= out293_buf;
out294 <= out294_buf;
out295 <= out295_buf;
out296 <= out296_buf;
out312 <= out312_buf;
out313 <= out313_buf;
out314 <= out314_buf;
out315 <= out315_buf;
out318 <= out318_buf;
out322 <= out322_buf;
out323 <= out323_buf;
out324 <= out324_buf;
out325 <= out325_buf;
out326 <= out326_buf;
out327 <= out327_buf;
out328 <= out328_buf;
out333 <= out333_buf;
out341 <= out341_buf;
out342 <= out342_buf;
out343 <= out343_buf;
out344 <= out344_buf;
out346 <= out346_buf;
out349 <= out349_buf;
out351 <= out351_buf;
out352 <= out352_buf;
out353 <= out353_buf;
out354 <= out354_buf;
out357 <= out357_buf;
out361 <= out361_buf;
out364 <= out364_buf;
out366 <= out366_buf;
out371 <= out371_buf;
out393 <= out393_buf;
out394 <= out394_buf;
out395 <= out395_buf;
out400 <= out400_buf;
out401 <= out401_buf;
out404 <= out404_buf;
out407 <= out407_buf;
out408 <= out408_buf;
out409 <= out409_buf;
out410 <= out410_buf;
out413 <= out413_buf;
out414 <= out414_buf;
out417 <= out417_buf;
out418 <= out418_buf;
out422 <= out422_buf;
out426 <= out426_buf;
out428 <= out428_buf;
out431 <= out431_buf;
out433 <= out433_buf;
out434 <= out434_buf;
out435 <= out435_buf;
out436 <= out436_buf;
out437 <= out437_buf;
out438 <= out438_buf;
out440 <= out440_buf;
out444 <= out444_buf;
out446 <= out446_buf;
out451 <= out451_buf;
out457 <= out457_buf;
out458 <= out458_buf;
out459 <= out459_buf;
out460 <= out460_buf;
out461 <= out461_buf;
out463 <= out463_buf;
out464 <= out464_buf;
out466 <= out466_buf;
out468 <= out468_buf;
out472 <= out472_buf;
out475 <= out475_buf;
out481 <= out481_buf;
out482 <= out482_buf;
out483 <= out483_buf;
out487 <= out487_buf;
out495 <= out495_buf;
out496 <= out496_buf;
out497 <= out497_buf;
out499 <= out499_buf;
out500 <= out500_buf;
out512 <= out512_buf;
out517 <= out517_buf;
out518 <= out518_buf;
out521 <= out521_buf;
out524 <= out524_buf;
out525 <= out525_buf;
out526 <= out526_buf;
out531 <= out531_buf;
out554 <= out554_buf;
out562 <= out562_buf;
out566 <= out566_buf;
-- Retiming: the comparators
rtmcmp90 <= '1' when state_cur(90) = '1' and rtmcounter0 = 1 else '0';
rtmcmp95 <= '1' when state_cur(95) = '1' and rtmcounter0 = 1 else '0';
rtmcmp98 <= '1' when state_cur(98) = '1' and rtmcounter0 = 1 else '0';
rtmcmp104 <= '1' when state_cur(104) = '1' and rtmcounter0 = 1 else '0';
rtmcmp148 <= '1' when state_cur(148) = '1' and rtmcounter0 = 1 else '0';
rtmcmp167 <= '1' when state_cur(167) = '1' and rtmcounter0 = 1 else '0';
rtmcmp174 <= '1' when state_cur(174) = '1' and rtmcounter0 = 1 else '0';
rtmcmp181 <= '1' when state_cur(181) = '1' and rtmcounter0 = 1 else '0';
rtmcmp183 <= '1' when state_cur(183) = '1' and rtmcounter0 = 1 else '0';
rtmcmp194 <= '1' when state_cur(194) = '1' and rtmcounter0 = 1 else '0';
rtmcmp197 <= '1' when state_cur(197) = '1' and rtmcounter0 = 1 else '0';
rtmcmp203 <= '1' when state_cur(203) = '1' and rtmcounter0 = 1 else '0';
rtmcmp205 <= '1' when state_cur(205) = '1' and rtmcounter0 = 1 else '0';
rtmcmp215 <= '1' when state_cur(215) = '1' and rtmcounter0 = 1 else '0';
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_16_fg_16_16.vhd | 4 | 2099 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_16_fg_16_16.vhd,v 1.2 2001-10-24 23:31:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity real_subcircuit is
port ( a, b : in bit; y1, y2 : out bit );
end entity real_subcircuit;
architecture basic of real_subcircuit is
begin
y1 <= a and b after 10 ns;
y2 <= a nand b after 10 ns;
end architecture basic;
-- code from book
configuration full of circuit is
for with_pad_delays -- configure the architecture
for functionality -- configure the block
for all : subcircuit
use entity work.real_subcircuit(basic);
end for;
end for;
end for;
end configuration full;
-- end code from book
entity fg_16_16 is
end entity fg_16_16;
library stimulus;
use stimulus.stimulus_generators.all;
architecture test of fg_16_16 is
signal in1, in2, in3, out1, out2 : bit;
signal test_vector : bit_vector(1 to 3);
begin
dut : configuration work.full
generic map ( inpad_delay => 2 ns, outpad_delay => 3 ns )
port map ( in1 => in1, in2 => in2, in3 => in3, out1 => out1, out2 => out2 );
stimulus : all_possible_values ( test_vector, 50 ns );
(in1, in2, in3) <= test_vector;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc738.vhd | 4 | 2618 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc738.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity c01s01b01x01p04n03i00738ent_a is
generic (
constant gc1 : integer;
constant gc2 : natural;
constant gc3 : positive
);
port ( signal cent1 : in bit;
signal cent2 : in bit
);
end c01s01b01x01p04n03i00738ent_a;
architecture arch of c01s01b01x01p04n03i00738ent_a is
begin
assert false
report "FAIL: should not compile";
end arch;
ENTITY c01s01b01x01p04n03i00738ent IS
generic ( constant gen_con : natural := 7 );
port ( signal ee1 : in bit;
signal ee2 : in bit;
signal eo1 : out bit
);
END c01s01b01x01p04n03i00738ent;
ARCHITECTURE c01s01b01x01p04n03i00738arch OF c01s01b01x01p04n03i00738ent IS
signal s1 : integer;
signal s2 : natural;
signal s3 : positive;
component comp1
generic (
constant dgc1 : integer;
constant dgc2 : natural;
constant dgc3 : positive
);
port ( signal dcent1 : in bit;
signal dcent2 : in bit
);
end component;
for u1 : comp1 use entity work.c01s01b01x01p04n03i00738ent_a(arch)
generic map (dgc1, dgc2, dgc3)
port map ( dcent1, dcent2 );
BEGIN
u1 : comp1
generic map (s1,s2,s3)
port map (ee1,ee2);
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b01x01p04n03i00738 - Formal generic should have actual or default expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x01p04n03i00738arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/python/units01/demo.vhdl | 1 | 111 | entity e1 is
end e1;
architecture behav of e1 is
begin
assert false report "arch" severity note;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/synth34/tb_repro_sgn.vhdl | 1 | 641 | entity tb_repro_sgn is
end tb_repro_sgn;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_repro_sgn is
signal clk : std_logic;
signal a : signed(7 downto 0);
signal b : signed(7 downto 0);
begin
dut: entity work.repro_sgn
port map (
clk => clk, a => a, b => b);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
a <= x"ab";
pulse;
assert b = x"ab" severity failure;
a <= x"12";
pulse;
assert b = x"12" severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2604.vhd | 4 | 1587 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2604.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02604ent IS
END c13s03b01x00p02n01i02604ent;
ARCHITECTURE c13s03b01x00p02n01i02604arch OF c13s03b01x00p02n01i02604ent IS
BEGIN
TESTING: PROCESS
variable k/ : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02604 - Identifier can not end with '/'."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02604arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/vector.d/cmp_217.vhd | 2 | 376 | library ieee;
use ieee.std_logic_1164.all;
entity cmp_217 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_217;
architecture augh of cmp_217 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2342.vhd | 4 | 1867 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2342.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p02n02i02342ent IS
END c07s02b07x00p02n02i02342ent;
ARCHITECTURE c07s02b07x00p02n02i02342arch OF c07s02b07x00p02n02i02342ent IS
BEGIN
TESTING: PROCESS
-- record types.
type DATE is
record
DAY : INTEGER range 1 to 31;
MONTH : INTEGER range 1 to 12;
YEAR : INTEGER range -10000 to 1988;
end record;
variable RECV : DATE;
variable INTV : INTEGER;
BEGIN
INTV := RECV ** 2;
assert FALSE
report "***FAILED TEST: c07s02b07x00p02n02i02342 - Exponent can only be of type Integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p02n02i02342arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc121.vhd | 4 | 3526 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc121.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x00p29n15i00121ent_a IS
port ( cpt1 : in BIT;
cpt2 : inout BIT;
cpt3 : out BIT;
cpt4 : buffer BIT;
cpt5 : linkage BIT);
END c04s03b02x00p29n15i00121ent_a;
ARCHITECTURE c04s03b02x00p29n15i00121arch_a OF c04s03b02x00p29n15i00121ent_a IS
BEGIN
END c04s03b02x00p29n15i00121arch_a;
ENTITY c04s03b02x00p29n15i00121ent IS
port ( lpt1 : linkage BIT;
lpt2 : linkage BIT;
lpt3 : linkage BIT;
lpt4 : linkage BIT;
lpt5 : linkage BIT;
lpt6 : linkage BIT) ;
END c04s03b02x00p29n15i00121ent;
ARCHITECTURE c04s03b02x00p29n15i00121arch OF c04s03b02x00p29n15i00121ent IS
component com1
port ( cpt1 : in BIT;
cpt2 : inout BIT;
cpt3 : out BIT;
cpt4 : buffer BIT;
cpt5 : linkage BIT);
end component;
for CIS : com1 use entity work.ch040302_p03401_03_01_ent_a(ch040302_p03401_03_01_arch_a);
BEGIN
CIS : com1 port map (cpt1 => lpt2, -- in formal -- Failure_here
-- ERROR: Interface elements of mode linkage may not be read except
-- by association with formal linkage ports of subcomponents.
cpt2 => lpt3, -- inout formal -- Failure_here
-- ERROR: Interface elements of mode linkage may not be read except
-- by association with formal linkage ports of subcomponents.
cpt3 => lpt4, -- out formal -- Failure_here
-- ERROR: Interface elements of mode linkage may not be read except
-- by association with formal linkage ports of subcomponents.
cpt4 => lpt5, -- buffer formal -- Failure_here
-- ERROR: Interface elements of mode linkage may not be read except
-- by association with formal linkage ports of subcomponents.
cpt5 => lpt6);
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b02x00p29n15i00121 - Reading and updating are not permitted on this mode."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x00p29n15i00121arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc544.vhd | 4 | 1827 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc544.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s04b00x00p03n01i00544ent IS
END c03s04b00x00p03n01i00544ent;
ARCHITECTURE c03s04b00x00p03n01i00544arch OF c03s04b00x00p03n01i00544ent IS
type L is -- constrained array decl
array (1 to 1023, 31 downto 0) of Bit;
type M is -- record type decl
record
A: Integer;
B: L;
end record;
type O is -- file decl
file of M; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c03s04b00x00p03n01i00544"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b00x00p03n01i00544arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue99/repro1.vhdl | 2 | 176 | package pkg is
generic ( gen: natural );
constant test: natural:=gen;
end package;
package body pkg is
end pkg;
package mygpkg is new work.pkg generic map ( gen => 17 );
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug19195/top.vhdl | 3 | 89 | entity top is
end top;
use work.test_pkg;
architecture behav of top is
begin
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2059.vhd | 4 | 1720 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2059.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n02i02059ent IS
END c07s02b04x00p01n02i02059ent;
ARCHITECTURE c07s02b04x00p01n02i02059arch OF c07s02b04x00p01n02i02059ent IS
signal S1 : BOOLEAN := TRUE;
signal S2 : BOOLEAN := FALSE;
BEGIN
TESTING: PROCESS
BEGIN
case (S1&S2) is -- Failure_here
when others => null;
end case;
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n02i02059 - Concatenation operator cannot be used with this type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n02i02059arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2091.vhd | 4 | 2201 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2091.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02091ent IS
END c07s02b04x00p20n01i02091ent;
ARCHITECTURE c07s02b04x00p20n01i02091arch OF c07s02b04x00p20n01i02091ent IS
TYPE bit_v is array (integer range <>) of bit;
SUBTYPE bit_8 is bit_v (1 to 8);
SUBTYPE bit_4 is bit_v (1 to 4);
BEGIN
TESTING: PROCESS
variable result : bit_4;
variable l_operand : bit_4 := ('1','0','1','0');
variable r_operand : bit_4 := ('0','0','1','1');
alias l_alias : bit_v (1 to 2) is l_operand (2 to 3);
alias r_alias : bit_v (1 to 2) is r_operand (3 to 4);
BEGIN
result := l_alias & r_alias;
wait for 5 ns;
assert NOT((result = ('0','1','1','1')) and (result(1) = '0'))
report "***PASSED TEST: c07s02b04x00p20n01i02091"
severity NOTE;
assert ((result = ('0','1','1','1')) and (result(1) = '0'))
report "***FAILED TEST: c07s02b04x00p20n01i02091 - Concatenation of two BOOLEAITses failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02091arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2181.vhd | 4 | 1793 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2181.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b05x00p01n02i02181ent IS
END c07s02b05x00p01n02i02181ent;
ARCHITECTURE c07s02b05x00p01n02i02181arch OF c07s02b05x00p01n02i02181ent IS
BEGIN
TESTING: PROCESS
variable k : real := 0.0;
variable m : real := 5.5;
BEGIN
k := abs (-m);
assert NOT( k = 5.5 )
report "***PASSED TEST: c07s02b05x00p01n02i02181"
severity NOTE;
assert ( k = 5.5 )
report "***FAILED TEST: c07s02b05x00p01n02i02181 - For each of these unary operators, the operand and the result have the same type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b05x00p01n02i02181arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue301/src/recursion.vhd | 2 | 2910 | --!
--! Copyright (C) 2011 - 2014 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Recursion unit for recursive code.
--! @author Markus Fehrenz
--! @date 2011/01/12
--!
--! @details The recusion handling buffers the reorder ouput and
--! calculates the correct output depending on the feedback polynomial.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library dec_viterbi;
use dec_viterbi.pkg_param.all;
use dec_viterbi.pkg_param_derived.all;
entity recursionx is
port(
clk : in std_logic;
rst : in std_logic;
--
-- Decoded bits input from the reordering units in std_logic
--
s_axis_input_tvalid : in std_logic;
s_axis_input_tdata : in std_logic;
s_axis_input_tlast : in std_logic;
s_axis_input_tready : out std_logic;
--
-- Output decoded bits convolved with the feedback polynomial
--
m_axis_output_tvalid : out std_logic;
m_axis_output_tdata : out std_logic;
m_axis_output_tlast : out std_logic;
m_axis_output_tready : in std_logic
);
end entity recursionx;
architecture rtl of recursionx is
signal recursion_sreg : unsigned(ENCODER_MEMORY_DEPTH downto 0);
signal s_axis_input_tready_int : std_logic;
signal m_axis_output_tvalid_int : std_logic;
begin
s_axis_input_tready_int <= '1' when m_axis_output_tready = '1' or m_axis_output_tvalid_int = '0' else
'0';
s_axis_input_tready <= s_axis_input_tready_int;
m_axis_output_tvalid <= m_axis_output_tvalid_int;
-- Use the feedback polynomial to convolve the global path.
pr_recursion : process(clk) is
variable v_bit : std_logic := '0';
variable v_recursion_state : unsigned(ENCODER_MEMORY_DEPTH downto 0);
begin
if rising_edge(clk) then
if rst = '1' then
recursion_sreg <= (others => '0');
m_axis_output_tdata <= '0';
m_axis_output_tlast <= '0';
else
m_axis_output_tvalid_int <= s_axis_input_tvalid;
if s_axis_input_tvalid = '1' and s_axis_input_tready_int = '1' then
-- move current decoded output bits into shift register and reset if last flag is valid
if s_axis_input_tlast = '1' then
recursion_sreg <= (others => '0');
else
recursion_sreg <= s_axis_input_tdata & recursion_sreg(ENCODER_MEMORY_DEPTH downto 1);
end if;
-- convolve with feedback polynomial with the output register.
v_bit := '0';
v_recursion_state := (s_axis_input_tdata & recursion_sreg(ENCODER_MEMORY_DEPTH downto 1)) and
('1' & to_unsigned(FEEDBACK_POLYNOMIAL, ENCODER_MEMORY_DEPTH));
for i in ENCODER_MEMORY_DEPTH downto 0 loop
v_bit := v_bit xor v_recursion_state(i);
end loop;
m_axis_output_tdata <= v_bit;
m_axis_output_tlast <= s_axis_input_tlast;
end if;
end if;
end if;
end process pr_recursion;
end architecture rtl;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/idct.d/add_466.vhd | 2 | 800 | library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_466 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_466;
architecture augh of add_466 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc2792.vhd | 4 | 1608 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2792.vhd,v 1.2 2001-10-26 16:30:22 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity DOWNTO is
end DOWNTO;
ENTITY c13s09b00x00p99n01i02792ent IS
END c13s09b00x00p99n01i02792ent;
ARCHITECTURE c13s09b00x00p99n01i02792arch OF c13s09b00x00p99n01i02792ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s09b00x00p99n01i02792 - Reserved word DOWNTO can not be used as an entity name."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s09b00x00p99n01i02792arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1247.vhd | 4 | 1671 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1247.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p04n01i01247ent IS
END c08s02b00x00p04n01i01247ent;
ARCHITECTURE c08s02b00x00p04n01i01247arch OF c08s02b00x00p04n01i01247ent IS
BEGIN
TESTING: PROCESS
variable N2 : SEVERITY_LEVEL;
BEGIN
assert FALSE
report N2
severity NOTE;
assert FALSE
report "***FAILED TEST: c08s02b00x00p04n01i01247 - Expression type used in a report clause should be STRING"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s02b00x00p04n01i01247arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/fundamental/d_ff.vhd | 4 | 1065 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity d_ff is
port ( d, clk : in bit; q : out bit );
end d_ff;
architecture basic of d_ff is
begin
ff_behavior : process is
begin
if clk = '1' then
q <= d after 2 ns;
end if;
wait on clk;
end process ff_behavior;
end architecture basic;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug090/crash5.vhdl | 1 | 1216 | library ieee;
use ieee.s_1164.all;
entity dff is
generic (len : natural := 8);
port (clk : in std_logic;
rst_n : in std_logic;
d : std_logic_vector (len - 1 downto 0);
q : out std_logic_vector (len - 1 downto 0));
end dff;
architecture behav of dff is
begin
p: process (clk)
begin
if rising_edge (clk) then
if rst_n then
q <= (others => '0');
else
q <= d;
end if;
end if;
end process p;
end behav;
entity hello is
end hello;
architecture behav of hello is
signal clk : s;
signal rst_n : std_logic;
signal din, dout : std_logic_vector (7 downto 0);
begin
mydff : entity wor{.dff
generic map (l => 8)
port map (clk => clk, rst_n => rst_n, d => din, q => dout);
rst_n <= '0' after 0 ns, '1' after 4 ns;
process
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end process;
process
variable v : natural := 0;
begin
wait until rst_n = '1';
wait until clk = '0';
report "start of tb" severity note;
for i in din'range loop
din(i) <= '0';
end loop;
wait until clk = '0';
end process;
assert false report "Hello world" severity note;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug077/repro.vhdl | 1 | 539 | package pkg is
type my_inputs is record
a : bit;
w : bit_vector;
end record;
end pkg;
use work.pkg.all;
entity child is
port (i : my_inputs);
end;
architecture behav of child is
begin
assert i.w = (i.w'range => i.a);
end behav;
entity repro is
end repro;
use work.pkg.all;
architecture behav of repro is
signal s : bit_vector (7 downto 0);
signal a : bit;
begin
inst : entity work.child
port map(
i.a => a,
i.w => s);
process
begin
a <= '0';
s <= x"01";
wait;
end process;
end;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue467/testbench.vhdl | 1 | 336 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.AbstractMmPkg.all;
entity testbench is
end entity testbench;
architecture TB of testbench is
signal rec : AbstractMmRecType(
writedata(31 downto 0),
readdata(31 downto 0),
address(4 downto 0),
byteen(3 downto 0)
);
begin
end architecture TB;
| gpl-2.0 |
tgingold/ghdl | testsuite/synth/func01/tb_func01.vhdl | 1 | 466 | entity tb_func01 is
end tb_func01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_func01 is
signal a, b : std_logic_vector(7 downto 0);
signal sel : std_logic;
begin
dut: entity work.func01
port map (a, sel, b);
process
begin
a <= x"5d";
sel <= '1';
wait for 1 ns;
assert b = x"0d" severity failure;
sel <= '0';
wait for 1 ns;
assert b = x"5d" severity failure;
wait;
end process;
end behav;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc2551.vhd | 4 | 1985 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2551.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b06x00p02n01i02551ent IS
END c07s03b06x00p02n01i02551ent;
ARCHITECTURE c07s03b06x00p02n01i02551arch OF c07s03b06x00p02n01i02551ent IS
BEGIN
TESTING: PROCESS
type T is
record
a:integer;
b:integer;
end record;
type A is access T;
variable B1, B2: A := new T'(0, 0);
variable C : T;
BEGIN
C := B1.all;
assert NOT(C.a = 0 and C.b = 0 )
report "***PASSED TEST: c07s03b06x00p02n01i02551"
severity NOTE;
assert (C.a = 0 and C.b = 0 )
report "***FAILED TEST: c07s03b06x00p02n01i02551 - The allocator must either consist of the reserved word new and a subtype indication or consist of the reserved word new and a qualified expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b06x00p02n01i02551arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue1191/mux_fifo.vhd | 1 | 2376 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mux_fifo_pkg.all;
entity mux_fifo is
generic (g_enabled_channels : std_logic_vector;
g_extend : natural range 0 to 1);
port (rst : in std_logic;
clk : in std_logic;
-- fifo if
fifo_if_in : inout t_mux_fifo_if;
-- out if
dataout : out std_logic_vector;
wr_en : out std_logic;
full : in std_logic);
end entity mux_fifo;
architecture simple of mux_fifo is
type t_state is (s_wait, s_capture, s_write);
signal index : integer := -1;
signal state : t_state;
function DetectFirstNonEmpty (EmptyIn : std_logic_vector) return integer is
begin
for I in EmptyIn'range loop
if EmptyIn(I) = '0' then
return i;
end if;
end loop;
return -1;
end function;
begin
fifo_if_in.clk <= clk;
u_mux : process (clk)
begin
if rising_edge(clk) then
if (rst = '1') then
index <= -1;
dataout <= (others => '0');
wr_en <= '0';
fifo_if_in.rd <= (others => '0');
state <= s_wait;
else
case state is
when s_wait =>
-- index <= DetectFirstNonEmpty(empty and enabled_channels);
index <= DetectFirstNonEmpty(fifo_if_in.empty);
dataout <= (others => '0');
wr_en <= '0';
fifo_if_in.rd <= (others => '0');
if index >= 0 then
fifo_if_in.rd(index) <= '1';
state <= s_capture;
end if;
when s_capture =>
dataout <= (others => '0');
wr_en <= '0';
fifo_if_in.rd <= (others => '0');
if not(full) then
state <= s_write;
end if;
when s_write =>
index <= -1;
if g_extend = 1 then
dataout <= fifo_if_in.data(index) & std_logic_vector(to_signed(index, 8));
else
dataout <= fifo_if_in.data(index);
end if;
wr_en <= '1';
fifo_if_in.rd <= (others => '0');
state <= s_wait;
end case;
end if;
end if;
end process u_mux;
end architecture simple;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc867.vhd | 4 | 9742 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc867.vhd,v 1.2 2001-10-26 16:30:01 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c01s03b01x00p12n01i00867pkg is
constant low_number : integer := 0;
constant hi_number : integer := 3;
subtype hi_to_low_range is integer range low_number to hi_number;
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
type record_std_package is record
a: boolean;
b: bit;
c:character;
d:severity_level;
e:integer;
f:real;
g:time;
h:natural;
i:positive;
end record;
type array_rec_std is array (natural range <>) of record_std_package;
type four_value is ('Z','0','1','X');
--enumerated type
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
subtype dumy is integer range 0 to 3;
signal Sin1 : bit_vector(0 to 5) ;
signal Sin2 : boolean_vector(0 to 5) ;
signal Sin4 : severity_level_vector(0 to 5) ;
signal Sin5 : integer_vector(0 to 5) ;
signal Sin6 : real_vector(0 to 5) ;
signal Sin7 : time_vector(0 to 5) ;
signal Sin8 : natural_vector(0 to 5) ;
signal Sin9 : positive_vector(0 to 5) ;
signal Sin10: array_rec_std(0 to 5) ;
end c01s03b01x00p12n01i00867pkg;
use work.c01s03b01x00p12n01i00867pkg.all;
entity test is
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end;
architecture test of test is
begin
sigout1 <= sigin1;
sigout2 <= sigin2;
sigout4 <= sigin4;
sigout5 <= sigin5;
sigout6 <= sigin6;
sigout7 <= sigin7;
sigout8 <= sigin8;
sigout9 <= sigin9;
sigout10 <= sigin10;
end;
configuration testbench of test is
for test
end for;
end;
use work.c01s03b01x00p12n01i00867pkg.all;
ENTITY c01s03b01x00p12n01i00867ent IS
generic(
zero : integer := 0;
one : integer := 1;
two : integer := 2;
three: integer := 3;
four : integer := 4;
five : integer := 5;
six : integer := 6;
seven: integer := 7;
eight: integer := 8;
nine : integer := 9;
fifteen:integer:= 15;
dumb : bit_vector(0 to 3) := "1010");
END c01s03b01x00p12n01i00867ent;
ARCHITECTURE c01s03b01x00p12n01i00867arch OF c01s03b01x00p12n01i00867ent IS
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
begin
Sin1(zero) <='1';
Sin2(zero) <= true;
Sin4(zero) <= note;
Sin5(zero) <= 3;
Sin6(zero) <= 3.0;
Sin7(zero) <= 3 ns;
Sin8(zero) <= 1;
Sin9(zero) <= 1;
Sin10(zero) <= (C1,C2,C3,C4,C5,C6,C7,C8,C9);
K:block
component test
port(
sigin1 : in boolean ;
sigout1 : out boolean ;
sigin2 : in bit ;
sigout2 : out bit ;
sigin4 : in severity_level ;
sigout4 : out severity_level ;
sigin5 : in integer ;
sigout5 : out integer ;
sigin6 : in real ;
sigout6 : out real ;
sigin7 : in time ;
sigout7 : out time ;
sigin8 : in natural ;
sigout8 : out natural ;
sigin9 : in positive ;
sigout9 : out positive ;
sigin10 : in record_std_package ;
sigout10 : out record_std_package
);
end component;
BEGIN
T5 : test
port map
(
Sin2(4),Sin2(5),
Sin1(4),Sin1(5),
Sin4(4),Sin4(5),
Sin5(4),Sin5(5),
Sin6(4),Sin6(5),
Sin7(4),Sin7(5),
Sin8(4),Sin8(5),
Sin9(4),Sin9(5),
Sin10(4),Sin10(5)
);
G: for i in zero to three generate
T1:test
port map
(
Sin2(i),Sin2(i+1),
Sin1(i),Sin1(i+1),
Sin4(i),Sin4(i+1),
Sin5(i),Sin5(i+1),
Sin6(i),Sin6(i+1),
Sin7(i),Sin7(i+1),
Sin8(i),Sin8(i+1),
Sin9(i),Sin9(i+1),
Sin10(i),Sin10(i+1)
);
end generate;
end block;
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert Sin1(0) = Sin1(5) report "assignment of Sin1(0) to Sin1(4) is invalid through entity port" severity failure;
assert Sin2(0) = Sin2(5) report "assignment of Sin2(0) to Sin2(4) is invalid through entity port" severity failure;
assert Sin4(0) = Sin4(5) report "assignment of Sin4(0) to Sin4(4) is invalid through entity port" severity failure;
assert Sin5(0) = Sin5(5) report "assignment of Sin5(0) to Sin5(4) is invalid through entity port" severity failure;
assert Sin6(0) = Sin6(5) report "assignment of Sin6(0) to Sin6(4) is invalid through entity port" severity failure;
assert Sin7(0) = Sin7(5) report "assignment of Sin7(0) to Sin7(4) is invalid through entity port" severity failure;
assert Sin8(0) = Sin8(5) report "assignment of Sin8(0) to Sin8(4) is invalid through entity port" severity failure;
assert Sin9(0) = Sin9(5) report "assignment of Sin9(0) to Sin9(4) is invalid through entity port" severity failure;
assert Sin10(0) = Sin10(5) report "assignment of Sin10(0) to Sin10(4) is invalid through entity port" severity failure;
assert NOT( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***PASSED TEST: c01s03b01x00p12n01i00867"
severity NOTE;
assert ( Sin1(0) = sin1(5) and
Sin2(0) = Sin2(5) and
Sin4(0) = Sin4(5) and
Sin5(0) = Sin5(5) and
Sin6(0) = Sin6(5) and
Sin7(0) = Sin7(5) and
Sin8(0) = Sin8(5) and
Sin9(0) = Sin9(5) and
Sin10(0)= Sin10(0) )
report "***FAILED TEST: c01s03b01x00p12n01i00867 - If such a block configuration contains an index specification that is a discrete range, then the block configuration applies to those implicit block statements that are generated for the specified range of values of the corresponding generate index."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s03b01x00p12n01i00867arch;
configuration c01s03b01x00p12n01i00867cfg of c01s03b01x00p12n01i00867ent is
for c01s03b01x00p12n01i00867arch
for K
for T5:test use configuration work.testbench;
end for;
for G(one)
for T1:test
use configuration work.testbench;
end for;
end for;
for G(dumy'low)
for T1:test
use configuration work.testbench;
end for;
end for;
for G(2 to dumy'high)
for T1:test
use configuration work.testbench;
end for;
end for;
end for;
end for;
end;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue50/vector.d/cmp_146.vhd | 2 | 376 | library ieee;
use ieee.std_logic_1164.all;
entity cmp_146 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_146;
architecture augh of cmp_146 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-ams/ashenden/compliant/guards-and-blocks/reg_read_selector.vhd | 4 | 1832 |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity reg_read_selector is
end entity reg_read_selector;
architecture test of reg_read_selector is
constant reg0 : std_logic_vector(7 downto 0) := "00000000";
constant reg1 : std_logic_vector(7 downto 0) := "11111111";
signal dbus : std_logic_vector(7 downto 0);
signal reg_sel, read, reg_addr : X01 := '0';
begin
-- code from book
reg_read_selector : block (reg_sel = '1' and read = '1') is
begin
dbus <= reg0 when guard and reg_addr = '0' else
reg1 when guard and reg_addr = '1' else
"ZZZZZZZZ";
end block reg_read_selector;
-- end code from book
stimulus : process is
begin
reg_sel <= '1'; wait for 10 ns;
read <= '1', '0' after 5 ns; wait for 10 ns;
reg_sel <= '0'; wait for 10 ns;
read <= '1', '0' after 5 ns; wait for 10 ns;
reg_addr <= '1'; wait for 10 ns;
reg_sel <= '1'; wait for 10 ns;
read <= '1', '0' after 5 ns; wait for 10 ns;
wait;
end process stimulus;
end architecture test;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/bug18361/cnt.vhdl | 3 | 1771 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity CNT_V is
Generic(clk_divisor: natural);
Port(clk : in std_logic;
reset : in std_logic;
q_o : out std_logic);
end CNT_V;
architecture behv of CNT_V is
--components
--constants
--signals
signal q: std_logic;
begin
q_o <= q;
count: process(clk, reset) is
--variable
variable idx: natural range 0 to clk_divisor-1;
begin
if reset = '1' then
idx:= 0;
q <= '0';
elsif rising_edge(clk) then
if idx = clk_divisor - 1 then
q <= '1';
idx := 0;
else
q <= '0';
idx := idx + 1;
end if;
end if;
end process;
end behv;
-- Testbench:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cnt_v_tb is
end cnt_v_tb;
architecture TB of cnt_v_tb is
component CNT_V is
Generic(clk_divisor: natural);
Port(clk : in std_logic;
reset : in std_logic;
q_o : out std_logic);
end component;
--components
--constants
--signals
signal clk : std_logic;
signal reset : std_logic;
signal q_o : std_logic;
begin
DUV: cnt_v
--generic map(clk_divisor => 10) -- here ist the error
port map( clk, reset, q_o);
--stimuli here
--Stimuli for Signal "clk" 40 mhz
process
begin
clk <= '1';
wait for 12.5 ns;
clk <= '0';
wait for 12.5 ns;
end process;
process
begin
--initialisation
reset <= '1';
wait for 20 ns;
--stimuli
reset <= '0';
wait for 22 ns;
-- do some stuff
wait;
end process;
end TB;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc1454.vhd | 4 | 1705 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1454.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p01n01i01454ent IS
END c08s07b00x00p01n01i01454ent;
ARCHITECTURE c08s07b00x00p01n01i01454arch OF c08s07b00x00p01n01i01454ent IS
begin
TESTING: process
variable b1, b2 : bit := '0';
begin
if '1' then -- failure_here condition not boolean.
b1 := '1';
end if;
assert FALSE
report "***FAILED TEST: c08s07b00x00p01n01i01454 - Expression of IF statement is not of type BOOLEAN"
severity ERROR;
wait;
end process TESTING;
END c08s07b00x00p01n01i01454arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue241/test.vhdl | 2 | 1588 | LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE test_ctrl_parameter_pkg IS
TYPE device_t IS (
DEVICE_NONAME,
DEVICE_TEST
);
-----------------------------------------------------------------------------
-- DDR SDRAM device definitions
-----------------------------------------------------------------------------
TYPE mem_device_t IS (
TEST_1,
TEST_2,
TEST_3
);
TYPE mem_device_array_t IS ARRAY (natural RANGE <>) OF mem_device_t;
CONSTANT C_TEST_BUS_ARRAY_SIZE : natural := 10;
SUBTYPE test_device_type_t IS
mem_device_array_t(0 TO C_TEST_BUS_ARRAY_SIZE - 1);
CONSTANT DEFAULT_TEST_DEVICE_TYPE_ARRAY : test_device_type_t :=
(OTHERS => TEST_1);
TYPE device_test_parameters_t IS RECORD
test_devices : test_device_type_t;
END RECORD;
CONSTANT DEFAULT_DEVICE_TEST_PARAMETERS :
device_test_parameters_t := (
test_devices => DEFAULT_TEST_DEVICE_TYPE_ARRAY);
TYPE device_test_parameters_array_t IS ARRAY (natural RANGE <>) OF
device_test_parameters_t;
SUBTYPE constrained_device_test_parameters_array_t IS
device_test_parameters_array_t(0 TO device_t'pos(device_t'high));
CONSTANT DEVICE_TEST_PARAMETERS :
constrained_device_test_parameters_array_t := (
device_t'pos(DEVICE_TEST) =>
(
test_devices => (1 | 2 => TEST_1, 3 => TEST_2, OTHERS => TEST_3)
),
OTHERS => DEFAULT_DEVICE_TEST_PARAMETERS
);
END test_ctrl_parameter_pkg;
ENTITY test IS
END ENTITY test;
ARCHITECTURE rtl OF test IS
BEGIN
END ARCHITECTURE rtl;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc1597.vhd | 4 | 1945 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1597.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p03n01i01597ent IS
END c08s11b00x00p03n01i01597ent;
ARCHITECTURE c08s11b00x00p03n01i01597arch OF c08s11b00x00p03n01i01597ent IS
BEGIN
TESTING: PROCESS
variable p : integer := 0;
BEGIN
L1 :
for i in boolean loop
p := 5 + p;
L2 :
for j in 1 to 3 loop
exit ;
p := 0;
end loop L2 ;
end loop L1;
assert NOT( p=10 )
report "***PASSED TEST: c08s11b00x00p03n01i01597"
severity NOTE;
assert ( p=10 )
report "***FAILED TEST: c08s11b00x00p03n01i01597 - An exit statement used without a loop label only occurs within a loop and refers only to the lowest level, or innermost, loop."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p03n01i01597arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/gna/issue1138/wbcrc_syn.vhdl | 1 | 1852 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.MATH_REAL.all;
--library ghdl_test;
-- use ghdl_test.crc_pkg.all;
use work.crc_pkg.all;
entity wbCrc_syn is
generic( yes_G : std_logic :='1'
; fClkSys_Hz_G : integer := 100e6
; isSimul_G : boolean := false
; wbDataWidth_G : integer := 8
; wbAddrWidth_G : integer := 32
; wbTgaWidth_G : integer := 1
; wbTgcWidth_G : integer := 1
; wbTgdWidth_G : integer := 1
; crcDefault_G : String := "CRC-32/CCITT-FALSE"
);
port( clk_i : in std_ulogic;
rx_is_dat_i : in std_ulogic_vector( wbDataWidth_G - 1 downto 0 );
rx_is_adr_i : in std_ulogic_vector( wbAddrWidth_G - 1 downto 0 );
rx_is_sel_i : in std_ulogic_vector( wbDataWidth_G / 8 - 1 downto 0 );
rx_is_loc_i : in std_ulogic;
rx_is_cyc_i : in std_ulogic;
rx_is_stb_i : in std_ulogic;
rx_is_we_i : in std_ulogic;
rx_os_ack_o : out std_ulogic;
rx_os_stl_o : out std_ulogic;
rx_os_err_o : out std_ulogic;
tx_os_cyc_o : out std_ulogic;
tx_os_stb_o : out std_ulogic;
tx_os_we_o : out std_ulogic;
tx_os_dat_o : out std_ulogic_vector( getCrc32Param( crcDefault_G , 8 ).poly'length - 1 downto 0 );
tx_os_cti_o : out std_ulogic_vector(2 downto 0) ;
tx_os_sel_o : out std_ulogic_vector( wbDataWidth_G / 8 - 1 downto 0 );
tx_os_loc_o : out std_ulogic;
tx_is_ack_i : in std_ulogic
);
end wbCrc_syn;
architecture rtl of wbCrc_syn is
begin
end rtl;
| gpl-2.0 |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.