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vira-lytvyn/labsAndOthersNiceThings | HardwareAndSoftwareOfNeuralNetworks/Lab_12/Lab_12_2/DC7.vhd | 1 | 902 | Library IEEE;
use IEEE.std_logic_1164.all;
entity DC7 is
port( A: in std_logic_vector (3 downto 0);
Q: out std_logic_vector (6 downto 0));
end entity DC7;
architecture Behave of DC7 is
begin
process (A)
begin
case A is
when "0000" => Q <= "0000001";
when "0001" => Q <= "1001111";
when "0010" => Q <= "0010011";
when "0011" => Q <= "0000110";
when "0100" => Q <= "1001100";
when "0101" => Q <= "0100100";
when "0110" => Q <= "0100000";
when "0111" => Q <= "0001111";
when "1000" => Q <= "0000000";
when "1001" => Q <= "0000100";
when "1010" => Q <= "0001000";
when "1011" => Q <= "1100000";
when "1100" => Q <= "1110010";
when "1101" => Q <= "1000010";
when "1110" => Q <= "0110000";
when "1111" => Q <= "0111000";
when others => Q <= "0000001";
end case;
end process;
end Behave; | gpl-2.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_prime_fifo_plain/simulation/k7_prime_fifo_plain_dgen.vhd | 1 | 4581 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_prime_fifo_plain_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.k7_prime_fifo_plain_pkg.ALL;
ENTITY k7_prime_fifo_plain_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF k7_prime_fifo_plain_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 100 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:k7_prime_fifo_plain_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
| gpl-2.0 |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/wr_fifo32to256/simulation/wr_fifo32to256_rng.vhd | 1 | 3905 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: wr_fifo32to256_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY wr_fifo32to256_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF wr_fifo32to256_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
| gpl-2.0 |
freecores/w11 | rtl/sys_gen/w11a/nexys2/sys_conf.vhd | 1 | 3842 | -- $Id: sys_conf.vhd 509 2013-04-21 20:46:20Z mueller $
--
-- Copyright 2010-2013 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_n2 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 11.4, 13.1; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-21 509 1.2 add fx2 settings
-- 2011-11-19 428 1.1.1 use clksys=56 (58 no closure after numeric_std...)
-- 2010-11-27 341 1.1 add dcm and memctl related constants (clksys=58)
-- 2010-05-05 295 1.0 Initial version (derived from _s3 version)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
-- valid system clock / delay combinations:
-- div mul clksys read0 read1 write
-- 1 1 50.0 2 2 3
-- 25 27 54.0 3 3 3
-- 25 29 58.0 3 3 4
package sys_conf is
constant sys_conf_clkfx_divide : positive := 25;
constant sys_conf_clkfx_multiply : positive := 28; -- ==> 56 MHz
constant sys_conf_memctl_read0delay : positive := 3;
constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay;
constant sys_conf_memctl_writedelay : positive := 4;
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
-- fx2 settings: petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_fx2_ccwidth : positive := 5;
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_bram : integer := 0; -- no bram, use cache
constant sys_conf_bram_awidth : integer := 14; -- bram size (16 kB)
constant sys_conf_mem_losize : integer := 8#167777#; -- 4 MByte
--constant sys_conf_mem_losize : integer := 8#003777#; -- 128 kByte (debug)
-- constant sys_conf_bram : integer := 1; -- bram only
-- constant sys_conf_bram_awidth : integer := 15; -- bram size (32 kB)
-- constant sys_conf_mem_losize : integer := 8#000777#; -- 32 kByte
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
-- derived constants
constant sys_conf_clksys : integer :=
(50000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clksys/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;
-- Note: mem_losize holds 16 MSB of the PA of the addressable memory
-- 2 211 111 111 110 000 000 000
-- 1 098 765 432 109 876 543 210
--
-- 0 000 000 011 111 111 000 000 -> 00037777 --> 14bit --> 16 kByte
-- 0 000 000 111 111 111 000 000 -> 00077777 --> 15bit --> 32 kByte
-- 0 000 001 111 111 111 000 000 -> 00177777 --> 16bit --> 64 kByte
-- 0 000 011 111 111 111 000 000 -> 00377777 --> 17bit --> 128 kByte
-- 0 011 111 111 111 111 000 000 -> 03777777 --> 20bit --> 1 MByte
-- 1 110 111 111 111 111 000 000 -> 16777777 --> 22bit --> 4 MByte
-- upper 256 kB excluded for 11/70 UB
| gpl-2.0 |
freecores/w11 | rtl/vlib/serport/serport_uart_autobaud.vhd | 2 | 6460 | -- $Id: serport_uart_autobaud.vhd 417 2011-10-22 10:30:29Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: serport_uart_autobaud - syn
-- Description: serial port UART - autobauder
--
-- Dependencies: -
-- Test bench: tb/tb_serport_autobaud
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-22 417 1.0.4 now numeric_std clean
-- 2010-04-18 279 1.0.3 change ccnt start value to -3, better rounding
-- 2007-10-14 89 1.0.2 all instantiation with CDINIT=0
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-06-30 62 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity serport_uart_autobaud is -- serial port uart: autobauder
generic (
CDWIDTH : positive := 13; -- clk divider width
CDINIT: natural := 15); -- clk divider initial/reset setting
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- 1 msec clock enable
RESET : in slbit; -- reset
RXSD : in slbit; -- receive serial data (uart view)
CLKDIV : out slv(CDWIDTH-1 downto 0); -- clock divider setting
ACT : out slbit; -- active; if 1 clkdiv is invalid
DONE : out slbit -- resync done
);
end serport_uart_autobaud;
architecture syn of serport_uart_autobaud is
type state_type is (
s_idle,
s_break,
s_wait,
s_sync
);
type regs_type is record
ccnt : slv(CDWIDTH-1+3 downto 0); -- clock divider counter
mcnt : slv7; -- msec counter
seen1 : slbit; -- seen a '1' in this msec
state : state_type; -- state
end record regs_type;
-- Note on initialization of ccnt:
-- - in the current logic ccnt is incremented n-1 times when n is number
-- clock cycles with a RXD of '0'. When running at 50 MBaud, ccnt will
-- be incremented 7 (not 8!) times.
-- - the three LSBs of ccnt should be at 100 under perfect conditions, this
-- gives the best rounded estimate of CLKDIV.
-- - therefore ccnt is inititialized with 111111.101: 101 + 111 -> 1100
-- --> ccntinit = -3
constant ccntinit : slv(CDWIDTH-1+3 downto 0) :=
slv(to_unsigned(2**(CDWIDTH+3)-3, CDWIDTH+3));
constant mcntzero : slv7 := (others=>'0');
constant mcntlast : slv7 := (others=>'1');
constant regs_init : regs_type := (
slv(to_unsigned(CDINIT,CDWIDTH))&"000",
(others=>'0'),
'0',
s_idle
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
assert CDINIT <= 2**CDWIDTH-1
report "assert(CDINIT <= 2**CDWIDTH-1): CDINIT too large for given CDWIDTH"
severity FAILURE;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_MSEC, RESET, RXSD)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable iact : slbit := '0';
variable idone : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
iact := '1';
idone := '0';
case r.state is
when s_idle => -- s_idle: idle, detect break --------
iact := '0';
if CE_MSEC = '1' then -- if end of msec
if r.seen1 = '0' then -- if no '1' seen on RXD
n.mcnt := slv(unsigned(r.mcnt) + 1); -- up break timer counter
if r.mcnt = mcntlast then -- after 127 msec
n.state := s_break; -- break detected !
end if;
else -- otherwise if '1' seen
n.mcnt := mcntzero; -- clear break timer again
end if;
n.seen1 := RXSD; -- latch current RXD value
else -- otherwise if not at end-of-msec
n.seen1 := r.seen1 or RXSD; -- remember whether RXS=1 seen
end if;
when s_break => -- s_break: detect end of break ------
if RXSD = '1' then -- if end of break seen
n.state := s_wait; -- to s_wait to wait for sync char
n.ccnt := ccntinit; -- and initialize ccnt
end if; -- otherwise stay in s_break
when s_wait => -- s_wait: wait for sync char --------
if RXSD = '0' then -- if start bit if sync char seen
n.state := s_sync; -- to s_sync to wait for end of '0'
end if; -- otherwise stay in s_wait
when s_sync => -- s_sync: wait for end of '0' bits --
if RXSD = '1' then -- if end of '0' bits seen
n.state := s_idle; -- to s_idle, autobauding done
idone := '1'; -- emit done pulse
else -- otherwise still in '0' of sync
n.ccnt := slv(unsigned(n.ccnt) + 1); -- increment ccnt
end if;
when others => null; -- -----------------------------------
end case;
N_REGS <= n;
CLKDIV <= r.ccnt(CDWIDTH-1+3 downto 3);
ACT <= iact or RESET;
DONE <= idone;
end process proc_next;
end syn;
| gpl-2.0 |
freecores/w11 | rtl/vlib/rlink/rlink_core.vhd | 2 | 40169 | -- $Id: rlink_core.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: rlink_core - syn
-- Description: rlink core with 9bit interface
--
-- Dependencies: comlib/crc8
--
-- Test bench: tb/tb_rlink_direct
-- tb/tb_rlink_serport
-- tb/tb_rlink_tba_ttcombo
--
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-12-04 343 12.1 M53d xc3s1000-4 155 322 0 199 s 8.9
-- 2010-06-06 302 11.4 L68 xc3s1000-4 151 323 0 197 s 8.9
-- 2010-04-03 274 11.4 L68 xc3s1000-4 148 313 0 190 s 8.0
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 147 321 0 197 s 8.3
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-19 427 3.1.3 now numeric_std clean
-- 2010-12-25 348 3.1.2 drop RL_FLUSH support, add RL_MONI for rlink_core;
-- 2010-12-24 347 3.1.1 rename: CP_*->RL->*
-- 2010-12-22 346 3.1 wblk dcrc error: send nak, transit to s_error now;
-- rename stat flags: [cd]crc->[cd]err, ioto->rbnak,
-- ioerr->rberr; '111' cmd now aborts via s_txnak and
-- sets cerr flag; set [cd]err on eop/nak aborts;
-- 2010-12-04 343 3.0 renamed rri_ -> rlink_; rbus V3 interface: use now
-- aval,re,we; add new states: s_rstart, s_wstart
-- 2010-06-20 308 2.6 use rbinit,rbreq,rbwe state flops to drive rb_mreq;
-- now nak on reserved cmd 111; use do_comma_abort();
-- 2010-06-18 306 2.5.1 rename rbus data fields to _rbf_
-- 2010-06-06 302 2.5 use sop/eop framing instead of soc+chaining
-- 2010-06-03 299 2.1.2 drop unneeded unsigned casts; change init encoding
-- 2010-05-02 287 2.1.1 ren CE_XSEC->CE_INT,RP_STAT->RB_STAT,AP_LAM->RB_LAM
-- drop RP_IINT signal from interfaces
-- 2010-04-03 274 2.1 add CP_FLUSH output
-- 2009-07-12 233 2.0.1 remove snoopers
-- 2008-08-24 162 2.0 with new rb_mreq/rb_sres interface
-- 2008-03-02 121 1.1.1 comment out snoopers
-- 2007-11-24 98 1.1 new internal init handling (addr=11111111)
-- 2007-10-12 88 1.0.1 avoid ieee.std_logic_unsigned, use cast to unsigned
-- 2007-09-15 82 1.0 Initial version, fully functional
-- 2007-06-17 58 0.5 First preliminary version
------------------------------------------------------------------------------
--
-- Overall protocol:
-- _idle : expect
-- sop -> _txsop (echo sop, , to _txsop, _rxcmd)
-- eop -> _txeop (send nak,eop , to _txnak, _txeop, _idle)
-- nak -> _txnak (silently ignore nak)
-- attn -> _txito (send ito , to _idle)
-- data -> _idle (silently ignore data)
-- _error: expect
-- sop -> _txnak (send nak , to _txnak, _error)
-- eop -> _txeop (echo eop , to _txeop, _idle)
-- nak -> _txnak (echo nak , to _txnak, _error)
-- attn -> _txito (silently ignore attn)
-- data -> _idle (silently ignore data)
-- _rxcmd: expect
-- sop -> _txnak (send nak , to _txnak, _error)
-- eop -> _txeop (echo eop , to _txeop, _idle)
-- nak -> _txnak (echo nak , to _txnak, _error)
-- attn -> _txito (silently ignore attn)
-- data -> _idle (decode command)
-- _rx...: expect
-- sop -> _txnak (send nak , to _txnak, _error)
-- eop -> _txnak (send nak,eop , to _txnak, _txeop, _idle)
-- nak -> _txnak (echo nak , to _txnak, _error)
-- attn -> _txito (silently ignore attn)
-- data -> _idle (decode data)
--
-- 7 supported commands:
--
-- 000 read reg (rreg):
-- rx: cmd addr ccrc
-- tx: cmd dl dh stat crc
-- seq: _rxcmd _rxaddr _rxccrc (_txcmd|_txnak)
-- _rstart _rreg _txdatl _txdath _txstat _txcrc -> _rxcmd
--
-- 001 read blk (rblk):
-- rx: cmd addr cnt ccrc
-- tx: cmd cnt dl dh ... stat crc
-- seq: _rxcmd _rxaddr _rxcnt _rxccrc (_txcmd|_txnak) _txcnt
-- {_rstart _rreg _txdatl _txdath _blk}*
-- _txstat _txcrc -> _rxcmd
--
-- 010 write reg (wreg):
-- rx: cmd addr dl dh ccrc
-- tx: cmd stat crc
-- seq: _rxcmd _rxaddr _rxdatl _rxdath _rxccrc (_txcmd|_txnak)
-- _wstart _wreg _txstat _txcrc -> _rxcmd
--
-- 011 write blk (wblk):
-- rx: cmd addr cnt ccrc dl dh ... dcrc
-- tx: cmd stat crc
-- seq: _rxcmd _rxaddr _rxcnt _rxccrc (_txcmd|_txnak)
-- {_rxdatl _rxdath _wstart _wreg _blk}*
-- _rxdcrc _txstat _txcrc -> (_rxcmd|_txnak)
--
-- 100 read stat (stat):
-- rx: cmd ccrc
-- tx: cmd ccmd dl dh stat crc
-- seq: _rxcmd _rxccrc (_txcmd|_txnak)
-- _txccmd _txdatl _txdath _txstat _txcrc -> _rxcmd
--
-- 101 read attn (attn):
-- rx: cmd ccrc
-- tx: cmd dl dh stat crc
-- seq: _rxcmd _rxccrc (_txcmd|_txnak)
-- _attn _txdatl _txdath _txstat _txcrc -> _rxcmd
--
-- 110 write init (init):
-- rx: cmd addr dl dh ccrc
-- tx: cmd stat crc
-- seq: _rxcmd _rxaddr _rxdatl _rxdath _rxccrc (_txcmd|_txnak)
-- _txstat _txcrc -> _rxcmd
-- like wreg, but no rp_we - rp_hold, just a 1 cycle rp_init pulse
--
-- 111 is currently not a legal command and causes a nak
-- seq: _txnak
--
-- The state bits nakcerr and nakderr determine whether cerr/derr is set
-- when s_txnak is entered. cerr is '1' during command receive, derr is '1'
-- during data wblk data receive phase:
-- nakcerr set in s_rxcmd (when command received, unless it's stat)
-- clr in s_txcmd (when wblk)
-- clr in s_txnak
-- clr in s_txcrc (for sucessful completion)
-- nakderr set in s_txcmd (when wblk)
-- clr in s_txnak
-- clr in s_txcrc (for sucessful completion)
--
-- The different rbus cycle types are encoded as:
--
-- init aval re we
-- 0 0 0 0 idle
-- 0 0 1 0 not allowed
-- 0 0 0 1 not allowed
-- 0 1 1 0 read
-- 0 1 0 1 write
-- 1 0 0 0 internal init
-- 1 0 0 1 external init
-- 1 0 1 0 not allowed
-- * * 1 1 not allowed
-- 1 1 * * not allowed
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.comlib.all;
use work.rblib.all;
use work.rlinklib.all;
entity rlink_core is -- rlink core with 9bit interface
generic (
ATOWIDTH : positive := 5; -- access timeout counter width
ITOWIDTH : positive := 6); -- idle timeout counter width
port (
CLK : in slbit; -- clock
CE_INT : in slbit := '0'; -- rri ito time unit clock enable
RESET : in slbit; -- reset
RL_DI : in slv9; -- rlink 9b: data in
RL_ENA : in slbit; -- rlink 9b: data enable
RL_BUSY : out slbit; -- rlink 9b: data busy
RL_DO : out slv9; -- rlink 9b: data out
RL_VAL : out slbit; -- rlink 9b: data valid
RL_HOLD : in slbit; -- rlink 9b: data hold
RL_MONI : out rl_moni_type; -- rlink: monitor port
RB_MREQ : out rb_mreq_type; -- rbus: request
RB_SRES : in rb_sres_type; -- rbus: response
RB_LAM : in slv16; -- rbus: look at me
RB_STAT : in slv3 -- rbus: status flags
);
end entity rlink_core;
architecture syn of rlink_core is
type state_type is (
s_idle, -- s_idle: wait for sop
s_txito, -- s_txito: send timeout symbol
s_txsop, -- s_txsop: send sop
s_txnak, -- s_txnak: send nak
s_txeop, -- s_txeop: send eop
s_error, -- s_error: wait for eop
s_rxcmd, -- s_rxcmd: wait for cmd
s_rxaddr, -- s_rxaddr: wait for addr
s_rxdatl, -- s_rxdatl: wait for data low
s_rxdath, -- s_rxdath: wait for data high
s_rxcnt, -- s_rxcnt: wait for count
s_rxccrc, -- s_rxccrc: wait for command crc
s_txcmd, -- s_txcmd: send cmd
s_txcnt, -- s_txcnt: send cnt
s_rstart, -- s_rstart: start reg or blk read
s_rreg, -- s_rreg: do reg or blk read
s_txdatl, -- s_txdatl: send data low
s_txdath, -- s_txdath: send data high
s_wstart, -- s_wstart: start reg or blk write
s_wreg, -- s_wreg: do reg or blk write
s_blk, -- s_blk: block count handling
s_rxdcrc, -- s_rxdcrc: wait for data crc
s_attn, -- s_attn: handle attention flags
s_txccmd, -- s_txccmd: send last command
s_txstat, -- s_txstat: send status
s_txcrc -- s_txcrc: send crc
);
type regs_type is record
state : state_type; -- state
rcmd : slv8; -- received command
ccmd : slv8; -- current command
addr : slv8; -- register address
dil : slv8; -- input data, lsb
dih : slv8; -- input data, msb
dol : slv8; -- output data, lsb
doh : slv8; -- output data, msb
cnt : slv8; -- block transfer count
attn : slv16; -- attn mask
atocnt : slv(ATOWIDTH-1 downto 0); -- access timeout counter
itocnt : slv(ITOWIDTH-1 downto 0); -- idle timeout counter
itoval : slv(ITOWIDTH-1 downto 0); -- idle timeout value
itoena : slbit; -- idle timeout enable flag
anena : slbit; -- attn notification enable flag
andone : slbit; -- attn notification done
cerr : slbit; -- stat: command error
derr : slbit; -- stat: data error
rbnak: slbit; -- stat: rbus no ack or timeout
rberr : slbit; -- stat: rbus err bit set
nakeop : slbit; -- send eop after nak
nakcerr : slbit; -- set cerr after nak
nakderr : slbit; -- set derr after nak
rbinit : slbit; -- rbus init signal
rbaval : slbit; -- rbus aval signal
rbre : slbit; -- rbus re signal
rbwe : slbit; -- rbus we signal
moneop : slbit; -- rl_moni: eop send pulse
monattn : slbit; -- rl_moni: attn send pulse
monlamp : slbit; -- rl_moni: attn pending state
stat : slv3; -- external status flags
end record regs_type;
constant atocnt_init : slv(ATOWIDTH-1 downto 0) := (others=>'1');
constant itocnt_init : slv(ITOWIDTH-1 downto 0) := (others=>'0');
constant c_idle : slv4 := "0000";
constant c_sop : slv4 := "0001";
constant c_eop : slv4 := "0010";
constant c_nak : slv4 := "0011";
constant c_attn : slv4 := "0100";
constant regs_init : regs_type := (
s_idle, --
(others=>'0'), -- rcmd
(others=>'0'), -- ccmd
(others=>'0'), -- addr
(others=>'0'), -- dil
(others=>'0'), -- dih
(others=>'0'), -- dol
(others=>'0'), -- doh
(others=>'0'), -- cnt
(others=>'0'), -- attn
atocnt_init, -- atocnt
itocnt_init, -- itocnt
itocnt_init, -- itoval
'0', -- itoena
'0','0', -- anena, andone
'0','0','0','0', -- stat flags
'0','0','0', -- nakeop,nakcerr,nakderr
'0','0','0','0', -- rbinit,rbaval,rbre,rbwe
'0','0','0', -- moneop,monattn,monlamp
(others=>'0') -- stat
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal CRC_RESET : slbit := '0';
signal ICRC_ENA : slbit := '0';
signal OCRC_ENA : slbit := '0';
signal ICRC_OUT : slv8 := (others=>'0');
signal OCRC_OUT : slv8 := (others=>'0');
signal OCRC_IN : slv8 := (others=>'0');
begin
assert ITOWIDTH<=8
report "assert(ITOWIDTH<=8): max byte size ITO counter supported"
severity failure;
ICRC : crc8 -- crc generator for input data
port map (
CLK => CLK,
RESET => CRC_RESET,
ENA => ICRC_ENA,
DI => RL_DI(7 downto 0),
CRC => ICRC_OUT
);
OCRC : crc8 -- crc generator for output data
port map (
CLK => CLK,
RESET => CRC_RESET,
ENA => OCRC_ENA,
DI => OCRC_IN,
CRC => OCRC_OUT
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_INT, RL_DI, RL_ENA, RL_HOLD, RB_LAM,
RB_SRES, RB_STAT, ICRC_OUT, OCRC_OUT)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable ival : slbit := '0';
variable ibusy : slbit := '0';
variable ido : slv9 := (others=>'0');
variable ato_go : slbit := '0';
variable ato_end : slbit := '0';
variable ito_go : slbit := '0';
variable ito_end : slbit := '0';
variable crcreset : slbit := '0';
variable icrcena : slbit := '0';
variable ocrcena : slbit := '0';
variable has_attn : slbit := '0';
variable snd_attn : slbit := '0';
variable idi8 : slv8 := (others=>'0');
variable is_comma : slbit := '0';
variable comma_typ : slv4 := "0000";
procedure do_comma_abort(nstate : inout state_type;
nnakeop : inout slbit;
comma_typ : in slv4) is
begin
if comma_typ=c_sop or comma_typ=c_eop or comma_typ=c_nak then
if comma_typ = c_eop then
nnakeop := '1';
end if;
nstate := s_txnak; -- next: send nak
end if;
end procedure do_comma_abort;
begin
r := R_REGS;
n := R_REGS;
idi8 := RL_DI(7 downto 0); -- get data part of RL_DI
is_comma := RL_DI(8); -- get comma marker
comma_typ := RL_DI(3 downto 0); -- get comma type
n.rbinit := '0'; -- clear rb(init|aval|re|we) by default
n.rbaval := '0'; -- they must always be set by the
n.rbre := '0'; -- 'previous state'
n.rbwe := '0'; --
n.moneop := '0'; -- default '0', only set by states
n.monattn := '0'; -- "
n.monlamp := '0'; --
ibusy := '1'; -- default is to hold input
ival := '0';
ido := (others=>'0');
crcreset := '0';
icrcena := '0';
ocrcena := '0';
for i in RB_LAM'range loop -- handle attention "LAM's"
if RB_LAM(i) = '1' then -- if LAM bit set
n.attn(i) := '1'; -- set attention bit
end if;
end loop;
has_attn := '0';
snd_attn := '0';
if unsigned(r.attn) /= 0 then -- is any of the attn bits set ?
has_attn := '1';
if r.anena='1' and r.andone='0' then -- is attn notification to be send ?
snd_attn := '1';
n.monlamp := '1'; -- set lamp flag in rl_moni
end if;
end if;
ato_go := '0'; -- default: keep access timeout in reset
ato_end := '0';
if unsigned(r.atocnt) = 0 then -- if access timeout count at zero
ato_end := '1'; -- signal expiration
end if;
ito_go := '0'; -- default: keep idle timeout in reset
ito_end := '0';
if unsigned(r.itocnt) = 0 then -- if idle timeout count at zero
ito_end := '1'; -- signal expiration
end if;
case r.state is
when s_idle => -- s_idle: wait for sop --------------
ito_go := '1'; -- idle timeout active
if snd_attn = '1' then -- if attn notification to be send
n.state := s_txito; -- next: send ito byte
else
ibusy := '0'; -- accept input
if RL_ENA = '1' then -- if input
if is_comma = '1' then -- if comma
case comma_typ is
when c_sop => -- if sop
crcreset := '1'; -- reset crc generators
n.state := s_txsop; -- next: echo it
when c_eop => -- if eop (unexpected)
n.nakeop := '1'; -- send nak,eop
n.state := s_txnak; -- next: send nak
when c_attn => -- if attn
n.state := s_txito; -- next: send ito byte
when others => null; -- other commas: silently ignore
end case;
else -- if normal data
n.state := s_idle; -- silently dropped
end if;
elsif (r.itoena='1' and -- if ito enable, expired and XSEC
ito_end='1' and CE_INT='1') then
n.state := s_txito; -- next: send ito byte
end if;
end if;
when s_txito => -- s_txito: send timeout symbol ------
if has_attn = '1' then
ido := c_rlink_dat_attn; -- if attn pending: send attn symbol
n.andone := '1';
else
ido := c_rlink_dat_idle; -- otherwise: send idle symbol
end if;
ival := '1';
if RL_HOLD = '0' then -- wait for accept
n.monattn := has_attn; -- signal on rl_moni
n.state := s_idle; -- next: wait for sop
end if;
when s_txsop => -- s_txsop: send sop -----------------
ido := c_rlink_dat_sop; -- send sop character
ival := '1';
if RL_HOLD = '0' then -- wait for accept
n.state := s_rxcmd; -- next: read first command
end if;
when s_txnak => -- s_txnak: send nak -----------------
ido := c_rlink_dat_nak; -- send nak character
ival := '1';
if RL_HOLD = '0' then -- wait for accept
n.nakeop := '0'; -- clear all 'do on nak' state flags
n.nakcerr := '0';
n.nakderr := '0';
if r.nakcerr = '1' then -- if setting cerr requested
n.cerr := '1'; -- do it
end if;
if r.nakderr = '1' then -- if settung derr requested
n.derr := '1'; -- do it
end if;
if r.nakeop = '1' then -- if eop after nak requested
n.state := s_txeop; -- next: send eop
else
n.state := s_error; -- next: error state, wait for eop
end if;
end if;
when s_txeop => -- s_txeop: send eop -----------------
ido := c_rlink_dat_eop; -- send eop character
ival := '1';
if RL_HOLD = '0' then -- wait for accept
n.moneop := '1'; -- signal on rl_moni
n.state := s_idle; -- next: idle state, wait for sop
end if;
when s_error => -- s_error: wait for eop -------------
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
case comma_typ is
when c_sop => -- if sop (unexpected)
n.state := s_txnak; -- next: send nak
when c_eop => -- if eop
n.state := s_txeop; -- next: echo eop
when c_nak => -- if nak
n.state := s_txnak; -- next: echo nak
when others => null; -- other commas: silently ignore
end case;
else -- if normal data
n.state := s_error; -- silently dropped
end if;
end if;
when s_rxcmd => -- s_rxcmd: wait for cmd -------------
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
case comma_typ is
when c_sop => -- if sop (unexpected)
n.state := s_txnak; -- next: send nak
when c_eop => -- if eop
n.state := s_txeop; -- next: echo eop
when c_nak => -- if nak
n.state := s_txnak; -- next: echo nak
when others => null; --other commas: silently ignore
end case;
else -- if not comma
icrcena := '1'; -- update input crc
n.rcmd := idi8; -- latch received command code
-- unless the command is stat
if RL_DI(c_rlink_cmd_rbf_code) /= c_rlink_cmd_stat then
n.nakcerr := '1'; -- set cerr on eop/nak abort
end if;
case RL_DI(c_rlink_cmd_rbf_code) is
when c_rlink_cmd_rreg |
c_rlink_cmd_rblk |
c_rlink_cmd_wreg |
c_rlink_cmd_wblk |
c_rlink_cmd_init => -- for commands needing addr(data)
n.state := s_rxaddr; -- next: read address
when c_rlink_cmd_stat |
c_rlink_cmd_attn => -- stat and attn commands
n.state := s_rxccrc; -- next: read command crc
when others =>
n.state := s_txnak; -- next: send nak
end case; -- rcmd,ccmd always hold good cmd
end if;
end if;
when s_rxaddr => -- s_rxaddr: wait for addr -----------
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
do_comma_abort(n.state, n.nakeop, comma_typ);
else
icrcena := '1'; -- update input crc
n.addr := idi8; -- latch read address
case r.rcmd(c_rlink_cmd_rbf_code) is
when c_rlink_cmd_rreg => -- for rreg command
n.state := s_rxccrc; -- next: read command crc
when c_rlink_cmd_wreg |
c_rlink_cmd_init => -- for wreg, init command
n.state := s_rxdatl; -- next: read data lsb
when others => -- for rblk or wblk
n.state := s_rxcnt; -- next: read count
end case;
end if;
end if;
when s_rxdatl => -- s_rxdatl: wait for data low -------
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
do_comma_abort(n.state, n.nakeop, comma_typ);
else
icrcena := '1'; -- update input crc
n.dil := idi8; -- latch data lsb part
n.state := s_rxdath; -- next: read data msb
end if;
end if;
when s_rxdath => -- s_rxdath: wait for data high ------
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
do_comma_abort(n.state, n.nakeop, comma_typ);
else
icrcena := '1'; -- update input crc
n.dih := idi8; -- latch data msb part
if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_wblk then -- if wblk
n.rbaval := '1'; -- prepare rbus cycle
n.state := s_wstart; -- next: start write reg
else -- otherwise
n.state := s_rxccrc; -- next: read command crc
end if;
end if;
end if;
when s_rxcnt => -- s_rxcnt: wait for count -----------
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
do_comma_abort(n.state, n.nakeop, comma_typ);
else
icrcena := '1'; -- update input crc
n.cnt := idi8; -- latch count
n.state := s_rxccrc; -- next: read command crc
end if;
end if;
when s_rxccrc => -- s_rxccrc: wait for command crc ----
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
do_comma_abort(n.state, n.nakeop, comma_typ);
else
if idi8 /= ICRC_OUT then -- if crc error
-- unless the command is stat
if r.rcmd(c_rlink_cmd_rbf_code) /= c_rlink_cmd_stat then
n.cerr := '1'; -- set command error flag
end if;
n.state := s_txnak; -- next: send nak
else -- if crc ok
n.state := s_txcmd; -- next: echo command
end if;
end if;
end if;
when s_txcmd => -- s_txcmd: send cmd -----------------
ido := '0' & r.rcmd; -- send read command
ival := '1';
if RL_HOLD = '0' then -- wait for accept
ocrcena := '1'; -- update output crc
if r.rcmd(c_rlink_cmd_rbf_code) /= c_rlink_cmd_stat then --unless stat
n.ccmd := r.rcmd; -- latch current command in ccmd
n.stat := RB_STAT; -- latch external status bits
n.cerr := '0';
n.derr := '0';
n.rbnak := '0';
n.rberr := '0';
end if;
n.nakcerr := '0'; -- all command rx done up to here
case r.rcmd(c_rlink_cmd_rbf_code) is -- main command dispatcher
when c_rlink_cmd_rreg => -- rreg ----------------
n.rbaval := '1'; -- prepare rbus cycle
n.state := s_rstart; -- next: start read reg
when c_rlink_cmd_rblk => -- rblk ----------------
n.state := s_txcnt;
when c_rlink_cmd_wreg => -- wreg ----------------
n.rbaval := '1'; -- prepare rbus cycle
n.state := s_wstart; -- next: start write reg
when c_rlink_cmd_wblk => -- wblk ----------------
n.nakderr := '1'; -- set derr on eop/nak abort
n.state := s_rxdatl;
when c_rlink_cmd_stat => -- stat ----------------
n.state := s_txccmd;
when c_rlink_cmd_attn => -- attn ----------------
n.state := s_attn;
when c_rlink_cmd_init => -- init ----------------
n.rbinit := '1'; -- send init pulse
if r.addr(7 downto 3) = "11111" then -- is internal init
if r.addr(2 downto 0) = "111" then -- is rri init
n.anena := r.dih(c_rlink_iint_rbf_anena - 8);
n.itoena := r.dih(c_rlink_iint_rbf_itoena - 8);
n.itoval := r.dil(ITOWIDTH-1 downto 0);
-- note: itocnt will load in next
-- cycle because ito_go=0, so no
-- action required here
end if;
else -- is external init
n.rbwe := '1'; -- send init with we
end if;
n.state := s_txstat;
when others => -- '111' ---------------
n.state := s_txnak; -- send NAK on reserved command
end case;
end if;
when s_txcnt => -- s_txcnt: send cnt -----------------
ido := '0' & r.cnt; -- send cnt
ival := '1';
if RL_HOLD = '0' then -- wait for accept
ocrcena := '1'; -- update output crc
n.rbaval := '1'; -- prepare rbus cycle
n.state := s_rstart; -- next: start first read reg
end if;
when s_rstart => -- s_rstart: start reg or blk read ---
n.rbaval := '1'; -- start actual read cycle
n.rbre := '1';
n.state := s_rreg; -- next: reg read
when s_rreg => -- s_rreg: do reg or blk read --------
-- this state handles all rbus reads
ato_go := '1'; -- activate timeout counter
if RB_SRES.err = '1' then -- latch rbus error flag
n.rberr := '1';
end if;
n.doh := RB_SRES.dout(15 downto 8); -- latch data
n.dol := RB_SRES.dout( 7 downto 0);
n.stat := RB_STAT; -- latch external status bits
if RB_SRES.busy='0' or ato_end='1' then -- wait for non-busy or timeout
if RB_SRES.busy='1' and ato_end='1' then -- if timeout and still busy
n.rbnak := '1'; -- set rbus nak flag
elsif RB_SRES.ack = '0' then -- if non-busy and no ack
n.rbnak := '1'; -- set rbus nak flag
end if;
n.state := s_txdatl; -- next: send data lsb
else -- otherwise rbus read continues
n.rbaval := '1'; -- extend cycle
n.rbre := '1';
end if;
when s_txdatl => -- s_txdatl: send data low -----------
ido := '0' & r.dol; -- send data
ival := '1';
if RL_HOLD = '0' then -- wait for accept
ocrcena := '1'; -- update output crc
n.state := s_txdath; -- next: send data msb
end if;
when s_txdath => -- s_txdath: send data high
ido := '0' & r.doh; -- send data
ival := '1';
if RL_HOLD = '0' then -- wait for accept
ocrcena := '1'; -- update output crc
if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_rblk then -- if rblk
n.state := s_blk; -- next: block count handling
else -- otherwise
n.state := s_txstat; -- next: send stat
end if;
end if;
when s_wstart => -- s_wstart: start reg or blk write --
n.rbaval := '1'; -- start actual write cycle
n.rbwe := '1';
n.state := s_wreg; -- next: reg write
when s_wreg => -- s_wreg: do reg or blk write -------
-- this state handles all rbus writes
ato_go := '1'; -- activate timeout counter
if RB_SRES.err = '1' then -- latch rbus error flag
n.rberr := '1';
end if;
n.stat := RB_STAT; -- latch external status bits
if RB_SRES.busy='0' or ato_end='1' then -- wait for non-busy or timeout
if RB_SRES.busy='1' and ato_end='1' then -- if timeout and still busy
n.rbnak := '1'; -- set rbus nak flag
elsif RB_SRES.ack='0' then -- if non-busy and no ack
n.rbnak := '1'; -- set rbus nak flag
end if;
if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_wblk then -- if wblk
n.state := s_blk; -- next: block count handling
else -- otherwise
n.state := s_txstat; -- next: send stat
end if;
else -- otherwise rbus write continues
n.rbaval := '1'; -- extend cycle
n.rbwe := '1';
end if;
when s_blk => -- s_blk: block count handling -------
n.cnt := slv(unsigned(r.cnt) - 1);-- decrement transfer count
if unsigned(r.cnt) = 0 then -- if last transfer
if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_rblk then -- if rblk
n.state := s_txstat; -- next: send stat
else -- otherwise
n.state := s_rxdcrc; -- next: read data crc
end if;
else -- otherwise more to transfer
if r.rcmd(c_rlink_cmd_rbf_code) = c_rlink_cmd_rblk then -- if rblk
n.rbaval := '1'; -- prepare rbus cycle
n.state := s_rstart; -- next: start read blk
else -- otherwise
n.state := s_rxdatl; -- next: read data
end if;
end if;
when s_rxdcrc => -- s_rxdcrc: wait for data crc -------
ibusy := '0'; -- accept input
if RL_ENA = '1' then
if is_comma = '1' then -- if comma
do_comma_abort(n.state, n.nakeop, comma_typ);
else
if idi8 /= ICRC_OUT then -- if crc error
n.derr := '1'; -- set data error flag
end if;
n.state := s_txstat; -- next: echo command
end if;
end if;
when s_attn => -- s_attn: handle attention flags ----
n.dol := r.attn(7 downto 0); -- move attention flags to do buffer
n.doh := r.attn(15 downto 8);
n.attn := RB_LAM; -- LAM in current cycle send next time
n.andone := '0'; -- reenable attn nofification
n.state := s_txdatl; -- next: send data lsb
when s_txccmd => -- s_txccmd: send last command
ido := '0' & r.ccmd; -- send last accepted command
ival := '1';
if RL_HOLD = '0' then -- wait for accept
ocrcena := '1'; -- update output crc
n.state := s_txdatl; -- next: send last data lsb
end if;
when s_txstat => -- s_txstat: send status -------------
ido := (others=>'0');
ido(c_rlink_stat_rbf_stat) := r.stat;
ido(c_rlink_stat_rbf_attn) := has_attn;
ido(c_rlink_stat_rbf_cerr) := r.cerr;
ido(c_rlink_stat_rbf_derr) := r.derr;
ido(c_rlink_stat_rbf_rbnak) := r.rbnak;
ido(c_rlink_stat_rbf_rberr) := r.rberr;
ival := '1';
if RL_HOLD ='0' then -- wait for accept
ocrcena := '1'; -- update output crc
n.state := s_txcrc; -- next: send crc
end if;
when s_txcrc => -- s_txcrc: send crc -----------------
ido := "0" & OCRC_OUT; -- send crc code
ival := '1';
if RL_HOLD = '0' then -- wait for accept
-- if dcrc seen in wblk
if r.rcmd(c_rlink_cmd_rbf_code)=c_rlink_cmd_wblk and r.derr='1' then
n.state := s_txnak; -- next: send nak
else -- otherwise
n.nakcerr := '0'; -- clear 'set on nak' requests
n.nakderr := '0';
n.state := s_rxcmd; -- next: read command or eop
end if;
end if;
when others => null; -- <> --------------------------------
end case;
if ato_go = '0' then -- handle access timeout counter
n.atocnt := atocnt_init; -- if ato_go=0, keep in reset
else
n.atocnt := slv(unsigned(r.atocnt) - 1);-- otherwise count down
end if;
if ito_go = '0' then -- handle idle timeout counter
n.itocnt := r.itoval; -- if ito_go=0, keep at start value
else
if CE_INT = '1' then
n.itocnt := slv(unsigned(r.itocnt) - 1);-- otherwise cnt dn every CE_INT
end if;
end if;
N_REGS <= n;
RL_BUSY <= ibusy;
RL_DO <= ido;
RL_VAL <= ival;
RL_MONI.eop <= r.moneop;
RL_MONI.attn <= r.monattn;
RL_MONI.lamp <= r.monlamp;
RB_MREQ <= rb_mreq_init;
RB_MREQ.aval <= r.rbaval;
RB_MREQ.re <= r.rbre;
RB_MREQ.we <= r.rbwe;
RB_MREQ.init <= r.rbinit;
RB_MREQ.addr <= r.addr;
RB_MREQ.din <= r.dih & r.dil;
CRC_RESET <= crcreset;
ICRC_ENA <= icrcena;
OCRC_ENA <= ocrcena;
OCRC_IN <= ido(7 downto 0);
end process proc_next;
end syn;
| gpl-2.0 |
freecores/w11 | rtl/sys_gen/tst_serloop/tst_serloop.vhd | 1 | 7740 | -- $Id: tst_serloop.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tst_serloop - syn
-- Description: simple stand-alone tester for serport components
--
-- Dependencies: -
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-10 438 1.0.2 clr fecnt when abact; add rxui(cnt|dat) regs
-- 2011-12-09 437 1.0.1 rename serport stat->moni port
-- 2011-11-06 420 1.0 Initial version
-- 2011-10-14 416 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.tst_serlooplib.all;
-- ----------------------------------------------------------------------------
entity tst_serloop is -- tester for serport components
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CE_MSEC : in slbit; -- msec pulse
HIO_CNTL : in hio_cntl_type; -- humanio controls
HIO_STAT : out hio_stat_type; -- humanio status
SER_MONI : in serport_moni_type; -- serport monitor
RXDATA : in slv8; -- receiver data out
RXVAL : in slbit; -- receiver data valid
RXHOLD : out slbit; -- receiver data hold
TXDATA : out slv8; -- transmit data in
TXENA : out slbit; -- transmit data enable
TXBUSY : in slbit -- transmit busy
);
end tst_serloop;
architecture syn of tst_serloop is
type regs_type is record
rxdata : slv8; -- next rx char
txdata : slv8; -- next tx char
rxfecnt : slv16; -- rx frame error counter
rxoecnt : slv16; -- rx overrun error counter
rxsecnt : slv16; -- rx sequence error counter
rxcnt : slv32; -- rx char counter
txcnt : slv32; -- tx char counter
rxuicnt : slv8; -- rx unsolicited input counter
rxuidat : slv8; -- rx unsolicited input data
rxokcnt : slv16; -- rxok 1->0 transition counter
txokcnt : slv16; -- txok 1->0 transition counter
rxok_1 : slbit; -- rxok last cycle
txok_1 : slbit; -- txok last cycle
rxthrottle : slbit; -- rx throttle flag
end record regs_type;
constant regs_init : regs_type := (
(others=>'0'), -- rxdata
(others=>'0'), -- txdata
(others=>'0'), -- rxfecnt
(others=>'0'), -- rxoecnt
(others=>'0'), -- rxsecnt
(others=>'0'), -- rxcnt
(others=>'0'), -- txcnt
(others=>'0'), -- rxuicnt
(others=>'0'), -- rxuidat
(others=>'0'), -- rxokcnt
(others=>'0'), -- txokcnt
'0','0', -- rxok_1,txok_1
'0' -- rxthrottle
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, CE_MSEC, HIO_CNTL, SER_MONI,
RXDATA, RXVAL, TXBUSY)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irxhold : slbit := '1';
variable itxena : slbit := '0';
variable itxdata : slv8 := (others=>'0');
variable skipxon : slbit := '0';
function nextchar(skipxon: in slbit; data: in slv8) return slv8 is
variable inc : slv8 := (others=>'0');
begin
inc := "00000001";
if skipxon='1' and (data=c_serport_xon or data=c_serport_xoff) then
inc := "00000010";
end if;
return slv(unsigned(data)+unsigned(inc));
end function nextchar;
begin
r := R_REGS;
n := R_REGS;
irxhold := '1';
itxena := '0';
itxdata := RXDATA;
if HIO_CNTL.mode = c_mode_txblast then
itxdata := r.txdata;
end if;
skipxon := '0';
if HIO_CNTL.enaxon='1' and HIO_CNTL.enaesc='0' then
skipxon := '1';
end if;
if HIO_CNTL.enathrottle = '1' then
if CE_MSEC = '1' then
n.rxthrottle := not r.rxthrottle;
end if;
else
n.rxthrottle := '0';
end if;
case HIO_CNTL.mode is
when c_mode_idle =>
null;
when c_mode_rxblast =>
if RXVAL='1' and r.rxthrottle='0' then
irxhold := '0';
if RXDATA /= r.rxdata then
n.rxsecnt := slv(unsigned(r.rxsecnt) + 1);
end if;
n.rxdata := nextchar(skipxon, RXDATA);
end if;
when c_mode_txblast =>
if TXBUSY = '0' then
itxena := '1';
n.txdata := nextchar(skipxon, r.txdata);
end if;
irxhold := '0';
if RXVAL = '1' then
n.rxuicnt := slv(unsigned(r.rxuicnt) + 1);
n.rxuidat := RXDATA;
end if;
when c_mode_loop =>
if RXVAL='1' and r.rxthrottle='0' and TXBUSY = '0' then
irxhold := '0';
itxena := '1';
end if;
when others => null;
end case;
if SER_MONI.abact = '1' then -- if auto bauder active
n.rxfecnt := (others=>'0'); -- reset frame error counter
else -- otherwise
if SER_MONI.rxerr = '1' then -- count rx frame errors
n.rxfecnt := slv(unsigned(r.rxfecnt) + 1);
end if;
end if;
if SER_MONI.rxovr = '1' then
n.rxoecnt := slv(unsigned(r.rxoecnt) + 1);
end if;
if RXVAL='1' and irxhold='0' then
n.rxcnt := slv(unsigned(r.rxcnt) + 1);
end if;
if itxena = '1' then
n.txcnt := slv(unsigned(r.txcnt) + 1);
end if;
n.rxok_1 := SER_MONI.rxok;
n.txok_1 := SER_MONI.txok;
if SER_MONI.rxok='0' and r.rxok_1='1' then
n.rxokcnt := slv(unsigned(r.rxokcnt) + 1);
end if;
if SER_MONI.txok='0' and r.txok_1='1' then
n.txokcnt := slv(unsigned(r.txokcnt) + 1);
end if;
N_REGS <= n;
RXHOLD <= irxhold;
TXENA <= itxena;
TXDATA <= itxdata;
HIO_STAT.rxfecnt <= r.rxfecnt;
HIO_STAT.rxoecnt <= r.rxoecnt;
HIO_STAT.rxsecnt <= r.rxsecnt;
HIO_STAT.rxcnt <= r.rxcnt;
HIO_STAT.txcnt <= r.txcnt;
HIO_STAT.rxuicnt <= r.rxuicnt;
HIO_STAT.rxuidat <= r.rxuidat;
HIO_STAT.rxokcnt <= r.rxokcnt;
HIO_STAT.txokcnt <= r.txokcnt;
end process proc_next;
end syn;
| gpl-2.0 |
freecores/w11 | rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vhd | 1 | 12625 | -- $Id: sys_tst_fx2loop_n3.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2012-2013 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_fx2loop_n3 - syn
-- Description: test of Cypress EZ-USB FX2 controller
--
-- Dependencies: vlib/xlib/s6_cmt_sfs
-- vlib/genlib/clkdivce
-- bpgen/sn_humanio
-- tst_fx2loop_hiomap
-- tst_fx2loop
-- bplib/fx2lib/fx2_2fifoctl_as [sys_conf_fx2_type="as2"]
-- bplib/fx2lib/fx2_2fifoctl_ic [sys_conf_fx2_type="ic2"]
-- bplib/fx2lib/fx2_3fifoctl_ic [sys_conf_fx2_type="ic3"]
-- bplib/nxcramlib/nx_cram_dummy
--
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3, 14.5, 14.6; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz
-- 2013-04-25 510 14.5 P58f xc6slx16-2 416 516 68 199 p 5.3 ic3/150
-- 2013-04-24 510 13.3 O76d xc6slx16-2 417 674 68 228 p 5.3 ic3/175
-- 2012-04-09 461 13.3 O76d xc6slx16-2 429 620 48 232 p 7.2 ic3/100
--
-- 2013-04-25 510 14.5 P58f xc6slx16-2 349 427 48 163 p 5.4 ic2/150
-- 2013-04-24 510 13.3 O76d xc6slx16-2 355 569 48 208 p 5.4 ic2/175
-- 2012-04-09 461 13.3 O76d xc6slx16-2 347 499 32 175 p 7.9 ic2/100
--
-- 2013-04-24 510 13.3 O76d xc6slx16-2 299 486 32 175 p FAIL as2/100
-- 2012-04-09 461 13.3 O76d xc6slx16-2 299 460 32 164 p FAIL as2/100
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
-- 2013-04-24 510 1.0.1 CLKDIV.CDUWIDTH now 8, support >127 sysclk
-- 2012-04-09 461 1.0 Initial version (derived from sys_tst_fx2loop_n2)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.bpgenlib.all;
use work.tst_fx2looplib.all;
use work.fx2lib.all;
use work.nxcramlib.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_tst_fx2loop_n3 is -- top level
-- implements nexys3_aif + fx2 pins
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n3 switches
I_BTN : in slv5; -- n3 buttons
O_LED : out slv8; -- n3 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_PPCM_CE_N : out slbit; -- ppcm: ...
O_PPCM_RST_N : out slbit; -- ppcm: ...
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end sys_tst_fx2loop_n3;
architecture syn of sys_tst_fx2loop_n3 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal SWI : slv8 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv8 := (others=>'0');
signal DSP_DAT : slv16 := (others=>'0');
signal DSP_DP : slv4 := (others=>'0');
signal LED_MAP : slv8 := (others=>'0');
signal HIO_CNTL : hio_cntl_type := hio_cntl_init;
signal HIO_STAT : hio_stat_type := hio_stat_init;
signal FX2_RXDATA : slv8 := (others=>'0');
signal FX2_RXVAL : slbit := '0';
signal FX2_RXHOLD : slbit := '0';
signal FX2_RXAEMPTY : slbit := '0';
signal FX2_TXDATA : slv8 := (others=>'0');
signal FX2_TXENA : slbit := '0';
signal FX2_TXBUSY : slbit := '0';
signal FX2_TXAFULL : slbit := '0';
signal FX2_TX2DATA : slv8 := (others=>'0');
signal FX2_TX2ENA : slbit := '0';
signal FX2_TX2BUSY : slbit := '1';
signal FX2_TX2AFULL : slbit := '0';
signal FX2_MONI : fx2ctl_moni_type := fx2ctl_moni_init;
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
GEN_CLKSYS : s6_cmt_sfs
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,
LOCKED => open
);
CLKDIV : clkdivce
generic map (
CDUWIDTH => 8, -- good for up to 255 MHz !
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
HIO : sn_humanio
generic map (
BWIDTH => 5,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => '0',
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
RESET <= BTN(0); -- BTN(0) will reset tester !!
HIOMAP : tst_fx2loop_hiomap
port map (
CLK => CLK,
RESET => RESET,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
FX2_MONI => FX2_MONI,
SWI => SWI,
BTN => BTN(3 downto 0),
LED => LED_MAP,
DSP_DAT => DSP_DAT,
DSP_DP => DSP_DP
);
proc_led: process (SWI, LED_MAP, FX2_TX2BUSY, FX2_TX2ENA,
FX2_TXBUSY, FX2_TXENA, FX2_RXHOLD, FX2_RXVAL)
begin
if SWI(4) = '1' then
LED(7) <= '0';
LED(6) <= '0';
LED(5) <= FX2_TX2BUSY;
LED(4) <= FX2_TX2ENA;
LED(3) <= FX2_TXBUSY;
LED(2) <= FX2_TXENA;
LED(1) <= FX2_RXHOLD;
LED(0) <= FX2_RXVAL;
else
LED <= LED_MAP;
end if;
end process proc_led;
TST : tst_fx2loop
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
HIO_CNTL => HIO_CNTL,
HIO_STAT => HIO_STAT,
FX2_MONI => FX2_MONI,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TX2DATA => FX2_TX2DATA,
TX2ENA => FX2_TX2ENA,
TX2BUSY => FX2_TX2BUSY
);
FX2_CNTL_AS : if sys_conf_fx2_type = "as2" generate
CNTL : fx2_2fifoctl_as
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1,
PETOWIDTH => sys_conf_fx2_petowidth,
RDPWLDELAY => sys_conf_fx2_rdpwldelay,
RDPWHDELAY => sys_conf_fx2_rdpwhdelay,
WRPWLDELAY => sys_conf_fx2_wrpwldelay,
WRPWHDELAY => sys_conf_fx2_wrpwhdelay,
FLAGDELAY => sys_conf_fx2_flagdelay)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_AS;
FX2_CNTL_IC : if sys_conf_fx2_type = "ic2" generate
CNTL : fx2_2fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC;
FX2_CNTL_IC3 : if sys_conf_fx2_type = "ic3" generate
CNTL : fx2_3fifoctl_ic
generic map (
RXFAWIDTH => 5,
TXFAWIDTH => 5,
PETOWIDTH => sys_conf_fx2_petowidth,
CCWIDTH => sys_conf_fx2_ccwidth,
RXAEMPTY_THRES => 1,
TXAFULL_THRES => 1,
TX2AFULL_THRES => 1)
port map (
CLK => CLK,
RESET => RESET,
RXDATA => FX2_RXDATA,
RXVAL => FX2_RXVAL,
RXHOLD => FX2_RXHOLD,
RXAEMPTY => FX2_RXAEMPTY,
TXDATA => FX2_TXDATA,
TXENA => FX2_TXENA,
TXBUSY => FX2_TXBUSY,
TXAFULL => FX2_TXAFULL,
TX2DATA => FX2_TX2DATA,
TX2ENA => FX2_TX2ENA,
TX2BUSY => FX2_TX2BUSY,
TX2AFULL => FX2_TX2AFULL,
MONI => FX2_MONI,
I_FX2_IFCLK => I_FX2_IFCLK,
O_FX2_FIFO => O_FX2_FIFO,
I_FX2_FLAG => I_FX2_FLAG,
O_FX2_SLRD_N => O_FX2_SLRD_N,
O_FX2_SLWR_N => O_FX2_SLWR_N,
O_FX2_SLOE_N => O_FX2_SLOE_N,
O_FX2_PKTEND_N => O_FX2_PKTEND_N,
IO_FX2_DATA => IO_FX2_DATA
);
end generate FX2_CNTL_IC3;
SRAM_PROT : nx_cram_dummy -- connect CRAM to protection dummy
port map (
O_MEM_CE_N => O_MEM_CE_N,
O_MEM_BE_N => O_MEM_BE_N,
O_MEM_WE_N => O_MEM_WE_N,
O_MEM_OE_N => O_MEM_OE_N,
O_MEM_ADV_N => O_MEM_ADV_N,
O_MEM_CLK => O_MEM_CLK,
O_MEM_CRE => O_MEM_CRE,
I_MEM_WAIT => I_MEM_WAIT,
O_MEM_ADDR => O_MEM_ADDR,
IO_MEM_DATA => IO_MEM_DATA
);
O_PPCM_CE_N <= '1'; -- keep parallel PCM memory disabled
O_PPCM_RST_N <= '1'; --
O_TXD <= I_RXD; -- loop-back in serial port...
end syn;
| gpl-2.0 |
freecores/w11 | rtl/sys_gen/tst_serloop/s3board/sys_conf.vhd | 2 | 1484 | -- $Id: sys_conf.vhd 441 2011-12-20 17:01:16Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_serloop_s3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-13 424 1.0 Initial version
-- 2011-10-25 419 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkdiv_usecdiv : integer := 60; -- default usec
constant sys_conf_clkdiv_msecdiv : integer := 1000; -- default msec
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
constant sys_conf_uart_cdinit : integer := 521-1; -- 60000000/115200
end package sys_conf;
| gpl-2.0 |
freecores/w11 | rtl/bplib/bpgen/sn_4x7segctl.vhd | 2 | 5432 | -- $Id: sn_4x7segctl.vhd 410 2011-09-18 11:23:09Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sn_4x7segctl - syn
-- Description: Quad 7 segment display controller (for s3board and nexys2/3)
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 12.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-09-17 410 1.2.1 now numeric_std clean
-- 2011-07-30 400 1.2 digit dark in last quarter (not 16 clocks)
-- 2011-07-08 390 1.1.2 renamed from s3_dispdrv
-- 2010-04-17 278 1.1.1 renamed from dispdrv
-- 2010-03-29 272 1.1 add all ANO off time to allow to driver turn-off
-- delay and to avoid cross talk between digits
-- 2007-12-16 101 1.0.1 use _N for active low
-- 2007-09-16 83 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
entity sn_4x7segctl is -- Quad 7 segment display controller
generic (
CDWIDTH : positive := 6); -- clk divider width (must be >= 5)
port (
CLK : in slbit; -- clock
DIN : in slv16; -- data
DP : in slv4; -- decimal points
ANO_N : out slv4; -- anodes (act.low)
SEG_N : out slv8 -- segements (act.low)
);
end sn_4x7segctl;
architecture syn of sn_4x7segctl is
type regs_type is record
cdiv : slv(CDWIDTH-1 downto 0); -- clock divider counter
dcnt : slv2; -- digit counter
end record regs_type;
constant regs_init : regs_type := (
slv(to_unsigned(0,CDWIDTH)),
(others=>'0')
);
type hex2segtbl_type is array (0 to 15) of slv7;
constant hex2segtbl : hex2segtbl_type :=
("0111111", -- 0: "0000"
"0000110", -- 1: "0001"
"1011011", -- 2: "0010"
"1001111", -- 3: "0011"
"1100110", -- 4: "0100"
"1101101", -- 5: "0101"
"1111101", -- 6: "0110"
"0000111", -- 7: "0111"
"1111111", -- 8: "1000"
"1101111", -- 9: "1001"
"1110111", -- a: "1010"
"1111100", -- b: "1011"
"0111001", -- c: "1100"
"1011110", -- d: "1101"
"1111001", -- e: "1110"
"1110001" -- f: "1111"
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
assert CDWIDTH >= 5
report "assert(CDWIDTH >= 5): CDWIDTH too small"
severity FAILURE;
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
R_REGS <= N_REGS;
end if;
end process proc_regs;
proc_next: process (R_REGS, DIN, DP)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable cano : slv4 := "0000";
variable chex : slv4 := "0000";
variable cdp : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
n.cdiv := slv(unsigned(r.cdiv) - 1);
if unsigned(r.cdiv) = 0 then
n.dcnt := slv(unsigned(r.dcnt) + 1);
end if;
chex := "0000";
cdp := '0';
case r.dcnt is
when "00" => chex := DIN( 3 downto 0); cdp := DP(0);
when "01" => chex := DIN( 7 downto 4); cdp := DP(1);
when "10" => chex := DIN(11 downto 8); cdp := DP(2);
when "11" => chex := DIN(15 downto 12); cdp := DP(3);
when others => chex := "----"; cdp := '-';
end case;
-- the logic below ensures that the anode PNP driver transistor is switched
-- off in the last quarter of the digit cycle.This prevents 'cross talk'
-- between digits due to transistor turn off delays.
-- For a nexys2 board at 50 MHz observed:
-- no or 4 cycles gap well visible cross talk
-- with 8 cycles still some weak cross talk
-- with 16 cycles none is visible.
-- --> The turn-off delay of the anode driver PNP's this therefore
-- larger 160 ns and below 320 ns.
-- As consquence CDWIDTH should be at least 6 for 50 MHz and 7 for 100 MHz.
cano := "1111";
if r.cdiv(CDWIDTH-1 downto CDWIDTH-2) /= "00" then
cano(to_integer(unsigned(r.dcnt))) := '0';
end if;
N_REGS <= n;
ANO_N <= cano;
SEG_N <= not (cdp & hex2segtbl(to_integer(unsigned(chex))));
end process proc_next;
end syn;
| gpl-2.0 |
freecores/w11 | rtl/ibus/ibdr_dl11.vhd | 2 | 13865 | -- $Id: ibdr_dl11.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ibdr_dl11 - syn
-- Description: ibus dev(rem): DL11-A/B
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 10.1, 12.1, 13.1; ghdl 0.18-0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53d xc3s1000-4 39 126 0 72 s 7.6
-- 2009-07-12 233 10.1.03 K39 xc3s1000-4 38 119 0 69 s 6.3
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 23 61 0 40 s 5.5
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-07-12 233 1.0.5 add RESET, CE_USEC port; implement input rate limit
-- 2008-08-22 161 1.0.6 use iblib; add EI_ACK_* to proc_next sens. list
-- 2008-05-09 144 1.0.5 use intreq flop, use EI_ACK
-- 2008-03-22 128 1.0.4 rename xdone -> xval (no functional change)
-- 2008-01-27 115 1.0.3 bugfix: set ilam when rbuf read by cpu;
-- add xdone and rrdy bits to rri xbuf read
-- 2008-01-20 113 1.0.2 fix maint mode logic (proper double buffer now)
-- 2008-01-20 112 1.0.1 use BRESET
-- 2008-01-05 108 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibdr_dl11 is -- ibus dev(rem): DL11-A/B
generic (
IB_ADDR : slv16 := slv(to_unsigned(8#177560#,16)));
port (
CLK : in slbit; -- clock
CE_USEC : in slbit; -- usec pulse
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ_RX : out slbit; -- interrupt request, receiver
EI_REQ_TX : out slbit; -- interrupt request, transmitter
EI_ACK_RX : in slbit; -- interrupt acknowledge, receiver
EI_ACK_TX : in slbit -- interrupt acknowledge, transmitter
);
end ibdr_dl11;
architecture syn of ibdr_dl11 is
constant ibaddr_rcsr : slv2 := "00"; -- rcsr address offset
constant ibaddr_rbuf : slv2 := "01"; -- rbuf address offset
constant ibaddr_xcsr : slv2 := "10"; -- xcsr address offset
constant ibaddr_xbuf : slv2 := "11"; -- xbuf address offset
subtype rcsr_ibf_rrlim is integer range 14 downto 12;
constant rcsr_ibf_rdone : integer := 7;
constant rcsr_ibf_rie : integer := 6;
constant xcsr_ibf_xrdy : integer := 7;
constant xcsr_ibf_xie : integer := 6;
constant xcsr_ibf_xmaint: integer := 2;
constant xbuf_ibf_xval : integer := 8;
constant xbuf_ibf_rrdy : integer := 9;
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
rrlim : slv3; -- rcsr: receiver rate limit
rdone : slbit; -- rcsr: receiver done
rie : slbit; -- rcsr: receiver interrupt enable
rbuf : slv8; -- rbuf:
rval : slbit; -- rx rbuf valid
rintreq : slbit; -- rx interrupt request
rdlybsy : slbit; -- rx delay busy
rdlycnt : slv10; -- rx delay counter
xrdy : slbit; -- xcsr: transmitter ready
xie : slbit; -- xcsr: transmitter interrupt enable
xmaint : slbit; -- xcsr: maintenance mode
xbuf : slv8; -- xbuf:
xintreq : slbit; -- tx interrupt request
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
(others=>'0'), -- rrlim
'0','0', -- rdone, rie
(others=>'0'), -- rbuf
'0','0','0', -- rval,rintreq,rdlybsy
(others=>'0'), -- rdlycnt
'1', -- xrdy !! is set !!
'0','0', -- xie,xmaint
(others=>'0'), -- xbuf
'0' -- xintreq
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then
R_REGS <= regs_init;
if RESET = '0' then -- if RESET=0 we do just an ibus reset
R_REGS.rrlim <= N_REGS.rrlim; -- don't reset rx rate limit
R_REGS.rdlybsy <= N_REGS.rdlybsy; -- don't reset rx delay busy
R_REGS.rdlycnt <= N_REGS.rdlycnt; -- don't reset rx delay counter
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (CE_USEC, R_REGS, IB_MREQ, EI_ACK_RX, EI_ACK_TX)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable ilam : slbit := '0';
variable rdlystart : slbit := '0';
variable rdlyinit : slv10 := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ilam := '0';
rdlystart := '0';
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr(12 downto 3)=IB_ADDR(12 downto 3) then
n.ibsel := '1';
end if;
-- ibus transactions
if r.ibsel = '1' then
case IB_MREQ.addr(2 downto 1) is
when ibaddr_rcsr => -- RCSR -- receive control status ----
idout(rcsr_ibf_rdone) := r.rdone;
idout(rcsr_ibf_rie) := r.rie;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
n.rie := IB_MREQ.din(rcsr_ibf_rie);
if IB_MREQ.din(rcsr_ibf_rie) = '1' then
if r.rdone='1' and r.rie='0' then -- ie set while done=1
n.rintreq := '1'; -- request interrupt
end if;
else
n.rintreq := '0';
end if;
end if;
else -- rri ---------------------
idout(rcsr_ibf_rrlim) := r.rrlim;
if ibw1 = '1' then
n.rrlim := IB_MREQ.din(rcsr_ibf_rrlim);
end if;
end if;
when ibaddr_rbuf => -- RBUF -- receive data buffer -------
idout(r.rbuf'range) := r.rbuf;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibrd = '1' then
n.rdone := '0'; -- clear DONE
n.rval := '0'; -- clear rbuf valid
n.rintreq := '0'; -- clear pending interrupts
rdlystart := '1'; -- start rx delay counter
if r.xmaint = '0' then -- if not in loop-back
ilam := '1'; -- request rb attention
end if;
end if;
else -- rri ---------------------
if ibw0 = '1' then
n.rbuf := IB_MREQ.din(n.rbuf'range);
n.rval := '1'; -- set rbuf valid
if r.rdlybsy = '0' then -- if rdly timer not running
n.rdone := '1'; -- set DONE
if r.rie = '1' then -- if rx interrupt enabled
n.rintreq := '1'; -- request interrupt
end if;
end if;
end if;
end if;
when ibaddr_xcsr => -- XCSR -- transmit control status ---
idout(xcsr_ibf_xrdy) := r.xrdy;
idout(xcsr_ibf_xie) := r.xie;
idout(xcsr_ibf_xmaint):= r.xmaint;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
n.xie := IB_MREQ.din(xcsr_ibf_xie);
if IB_MREQ.din(xcsr_ibf_xie) = '1' then
if r.xrdy='1' and r.xie='0' then -- ie set while ready=1
n.xintreq := '1'; -- request interrupt
end if;
else
n.xintreq := '0';
end if;
n.xmaint := IB_MREQ.din(xcsr_ibf_xmaint);
end if;
end if;
when ibaddr_xbuf => -- XBUF -- transmit data buffer ------
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
n.xbuf := IB_MREQ.din(n.xbuf'range);
n.xrdy := '0';
n.xintreq := '0';
if r.xmaint = '0' then
ilam := '1';
end if;
end if;
else -- rri ---------------------
idout(r.xbuf'range) := r.xbuf;
if r.xmaint = '0' then -- if not in maintenace mode
idout(xbuf_ibf_xval) := not r.xrdy;
idout(xbuf_ibf_rrdy) := not r.rval;
end if;
if ibrd = '1' then
n.xrdy := '1';
if r.xie = '1' then
n.xintreq := '1';
end if;
end if;
end if;
when others => null;
end case;
else -- if unselected handle loop-back
if r.xmaint = '1' and -- if in maintenace mode
r.xrdy='0' and -- and transmit pending
r.rdone='0' and -- and receive buffer empty
r.rdlybsy='0' then -- and rdly timer not running
n.rbuf := r.xbuf; -- copy transmit to receive buffer
n.xrdy := '1'; -- mark transmit done
n.rdone := '1'; -- make receive done
if r.rie = '1' then -- if rx interrupt enabled
n.rintreq := '1'; -- request it
end if;
if r.xie = '1' then -- if tx interrupt enabled
n.xintreq := '1'; -- request it
end if;
end if;
end if;
-- other state changes
rdlyinit := (others=>'0');
case r.rrlim is
when "000" => rdlyinit := "0000000000"; -- rlim=0 -> disabled
when "001" => rdlyinit := "0000000011"; -- rlim=1 -> delay by 3+ usec
when "010" => rdlyinit := "0000001111"; -- rlim=2 -> delay by 15+ usec
when "011" => rdlyinit := "0000111111"; -- rlim=3 -> delay by 63+ usec
when "100" => rdlyinit := "0001111111"; -- rlim=4 -> delay by 127+ usec
when "101" => rdlyinit := "0011111111"; -- rlim=5 -> delay by 255+ usec
when "110" => rdlyinit := "0111111111"; -- rlim=6 -> delay by 511+ usec
when "111" => rdlyinit := "1111111111"; -- rlim=7 -> delay by 1023+ usec
when others => null;
end case;
if rdlystart = '1' then -- if rdly timer start requested
n.rdlycnt := rdlyinit; -- init counter
if r.rrlim /= "000" then -- rate limiter enabled ?
n.rdlybsy := '1'; -- set busy
end if;
elsif CE_USEC = '1' then -- if end-of-usec
n.rdlycnt := slv(unsigned(r.rdlycnt) - 1); -- decrement
if r.rdlybsy='1' and -- if delay busy
unsigned(r.rdlycnt) = 0 then -- and counter at zero
n.rdlybsy := '0'; -- clear busy
if n.rval = '1' then -- if rbuf is valid or is set
-- valid this cycle (use n.!!)
n.rdone := '1'; -- set DONE
if r.rie = '1' then -- if rx interrupt enabled
n.rintreq := '1'; -- request interrupt
end if;
end if;
end if;
end if;
if EI_ACK_RX = '1' then
n.rintreq := '0';
end if;
if EI_ACK_TX = '1' then
n.xintreq := '0';
end if;
N_REGS <= n;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= '0';
RB_LAM <= ilam;
EI_REQ_RX <= r.rintreq;
EI_REQ_TX <= r.xintreq;
end process proc_next;
end syn;
| gpl-2.0 |
freecores/w11 | rtl/w11a/pdp11_cache.vhd | 2 | 16370 | -- $Id: pdp11_cache.vhd 427 2011-11-19 21:04:11Z mueller $
--
-- Copyright 2008-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_cache - syn
-- Description: pdp11: cache
--
-- Dependencies: memlib/ram_2swsr_rfirst_gen
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-18 427 1.0.3 now numeric_std clean
-- 2008-02-23 118 1.0.2 ce cache in s_idle to avoid U's in sim
-- factor invariants out of if's; fix tag rmiss logic
-- 2008-02-17 117 1.0.1 use em_(mreq|sres) interface; use req,we for mem
-- recode, ghdl doesn't like partial vector port maps
-- 2008-02-16 116 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.pdp11.all;
entity pdp11_cache is -- cache
port (
CLK : in slbit; -- clock
GRESET : in slbit; -- global reset
EM_MREQ : in em_mreq_type; -- em request
EM_SRES : out em_sres_type; -- em response
FMISS : in slbit; -- force miss
CHIT : out slbit; -- cache hit flag
MEM_REQ : out slbit; -- memory: request
MEM_WE : out slbit; -- memory: write enable
MEM_BUSY : in slbit; -- memory: controller busy
MEM_ACK_R : in slbit; -- memory: acknowledge read
MEM_ADDR : out slv20; -- memory: address
MEM_BE : out slv4; -- memory: byte enable
MEM_DI : out slv32; -- memory: data in (memory view)
MEM_DO : in slv32 -- memory: data out (memory view)
);
end pdp11_cache;
architecture syn of pdp11_cache is
type state_type is (
s_idle, -- s_idle: wait for req
s_read, -- s_read: read cycle
s_rmiss, -- s_rmiss: read miss
s_write -- s_write: write cycle
);
type regs_type is record
state : state_type; -- state
addr_w : slbit; -- address - word select
addr_l : slv11; -- address - cache line address
addr_t : slv9; -- address - cache tag part
be : slv4; -- byte enables (at 4 byte level)
di : slv16; -- data
end record regs_type;
constant regs_init : regs_type := (
s_idle, -- state
'0', -- addr_w
(others=>'0'), -- addr_l
(others=>'0'), -- addr_t
(others=>'0'), -- be
(others=>'0') -- di
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
signal CMEM_TAG_CEA : slbit := '0';
signal CMEM_TAG_CEB : slbit := '0';
signal CMEM_TAG_WEA : slbit := '0';
signal CMEM_TAG_WEB : slbit := '0';
signal CMEM_TAG_DIB : slv9 := (others=>'0');
signal CMEM_TAG_DOA : slv9 := (others=>'0');
signal CMEM_DAT_CEA : slbit := '0';
signal CMEM_DAT_CEB : slbit := '0';
signal CMEM_DAT_WEA : slv4 := "0000";
signal CMEM_DAT_WEB : slv4 := "0000";
signal CMEM_DIA_0 : slv9 := (others=>'0');
signal CMEM_DIA_1 : slv9 := (others=>'0');
signal CMEM_DIA_2 : slv9 := (others=>'0');
signal CMEM_DIA_3 : slv9 := (others=>'0');
signal CMEM_DIB_0 : slv9 := (others=>'0');
signal CMEM_DIB_1 : slv9 := (others=>'0');
signal CMEM_DIB_2 : slv9 := (others=>'0');
signal CMEM_DIB_3 : slv9 := (others=>'0');
signal CMEM_DOA_0 : slv9 := (others=>'0');
signal CMEM_DOA_1 : slv9 := (others=>'0');
signal CMEM_DOA_2 : slv9 := (others=>'0');
signal CMEM_DOA_3 : slv9 := (others=>'0');
begin
CMEM_TAG : ram_2swsr_rfirst_gen
generic map (
AWIDTH => 11,
DWIDTH => 9)
port map (
CLKA => CLK,
CLKB => CLK,
ENA => CMEM_TAG_CEA,
ENB => CMEM_TAG_CEB,
WEA => CMEM_TAG_WEA,
WEB => CMEM_TAG_WEB,
ADDRA => EM_MREQ.addr(12 downto 2),
ADDRB => R_REGS.addr_l,
DIA => EM_MREQ.addr(21 downto 13),
DIB => CMEM_TAG_DIB,
DOA => CMEM_TAG_DOA,
DOB => open
);
CMEM_DAT0 : ram_2swsr_rfirst_gen
generic map (
AWIDTH => 11,
DWIDTH => 9)
port map (
CLKA => CLK,
CLKB => CLK,
ENA => CMEM_DAT_CEA,
ENB => CMEM_DAT_CEB,
WEA => CMEM_DAT_WEA(0),
WEB => CMEM_DAT_WEB(0),
ADDRA => EM_MREQ.addr(12 downto 2),
ADDRB => R_REGS.addr_l,
DIA => CMEM_DIA_0,
DIB => CMEM_DIB_0,
DOA => CMEM_DOA_0,
DOB => open
);
CMEM_DAT1 : ram_2swsr_rfirst_gen
generic map (
AWIDTH => 11,
DWIDTH => 9)
port map (
CLKA => CLK,
CLKB => CLK,
ENA => CMEM_DAT_CEA,
ENB => CMEM_DAT_CEB,
WEA => CMEM_DAT_WEA(1),
WEB => CMEM_DAT_WEB(1),
ADDRA => EM_MREQ.addr(12 downto 2),
ADDRB => R_REGS.addr_l,
DIA => CMEM_DIA_1,
DIB => CMEM_DIB_1,
DOA => CMEM_DOA_1,
DOB => open
);
CMEM_DAT2 : ram_2swsr_rfirst_gen
generic map (
AWIDTH => 11,
DWIDTH => 9)
port map (
CLKA => CLK,
CLKB => CLK,
ENA => CMEM_DAT_CEA,
ENB => CMEM_DAT_CEB,
WEA => CMEM_DAT_WEA(2),
WEB => CMEM_DAT_WEB(2),
ADDRA => EM_MREQ.addr(12 downto 2),
ADDRB => R_REGS.addr_l,
DIA => CMEM_DIA_2,
DIB => CMEM_DIB_2,
DOA => CMEM_DOA_2,
DOB => open
);
CMEM_DAT3 : ram_2swsr_rfirst_gen
generic map (
AWIDTH => 11,
DWIDTH => 9)
port map (
CLKA => CLK,
CLKB => CLK,
ENA => CMEM_DAT_CEA,
ENB => CMEM_DAT_CEB,
WEA => CMEM_DAT_WEA(3),
WEB => CMEM_DAT_WEB(3),
ADDRA => EM_MREQ.addr(12 downto 2),
ADDRB => R_REGS.addr_l,
DIA => CMEM_DIA_3,
DIB => CMEM_DIB_3,
DOA => CMEM_DOA_3,
DOB => open
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if GRESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, EM_MREQ, FMISS,
CMEM_TAG_DOA,
CMEM_DOA_0, CMEM_DOA_1, CMEM_DOA_2, CMEM_DOA_3,
MEM_BUSY, MEM_ACK_R, MEM_DO)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable iaddr_w : slbit := '0';
variable iaddr_l : slv11 := (others=>'0');
variable iaddr_t : slv9 := (others=>'0');
variable itagok : slbit := '0';
variable ivalok : slbit := '0';
variable icmem_tag_cea : slbit := '0';
variable icmem_tag_ceb : slbit := '0';
variable icmem_tag_wea : slbit := '0';
variable icmem_tag_web : slbit := '0';
variable icmem_tag_dib : slv9 := (others=>'0');
variable icmem_dat_cea : slbit := '0';
variable icmem_dat_ceb : slbit := '0';
variable icmem_dat_wea : slv4 := "0000";
variable icmem_dat_web : slv4 := "0000";
variable icmem_val_doa : slv4 := "0000";
variable icmem_dat_doa : slv32 := (others=>'0');
variable icmem_val_dib : slv4 := "0000";
variable icmem_dat_dib : slv32 := (others=>'0');
variable iackr : slbit := '0';
variable iackw : slbit := '0';
variable ichit : slbit := '0';
variable iosel : slv2 := "11";
variable imem_reqr : slbit := '0';
variable imem_reqw : slbit := '0';
variable imem_be : slv4 := "0000";
begin
r := R_REGS;
n := R_REGS;
iaddr_w := EM_MREQ.addr(1); -- get word select
iaddr_l := EM_MREQ.addr(12 downto 2); -- get cache line addr
iaddr_t := EM_MREQ.addr(21 downto 13); -- get cache tag part
icmem_tag_cea := '0';
icmem_tag_ceb := '0';
icmem_tag_wea := '0';
icmem_tag_web := '0';
icmem_tag_dib := r.addr_t; -- default, local define whenver used
icmem_dat_cea := '0';
icmem_dat_ceb := '0';
icmem_dat_wea := "0000";
icmem_dat_web := "0000";
icmem_val_dib := "0000";
icmem_dat_dib := MEM_DO; -- default, local define whenver used
icmem_val_doa(0) := CMEM_DOA_0(8);
icmem_dat_doa( 7 downto 0) := CMEM_DOA_0(7 downto 0);
icmem_val_doa(1) := CMEM_DOA_1(8);
icmem_dat_doa(15 downto 8) := CMEM_DOA_1(7 downto 0);
icmem_val_doa(2) := CMEM_DOA_2(8);
icmem_dat_doa(23 downto 16) := CMEM_DOA_2(7 downto 0);
icmem_val_doa(3) := CMEM_DOA_3(8);
icmem_dat_doa(31 downto 24) := CMEM_DOA_3(7 downto 0);
itagok := '0';
if CMEM_TAG_DOA = r.addr_t then -- cache tag hit
itagok := '1';
end if;
ivalok := '0';
if (icmem_val_doa and r.be) = r.be then
ivalok := '1';
end if;
iackr := '0';
iackw := '0';
ichit := '0';
iosel := "11"; -- default to ext. mem data
-- this prevents U's from cache bram's
-- to propagate to dout in beginning...
imem_reqr := '0';
imem_reqw := '0';
imem_be := r.be;
case r.state is
when s_idle => -- s_idle: wait for req
n.addr_w := iaddr_w; -- capture address: word select
n.addr_l := iaddr_l; -- capture address: cache line addr
n.addr_t := iaddr_t; -- capture address: cache tag part
n.be := "0000";
icmem_tag_cea := '1'; -- access cache tag port A
icmem_dat_cea := '1'; -- access cache data port A
if iaddr_w = '0' then -- capture byte enables at 4 byte lvl
n.be(1 downto 0) := EM_MREQ.be;
else
n.be(3 downto 2) := EM_MREQ.be;
end if;
n.di := EM_MREQ.din; -- capture data
if EM_MREQ.req = '1' then -- if access requested
if EM_MREQ.we = '0' then -- if READ requested
n.state := s_read; -- next: read
else -- if WRITE requested
icmem_tag_wea := '1'; -- write tag
icmem_dat_wea := n.be; -- write cache data
n.state := s_write; -- next: write
end if;
end if;
when s_read => -- s_read: read cycle
iosel := '0' & r.addr_w; -- output select: cache
imem_be := "1111"; -- mem read: all 4 bytes
if EM_MREQ.cancel = '0' then
if FMISS='0' and itagok='1' and ivalok='1' then -- read tag&val hit
iackr := '1'; -- signal read acknowledge
ichit := '1'; -- signal cache hit
n.state := s_idle; -- next: back to idle
else -- read miss
if MEM_BUSY = '0' then -- if mem not busy
imem_reqr :='1'; -- request mem read
n.state := s_rmiss; -- next: rmiss, wait for mem data
end if;
end if;
else
n.state := s_idle; -- next: back to idle
end if;
when s_rmiss => -- s_rmiss: read cycle
iosel := '1' & r.addr_w; -- output select: memory
icmem_tag_web := '1'; -- cache update: write tag
icmem_tag_dib := r.addr_t; -- cache update: new tag
icmem_val_dib := "1111"; -- cache update: all valid
icmem_dat_dib := MEM_DO; -- cache update: data from mem
icmem_dat_web := "1111"; -- cache update: write all 4 bytes
if MEM_ACK_R = '1' then -- mem data valid
iackr := '1'; -- signal read acknowledge
icmem_tag_ceb := '1'; -- access cache tag port B
icmem_dat_ceb := '1'; -- access cache data port B
n.state := s_idle; -- next: back to idle
end if;
when s_write => -- s_write: write cycle
icmem_tag_dib := CMEM_TAG_DOA; -- cache restore: last state
icmem_dat_dib := icmem_dat_doa; -- cache restore: last state
if EM_MREQ.cancel = '0' then -- request ok
if MEM_BUSY = '0' then -- if mem not busy
if itagok = '0' then -- if write tag miss
icmem_dat_ceb := '1'; -- access cache (invalidate)
icmem_dat_web := not r.be; -- write missed bytes
icmem_val_dib := "0000"; -- invalidate missed bytes
end if;
imem_reqw := '1'; -- write back to main memory
iackw := '1'; -- and done
n.state := s_idle; -- next: back to idle
end if;
else -- request canceled -> restore
icmem_tag_ceb := '1'; -- access cache line
icmem_tag_web := '1'; -- write tag
icmem_dat_ceb := '1'; -- access cache line
icmem_dat_web := "1111"; -- restore cache line
icmem_val_dib := icmem_val_doa; -- cache restore: last state
n.state := s_idle; -- next: back to idle
end if;
when others => null;
end case;
N_REGS <= n;
CMEM_TAG_CEA <= icmem_tag_cea;
CMEM_TAG_CEB <= icmem_tag_ceb;
CMEM_TAG_WEA <= icmem_tag_wea;
CMEM_TAG_WEB <= icmem_tag_web;
CMEM_TAG_DIB <= icmem_tag_dib;
CMEM_DAT_CEA <= icmem_dat_cea;
CMEM_DAT_CEB <= icmem_dat_ceb;
CMEM_DAT_WEA <= icmem_dat_wea;
CMEM_DAT_WEB <= icmem_dat_web;
CMEM_DIA_0(8) <= '1';
CMEM_DIA_0(7 downto 0) <= EM_MREQ.din( 7 downto 0);
CMEM_DIA_1(8) <= '1';
CMEM_DIA_1(7 downto 0) <= EM_MREQ.din(15 downto 8);
CMEM_DIA_2(8) <= '1';
CMEM_DIA_2(7 downto 0) <= EM_MREQ.din( 7 downto 0);
CMEM_DIA_3(8) <= '1';
CMEM_DIA_3(7 downto 0) <= EM_MREQ.din(15 downto 8);
CMEM_DIB_0(8) <= icmem_val_dib(0);
CMEM_DIB_0(7 downto 0) <= icmem_dat_dib(7 downto 0);
CMEM_DIB_1(8) <= icmem_val_dib(1);
CMEM_DIB_1(7 downto 0) <= icmem_dat_dib(15 downto 8);
CMEM_DIB_2(8) <= icmem_val_dib(2);
CMEM_DIB_2(7 downto 0) <= icmem_dat_dib(23 downto 16);
CMEM_DIB_3(8) <= icmem_val_dib(3);
CMEM_DIB_3(7 downto 0) <= icmem_dat_dib(31 downto 24);
EM_SRES <= em_sres_init;
EM_SRES.ack_r <= iackr;
EM_SRES.ack_w <= iackw;
case iosel is
when "00" => EM_SRES.dout <= icmem_dat_doa(15 downto 0);
when "01" => EM_SRES.dout <= icmem_dat_doa(31 downto 16);
when "10" => EM_SRES.dout <= MEM_DO(15 downto 0);
when "11" => EM_SRES.dout <= MEM_DO(31 downto 16);
when others => null;
end case;
CHIT <= ichit;
MEM_REQ <= imem_reqr or imem_reqw;
MEM_WE <= imem_reqw;
MEM_ADDR <= r.addr_t & r.addr_l;
MEM_BE <= imem_be;
MEM_DI <= r.di & r.di;
end process proc_next;
end syn;
| gpl-2.0 |
freecores/w11 | rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb/tb_tst_rlink_cuff_ic_n3.vhd | 1 | 1527 | -- $Id: tb_tst_rlink_cuff_ic_n3.vhd 512 2013-04-28 07:44:02Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_rlink_cuff_ic_n3
-- Description: Configuration for tb_tst_rlink_cuff_ic_n3 for
-- tb_nexys3_fusp_cuff
--
-- Dependencies: sys_tst_rlink_cuff_n3 (fx2_type = 'ic2')
--
-- To test: sys_tst_rlink_cuff_n3 (fx2_type = 'ic2')
--
-- Verified:
-- Date Rev Code ghdl ise Target Comment
-- 2013-01-xx xxx - 0.29 13.3 O76d xc6slx16-2 u:???
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-04-27 512 1.0 Initial version
------------------------------------------------------------------------------
configuration tb_tst_rlink_cuff_ic_n3 of tb_nexys3_fusp_cuff is
for sim
for all : nexys3_fusp_cuff_aif
use entity work.sys_tst_rlink_cuff_n3;
end for;
end for;
end tb_tst_rlink_cuff_ic_n3;
| gpl-2.0 |
freecores/w11 | rtl/ibus/ib_sres_or_2.vhd | 2 | 2410 | -- $Id: ib_sres_or_2.vhd 335 2010-10-24 22:24:23Z mueller $
--
-- Copyright 2007-2010 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ib_sres_or_2 - syn
-- Description: ibus: result or, 2 input
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2010-10-23 335 1.1 add ib_sres_or_mon
-- 2008-08-22 161 1.0.2 renamed pdp11_ibres_ -> ib_sres_; use iblib
-- 2008-01-05 110 1.0.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2007-12-29 107 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ib_sres_or_2 is -- ibus result or, 2 input
port (
IB_SRES_1 : in ib_sres_type; -- ib_sres input 1
IB_SRES_2 : in ib_sres_type := ib_sres_init; -- ib_sres input 2
IB_SRES_OR : out ib_sres_type -- ib_sres or'ed output
);
end ib_sres_or_2;
architecture syn of ib_sres_or_2 is
begin
proc_comb : process (IB_SRES_1, IB_SRES_2)
begin
IB_SRES_OR.ack <= IB_SRES_1.ack or
IB_SRES_2.ack;
IB_SRES_OR.busy <= IB_SRES_1.busy or
IB_SRES_2.busy;
IB_SRES_OR.dout <= IB_SRES_1.dout or
IB_SRES_2.dout;
end process proc_comb;
-- synthesis translate_off
ORMON : ib_sres_or_mon
port map (
IB_SRES_1 => IB_SRES_1,
IB_SRES_2 => IB_SRES_2,
IB_SRES_3 => ib_sres_init,
IB_SRES_4 => ib_sres_init
);
-- synthesis translate_on
end syn;
| gpl-2.0 |
freecores/w11 | rtl/vlib/serport/serport_xonrx.vhd | 1 | 4232 | -- $Id: serport_xonrx.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: serport_xonrx - syn
-- Description: serial port: xon/xoff logic rx path
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-10-22 417 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
entity serport_xonrx is -- serial port: xon/xoff logic rx path
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
UART_RXDATA : in slv8; -- uart data out
UART_RXVAL : in slbit; -- uart data valid
RXDATA : out slv8; -- user data out
RXVAL : out slbit; -- user data valid
RXHOLD : in slbit; -- user data hold
RXOVR : out slbit; -- user data overrun
TXOK : out slbit -- tx channel ok
);
end serport_xonrx;
architecture syn of serport_xonrx is
type regs_type is record
txok : slbit; -- tx channel ok state
escseen : slbit; -- escape seen
rxdata : slv8; -- user rxdata
rxval : slbit; -- user rxval
rxovr : slbit; -- user rxovr
end record regs_type;
constant regs_init : regs_type := (
'1', -- txok (startup default is ok !!)
'0', -- escseen
(others=>'0'), -- rxdata
'0','0' -- rxval,rxovr
);
signal R_REGS : regs_type := regs_init; -- state registers
signal N_REGS : regs_type := regs_init; -- next value state regs
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, ENAXON, ENAESC, UART_RXDATA, UART_RXVAL, RXHOLD)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
begin
r := R_REGS;
n := R_REGS;
if ENAXON = '0' then
n.txok := '1';
end if;
if ENAESC = '0' then
n.escseen := '0';
end if;
n.rxovr := '0'; -- ensure single clock pulse
if UART_RXVAL = '1' then
if ENAXON='1' and UART_RXDATA=c_serport_xon then
n.txok := '1';
elsif ENAXON='1' and UART_RXDATA=c_serport_xoff then
n.txok := '0';
elsif ENAESC='1' and UART_RXDATA=c_serport_xesc then
n.escseen := '1';
else
if r.escseen = '1' then
n.escseen := '0';
end if;
if r.rxval = '0' then
n.rxval := '1';
if r.escseen = '1' then
n.rxdata := not UART_RXDATA;
else
n.rxdata := UART_RXDATA;
end if;
else
n.rxovr := '1';
end if;
end if;
end if;
if r.rxval='1' and RXHOLD='0' then
n.rxval := '0';
end if;
N_REGS <= n;
RXDATA <= r.rxdata;
RXVAL <= r.rxval;
RXOVR <= r.rxovr;
TXOK <= r.txok;
end process proc_next;
end syn;
| gpl-2.0 |
freecores/w11 | rtl/vlib/simlib/simbus.vhd | 1 | 1960 | -- $Id: simbus.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: simbus
-- Description: Global signals for support control in test benches
--
-- Dependencies: -
-- Tool versions: xst 8.2, 9.1, 9.2, 11.4, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 2.0 remove global clock cycle signal
-- 2010-04-24 282 1.1 add SB_(VAL|ADDR|DATA)
-- 2008-03-24 129 1.0.1 use 31 bits for SB_CLKCYCLE
-- 2007-08-27 76 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package simbus is
signal SB_CLKSTOP : slbit := '0'; -- global clock stop
signal SB_CNTL : slv16 := (others=>'0'); -- global signals tb -> uut
signal SB_STAT : slv16 := (others=>'0'); -- global signals uut -> tb
signal SB_VAL : slbit := '0'; -- init bcast valid
signal SB_ADDR : slv8 := (others=>'0'); -- init bcast address
signal SB_DATA : slv16 := (others=>'0'); -- init bcast data
-- Note: SB_CNTL, SB_VAL, SB_ADDR, SB_DATA can have weak ('L','H') and
-- strong ('0','1') drivers. Therefore always remove strenght before
-- using, e.g. with to_x01()
end package simbus;
| gpl-2.0 |
freecores/w11 | rtl/sys_gen/tst_serloop/nexys2/tb/tb_tst_serloop1_n2.vhd | 1 | 3995 | -- $Id: tb_tst_serloop1_n2.vhd 444 2011-12-25 10:04:58Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop1_n2 - sim
-- Description: Test bench for sys_tst_serloop1_n2
--
-- Dependencies: simlib/simclk
-- sys_tst_serloop2_n2 [UUT]
-- tb/tb_tst_serloop
--
-- To test: sys_tst_serloop1_n2
--
-- Target Devices: generic
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 use new simclk; remove clksys output hack
-- 2011-12-16 439 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.xlib.all;
use work.simlib.all;
entity tb_tst_serloop1_n2 is
end tb_tst_serloop1_n2;
architecture sim of tb_tst_serloop1_n2 is
signal CLK50 : slbit := '0';
signal CLK_STOP : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal I_SWI : slv8 := (others=>'0');
signal I_BTN : slv4 := (others=>'0');
signal O_FUSP_RTS_N : slbit := '0';
signal I_FUSP_CTS_N : slbit := '0';
signal I_FUSP_RXD : slbit := '1';
signal O_FUSP_TXD : slbit := '1';
signal RXD : slbit := '1';
signal TXD : slbit := '1';
signal SWI : slv8 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal FUSP_RTS_N : slbit := '0';
signal FUSP_CTS_N : slbit := '0';
signal FUSP_RXD : slbit := '1';
signal FUSP_TXD : slbit := '1';
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant delay_time : time := 2 ns;
begin
SYSCLK : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK50,
CLK_STOP => CLK_STOP
);
UUT : entity work.sys_tst_serloop1_n2
port map (
I_CLK50 => CLK50,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => open,
O_ANO_N => open,
O_SEG_N => open,
O_MEM_CE_N => open,
O_MEM_BE_N => open,
O_MEM_WE_N => open,
O_MEM_OE_N => open,
O_MEM_ADV_N => open,
O_MEM_CLK => open,
O_MEM_CRE => open,
I_MEM_WAIT => '0',
O_MEM_ADDR => open,
IO_MEM_DATA => open,
O_FLA_CE_N => open,
O_FUSP_RTS_N => O_FUSP_RTS_N,
I_FUSP_CTS_N => I_FUSP_CTS_N,
I_FUSP_RXD => I_FUSP_RXD,
O_FUSP_TXD => O_FUSP_TXD
);
GENTB : entity work.tb_tst_serloop
port map (
CLKS => CLK50,
CLKH => CLK50,
CLK_STOP => CLK_STOP,
P0_RXD => RXD,
P0_TXD => TXD,
P0_RTS_N => '0',
P0_CTS_N => open,
P1_RXD => FUSP_RXD,
P1_TXD => FUSP_TXD,
P1_RTS_N => FUSP_RTS_N,
P1_CTS_N => FUSP_CTS_N,
SWI => SWI,
BTN => BTN
);
I_RXD <= RXD after delay_time;
TXD <= O_TXD after delay_time;
FUSP_RTS_N <= O_FUSP_RTS_N after delay_time;
I_FUSP_CTS_N <= FUSP_CTS_N after delay_time;
I_FUSP_RXD <= FUSP_RXD after delay_time;
FUSP_TXD <= O_FUSP_TXD after delay_time;
I_SWI <= SWI after delay_time;
I_BTN <= BTN after delay_time;
end sim;
| gpl-2.0 |
rodrigosurita/new-crpuf | vhdl/src/std_logic_arith.vhd | 1 | 70493 | --------------------------------------------------------------------------
-- --
-- Copyright (c) 1990,1991,1992 by Synopsys, Inc. All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_ARITH --
-- --
-- Purpose: --
-- A set of arithemtic, conversion, and comparison functions --
-- for SIGNED, UNSIGNED, SMALL_INT, INTEGER, --
-- STD_ULOGIC, STD_LOGIC, and STD_LOGIC_VECTOR. --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package std_logic_arith is
type UNSIGNED is array (NATURAL range <>) of STD_LOGIC;
type SIGNED is array (NATURAL range <>) of STD_LOGIC;
subtype SMALL_INT is INTEGER range 0 to 1;
function "+"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "+"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: INTEGER) return UNSIGNED;
function "+"(L: INTEGER; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: INTEGER) return SIGNED;
function "+"(L: INTEGER; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED; R: STD_ULOGIC) return SIGNED;
function "+"(L: STD_ULOGIC; R: SIGNED) return SIGNED;
function "+"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "-"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: INTEGER) return UNSIGNED;
function "-"(L: INTEGER; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: INTEGER) return SIGNED;
function "-"(L: INTEGER; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED;
function "-"(L: SIGNED; R: STD_ULOGIC) return SIGNED;
function "-"(L: STD_ULOGIC; R: SIGNED) return SIGNED;
function "-"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR;
function "+"(L: UNSIGNED) return UNSIGNED;
function "+"(L: SIGNED) return SIGNED;
function "-"(L: SIGNED) return SIGNED;
function "ABS"(L: SIGNED) return SIGNED;
function "+"(L: UNSIGNED) return STD_LOGIC_VECTOR;
function "+"(L: SIGNED) return STD_LOGIC_VECTOR;
function "-"(L: SIGNED) return STD_LOGIC_VECTOR;
function "ABS"(L: SIGNED) return STD_LOGIC_VECTOR;
function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED;
function "*"(L: SIGNED; R: SIGNED) return SIGNED;
function "*"(L: SIGNED; R: UNSIGNED) return SIGNED;
function "*"(L: UNSIGNED; R: SIGNED) return SIGNED;
function "*"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "*"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "*"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR;
function "*"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR;
function "<"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: SIGNED) return BOOLEAN;
function "<"(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "<"(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "<"(L: SIGNED; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: SIGNED) return BOOLEAN;
function "<="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "<="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "<="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "<="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: SIGNED) return BOOLEAN;
function ">"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: SIGNED) return BOOLEAN;
function ">"(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function ">"(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function ">"(L: SIGNED; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: SIGNED) return BOOLEAN;
function ">="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: SIGNED) return BOOLEAN;
function ">="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function ">="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function ">="(L: SIGNED; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: SIGNED) return BOOLEAN;
function "="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: SIGNED) return BOOLEAN;
function "/="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: SIGNED) return BOOLEAN;
function "/="(L: UNSIGNED; R: SIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: UNSIGNED) return BOOLEAN;
function "/="(L: UNSIGNED; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: UNSIGNED) return BOOLEAN;
function "/="(L: SIGNED; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: SIGNED) return BOOLEAN;
function SHL(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED;
function SHL(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED;
function SHR(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED;
function SHR(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED;
function CONV_INTEGER(ARG: INTEGER) return INTEGER;
function CONV_INTEGER(ARG: UNSIGNED) return INTEGER;
function CONV_INTEGER(ARG: SIGNED) return INTEGER;
function CONV_INTEGER(ARG: STD_ULOGIC) return SMALL_INT;
function CONV_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: UNSIGNED; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: SIGNED; SIZE: INTEGER) return UNSIGNED;
function CONV_UNSIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return UNSIGNED;
function CONV_SIGNED(ARG: INTEGER; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: UNSIGNED; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: SIGNED; SIZE: INTEGER) return SIGNED;
function CONV_SIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return SIGNED;
function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: UNSIGNED; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: SIGNED; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
function CONV_STD_LOGIC_VECTOR(ARG: STD_ULOGIC; SIZE: INTEGER)
return STD_LOGIC_VECTOR;
-- zero extend STD_LOGIC_VECTOR (ARG) to SIZE,
-- SIZE < 0 is same as SIZE = 0
-- returns STD_LOGIC_VECTOR(SIZE-1 downto 0)
function EXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR;
-- sign extend STD_LOGIC_VECTOR (ARG) to SIZE,
-- SIZE < 0 is same as SIZE = 0
-- return STD_LOGIC_VECTOR(SIZE-1 downto 0)
function SXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end Std_logic_arith;
library IEEE;
use IEEE.std_logic_1164.all;
package body std_logic_arith is
function max(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
-- synopsys synthesis_off
type tbl_type is array (STD_ULOGIC) of STD_ULOGIC;
constant tbl_BINARY : tbl_type :=
('X', 'X', '0', '1', 'X', 'X', '0', '1', 'X');
-- synopsys synthesis_on
-- synopsys synthesis_off
type tbl_mvl9_boolean is array (STD_ULOGIC) of boolean;
constant IS_X : tbl_mvl9_boolean :=
(true, true, false, false, true, true, false, false, true);
-- synopsys synthesis_on
function MAKE_BINARY(A : STD_ULOGIC) return STD_ULOGIC is
-- synopsys built_in SYN_FEED_THRU
begin
-- synopsys synthesis_off
if (IS_X(A)) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
return ('X');
end if;
return tbl_BINARY(A);
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return UNSIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : UNSIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return SIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : SIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return UNSIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : UNSIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return SIGNED is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : SIGNED (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : UNSIGNED) return STD_LOGIC_VECTOR is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
function MAKE_BINARY(A : SIGNED) return STD_LOGIC_VECTOR is
-- synopsys built_in SYN_FEED_THRU
variable one_bit : STD_ULOGIC;
variable result : STD_LOGIC_VECTOR (A'range);
begin
-- synopsys synthesis_off
for i in A'range loop
if (IS_X(A(i))) then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
result := (others => 'X');
return result;
end if;
result(i) := tbl_BINARY(A(i));
end loop;
return result;
-- synopsys synthesis_on
end;
-- Type propagation function which returns a signed type with the
-- size of the left arg.
function LEFT_SIGNED_ARG(A,B: SIGNED) return SIGNED is
variable Z: SIGNED (A'left downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns an unsigned type with the
-- size of the left arg.
function LEFT_UNSIGNED_ARG(A,B: UNSIGNED) return UNSIGNED is
variable Z: UNSIGNED (A'left downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns a signed type with the
-- size of the result of a signed multiplication
function MULT_SIGNED_ARG(A,B: SIGNED) return SIGNED is
variable Z: SIGNED ((A'length+B'length-1) downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns an unsigned type with the
-- size of the result of a unsigned multiplication
function MULT_UNSIGNED_ARG(A,B: UNSIGNED) return UNSIGNED is
variable Z: UNSIGNED ((A'length+B'length-1) downto 0);
-- pragma return_port_name Z
begin
return(Z);
end;
function mult(A,B: SIGNED) return SIGNED is
variable BA: SIGNED((A'length+B'length-1) downto 0);
variable PA: SIGNED((A'length+B'length-1) downto 0);
variable AA: SIGNED(A'length downto 0);
variable neg: STD_ULOGIC;
constant one : UNSIGNED(1 downto 0) := "01";
-- pragma map_to_operator MULT_TC_OP
-- pragma type_function MULT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
PA := (others => 'X');
return(PA);
end if;
PA := (others => '0');
neg := B(B'left) xor A(A'left);
BA := CONV_SIGNED(('0' & ABS(B)),(A'length+B'length));
AA := '0' & ABS(A);
for i in 0 to A'length-1 loop
if AA(i) = '1' then
PA := PA+BA;
end if;
BA := SHL(BA,one);
end loop;
if (neg= '1') then
return(-PA);
else
return(PA);
end if;
end;
function mult(A,B: UNSIGNED) return UNSIGNED is
variable BA: UNSIGNED((A'length+B'length-1) downto 0);
variable PA: UNSIGNED((A'length+B'length-1) downto 0);
constant one : UNSIGNED(1 downto 0) := "01";
-- pragma map_to_operator MULT_UNS_OP
-- pragma type_function MULT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
PA := (others => 'X');
return(PA);
end if;
PA := (others => '0');
BA := CONV_UNSIGNED(B,(A'length+B'length));
for i in 0 to A'length-1 loop
if A(i) = '1' then
PA := PA+BA;
end if;
BA := SHL(BA,one);
end loop;
return(PA);
end;
-- subtract two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function minus(A, B: SIGNED) return SIGNED is
variable carry: STD_ULOGIC;
variable BV: STD_ULOGIC_VECTOR (A'left downto 0);
variable sum: SIGNED (A'left downto 0);
-- pragma map_to_operator SUB_TC_OP
-- pragma type_function LEFT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '1';
BV := not STD_ULOGIC_VECTOR(B);
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- add two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function plus(A, B: SIGNED) return SIGNED is
variable carry: STD_ULOGIC;
variable BV, sum: SIGNED (A'left downto 0);
-- pragma map_to_operator ADD_TC_OP
-- pragma type_function LEFT_SIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '0';
BV := B;
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- subtract two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_minus(A, B: UNSIGNED) return UNSIGNED is
variable carry: STD_ULOGIC;
variable BV: STD_ULOGIC_VECTOR (A'left downto 0);
variable sum: UNSIGNED (A'left downto 0);
-- pragma map_to_operator SUB_UNS_OP
-- pragma type_function LEFT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '1';
BV := not STD_ULOGIC_VECTOR(B);
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
-- add two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_plus(A, B: UNSIGNED) return UNSIGNED is
variable carry: STD_ULOGIC;
variable BV, sum: UNSIGNED (A'left downto 0);
-- pragma map_to_operator ADD_UNS_OP
-- pragma type_function LEFT_UNSIGNED_ARG
-- pragma return_port_name Z
begin
if (A(A'left) = 'X' or B(B'left) = 'X') then
sum := (others => 'X');
return(sum);
end if;
carry := '0';
BV := B;
for i in 0 to A'left loop
sum(i) := A(i) xor BV(i) xor carry;
carry := (A(i) and BV(i)) or
(A(i) and carry) or
(carry and BV(i));
end loop;
return sum;
end;
function "*"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 296
begin
return mult(CONV_SIGNED(L, L'length),
CONV_SIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 295
begin
return mult(CONV_UNSIGNED(L, L'length),
CONV_UNSIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 297
begin
return mult(CONV_SIGNED(L, L'length+1),
CONV_SIGNED(R, R'length)); -- pragma label mult
end;
function "*"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to mult
-- synopsys subpgm_id 298
begin
return mult(CONV_SIGNED(L, L'length),
CONV_SIGNED(R, R'length+1)); -- pragma label mult
end;
function "*"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 301
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_SIGNED(L, L'length), CONV_SIGNED(R, R'length)));
end;
function "*"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 300
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_UNSIGNED(L, L'length), CONV_UNSIGNED(R, R'length)));
end;
function "*"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 302
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_SIGNED(L, L'length+1), CONV_SIGNED(R, R'length)));
end;
function "*"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
-- synopsys subpgm_id 303
begin
return STD_LOGIC_VECTOR (
mult(-- pragma label mult
CONV_SIGNED(L, L'length), CONV_SIGNED(R, R'length+1)));
end;
function "+"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 236
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 237
constant length: INTEGER := max(L'length, R'length);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 238
constant length: INTEGER := max(L'length + 1, R'length);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 239
constant length: INTEGER := max(L'length, R'length + 1);
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: INTEGER) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 240
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "+"(L: INTEGER; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 241
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "+"(L: SIGNED; R: INTEGER) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 242
constant length: INTEGER := L'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: INTEGER; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 243
constant length: INTEGER := R'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 244
constant length: INTEGER := L'length;
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)) ; -- pragma label plus
end;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 245
constant length: INTEGER := R'length;
begin
return unsigned_plus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label plus
end;
function "+"(L: SIGNED; R: STD_ULOGIC) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 246
constant length: INTEGER := L'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: STD_ULOGIC; R: SIGNED) return SIGNED is
-- pragma label_applies_to plus
-- synopsys subpgm_id 247
constant length: INTEGER := R'length;
begin
return plus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label plus
end;
function "+"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 260
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
unsigned_plus(-- pragma label plus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length)));
end;
function "+"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 261
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 262
constant length: INTEGER := max(L'length + 1, R'length);
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 263
constant length: INTEGER := max(L'length, R'length + 1);
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 264
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "+"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 265
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
plus( -- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "+"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 266
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 267
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 268
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
unsigned_plus(-- pragma label plus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length))) ;
end;
function "+"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 269
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
unsigned_plus(-- pragma label plus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length)));
end;
function "+"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 270
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
-- synopsys subpgm_id 271
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
plus(-- pragma label plus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 248
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_minus(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label minus
end;
function "-"(L: SIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 249
constant length: INTEGER := max(L'length, R'length);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 250
constant length: INTEGER := max(L'length + 1, R'length);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: SIGNED; R: UNSIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 251
constant length: INTEGER := max(L'length, R'length + 1);
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: INTEGER) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 252
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: INTEGER; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 253
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: SIGNED; R: INTEGER) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 254
constant length: INTEGER := L'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: INTEGER; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 255
constant length: INTEGER := R'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 256
constant length: INTEGER := L'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return UNSIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 257
constant length: INTEGER := R'length + 1;
begin
return CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1);
end;
function "-"(L: SIGNED; R: STD_ULOGIC) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 258
constant length: INTEGER := L'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: STD_ULOGIC; R: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 259
constant length: INTEGER := R'length;
begin
return minus(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label minus
end;
function "-"(L: UNSIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 272
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
unsigned_minus(-- pragma label minus
CONV_UNSIGNED(L, length), CONV_UNSIGNED(R, length)));
end;
function "-"(L: SIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 273
constant length: INTEGER := max(L'length, R'length);
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 274
constant length: INTEGER := max(L'length + 1, R'length);
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: SIGNED; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 275
constant length: INTEGER := max(L'length, R'length + 1);
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 276
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: INTEGER; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 277
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: SIGNED; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 278
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: INTEGER; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 279
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: UNSIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 280
constant length: INTEGER := L'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: STD_ULOGIC; R: UNSIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 281
constant length: INTEGER := R'length + 1;
begin
return STD_LOGIC_VECTOR (CONV_UNSIGNED(
minus( -- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)), length-1));
end;
function "-"(L: SIGNED; R: STD_ULOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 282
constant length: INTEGER := L'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "-"(L: STD_ULOGIC; R: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 283
constant length: INTEGER := R'length;
begin
return STD_LOGIC_VECTOR (
minus(-- pragma label minus
CONV_SIGNED(L, length), CONV_SIGNED(R, length)));
end;
function "+"(L: UNSIGNED) return UNSIGNED is
-- synopsys subpgm_id 284
begin
return L;
end;
function "+"(L: SIGNED) return SIGNED is
-- synopsys subpgm_id 285
begin
return L;
end;
function "-"(L: SIGNED) return SIGNED is
-- pragma label_applies_to minus
-- synopsys subpgm_id 286
begin
return 0 - L; -- pragma label minus
end;
function "ABS"(L: SIGNED) return SIGNED is
-- synopsys subpgm_id 287
begin
if (L(L'left) = '0' or L(L'left) = 'L') then
return L;
else
return 0 - L;
end if;
end;
function "+"(L: UNSIGNED) return STD_LOGIC_VECTOR is
-- synopsys subpgm_id 289
begin
return STD_LOGIC_VECTOR (L);
end;
function "+"(L: SIGNED) return STD_LOGIC_VECTOR is
-- synopsys subpgm_id 290
begin
return STD_LOGIC_VECTOR (L);
end;
function "-"(L: SIGNED) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
-- synopsys subpgm_id 292
variable tmp: SIGNED(L'length-1 downto 0);
begin
tmp := 0 - L; -- pragma label minus
return STD_LOGIC_VECTOR (tmp);
end;
function "ABS"(L: SIGNED) return STD_LOGIC_VECTOR is
-- synopsys subpgm_id 294
variable tmp: SIGNED(L'length-1 downto 0);
begin
if (L(L'left) = '0' or L(L'left) = 'L') then
return STD_LOGIC_VECTOR (L);
else
tmp := 0 - L;
return STD_LOGIC_VECTOR (tmp);
end if;
end;
-- Type propagation function which returns the type BOOLEAN
function UNSIGNED_RETURN_BOOLEAN(A,B: UNSIGNED) return BOOLEAN is
variable Z: BOOLEAN;
-- pragma return_port_name Z
begin
return(Z);
end;
-- Type propagation function which returns the type BOOLEAN
function SIGNED_RETURN_BOOLEAN(A,B: SIGNED) return BOOLEAN is
variable Z: BOOLEAN;
-- pragma return_port_name Z
begin
return(Z);
end;
-- compare two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function is_less(A, B: SIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LT_TC_OP
-- pragma type_function SIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
if A(sign) /= B(sign) then
result := A(sign) = '1';
else
result := FALSE;
for i in 0 to sign-1 loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
end if;
return result;
end;
-- compare two signed numbers of the same length
-- both arrays must have range (msb downto 0)
function is_less_or_equal(A, B: SIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LEQ_TC_OP
-- pragma type_function SIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
if A(sign) /= B(sign) then
result := A(sign) = '1';
else
result := TRUE;
for i in 0 to sign-1 loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
end if;
return result;
end;
-- compare two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_is_less(A, B: UNSIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LT_UNS_OP
-- pragma type_function UNSIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
result := FALSE;
for i in 0 to sign loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
return result;
end;
-- compare two unsigned numbers of the same length
-- both arrays must have range (msb downto 0)
function unsigned_is_less_or_equal(A, B: UNSIGNED) return BOOLEAN is
constant sign: INTEGER := A'left;
variable a_is_0, b_is_1, result : boolean;
-- pragma map_to_operator LEQ_UNS_OP
-- pragma type_function UNSIGNED_RETURN_BOOLEAN
-- pragma return_port_name Z
begin
result := TRUE;
for i in 0 to sign loop
a_is_0 := A(i) = '0';
b_is_1 := B(i) = '1';
result := (a_is_0 and b_is_1) or
(a_is_0 and result) or
(b_is_1 and result);
end loop;
return result;
end;
function "<"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 305
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 306
constant length: INTEGER := max(L'length, R'length);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 307
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 308
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 309
constant length: INTEGER := L'length + 1;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 310
constant length: INTEGER := R'length + 1;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 311
constant length: INTEGER := L'length;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<"(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to lt
-- synopsys subpgm_id 312
constant length: INTEGER := R'length;
begin
return is_less(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label lt
end;
function "<="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 314
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less_or_equal(CONV_UNSIGNED(L, length),
CONV_UNSIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 315
constant length: INTEGER := max(L'length, R'length);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 316
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 317
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 318
constant length: INTEGER := L'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 319
constant length: INTEGER := R'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 320
constant length: INTEGER := L'length;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function "<="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to leq
-- synopsys subpgm_id 321
constant length: INTEGER := R'length;
begin
return is_less_or_equal(CONV_SIGNED(L, length),
CONV_SIGNED(R, length)); -- pragma label leq
end;
function ">"(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 323
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less(CONV_UNSIGNED(R, length),
CONV_UNSIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 324
constant length: INTEGER := max(L'length, R'length);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 325
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 326
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 327
constant length: INTEGER := L'length + 1;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 328
constant length: INTEGER := R'length + 1;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 329
constant length: INTEGER := L'length;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">"(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to gt
-- synopsys subpgm_id 330
constant length: INTEGER := R'length;
begin
return is_less(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label gt
end;
function ">="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 332
constant length: INTEGER := max(L'length, R'length);
begin
return unsigned_is_less_or_equal(CONV_UNSIGNED(R, length),
CONV_UNSIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 333
constant length: INTEGER := max(L'length, R'length);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 334
constant length: INTEGER := max(L'length + 1, R'length);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 335
constant length: INTEGER := max(L'length, R'length + 1);
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 336
constant length: INTEGER := L'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 337
constant length: INTEGER := R'length + 1;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 338
constant length: INTEGER := L'length;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
function ">="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- pragma label_applies_to geq
-- synopsys subpgm_id 339
constant length: INTEGER := R'length;
begin
return is_less_or_equal(CONV_SIGNED(R, length),
CONV_SIGNED(L, length)); -- pragma label geq
end;
-- for internal use only. Assumes SIGNED arguments of equal length.
function bitwise_eql(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR)
return BOOLEAN is
-- pragma built_in SYN_EQL
begin
for i in L'range loop
if L(i) /= R(i) then
return FALSE;
end if;
end loop;
return TRUE;
end;
-- for internal use only. Assumes SIGNED arguments of equal length.
function bitwise_neq(L: STD_ULOGIC_VECTOR; R: STD_ULOGIC_VECTOR)
return BOOLEAN is
-- pragma built_in SYN_NEQ
begin
for i in L'range loop
if L(i) /= R(i) then
return TRUE;
end if;
end loop;
return FALSE;
end;
function "="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 341
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_UNSIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_UNSIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 342
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 343
constant length: INTEGER := max(L'length + 1, R'length);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 344
constant length: INTEGER := max(L'length, R'length + 1);
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 345
constant length: INTEGER := L'length + 1;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 346
constant length: INTEGER := R'length + 1;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 347
constant length: INTEGER := L'length;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 348
constant length: INTEGER := R'length;
begin
return bitwise_eql( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 350
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_UNSIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_UNSIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 351
constant length: INTEGER := max(L'length, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 352
constant length: INTEGER := max(L'length + 1, R'length);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 353
constant length: INTEGER := max(L'length, R'length + 1);
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: UNSIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 354
constant length: INTEGER := L'length + 1;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: INTEGER; R: UNSIGNED) return BOOLEAN is
-- synopsys subpgm_id 355
constant length: INTEGER := R'length + 1;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: SIGNED; R: INTEGER) return BOOLEAN is
-- synopsys subpgm_id 356
constant length: INTEGER := L'length;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function "/="(L: INTEGER; R: SIGNED) return BOOLEAN is
-- synopsys subpgm_id 357
constant length: INTEGER := R'length;
begin
return bitwise_neq( STD_ULOGIC_VECTOR( CONV_SIGNED(L, length) ),
STD_ULOGIC_VECTOR( CONV_SIGNED(R, length) ) );
end;
function SHL(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED is
-- synopsys subpgm_id 358
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is UNSIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb downto 2**i) :=
result(result_msb - 2**i downto 0);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHL(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED is
-- synopsys subpgm_id 359
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is SIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb downto 2**i) :=
result(result_msb - 2**i downto 0);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHR(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED is
-- synopsys subpgm_id 360
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is UNSIGNED (result_msb downto 0);
variable result, temp: rtype;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => '0');
if 2**i <= result_msb then
temp(result_msb - 2**i downto 0) :=
result(result_msb downto 2**i);
end if;
result := temp;
end if;
end loop;
return result;
end;
function SHR(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED is
-- synopsys subpgm_id 361
constant control_msb: INTEGER := COUNT'length - 1;
variable control: UNSIGNED (control_msb downto 0);
constant result_msb: INTEGER := ARG'length-1;
subtype rtype is SIGNED (result_msb downto 0);
variable result, temp: rtype;
variable sign_bit: STD_ULOGIC;
begin
control := MAKE_BINARY(COUNT);
-- synopsys synthesis_off
if (control(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
-- synopsys synthesis_on
result := ARG;
sign_bit := ARG(ARG'left);
for i in 0 to control_msb loop
if control(i) = '1' then
temp := rtype'(others => sign_bit);
if 2**i <= result_msb then
temp(result_msb - 2**i downto 0) :=
result(result_msb downto 2**i);
end if;
result := temp;
end if;
end loop;
return result;
end;
function CONV_INTEGER(ARG: INTEGER) return INTEGER is
-- synopsys subpgm_id 365
begin
return ARG;
end;
function CONV_INTEGER(ARG: UNSIGNED) return INTEGER is
variable result: INTEGER;
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_UNSIGNED_TO_INTEGER
-- synopsys subpgm_id 366
begin
-- synopsys synthesis_off
assert ARG'length <= 31
report "ARG is too large in CONV_INTEGER"
severity FAILURE;
result := 0;
for i in ARG'range loop
result := result * 2;
tmp := tbl_BINARY(ARG(i));
if tmp = '1' then
result := result + 1;
elsif tmp = 'X' then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
assert false
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
return 0;
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_INTEGER(ARG: SIGNED) return INTEGER is
variable result: INTEGER;
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_SIGNED_TO_INTEGER
-- synopsys subpgm_id 367
begin
-- synopsys synthesis_off
assert ARG'length <= 32
report "ARG is too large in CONV_INTEGER"
severity FAILURE;
result := 0;
for i in ARG'range loop
if i /= ARG'left then
result := result * 2;
tmp := tbl_BINARY(ARG(i));
if tmp = '1' then
result := result + 1;
elsif tmp = 'X' then
assert false
report "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
severity warning;
assert false
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
return 0;
end if;
end if;
end loop;
tmp := MAKE_BINARY(ARG(ARG'left));
if tmp = '1' then
if ARG'length = 32 then
result := (result - 2**30) - 2**30;
else
result := result - (2 ** (ARG'length-1));
end if;
end if;
return result;
-- synopsys synthesis_on
end;
function CONV_INTEGER(ARG: STD_ULOGIC) return SMALL_INT is
variable tmp: STD_ULOGIC;
-- synopsys built_in SYN_FEED_THRU
-- synopsys subpgm_id 370
begin
-- synopsys synthesis_off
tmp := tbl_BINARY(ARG);
if tmp = '1' then
return 1;
elsif tmp = 'X' then
assert false
report "CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, and it has been converted to 0."
severity WARNING;
return 0;
else
return 0;
end if;
-- synopsys synthesis_on
end;
-- convert an integer to a unsigned STD_ULOGIC_VECTOR
function CONV_UNSIGNED(ARG: INTEGER; SIZE: INTEGER) return UNSIGNED is
variable result: UNSIGNED(SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_UNSIGNED
-- synopsys subpgm_id 371
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
else
temp := (temp - 1) / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: UNSIGNED; SIZE: INTEGER) return UNSIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable new_bounds: UNSIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 372
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: SIGNED; SIZE: INTEGER) return UNSIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable new_bounds: UNSIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 373
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_UNSIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return UNSIGNED is
subtype rtype is UNSIGNED (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 375
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
-- convert an integer to a 2's complement STD_ULOGIC_VECTOR
function CONV_SIGNED(ARG: INTEGER; SIZE: INTEGER) return SIGNED is
variable result: SIGNED (SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_SIGNED
-- synopsys subpgm_id 376
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
elsif (temp > integer'low) then
temp := (temp - 1) / 2; -- simulate ASR
else
temp := temp / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: UNSIGNED; SIZE: INTEGER) return SIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is SIGNED (SIZE-1 downto 0);
variable new_bounds : SIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 377
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: SIGNED; SIZE: INTEGER) return SIGNED is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is SIGNED (SIZE-1 downto 0);
variable new_bounds : SIGNED (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 378
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_SIGNED(ARG: STD_ULOGIC; SIZE: INTEGER) return SIGNED is
subtype rtype is SIGNED (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 380
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
-- convert an integer to an STD_LOGIC_VECTOR
function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
variable result: STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable temp: integer;
-- synopsys built_in SYN_INTEGER_TO_BIT_VECTOR
-- synopsys subpgm_id 381
begin
-- synopsys synthesis_off
temp := ARG;
for i in 0 to SIZE-1 loop
if (temp mod 2) = 1 then
result(i) := '1';
else
result(i) := '0';
end if;
if temp > 0 then
temp := temp / 2;
elsif (temp > integer'low) then
temp := (temp - 1) / 2; -- simulate ASR
else
temp := temp / 2; -- simulate ASR
end if;
end loop;
return result;
-- synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: UNSIGNED; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 382
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: SIGNED; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 383
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function CONV_STD_LOGIC_VECTOR(ARG: STD_ULOGIC; SIZE: INTEGER) return STD_LOGIC_VECTOR is
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 384
begin
-- synopsys synthesis_off
result := rtype'(others => '0');
result(0) := MAKE_BINARY(ARG);
if (result(0) = 'X') then
result := rtype'(others => 'X');
end if;
return result;
-- synopsys synthesis_on
end;
function EXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER)
return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds: STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_ZERO_EXTEND
-- synopsys subpgm_id 385
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => '0');
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
function SXT(ARG: STD_LOGIC_VECTOR; SIZE: INTEGER) return STD_LOGIC_VECTOR is
constant msb: INTEGER := min(ARG'length, SIZE) - 1;
subtype rtype is STD_LOGIC_VECTOR (SIZE-1 downto 0);
variable new_bounds : STD_LOGIC_VECTOR (ARG'length-1 downto 0);
variable result: rtype;
-- synopsys built_in SYN_SIGN_EXTEND
-- synopsys subpgm_id 386
begin
-- synopsys synthesis_off
new_bounds := MAKE_BINARY(ARG);
if (new_bounds(0) = 'X') then
result := rtype'(others => 'X');
return result;
end if;
result := rtype'(others => new_bounds(new_bounds'left));
result(msb downto 0) := new_bounds(msb downto 0);
return result;
-- synopsys synthesis_on
end;
end std_logic_arith;
| gpl-2.0 |
freecores/t400 | rtl/vhdl/t400_dmem_ctrl.vhd | 1 | 8275 | -------------------------------------------------------------------------------
--
-- The Data memory controller.
--
-- $Id: t400_dmem_ctrl.vhd,v 1.1.1.1 2006-05-06 01:56:44 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
use work.t400_pack.all;
entity t400_dmem_ctrl is
generic (
opt_type_g : integer := t400_opt_type_420_c
);
port (
-- System Interface -------------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
res_i : in boolean;
-- Control Interface ------------------------------------------------------
dmem_op_i : in dmem_op_t;
b_op_i : in b_op_t;
dec_data_i : in dec_data_t;
a_i : in dw_t;
q_high_i : in dw_t;
b_o : out b_t;
-- Data Memory Interface --------------------------------------------------
dm_addr_o : out dm_addr_t;
dm_data_i : in dw_t;
dm_data_o : out dw_t;
dm_we_o : out std_logic
);
end t400_dmem_ctrl;
library ieee;
use ieee.numeric_std.all;
architecture rtl of t400_dmem_ctrl is
signal br_q : unsigned(br_range_t);
signal bd_q : unsigned(bd_range_t);
begin
-----------------------------------------------------------------------------
-- Process b_reg
--
-- Purpose:
-- Implements the B register.
--
b_reg: process (ck_i, por_i)
begin
if por_i then
br_q <= (others => '0');
bd_q <= (others => '0');
elsif ck_i'event and ck_i = '1' then
if res_i then
-- synchronous reset upon external reset event
br_q <= (others => '0');
bd_q <= (others => '0');
elsif ck_en_i then
case b_op_i is
-- Set Bd from accumulator ------------------------------------------
when B_SET_BD =>
bd_q <= unsigned(a_i);
-- Set Br from accumulator ------------------------------------------
when B_SET_BR =>
br_q <= unsigned(a_i(1 downto 0));
-- Set Br and Bd from decoder data ----------------------------------
when B_SET_B =>
br_q <= unsigned(dec_data_i(br_range_t));
bd_q <= unsigned(dec_data_i(bd_range_t));
-- Set Br and Bd from decoder data, increment value for Bd ----------
when B_SET_B_INC =>
br_q <= unsigned(dec_data_i(br_range_t));
bd_q <= unsigned(dec_data_i(bd_range_t)) + 1;
-- XOR Br with decoder data -----------------------------------------
when B_XOR_BR =>
br_q <= br_q xor unsigned(dec_data_i(br_range_t));
-- Increment Bd -----------------------------------------------------
when B_INC_BD =>
bd_q <= bd_q + 1;
-- Increment Bd -----------------------------------------------------
when B_DEC_BD =>
bd_q <= bd_q - 1;
when others =>
null;
end case;
end if;
end if;
end process b_reg;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process data_mux
--
-- Purpose:
-- Multiplexes the data for writing to the memory.
--
data_mux: process (dmem_op_i,
br_q, bd_q,
a_i,
q_high_i,
dec_data_i,
dm_data_i,
ck_en_i)
variable dm_addr_v : dm_addr_t;
variable dm_data_v : dw_t;
variable dm_we_v : std_logic;
variable bd_v : std_logic_vector(2 downto 0);
begin
-- default assignment
dm_addr_v(br_range_t) := std_logic_vector(br_q);
dm_addr_v(bd_range_t) := std_logic_vector(bd_q);
dm_data_v := (others => '0');
dm_we_v := '0';
case dmem_op_i is
-- Read data memory, indexed by B ---------------------------------------
when DMEM_RB =>
null;
-- Write data memory, indexed by B, source is Q -------------------------
when DMEM_WB_SRC_Q =>
dm_we_v := '1';
dm_data_v := q_high_i;
-- Write data memory, indexed by B, source is decoder data --------------
when DMEM_WB_SRC_DEC =>
dm_we_v := '1';
dm_data_v := dec_data_i(bd_range_t);
-- Write data memory, indexed by B, source is accumulator ---------------
when DMEM_WB_SRC_A =>
dm_we_v := '1';
dm_data_v := a_i;
-- Read data memory, indexed by decoder data ----------------------------
when DMEM_RDEC =>
dm_addr_v := dec_data_i(br_range_t'high downto 0);
-- Write data memory, indexed by decoder data, source is accumulator ----
when DMEM_WDEC_SRC_A =>
dm_we_v := '1';
dm_addr_v := dec_data_i(br_range_t'high downto 0);
dm_data_v := a_i;
-- Write data memory, indexed by B, set bit -----------------------------
when DMEM_WB_SET_BIT =>
dm_we_v := '1';
dm_data_v := dm_data_i or dec_data_i(dw_range_t);
-- Write data memory, indexed by B, reset bit ---------------------------
when DMEM_WB_RES_BIT =>
dm_we_v := '1';
dm_data_v := dm_data_i and not dec_data_i(dw_range_t);
when others =>
null;
end case;
-- adjust address vector for 41xL family members
if opt_type_g = t400_opt_type_410_c then
dm_addr_v := '0' & dm_addr_v(br_range_t) &
dm_addr_v(bd_range_t'high-1 downto 0);
end if;
dm_addr_o <= dm_addr_v;
if ck_en_i then
dm_we_o <= dm_we_v;
else
dm_we_o <= '0';
end if;
dm_data_o <= dm_data_v;
end process data_mux;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
b_o(br_range_t) <= std_logic_vector(br_q);
b_o(bd_range_t) <= std_logic_vector(bd_q);
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
| gpl-2.0 |
freecores/t400 | rtl/vhdl/t400_stack.vhd | 1 | 4724 | -------------------------------------------------------------------------------
--
-- The stack unit.
--
-- $Id: t400_stack.vhd,v 1.3 2006-06-11 02:12:11 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
use work.t400_pack.all;
entity t400_stack is
generic (
opt_type_g : integer := t400_opt_type_420_c
);
port (
-- System Interface -------------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
-- Stack Control Interface ------------------------------------------------
op_i : in stack_op_t;
-- Program Counter Interface ----------------------------------------------
pc_i : in pc_t;
pc_o : out pc_t
);
end t400_stack;
-- pragma translate_off
use work.tb_pack.tb_sa_s;
-- pragma translate_on
architecture rtl of t400_stack is
signal sa_q,
sb_q,
sc_q : pc_t;
begin
-----------------------------------------------------------------------------
-- Process stack
--
-- Purpose:
-- Implements the stack consisting of SA, SB, SC.
-- SC is skipped when it's a 41xL.
--
stack: process (ck_i, por_i)
variable t41x_type_v : boolean;
begin
if por_i then
sa_q <= (others => '0');
sb_q <= (others => '0');
sc_q <= (others => '0');
elsif ck_i'event and ck_i = '1' then
-- determine type
t41x_type_v := opt_type_g = t400_opt_type_410_c;
if ck_en_i then
case op_i is
when STACK_PUSH =>
sa_q <= pc_i;
sb_q <= sa_q;
if not t41x_type_v then
sc_q <= sb_q;
else
sc_q <= (others => '0');
end if;
when STACK_POP =>
sa_q <= sb_q;
if not t41x_type_v then
sb_q <= sc_q;
end if;
when others =>
null;
end case;
end if;
end if;
end process stack;
--
-----------------------------------------------------------------------------
-- pragma translate_off
-- instrument interrupt testbench
tb_sa_s <= sa_q;
-- pragma translate_on
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
pc_o <= sa_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.2 2006/05/27 19:15:59 arniml
-- instrument testbench
--
-- Revision 1.1.1.1 2006/05/06 01:56:45 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------
| gpl-2.0 |
freecores/t400 | bench/vhdl/tb_t410.vhd | 1 | 4618 | -------------------------------------------------------------------------------
--
-- Testbench for the T410 system toplevel.
--
-- $Id: tb_t410.vhd,v 1.1 2006-06-11 22:19:32 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
entity tb_t410 is
end tb_t410;
library ieee;
use ieee.std_logic_1164.all;
use work.t400_system_comp_pack.t410;
use work.tb_pack.tb_elems;
use work.t400_opt_pack.all;
architecture behav of tb_t410 is
-- 210.4 kHz clock
constant period_c : time := 4.75 us;
signal ck_s : std_logic;
signal reset_n_s : std_logic;
signal io_l_s : std_logic_vector(7 downto 0);
signal io_d_s : std_logic_vector(3 downto 0);
signal io_g_s : std_logic_vector(3 downto 0);
signal si_s,
so_s,
sk_s : std_logic;
signal vdd_s : std_logic;
begin
vdd_s <= '1';
reset_n_s <= '1';
-----------------------------------------------------------------------------
-- DUT
-----------------------------------------------------------------------------
t410_b : t410
generic map (
opt_ck_div_g => t400_opt_ck_div_8_c
)
port map (
ck_i => ck_s,
ck_en_i => vdd_s,
reset_n_i => reset_n_s,
si_i => si_s,
so_o => so_s,
sk_o => sk_s,
io_l_b => io_l_s,
io_d_o => io_d_s,
io_g_b => io_g_s
);
io_l_s <= (others => 'H');
io_d_s <= (others => 'H');
io_g_s <= (others => 'H');
-----------------------------------------------------------------------------
-- Testbench elements
-----------------------------------------------------------------------------
tb_elems_b : tb_elems
generic map (
period_g => period_c,
d_width_g => 4,
g_width_g => 4
)
port map (
io_l_i => io_l_s,
io_d_i => io_d_s,
io_g_i => io_g_s,
io_in_o => open,
so_i => so_s,
si_o => si_s,
sk_i => sk_s,
ck_o => ck_s
);
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.6 2006/06/05 18:50:45 arniml
-- remove obsolete en_clk_s
--
-- Revision 1.5 2006/05/27 19:10:12 arniml
-- explicitly select clock divider 8
--
-- Revision 1.4 2006/05/23 01:18:26 arniml
-- consider IN port
--
-- Revision 1.3 2006/05/15 21:56:02 arniml
-- moved elements to separate design unit tb_elems
--
-- Revision 1.2 2006/05/06 13:34:25 arniml
-- remove delta cycle filter on sk_s
--
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------
| gpl-2.0 |
EPiCS/reconos | demos/matrixmul/hw/hwt_matrixmul_v2_00_a/hdl/vhdl/hwt_matrixmul.vhd | 2 | 14885 | ------------------------------------------------------------------------------
-- hwt_matrixmul - entity/architecture pair
------------------------------------------------------------------------------
-- Filename: hwt_matrixmul
-- Version: 2.00.a
-- Description: ReconOS matrix multiplier hardware thread (VHDL).
-- Date: Wed June 7 16:32:00 2013
-- VHDL Standard: VHDL'93
-- Author: Achim Loesch
------------------------------------------------------------------------------
-- Feel free to modify this file.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_01_a;
use reconos_v3_01_a.reconos_pkg.all;
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity hwt_matrixmul is
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic
);
attribute SIGIS : string;
attribute SIGIS of HWT_Clk : signal is "Clk";
attribute SIGIS of HWT_Rst : signal is "Rst";
end hwt_matrixmul;
------------------------------------------------------------------------------
-- Architecture Section
------------------------------------------------------------------------------
architecture implementation of hwt_matrixmul is
type STATE_TYPE is (
STATE_GET_ADDR2MADDRS,
STATE_READ_MADDRS,
STATE_READ_MATRIX_B,
STATE_READ_MATRIX_ROW_FROM_A,
STATE_MULTIPLY_MATRIX_ROW,
STATE_WRITE_MATRIX_ROW_TO_C,
STATE_ACK,
STATE_THREAD_EXIT
);
component matrixmultiplier is
generic (
G_LINE_LEN_MATRIX : integer := 128;
G_RAM_DATA_WIDTH : integer := 32;
G_RAM_SIZE_MATRIX_A_C : integer := 128;
G_RAM_ADDR_WIDTH_MATRIX_A_C : integer := 7;
G_RAM_SIZE_MATRIX_B : integer := 16384;
G_RAM_ADDR_WIDTH_MATRIX_B : integer := 14
);
port (
clk : in std_logic;
reset : in std_logic;
start : in std_logic;
done : out std_logic;
o_RAM_A_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
i_RAM_A_Data : in std_logic_vector(0 to G_RAM_DATA_WIDTH - 1);
o_RAM_B_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_B - 1);
i_RAM_B_Data : in std_logic_vector(0 to G_RAM_DATA_WIDTH - 1);
o_RAM_C_Addr : out std_logic_vector(0 to G_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
o_RAM_C_Data : out std_logic_vector(0 to G_RAM_DATA_WIDTH - 1);
o_RAM_C_WE : out std_logic
);
end component;
--constant C_LINE_LEN_MATRIX : integer := 128;
-- Use the following line for testing purposes.
constant C_LINE_LEN_MATRIX : integer := 4;
-- const for matrixes A and C
constant C_LOCAL_RAM_SIZE_MATRIX_A_C : integer := C_LINE_LEN_MATRIX;
constant C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C : integer := clog2(C_LOCAL_RAM_SIZE_MATRIX_A_C);
constant C_LOCAL_RAM_SIZE_IN_BYTES_MATRIX_A_C : integer := 4*C_LOCAL_RAM_SIZE_MATRIX_A_C;
type LOCAL_MEMORY_TYPE_MATRIX_A_C is array(0 to C_LOCAL_RAM_SIZE_MATRIX_A_C - 1) of std_logic_vector(31 downto 0);
-- const for matrix B
constant C_LOCAL_RAM_SIZE_MATRIX_B : integer := C_LINE_LEN_MATRIX*C_LINE_LEN_MATRIX;
constant C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B : integer := clog2(C_LOCAL_RAM_SIZE_MATRIX_B);
constant C_LOCAL_RAM_SIZE_IN_BYTES_MATRIX_B : integer := 4*C_LOCAL_RAM_SIZE_MATRIX_B;
type LOCAL_MEMORY_TYPE_MATRIX_B is array(0 to C_LOCAL_RAM_SIZE_MATRIX_B - 1) of std_logic_vector(31 downto 0);
-- communication with microblaze core
constant C_MBOX_RECV : std_logic_vector(31 downto 0) := x"00000000";
constant C_MBOX_SEND : std_logic_vector(31 downto 0) := x"00000001";
signal ignore : std_logic_vector(31 downto 0);
-- maddr is an acronym for "matrix address" (address that points to a matrix)
constant C_MADDRS : integer := 3;
type MADDR_BOX_TYPE is array(0 to C_MADDRS-1) of std_logic_vector(31 downto 0);
-- container for adresses pointing to the first element of matrixes A, B and C
signal maddrs : MADDR_BOX_TYPE;
-- points to pointers to the matrixes
signal addr2maddrs : std_logic_vector(31 downto 0);
-- temporary signals
signal temp_addr_A : std_logic_vector(31 downto 0);
signal temp_addr_C : std_logic_vector(31 downto 0);
-- fsm state
signal state : STATE_TYPE;
-- additional data for memif interfaces
signal len_data_MATRIX_A_C : std_logic_vector(23 downto 0);
signal len_data_MATRIX_B : std_logic_vector(23 downto 0);
-- osif, memif and different local BRAM interfaces
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal i_memif : i_memif_t;
signal o_memif : o_memif_t;
signal i_ram_A : i_ram_t;
signal o_ram_A : o_ram_t;
signal i_ram_B : i_ram_t;
signal o_ram_B : o_ram_t;
signal i_ram_C : i_ram_t;
signal o_ram_C : o_ram_t;
signal o_RAM_A_Addr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
signal o_RAM_A_Addr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAM_A_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_A_WE_reconos : std_logic;
signal i_RAM_A_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_B_Addr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B - 1);
signal o_RAM_B_Addr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAM_B_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_B_WE_reconos : std_logic;
signal i_RAM_B_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_C_Addr_reconos : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
signal o_RAM_C_Addr_reconos_2 : std_logic_vector(0 to 31);
signal o_RAM_C_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_C_WE_reconos : std_logic;
signal i_RAM_C_Data_reconos : std_logic_vector(0 to 31);
signal o_RAM_A_Addr_mul : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
signal i_RAM_A_Data_mul : std_logic_vector(0 to 31);
signal o_RAM_B_Addr_mul : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B - 1);
signal i_RAM_B_Data_mul : std_logic_vector(0 to 31);
signal o_RAM_C_Addr_mul : std_logic_vector(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1);
signal o_RAM_C_Data_mul : std_logic_vector(0 to 31);
signal o_RAM_C_WE_mul : std_logic;
shared variable local_ram_a : LOCAL_MEMORY_TYPE_MATRIX_A_C;
shared variable local_ram_b : LOCAL_MEMORY_TYPE_MATRIX_B;
shared variable local_ram_c : LOCAL_MEMORY_TYPE_MATRIX_A_C;
signal multiplier_start : std_logic;
signal multiplier_done : std_logic;
signal clk, rst : std_logic;
begin
clk <= HWT_Clk;
rst <= HWT_Rst;
-- local BRAM read and write access
local_ram_ctrl_1 : process (clk) is
begin
if (clk'event and clk = '1') then
if (o_RAM_A_WE_reconos = '1') then
local_ram_A(conv_integer(unsigned(o_RAM_A_Addr_reconos))) := o_RAM_A_Data_reconos;
end if;
if (o_RAM_B_WE_reconos = '1') then
local_ram_B(conv_integer(unsigned(o_RAM_B_Addr_reconos))) := o_RAM_B_Data_reconos;
end if;
if (o_RAM_C_WE_reconos = '0') then
i_RAM_C_Data_reconos <= local_ram_C(conv_integer(unsigned(o_RAM_C_Addr_reconos)));
end if;
end if;
end process;
local_ram_ctrl_2 : process (clk) is
begin
if (rising_edge(clk)) then
if (o_RAM_C_WE_mul = '1') then
local_ram_C(conv_integer(unsigned(o_RAM_C_Addr_mul))) := o_RAM_C_Data_mul;
else
i_RAM_A_Data_mul <= local_ram_A(conv_integer(unsigned(o_RAM_A_Addr_mul)));
i_RAM_B_Data_mul <= local_ram_B(conv_integer(unsigned(o_RAM_B_Addr_mul)));
end if;
end if;
end process;
-- the matrix multiplication module
matrixmultiplier_i : matrixmultiplier
generic map(
G_LINE_LEN_MATRIX => C_LINE_LEN_MATRIX,
G_RAM_DATA_WIDTH => 32,
G_RAM_SIZE_MATRIX_A_C => C_LOCAL_RAM_SIZE_MATRIX_A_C,
G_RAM_ADDR_WIDTH_MATRIX_A_C => C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C,
G_RAM_SIZE_MATRIX_B => C_LOCAL_RAM_SIZE_MATRIX_B,
G_RAM_ADDR_WIDTH_MATRIX_B => C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B
)
port map(
clk => clk,
reset => rst,
start => multiplier_start,
done => multiplier_done,
o_RAM_A_Addr => o_RAM_A_Addr_mul,
i_RAM_A_Data => i_RAM_A_Data_mul,
o_RAM_B_Addr => o_RAM_B_Addr_mul,
i_RAM_B_Data => i_RAM_B_Data_mul,
o_RAM_C_Addr => o_RAM_C_Addr_mul,
o_RAM_C_Data => o_RAM_C_Data_mul,
o_RAM_C_WE => o_RAM_C_WE_mul
);
-- setup interfaces (FIFOs, FSL,...)
-- ReconOS initilization
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
memif_setup (
i_memif,
o_memif,
MEMIF_FIFO_Mem2Hwt_Data,
MEMIF_FIFO_Mem2Hwt_Fill,
MEMIF_FIFO_Mem2Hwt_Empty,
MEMIF_FIFO_Hwt2Mem_Rem,
MEMIF_FIFO_Hwt2Mem_Full,
MEMIF_FIFO_Mem2Hwt_RE,
MEMIF_FIFO_Hwt2Mem_Data,
MEMIF_FIFO_Hwt2Mem_WE
);
ram_setup (
i_ram_A,
o_ram_A,
o_RAM_A_Addr_reconos_2,
o_RAM_A_WE_reconos,
o_RAM_A_Data_reconos,
i_RAM_A_Data_reconos
);
ram_setup (
i_ram_B,
o_ram_B,
o_RAM_B_Addr_reconos_2,
o_RAM_B_WE_reconos,
o_RAM_B_Data_reconos,
i_RAM_B_Data_reconos
);
ram_setup (
i_ram_C,
o_ram_C,
o_RAM_C_Addr_reconos_2,
o_RAM_C_WE_reconos,
o_RAM_C_Data_reconos,
i_RAM_C_Data_reconos
);
o_RAM_A_Addr_reconos(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1) <= o_RAM_A_Addr_reconos_2((32-C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C) to 31);
o_RAM_B_Addr_reconos(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B - 1) <= o_RAM_B_Addr_reconos_2((32-C_LOCAL_RAM_ADDR_WIDTH_MATRIX_B ) to 31);
o_RAM_C_Addr_reconos(0 to C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C - 1) <= o_RAM_C_Addr_reconos_2((32-C_LOCAL_RAM_ADDR_WIDTH_MATRIX_A_C) to 31);
reconos_fsm : process(clk, rst, o_osif, o_memif, o_ram_a, o_ram_b, o_ram_c) is
variable done : boolean;
variable addr_pos : integer;
variable calculated_rows : integer;
begin
if (rst = '1') then
osif_reset(o_osif);
memif_reset(o_memif);
ram_reset(o_ram_A);
ram_reset(o_ram_B);
ram_reset(o_ram_C);
multiplier_start <= '0';
done := false;
calculated_rows := 0;
len_data_MATRIX_A_C <= conv_std_logic_vector(C_LOCAL_RAM_SIZE_IN_BYTES_MATRIX_A_C, 24);
len_data_MATRIX_B <= conv_std_logic_vector(C_LOCAL_RAM_SIZE_IN_BYTES_MATRIX_B , 24);
-- important to know:
-- maddrs(0) = C, maddrs(1) = B, maddrs(2) = A
addr2maddrs <= (others => '0');
addr_pos := C_MADDRS - 1;
for i in 0 to (C_MADDRS - 1) loop
maddrs(i) <= (others => '0');
end loop;
temp_addr_A <= (others => '0');
temp_addr_C <= (others => '0');
state <= STATE_GET_ADDR2MADDRS;
elsif (clk'event and clk = '1') then
case state is
-- Get address pointing to the addresses pointing to the 3 matrixes via FSL.
when STATE_GET_ADDR2MADDRS =>
osif_mbox_get(i_osif, o_osif, C_MBOX_RECV, addr2maddrs, done);
if (done) then
if (addr2maddrs = x"FFFFFFFF") then
state <= STATE_THREAD_EXIT;
else
addr2maddrs <= addr2maddrs(31 downto 2) & "00";
addr_pos := C_MADDRS - 1;
state <= STATE_READ_MADDRS;
end if;
end if;
-- Read addresses pointing to input matrixes A, B and output matrix C from main memory.
when STATE_READ_MADDRS =>
memif_read_word(i_memif, o_memif, addr2maddrs, maddrs(addr_pos), done);
if done then
if (addr_pos = 0) then
state <= STATE_READ_MATRIX_B;
else
addr_pos := addr_pos - 1;
addr2maddrs <= conv_std_logic_vector(unsigned(addr2maddrs) + 4, 32);
end if;
end if;
-- Read matrix B from main memory.
when STATE_READ_MATRIX_B =>
memif_read(i_ram_B, o_ram_B, i_memif, o_memif, maddrs(1), X"00000000", len_data_MATRIX_B, done);
if done then
temp_addr_A <= maddrs(2);
temp_addr_C <= maddrs(0);
state <= STATE_READ_MATRIX_ROW_FROM_A;
end if;
-- Read a row of matrix A.
when STATE_READ_MATRIX_ROW_FROM_A =>
memif_read(i_ram_A, o_ram_A, i_memif, o_memif, temp_addr_A, X"00000000", len_data_MATRIX_A_C, done);
if done then
multiplier_start <= '1';
state <= STATE_MULTIPLY_MATRIX_ROW;
end if;
-- Multiply row of matrix A with matrix B.
when STATE_MULTIPLY_MATRIX_ROW =>
multiplier_start <= '0';
if (multiplier_done = '1') then
calculated_rows := calculated_rows + 1;
state <= STATE_WRITE_MATRIX_ROW_TO_C;
end if;
-- Write multiplication result (row of matrix C) to main memory.
when STATE_WRITE_MATRIX_ROW_TO_C =>
memif_write(i_ram_C, o_ram_C, i_memif, o_memif, X"00000000", temp_addr_C, len_data_MATRIX_A_C, done);
if (done) then
if (calculated_rows < C_LINE_LEN_MATRIX) then
-- Calculate new temporary addresses
-- => to fetch next matrix row of matrix A
-- => to store calculated values to next matrix row of matrix C
temp_addr_A <= conv_std_logic_vector(unsigned(temp_addr_A) + C_LINE_LEN_MATRIX*4, 32);
temp_addr_C <= conv_std_logic_vector(unsigned(temp_addr_C) + C_LINE_LEN_MATRIX*4, 32);
state <= STATE_READ_MATRIX_ROW_FROM_A;
else
state <= STATE_ACK;
end if;
end if;
-- We finished calculating matrix multiplication A * B = C.
when STATE_ACK =>
osif_mbox_put(i_osif, o_osif, C_MBOX_SEND, maddrs(addr_pos), ignore, done);
if (done) then
calculated_rows := 0;
addr_pos := C_MADDRS - 1;
temp_addr_A <= (others => '0');
temp_addr_C <= (others => '0');
state <= STATE_GET_ADDR2MADDRS;
end if;
-- Terminate hardware thread.
when STATE_THREAD_EXIT =>
osif_thread_exit(i_osif, o_osif);
end case;
end if;
end process;
end architecture implementation;
| gpl-2.0 |
EPiCS/reconos | pcores/reconos_memif_mmu_zynq_v1_00_a/hdl/vhdl/reconos_memif_mmu_zynq.vhd | 2 | 11465 | -- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - MEMIF MMU
--
-- project: ReconOS
-- author: Christoph Rüthing, University of Paderborn
-- description: The memory management unit enables virtual address
-- support. Therefore it performs page table walks,
-- manages a TLB for faster translation and handles
-- page fault via the proc control unit.
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_memif_mmu_zynq_v1_00_a;
use reconos_memif_mmu_zynq_v1_00_a.tlb;
entity reconos_memif_mmu_zynq is
generic (
C_CTRL_FIFO_WIDTH : integer := 32;
C_MEMIF_LENGTH_WIDTH : integer := 24;
C_TLB_SIZE : integer := 128
);
port (
-- Input FIFO ports from the HWTs (via burst converter and transaction control)
CTRL_FIFO_In_Data : in std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
CTRL_FIFO_In_Fill : in std_logic_vector(15 downto 0);
CTRL_FIFO_In_Empty : in std_logic;
CTRL_FIFO_In_RE : out std_logic;
-- Output FIFO ports to memory controller
CTRL_FIFO_Out_Data : out std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
CTRL_FIFO_Out_Fill : out std_logic_vector(15 downto 0);
CTRL_FIFO_Out_Empty : out std_logic;
CTRL_FIFO_Out_RE : in std_logic;
-- Seperate control and data FIFOs (emulated) for page table walks
CTRL_FIFO_Mmu_Data : out std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
CTRL_FIFO_Mmu_Fill : out std_logic_vector(15 downto 0);
CTRL_FIFO_Mmu_Empty : out std_logic;
CTRL_FIFO_Mmu_RE : in std_logic;
MEMIF_FIFO_Mmu_Data : in std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
MEMIF_FIFO_Mmu_Rem : out std_logic_vector(15 downto 0);
MEMIF_FIFO_Mmu_Full : out std_logic;
MEMIF_FIFO_Mmu_WE : in std_logic;
-- MMU ports
MMU_Pgf : out std_logic;
MMU_Fault_addr : out std_logic_vector(31 downto 0);
MMU_Retry : in std_logic;
MMU_Pgd : in std_logic_vector(31 downto 0);
MMU_Tlb_Hits : out std_logic_vector(31 downto 0);
MMU_Tlb_Misses : out std_logic_vector(31 downto 0);
MMU_Clk : in std_logic;
MMU_Rst : in std_logic;
DEBUG_DATA : out std_logic_vector(203 downto 0)
);
attribute SIGIS : string;
attribute SIGIS of MMU_Clk : signal is "Clk";
attribute SIGIS of MMU_Rst : signal is "Rst";
end entity reconos_memif_mmu_zynq;
architecture implementation of reconos_memif_mmu_zynq is
constant C_MEMIF_CMD_WIDTH : integer := C_CTRL_FIFO_WIDTH - C_MEMIF_LENGTH_WIDTH;
signal ctrl_in_re : std_logic;
signal ctrl_out_data : std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
signal ctrl_out_fill : std_logic_vector(15 downto 0);
signal ctrl_out_empty : std_logic;
signal ctrl_mmu_data : std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
signal ctrl_mmu_fill : std_logic_vector(15 downto 0);
signal ctrl_mmu_empty : std_logic;
-- MMU signals
type STATE_TYPE is (WAIT_REQUEST, READ_CMD, READ_ADDR,
READ_L1_ENTRY_0, READ_L1_ENTRY_1, READ_L1_ENTRY_2,
READ_L2_ENTRY_0, READ_L2_ENTRY_1, READ_L2_ENTRY_2,
WRITE_CMD, WRITE_ADDR, PAGE_FAULT);
signal state : STATE_TYPE;
signal pgf : std_logic;
signal tlb_hits : std_logic_vector(31 downto 0);
signal tlb_misses : std_logic_vector(31 downto 0);
-- these signals contain the received request data unchanged
signal ctrl_cmd : std_logic_vector(C_MEMIF_CMD_WIDTH - 1 downto 0);
signal ctrl_length : std_logic_vector(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
signal ctrl_addr : std_logic_vector(C_CTRL_FIFO_WIDTH - 1 downto 0);
signal l1_table_addr : std_logic_vector(31 downto 0); -- address of the level 1 page table
signal l1_descriptor_addr : std_logic_vector(31 downto 0); -- address of the level 1 page table entry
signal l2_table_addr : std_logic_vector(31 downto 0); -- address of the level 2 page table
signal l2_descriptor_addr : std_logic_vector(31 downto 0); -- address of the level 2 page table entry
signal small_page_addr : std_logic_vector(31 downto 0); -- page table entry
signal physical_addr : std_logic_vector(31 downto 0); -- physical address
signal tlb_hit : std_logic;
signal tlb_tag : std_logic_vector(19 downto 0);
signal tlb_do : std_logic_vector(19 downto 0);
signal tlb_di : std_logic_vector(19 downto 0);
signal tlb_we : std_logic;
signal clk : std_logic;
signal rst : std_logic;
begin
DEBUG_DATA(0) <= '1' when state = WAIT_REQUEST else '0';
DEBUG_DATA(1) <= '1' when state = READ_CMD else '0';
DEBUG_DATA(2) <= '1' when state = READ_ADDR else '0';
DEBUG_DATA(3) <= '1' when state = READ_L1_ENTRY_0 else '0';
DEBUG_DATA(4) <= '1' when state = READ_L1_ENTRY_1 else '0';
DEBUG_DATA(5) <= '1' when state = READ_L1_ENTRY_2 else '0';
DEBUG_DATA(6) <= '1' when state = READ_L2_ENTRY_0 else '0';
DEBUG_DATA(7) <= '1' when state = READ_L2_ENTRY_1 else '0';
DEBUG_DATA(8) <= '1' when state = READ_L2_ENTRY_2 else '0';
DEBUG_DATA(9) <= '1' when state = WRITE_CMD else '0';
DEBUG_DATA(10) <= '1' when state = WRITE_ADDR else '0';
DEBUG_DATA(11) <= '1' when state = PAGE_FAULT else '0';
DEBUG_DATA(203 downto 172) <= l1_table_addr;
DEBUG_DATA(171 downto 140) <= l1_descriptor_addr;
DEBUG_DATA(139 downto 108) <= l2_table_addr;
DEBUG_DATA(107 downto 76) <= l2_descriptor_addr;
DEBUG_DATA(75 downto 44) <= small_page_addr;
DEBUG_DATA(43 downto 12) <= physical_addr;
clk <= MMU_Clk;
rst <= MMU_Rst;
CTRL_FIFO_In_RE <= ctrl_in_re;
CTRL_FIFO_Out_Data <= ctrl_out_data;
CTRL_FIFO_Out_Fill <= ctrl_out_fill;
CTRL_FIFO_Out_Empty <= ctrl_out_empty;
CTRL_FIFO_Mmu_Data <= ctrl_mmu_data;
CTRL_FIFO_Mmu_Fill <= ctrl_mmu_fill;
CTRL_FIFO_Mmu_Empty <= ctrl_mmu_empty;
MEMIF_FIFO_Mmu_Rem <= X"1111";
MEMIF_FIFO_Mmu_Full <= '0';
MMU_Pgf <= pgf;
MMU_Fault_Addr <= ctrl_addr;
MMU_Tlb_Hits <= tlb_hits;
MMU_Tlb_Misses <= tlb_misses;
-- some address calculations based on the page table architecture
-- for detailed information look into the TRM on page 80
l1_table_addr <= MMU_Pgd;
l1_descriptor_addr <= l1_table_addr(31 downto 14) & ctrl_addr(31 downto 20) & "00";
l2_descriptor_addr <= l2_table_addr(31 downto 10) & ctrl_addr(19 downto 12) & "00";
physical_addr <= small_page_addr(31 downto 12) & ctrl_addr(11 downto 0);
mmu_proc : process(clk,rst) is
begin
if rst = '1' then
state <= WAIT_REQUEST;
ctrl_cmd <= (others => '0');
ctrl_length <= (others => '0');
ctrl_addr <= (others => '0');
ctrl_out_empty <= '1';
ctrl_out_fill <= (others => '0');
ctrl_out_data <= (others => '0');
ctrl_in_re <= '0';
ctrl_mmu_empty <= '1';
ctrl_mmu_fill <= (others => '0');
ctrl_mmu_data <= (others => '0');
pgf <= '0';
tlb_hits <= (others => '0');
tlb_misses <= (others => '0');
elsif rising_edge(clk) then
tlb_we <= '0';
case state is
when WAIT_REQUEST =>
-- start reading if there are 2 word in FIFO
--if CTRL_FIFO_In_Empty = '0' and CTRL_FIFO_In_Fill >= X"0001" then
ctrl_in_re <= '1';
state <= READ_CMD;
--end if;
when READ_CMD =>
-- read cmd and length
if CTRL_FIFO_In_Empty = '0' then
ctrl_cmd <= CTRL_FIFO_In_Data(31 downto C_MEMIF_LENGTH_WIDTH);
ctrl_length <= CTRL_FIFO_In_Data(C_MEMIF_LENGTH_WIDTH - 1 downto 0);
state <= READ_ADDR;
end if;
when READ_ADDR =>
-- read address
if CTRL_FIFO_In_Empty = '0' then
ctrl_addr <= CTRL_FIFO_In_Data;
ctrl_in_re <= '0';
state <= READ_L1_ENTRY_0;
end if;
when READ_L1_ENTRY_0 =>
if tlb_hit = '1' then
small_page_addr(31 downto 12) <= tlb_do;
ctrl_out_empty <= '0';
ctrl_out_fill <= X"0001";
ctrl_out_data <= ctrl_cmd & ctrl_length;
tlb_hits <= tlb_hits + 1;
state <= WRITE_CMD;
else
-- write command to memory controller
ctrl_mmu_empty <= '0';
ctrl_mmu_fill <= X"0001";
ctrl_mmu_data <= X"00000004";
if CTRL_FIFO_Mmu_RE = '1' and ctrl_mmu_empty = '0' then
ctrl_mmu_fill <= X"0000";
ctrl_mmu_data <= l1_descriptor_addr;
tlb_misses <= tlb_misses + 1;
state <= READ_L1_ENTRY_1;
end if;
end if;
when READ_L1_ENTRY_1 =>
if CTRL_FIFO_Mmu_RE = '1' and ctrl_mmu_empty = '0' then
ctrl_mmu_empty <= '1';
ctrl_mmu_fill <= X"0000";
state <= READ_L1_ENTRY_2;
end if;
when READ_L1_ENTRY_2 =>
if MEMIF_FIFO_Mmu_WE = '1' then
l2_table_addr <= MEMIF_FIFO_Mmu_Data;
if MEMIF_FIFO_Mmu_Data(1 downto 0) = "00" then
pgf <= '1';
state <= PAGE_FAULT;
else
state <= READ_L2_ENTRY_0;
end if;
end if;
when READ_L2_ENTRY_0 =>
ctrl_mmu_empty <= '0';
ctrl_mmu_fill <= X"0001";
ctrl_mmu_data <= X"00000004";
if CTRL_FIFO_Mmu_RE = '1' and ctrl_mmu_empty = '0' then
ctrl_mmu_fill <= X"0000";
ctrl_mmu_data <= l2_descriptor_addr;
state <= READ_L2_ENTRY_1;
end if;
when READ_L2_ENTRY_1 =>
if CTRL_FIFO_Mmu_RE = '1' and ctrl_mmu_empty = '0' then
ctrl_mmu_empty <= '1';
ctrl_mmu_fill <= X"0000";
state <= READ_L2_ENTRY_2;
end if;
when READ_L2_ENTRY_2 =>
if MEMIF_FIFO_Mmu_WE = '1' then
small_page_addr <= MEMIF_FIFO_Mmu_Data;
if MEMIF_FIFO_Mmu_Data(1 downto 0) = "00" then
pgf <= '1';
state <= PAGE_FAULT;
else
ctrl_out_empty <= '0';
ctrl_out_fill <= X"0001";
ctrl_out_data <= ctrl_cmd & ctrl_length;
tlb_we <= '1';
state <= WRITE_CMD;
end if;
end if;
when WRITE_CMD =>
if CTRL_FIFO_Out_RE = '1' then
ctrl_out_fill <= X"0000";
ctrl_out_data <= physical_addr;
state <= WRITE_ADDR;
end if;
when WRITE_ADDR =>
if CTRL_FIFO_Out_RE = '1' then
ctrl_out_empty <= '1';
ctrl_out_fill <= X"0000";
state <= WAIT_REQUEST;
end if;
when PAGE_FAULT =>
pgf <= '0';
if MMU_Retry = '1' then
pgf <= '0';
state <= READ_L1_ENTRY_0;
end if;
end case;
end if;
end process mmu_proc;
tlb_tag <= ctrl_addr(31 downto 12);
tlb_di <= small_page_addr(31 downto 12);
tlb_gen : if C_TLB_SIZE > 0 generate
tlb : entity reconos_memif_mmu_zynq_v1_00_a.tlb
generic map (
C_TLB_SIZE => C_TLB_SIZE,
C_TAG_SIZE => 20,
C_DATA_SIZE => 20
)
port map (
TLB_Tag => tlb_tag,
TLB_DI => tlb_di,
TLB_DO => tlb_do,
TLB_WE => tlb_we,
TLB_Hit => tlb_hit,
TLB_Clk => clk,
TLB_Rst => rst
);
end generate;
end architecture implementation;
| gpl-2.0 |
freecores/t400 | bench/vhdl/tb_t420-c.vhd | 1 | 845 | -------------------------------------------------------------------------------
--
-- Testbench for the T420 system toplevel.
--
-- $Id: tb_t420-c.vhd,v 1.1 2006-05-15 22:21:59 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration tb_t420_behav_c0 of tb_t420 is
for behav
for t420_b: t420
use configuration work.t420_struct_c0;
end for;
for tb_elems_b: tb_elems
use configuration work.tb_elems_behav_c0;
end for;
end for;
end tb_t420_behav_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
| gpl-2.0 |
openPOWERLINK/openPOWERLINK_V2 | hardware/ipcore/common/lib/src/clkXingRtl.vhd | 3 | 8481 | -------------------------------------------------------------------------------
--! @file clkXingRtl.vhd
--
--! @brief Clock Crossing Bus converter
--
--! @details Used to transfer a faster slave interface to a slower one.
--
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! need reduce or operation
use ieee.std_logic_misc.OR_REDUCE;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
entity clkXing is
generic (
gCsNum : natural := 2;
gDataWidth : natural := 32
);
port (
iArst : in std_logic;
--fast
iFastClk : in std_logic;
iFastCs : in std_logic_vector(gCsNum-1 downto 0);
iFastRNW : in std_logic;
oFastReaddata : out std_logic_vector(gDataWidth-1 downto 0);
oFastWrAck : out std_logic;
oFastRdAck : out std_logic;
--slow
iSlowClk : in std_logic;
oSlowCs : out std_logic_vector(gCsNum-1 downto 0);
oSlowRNW : out std_logic;
iSlowReaddata : in std_logic_vector(gDataWidth-1 downto 0);
iSlowWrAck : in std_logic;
iSlowRdAck : in std_logic
);
end entity;
architecture rtl of clkXing is
--! Fsm type
type tFsm is (sIdle, sTransfer);
--! Clock domain registers
type tRegClkDomain is record
chipselect : std_logic_vector(gCsNum-1 downto 0);
rnw : std_logic;
sync : std_logic;
ack : std_logic;
fsm : tFsm;
end record;
--! Register init
constant cRegClkDomainInit : tRegClkDomain := (
chipselect => (others => cInactivated),
rnw => cInactivated,
sync => cInactivated,
ack => cInactivated,
fsm => sIdle
);
--! Slow clock domain register
signal slowClkReg : tRegClkDomain;
signal slowClkReg_next : tRegClkDomain;
--! Fast clock domain register
signal fastClkReg : tRegClkDomain;
signal fastClkReg_next : tRegClkDomain;
--! Readdata register
signal readdataReg : std_logic_vector(iSlowReaddata'range);
signal readdataReg_next : std_logic_vector(readdataReg'range);
--! Transferred sync signal (fast ---> slow)
signal tranSync_sync : std_logic;
--! Transferred ack signal (slow ---> fast)
signal tranAck_sync : std_logic;
begin
-- Map registers to outputs
-- FAST
oFastWrAck <= fastClkReg.ack and not iFastRNW;
oFastRdAck <= fastClkReg.ack and iFastRNW;
oFastReaddata <= readdataReg;
-- SLOW
oSlowCs <= slowClkReg.chipselect;
oSlowRNW <= iFastRNW;
--! Fast clock domain logic
fastComb : process (
fastClkReg,
tranAck_sync,
iFastCs, iFastRNW
)
begin
-- General defaults to avoid latches
fastClkReg_next <= fastClkReg;
-- Inactivate pulsing registers
fastClkReg_next.sync <= cInactivated;
-- Assign transferred signals
fastClkReg_next.ack <= tranAck_sync;
case fastClkReg.fsm is
when sIdle =>
if OR_REDUCE(iFastCs) = cActivated then
fastClkReg_next.fsm <= sTransfer;
fastClkReg_next.sync <= cActivated;
fastClkReg_next.chipselect <= iFastCs;
fastClkReg_next.rnw <= iFastRNW;
end if;
when sTransfer =>
if fastClkReg.ack = cActivated then
fastClkReg_next.fsm <= sIdle;
end if;
end case;
end process fastComb;
--! Slow clock domain logic
slowComb : process (
slowClkReg, fastClkReg, readdataReg,
tranSync_sync,
iSlowWrAck, iSlowRdAck, iSlowReaddata
)
begin
-- Default
slowClkReg_next <= slowClkReg;
readdataReg_next <= readdataReg;
-- Inactivate pulsing registers
slowClkReg_next.ack <= cInactivated;
-- Assign transferred signals
slowClkReg_next.sync <= tranSync_sync;
case slowClkReg.fsm is
when sIdle =>
if slowClkReg.sync = cActivated then
slowClkReg_next.fsm <= sTransfer;
end if;
when sTransfer =>
slowClkReg_next.chipselect <= fastClkReg.chipselect;
slowClkReg_next.rnw <= fastClkReg.rnw;
if iSlowRdAck = cActivated or iSlowWrAck = cActivated then
slowClkReg_next.fsm <= sIdle;
slowClkReg_next.chipselect <= (others => cInactivated);
slowClkReg_next.ack <= cActivated;
if iSlowRdAck = cActivated then
readdataReg_next <= iSlowReaddata;
end if;
end if;
end case;
end process slowComb;
--! Fast clock registers
fastClockReg : process(iArst, iFastClk)
begin
if iArst = cActivated then
fastClkReg <= cRegClkDomainInit;
elsif rising_edge(iFastClk) then
fastClkReg <= fastClkReg_next;
end if;
end process fastClockReg;
--! Slow clock registers
slowClockReg : process(iArst, iSlowClk)
begin
if iArst = cActivated then
slowClkReg <= cRegClkDomainInit;
readdataReg <= (others => cInactivated);
elsif rising_edge(iSlowClk) then
slowClkReg <= slowClkReg_next;
readdataReg <= readdataReg_next;
end if;
end process slowClockReg;
--! Transfer sync pulse to slow clock domain
tranSyncToSlow : entity libcommon.syncTog
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iSrc_rst => iArst,
iSrc_clk => iFastClk,
iSrc_data => fastClkReg.sync,
iDst_rst => iArst,
iDst_clk => iSlowClk,
oDst_data => tranSync_sync
);
--! Transfer ack pulse to fast clock domain
tranAckToFast : entity libcommon.syncTog
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iSrc_rst => iArst,
iSrc_clk => iSlowClk,
iSrc_data => slowClkReg.ack,
iDst_rst => iArst,
iDst_clk => iFastClk,
oDst_data => tranAck_sync
);
end architecture;
| gpl-2.0 |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/tracking_camera_system/testbench/tracking_camera_system_tb/simulation/submodules/tracking_camera_system_jtag_uart_0_avalon_jtag_slave_translator.vhd | 1 | 12724 | -- tracking_camera_system_jtag_uart_0_avalon_jtag_slave_translator.vhd
-- Generated using ACDS version 12.1sp1 243 at 2015.02.13.13:59:38
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tracking_camera_system_jtag_uart_0_avalon_jtag_slave_translator is
generic (
AV_ADDRESS_W : integer := 1;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 1;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 25;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(24 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(0 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_read : out std_logic; -- .read
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_waitrequest : in std_logic := '0'; -- .waitrequest
av_chipselect : out std_logic; -- .chipselect
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_byteenable : out std_logic_vector(0 downto 0);
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_readdatavalid : in std_logic := '0';
av_writebyteenable : out std_logic_vector(0 downto 0);
uav_clken : in std_logic := '0'
);
end entity tracking_camera_system_jtag_uart_0_avalon_jtag_slave_translator;
architecture rtl of tracking_camera_system_jtag_uart_0_avalon_jtag_slave_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(0 downto 0); -- address
av_write : out std_logic; -- write
av_read : out std_logic; -- read
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_chipselect : out std_logic; -- chipselect
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component altera_merlin_slave_translator;
begin
jtag_uart_0_avalon_jtag_slave_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_read => av_read, -- .read
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_waitrequest => av_waitrequest, -- .waitrequest
av_chipselect => av_chipselect, -- .chipselect
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
end architecture rtl; -- of tracking_camera_system_jtag_uart_0_avalon_jtag_slave_translator
| gpl-2.0 |
SonicFrog/ArchOrd | piso.vhdl | 1 | 916 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity PISO is
port (
Pattern : in std_logic_vector(7 downto 0);
DataIn : in std_logic;
Load : in std_logic;
Reset : in std_logic;
Clk : in std_logic;
Found : out std_logic
);
end entity; --PISO
architecture synth of piso is
signal content : std_logic_vector(7 downto 0);
signal reg_pattern : std_logic_vector(7 downto 0);
begin
load : process(Clk, Load, DataIn)
begin
if rising_edge(Clk) then
if Reset = '1' then
reg_pattern <= (others => '0')
elsif Load = '1' then
reg_pattern <= Pattern;
end if;
end if;
end process;
input_handle : process(Clk, Pattern)
begin
if rising_edge(Clk) then
content <= content(7 downto 1) & DataIn;
end if;
end process;
Found <= '1' when content = reg_pattern else '0';
end architecture ; -- synth | gpl-2.0 |
hpeng2/ECE492_Group4_Project | ECE_492_Project_new/Video_System/simulation/submodules/Video_System_CPU_jtag_debug_module_sysclk.vhd | 1 | 6915 | --Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
--use of Altera Corporation's design tools, logic functions and other
--software and tools, and its AMPP partner logic functions, and any
--output files any of the foregoing (including device programming or
--simulation files), and any associated documentation or information are
--expressly subject to the terms and conditions of the Altera Program
--License Subscription Agreement or other applicable license agreement,
--including, without limitation, that your use is for the sole purpose
--of programming logic devices manufactured by Altera and sold by Altera
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030
library altera;
use altera.altera_europa_support_lib.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Video_System_CPU_jtag_debug_module_sysclk is
port (
-- inputs:
signal clk : IN STD_LOGIC;
signal ir_in : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
signal sr : IN STD_LOGIC_VECTOR (37 DOWNTO 0);
signal vs_udr : IN STD_LOGIC;
signal vs_uir : IN STD_LOGIC;
-- outputs:
signal jdo : OUT STD_LOGIC_VECTOR (37 DOWNTO 0);
signal take_action_break_a : OUT STD_LOGIC;
signal take_action_break_b : OUT STD_LOGIC;
signal take_action_break_c : OUT STD_LOGIC;
signal take_action_ocimem_a : OUT STD_LOGIC;
signal take_action_ocimem_b : OUT STD_LOGIC;
signal take_action_tracectrl : OUT STD_LOGIC;
signal take_action_tracemem_a : OUT STD_LOGIC;
signal take_action_tracemem_b : OUT STD_LOGIC;
signal take_no_action_break_a : OUT STD_LOGIC;
signal take_no_action_break_b : OUT STD_LOGIC;
signal take_no_action_break_c : OUT STD_LOGIC;
signal take_no_action_ocimem_a : OUT STD_LOGIC;
signal take_no_action_tracemem_a : OUT STD_LOGIC
);
end entity Video_System_CPU_jtag_debug_module_sysclk;
architecture europa of Video_System_CPU_jtag_debug_module_sysclk is
component altera_std_synchronizer is
GENERIC (
depth : NATURAL
);
PORT (
signal dout : OUT STD_LOGIC;
signal clk : IN STD_LOGIC;
signal reset_n : IN STD_LOGIC;
signal din : IN STD_LOGIC
);
end component altera_std_synchronizer;
signal enable_action_strobe : STD_LOGIC;
signal internal_jdo1 : STD_LOGIC_VECTOR (37 DOWNTO 0);
signal ir : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal jxuir : STD_LOGIC;
signal sync2_udr : STD_LOGIC;
signal sync2_uir : STD_LOGIC;
signal sync_udr : STD_LOGIC;
signal sync_uir : STD_LOGIC;
signal unxunused_resetxx2 : STD_LOGIC;
signal unxunused_resetxx3 : STD_LOGIC;
signal update_jdo_strobe : STD_LOGIC;
attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of jdo : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,R101""";
attribute ALTERA_ATTRIBUTE of sync2_udr : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,D103""";
attribute ALTERA_ATTRIBUTE of sync2_uir : signal is "SUPPRESS_DA_RULE_INTERNAL=""D101,D103""";
begin
unxunused_resetxx2 <= std_logic'('1');
the_altera_std_synchronizer2 : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => clk,
din => vs_udr,
dout => sync_udr,
reset_n => unxunused_resetxx2
);
unxunused_resetxx3 <= std_logic'('1');
the_altera_std_synchronizer3 : altera_std_synchronizer
generic map(
depth => 2
)
port map(
clk => clk,
din => vs_uir,
dout => sync_uir,
reset_n => unxunused_resetxx3
);
process (clk)
begin
if clk'event and clk = '1' then
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr AND NOT sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir AND NOT sync2_uir;
end if;
end process;
take_action_ocimem_a <= ((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("00"))))) AND NOT internal_jdo1(35)) AND internal_jdo1(34);
take_no_action_ocimem_a <= ((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("00"))))) AND NOT internal_jdo1(35)) AND NOT internal_jdo1(34);
take_action_ocimem_b <= (enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("00"))))) AND internal_jdo1(35);
take_action_tracemem_a <= ((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("01"))))) AND NOT internal_jdo1(37)) AND internal_jdo1(36);
take_no_action_tracemem_a <= ((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("01"))))) AND NOT internal_jdo1(37)) AND NOT internal_jdo1(36);
take_action_tracemem_b <= (enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("01"))))) AND internal_jdo1(37);
take_action_break_a <= ((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("10"))))) AND NOT internal_jdo1(36)) AND internal_jdo1(37);
take_no_action_break_a <= ((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("10"))))) AND NOT internal_jdo1(36)) AND NOT internal_jdo1(37);
take_action_break_b <= (((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("10"))))) AND internal_jdo1(36)) AND NOT internal_jdo1(35)) AND internal_jdo1(37);
take_no_action_break_b <= (((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("10"))))) AND internal_jdo1(36)) AND NOT internal_jdo1(35)) AND NOT internal_jdo1(37);
take_action_break_c <= (((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("10"))))) AND internal_jdo1(36)) AND internal_jdo1(35)) AND internal_jdo1(37);
take_no_action_break_c <= (((enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("10"))))) AND internal_jdo1(36)) AND internal_jdo1(35)) AND NOT internal_jdo1(37);
take_action_tracectrl <= (enable_action_strobe AND to_std_logic(((ir = std_logic_vector'("11"))))) AND internal_jdo1(15);
process (clk)
begin
if clk'event and clk = '1' then
if std_logic'(jxuir) = '1' then
ir <= ir_in;
end if;
if std_logic'(update_jdo_strobe) = '1' then
internal_jdo1 <= sr;
end if;
end if;
end process;
--vhdl renameroo for output signals
jdo <= internal_jdo1;
end europa;
| gpl-2.0 |
hpeng2/ECE492_Group4_Project | Ryans_stuff/tracking_camera/tracking_camera_system/testbench/tracking_camera_system_tb/simulation/submodules/tracking_camera_system_green_leds_s1_translator.vhd | 1 | 12489 | -- tracking_camera_system_green_leds_s1_translator.vhd
-- Generated using ACDS version 12.1sp1 243 at 2015.02.13.13:59:38
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tracking_camera_system_green_leds_s1_translator is
generic (
AV_ADDRESS_W : integer := 2;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 1;
AV_BYTEENABLE_W : integer := 1;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 25;
UAV_BURSTCOUNT_W : integer := 3;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 0;
USE_WAITREQUEST : integer := 0;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 1;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := '0'; -- clk.clk
reset : in std_logic := '0'; -- reset.reset
uav_address : in std_logic_vector(24 downto 0) := (others => '0'); -- avalon_universal_slave_0.address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => '0'); -- .burstcount
uav_read : in std_logic := '0'; -- .read
uav_write : in std_logic := '0'; -- .write
uav_waitrequest : out std_logic; -- .waitrequest
uav_readdatavalid : out std_logic; -- .readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- .readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
uav_lock : in std_logic := '0'; -- .lock
uav_debugaccess : in std_logic := '0'; -- .debugaccess
av_address : out std_logic_vector(1 downto 0); -- avalon_anti_slave_0.address
av_write : out std_logic; -- .write
av_readdata : in std_logic_vector(31 downto 0) := (others => '0'); -- .readdata
av_writedata : out std_logic_vector(31 downto 0); -- .writedata
av_chipselect : out std_logic; -- .chipselect
av_beginbursttransfer : out std_logic;
av_begintransfer : out std_logic;
av_burstcount : out std_logic_vector(0 downto 0);
av_byteenable : out std_logic_vector(0 downto 0);
av_clken : out std_logic;
av_debugaccess : out std_logic;
av_lock : out std_logic;
av_outputenable : out std_logic;
av_read : out std_logic;
av_readdatavalid : in std_logic := '0';
av_waitrequest : in std_logic := '0';
av_writebyteenable : out std_logic_vector(0 downto 0);
uav_clken : in std_logic := '0'
);
end entity tracking_camera_system_green_leds_s1_translator;
architecture rtl of tracking_camera_system_green_leds_s1_translator is
component altera_merlin_slave_translator is
generic (
AV_ADDRESS_W : integer := 30;
AV_DATA_W : integer := 32;
UAV_DATA_W : integer := 32;
AV_BURSTCOUNT_W : integer := 4;
AV_BYTEENABLE_W : integer := 4;
UAV_BYTEENABLE_W : integer := 4;
UAV_ADDRESS_W : integer := 32;
UAV_BURSTCOUNT_W : integer := 4;
AV_READLATENCY : integer := 0;
USE_READDATAVALID : integer := 1;
USE_WAITREQUEST : integer := 1;
USE_UAV_CLKEN : integer := 0;
AV_SYMBOLS_PER_WORD : integer := 4;
AV_ADDRESS_SYMBOLS : integer := 0;
AV_BURSTCOUNT_SYMBOLS : integer := 0;
AV_CONSTANT_BURST_BEHAVIOR : integer := 0;
UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
CHIPSELECT_THROUGH_READLATENCY : integer := 0;
AV_READ_WAIT_CYCLES : integer := 0;
AV_WRITE_WAIT_CYCLES : integer := 0;
AV_SETUP_WAIT_CYCLES : integer := 0;
AV_DATA_HOLD_CYCLES : integer := 0
);
port (
clk : in std_logic := 'X'; -- clk
reset : in std_logic := 'X'; -- reset
uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address
uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount
uav_read : in std_logic := 'X'; -- read
uav_write : in std_logic := 'X'; -- write
uav_waitrequest : out std_logic; -- waitrequest
uav_readdatavalid : out std_logic; -- readdatavalid
uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
uav_readdata : out std_logic_vector(31 downto 0); -- readdata
uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
uav_lock : in std_logic := 'X'; -- lock
uav_debugaccess : in std_logic := 'X'; -- debugaccess
av_address : out std_logic_vector(1 downto 0); -- address
av_write : out std_logic; -- write
av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
av_writedata : out std_logic_vector(31 downto 0); -- writedata
av_chipselect : out std_logic; -- chipselect
av_read : out std_logic; -- read
av_begintransfer : out std_logic; -- begintransfer
av_beginbursttransfer : out std_logic; -- beginbursttransfer
av_burstcount : out std_logic_vector(0 downto 0); -- burstcount
av_byteenable : out std_logic_vector(0 downto 0); -- byteenable
av_readdatavalid : in std_logic := 'X'; -- readdatavalid
av_waitrequest : in std_logic := 'X'; -- waitrequest
av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable
av_lock : out std_logic; -- lock
av_clken : out std_logic; -- clken
uav_clken : in std_logic := 'X'; -- clken
av_debugaccess : out std_logic; -- debugaccess
av_outputenable : out std_logic -- outputenable
);
end component altera_merlin_slave_translator;
begin
green_leds_s1_translator : component altera_merlin_slave_translator
generic map (
AV_ADDRESS_W => AV_ADDRESS_W,
AV_DATA_W => AV_DATA_W,
UAV_DATA_W => UAV_DATA_W,
AV_BURSTCOUNT_W => AV_BURSTCOUNT_W,
AV_BYTEENABLE_W => AV_BYTEENABLE_W,
UAV_BYTEENABLE_W => UAV_BYTEENABLE_W,
UAV_ADDRESS_W => UAV_ADDRESS_W,
UAV_BURSTCOUNT_W => UAV_BURSTCOUNT_W,
AV_READLATENCY => AV_READLATENCY,
USE_READDATAVALID => USE_READDATAVALID,
USE_WAITREQUEST => USE_WAITREQUEST,
USE_UAV_CLKEN => USE_UAV_CLKEN,
AV_SYMBOLS_PER_WORD => AV_SYMBOLS_PER_WORD,
AV_ADDRESS_SYMBOLS => AV_ADDRESS_SYMBOLS,
AV_BURSTCOUNT_SYMBOLS => AV_BURSTCOUNT_SYMBOLS,
AV_CONSTANT_BURST_BEHAVIOR => AV_CONSTANT_BURST_BEHAVIOR,
UAV_CONSTANT_BURST_BEHAVIOR => UAV_CONSTANT_BURST_BEHAVIOR,
AV_REQUIRE_UNALIGNED_ADDRESSES => AV_REQUIRE_UNALIGNED_ADDRESSES,
CHIPSELECT_THROUGH_READLATENCY => CHIPSELECT_THROUGH_READLATENCY,
AV_READ_WAIT_CYCLES => AV_READ_WAIT_CYCLES,
AV_WRITE_WAIT_CYCLES => AV_WRITE_WAIT_CYCLES,
AV_SETUP_WAIT_CYCLES => AV_SETUP_WAIT_CYCLES,
AV_DATA_HOLD_CYCLES => AV_DATA_HOLD_CYCLES
)
port map (
clk => clk, -- clk.clk
reset => reset, -- reset.reset
uav_address => uav_address, -- avalon_universal_slave_0.address
uav_burstcount => uav_burstcount, -- .burstcount
uav_read => uav_read, -- .read
uav_write => uav_write, -- .write
uav_waitrequest => uav_waitrequest, -- .waitrequest
uav_readdatavalid => uav_readdatavalid, -- .readdatavalid
uav_byteenable => uav_byteenable, -- .byteenable
uav_readdata => uav_readdata, -- .readdata
uav_writedata => uav_writedata, -- .writedata
uav_lock => uav_lock, -- .lock
uav_debugaccess => uav_debugaccess, -- .debugaccess
av_address => av_address, -- avalon_anti_slave_0.address
av_write => av_write, -- .write
av_readdata => av_readdata, -- .readdata
av_writedata => av_writedata, -- .writedata
av_chipselect => av_chipselect, -- .chipselect
av_read => open, -- (terminated)
av_begintransfer => open, -- (terminated)
av_beginbursttransfer => open, -- (terminated)
av_burstcount => open, -- (terminated)
av_byteenable => open, -- (terminated)
av_readdatavalid => '0', -- (terminated)
av_waitrequest => '0', -- (terminated)
av_writebyteenable => open, -- (terminated)
av_lock => open, -- (terminated)
av_clken => open, -- (terminated)
uav_clken => '0', -- (terminated)
av_debugaccess => open, -- (terminated)
av_outputenable => open -- (terminated)
);
end architecture rtl; -- of tracking_camera_system_green_leds_s1_translator
| gpl-2.0 |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/Source/IP/FIR/FIR_sim/FIR_rtl.vhd | 1 | 46601 | -----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.0sp1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from FIR_rtl
-- VHDL created on Wed Oct 21 00:24:41 2015
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
-- Text written from d:/SJ/nightly/13.0sp1/232/w32/p4/ip/aion/src/mip_common/hw_model.cpp:1303
entity FIR_rtl is
port (
xIn_v : in std_logic_vector(0 downto 0);
xIn_c : in std_logic_vector(7 downto 0);
xIn_0 : in std_logic_vector(12 downto 0);
bankIn_0 : in std_logic_vector(2 downto 0);
xOut_v : out std_logic_vector(0 downto 0);
xOut_c : out std_logic_vector(7 downto 0);
xOut_0 : out std_logic_vector(29 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of FIR_rtl is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal d_xIn_bankIn_0_12_q : std_logic_vector (2 downto 0);
signal d_xIn_0_12_q : std_logic_vector (12 downto 0);
signal d_in0_m0_wi0_wo0_assign_data_q_13_q : std_logic_vector (15 downto 0);
signal d_in0_m0_wi0_wo0_assign_sel_q_12_q : std_logic_vector (0 downto 0);
signal d_in0_m0_wi0_wo0_assign_sel_q_13_q : std_logic_vector (0 downto 0);
signal u0_m0_wo0_run_count : std_logic_vector(1 downto 0);
signal u0_m0_wo0_run_pre_ena_q : std_logic_vector (0 downto 0);
signal u0_m0_wo0_run_q : std_logic_vector (0 downto 0);
signal u0_m0_wo0_run_out : std_logic_vector (0 downto 0);
signal u0_m0_wo0_run_enable_q : std_logic_vector (0 downto 0);
signal u0_m0_wo0_run_ctrl : std_logic_vector(2 downto 0);
signal u0_m0_wo0_memread_q : std_logic_vector (0 downto 0);
signal u0_m0_wo0_compute_q : std_logic_vector (0 downto 0);
signal d_u0_m0_wo0_compute_q_14_q : std_logic_vector (0 downto 0);
signal d_u0_m0_wo0_compute_q_15_q : std_logic_vector (0 downto 0);
signal u0_m0_wo0_wi0_ra0_count0_q : std_logic_vector(7 downto 0);
signal u0_m0_wo0_wi0_ra0_count0_i : unsigned(6 downto 0);
signal u0_m0_wo0_wi0_ra0_count0_sc : signed(6 downto 0);
signal u0_m0_wo0_wi0_ra0_count1_q : std_logic_vector(7 downto 0);
signal u0_m0_wo0_wi0_ra0_count1_i : unsigned(6 downto 0);
signal u0_m0_wo0_wi0_ra0_add_0_0_a : std_logic_vector(8 downto 0);
signal u0_m0_wo0_wi0_ra0_add_0_0_b : std_logic_vector(8 downto 0);
signal u0_m0_wo0_wi0_ra0_add_0_0_o : std_logic_vector (8 downto 0);
signal u0_m0_wo0_wi0_ra0_add_0_0_q : std_logic_vector (8 downto 0);
signal u0_m0_wo0_wi0_wa0_q : std_logic_vector(6 downto 0);
signal u0_m0_wo0_wi0_wa0_i : unsigned(6 downto 0);
signal u0_m0_wo0_wi0_delayr0_reset0 : std_logic;
signal u0_m0_wo0_wi0_delayr0_ia : std_logic_vector (12 downto 0);
signal u0_m0_wo0_wi0_delayr0_aa : std_logic_vector (6 downto 0);
signal u0_m0_wo0_wi0_delayr0_ab : std_logic_vector (6 downto 0);
signal u0_m0_wo0_wi0_delayr0_iq : std_logic_vector (12 downto 0);
signal u0_m0_wo0_wi0_delayr0_q : std_logic_vector (12 downto 0);
signal u0_m0_wo0_bank_delayr0_reset0 : std_logic;
signal u0_m0_wo0_bank_delayr0_ia : std_logic_vector (2 downto 0);
signal u0_m0_wo0_bank_delayr0_aa : std_logic_vector (0 downto 0);
signal u0_m0_wo0_bank_delayr0_ab : std_logic_vector (0 downto 0);
signal u0_m0_wo0_bank_delayr0_iq : std_logic_vector (2 downto 0);
signal u0_m0_wo0_bank_delayr0_q : std_logic_vector (2 downto 0);
signal u0_m0_wo0_ca0_q : std_logic_vector(6 downto 0);
signal u0_m0_wo0_ca0_i : unsigned(6 downto 0);
signal u0_m0_wo0_ca0_eq : std_logic;
signal u0_m0_wo0_cm0_q : std_logic_vector(9 downto 0);
signal u0_m0_wo0_mtree_mult1_0_a : std_logic_vector (9 downto 0);
signal u0_m0_wo0_mtree_mult1_0_b : std_logic_vector (12 downto 0);
signal u0_m0_wo0_mtree_mult1_0_s1 : std_logic_vector (22 downto 0);
signal u0_m0_wo0_mtree_mult1_0_reset : std_logic;
signal u0_m0_wo0_mtree_mult1_0_q : std_logic_vector (22 downto 0);
signal u0_m0_wo0_aseq_q : std_logic_vector(0 downto 0);
signal u0_m0_wo0_aseq_eq : std_logic;
signal u0_m0_wo0_accum_a : std_logic_vector(29 downto 0);
signal u0_m0_wo0_accum_b : std_logic_vector(29 downto 0);
signal u0_m0_wo0_accum_i : std_logic_vector (29 downto 0);
signal u0_m0_wo0_accum_o : std_logic_vector (29 downto 0);
signal u0_m0_wo0_accum_q : std_logic_vector (29 downto 0);
signal u0_m0_wo0_oseq_q : std_logic_vector(0 downto 0);
signal u0_m0_wo0_oseq_eq : std_logic;
signal u0_m0_wo0_oseq_gated_reg_q : std_logic_vector (0 downto 0);
signal xIn_bankIn_0_q : std_logic_vector (15 downto 0);
signal data_u0_m0_wi0_wo0_in : std_logic_vector (12 downto 0);
signal data_u0_m0_wi0_wo0_b : std_logic_vector (12 downto 0);
signal u0_m0_wo0_oseq_gated_a : std_logic_vector(0 downto 0);
signal u0_m0_wo0_oseq_gated_b : std_logic_vector(0 downto 0);
signal u0_m0_wo0_oseq_gated_q : std_logic_vector(0 downto 0);
signal u0_m0_wo0_wi0_ra0_resize_in : std_logic_vector (6 downto 0);
signal u0_m0_wo0_wi0_ra0_resize_b : std_logic_vector (6 downto 0);
signal u0_m0_wo0_cab0_q : std_logic_vector (9 downto 0);
signal bank_u0_m0_wi0_wo0_in : std_logic_vector (15 downto 0);
signal bank_u0_m0_wi0_wo0_b : std_logic_vector (2 downto 0);
begin
--VCC(CONSTANT,1)@0
VCC_q <= "1";
--xIn(PORTIN,2)@10
--u0_m0_wo0_run(ENABLEGENERATOR,8)@10
u0_m0_wo0_run_ctrl <= u0_m0_wo0_run_out & xIn_v & u0_m0_wo0_run_enable_q;
u0_m0_wo0_run: PROCESS (clk, areset)
variable u0_m0_wo0_run_enable_c : signed(6 downto 0);
variable u0_m0_wo0_run_inc : signed(1 downto 0);
BEGIN
IF (areset = '1') THEN
u0_m0_wo0_run_q <= "0";
u0_m0_wo0_run_enable_c := TO_SIGNED(63,7);
u0_m0_wo0_run_enable_q <= "0";
u0_m0_wo0_run_count <= "00";
u0_m0_wo0_run_inc := (OTHERS => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (u0_m0_wo0_run_out = "1") THEN
IF (u0_m0_wo0_run_enable_c(6) = '1') THEN
u0_m0_wo0_run_enable_c := u0_m0_wo0_run_enable_c - (-64);
ELSE
u0_m0_wo0_run_enable_c := u0_m0_wo0_run_enable_c + (-1);
END IF;
u0_m0_wo0_run_enable_q <= STD_LOGIC_VECTOR(u0_m0_wo0_run_enable_c(6 DOWNTO 6));
ELSE
u0_m0_wo0_run_enable_q <= "0";
END IF;
CASE u0_m0_wo0_run_ctrl is
WHEN "000" | "001" =>
u0_m0_wo0_run_inc := "00";
WHEN "010" | "011" =>
u0_m0_wo0_run_inc := "11";
WHEN "100" =>
u0_m0_wo0_run_inc := "00";
WHEN "101" =>
u0_m0_wo0_run_inc := "01";
WHEN "110" =>
u0_m0_wo0_run_inc := "11";
WHEN "111" =>
u0_m0_wo0_run_inc := "00";
WHEN OTHERS =>
END CASE;
u0_m0_wo0_run_count <= STD_LOGIC_VECTOR(SIGNED(u0_m0_wo0_run_count) + SIGNED(u0_m0_wo0_run_inc));
u0_m0_wo0_run_q <= u0_m0_wo0_run_out;
END IF;
END PROCESS;
u0_m0_wo0_run_pre_ena_q <= u0_m0_wo0_run_count(1 downto 1);
u0_m0_wo0_run_out <= u0_m0_wo0_run_pre_ena_q AND VCC_q;
--u0_m0_wo0_memread(DELAY,9)@12
u0_m0_wo0_memread : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => u0_m0_wo0_run_q, xout => u0_m0_wo0_memread_q, clk => clk, aclr => areset );
--u0_m0_wo0_compute(DELAY,10)@12
u0_m0_wo0_compute : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => u0_m0_wo0_memread_q, xout => u0_m0_wo0_compute_q, clk => clk, aclr => areset );
--d_u0_m0_wo0_compute_q_14(DELAY,39)@12
d_u0_m0_wo0_compute_q_14 : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => u0_m0_wo0_compute_q, xout => d_u0_m0_wo0_compute_q_14_q, clk => clk, aclr => areset );
--u0_m0_wo0_aseq(SEQUENCE,25)@14
u0_m0_wo0_aseq: PROCESS (clk, areset)
variable u0_m0_wo0_aseq_c : signed (8 downto 0);
BEGIN
IF (areset = '1') THEN
u0_m0_wo0_aseq_c := "000000000";
u0_m0_wo0_aseq_q <= "0";
u0_m0_wo0_aseq_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (d_u0_m0_wo0_compute_q_14_q = "1") THEN
IF (u0_m0_wo0_aseq_c = "000000000") THEN
u0_m0_wo0_aseq_eq <= '1';
ELSE
u0_m0_wo0_aseq_eq <= '0';
END IF;
IF (u0_m0_wo0_aseq_eq = '1') THEN
u0_m0_wo0_aseq_c := u0_m0_wo0_aseq_c + 64;
ELSE
u0_m0_wo0_aseq_c := u0_m0_wo0_aseq_c - 1;
END IF;
u0_m0_wo0_aseq_q <= std_logic_vector(u0_m0_wo0_aseq_c(8 DOWNTO 8));
END IF;
END IF;
END PROCESS;
--d_u0_m0_wo0_compute_q_15(DELAY,40)@14
d_u0_m0_wo0_compute_q_15 : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => d_u0_m0_wo0_compute_q_14_q, xout => d_u0_m0_wo0_compute_q_15_q, clk => clk, aclr => areset );
--d_xIn_bankIn_0_12(DELAY,35)@10
d_xIn_bankIn_0_12 : dspba_delay
GENERIC MAP ( width => 3, depth => 2 )
PORT MAP ( xin => bankIn_0, xout => d_xIn_bankIn_0_12_q, clk => clk, aclr => areset );
--d_xIn_0_12(DELAY,34)@10
d_xIn_0_12 : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => xIn_0, xout => d_xIn_0_12_q, clk => clk, aclr => areset );
--xIn_bankIn_0(BITJOIN,3)@12
xIn_bankIn_0_q <= d_xIn_bankIn_0_12_q & d_xIn_0_12_q;
--d_in0_m0_wi0_wo0_assign_data_q_13(DELAY,36)@12
d_in0_m0_wi0_wo0_assign_data_q_13 : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => xIn_bankIn_0_q, xout => d_in0_m0_wi0_wo0_assign_data_q_13_q, clk => clk, aclr => areset );
--data_u0_m0_wi0_wo0(BITSELECT,7)@13
data_u0_m0_wi0_wo0_in <= d_in0_m0_wi0_wo0_assign_data_q_13_q(12 downto 0);
data_u0_m0_wi0_wo0_b <= data_u0_m0_wi0_wo0_in(12 downto 0);
--u0_m0_wo0_wi0_wa0(COUNTER,15)@13
-- every=1, low=0, high=127, step=1, init=1
u0_m0_wo0_wi0_wa0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
u0_m0_wo0_wi0_wa0_i <= TO_UNSIGNED(1,7);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (d_in0_m0_wi0_wo0_assign_sel_q_13_q = "1") THEN
u0_m0_wo0_wi0_wa0_i <= u0_m0_wo0_wi0_wa0_i + 1;
END IF;
END IF;
END PROCESS;
u0_m0_wo0_wi0_wa0_q <= STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_wi0_wa0_i,7));
--d_in0_m0_wi0_wo0_assign_sel_q_12(DELAY,37)@10
d_in0_m0_wi0_wo0_assign_sel_q_12 : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => xIn_v, xout => d_in0_m0_wi0_wo0_assign_sel_q_12_q, clk => clk, aclr => areset );
--d_in0_m0_wi0_wo0_assign_sel_q_13(DELAY,38)@12
d_in0_m0_wi0_wo0_assign_sel_q_13 : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => d_in0_m0_wi0_wo0_assign_sel_q_12_q, xout => d_in0_m0_wi0_wo0_assign_sel_q_13_q, clk => clk, aclr => areset );
--u0_m0_wo0_wi0_ra0_count1(COUNTER,12)@12
-- every=1, low=0, high=127, step=1, init=0
u0_m0_wo0_wi0_ra0_count1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
u0_m0_wo0_wi0_ra0_count1_i <= TO_UNSIGNED(0,7);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (u0_m0_wo0_memread_q = "1") THEN
u0_m0_wo0_wi0_ra0_count1_i <= u0_m0_wo0_wi0_ra0_count1_i + 1;
END IF;
END IF;
END PROCESS;
u0_m0_wo0_wi0_ra0_count1_q <= STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_wi0_ra0_count1_i,8));
--u0_m0_wo0_wi0_ra0_count0(COUNTER,11)@12
-- every=65, low=0, high=127, step=64, init=65
u0_m0_wo0_wi0_ra0_count0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
u0_m0_wo0_wi0_ra0_count0_i <= TO_UNSIGNED(65,7);
u0_m0_wo0_wi0_ra0_count0_sc <= TO_SIGNED(63,7);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (u0_m0_wo0_memread_q = "1") THEN
IF (u0_m0_wo0_wi0_ra0_count0_sc(6) = '1') THEN
u0_m0_wo0_wi0_ra0_count0_sc <= u0_m0_wo0_wi0_ra0_count0_sc - (-64);
ELSE
u0_m0_wo0_wi0_ra0_count0_sc <= u0_m0_wo0_wi0_ra0_count0_sc + (-1);
END IF;
IF (u0_m0_wo0_wi0_ra0_count0_sc(6) = '1') THEN
u0_m0_wo0_wi0_ra0_count0_i <= u0_m0_wo0_wi0_ra0_count0_i + 64;
END IF;
END IF;
END IF;
END PROCESS;
u0_m0_wo0_wi0_ra0_count0_q <= STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_wi0_ra0_count0_i,8));
--u0_m0_wo0_wi0_ra0_add_0_0(ADD,13)@12
u0_m0_wo0_wi0_ra0_add_0_0_a <= STD_LOGIC_VECTOR("0" & u0_m0_wo0_wi0_ra0_count0_q);
u0_m0_wo0_wi0_ra0_add_0_0_b <= STD_LOGIC_VECTOR("0" & u0_m0_wo0_wi0_ra0_count1_q);
u0_m0_wo0_wi0_ra0_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
u0_m0_wo0_wi0_ra0_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
u0_m0_wo0_wi0_ra0_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(u0_m0_wo0_wi0_ra0_add_0_0_a) + UNSIGNED(u0_m0_wo0_wi0_ra0_add_0_0_b));
END IF;
END PROCESS;
u0_m0_wo0_wi0_ra0_add_0_0_q <= u0_m0_wo0_wi0_ra0_add_0_0_o(8 downto 0);
--u0_m0_wo0_wi0_ra0_resize(BITSELECT,14)@13
u0_m0_wo0_wi0_ra0_resize_in <= u0_m0_wo0_wi0_ra0_add_0_0_q(6 downto 0);
u0_m0_wo0_wi0_ra0_resize_b <= u0_m0_wo0_wi0_ra0_resize_in(6 downto 0);
--u0_m0_wo0_wi0_delayr0(DUALMEM,16)@13
u0_m0_wo0_wi0_delayr0_ia <= data_u0_m0_wi0_wo0_b;
u0_m0_wo0_wi0_delayr0_aa <= u0_m0_wo0_wi0_wa0_q;
u0_m0_wo0_wi0_delayr0_ab <= u0_m0_wo0_wi0_ra0_resize_b;
u0_m0_wo0_wi0_delayr0_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M4K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 7,
numwords_a => 128,
width_b => 13,
widthad_b => 7,
numwords_b => 128,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "OLD_DATA",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Cyclone II"
)
PORT MAP (
clocken0 => '1',
wren_a => d_in0_m0_wi0_wo0_assign_sel_q_13_q(0),
aclr0 => u0_m0_wo0_wi0_delayr0_reset0,
clock0 => clk,
address_b => u0_m0_wo0_wi0_delayr0_ab,
-- data_b => (others => '0'),
q_b => u0_m0_wo0_wi0_delayr0_iq,
address_a => u0_m0_wo0_wi0_delayr0_aa,
data_a => u0_m0_wo0_wi0_delayr0_ia
);
u0_m0_wo0_wi0_delayr0_reset0 <= areset;
u0_m0_wo0_wi0_delayr0_q <= u0_m0_wo0_wi0_delayr0_iq(12 downto 0);
--bank_u0_m0_wi0_wo0(BITSELECT,6)@12
bank_u0_m0_wi0_wo0_in <= xIn_bankIn_0_q;
bank_u0_m0_wi0_wo0_b <= bank_u0_m0_wi0_wo0_in(15 downto 13);
--u0_m0_wo0_bank_delayr0(DUALMEM,19)@12
u0_m0_wo0_bank_delayr0_ia <= bank_u0_m0_wi0_wo0_b;
u0_m0_wo0_bank_delayr0_aa <= GND_q;
u0_m0_wo0_bank_delayr0_ab <= GND_q;
u0_m0_wo0_bank_delayr0_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M4K",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 1,
numwords_a => 2,
width_b => 3,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "OLD_DATA",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Cyclone II"
)
PORT MAP (
clocken0 => '1',
wren_a => d_in0_m0_wi0_wo0_assign_sel_q_12_q(0),
aclr0 => u0_m0_wo0_bank_delayr0_reset0,
clock0 => clk,
address_b => u0_m0_wo0_bank_delayr0_ab,
-- data_b => (others => '0'),
q_b => u0_m0_wo0_bank_delayr0_iq,
address_a => u0_m0_wo0_bank_delayr0_aa,
data_a => u0_m0_wo0_bank_delayr0_ia
);
u0_m0_wo0_bank_delayr0_reset0 <= areset;
u0_m0_wo0_bank_delayr0_q <= u0_m0_wo0_bank_delayr0_iq(2 downto 0);
--u0_m0_wo0_ca0(COUNTER,21)@12
-- every=1, low=0, high=64, step=1, init=0
u0_m0_wo0_ca0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
u0_m0_wo0_ca0_i <= TO_UNSIGNED(0,7);
u0_m0_wo0_ca0_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (u0_m0_wo0_compute_q = "1") THEN
IF u0_m0_wo0_ca0_i = 63 THEN
u0_m0_wo0_ca0_eq <= '1';
ELSE
u0_m0_wo0_ca0_eq <= '0';
END IF;
IF (u0_m0_wo0_ca0_eq = '1') THEN
u0_m0_wo0_ca0_i <= u0_m0_wo0_ca0_i - 64;
ELSE
u0_m0_wo0_ca0_i <= u0_m0_wo0_ca0_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
u0_m0_wo0_ca0_q <= STD_LOGIC_VECTOR(RESIZE(u0_m0_wo0_ca0_i,7));
--u0_m0_wo0_cab0(BITJOIN,22)@12
u0_m0_wo0_cab0_q <= u0_m0_wo0_bank_delayr0_q & u0_m0_wo0_ca0_q;
--u0_m0_wo0_cm0(LOOKUP,23)@12
u0_m0_wo0_cm0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
u0_m0_wo0_cm0_q <= "0000000011";
ELSIF rising_edge(clk) THEN CASE (u0_m0_wo0_cab0_q) IS
WHEN "0000000000" => u0_m0_wo0_cm0_q <= "0000000011";
WHEN "0000000001" => u0_m0_wo0_cm0_q <= "0000001001";
WHEN "0000000010" => u0_m0_wo0_cm0_q <= "0000001001";
WHEN "0000000011" => u0_m0_wo0_cm0_q <= "0000001011";
WHEN "0000000100" => u0_m0_wo0_cm0_q <= "1111100001";
WHEN "0000000101" => u0_m0_wo0_cm0_q <= "1111001111";
WHEN "0000000110" => u0_m0_wo0_cm0_q <= "1111100000";
WHEN "0000000111" => u0_m0_wo0_cm0_q <= "0000001111";
WHEN "0000001000" => u0_m0_wo0_cm0_q <= "0001010000";
WHEN "0000001001" => u0_m0_wo0_cm0_q <= "0001010011";
WHEN "0000001010" => u0_m0_wo0_cm0_q <= "0000100010";
WHEN "0000001011" => u0_m0_wo0_cm0_q <= "1110110011";
WHEN "0000001100" => u0_m0_wo0_cm0_q <= "1110001100";
WHEN "0000001101" => u0_m0_wo0_cm0_q <= "1110011001";
WHEN "0000001110" => u0_m0_wo0_cm0_q <= "0000110001";
WHEN "0000001111" => u0_m0_wo0_cm0_q <= "0010001001";
WHEN "0000010000" => u0_m0_wo0_cm0_q <= "0010000001";
WHEN "0000010001" => u0_m0_wo0_cm0_q <= "0000100110";
WHEN "0000010010" => u0_m0_wo0_cm0_q <= "1110000000";
WHEN "0000010011" => u0_m0_wo0_cm0_q <= "1101001100";
WHEN "0000010100" => u0_m0_wo0_cm0_q <= "1101110010";
WHEN "0000010101" => u0_m0_wo0_cm0_q <= "0001010110";
WHEN "0000010110" => u0_m0_wo0_cm0_q <= "0011010011";
WHEN "0000010111" => u0_m0_wo0_cm0_q <= "0011000001";
WHEN "0000011000" => u0_m0_wo0_cm0_q <= "0000100110";
WHEN "0000011001" => u0_m0_wo0_cm0_q <= "1100111100";
WHEN "0000011010" => u0_m0_wo0_cm0_q <= "1011111011";
WHEN "0000011011" => u0_m0_wo0_cm0_q <= "1100101101";
WHEN "0000011100" => u0_m0_wo0_cm0_q <= "0001110100";
WHEN "0000011101" => u0_m0_wo0_cm0_q <= "0100100111";
WHEN "0000011110" => u0_m0_wo0_cm0_q <= "0100000111";
WHEN "0000011111" => u0_m0_wo0_cm0_q <= "0000011000";
WHEN "0000100000" => u0_m0_wo0_cm0_q <= "1011111100";
WHEN "0000100001" => u0_m0_wo0_cm0_q <= "1010110100";
WHEN "0000100010" => u0_m0_wo0_cm0_q <= "1100010000";
WHEN "0000100011" => u0_m0_wo0_cm0_q <= "0010100000";
WHEN "0000100100" => u0_m0_wo0_cm0_q <= "0101101100";
WHEN "0000100101" => u0_m0_wo0_cm0_q <= "0100111110";
WHEN "0000100110" => u0_m0_wo0_cm0_q <= "0000011111";
WHEN "0000100111" => u0_m0_wo0_cm0_q <= "1010111110";
WHEN "0000101000" => u0_m0_wo0_cm0_q <= "1001101100";
WHEN "0000101001" => u0_m0_wo0_cm0_q <= "1100001000";
WHEN "0000101010" => u0_m0_wo0_cm0_q <= "0011001101";
WHEN "0000101011" => u0_m0_wo0_cm0_q <= "0110100111";
WHEN "0000101100" => u0_m0_wo0_cm0_q <= "0101101010";
WHEN "0000101101" => u0_m0_wo0_cm0_q <= "0000010111";
WHEN "0000101110" => u0_m0_wo0_cm0_q <= "1010001100";
WHEN "0000101111" => u0_m0_wo0_cm0_q <= "1000110111";
WHEN "0000110000" => u0_m0_wo0_cm0_q <= "1011111100";
WHEN "0000110001" => u0_m0_wo0_cm0_q <= "0011101011";
WHEN "0000110010" => u0_m0_wo0_cm0_q <= "0111001110";
WHEN "0000110011" => u0_m0_wo0_cm0_q <= "0110001000";
WHEN "0000110100" => u0_m0_wo0_cm0_q <= "0000000110";
WHEN "0000110101" => u0_m0_wo0_cm0_q <= "1001101010";
WHEN "0000110110" => u0_m0_wo0_cm0_q <= "1000100000";
WHEN "0000110111" => u0_m0_wo0_cm0_q <= "1011101001";
WHEN "0000111000" => u0_m0_wo0_cm0_q <= "0100000111";
WHEN "0000111001" => u0_m0_wo0_cm0_q <= "0111111001";
WHEN "0000111010" => u0_m0_wo0_cm0_q <= "0110010011";
WHEN "0000111011" => u0_m0_wo0_cm0_q <= "1111010001";
WHEN "0000111100" => u0_m0_wo0_cm0_q <= "1001010100";
WHEN "0000111101" => u0_m0_wo0_cm0_q <= "1000011001";
WHEN "0000111110" => u0_m0_wo0_cm0_q <= "1100010010";
WHEN "0000111111" => u0_m0_wo0_cm0_q <= "0100101000";
WHEN "0001000000" => u0_m0_wo0_cm0_q <= "0111111111";
WHEN "0010000000" => u0_m0_wo0_cm0_q <= "0000010010";
WHEN "0010000001" => u0_m0_wo0_cm0_q <= "0000001000";
WHEN "0010000010" => u0_m0_wo0_cm0_q <= "0000000011";
WHEN "0010000011" => u0_m0_wo0_cm0_q <= "1111100101";
WHEN "0010000100" => u0_m0_wo0_cm0_q <= "1111010011";
WHEN "0010000101" => u0_m0_wo0_cm0_q <= "1111010011";
WHEN "0010000110" => u0_m0_wo0_cm0_q <= "1111010110";
WHEN "0010000111" => u0_m0_wo0_cm0_q <= "0000011101";
WHEN "0010001000" => u0_m0_wo0_cm0_q <= "0001000101";
WHEN "0010001001" => u0_m0_wo0_cm0_q <= "0000111010";
WHEN "0010001010" => u0_m0_wo0_cm0_q <= "0000000011";
WHEN "0010001011" => u0_m0_wo0_cm0_q <= "1110100100";
WHEN "0010001100" => u0_m0_wo0_cm0_q <= "1110001101";
WHEN "0010001101" => u0_m0_wo0_cm0_q <= "1110101000";
WHEN "0010001110" => u0_m0_wo0_cm0_q <= "0000111111";
WHEN "0010001111" => u0_m0_wo0_cm0_q <= "0010001100";
WHEN "0010010000" => u0_m0_wo0_cm0_q <= "0010110111";
WHEN "0010010001" => u0_m0_wo0_cm0_q <= "1111110000";
WHEN "0010010010" => u0_m0_wo0_cm0_q <= "1101011101";
WHEN "0010010011" => u0_m0_wo0_cm0_q <= "1101000110";
WHEN "0010010100" => u0_m0_wo0_cm0_q <= "1110001100";
WHEN "0010010101" => u0_m0_wo0_cm0_q <= "0001110111";
WHEN "0010010110" => u0_m0_wo0_cm0_q <= "0011100010";
WHEN "0010010111" => u0_m0_wo0_cm0_q <= "0010101011";
WHEN "0010011000" => u0_m0_wo0_cm0_q <= "1111011000";
WHEN "0010011001" => u0_m0_wo0_cm0_q <= "1100000101";
WHEN "0010011010" => u0_m0_wo0_cm0_q <= "1011101111";
WHEN "0010011011" => u0_m0_wo0_cm0_q <= "1110001001";
WHEN "0010011100" => u0_m0_wo0_cm0_q <= "0011000000";
WHEN "0010011101" => u0_m0_wo0_cm0_q <= "0100111010";
WHEN "0010011110" => u0_m0_wo0_cm0_q <= "0011100100";
WHEN "0010011111" => u0_m0_wo0_cm0_q <= "1110111111";
WHEN "0010100000" => u0_m0_wo0_cm0_q <= "1010110010";
WHEN "0010100001" => u0_m0_wo0_cm0_q <= "1010011111";
WHEN "0010100010" => u0_m0_wo0_cm0_q <= "1101111000";
WHEN "0010100011" => u0_m0_wo0_cm0_q <= "0011110111";
WHEN "0010100100" => u0_m0_wo0_cm0_q <= "0110001000";
WHEN "0010100101" => u0_m0_wo0_cm0_q <= "0100011011";
WHEN "0010100110" => u0_m0_wo0_cm0_q <= "1110101010";
WHEN "0010100111" => u0_m0_wo0_cm0_q <= "1001110010";
WHEN "0010101000" => u0_m0_wo0_cm0_q <= "1001100010";
WHEN "0010101001" => u0_m0_wo0_cm0_q <= "1101011001";
WHEN "0010101010" => u0_m0_wo0_cm0_q <= "0100100101";
WHEN "0010101011" => u0_m0_wo0_cm0_q <= "0111001111";
WHEN "0010101100" => u0_m0_wo0_cm0_q <= "0110011000";
WHEN "0010101101" => u0_m0_wo0_cm0_q <= "1110000010";
WHEN "0010101110" => u0_m0_wo0_cm0_q <= "1001000011";
WHEN "0010101111" => u0_m0_wo0_cm0_q <= "1000111001";
WHEN "0010110000" => u0_m0_wo0_cm0_q <= "1101010101";
WHEN "0010110001" => u0_m0_wo0_cm0_q <= "0101000110";
WHEN "0010110010" => u0_m0_wo0_cm0_q <= "0111110110";
WHEN "0010110011" => u0_m0_wo0_cm0_q <= "0111001010";
WHEN "0010110100" => u0_m0_wo0_cm0_q <= "1101111011";
WHEN "0010110101" => u0_m0_wo0_cm0_q <= "1000011001";
WHEN "0010110110" => u0_m0_wo0_cm0_q <= "1000011100";
WHEN "0010110111" => u0_m0_wo0_cm0_q <= "1101111011";
WHEN "0010111000" => u0_m0_wo0_cm0_q <= "0101011101";
WHEN "0010111001" => u0_m0_wo0_cm0_q <= "0111111110";
WHEN "0010111010" => u0_m0_wo0_cm0_q <= "0101010011";
WHEN "0010111011" => u0_m0_wo0_cm0_q <= "1101100010";
WHEN "0010111100" => u0_m0_wo0_cm0_q <= "1000010110";
WHEN "0010111101" => u0_m0_wo0_cm0_q <= "1000100011";
WHEN "0010111110" => u0_m0_wo0_cm0_q <= "1110010010";
WHEN "0010111111" => u0_m0_wo0_cm0_q <= "0101011110";
WHEN "0011000000" => u0_m0_wo0_cm0_q <= "0111101101";
WHEN "0100000000" => u0_m0_wo0_cm0_q <= "1111101100";
WHEN "0100000001" => u0_m0_wo0_cm0_q <= "1111111110";
WHEN "0100000010" => u0_m0_wo0_cm0_q <= "0000011110";
WHEN "0100000011" => u0_m0_wo0_cm0_q <= "0000110100";
WHEN "0100000100" => u0_m0_wo0_cm0_q <= "1111110001";
WHEN "0100000101" => u0_m0_wo0_cm0_q <= "1111000101";
WHEN "0100000110" => u0_m0_wo0_cm0_q <= "1111001011";
WHEN "0100000111" => u0_m0_wo0_cm0_q <= "0000000000";
WHEN "0100001000" => u0_m0_wo0_cm0_q <= "0001001100";
WHEN "0100001001" => u0_m0_wo0_cm0_q <= "0001011100";
WHEN "0100001010" => u0_m0_wo0_cm0_q <= "0001000000";
WHEN "0100001011" => u0_m0_wo0_cm0_q <= "1111000100";
WHEN "0100001100" => u0_m0_wo0_cm0_q <= "1110001001";
WHEN "0100001101" => u0_m0_wo0_cm0_q <= "1110100010";
WHEN "0100001110" => u0_m0_wo0_cm0_q <= "0000001100";
WHEN "0100001111" => u0_m0_wo0_cm0_q <= "0010000111";
WHEN "0100010000" => u0_m0_wo0_cm0_q <= "0010011000";
WHEN "0100010001" => u0_m0_wo0_cm0_q <= "0001001101";
WHEN "0100010010" => u0_m0_wo0_cm0_q <= "1110010110";
WHEN "0100010011" => u0_m0_wo0_cm0_q <= "1101001000";
WHEN "0100010100" => u0_m0_wo0_cm0_q <= "1101110100";
WHEN "0100010101" => u0_m0_wo0_cm0_q <= "0000011010";
WHEN "0100010110" => u0_m0_wo0_cm0_q <= "0011000101";
WHEN "0100010111" => u0_m0_wo0_cm0_q <= "0011010110";
WHEN "0100011000" => u0_m0_wo0_cm0_q <= "0001100110";
WHEN "0100011001" => u0_m0_wo0_cm0_q <= "1101100001";
WHEN "0100011010" => u0_m0_wo0_cm0_q <= "1011111001";
WHEN "0100011011" => u0_m0_wo0_cm0_q <= "1100000100";
WHEN "0100011100" => u0_m0_wo0_cm0_q <= "0001000111";
WHEN "0100011101" => u0_m0_wo0_cm0_q <= "0100001111";
WHEN "0100011110" => u0_m0_wo0_cm0_q <= "0100010111";
WHEN "0100011111" => u0_m0_wo0_cm0_q <= "0001101111";
WHEN "0100100000" => u0_m0_wo0_cm0_q <= "1100100110";
WHEN "0100100001" => u0_m0_wo0_cm0_q <= "1010101111";
WHEN "0100100010" => u0_m0_wo0_cm0_q <= "1010111011";
WHEN "0100100011" => u0_m0_wo0_cm0_q <= "0001011010";
WHEN "0100100100" => u0_m0_wo0_cm0_q <= "0101011010";
WHEN "0100100101" => u0_m0_wo0_cm0_q <= "0101011000";
WHEN "0100100110" => u0_m0_wo0_cm0_q <= "0001100000";
WHEN "0100100111" => u0_m0_wo0_cm0_q <= "1011101110";
WHEN "0100101000" => u0_m0_wo0_cm0_q <= "1001110010";
WHEN "0100101001" => u0_m0_wo0_cm0_q <= "1011111000";
WHEN "0100101010" => u0_m0_wo0_cm0_q <= "0001111101";
WHEN "0100101011" => u0_m0_wo0_cm0_q <= "0110010100";
WHEN "0100101100" => u0_m0_wo0_cm0_q <= "0110001001";
WHEN "0100101101" => u0_m0_wo0_cm0_q <= "0001101100";
WHEN "0100101110" => u0_m0_wo0_cm0_q <= "1010111011";
WHEN "0100101111" => u0_m0_wo0_cm0_q <= "1000110100";
WHEN "0100110000" => u0_m0_wo0_cm0_q <= "1010101000";
WHEN "0100110001" => u0_m0_wo0_cm0_q <= "0010101011";
WHEN "0100110010" => u0_m0_wo0_cm0_q <= "0111000000";
WHEN "0100110011" => u0_m0_wo0_cm0_q <= "0110100011";
WHEN "0100110100" => u0_m0_wo0_cm0_q <= "0001010111";
WHEN "0100110101" => u0_m0_wo0_cm0_q <= "1010010010";
WHEN "0100110110" => u0_m0_wo0_cm0_q <= "1000010101";
WHEN "0100110111" => u0_m0_wo0_cm0_q <= "1010011000";
WHEN "0100111000" => u0_m0_wo0_cm0_q <= "0011001011";
WHEN "0100111001" => u0_m0_wo0_cm0_q <= "0111101101";
WHEN "0100111010" => u0_m0_wo0_cm0_q <= "0110101111";
WHEN "0100111011" => u0_m0_wo0_cm0_q <= "0000010100";
WHEN "0100111100" => u0_m0_wo0_cm0_q <= "1001101101";
WHEN "0100111101" => u0_m0_wo0_cm0_q <= "1000001100";
WHEN "0100111110" => u0_m0_wo0_cm0_q <= "1011000101";
WHEN "0100111111" => u0_m0_wo0_cm0_q <= "0011111001";
WHEN "0101000000" => u0_m0_wo0_cm0_q <= "0111111111";
WHEN "0110000000" => u0_m0_wo0_cm0_q <= "0000101101";
WHEN "0110000001" => u0_m0_wo0_cm0_q <= "0001001111";
WHEN "0110000010" => u0_m0_wo0_cm0_q <= "0000111110";
WHEN "0110000011" => u0_m0_wo0_cm0_q <= "1111111001";
WHEN "0110000100" => u0_m0_wo0_cm0_q <= "1110110100";
WHEN "0110000101" => u0_m0_wo0_cm0_q <= "1110101110";
WHEN "0110000110" => u0_m0_wo0_cm0_q <= "1111011101";
WHEN "0110000111" => u0_m0_wo0_cm0_q <= "0001000110";
WHEN "0110001000" => u0_m0_wo0_cm0_q <= "0001110010";
WHEN "0110001001" => u0_m0_wo0_cm0_q <= "0001010111";
WHEN "0110001010" => u0_m0_wo0_cm0_q <= "1111111000";
WHEN "0110001011" => u0_m0_wo0_cm0_q <= "1110000000";
WHEN "0110001100" => u0_m0_wo0_cm0_q <= "1101101111";
WHEN "0110001101" => u0_m0_wo0_cm0_q <= "1110111100";
WHEN "0110001110" => u0_m0_wo0_cm0_q <= "0001101100";
WHEN "0110001111" => u0_m0_wo0_cm0_q <= "0010110111";
WHEN "0110010000" => u0_m0_wo0_cm0_q <= "0010001111";
WHEN "0110010001" => u0_m0_wo0_cm0_q <= "1111111000";
WHEN "0110010010" => u0_m0_wo0_cm0_q <= "1100111111";
WHEN "0110010011" => u0_m0_wo0_cm0_q <= "1100011110";
WHEN "0110010100" => u0_m0_wo0_cm0_q <= "1110000001";
WHEN "0110010101" => u0_m0_wo0_cm0_q <= "0010001111";
WHEN "0110010110" => u0_m0_wo0_cm0_q <= "0100001101";
WHEN "0110010111" => u0_m0_wo0_cm0_q <= "0011011110";
WHEN "0110011000" => u0_m0_wo0_cm0_q <= "0000000101";
WHEN "0110011001" => u0_m0_wo0_cm0_q <= "1100000000";
WHEN "0110011010" => u0_m0_wo0_cm0_q <= "1011001100";
WHEN "0110011011" => u0_m0_wo0_cm0_q <= "1101010011";
WHEN "0110011100" => u0_m0_wo0_cm0_q <= "0010101110";
WHEN "0110011101" => u0_m0_wo0_cm0_q <= "0101001111";
WHEN "0110011110" => u0_m0_wo0_cm0_q <= "0100011100";
WHEN "0110011111" => u0_m0_wo0_cm0_q <= "0000010011";
WHEN "0110100000" => u0_m0_wo0_cm0_q <= "1011001100";
WHEN "0110100001" => u0_m0_wo0_cm0_q <= "1010000101";
WHEN "0110100010" => u0_m0_wo0_cm0_q <= "1100011000";
WHEN "0110100011" => u0_m0_wo0_cm0_q <= "0011000110";
WHEN "0110100100" => u0_m0_wo0_cm0_q <= "0110010100";
WHEN "0110100101" => u0_m0_wo0_cm0_q <= "0101011101";
WHEN "0110100110" => u0_m0_wo0_cm0_q <= "0000011001";
WHEN "0110100111" => u0_m0_wo0_cm0_q <= "1010010111";
WHEN "0110101000" => u0_m0_wo0_cm0_q <= "1001000100";
WHEN "0110101001" => u0_m0_wo0_cm0_q <= "1011011010";
WHEN "0110101010" => u0_m0_wo0_cm0_q <= "0011011000";
WHEN "0110101011" => u0_m0_wo0_cm0_q <= "0111010011";
WHEN "0110101100" => u0_m0_wo0_cm0_q <= "0110001000";
WHEN "0110101101" => u0_m0_wo0_cm0_q <= "1111111100";
WHEN "0110101110" => u0_m0_wo0_cm0_q <= "1001110011";
WHEN "0110101111" => u0_m0_wo0_cm0_q <= "1000011111";
WHEN "0110110000" => u0_m0_wo0_cm0_q <= "1011001001";
WHEN "0110110001" => u0_m0_wo0_cm0_q <= "0011101101";
WHEN "0110110010" => u0_m0_wo0_cm0_q <= "0111110101";
WHEN "0110110011" => u0_m0_wo0_cm0_q <= "0110100010";
WHEN "0110110100" => u0_m0_wo0_cm0_q <= "1111111001";
WHEN "0110110101" => u0_m0_wo0_cm0_q <= "1001100011";
WHEN "0110110110" => u0_m0_wo0_cm0_q <= "1000001111";
WHEN "0110110111" => u0_m0_wo0_cm0_q <= "1011001001";
WHEN "0110111000" => u0_m0_wo0_cm0_q <= "0011110111";
WHEN "0110111001" => u0_m0_wo0_cm0_q <= "0111111111";
WHEN "0110111010" => u0_m0_wo0_cm0_q <= "0110101000";
WHEN "0110111011" => u0_m0_wo0_cm0_q <= "1111110100";
WHEN "0110111100" => u0_m0_wo0_cm0_q <= "1001011110";
WHEN "0110111101" => u0_m0_wo0_cm0_q <= "1000001101";
WHEN "0110111110" => u0_m0_wo0_cm0_q <= "1011100000";
WHEN "0110111111" => u0_m0_wo0_cm0_q <= "0100000101";
WHEN "0111000000" => u0_m0_wo0_cm0_q <= "0111111001";
WHEN "1000000000" => u0_m0_wo0_cm0_q <= "0000010010";
WHEN "1000000001" => u0_m0_wo0_cm0_q <= "0000001000";
WHEN "1000000010" => u0_m0_wo0_cm0_q <= "0000000011";
WHEN "1000000011" => u0_m0_wo0_cm0_q <= "1111100101";
WHEN "1000000100" => u0_m0_wo0_cm0_q <= "1111010011";
WHEN "1000000101" => u0_m0_wo0_cm0_q <= "1111010011";
WHEN "1000000110" => u0_m0_wo0_cm0_q <= "1111010110";
WHEN "1000000111" => u0_m0_wo0_cm0_q <= "0000011101";
WHEN "1000001000" => u0_m0_wo0_cm0_q <= "0001000101";
WHEN "1000001001" => u0_m0_wo0_cm0_q <= "0000111010";
WHEN "1000001010" => u0_m0_wo0_cm0_q <= "0000000011";
WHEN "1000001011" => u0_m0_wo0_cm0_q <= "1110100100";
WHEN "1000001100" => u0_m0_wo0_cm0_q <= "1110001101";
WHEN "1000001101" => u0_m0_wo0_cm0_q <= "1110101000";
WHEN "1000001110" => u0_m0_wo0_cm0_q <= "0000111111";
WHEN "1000001111" => u0_m0_wo0_cm0_q <= "0010001100";
WHEN "1000010000" => u0_m0_wo0_cm0_q <= "0010110111";
WHEN "1000010001" => u0_m0_wo0_cm0_q <= "1111110000";
WHEN "1000010010" => u0_m0_wo0_cm0_q <= "1101011101";
WHEN "1000010011" => u0_m0_wo0_cm0_q <= "1101000110";
WHEN "1000010100" => u0_m0_wo0_cm0_q <= "1110001100";
WHEN "1000010101" => u0_m0_wo0_cm0_q <= "0001110111";
WHEN "1000010110" => u0_m0_wo0_cm0_q <= "0011100010";
WHEN "1000010111" => u0_m0_wo0_cm0_q <= "0010101011";
WHEN "1000011000" => u0_m0_wo0_cm0_q <= "1111011000";
WHEN "1000011001" => u0_m0_wo0_cm0_q <= "1100000101";
WHEN "1000011010" => u0_m0_wo0_cm0_q <= "1011101111";
WHEN "1000011011" => u0_m0_wo0_cm0_q <= "1110001001";
WHEN "1000011100" => u0_m0_wo0_cm0_q <= "0011000000";
WHEN "1000011101" => u0_m0_wo0_cm0_q <= "0100111010";
WHEN "1000011110" => u0_m0_wo0_cm0_q <= "0011100100";
WHEN "1000011111" => u0_m0_wo0_cm0_q <= "1110111111";
WHEN "1000100000" => u0_m0_wo0_cm0_q <= "1010110010";
WHEN "1000100001" => u0_m0_wo0_cm0_q <= "1010011111";
WHEN "1000100010" => u0_m0_wo0_cm0_q <= "1101111000";
WHEN "1000100011" => u0_m0_wo0_cm0_q <= "0011110111";
WHEN "1000100100" => u0_m0_wo0_cm0_q <= "0110001000";
WHEN "1000100101" => u0_m0_wo0_cm0_q <= "0100011011";
WHEN "1000100110" => u0_m0_wo0_cm0_q <= "1110101010";
WHEN "1000100111" => u0_m0_wo0_cm0_q <= "1001110010";
WHEN "1000101000" => u0_m0_wo0_cm0_q <= "1001100010";
WHEN "1000101001" => u0_m0_wo0_cm0_q <= "1101011001";
WHEN "1000101010" => u0_m0_wo0_cm0_q <= "0100100101";
WHEN "1000101011" => u0_m0_wo0_cm0_q <= "0111001111";
WHEN "1000101100" => u0_m0_wo0_cm0_q <= "0110011000";
WHEN "1000101101" => u0_m0_wo0_cm0_q <= "1110000010";
WHEN "1000101110" => u0_m0_wo0_cm0_q <= "1001000011";
WHEN "1000101111" => u0_m0_wo0_cm0_q <= "1000111001";
WHEN "1000110000" => u0_m0_wo0_cm0_q <= "1101010101";
WHEN "1000110001" => u0_m0_wo0_cm0_q <= "0101000110";
WHEN "1000110010" => u0_m0_wo0_cm0_q <= "0111110110";
WHEN "1000110011" => u0_m0_wo0_cm0_q <= "0111001010";
WHEN "1000110100" => u0_m0_wo0_cm0_q <= "1101111011";
WHEN "1000110101" => u0_m0_wo0_cm0_q <= "1000011001";
WHEN "1000110110" => u0_m0_wo0_cm0_q <= "1000011100";
WHEN "1000110111" => u0_m0_wo0_cm0_q <= "1101111011";
WHEN "1000111000" => u0_m0_wo0_cm0_q <= "0101011101";
WHEN "1000111001" => u0_m0_wo0_cm0_q <= "0111111110";
WHEN "1000111010" => u0_m0_wo0_cm0_q <= "0101010011";
WHEN "1000111011" => u0_m0_wo0_cm0_q <= "1101100010";
WHEN "1000111100" => u0_m0_wo0_cm0_q <= "1000010110";
WHEN "1000111101" => u0_m0_wo0_cm0_q <= "1000100011";
WHEN "1000111110" => u0_m0_wo0_cm0_q <= "1110010010";
WHEN "1000111111" => u0_m0_wo0_cm0_q <= "0101011110";
WHEN "1001000000" => u0_m0_wo0_cm0_q <= "0111101101";
WHEN OTHERS =>
u0_m0_wo0_cm0_q <= (others => '-');
END CASE;
END IF;
END PROCESS;
--u0_m0_wo0_mtree_mult1_0(MULT,24)@13
u0_m0_wo0_mtree_mult1_0_a <= u0_m0_wo0_cm0_q;
u0_m0_wo0_mtree_mult1_0_b <= u0_m0_wo0_wi0_delayr0_q;
u0_m0_wo0_mtree_mult1_0_reset <= areset;
u0_m0_wo0_mtree_mult1_0_component : lpm_mult
GENERIC MAP (
lpm_widtha => 10,
lpm_widthb => 13,
lpm_widthp => 23,
lpm_widths => 1,
lpm_type => "LPM_MULT",
lpm_representation => "SIGNED",
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=5",
lpm_pipeline => 2
)
PORT MAP (
dataa => u0_m0_wo0_mtree_mult1_0_a,
datab => u0_m0_wo0_mtree_mult1_0_b,
clken => VCC_q(0),
aclr => u0_m0_wo0_mtree_mult1_0_reset,
clock => clk,
result => u0_m0_wo0_mtree_mult1_0_s1
);
u0_m0_wo0_mtree_mult1_0_q <= u0_m0_wo0_mtree_mult1_0_s1;
--u0_m0_wo0_accum(ADD,26)@15
u0_m0_wo0_accum_a <= STD_LOGIC_VECTOR((29 downto 23 => u0_m0_wo0_mtree_mult1_0_q(22)) & u0_m0_wo0_mtree_mult1_0_q);
u0_m0_wo0_accum_b <= u0_m0_wo0_accum_q;
u0_m0_wo0_accum_i <= u0_m0_wo0_accum_a;
u0_m0_wo0_accum: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
u0_m0_wo0_accum_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (d_u0_m0_wo0_compute_q_15_q = "1") THEN
IF (u0_m0_wo0_aseq_q = "1") THEN
u0_m0_wo0_accum_o <= u0_m0_wo0_accum_i;
ELSE
u0_m0_wo0_accum_o <= STD_LOGIC_VECTOR(SIGNED(u0_m0_wo0_accum_a) + SIGNED(u0_m0_wo0_accum_b));
END IF;
END IF;
END IF;
END PROCESS;
u0_m0_wo0_accum_q <= u0_m0_wo0_accum_o(29 downto 0);
--GND(CONSTANT,0)@0
GND_q <= "0";
--u0_m0_wo0_oseq(SEQUENCE,27)@14
u0_m0_wo0_oseq: PROCESS (clk, areset)
variable u0_m0_wo0_oseq_c : signed (8 downto 0);
BEGIN
IF (areset = '1') THEN
u0_m0_wo0_oseq_c := "001000000";
u0_m0_wo0_oseq_q <= "0";
u0_m0_wo0_oseq_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (d_u0_m0_wo0_compute_q_14_q = "1") THEN
IF (u0_m0_wo0_oseq_c = "000000000") THEN
u0_m0_wo0_oseq_eq <= '1';
ELSE
u0_m0_wo0_oseq_eq <= '0';
END IF;
IF (u0_m0_wo0_oseq_eq = '1') THEN
u0_m0_wo0_oseq_c := u0_m0_wo0_oseq_c + 64;
ELSE
u0_m0_wo0_oseq_c := u0_m0_wo0_oseq_c - 1;
END IF;
u0_m0_wo0_oseq_q <= std_logic_vector(u0_m0_wo0_oseq_c(8 DOWNTO 8));
END IF;
END IF;
END PROCESS;
--u0_m0_wo0_oseq_gated(LOGICAL,28)@15
u0_m0_wo0_oseq_gated_a <= u0_m0_wo0_oseq_q;
u0_m0_wo0_oseq_gated_b <= d_u0_m0_wo0_compute_q_15_q;
u0_m0_wo0_oseq_gated_q <= u0_m0_wo0_oseq_gated_a and u0_m0_wo0_oseq_gated_b;
--u0_m0_wo0_oseq_gated_reg(REG,29)@15
u0_m0_wo0_oseq_gated_reg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
u0_m0_wo0_oseq_gated_reg_q <= "0";
ELSIF rising_edge(clk) THEN
u0_m0_wo0_oseq_gated_reg_q <= u0_m0_wo0_oseq_gated_q;
END IF;
END PROCESS;
--xOut(PORTOUT,32)@16
xOut_v <= u0_m0_wo0_oseq_gated_reg_q;
xOut_c <= STD_LOGIC_VECTOR("0000000" & GND_q);
xOut_0 <= u0_m0_wo0_accum_q;
end normal;
| gpl-2.0 |
dummylink/plnk_fpga-stack | Examples/xilinx_microblaze/avnet_lx9/pcores/plb_powerlink_v1_00_a/hdl/vhdl/OpenMAC_DPR_Xilinx.vhd | 2 | 11805 | ------------------------------------------------------------------------------------------------------------------------
-- OpenMAC - DPR for Xilinx FPGA
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2009-08-07 V0.01 zelenkaj Converted to official version.
-- 2011-10-12 V0.10 zelenkaj Implementation is based on UG687 (v13.2)
------------------------------------------------------------------------------------------------------------------------
--
-- dual clocked DPRAM for XILINX SPARTAN 6 --
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dc_dpr is
generic (
WIDTH : integer := 16;
SIZE : integer := 128;
ADDRWIDTH : integer := 7
);
port (
clkA : in std_logic;
clkB : in std_logic;
enA : in std_logic;
enB : in std_logic;
weA : in std_logic;
weB : in std_logic;
addrA : in std_logic_vector(ADDRWIDTH-1 downto 0);
addrB : in std_logic_vector(ADDRWIDTH-1 downto 0);
diA : in std_logic_vector(WIDTH-1 downto 0);
diB : in std_logic_vector(WIDTH-1 downto 0);
doA : out std_logic_vector(WIDTH-1 downto 0);
doB : out std_logic_vector(WIDTH-1 downto 0)
);
end dc_dpr;
architecture xilinx of dc_dpr is
function log2 (val: INTEGER) return natural is
variable res : natural;
begin
for i in 0 to 31 loop
if (val <= (2**i)) then
res := i;
exit;
end if;
end loop;
return res;
end function Log2;
type ramType is array (0 to SIZE-1) of std_logic_vector(WIDTH-1 downto 0);
shared variable ram : ramType := (others => (others => '0'));
signal readA : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
signal readB : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
begin
process (clkA)
begin
if rising_edge(clkA) then
if enA = '1' then
if weA = '1' then
ram(conv_integer(addrA)) := diA;
end if;
readA <= ram(conv_integer(addrA));
end if;
end if;
end process;
doA <= readA;
process (clkB)
begin
if rising_edge(clkB) then
if enB = '1' then
if weB = '1' then
ram(conv_integer(addrB)) := diB;
end if;
readB <= ram(conv_integer(addrB));
end if;
end if;
end process;
doB <= readB;
end xilinx;
-- dual clocked DPRAM with byte enables for XILINX SPARTAN 6 --
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dc_dpr_be is
generic (
WIDTH : integer := 16;
SIZE : integer := 128;
ADDRWIDTH : integer := 7
);
port (
clkA : in std_logic;
clkB : in std_logic;
enA : in std_logic;
enB : in std_logic;
weA : in std_logic;
weB : in std_logic;
beA : in std_logic_vector(WIDTH/8-1 downto 0);
beB : in std_logic_vector(WIDTH/8-1 downto 0);
addrA : in std_logic_vector(ADDRWIDTH-1 downto 0);
addrB : in std_logic_vector(ADDRWIDTH-1 downto 0);
diA : in std_logic_vector(WIDTH-1 downto 0);
diB : in std_logic_vector(WIDTH-1 downto 0);
doA : out std_logic_vector(WIDTH-1 downto 0);
doB : out std_logic_vector(WIDTH-1 downto 0)
);
end dc_dpr_be;
architecture xilinx of dc_dpr_be is
function log2 (val: INTEGER) return natural is
variable res : natural;
begin
for i in 0 to 31 loop
if (val <= (2**i)) then
res := i;
exit;
end if;
end loop;
return res;
end function Log2;
type ramType is array (0 to SIZE-1) of std_logic_vector(WIDTH-1 downto 0);
shared variable ram : ramType := (others => (others => '0'));
constant BYTE : integer := 8;
signal readA : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
signal readB : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
begin
process (clkA)
begin
if rising_edge(clkA) then
if enA = '1' then
if weA = '1' then
for i in beA'range loop
if beA(i) = '1' then
ram(conv_integer(addrA))((i+1)*BYTE-1 downto i*BYTE) := diA((i+1)*BYTE-1 downto i*BYTE);
end if;
end loop;
end if;
readA <= ram(conv_integer(addrA));
end if;
end if;
end process;
doA <= readA;
process (clkB)
begin
if rising_edge(clkB) then
if enB = '1' then
if weB = '1' then
for i in beB'range loop
if beB(i) = '1' then
ram(conv_integer(addrB))((i+1)*BYTE-1 downto i*BYTE) := diB((i+1)*BYTE-1 downto i*BYTE);
end if;
end loop;
end if;
readB <= ram(conv_integer(addrB));
end if;
end if;
end process;
doB <= readB;
end xilinx;
-- dual clocked DPRAM with 16x16 --
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity Dpr_16_16 is
generic(Simulate : in boolean);
port (
ClkA, ClkB : in std_logic;
WeA, WeB : in std_logic := '0';
EnA, EnB : in std_logic := '1';
BeA : in std_logic_vector ( 1 downto 0) := "11";
AddrA : in std_logic_vector ( 7 downto 0);
DiA : in std_logic_vector (15 downto 0) := (others => '0');
DoA : out std_logic_vector(15 downto 0);
BeB : in std_logic_vector ( 1 downto 0) := "11";
AddrB : in std_logic_vector ( 7 downto 0);
DiB : in std_logic_vector (15 downto 0) := (others => '0');
DoB : out std_logic_vector(15 downto 0)
);
end Dpr_16_16;
architecture struct of Dpr_16_16 is
begin
dpr_packet: entity work.dc_dpr_be
generic map (
WIDTH => 16,
SIZE => 2**AddrA'length,
ADDRWIDTH => AddrA'length
)
port map (
clkA => ClkA, clkB => ClkB,
enA => EnA, enB => EnB,
addrA => AddrA, addrB => AddrB,
diA => DiA, diB => DiB,
doA => DoA, doB => DoB,
weA => WeA, weB => WeB,
beA => BeA, beB => BeB
);
end struct;
-- dual clocked DPRAM with 16x32 --
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity Dpr_16_32 is
generic(Simulate : in boolean);
port (
ClkA, ClkB : in std_logic;
WeA : in std_logic := '0';
EnA, EnB : in std_logic := '1';
AddrA : in std_logic_vector ( 7 downto 0);
DiA : in std_logic_vector (15 downto 0) := (others => '0');
BeA : in std_logic_vector ( 1 downto 0) := "11";
AddrB : in std_logic_vector ( 6 downto 0);
DoB : out std_logic_vector(31 downto 0)
);
end Dpr_16_32;
architecture struct of Dpr_16_32 is
signal addra_s : std_logic_vector(AddrB'range);
signal dia_s : std_logic_vector(DoB'range);
signal bea_s : std_logic_vector(DoB'length/8-1 downto 0);
begin
dpr_packet: entity work.dc_dpr_be
generic map (
WIDTH => 32,
SIZE => 2**AddrB'length,
ADDRWIDTH => AddrB'length
)
port map (
clkA => ClkA, clkB => ClkB,
enA => EnA, enB => EnB,
addrA => addra_s, addrB => AddrB,
diA => dia_s, diB => (others => '0'),
doA => open, doB => DoB,
weA => weA, weB => '0',
beA => bea_s, beB => (others => '1')
);
addra_s <= AddrA(AddrA'left downto 1);
dia_s <= DiA & DiA;
bea_s(3) <= BeA(1) and AddrA(0);
bea_s(2) <= BeA(0) and AddrA(0);
bea_s(1) <= BeA(1) and not AddrA(0);
bea_s(0) <= BeA(0) and not AddrA(0);
end struct;
-- dual clocked DPRAM with 32x32 for packets --
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY OpenMAC_DPRpackets IS
GENERIC
(
memSizeLOG2_g : integer := 10;
memSize_g : integer := 1024
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (memSizeLOG2_g-2 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (memSizeLOG2_g-3 DOWNTO 0);
byteena_a : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '1');
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
rden_a : IN STD_LOGIC := '1';
rden_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END OpenMAC_DPRpackets;
architecture struct of OpenMAC_DPRpackets is
signal address_a_s : std_logic_vector(address_b'range);
signal bea : std_logic_vector(byteena_b'range);
signal q_a_s, q_b_s, data_a_s : std_logic_vector(q_b'range);
signal q_a_s1 : std_logic_vector(q_a'range);
begin
dpr_packet: entity work.dc_dpr_be
generic map (
WIDTH => 32,
SIZE => memSize_g/4,
ADDRWIDTH => memSizeLOG2_g-2
)
port map (
clkA => clock_a, clkB => clock_b,
enA => '1', enB => '1',
addrA => address_a_s, addrB => address_b,
diA => data_a_s, diB => data_b,
doA => q_a_s, doB => q_b_s,
weA => wren_a, weB => wren_b,
beA => bea, beB => byteena_b
);
address_a_s <= address_a(address_a'left downto 1);
bea(3) <= byteena_a(1) and address_a(0);
bea(2) <= byteena_a(0) and address_a(0);
bea(1) <= byteena_a(1) and not address_a(0);
bea(0) <= byteena_a(0) and not address_a(0);
data_a_s <= data_a & data_a;
q_a_s1 <= q_a_s(q_a'length*2-1 downto q_a'length) when address_a(0) = '1' else
q_a_s(q_a'range);
--sync outputs
process(clock_a)
begin
if rising_edge(clock_a) then
q_a <= q_a_s1;
end if;
end process;
process(clock_b)
begin
if rising_edge(clock_b) then
q_b <= q_b_s;
end if;
end process;
end struct;
| gpl-2.0 |
dummylink/plnk_fpga-stack | Examples/altera_nios2/EBV_DBC3C40/design_nios2_directIO/POWERLINK/src/plb_slave.vhd | 5 | 3186 | -------------------------------------------------------------------------------
--
-- Title : No Title
-- Design : POWERLINK
-- Author : ATSALZ137
-- Company : Bernecker + Rainer
--
-------------------------------------------------------------------------------
--
-- File : C:\mairt\workspace\VHDL_IP-Cores_mairt\active_hdl\compile\plb_slave.vhd
-- Generated : Mon Dec 5 16:05:26 2011
-- From : C:\mairt\workspace\VHDL_IP-Cores_mairt\active_hdl\src\template\plb_slave.bde
-- By : Bde2Vhdl ver. 2.6
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
-- Design unit header --
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.STD_LOGIC_UNSIGNED.all;
entity plb_slave is
generic(
C_SLAVE_BASEADDR : INTEGER := 0;
C_SLAVE_HIGHADDR : INTEGER := 0;
C_SLAVE_NUM_MASTERS : INTEGER := 1;
C_SLAVE_PLB_AWIDTH : INTEGER := 32;
C_SLAVE_PLB_DWIDTH : INTEGER := 32;
C_SLAVE_PLB_MID_WIDTH : INTEGER := 1
);
port(
SLAVE_Clk : in STD_LOGIC;
SLAVE_PAValid : in STD_LOGIC;
SLAVE_RNW : in STD_LOGIC;
SLAVE_Rst : in STD_LOGIC;
SLAVE_SAValid : in STD_LOGIC;
SLAVE_abort : in STD_LOGIC;
SLAVE_busLock : in STD_LOGIC;
SLAVE_compress : in STD_LOGIC;
SLAVE_guarded : in STD_LOGIC;
SLAVE_lockErr : in STD_LOGIC;
SLAVE_ordered : in STD_LOGIC;
SLAVE_pendReq : in STD_LOGIC;
SLAVE_rdBurst : in STD_LOGIC;
SLAVE_rdPrim : in STD_LOGIC;
SLAVE_wrBurst : in STD_LOGIC;
SLAVE_wrPrim : in STD_LOGIC;
SLAVE_ABus : in STD_LOGIC_VECTOR(C_SLAVE_PLB_AWIDTH - 1 downto 0);
SLAVE_BE : in STD_LOGIC_VECTOR((C_SLAVE_PLB_DWIDTH / 8) - 1 downto 0);
SLAVE_MSize : in STD_LOGIC_VECTOR(1 downto 0);
SLAVE_masterID : in STD_LOGIC_VECTOR(C_SLAVE_PLB_MID_WIDTH - 1 downto 0);
SLAVE_pendPri : in STD_LOGIC_VECTOR(1 downto 0);
SLAVE_reqPri : in STD_LOGIC_VECTOR(1 downto 0);
SLAVE_size : in STD_LOGIC_VECTOR(3 downto 0);
SLAVE_type : in STD_LOGIC_VECTOR(2 downto 0);
SLAVE_wrDBus : in STD_LOGIC_VECTOR(C_SLAVE_PLB_DWIDTH - 1 downto 0);
SLAVE_addrAck : out STD_LOGIC;
SLAVE_rdBTerm : out STD_LOGIC;
SLAVE_rdComp : out STD_LOGIC;
SLAVE_rdDAck : out STD_LOGIC;
SLAVE_rearbitrate : out STD_LOGIC;
SLAVE_wait : out STD_LOGIC;
SLAVE_wrBTerm : out STD_LOGIC;
SLAVE_wrComp : out STD_LOGIC;
SLAVE_wrDAck : out STD_LOGIC;
SLAVE_MBusy : out STD_LOGIC_VECTOR(C_SLAVE_NUM_MASTERS - 1 downto 0);
SLAVE_MErr : out STD_LOGIC_VECTOR(C_SLAVE_NUM_MASTERS - 1 downto 0);
SLAVE_SSize : out STD_LOGIC_VECTOR(1 downto 0);
SLAVE_rdDBus : out STD_LOGIC_VECTOR(C_SLAVE_PLB_DWIDTH - 1 downto 0);
SLAVE_rdWdAddr : out STD_LOGIC_VECTOR(3 downto 0)
);
end plb_slave;
architecture template of plb_slave is
begin
end template;
| gpl-2.0 |
dummylink/plnk_fpga-stack | Examples/altera_nios2/TERASIC_DE2-115/design_nios2_directIO/POWERLINK/src/pdi_led.vhd | 5 | 3876 | ------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) led gadget
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2011-09-14 V0.01 zelenkaj extract from pdi.vhd
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
--the led gadget can be set by three different sources
-- source A, B and C
-- the highest priority has C
entity pdiLed is
generic (
iLedWidth_g : integer := 8
);
port (
--src A
srcAled : in std_logic_vector(iLedWidth_g-1 downto 0);
srcAforce : in std_logic_vector(iLedWidth_g-1 downto 0);
--src B
srcBled : in std_logic_vector(iLedWidth_g-1 downto 0);
srcBforce : in std_logic_vector(iLedWidth_g-1 downto 0);
--src C
srcCled : in std_logic_vector(iLedWidth_g-1 downto 0);
srcCforce : in std_logic_vector(iLedWidth_g-1 downto 0);
--led output
ledOut : out std_logic_vector(iLedWidth_g-1 downto 0)
);
end entity pdiLed;
architecture rtl of pdiLed is
begin
theLedGadget : process(srcAled, srcAforce, srcBled, srcBforce, srcCled, srcCforce)
variable tmp_led : std_logic_vector(ledOut'range);
begin
tmp_led := (others => '0');
for i in tmp_led'range loop
--okay, src A may drive if forced
if srcAforce(i) = '1' then
tmp_led(i) := srcAled(i);
end if;
--same vaild for src B, but it overrules src A
if srcBforce(i) = '1' then
tmp_led(i) := srcBled(i);
end if;
--and the head of the logics => src C
if srcCforce(i) = '1' then
tmp_led(i) := srcCled(i);
end if;
end loop;
--let's export and go for a coffee...
ledOut <= tmp_led;
end process;
end architecture rtl; | gpl-2.0 |
Monash-2015-Ultrasonic/Logs | Final System Code/SYSTEMV3/Source/IP/FIR/FIR/auk_dspip_lib_pkg_hpfir.vhd | 2 | 23067 | -- (C) 2001-2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Alex, 02-10-07, this package declaration results in error at built time on a new machine
--
use work.auk_dspip_math_pkg_hpfir.all;
package auk_dspip_lib_pkg_hpfir is
--Component names:
--auk_dspip_atlantic_sink
--auk_dspip_atlantic_source
--auk_dspip_interface_controller
--auk_dspip_avalon_streaming_controller_hpfir
--auk_dspip_avalon_streaming_controller_pe_fir_91
--auk_dspip_avalon_streaming_sink_hpfir
--auk_dspip_avalon_streaming_source_hpfir
--auk_dspip_delay_fir_91
--auk_dspip_fastadd_fir_91
--auk_dspip_fastaddsub_fir_91
--auk_dspip_pipelined_adder_fir_91
--auk_dspip_fast_accumulator_fir_91
--auk_dspip_fifo_pfc_fir_91
--auk_dspip_fpcompiler_alufp
--auk_dspip_fpcompiler_aslf
--auk_dspip_fpcompiler_asrf
--auk_dspip_fpcompiler_castftox
--auk_dspip_fpcompiler_castxtof
--auk_dspip_fpcompiler_clzf
--auk_dspip_fpcompiler_mulfp
--auk_dspip_pfc_fir_91
--auk_dspip_roundsat_fir_91
component auk_dspip_atlantic_sink is
generic(
WIDTH : integer := 16;
PACKET_SIZE : natural := 4;
log2packet_size : integer := 2
);
port(
clk : in std_logic;
reset_n : in std_logic;
----------------- DESIGN SIDE SIGNALS
data_available : out std_logic; --goes high when new data is available
data : out std_logic_vector(WIDTH-1 downto 0);
sink_ready_ctrl : in std_logic; --the controller will tell
--the interface whether
--new input can be accepted.
sink_stall : out std_logic; --needs to stall the design
--if no new data is coming
packet_error : out std_logic_vector (1 downto 0); --this is for SOP and EOP check only.
--when any of these doesn't behave as
--expected, the error is flagged.
send_sop : out std_logic; -- transmit SOP signal to the design.
-- It only transmits the legal SOP.
send_eop : out std_logic; -- transmit EOP signal to the design.
-- It only transmits the legal EOP.
----------------- ATLANTIC SIDE SIGNALS
at_sink_ready : out std_logic; --it will be '1' whenever the
--sink_ready_ctrl signal is high.
at_sink_valid : in std_logic;
at_sink_data : in std_logic_vector(WIDTH-1 downto 0);
at_sink_sop : in std_logic := '0';
at_sink_eop : in std_logic := '0';
at_sink_error : in std_logic_vector(1 downto 0) --it indicates to the data source
--that the SOP and EOP signals
--are not received as expected.
);
end component auk_dspip_atlantic_sink;
component auk_dspip_atlantic_source is
generic(
WIDTH : integer := 16;
packet_size : natural := 4;
LOG2packet_size : integer := 2;
multi_channel : BOOLEAN := TRUE
);
port(
clk : in std_logic;
reset_n : in std_logic;
----------------- DESIGN SIDE SIGNALS
data : in std_logic_vector (WIDTH-1 downto 0);
data_count : in std_logic_vector (LOG2packet_size-1 downto 0) := (others => '0');
source_valid_ctrl : in std_logic; --the controller will tell
--the interface whether
--new input can be accepted.
source_stall : out std_logic; --needs to stall the design
--if no new data is coming
packet_error : in std_logic_vector (1 downto 0);
----------------- ATLANTIC SIDE SIGNALS
at_source_ready : in std_logic;
at_source_valid : out std_logic;
at_source_data : out std_logic_vector (WIDTH-1 downto 0);
at_source_channel : out std_logic_vector (log2packet_size-1 downto 0);
at_source_error : out std_logic_vector (1 downto 0);
at_source_sop : out std_logic;
at_source_eop : out std_logic
);
-- Declarations
end component auk_dspip_atlantic_source;
component auk_dspip_interface_controller IS
PORT(
clk : in std_logic;
reset : IN std_logic;
ready : in std_logic;
sink_packet_error : IN std_logic_vector (1 DOWNTO 0);
sink_stall : IN std_logic;
source_stall : IN std_logic;
valid : IN std_logic;
reset_design : OUT std_logic;
reset_n : OUT std_logic;
sink_ready_ctrl : OUT std_logic;
source_packet_error : OUT std_logic_vector (1 DOWNTO 0);
source_valid_ctrl : OUT std_logic;
stall : OUT std_logic
);
-- Declarations
end component auk_dspip_interface_controller ;
component auk_dspip_avalon_streaming_controller_hpfir is
port(
clk : in std_logic;
--clk_en : in std_logic := '1';
reset_n : in std_logic;
--ready : in std_logic;
sink_packet_error : in std_logic_vector (1 downto 0);
--sink_stall : in std_logic;
source_stall : in std_logic;
valid : in std_logic;
reset_design : out std_logic;
sink_ready_ctrl : out std_logic;
source_packet_error : out std_logic_vector (1 downto 0);
source_valid_ctrl : out std_logic;
stall : out std_logic
);
-- Declarations
end component auk_dspip_avalon_streaming_controller_hpfir;
component auk_dspip_avalon_streaming_controller_pe_fir_91 is
generic (
FIFO_WIDTH_g : natural := 8;
ENABLE_PIPELINE_DEPTH_g : natural := 0; -- this value should match the depth of the enable pipeline in the core
FAMILY_g : string := "Stratix II";
MEM_TYPE_g : string := "Auto"
);
port(
clk : in std_logic;
clk_en : in std_logic := '1';
reset_n : in std_logic;
ready : in std_logic;
sink_packet_error : in std_logic_vector (1 downto 0);
sink_stall : in std_logic;
source_stall : in std_logic;
valid : in std_logic;
reset_design : out std_logic;
sink_ready_ctrl : out std_logic;
source_packet_error : out std_logic_vector (1 downto 0);
source_valid_ctrl : out std_logic;
stall : out std_logic;
data_in : in std_logic_vector(FIFO_WIDTH_g-1 downto 0);
data_out : out std_logic_vector(FIFO_WIDTH_g-1 downto 0);
design_stall : out std_logic
);
-- Declarations
end component auk_dspip_avalon_streaming_controller_pe_fir_91;
component auk_dspip_avalon_streaming_sink_hpfir is
generic(
WIDTH_g : integer := 16;
DATA_WIDTH : integer := 8;
DATA_PORT_COUNT : integer := 3;
PACKET_SIZE_g : natural := 4
--FIFO_DEPTH_g : natural := 5 --if PFC mode is selected, this generic
--is used for passing the poly_factor.
--MIN_DATA_COUNT_g : natural := 2;
--PFC_MODE_g : boolean := false;
--SOP_EOP_CALC_g : boolean := false; -- calculate sop and eop rather than
-- reading value from fifo
--FAMILY_g : string := "Stratix II";
--MEM_TYPE_g : string := "Auto"
);
port(
clk : in std_logic;
reset_n : in std_logic;
----------------- DESIGN SIDE SIGNALS
data : out std_logic_vector(WIDTH_g-1 downto 0);
data_valid : out std_logic_vector(0 downto 0);
sink_ready_ctrl : in std_logic; --the controller will tell
--the interface whether
--new input can be accepted.
--sink_stall : out std_logic; --needs to stall the design
--if no new data is coming
packet_error : out std_logic_vector (1 downto 0); --this is for SOP and EOP check only.
--when any of these doesn't behave as
--expected, the error is flagged.
--send_sop : out std_logic; -- transmit SOP signal to the design.
-- It only transmits the legal SOP.
--send_eop : out std_logic; -- transmit EOP signal to the design.
-- It only transmits the legal EOP.
----------------- ATLANTIC SIDE SIGNALS
at_sink_ready : out std_logic; --it will be '1' whenever the
--sink_ready_ctrl signal is high.
at_sink_valid : in std_logic;
at_sink_data : in std_logic_vector(WIDTH_g-1 downto 0);
at_sink_sop : in std_logic := '0';
at_sink_eop : in std_logic := '0';
at_sink_error : in std_logic_vector(1 downto 0) := "00" --it indicates
--that there is an error in the packet.
);
end component auk_dspip_avalon_streaming_sink_hpfir;
component auk_dspip_avalon_streaming_source_hpfir is
generic(
WIDTH_g : integer := 8;
DATA_WIDTH : integer := 8;
DATA_PORT_COUNT : integer := 1;
PACKET_SIZE_g : natural := 2;
FIFO_DEPTH_g : natural := 0;
HAVE_COUNTER_g : boolean := false;
COUNTER_LIMIT_g : natural := 4;
--MULTI_CHANNEL_g : boolean := true;
USE_PACKETS : integer := 1;
--FAMILY_g : string := "Stratix II";
--MEM_TYPE_g : string := "Auto";
ENABLE_BACKPRESSURE_g : boolean := true
);
port(
clk : in std_logic;
reset_n : in std_logic;
----------------- DESIGN SIDE SIGNALS
data_in : in std_logic_vector (WIDTH_g-1 downto 0);
data_count : in std_logic_vector (log2_ceil_one(PACKET_SIZE_g)-1 downto 0) := (others => '0');
source_valid_ctrl : in std_logic;
source_stall : out std_logic;
packet_error : in std_logic_vector (1 downto 0);
----------------- AVALON_STREAMING SIDE SIGNALS
at_source_ready : in std_logic;
at_source_valid : out std_logic;
at_source_data : out std_logic_vector (WIDTH_g-1 downto 0);
at_source_channel : out std_logic_vector (log2_ceil_one(PACKET_SIZE_g)-1 downto 0);
at_source_error : out std_logic_vector (1 downto 0);
at_source_sop : out std_logic;
at_source_eop : out std_logic
);
-- Declarations
end component auk_dspip_avalon_streaming_source_hpfir;
component auk_dspip_roundsat_hpfir is
generic (
IN_WIDTH_g : natural := 8; -- i/p data width
REM_LSB_BIT_g : natural := 2; -- no. of lsb to be removed
REM_LSB_TYPE_g : string := "Truncation"; -- TRUNCATE/ROUND_UP
REM_MSB_BIT_g : natural := 2; -- no. of msb to be removed
REM_MSB_TYPE_g : string := "Truncation" -- TRUNCATE/SATURATE
);
port (
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(IN_WIDTH_g-1 downto 0);
valid : out std_logic;
dataout : out std_logic_vector(IN_WIDTH_g-REM_LSB_BIT_g-REM_MSB_BIT_g-1 downto 0)
);
end component auk_dspip_roundsat_hpfir;
component auk_dspip_delay_fir_91 is
generic (
WIDTH_g : natural := 8; -- data width
DELAY_g : natural := 8;
-- number of clock cycles the input
-- will be delayed by
MEMORY_TYPE_g : string := "AUTO";
-- possible values are "m4k", "m512",
-- "register", "mram", "auto",
-- "lutram", "M9K", "M144K".
-- Any other string will be interpreted
-- as "auto"
REGISTER_FIRST_g : natural := 1;
-- if "1", the first delay is guaranteed
-- to be in registers
REGISTER_LAST_g : natural := 1); -- if "1", the last delay is guaranteed
-- to be in registers
port (
clk : in std_logic;
reset : in std_logic;
enable : in std_logic; -- global clock enable
datain : in std_logic_vector(WIDTH_g-1 downto 0);
dataout : out std_logic_vector(WIDTH_g-1 downto 0)
);
end component auk_dspip_delay_fir_91;
component auk_dspip_fastadd_fir_91 is
generic (
INWIDTH_g : natural := 18;
LABWIDTH_g : natural := 16);
-- width of lab in selected device ( 10 or 16 in Cyclone,
-- Cylone II, Stratix and Stratix II. Don't know
-- Stratix III yet.
port (
datain1 : in std_logic_vector(INWIDTH_g-1 downto 0);
datain2 : in std_logic_vector(INWIDTH_g-1 downto 0);
clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
dataout : out std_logic_vector(INWIDTH_g downto 0));
end component auk_dspip_fastadd_fir_91;
component auk_dspip_fastaddsub_fir_91 is
generic (
INWIDTH_g : natural := 18;
LABWIDTH_g : natural := 16);
-- width of lab in selected device ( 10 or 16 in Cyclone,
-- Cylone II, Stratix and Stratix II. Don't know
-- Stratix III yet.
port (
datain1 : in std_logic_vector(INWIDTH_g-1 downto 0);
datain2 : in std_logic_vector(INWIDTH_g-1 downto 0);
add_nsub : in std_logic;
clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
dataout : out std_logic_vector(INWIDTH_g downto 0));
end component auk_dspip_fastaddsub_fir_91;
component auk_dspip_pipelined_adder_fir_91 is
generic (
INWIDTH_g : natural := 42;
-- width of lab in selected device ( 10 or 16 in Cyclone,
-- Cylone II, Stratix and Stratix II.
-- Alex : should I use 19 bits for Stratix III?
-- The rational being 10 ALM (2 bits x ALM + the carry chain inside the same LAB for efficiency.
LABWIDTH_g : natural := 38);
port (
datain1 : in std_logic_vector(INWIDTH_g-1 downto 0);
datain2 : in std_logic_vector(INWIDTH_g-1 downto 0);
clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
dataout : out std_logic_vector(INWIDTH_g downto 0));
end component auk_dspip_pipelined_adder_fir_91;
component auk_dspip_fast_accumulator_fir_91 is
generic (
DATA_WIDTH_g : natural := 42;
-- width of lab in selected device ( 10 or 16 in Cyclone,
-- Cylone II, Stratix and Stratix II.
-- for Stratix III is 20 so labwidth should be set to 18.
-- The rational being 10 ALM (2 bits x ALM + the carry chain inside the same LAB for efficiency.
LABWIDTH_g : natural := 38;
NUM_OF_CHANNELS_g : natural := 1;
ACCUM_OUT_WIDTH_g : natural := 48;
ACCUM_MEM_TYPE_g : string := "auto");
port (
reset : in std_logic;
clk : in std_logic;
enb : in std_logic;
add_to_zero : in std_logic;
datai : in std_logic_vector(DATA_WIDTH_g-1 downto 0);
datao : out std_logic_vector(ACCUM_OUT_WIDTH_g-1 downto 0));
end component auk_dspip_fast_accumulator_fir_91;
component auk_dspip_fifo_pfc_fir_91 is
generic (
NUM_CHANNELS_g : integer := 5;
POLY_FACTOR_g : integer := 3;
DATA_WIDTH_g : integer := 16;
ALMOST_FULL_VALUE_g : integer := 2;
RAM_TYPE_g : string := "AUTO";
CALCULATE_USED_WORDS_ONCE : boolean := true
);
port (
datai : in std_logic_vector(DATA_WIDTH_g-1 downto 0);
datao : out std_logic_vector(DATA_WIDTH_g-1 downto 0);
channel_out : out std_logic_vector(log2_ceil(NUM_CHANNELS_g)-1 downto 0);
used_w : out std_logic_vector(log2_ceil(POLY_FACTOR_g * NUM_CHANNELS_g)+1 downto 0);
wrreq : in std_logic;
rdreq : in std_logic;
almost_full : out std_logic;
empty : out std_logic;
sclr : in std_logic;
clk : in std_logic;
reset : in std_logic;
enable : in std_logic
);
end component auk_dspip_fifo_pfc_fir_91;
component auk_dspip_fpcompiler_alufp is
port (
sysclk : in std_logic;
reset : in std_logic;
enable : in std_logic;
addsub : in std_logic;
aa : in std_logic_vector (42 downto 1);
aasat, aazip : in std_logic;
bb : in std_logic_vector (42 downto 1);
bbsat, bbzip : in std_logic;
cc : out std_logic_vector (42 downto 1);
ccsat, cczip : out std_logic
);
end component auk_dspip_fpcompiler_alufp;
component auk_dspip_fpcompiler_aslf is
port (
inbus : in std_logic_vector (32 downto 1);
shift : in std_logic_vector (5 downto 1);
outbus : out std_logic_vector (32 downto 1)
);
end component auk_dspip_fpcompiler_aslf;
component auk_dspip_fpcompiler_asrf is
port (
inbus : in std_logic_vector (32 downto 1);
shift : in std_logic_vector (5 downto 1);
outbus : out std_logic_vector (32 downto 1)
);
end component auk_dspip_fpcompiler_asrf;
component auk_dspip_fpcompiler_castftox is
port (
aa : in std_logic_vector (32 downto 1);
cc : out std_logic_vector (42 downto 1);
ccsat, cczip : out std_logic
);
end component auk_dspip_fpcompiler_castftox;
component auk_dspip_fpcompiler_castxtof is
port (
sysclk : in std_logic;
reset : in std_logic;
enable : in std_logic;
aa : in std_logic_vector (42 downto 1);
aasat, aazip : in std_logic;
cc : out std_logic_vector (32 downto 1)
);
end component auk_dspip_fpcompiler_castxtof;
component auk_dspip_fpcompiler_clzf is
port (
frac : in std_logic_vector (32 downto 1);
count : out std_logic_vector (5 downto 1)
);
end component auk_dspip_fpcompiler_clzf;
component auk_dspip_fpcompiler_mulfp is
port (
sysclk : in std_logic;
reset : in std_logic;
enable : in std_logic;
aa : in std_logic_vector (42 downto 1);
aasat, aazip : in std_logic;
bb : in std_logic_vector (42 downto 1);
bbsat, bbzip : in std_logic;
cc : out std_logic_vector (42 downto 1);
ccsat, cczip : out std_logic
);
end component auk_dspip_fpcompiler_mulfp;
component auk_dspip_pfc_fir_91 is
generic (
NUM_CHANNELS_g : integer := 5;
POLY_FACTOR_g : integer := 3;
DATA_WIDTH_g : integer := 16;
RAM_TYPE_g : string := "AUTO"
);
port (
datai : in std_logic_vector(DATA_WIDTH_g-1 downto 0);
datao : out std_logic_vector(DATA_WIDTH_g-1 downto 0);
channel_out : out std_logic_vector(log2_ceil(NUM_CHANNELS_g)-1 downto 0);
in_valid : in std_logic;
out_valid : out std_logic;
clk : in std_logic;
reset : in std_logic;
enable : in std_logic
);
end component auk_dspip_pfc_fir_91;
component auk_dspip_roundsat_fir_91 is
generic (
IN_WIDTH_g : natural := 8; -- data width
OUT_WIDTH_g : natural := 8; -- data width
ROUNDING_TYPE_g : string := "TRUNCATE_LOW"
);
port (
clk : in std_logic;
reset : in std_logic;
enable : in std_logic; -- global clock enable
datain : in std_logic_vector(IN_WIDTH_g-1 downto 0);
dataout : out std_logic_vector(OUT_WIDTH_g-1 downto 0));
end component auk_dspip_roundsat_fir_91;
component auk_dspip_avalon_streaming_block_source_fir_91 is
generic (
MAX_BLK_g : natural;
DATAWIDTH_g : natural);
port (
clk : in std_logic;
reset : in std_logic;
in_blk : in std_logic_vector(log2_ceil(MAX_BLK_g) downto 0);
in_valid : in std_logic;
source_stall : out std_logic;
in_data : in std_logic_vector(DATAWIDTH_g - 1 downto 0);
source_valid : out std_logic;
source_ready : in std_logic;
source_sop : out std_logic;
source_eop : out std_logic;
source_data : out std_logic_vector(DATAWIDTH_g - 1 downto 0));
end component auk_dspip_avalon_streaming_block_source_fir_91;
component auk_dspip_avalon_streaming_block_sink_fir_91 is
generic (
MAX_BLK_g : natural;
STALL_g : natural;
DATAWIDTH_g : natural;
-- this generic is specific for the FFT.
NUM_STAGES_g : natural);
port (
clk : in std_logic;
reset : in std_logic;
in_blk : in std_logic_vector(log2_ceil(MAX_BLK_g) downto 0);
in_sop : in std_logic;
in_eop : in std_logic;
in_inverse : in std_logic;
sink_valid : in std_logic;
sink_ready : out std_logic;
source_stall : in std_logic;
in_data : in std_logic_vector(DATAWIDTH_g - 1 downto 0);
processing : in std_logic;
in_error : in std_logic_vector(1 downto 0);
out_error : out std_logic_vector(1 downto 0);
out_valid : out std_logic;
out_sop : out std_logic;
out_eop : out std_logic;
out_data : out std_logic_vector(DATAWIDTH_g - 1 downto 0);
curr_blk : out std_logic_vector(log2_ceil(MAX_BLK_g) downto 0);
-- these are specific to the FFT, no effort has been made to optimize!
curr_pwr_2 : out std_logic;
curr_inverse : out std_logic;
curr_input_sel : out std_logic_vector(NUM_STAGES_g - 1 downto 0));
end component auk_dspip_avalon_streaming_block_sink_fir_91;
end package auk_dspip_lib_pkg_hpfir;
| gpl-2.0 |
wklimann/PCM3168 | PCM3168/I2S_OUT.vhd | 1 | 3429 | ---------------------------------------------------------------------------------
-- Engineer: Klimann Wendelin
--
-- Create Date: 08:36:20 11/Okt/2013
-- Design Name: i2s_out
--
-- Description:
--
-- This module provides a bridge between an I2S serial device (audio ADC, S/PDIF
-- Decoded data) and a parallel device (microcontroller, IP block).
--
-- It's coded as a generic VHDL entity, so developer can choose the proper signal
-- width (8/16/24/32 bit)
--
-- Input takes:
-- -I2S Bit Clock
-- -I2S LR Clock (Left/Right channel indication)
-- -DATA_L / DATA_R parallel inputs
--
-- Output provides:
-- -I2S Data
-- -DATA_RDY output ready signals.
--
--
-- The data from the parallel inputs is shifted to the I2S data output
--
--------------------------------------------------------------------------------
-- I2S Waveform summary
--
-- BIT_CK __ __ __ __ __ __ __ __ __
-- | 1|__| 2|_| 3|__| 4|__| 5|__... ... |32|__| 1|__| 2|__| 3| ...
--
-- LR_CK ... ... ___________________
-- ____________L_Channel_Data______________| R Channel Data ...
--
-- DATA x< 00 ><D24><D22><D21><D20> ... ... < 00 ><D24><D23> ...
--
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity i2s_out is
-- width: How many bits (from MSB) are gathered from the serial I2S input
generic(width : integer := 24);
port(
-- I2S ports
LR_CLK : in std_logic; --Left/Right indicator clock
BIT_CLK : in std_logic; --Bit clock
DOUT : out std_logic; --Data Output
-- Control ports
RESET : in std_logic; --Asynchronous Reset (Active Low)
-- Parallel ports
-- use (width-1 downto 0); for big endian fotmat
-- or (0 to width-1) for little endian
DATA_L : in std_logic_vector(0 to width-1);
DATA_R : in std_logic_vector(0 to width-1);
-- Output status ports
DATA_RDY_L : out std_logic; --Falling edge means data is ready
DATA_RDY_R : out std_logic --Falling edge means data is ready
);
end i2s_out;
architecture rtl of i2s_out is
--signals
signal counter : integer range 0 to width;
signal s_current_lr : std_logic;
begin
-- serial to parallel interface
i2s_out: process(RESET, BIT_CLK, LR_CLK, DATA_L, DATA_R)
begin
if(RESET = '0') then
counter <= 0;
s_current_lr <= '0';
DATA_RDY_L <= '0';
DATA_RDY_R <= '0';
DOUT <= '0';
elsif(BIT_CLK'event and BIT_CLK = '0') then
if(s_current_lr = LR_CLK) then
if(s_current_lr = '1') then
DOUT <= DATA_R(counter);
else
DOUT <= DATA_L(counter);
end if;
if (counter < width-1) then
counter <= counter + 1;
else
-- if there is a failure in the clk signals rate -> send 0 to DOUT
DOUT <= '0';
end if;
-- reset the DATA_RDY_x signals
DATA_RDY_L <= '0';
DATA_RDY_R <= '0';
-- if there is a change in the LR_CLK signal enter the else branch
else
if(s_current_lr = '1') then
DOUT <= DATA_R(counter);
DATA_RDY_R <= '1';
else
DOUT <= DATA_L(counter);
DATA_RDY_L <= '1';
end if;
counter <= 0;
s_current_lr <= LR_CLK;
end if; -- (s_current_lr = LR_CLK)
end if; -- reset / rising_edge
end process i2s_out;
end rtl;
| gpl-2.0 |
Caneda/Caneda | libraries/hdl/vhdl/library-ieee.vhd | 1 | 69 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
| gpl-2.0 |
geany/geany | tests/ctags/vhdl-port.vhd | 7 | 165 | -- https://www.ics.uci.edu/~jmoorkan/vhdlref/Synario%20VHDL%20Manual.pdf
entity logical_ops_1 is
port (a, b, c, d: in bit;
m: out bit);
end logical_ops_1;
| gpl-2.0 |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_datamover_v5_1/3acd8cae/hdl/src/vhdl/axi_datamover_mm2s_dre.vhd | 6 | 87880 | -------------------------------------------------------------------------------
-- axi_datamover_mm2s_dre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_mm2s_dre.vhd
--
-- Description:
-- This VHDL design implements a 64 bit wide (8 byte lane) function that
-- realigns an arbitrarily aligned input data stream to an arbitrarily aligned
-- output data stream.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
---------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1;
use axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n;
use axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n;
use axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n;
-------------------------------------------------------------------------------
entity axi_datamover_mm2s_dre is
Generic (
C_DWIDTH : Integer := 64;
-- Sets the native data width of the DRE
C_ALIGN_WIDTH : Integer := 3
-- Sets the alignment port widths. The value should be
-- log2(C_DWIDTH)
);
port (
-- Clock and Reset inputs ---------------
dre_clk : In std_logic; --
dre_rst : In std_logic; --
----------------------------------------
-- Alignment Controls ------------------------------------------------
dre_new_align : In std_logic; --
dre_use_autodest : In std_logic; --
dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
dre_flush : In std_logic; --
----------------------------------------------------------------------
-- Input Stream Interface --------------------------------------------
dre_in_tstrb : In std_logic_vector((C_DWIDTH/8)-1 downto 0); --
dre_in_tdata : In std_logic_vector(C_DWIDTH-1 downto 0); --
dre_in_tlast : In std_logic; --
dre_in_tvalid : In std_logic; --
dre_in_tready : Out std_logic; --
----------------------------------------------------------------------
-- Output Stream Interface -------------------------------------------
dre_out_tstrb : Out std_logic_vector((C_DWIDTH/8)-1 downto 0); --
dre_out_tdata : Out std_logic_vector(C_DWIDTH-1 downto 0); --
dre_out_tlast : Out std_logic; --
dre_out_tvalid : Out std_logic; --
dre_out_tready : In std_logic --
----------------------------------------------------------------------
);
end entity axi_datamover_mm2s_dre;
architecture implementation of axi_datamover_mm2s_dre is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the MSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_start_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_start : Integer := 0;
begin
bit_index_start := lane_index*lane_width;
return(bit_index_start);
end function get_start_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the LSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_end_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_end : Integer := 0;
begin
bit_index_end := (lane_index*lane_width) + (lane_width-1);
return(bit_index_end);
end function get_end_index;
-- Constants
Constant BYTE_WIDTH : integer := 8; -- bits
Constant DATA_WIDTH_BYTES : integer := C_DWIDTH/BYTE_WIDTH;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant NUM_BYTE_LANES : integer := C_DWIDTH/BYTE_WIDTH;
Constant ALIGN_VECT_WIDTH : integer := C_ALIGN_WIDTH;
Constant NO_STRB_SET_VALUE : integer := 0;
-- Types
type sig_byte_lane_type is array(DATA_WIDTH_BYTES-1 downto 0) of
std_logic_vector(SLICE_WIDTH-1 downto 0);
-- Signals
signal sig_input_data_reg : sig_byte_lane_type;
signal sig_delay_data_reg : sig_byte_lane_type;
signal sig_output_data_reg : sig_byte_lane_type;
signal sig_pass_mux_bus : sig_byte_lane_type;
signal sig_delay_mux_bus : sig_byte_lane_type;
signal sig_final_mux_bus : sig_byte_lane_type;
Signal sig_dre_strb_out_i : std_logic_vector(DATA_WIDTH_BYTES-1 downto 0) := (others => '0');
Signal sig_dre_data_out_i : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
Signal sig_dest_align_i : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_dre_flush_i : std_logic := '0';
Signal sig_pipeline_halt : std_logic := '0';
Signal sig_dre_tvalid_i : std_logic := '0';
Signal sig_input_accept : std_logic := '0';
Signal sig_tlast_enables : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_final_mux_has_tlast : std_logic := '0';
signal sig_tlast_out : std_logic := '0';
Signal sig_tlast_strobes : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
Signal sig_next_auto_dest : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_current_dest_align : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_last_written_strb : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
Signal sig_auto_flush : std_logic := '0';
Signal sig_flush_db1 : std_logic := '0';
Signal sig_flush_db2 : std_logic := '0';
signal sig_flush_db1_complete : std_logic := '0';
signal sig_flush_db2_complete : std_logic := '0';
signal sig_output_xfer : std_logic := '0';
signal sig_advance_pipe_data : std_logic := '0';
Signal sig_flush_reg : std_logic := '0';
Signal sig_input_flush_stall : std_logic := '0';
signal sig_enable_input_rdy : std_logic := '0';
signal sig_input_ready : std_logic := '0';
begin --(architecture implementation)
-- Misc assignments
--dre_in_tready <= sig_input_accept ;
dre_in_tready <= sig_input_ready ;
dre_out_tstrb <= sig_dre_strb_out_i ;
dre_out_tdata <= sig_dre_data_out_i ;
dre_out_tvalid <= sig_dre_tvalid_i ;
dre_out_tlast <= sig_tlast_out ;
sig_pipeline_halt <= sig_dre_tvalid_i and not(dre_out_tready);
sig_output_xfer <= sig_dre_tvalid_i and dre_out_tready;
sig_advance_pipe_data <= (dre_in_tvalid or
sig_dre_flush_i) and
not(sig_pipeline_halt) and
sig_enable_input_rdy;
sig_dre_flush_i <= sig_auto_flush ;
sig_input_accept <= dre_in_tvalid and
sig_input_ready;
sig_flush_db1_complete <= sig_flush_db1 and
not(sig_pipeline_halt);
sig_flush_db2_complete <= sig_flush_db2 and
not(sig_pipeline_halt);
sig_auto_flush <= sig_flush_db1 or sig_flush_db2;
sig_input_flush_stall <= sig_auto_flush; -- commanded flush needed for concatonation
sig_last_written_strb <= sig_dre_strb_out_i;
sig_input_ready <= sig_enable_input_rdy and
not(sig_pipeline_halt) and
not(sig_input_flush_stall) ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RESET_FLOP
--
-- Process Description:
-- Just a flop for generating an input disable while reset
-- is in progress.
--
-------------------------------------------------------------
IMP_RESET_FLOP : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_enable_input_rdy <= '0';
else
sig_enable_input_rdy <= '1';
end if;
end if;
end process IMP_RESET_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_FLUSH_IN
--
-- Process Description:
-- Register for the flush signal
--
-------------------------------------------------------------
REG_FLUSH_IN : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or
sig_flush_db2 = '1') then
sig_flush_reg <= '0';
elsif (sig_input_accept = '1') then
sig_flush_reg <= dre_flush;
else
null; -- hold current state
end if;
end if;
end process REG_FLUSH_IN;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_FINAL_MUX_TLAST_OR
--
-- Process Description:
-- Look at all associated tlast bits in the Final Mux output
-- and detirmine if any are set.
--
--
-------------------------------------------------------------
DO_FINAL_MUX_TLAST_OR : process (sig_final_mux_bus)
Variable lvar_finalmux_or : std_logic_vector(NUM_BYTE_LANES-1 downto 0);
begin
lvar_finalmux_or(0) := sig_final_mux_bus(0)(SLICE_TLAST_INDEX);
for tlast_index in 1 to NUM_BYTE_LANES-1 loop
lvar_finalmux_or(tlast_index) :=
lvar_finalmux_or(tlast_index-1) or
sig_final_mux_bus(tlast_index)(SLICE_TLAST_INDEX);
end loop;
sig_final_mux_has_tlast <= lvar_finalmux_or(NUM_BYTE_LANES-1);
end process DO_FINAL_MUX_TLAST_OR;
------------------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_FLUSH_DB1
--
-- Process Description:
-- Creates the first sequential flag indicating that the DRE needs to flush out
-- current contents before allowing any new inputs. This is
-- triggered by the receipt of the TLAST.
--
-------------------------------------------------------------
GEN_FLUSH_DB1 : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
If (dre_rst = '1' or
sig_flush_db2_complete = '1') Then
sig_flush_db1 <= '0';
Elsif (sig_input_accept = '1') Then
sig_flush_db1 <= dre_flush or dre_in_tlast;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_FLUSH_DB1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_FLUSH_DB2
--
-- Process Description:
-- Creates a second sequential flag indicating that the DRE
-- is flushing out current contents. This is
-- triggered by the assertion of the first sequential flush
-- flag.
--
-------------------------------------------------------------
GEN_FLUSH_DB2 : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
If (dre_rst = '1' or
sig_flush_db2_complete = '1') Then
sig_flush_db2 <= '0';
elsif (sig_pipeline_halt = '0') then
sig_flush_db2 <= sig_flush_db1;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_FLUSH_DB2;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CALC_DEST_STRB_ALIGN
--
-- Process Description:
-- This process calculates the byte lane position of the
-- left-most STRB that is unasserted on the DRE output STRB bus.
-- The resulting value is used as the Destination Alignment
-- Vector for the DRE.
--
-------------------------------------------------------------
CALC_DEST_STRB_ALIGN : process (sig_last_written_strb)
Variable lvar_last_strb_hole_position : Integer range 0 to NUM_BYTE_LANES;
Variable lvar_strb_hole_detected : Boolean;
Variable lvar_first_strb_assert_found : Boolean;
Variable lvar_loop_count : integer range 0 to NUM_BYTE_LANES;
Begin
lvar_loop_count := NUM_BYTE_LANES;
lvar_last_strb_hole_position := 0;
lvar_strb_hole_detected := FALSE;
lvar_first_strb_assert_found := FALSE;
-- Search through the output STRB bus starting with the MSByte
while (lvar_loop_count > 0) loop
If (sig_last_written_strb(lvar_loop_count-1) = '0' and
lvar_first_strb_assert_found = FALSE) Then
lvar_strb_hole_detected := TRUE;
lvar_last_strb_hole_position := lvar_loop_count-1;
Elsif (sig_last_written_strb(lvar_loop_count-1) = '1') Then
lvar_first_strb_assert_found := true;
else
null; -- do nothing
End if;
lvar_loop_count := lvar_loop_count - 1;
End loop;
-- now assign the encoder output value to the bit position of the last Strobe encountered
If (lvar_strb_hole_detected) Then
sig_current_dest_align <= STD_LOGIC_VECTOR(TO_UNSIGNED(lvar_last_strb_hole_position, ALIGN_VECT_WIDTH));
else
sig_current_dest_align <= STD_LOGIC_VECTOR(TO_UNSIGNED(NO_STRB_SET_VALUE, ALIGN_VECT_WIDTH));
End if;
end process CALC_DEST_STRB_ALIGN;
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
-- For Generate
--
-- Label: FORMAT_OUTPUT_DATA_STRB
--
-- For Generate Description:
-- Connect the output Data and Strobe ports to the appropriate
-- bits in the sig_output_data_reg.
--
------------------------------------------------------------
FORMAT_OUTPUT_DATA_STRB : for byte_lane_index in 0 to NUM_BYTE_LANES-1 generate
begin
sig_dre_data_out_i(get_end_index(byte_lane_index, BYTE_WIDTH) downto
get_start_index(byte_lane_index, BYTE_WIDTH)) <=
sig_output_data_reg(byte_lane_index)(BYTE_WIDTH-1 downto 0);
sig_dre_strb_out_i(byte_lane_index) <=
sig_output_data_reg(byte_lane_index)(SLICE_WIDTH-2);
end generate FORMAT_OUTPUT_DATA_STRB;
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
---------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_INPUT_REG
--
-- For Generate Description:
--
-- Implements a programble number of input register slices.
--
--
------------------------------------------------------------
GEN_INPUT_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_INPUTREG_SLICE
--
-- Process Description:
-- Implement a single register slice for the Input Register.
--
-------------------------------------------------------------
DO_INPUTREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or
sig_flush_db1_complete = '1' or -- clear on reset or if
(dre_in_tvalid = '1' and
sig_pipeline_halt = '0' and -- the pipe is being advanced and
dre_in_tstrb(slice_index) = '0')) then -- no new valid data id being loaded
sig_input_data_reg(slice_index) <= ZEROED_SLICE;
elsif (dre_in_tstrb(slice_index) = '1' and
sig_input_accept = '1') then
sig_input_data_reg(slice_index) <= sig_tlast_enables(slice_index) &
dre_in_tstrb(slice_index) &
dre_in_tdata((slice_index*8)+7 downto slice_index*8);
else
null; -- don't change state
end if;
end if;
end process DO_INPUTREG_SLICE;
end generate GEN_INPUT_REG;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_DELAY_REG
--
-- For Generate Description:
--
-- Implements a programble number of output register slices
--
--
------------------------------------------------------------
GEN_DELAY_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DELAYREG_SLICE
--
-- Process Description:
-- Implement a single register slice
--
-------------------------------------------------------------
DO_DELAYREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or -- clear on reset or if
(sig_advance_pipe_data = '1' and -- the pipe is being advanced and
sig_delay_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '0')) then -- no new valid data id being loaded
sig_delay_data_reg(slice_index) <= ZEROED_SLICE;
elsif (sig_delay_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '1' and
sig_advance_pipe_data = '1') then
sig_delay_data_reg(slice_index) <= sig_delay_mux_bus(slice_index);
else
null; -- don't change state
end if;
end if;
end process DO_DELAYREG_SLICE;
end generate GEN_DELAY_REG;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_OUTPUT_REG
--
-- For Generate Description:
--
-- Implements a programble number of output register slices
--
--
------------------------------------------------------------
GEN_OUTPUT_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_OUTREG_SLICE
--
-- Process Description:
-- Implement a single register slice
--
-------------------------------------------------------------
DO_OUTREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or -- clear on reset or if
(sig_output_xfer = '1' and -- the output is being transfered and
sig_final_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '0')) then -- no new valid data id being loaded
sig_output_data_reg(slice_index) <= ZEROED_SLICE;
elsif (sig_final_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '1' and
sig_advance_pipe_data = '1') then
sig_output_data_reg(slice_index) <= sig_final_mux_bus(slice_index);
else
null; -- don't change state
end if;
end if;
end process DO_OUTREG_SLICE;
end generate GEN_OUTPUT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_TVALID
--
-- Process Description:
-- This sync process generates the Write request for the
-- destination interface.
--
-------------------------------------------------------------
GEN_TVALID : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_dre_tvalid_i <= '0';
elsif (sig_advance_pipe_data = '1') then
sig_dre_tvalid_i <= sig_final_mux_bus(NUM_BYTE_LANES-1)(SLICE_STROBE_INDEX) or -- MS Strobe is set or
sig_final_mux_has_tlast; -- the Last data beat of a packet
Elsif (dre_out_tready = '1' and -- a completed write but no
sig_dre_tvalid_i = '1') Then -- new input data so clear
-- until more input data shows up
sig_dre_tvalid_i <= '0';
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_TVALID;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_TLAST_OUT
--
-- Process Description:
-- This sync process generates the TLAST output for the
-- destination interface.
--
-------------------------------------------------------------
GEN_TLAST_OUT : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_tlast_out <= '0';
elsif (sig_advance_pipe_data = '1') then
sig_tlast_out <= sig_final_mux_has_tlast;
Elsif (dre_out_tready = '1' and -- a completed transfer
sig_dre_tvalid_i = '1') Then -- so clear tlast
sig_tlast_out <= '0';
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_TLAST_OUT;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_64
--
-- If Generate Description:
-- Support Logic and Mux Farm for 64-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_64 : if (C_DWIDTH = 64) generate
signal sig_cntl_state_64 : std_logic_vector(5 downto 0) := (others => '0');
Signal s_case_i_64 : Integer range 0 to 7 := 0;
Signal sig_shift_case_i : std_logic_vector(2 downto 0) := (others => '0');
Signal sig_shift_case_reg : std_logic_vector(2 downto 0) := (others => '0');
Signal sig_final_mux_sel : std_logic_vector(7 downto 0) := (others => '0');
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_8
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_8 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(7 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "00000000";
elsif (sig_tlast_strobes(7) = '1') then
sig_tlast_enables <= "10000000";
elsif (sig_tlast_strobes(6) = '1') then
sig_tlast_enables <= "01000000";
elsif (sig_tlast_strobes(5) = '1') then
sig_tlast_enables <= "00100000";
elsif (sig_tlast_strobes(4) = '1') then
sig_tlast_enables <= "00010000";
elsif (sig_tlast_strobes(3) = '1') then
sig_tlast_enables <= "00001000";
elsif (sig_tlast_strobes(2) = '1') then
sig_tlast_enables <= "00000100";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "00000010";
else
sig_tlast_enables <= "00000001";
end if;
end process FIND_MS_STRB_SET_8;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to sld_logic_vector
--sig_shift_case_i <= CONV_STD_LOGIC_VECTOR(s_case_i_64, 3);
sig_shift_case_i <= STD_LOGIC_VECTOR(TO_UNSIGNED(s_case_i_64, 3));
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_64
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_64 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_64)
-- signal sig_cntl_state_64 : std_logic_vector(5 downto 0);
-- Signal s_case_i_64 : Integer range 0 to 7;
begin
sig_cntl_state_64 <= dre_src_align & sig_dest_align_i;
case sig_cntl_state_64 is
when "000000" =>
s_case_i_64 <= 0;
when "000001" =>
s_case_i_64 <= 7;
when "000010" =>
s_case_i_64 <= 6;
when "000011" =>
s_case_i_64 <= 5;
when "000100" =>
s_case_i_64 <= 4;
when "000101" =>
s_case_i_64 <= 3;
when "000110" =>
s_case_i_64 <= 2;
when "000111" =>
s_case_i_64 <= 1;
when "001000" =>
s_case_i_64 <= 1;
when "001001" =>
s_case_i_64 <= 0;
when "001010" =>
s_case_i_64 <= 7;
when "001011" =>
s_case_i_64 <= 6;
when "001100" =>
s_case_i_64 <= 5;
when "001101" =>
s_case_i_64 <= 4;
when "001110" =>
s_case_i_64 <= 3;
when "001111" =>
s_case_i_64 <= 2;
when "010000" =>
s_case_i_64 <= 2;
when "010001" =>
s_case_i_64 <= 1;
when "010010" =>
s_case_i_64 <= 0;
when "010011" =>
s_case_i_64 <= 7;
when "010100" =>
s_case_i_64 <= 6;
when "010101" =>
s_case_i_64 <= 5;
when "010110" =>
s_case_i_64 <= 4;
when "010111" =>
s_case_i_64 <= 3;
when "011000" =>
s_case_i_64 <= 3;
when "011001" =>
s_case_i_64 <= 2;
when "011010" =>
s_case_i_64 <= 1;
when "011011" =>
s_case_i_64 <= 0;
when "011100" =>
s_case_i_64 <= 7;
when "011101" =>
s_case_i_64 <= 6;
when "011110" =>
s_case_i_64 <= 5;
when "011111" =>
s_case_i_64 <= 4;
when "100000" =>
s_case_i_64 <= 4;
when "100001" =>
s_case_i_64 <= 3;
when "100010" =>
s_case_i_64 <= 2;
when "100011" =>
s_case_i_64 <= 1;
when "100100" =>
s_case_i_64 <= 0;
when "100101" =>
s_case_i_64 <= 7;
when "100110" =>
s_case_i_64 <= 6;
when "100111" =>
s_case_i_64 <= 5;
when "101000" =>
s_case_i_64 <= 5;
when "101001" =>
s_case_i_64 <= 4;
when "101010" =>
s_case_i_64 <= 3;
when "101011" =>
s_case_i_64 <= 2;
when "101100" =>
s_case_i_64 <= 1;
when "101101" =>
s_case_i_64 <= 0;
when "101110" =>
s_case_i_64 <= 7;
when "101111" =>
s_case_i_64 <= 6;
when "110000" =>
s_case_i_64 <= 6;
when "110001" =>
s_case_i_64 <= 5;
when "110010" =>
s_case_i_64 <= 4;
when "110011" =>
s_case_i_64 <= 3;
when "110100" =>
s_case_i_64 <= 2;
when "110101" =>
s_case_i_64 <= 1;
when "110110" =>
s_case_i_64 <= 0;
when "110111" =>
s_case_i_64 <= 7;
when "111000" =>
s_case_i_64 <= 7;
when "111001" =>
s_case_i_64 <= 6;
when "111010" =>
s_case_i_64 <= 5;
when "111011" =>
s_case_i_64 <= 4;
when "111100" =>
s_case_i_64 <= 3;
when "111101" =>
s_case_i_64 <= 2;
when "111110" =>
s_case_i_64 <= 1;
when "111111" =>
s_case_i_64 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_64;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= (others => '0');
elsif (dre_new_align = '1' and
sig_input_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0) ,
I0 => sig_input_data_reg(1) ,
I1 => sig_input_data_reg(0) ,
Y => sig_pass_mux_bus(1)
);
-- Pass Mux Byte 2 (4-1 x8 Mux)
I_MUX4_1_PASS_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(2) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
Y => sig_pass_mux_bus(2)
);
-- Pass Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_PASS_B3 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(3) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
Y => sig_pass_mux_bus(3)
);
-- Pass Mux Byte 4 (8-1 x8 Mux)
I_MUX8_1_PASS_B4 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(4) ,
I1 => ZEROED_SLICE ,
I2 => ZEROED_SLICE ,
I3 => ZEROED_SLICE ,
I4 => sig_input_data_reg(0) ,
I5 => sig_input_data_reg(1) ,
I6 => sig_input_data_reg(2) ,
I7 => sig_input_data_reg(3) ,
Y => sig_pass_mux_bus(4)
);
-- Pass Mux Byte 5 (8-1 x8 Mux)
I_MUX8_1_PASS_B5 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(5) ,
I1 => ZEROED_SLICE ,
I2 => ZEROED_SLICE ,
I3 => sig_input_data_reg(0) ,
I4 => sig_input_data_reg(1) ,
I5 => sig_input_data_reg(2) ,
I6 => sig_input_data_reg(3) ,
I7 => sig_input_data_reg(4) ,
Y => sig_pass_mux_bus(5)
);
-- Pass Mux Byte 6 (8-1 x8 Mux)
I_MUX8_1_PASS_B6 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(6) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
I4 => sig_input_data_reg(2) ,
I5 => sig_input_data_reg(3) ,
I6 => sig_input_data_reg(4) ,
I7 => sig_input_data_reg(5) ,
Y => sig_pass_mux_bus(6)
);
-- Pass Mux Byte 7 (8-1 x8 Mux)
I_MUX8_1_PASS_B7 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(7) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
I4 => sig_input_data_reg(3) ,
I5 => sig_input_data_reg(4) ,
I6 => sig_input_data_reg(5) ,
I7 => sig_input_data_reg(6) ,
Y => sig_pass_mux_bus(7)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Byte 0 (8-1 x8 Mux)
I_MUX8_1_DLY_B0 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0) ,
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(1) ,
I2 => sig_input_data_reg(2) ,
I3 => sig_input_data_reg(3) ,
I4 => sig_input_data_reg(4) ,
I5 => sig_input_data_reg(5) ,
I6 => sig_input_data_reg(6) ,
I7 => sig_input_data_reg(7) ,
Y => sig_delay_mux_bus(0)
);
-- Delay Mux Byte 1 (8-1 x8 Mux)
I_MUX8_1_DLY_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(2) ,
I2 => sig_input_data_reg(3) ,
I3 => sig_input_data_reg(4) ,
I4 => sig_input_data_reg(5) ,
I5 => sig_input_data_reg(6) ,
I6 => sig_input_data_reg(7) ,
I7 => ZEROED_SLICE ,
Y => sig_delay_mux_bus(1)
);
-- Delay Mux Byte 2 (8-1 x8 Mux)
I_MUX8_1_DLY_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(3) ,
I2 => sig_input_data_reg(4) ,
I3 => sig_input_data_reg(5) ,
I4 => sig_input_data_reg(6) ,
I5 => sig_input_data_reg(7) ,
I6 => ZEROED_SLICE ,
I7 => ZEROED_SLICE ,
Y => sig_delay_mux_bus(2)
);
-- Delay Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_DLY_B3 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(7) ,
I1 => sig_input_data_reg(4) ,
I2 => sig_input_data_reg(5) ,
I3 => sig_input_data_reg(6) ,
Y => sig_delay_mux_bus(3)
);
-- Delay Mux Byte 4 (4-1 x8 Mux)
I_MUX4_1_DLY_B4 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(5) ,
I2 => sig_input_data_reg(6) ,
I3 => sig_input_data_reg(7) ,
Y => sig_delay_mux_bus(4)
);
-- Delay Mux Byte 5 (2-1 x8 Mux)
I_MUX2_1_DLY_B5 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH -- : Integer := 8
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(7),
I1 => sig_input_data_reg(6),
Y => sig_delay_mux_bus(5)
);
-- Delay Mux Byte 6 (Wire)
sig_delay_mux_bus(6) <= sig_input_data_reg(7);
-- Delay Mux Byte 7 (Zeroed)
sig_delay_mux_bus(7) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Byte 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(0) <= '0';
when "001" =>
sig_final_mux_sel(0) <= '1';
when "010" =>
sig_final_mux_sel(0) <= '1';
when "011" =>
sig_final_mux_sel(0) <= '1';
when "100" =>
sig_final_mux_sel(0) <= '1';
when "101" =>
sig_final_mux_sel(0) <= '1';
when "110" =>
sig_final_mux_sel(0) <= '1';
when "111" =>
sig_final_mux_sel(0) <= '1';
when others =>
sig_final_mux_sel(0) <= '0';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_input_data_reg(0),
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Byte 1 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B1_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 1 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B1_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(1) <= '0';
when "001" =>
sig_final_mux_sel(1) <= '1';
when "010" =>
sig_final_mux_sel(1) <= '1';
when "011" =>
sig_final_mux_sel(1) <= '1';
when "100" =>
sig_final_mux_sel(1) <= '1';
when "101" =>
sig_final_mux_sel(1) <= '1';
when "110" =>
sig_final_mux_sel(1) <= '1';
when "111" =>
sig_final_mux_sel(1) <= '0';
when others =>
sig_final_mux_sel(1) <= '0';
end case;
end process MUX2_1_FINAL_B1_CNTL;
I_MUX2_1_FINAL_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(1) ,
I0 => sig_pass_mux_bus(1) ,
I1 => sig_delay_data_reg(1),
Y => sig_final_mux_bus(1)
);
-- Final Mux Byte 2 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B2_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 2 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B2_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(2) <= '0';
when "001" =>
sig_final_mux_sel(2) <= '1';
when "010" =>
sig_final_mux_sel(2) <= '1';
when "011" =>
sig_final_mux_sel(2) <= '1';
when "100" =>
sig_final_mux_sel(2) <= '1';
when "101" =>
sig_final_mux_sel(2) <= '1';
when "110" =>
sig_final_mux_sel(2) <= '0';
when "111" =>
sig_final_mux_sel(2) <= '0';
when others =>
sig_final_mux_sel(2) <= '0';
end case;
end process MUX2_1_FINAL_B2_CNTL;
I_MUX2_1_FINAL_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(2) ,
I0 => sig_pass_mux_bus(2) ,
I1 => sig_delay_data_reg(2),
Y => sig_final_mux_bus(2)
);
-- Final Mux Byte 3 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B3_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 3 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B3_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(3) <= '0';
when "001" =>
sig_final_mux_sel(3) <= '1';
when "010" =>
sig_final_mux_sel(3) <= '1';
when "011" =>
sig_final_mux_sel(3) <= '1';
when "100" =>
sig_final_mux_sel(3) <= '1';
when "101" =>
sig_final_mux_sel(3) <= '0';
when "110" =>
sig_final_mux_sel(3) <= '0';
when "111" =>
sig_final_mux_sel(3) <= '0';
when others =>
sig_final_mux_sel(3) <= '0';
end case;
end process MUX2_1_FINAL_B3_CNTL;
I_MUX2_1_FINAL_B3 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(3) ,
I0 => sig_pass_mux_bus(3) ,
I1 => sig_delay_data_reg(3),
Y => sig_final_mux_bus(3)
);
-- Final Mux Byte 4 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B4_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 4 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B4_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(4) <= '0';
when "001" =>
sig_final_mux_sel(4) <= '1';
when "010" =>
sig_final_mux_sel(4) <= '1';
when "011" =>
sig_final_mux_sel(4) <= '1';
when "100" =>
sig_final_mux_sel(4) <= '0';
when "101" =>
sig_final_mux_sel(4) <= '0';
when "110" =>
sig_final_mux_sel(4) <= '0';
when "111" =>
sig_final_mux_sel(4) <= '0';
when others =>
sig_final_mux_sel(4) <= '0';
end case;
end process MUX2_1_FINAL_B4_CNTL;
I_MUX2_1_FINAL_B4 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(4) ,
I0 => sig_pass_mux_bus(4) ,
I1 => sig_delay_data_reg(4),
Y => sig_final_mux_bus(4)
);
-- Final Mux Byte 5 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B5_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 5 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B5_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(5) <= '0';
when "001" =>
sig_final_mux_sel(5) <= '1';
when "010" =>
sig_final_mux_sel(5) <= '1';
when "011" =>
sig_final_mux_sel(5) <= '0';
when "100" =>
sig_final_mux_sel(5) <= '0';
when "101" =>
sig_final_mux_sel(5) <= '0';
when "110" =>
sig_final_mux_sel(5) <= '0';
when "111" =>
sig_final_mux_sel(5) <= '0';
when others =>
sig_final_mux_sel(5) <= '0';
end case;
end process MUX2_1_FINAL_B5_CNTL;
I_MUX2_1_FINAL_B5 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(5) ,
I0 => sig_pass_mux_bus(5) ,
I1 => sig_delay_data_reg(5),
Y => sig_final_mux_bus(5)
);
-- Final Mux Byte 6 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B6_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 6 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B6_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(6) <= '0';
when "001" =>
sig_final_mux_sel(6) <= '1';
when "010" =>
sig_final_mux_sel(6) <= '0';
when "011" =>
sig_final_mux_sel(6) <= '0';
when "100" =>
sig_final_mux_sel(6) <= '0';
when "101" =>
sig_final_mux_sel(6) <= '0';
when "110" =>
sig_final_mux_sel(6) <= '0';
when "111" =>
sig_final_mux_sel(6) <= '0';
when others =>
sig_final_mux_sel(6) <= '0';
end case;
end process MUX2_1_FINAL_B6_CNTL;
I_MUX2_1_FINAL_B6 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(6) ,
I0 => sig_pass_mux_bus(6) ,
I1 => sig_delay_data_reg(6),
Y => sig_final_mux_bus(6)
);
-- Final Mux Byte 7 (wire)
sig_final_mux_sel(7) <= '0';
sig_final_mux_bus(7) <= sig_pass_mux_bus(7);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_64;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_32
--
-- If Generate Description:
-- Support Logic and Mux Farm for 32-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_32 : if (C_DWIDTH = 32) generate
signal sig_cntl_state_32 : std_logic_vector(3 downto 0);
Signal s_case_i_32 : Integer range 0 to 3;
Signal sig_shift_case_i : std_logic_vector(1 downto 0);
Signal sig_shift_case_reg : std_logic_vector(1 downto 0);
Signal sig_final_mux_sel : std_logic_vector(3 downto 0);
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_4
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_4 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(3 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "0000";
elsif (sig_tlast_strobes(3) = '1') then
sig_tlast_enables <= "1000";
elsif (sig_tlast_strobes(2) = '1') then
sig_tlast_enables <= "0100";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "0010";
else
sig_tlast_enables <= "0001";
end if;
end process FIND_MS_STRB_SET_4;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to sld_logic_vector
--sig_shift_case_i <= CONV_STD_LOGIC_VECTOR(s_case_i_32, 2);
sig_shift_case_i <= STD_LOGIC_VECTOR(TO_UNSIGNED(s_case_i_32, 2));
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_32
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_32 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_32)
begin
sig_cntl_state_32 <= dre_src_align(1 downto 0) & sig_dest_align_i(1 downto 0);
case sig_cntl_state_32 is
when "0000" =>
s_case_i_32 <= 0;
when "0001" =>
s_case_i_32 <= 3;
when "0010" =>
s_case_i_32 <= 2;
when "0011" =>
s_case_i_32 <= 1;
when "0100" =>
s_case_i_32 <= 1;
when "0101" =>
s_case_i_32 <= 0;
when "0110" =>
s_case_i_32 <= 3;
when "0111" =>
s_case_i_32 <= 2;
when "1000" =>
s_case_i_32 <= 2;
when "1001" =>
s_case_i_32 <= 1;
when "1010" =>
s_case_i_32 <= 0;
when "1011" =>
s_case_i_32 <= 3;
when "1100" =>
s_case_i_32 <= 3;
when "1101" =>
s_case_i_32 <= 2;
when "1110" =>
s_case_i_32 <= 1;
when "1111" =>
s_case_i_32 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_32;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= (others => '0');
elsif (dre_new_align = '1' and
sig_input_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(1),
I1 => sig_input_data_reg(0),
Y => sig_pass_mux_bus(1)
);
-- Pass Mux Byte 2 (4-1 x8 Mux)
I_MUX4_1_PASS_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(2) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
Y => sig_pass_mux_bus(2)
);
-- Pass Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_PASS_B3 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(3) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
Y => sig_pass_mux_bus(3)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Byte 0 (4-1 x8 Mux)
I_MUX4_1_DLY_B4 : entity axi_datamover_v5_1.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(1) ,
I2 => sig_input_data_reg(2) ,
I3 => sig_input_data_reg(3) ,
Y => sig_delay_mux_bus(0)
);
-- Delay Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_DLY_B5 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(3),
I1 => sig_input_data_reg(2),
Y => sig_delay_mux_bus(1)
);
-- Delay Mux Byte 2 (Wire)
sig_delay_mux_bus(2) <= sig_input_data_reg(3);
-- Delay Mux Byte 3 (Zeroed)
sig_delay_mux_bus(3) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Slice 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(0) <= '0';
when "01" =>
sig_final_mux_sel(0) <= '1';
when "10" =>
sig_final_mux_sel(0) <= '1';
when "11" =>
sig_final_mux_sel(0) <= '1';
when others =>
sig_final_mux_sel(0) <= '0';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_pass_mux_bus(0) ,
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Slice 1 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B1_CNTL
--
-- Process Description:
-- This process generates the Select Control for slice 1 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B1_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(1) <= '0';
when "01" =>
sig_final_mux_sel(1) <= '1';
when "10" =>
sig_final_mux_sel(1) <= '1';
when "11" =>
sig_final_mux_sel(1) <= '0';
when others =>
sig_final_mux_sel(1) <= '0';
end case;
end process MUX2_1_FINAL_B1_CNTL;
I_MUX2_1_FINAL_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(1) ,
I0 => sig_pass_mux_bus(1) ,
I1 => sig_delay_data_reg(1),
Y => sig_final_mux_bus(1)
);
-- Final Mux Slice 2 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B2_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 2 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B2_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(2) <= '0';
when "01" =>
sig_final_mux_sel(2) <= '1';
when "10" =>
sig_final_mux_sel(2) <= '0';
when "11" =>
sig_final_mux_sel(2) <= '0';
when others =>
sig_final_mux_sel(2) <= '0';
end case;
end process MUX2_1_FINAL_B2_CNTL;
I_MUX2_1_FINAL_B2 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(2) ,
I0 => sig_pass_mux_bus(2) ,
I1 => sig_delay_data_reg(2),
Y => sig_final_mux_bus(2)
);
-- Final Mux Slice 3 (wire)
sig_final_mux_sel(3) <= '0';
sig_final_mux_bus(3) <= sig_pass_mux_bus(3);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_32;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_16
--
-- If Generate Description:
-- Support Logic and Mux Farm for 16-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_16 : if (C_DWIDTH = 16) generate
signal sig_cntl_state_16 : std_logic_vector(1 downto 0);
Signal s_case_i_16 : Integer range 0 to 1;
Signal sig_shift_case_i : std_logic;
Signal sig_shift_case_reg : std_logic;
Signal sig_final_mux_sel : std_logic_vector(1 downto 0);
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_2
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_2 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(1 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "00";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "10";
else
sig_tlast_enables <= "01";
end if;
end process FIND_MS_STRB_SET_2;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to std_logic
sig_shift_case_i <= '1'
When s_case_i_16 = 1
Else '0';
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_16
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_16 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_16)
begin
sig_cntl_state_16 <= dre_src_align(0) & sig_dest_align_i(0);
case sig_cntl_state_16 is
when "00" =>
s_case_i_16 <= 0;
when "01" =>
s_case_i_16 <= 1;
when "10" =>
s_case_i_16 <= 1;
when "11" =>
s_case_i_16 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_16;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= '0';
elsif (dre_new_align = '1' and
sig_input_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg,
I0 => sig_input_data_reg(1),
I1 => sig_input_data_reg(0),
Y => sig_pass_mux_bus(1)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Slice 0 (Wire)
sig_delay_mux_bus(0) <= sig_input_data_reg(1);
-- Delay Mux Slice 1 (Zeroed)
sig_delay_mux_bus(1) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Slice 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when '0' =>
sig_final_mux_sel(0) <= '0';
when others =>
sig_final_mux_sel(0) <= '1';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_pass_mux_bus(0) ,
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Slice 1 (wire)
sig_final_mux_sel(1) <= '0';
sig_final_mux_bus(1) <= sig_pass_mux_bus(1);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_16;
end implementation;
| gpl-2.0 |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_vdma_vregister.vhd | 2 | 13328 | -------------------------------------------------------------------------------
-- axi_vdma_vregister
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_vregister.vhd
--
-- Description: Top level for video register block. These registers provide
-- the video parameters to the DMA controllers.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
use lib_pkg_v1_0.lib_pkg.max2;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_vregister is
generic(
C_NUM_FSTORES : integer range 1 to 32 := 1 ;
-- Number of Frame Stores
C_ADDR_WIDTH : integer range 32 to 32 := 32
-- Start Address Width
);
port (
prmry_aclk : in std_logic ; --
prmry_resetn : in std_logic ; --
--
-- Video Register Update control --
video_reg_update : in std_logic ; --
--
dmasr_halt : in std_logic ; --
-- Scatter Gather register Bank --
vsize_sg : in std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
hsize_sg : in std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
stride_sg : in std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) ; --
frmdly_sg : in std_logic_vector --
(FRMDLY_DWIDTH-1 downto 0) ; --
start_address_sg : in STARTADDR_ARRAY_TYPE --
(0 to C_NUM_FSTORES - 1) ; --
-- Video Register Bank --
vsize_vid : out std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
hsize_vid : out std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
stride_vid : out std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) ; --
frmdly_vid : out std_logic_vector --
(FRMDLY_DWIDTH-1 downto 0) ; --
start_address_vid : out STARTADDR_ARRAY_TYPE
(0 to C_NUM_FSTORES - 1) --
);
end axi_vdma_vregister;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_vregister is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- No Signals Declared
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Vertical Size - Video Side
REG_VSIZE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
vsize_vid <= (others => '0');
-- update video register
elsif(video_reg_update='1') then
vsize_vid <= vsize_sg;
end if;
end if;
end process REG_VSIZE;
-- Horizontal Size - Video Side
REG_HSIZE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
hsize_vid <= (others => '0');
-- update video register
elsif(video_reg_update='1') then
hsize_vid <= hsize_sg;
end if;
end if;
end process REG_HSIZE;
-- Stride - Video Side
REG_STRIDE : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
stride_vid <= (others => '0');
-- update video register
elsif(video_reg_update='1') then
stride_vid <= stride_sg;
end if;
end if;
end process REG_STRIDE;
-- Frame Delay - Video Side
REG_FRMDLY : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0' or dmasr_halt = '1')then
frmdly_vid <= (others => '0');
-- update video register
elsif(video_reg_update='1') then
frmdly_vid <= frmdly_sg;
end if;
end if;
end process REG_FRMDLY;
-- Generate C_NUM_FSTORE start address registeres
GEN_START_ADDR_REG : for i in 0 to C_NUM_FSTORES-1 generate
begin
-- Start Address Registers
REG_START_ADDR : process(prmry_aclk)
begin
if(prmry_aclk'EVENT and prmry_aclk = '1')then
if(prmry_resetn = '0')then
start_address_vid(i) <= (others => '0');
elsif(video_reg_update = '1')then
start_address_vid(i) <= start_address_sg(i);
end if;
end if;
end process REG_START_ADDR;
end generate GEN_START_ADDR_REG;
end implementation;
| gpl-2.0 |
Caneda/Caneda | libraries/hdl/vhdl/synchronous/flipflop d with enable.vhd | 1 | 133 | process(CLK)
begin
if(CLK = '1' and CLK'event) then
if EN = '1' then
Q <= D;
end if;
end if;
end process;
| gpl-2.0 |
nulldozer/purisc | Compute_Group/CORE/execute_stage.vhd | 1 | 2962 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity execute_stage is
port(
clk : in std_logic;
reset_n : in std_logic;
stall : in std_logic;
noop_in : in std_logic;
--inputs
ubranch_in : in std_logic;
cbranch_in : in std_logic;
ex_w_addr : in std_logic_vector(31 downto 0);
ex_w_data : in std_logic_vector(31 downto 0);
ex_we : in std_logic;
start_address : in std_logic_vector(31 downto 0);
a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
c_in : in std_logic_vector(31 downto 0);
addr_a : in std_logic_vector(31 downto 0);
addr_b : in std_logic_vector(31 downto 0);
addr_c : in std_logic_vector(31 downto 0);
next_pc : in std_logic_vector(31 downto 0);
--outputs
cbranch_out : out std_logic;
cbranch_addr : out std_logic_vector(31 downto 0);
-- memory
da_in : in std_logic_vector(31 downto 0);
db_in : in std_logic_vector(31 downto 0);
w_data : out std_logic_vector(31 downto 0);
w_addr : out std_logic_vector(31 downto 0);
we_out : out std_logic
);
end entity;
architecture a1 of execute_stage is
--signals
signal da_fwd : std_logic_vector(31 downto 0);
signal db_fwd : std_logic_vector(31 downto 0);
-- --for self-modifying instruction forwarding
-- signal a_fwd : std_logic_vector(31 downto 0);
-- signal b_fwd : std_logic_vector(31 downto 0);
-- signal c_fwd : std_logic_vector(31 downto 0);
signal sub : signed(31 downto 0);
signal cbranch : std_logic;
signal we : std_logic;
begin
--determine forwarding
da_fwd <= ex_w_data when (a_in = ex_w_addr and ex_we = '1') else da_in;
db_fwd <= ex_w_data when (b_in = ex_w_addr and ex_we = '1') else db_in;
-- --self-modifying instruction forwarding (NOT USED. To enable this, replace instances of a with a_fwd, b with b_fwd ...)
-- a_fwd <= ex_db when (addr_a = ex_b) else a_in;
-- b_fwd <= ex_db when (addr_b = ex_b) else b_in;
-- c_fwd <= ex_db when (addr_c = ex_b) else c_in;
--'execute'
sub <= signed(db_fwd) - signed(da_fwd);
--determine cbranch
cbranch <= '1' when (sub <= 0 and not(noop_in = '1') and not(ubranch_in = '1') and not(next_pc = c_in)) else '0';
--determine whether to write
we <= '1' when (not(noop_in = '1') and not(cbranch_in = '1')) else '0';
process(clk, reset_n, start_address) begin
if(reset_n = '0') then
--initial values
w_data <= "00000000000000000000000000000000";
w_addr <= std_logic_vector(unsigned(start_address) + to_unsigned(7,32)); --as if the third instruction is executing
we_out <= '0';
cbranch_out <= '0';
elsif (rising_edge(clk)) then
if(stall = '0') then
cbranch_out <= cbranch;
cbranch_addr <= c_in;
if(not(noop_in = '1')) then w_addr <= b_in; end if; --to prevent undefined address output after reset
w_data <= std_logic_vector(sub);
we_out <= we;
else
--hold previous outputs on stall (automatic)
end if;
end if;
end process;
end architecture;
| gpl-2.0 |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/bd/tutorial/ip/tutorial_axi_vdma_0_0/sim/tutorial_axi_vdma_0_0.vhd | 1 | 21337 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_vdma:6.2
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_vdma_v6_2;
USE axi_vdma_v6_2.axi_vdma;
ENTITY tutorial_axi_vdma_0_0 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axis_mm2s_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
mm2s_introut : OUT STD_LOGIC
);
END tutorial_axi_vdma_0_0;
ARCHITECTURE tutorial_axi_vdma_0_0_arch OF tutorial_axi_vdma_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tutorial_axi_vdma_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_vdma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_VIDPRMTR_READS : INTEGER;
C_DYNAMIC_RESOLUTION : INTEGER;
C_NUM_FSTORES : INTEGER;
C_USE_FSYNC : INTEGER;
C_USE_MM2S_FSYNC : INTEGER;
C_USE_S2MM_FSYNC : INTEGER;
C_FLUSH_ON_FSYNC : INTEGER;
C_INCLUDE_INTERNAL_GENLOCK : INTEGER;
C_INCLUDE_SG : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_MM2S_GENLOCK_MODE : INTEGER;
C_MM2S_GENLOCK_NUM_MASTERS : INTEGER;
C_MM2S_GENLOCK_REPEAT_EN : INTEGER;
C_MM2S_SOF_ENABLE : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_LINEBUFFER_DEPTH : INTEGER;
C_MM2S_LINEBUFFER_THRESH : INTEGER;
C_MM2S_MAX_BURST_LENGTH : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TUSER_BITS : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_S2MM_GENLOCK_MODE : INTEGER;
C_S2MM_GENLOCK_NUM_MASTERS : INTEGER;
C_S2MM_GENLOCK_REPEAT_EN : INTEGER;
C_S2MM_SOF_ENABLE : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_LINEBUFFER_DEPTH : INTEGER;
C_S2MM_LINEBUFFER_THRESH : INTEGER;
C_S2MM_MAX_BURST_LENGTH : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TUSER_BITS : INTEGER;
C_ENABLE_DEBUG_ALL : INTEGER;
C_ENABLE_DEBUG_INFO_0 : INTEGER;
C_ENABLE_DEBUG_INFO_1 : INTEGER;
C_ENABLE_DEBUG_INFO_2 : INTEGER;
C_ENABLE_DEBUG_INFO_3 : INTEGER;
C_ENABLE_DEBUG_INFO_4 : INTEGER;
C_ENABLE_DEBUG_INFO_5 : INTEGER;
C_ENABLE_DEBUG_INFO_6 : INTEGER;
C_ENABLE_DEBUG_INFO_7 : INTEGER;
C_ENABLE_DEBUG_INFO_8 : INTEGER;
C_ENABLE_DEBUG_INFO_9 : INTEGER;
C_ENABLE_DEBUG_INFO_10 : INTEGER;
C_ENABLE_DEBUG_INFO_11 : INTEGER;
C_ENABLE_DEBUG_INFO_12 : INTEGER;
C_ENABLE_DEBUG_INFO_13 : INTEGER;
C_ENABLE_DEBUG_INFO_14 : INTEGER;
C_ENABLE_DEBUG_INFO_15 : INTEGER;
C_INSTANCE : STRING;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axis_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
s_axis_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
mm2s_fsync : IN STD_LOGIC;
mm2s_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
mm2s_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
s2mm_fsync : IN STD_LOGIC;
s2mm_frame_ptr_in : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
s2mm_frame_ptr_out : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
mm2s_buffer_empty : OUT STD_LOGIC;
mm2s_buffer_almost_empty : OUT STD_LOGIC;
s2mm_buffer_full : OUT STD_LOGIC;
s2mm_buffer_almost_full : OUT STD_LOGIC;
mm2s_fsync_out : OUT STD_LOGIC;
s2mm_fsync_out : OUT STD_LOGIC;
mm2s_prmtr_update : OUT STD_LOGIC;
s2mm_prmtr_update : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_vdma_tstvec : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END COMPONENT axi_vdma;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXIS_MM2S_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_frame_ptr_out: SIGNAL IS "xilinx.com:signal:video_frame_ptr:1.0 MM2S_FRAME_PTR_OUT FRAME_PTR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TUSER";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
BEGIN
U0 : axi_vdma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 9,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 1,
C_ENABLE_VIDPRMTR_READS => 1,
C_DYNAMIC_RESOLUTION => 1,
C_NUM_FSTORES => 3,
C_USE_FSYNC => 1,
C_USE_MM2S_FSYNC => 0,
C_USE_S2MM_FSYNC => 2,
C_FLUSH_ON_FSYNC => 1,
C_INCLUDE_INTERNAL_GENLOCK => 1,
C_INCLUDE_SG => 0,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_INCLUDE_MM2S => 1,
C_MM2S_GENLOCK_MODE => 0,
C_MM2S_GENLOCK_NUM_MASTERS => 1,
C_MM2S_GENLOCK_REPEAT_EN => 0,
C_MM2S_SOF_ENABLE => 1,
C_INCLUDE_MM2S_DRE => 1,
C_INCLUDE_MM2S_SF => 0,
C_MM2S_LINEBUFFER_DEPTH => 4096,
C_MM2S_LINEBUFFER_THRESH => 4,
C_MM2S_MAX_BURST_LENGTH => 8,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 64,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_M_AXIS_MM2S_TUSER_BITS => 1,
C_INCLUDE_S2MM => 0,
C_S2MM_GENLOCK_MODE => 0,
C_S2MM_GENLOCK_NUM_MASTERS => 1,
C_S2MM_GENLOCK_REPEAT_EN => 1,
C_S2MM_SOF_ENABLE => 1,
C_INCLUDE_S2MM_DRE => 0,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_LINEBUFFER_DEPTH => 512,
C_S2MM_LINEBUFFER_THRESH => 4,
C_S2MM_MAX_BURST_LENGTH => 8,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 64,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_TUSER_BITS => 1,
C_ENABLE_DEBUG_ALL => 0,
C_ENABLE_DEBUG_INFO_0 => 0,
C_ENABLE_DEBUG_INFO_1 => 0,
C_ENABLE_DEBUG_INFO_2 => 0,
C_ENABLE_DEBUG_INFO_3 => 0,
C_ENABLE_DEBUG_INFO_4 => 0,
C_ENABLE_DEBUG_INFO_5 => 0,
C_ENABLE_DEBUG_INFO_6 => 0,
C_ENABLE_DEBUG_INFO_7 => 0,
C_ENABLE_DEBUG_INFO_8 => 0,
C_ENABLE_DEBUG_INFO_9 => 0,
C_ENABLE_DEBUG_INFO_10 => 0,
C_ENABLE_DEBUG_INFO_11 => 0,
C_ENABLE_DEBUG_INFO_12 => 0,
C_ENABLE_DEBUG_INFO_13 => 0,
C_ENABLE_DEBUG_INFO_14 => 0,
C_ENABLE_DEBUG_INFO_15 => 0,
C_INSTANCE => "axi_vdma",
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => '0',
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axis_mm2s_aclk => m_axis_mm2s_aclk,
m_axi_s2mm_aclk => '0',
s_axis_s2mm_aclk => '0',
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
mm2s_fsync => '0',
mm2s_frame_ptr_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
mm2s_frame_ptr_out => mm2s_frame_ptr_out,
s2mm_fsync => '0',
s2mm_frame_ptr_in => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
m_axi_sg_arready => '0',
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_rlast => '0',
m_axi_sg_rvalid => '0',
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tuser => m_axis_mm2s_tuser,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axi_s2mm_awready => '0',
m_axi_s2mm_wready => '0',
m_axi_s2mm_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_s2mm_bvalid => '0',
s_axis_s2mm_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_tkeep => X"F",
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_s2mm_tvalid => '0',
s_axis_s2mm_tlast => '0',
mm2s_introut => mm2s_introut
);
END tutorial_axi_vdma_0_0_arch;
| gpl-2.0 |
straywarrior/MadeCPUin21days | ID_EXE_REG.vhd | 1 | 4006 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer: StrayWarrior
--
-- Create Date: 14:18:20 11/14/2015
-- Design Name:
-- Module Name: ID_EXE_REG - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ID_EXE_REG is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
clear : in STD_LOGIC;
stall : in STD_LOGIC;
RegWE_in : in STD_LOGIC;
RegDest_in : in STD_LOGIC_VECTOR (3 downto 0);
MemRd_in : in STD_LOGIC;
MemWE_in : in STD_LOGIC;
MemDIn_in : in STD_LOGIC_VECTOR (15 downto 0);
opcode_in : in STD_LOGIC_VECTOR (3 downto 0);
operandA_in : in STD_LOGIC_VECTOR (15 downto 0);
operandB_in : in STD_LOGIC_VECTOR (15 downto 0);
RegOpA_in : in STD_LOGIC_VECTOR (3 downto 0);
RegOpB_in : in STD_LOGIC_VECTOR (3 downto 0);
RegMemDIn_in : in STD_LOGIC_VECTOR (3 downto 0);
RegWE_out : out STD_LOGIC;
RegDest_out : out STD_LOGIC_VECTOR (3 downto 0);
MemRd_out : out STD_LOGIC;
MemWE_out : out STD_LOGIC;
MemDIn_out : out STD_LOGIC_VECTOR (15 downto 0);
RegMemDIn_out : out STD_LOGIC_VECTOR (3 downto 0);
opcode_out : out STD_LOGIC_VECTOR (3 downto 0);
operandA_out : out STD_LOGIC_VECTOR (15 downto 0);
operandB_out : out STD_LOGIC_VECTOR (15 downto 0);
RegOpA_out : out STD_LOGIC_VECTOR (3 downto 0);
RegOpB_out : out STD_LOGIC_VECTOR (3 downto 0)
);
end ID_EXE_REG;
architecture Behavioral of ID_EXE_REG is
begin
process (clear, reset, clk)
begin
if (reset = '0') then
RegWE_out <= '0';
RegDest_out <= (others => '1');
MemRd_out <= '0';
MemWE_out <= '0';
MemDIn_out <= (others => '0');
RegMemDIn_out <= (others => '0');
opcode_out <= (others => '1');
operandA_out <= (others => '0');
operandB_out <= (others => '0');
RegOpA_out <= (others => '1');
RegOpB_out <= (others => '1');
elsif (clk'event and clk = '1') then
if (clear = '0' and stall = '0') then
RegWE_out <= RegWE_in;
RegDest_out <= RegDest_in;
MemRd_out <= MemRd_in;
MemWE_out <= MemWE_in;
MemDIn_out <= MemDIn_in;
opcode_out <= opcode_in;
operandA_out <= operandA_in;
operandB_out <= operandB_in;
RegOpA_out <= RegOpA_in;
RegOpB_out <= RegOpB_in;
RegMemDIn_out <= RegMemDIn_in;
elsif (clear = '1' and stall = '0') then
RegWE_out <= '0';
RegDest_out <= (others => '1');
MemRd_out <= '0';
MemWE_out <= '0';
MemDIn_out <= (others => '0');
RegMemDIn_out <= (others => '0');
opcode_out <= (others => '1');
operandA_out <= (others => '0');
operandB_out <= (others => '0');
RegOpA_out <= (others => '1');
RegOpB_out <= (others => '1');
else
-- Insert a bubble here
null;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 |
nulldozer/purisc | Compute_Group/MAGIC_clocked/RAM_3.vhd | 1 | 10399 | -- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: RAM_3.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 14.0.0 Build 200 06/17/2014 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus II License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY RAM_3 IS
PORT
(
aclr : IN STD_LOGIC := '0';
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END RAM_3;
ARCHITECTURE SYN OF ram_3 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
q_a <= sub_wire0(31 DOWNTO 0);
q_b <= sub_wire1(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK0",
init_file => "RAM_3.mif",
intended_device_family => "Cyclone IV E",
lpm_type => "altsyncram",
numwords_a => 1024,
numwords_b => 1024,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "CLEAR0",
outdata_aclr_b => "CLEAR0",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "OLD_DATA",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => 10,
widthad_b => 10,
width_a => 32,
width_b => 32,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK0"
)
PORT MAP (
aclr0 => aclr,
address_a => address_a,
address_b => address_b,
clock0 => clock,
data_a => data_a,
data_b => data_b,
wren_a => wren_a,
wren_b => wren_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "1"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "RAM_3.mif"
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "1"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: INIT_FILE STRING "RAM_3.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "CLEAR0"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "CLEAR0"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-- Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]"
-- Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL "data_a[31..0]"
-- Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]"
-- Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]"
-- Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]"
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
-- Retrieval info: CONNECT: @aclr0 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
-- Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0
-- Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0
-- Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_3.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_3.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_3.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_3.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_3_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-2.0 |
nulldozer/purisc | Global_memory/MAGIC_global/SELECTOR_global.vhd | 2 | 4533 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SELECTOR_global is
PORT(
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
OPCODE : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
EQUALITY : OUT STD_LOGIC;
sel_A_0 : OUT STD_LOGIC;
sel_B_0 : OUT STD_LOGIC;
sel_C_0 : OUT STD_LOGIC;
sel_D_0 : OUT STD_LOGIC;
sel_E_0 : OUT STD_LOGIC;
sel_W_0 : OUT STD_LOGIC;
sel_A_1 : OUT STD_LOGIC;
sel_B_1 : OUT STD_LOGIC;
sel_C_1 : OUT STD_LOGIC;
sel_D_1 : OUT STD_LOGIC;
sel_E_1 : OUT STD_LOGIC;
sel_W_1 : OUT STD_LOGIC
);
end;
architecture input_select of SELECTOR_global is
signal opcode_sig : std_logic_vector (5 downto 0) := "000000";
signal serviced_vector : std_logic_vector (5 downto 0) := "000000";
signal equality_vector : std_logic_vector (5 downto 0) := "111111";
signal equality_extend : std_logic_vector (5 downto 0) := "111111";
signal equality_signal : std_logic := '1';
signal equality_buff : std_logic;
signal to_service_next : std_logic_vector (5 downto 0) := "000000";
signal hazard_to_mask : std_logic_vector (5 downto 0) := "111111";
signal hazard_mask : std_logic_vector (5 downto 0) := "111111";
signal SEL_A_0_sig : std_logic;
signal SEL_B_0_sig : std_logic;
signal SEL_C_0_sig : std_logic;
signal SEL_D_0_sig : std_logic;
signal SEL_E_0_sig : std_logic;
signal SEL_W_0_sig : std_logic;
signal SEL_A_1_sig : std_logic;
signal SEL_B_1_sig : std_logic;
signal SEL_C_1_sig : std_logic;
signal SEL_D_1_sig : std_logic;
signal SEL_E_1_sig : std_logic;
signal SEL_W_1_sig : std_logic;
begin
sel_A_0_sig <= opcode_sig(5) and RESET_n;
sel_B_0_sig <= opcode_sig(4) and (not opcode_sig(5)) and RESET_n;
sel_C_0_sig <= opcode_sig(3) and (not (opcode_sig(5) or opcode_sig(4))) and RESET_n;
sel_D_0_sig <= opcode_sig(2) and (not (opcode_sig(5) or opcode_sig(4) or opcode_sig(3))) and RESET_n;
sel_E_0_sig <= opcode_sig(1) and (not (opcode_sig(5) or opcode_sig(4) or opcode_sig(3) or opcode_sig(2))) and RESET_n;
sel_W_0_sig <= opcode_sig(0) and (not (opcode_sig(5) or opcode_sig(4) or opcode_sig(3) or opcode_sig(2) or opcode_sig(1))) and RESET_n;
sel_W_1_sig <= opcode_sig(0) and RESET_n;
sel_E_1_sig <= opcode_sig(1) and (not opcode_sig(0)) and RESET_n;
sel_D_1_sig <= opcode_sig(2) and (not (opcode_sig(1) or opcode_sig(0))) and RESET_n;
sel_C_1_sig <= opcode_sig(3) and (not (opcode_sig(2) or opcode_sig(1) or opcode_sig(0))) and RESET_n;
sel_B_1_sig <= opcode_sig(4) and (not (opcode_sig(3) or opcode_sig(2) or opcode_sig(1) or opcode_sig(0))) and RESET_n;
sel_A_1_sig <= opcode_sig(5) and (not (opcode_sig(4) or opcode_sig(3) or opcode_sig(2) or opcode_sig(1) or opcode_sig(0))) and RESET_n;
-- opcode_sig <= OPCODE and hazard_mask;
-- opcode_sig <= OPCODE;
opcode_sig <= (OPCODE(5) and hazard_mask(5)) & (OPCODE(4) and hazard_mask(4)) & (OPCODE(3) and hazard_mask(3)) &
(OPCODE(2) and hazard_mask(2)) & (OPCODE(1) and hazard_mask(1)) & (OPCODE(0) and hazard_mask(0));
serviced_vector <= (sel_A_0_sig or sel_A_1_sig ) &
(sel_B_0_sig or sel_B_1_sig ) &
(sel_C_0_sig or sel_C_1_sig ) &
(sel_D_0_sig or sel_D_1_sig ) &
(sel_E_0_sig or sel_E_1_sig ) &
(sel_W_0_sig or sel_W_1_sig );
to_service_next <= serviced_vector xor opcode_sig;
equality_vector <= opcode_sig xor (not serviced_vector);
hazard_to_mask <= to_service_next xor equality_extend;
hazard_latching : process (CLK, RESET_n) begin
if (RESET_n = '0') then
hazard_mask <= "111111";
elsif (rising_edge(CLK)) then
hazard_mask <= hazard_to_mask;
end if;
end process;
equality_extend <= equality_signal & equality_signal & equality_signal & equality_signal & equality_signal & equality_signal;
equality_signal <= equality_vector(5) and equality_vector(4) and equality_vector(3) and equality_vector(2) and equality_vector(1) and equality_vector(0);
-- derp : process (CLK) begin
-- if (falling_edge(CLK)) then
-- equality_buff <= equality_signal;
-- end if;
-- end process;
EQUALITY <= equality_signal; --used to be equality_signal
SEL_A_0 <= SEL_A_0_sig;
SEL_B_0 <= SEL_B_0_sig;
SEL_C_0 <= SEL_C_0_sig;
SEL_D_0 <= SEL_D_0_sig;
SEL_E_0 <= SEL_E_0_sig;
SEL_W_0 <= SEL_W_0_sig;
SEL_A_1 <= SEL_A_1_sig;
SEL_B_1 <= SEL_B_1_sig;
SEL_C_1 <= SEL_C_1_sig;
SEL_D_1 <= SEL_D_1_sig;
SEL_E_1 <= SEL_E_1_sig;
SEL_W_1 <= SEL_W_1_sig;
end; | gpl-2.0 |
freecores/t48 | rtl/vhdl/system/t48_system_comp_pack-p.vhd | 1 | 5824 | -------------------------------------------------------------------------------
--
-- $Id: t48_system_comp_pack-p.vhd,v 1.8 2006-06-20 00:47:08 arniml Exp $
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package t48_system_comp_pack is
component t48_wb_master
port (
xtal_i : in std_logic;
res_i : in std_logic;
en_clk_o : out std_logic;
ale_i : in std_logic;
rd_n_i : in std_logic;
wr_n_i : in std_logic;
adr_i : in std_logic;
db_bus_i : in std_logic_vector( 7 downto 0);
db_bus_o : out std_logic_vector( 7 downto 0);
wb_cyc_o : out std_logic;
wb_stb_o : out std_logic;
wb_we_o : out std_logic;
wb_adr_o : out std_logic_vector(23 downto 0);
wb_ack_i : in std_logic;
wb_dat_i : in std_logic_vector( 7 downto 0);
wb_dat_o : out std_logic_vector( 7 downto 0)
);
end component;
component t8048_notri
generic (
gate_port_input_g : integer := 1
);
port (
xtal_i : in std_logic;
xtal_en_i : in std_logic;
reset_n_i : in std_logic;
t0_i : in std_logic;
t0_o : out std_logic;
t0_dir_o : out std_logic;
int_n_i : in std_logic;
ea_i : in std_logic;
rd_n_o : out std_logic;
psen_n_o : out std_logic;
wr_n_o : out std_logic;
ale_o : out std_logic;
db_i : in std_logic_vector( 7 downto 0);
db_o : out std_logic_vector( 7 downto 0);
db_dir_o : out std_logic;
t1_i : in std_logic;
p2_i : in std_logic_vector( 7 downto 0);
p2_o : out std_logic_vector( 7 downto 0);
p2l_low_imp_o : out std_logic;
p2h_low_imp_o : out std_logic;
p1_i : in std_logic_vector( 7 downto 0);
p1_o : out std_logic_vector( 7 downto 0);
p1_low_imp_o : out std_logic;
prog_n_o : out std_logic
);
end component;
component t8039_notri
generic (
gate_port_input_g : integer := 1
);
port (
xtal_i : in std_logic;
xtal_en_i : in std_logic;
reset_n_i : in std_logic;
t0_i : in std_logic;
t0_o : out std_logic;
t0_dir_o : out std_logic;
int_n_i : in std_logic;
ea_i : in std_logic;
rd_n_o : out std_logic;
psen_n_o : out std_logic;
wr_n_o : out std_logic;
ale_o : out std_logic;
db_i : in std_logic_vector( 7 downto 0);
db_o : out std_logic_vector( 7 downto 0);
db_dir_o : out std_logic;
t1_i : in std_logic;
p2_i : in std_logic_vector( 7 downto 0);
p2_o : out std_logic_vector( 7 downto 0);
p2l_low_imp_o : out std_logic;
p2h_low_imp_o : out std_logic;
p1_i : in std_logic_vector( 7 downto 0);
p1_o : out std_logic_vector( 7 downto 0);
p1_low_imp_o : out std_logic;
prog_n_o : out std_logic
);
end component;
component t8050_wb
generic (
gate_port_input_g : integer := 1
);
port (
xtal_i : in std_logic;
reset_n_i : in std_logic;
t0_i : in std_logic;
t0_o : out std_logic;
t0_dir_o : out std_logic;
int_n_i : in std_logic;
ea_i : in std_logic;
rd_n_o : out std_logic;
psen_n_o : out std_logic;
wr_n_o : out std_logic;
ale_o : out std_logic;
t1_i : in std_logic;
p2_i : in std_logic_vector( 7 downto 0);
p2_o : out std_logic_vector( 7 downto 0);
p2l_low_imp_o : out std_logic;
p2h_low_imp_o : out std_logic;
p1_i : in std_logic_vector( 7 downto 0);
p1_o : out std_logic_vector( 7 downto 0);
p1_low_imp_o : out std_logic;
prog_n_o : out std_logic;
wb_cyc_o : out std_logic;
wb_stb_o : out std_logic;
wb_we_o : out std_logic;
wb_adr_o : out std_logic_vector(23 downto 0);
wb_ack_i : in std_logic;
wb_dat_i : in std_logic_vector( 7 downto 0);
wb_dat_o : out std_logic_vector( 7 downto 0)
);
end component;
component t8048
port (
xtal_i : in std_logic;
reset_n_i : in std_logic;
t0_b : inout std_logic;
int_n_i : in std_logic;
ea_i : in std_logic;
rd_n_o : out std_logic;
psen_n_o : out std_logic;
wr_n_o : out std_logic;
ale_o : out std_logic;
db_b : inout std_logic_vector( 7 downto 0);
t1_i : in std_logic;
p2_b : inout std_logic_vector( 7 downto 0);
p1_b : inout std_logic_vector( 7 downto 0);
prog_n_o : out std_logic
);
end component;
component t8039
port (
xtal_i : in std_logic;
reset_n_i : in std_logic;
t0_b : inout std_logic;
int_n_i : in std_logic;
ea_i : in std_logic;
rd_n_o : out std_logic;
psen_n_o : out std_logic;
wr_n_o : out std_logic;
ale_o : out std_logic;
db_b : inout std_logic_vector( 7 downto 0);
t1_i : in std_logic;
p2_b : inout std_logic_vector( 7 downto 0);
p1_b : inout std_logic_vector( 7 downto 0);
prog_n_o : out std_logic
);
end component;
end t48_system_comp_pack;
| gpl-2.0 |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_iic_v2_0/30815c58/hdl/src/vhdl/shift8.vhd | 2 | 7262 | -------------------------------------------------------------------------------
-- shift8.vhd - Entity and Architecture
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: shift8.vhd
-- Version: v1.01.b
-- Description:
-- This file contains an 8 bit shift register
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Release of v1.01.b
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Ports:
-- Clk -- System clock
-- Clr -- System reset
-- Data_ld -- Shift register data load enable
-- Data_in -- Shift register data in
-- Shift_in -- Shift register serial data in
-- Shift_en -- Shift register shift enable
-- Shift_out -- Shift register serial data out
-- Data_out -- Shift register shift data out
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity shift8 is
port(
Clk : in std_logic; -- Clock
Clr : in std_logic; -- Clear
Data_ld : in std_logic; -- Data load enable
Data_in : in std_logic_vector (7 downto 0);-- Data to load in
Shift_in : in std_logic; -- Serial data in
Shift_en : in std_logic; -- Shift enable
Shift_out : out std_logic; -- Shift serial data out
Data_out : out std_logic_vector (7 downto 0) -- Shifted data
);
end shift8;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of shift8 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
constant enable_n : std_logic := '0';
signal data_int : std_logic_vector (7 downto 0);
begin
----------------------------------------------------------------------------
-- PROCESS: SHIFT_REG_GEN
-- purpose: generate shift register
----------------------------------------------------------------------------
SHIFT_REG_GEN : process(Clk)
begin
if Clk'event and Clk = '1' then
if (Clr = enable_n) then -- Clear output register
data_int <= (others => '0');
elsif (Data_ld = '1') then -- Load data
data_int <= Data_in;
elsif Shift_en = '1' then -- If shift enable is high
data_int <= data_int(6 downto 0) & Shift_in; -- Shift the data
end if;
end if;
end process SHIFT_REG_GEN;
Shift_out <= data_int(7);
Data_out <= data_int;
end architecture RTL;
| gpl-2.0 |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/axi_vdma_v6_2/b57990b0/hdl/src/vhdl/axi_sg_ftch_cmdsts_if.vhd | 1 | 14926 | -------------------------------------------------------------------------------
-- axi_sg_ftch_cmdsts_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_cmdsts_if.vhd
-- Description: This entity is the descriptor fetch command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_cmdsts_if is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Fetch command write interface from fetch sm --
ftch_cmnd_wr : in std_logic ; --
ftch_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_ftch_cmd_tvalid : out std_logic ; --
s_axis_ftch_cmd_tready : in std_logic ; --
s_axis_ftch_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- Read response for detecting slverr, decerr early --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_rvalid : in std_logic ; --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_ftch_sts_tvalid : in std_logic ; --
m_axis_ftch_sts_tready : out std_logic ; --
m_axis_ftch_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_ftch_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
mm2s_err : in std_logic ; --
ftch_done : out std_logic ; --
ftch_error : out std_logic ; --
ftch_interr : out std_logic ; --
ftch_slverr : out std_logic ; --
ftch_decerr : out std_logic ; --
ftch_error_early : out std_logic --
);
end axi_sg_ftch_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_slverr_i : std_logic := '0';
signal ftch_decerr_i : std_logic := '0';
signal ftch_interr_i : std_logic := '0';
signal mm2s_error : std_logic := '0';
signal sg_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal sg_rvalid : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ftch_slverr <= ftch_slverr_i;
ftch_decerr <= ftch_decerr_i;
ftch_interr <= ftch_interr_i;
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor fetch command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_ftch_cmd_tvalid <= '0';
s_axis_ftch_cmd_tdata <= (others => '0');
elsif(ftch_cmnd_wr = '1')then
s_axis_ftch_cmd_tvalid <= '1';
s_axis_ftch_cmd_tdata <= ftch_cmnd_data;
elsif(s_axis_ftch_cmd_tready = '1')then
s_axis_ftch_cmd_tvalid <= '0';
s_axis_ftch_cmd_tdata <= (others => '0');
end if;
end if;
end process GEN_DATAMOVER_CMND;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis_ftch_sts_tready <= '0';
else
m_axis_ftch_sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_done <= '0';
ftch_slverr_i <= '0';
ftch_decerr_i <= '0';
ftch_interr_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_ftch_sts_tvalid = '1')then
ftch_done <= m_axis_ftch_sts_tdata(DATAMOVER_STS_CMDDONE_BIT);
ftch_slverr_i <= m_axis_ftch_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
ftch_decerr_i <= m_axis_ftch_sts_tdata(DATAMOVER_STS_DECERR_BIT);
ftch_interr_i <= m_axis_ftch_sts_tdata(DATAMOVER_STS_INTERR_BIT);
-- Only assert when valid
else
ftch_done <= '0';
ftch_slverr_i <= '0';
ftch_decerr_i <= '0';
ftch_interr_i <= '0';
end if;
end if;
end process DATAMOVER_STS;
-------------------------------------------------------------------------------
-- Early SlvErr and DecErr detections
-- Early detection primarily required for non-queue mode because fetched desc
-- is immediatle fed to DMA controller. Status from SG Datamover arrives
-- too late to stop the insuing transfer on fetch error
-------------------------------------------------------------------------------
REG_MM_RD_SIGNALS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_rresp <= (others => '0');
sg_rvalid <= '0';
else
sg_rresp <= m_axi_sg_rresp;
sg_rvalid <= m_axi_sg_rvalid;
end if;
end if;
end process REG_MM_RD_SIGNALS;
REG_ERLY_FTCH_ERROR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_error_early <= '0';
elsif(sg_rvalid = '1' and (sg_rresp = SLVERR_RESP
or sg_rresp = DECERR_RESP))then
ftch_error_early <= '1';
end if;
end if;
end process REG_ERLY_FTCH_ERROR;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
mm2s_error <= ftch_slverr_i or ftch_decerr_i or ftch_interr_i;
-- Log errors into a global error output
FETCH_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ftch_error <= '0';
elsif(mm2s_error = '1')then
ftch_error <= '1';
end if;
end if;
end process FETCH_ERROR_PROCESS;
end implementation;
| gpl-2.0 |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/bd/tutorial/ip/tutorial_v_tpg_0_0/synth/tutorial_v_tpg_0_0.vhd | 1 | 12937 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:v_tpg:6.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY v_tpg_v6_0;
USE v_tpg_v6_0.v_tpg;
ENTITY tutorial_v_tpg_0_0 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
irq : OUT STD_LOGIC;
m_axis_video_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_video_tvalid : OUT STD_LOGIC;
m_axis_video_tready : IN STD_LOGIC;
m_axis_video_tlast : OUT STD_LOGIC;
m_axis_video_tuser : OUT STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aclken : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC
);
END tutorial_v_tpg_0_0;
ARCHITECTURE tutorial_v_tpg_0_0_arch OF tutorial_v_tpg_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tutorial_v_tpg_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT v_tpg IS
GENERIC (
C_S_AXIS_VIDEO_DATA_WIDTH : INTEGER;
C_M_AXIS_VIDEO_DATA_WIDTH : INTEGER;
C_S_AXIS_VIDEO_TDATA_WIDTH : INTEGER;
C_M_AXIS_VIDEO_TDATA_WIDTH : INTEGER;
C_S_AXIS_VIDEO_FORMAT : INTEGER;
C_M_AXIS_VIDEO_FORMAT : INTEGER;
C_S_AXIS_VIDEO_TUSER_WIDTH : INTEGER;
C_M_AXIS_VIDEO_TUSER_WIDTH : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI_CLK_FREQ_HZ : INTEGER;
C_ACTIVE_ROWS : INTEGER;
C_ACTIVE_COLS : INTEGER;
C_PATTERN_CONTROL : INTEGER;
C_MOTION_SPEED : INTEGER;
C_CROSS_HAIRS : INTEGER;
C_ZPLATE_HOR_CONTROL : INTEGER;
C_ZPLATE_VER_CONTROL : INTEGER;
C_BOX_SIZE : INTEGER;
C_BOX_COLOR : INTEGER;
C_STUCK_PIXEL_THRESH : INTEGER;
C_NOISE_GAIN : INTEGER;
C_BAYER_PHASE : INTEGER;
C_HAS_INTC_IF : INTEGER;
C_HAS_AXI4_LITE : INTEGER;
C_HAS_VTIMING : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
intc_if : OUT STD_LOGIC_VECTOR(8 DOWNTO 0);
irq : OUT STD_LOGIC;
s_axis_video_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_video_tready : OUT STD_LOGIC;
s_axis_video_tvalid : IN STD_LOGIC;
s_axis_video_tlast : IN STD_LOGIC;
s_axis_video_tuser : IN STD_LOGIC;
m_axis_video_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axis_video_tvalid : OUT STD_LOGIC;
m_axis_video_tready : IN STD_LOGIC;
m_axis_video_tlast : OUT STD_LOGIC;
m_axis_video_tuser : OUT STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aclken : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
hsync_in : IN STD_LOGIC;
hblank_in : IN STD_LOGIC;
vsync_in : IN STD_LOGIC;
vblank_in : IN STD_LOGIC;
active_video_in : IN STD_LOGIC
);
END COMPONENT v_tpg;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF tutorial_v_tpg_0_0_arch: ARCHITECTURE IS "v_tpg,Vivado 2014.4.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF tutorial_v_tpg_0_0_arch : ARCHITECTURE IS "tutorial_v_tpg_0_0,v_tpg,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF tutorial_v_tpg_0_0_arch: ARCHITECTURE IS "tutorial_v_tpg_0_0,v_tpg,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=v_tpg,x_ipVersion=6.0,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXIS_VIDEO_DATA_WIDTH=8,C_M_AXIS_VIDEO_DATA_WIDTH=8,C_S_AXIS_VIDEO_TDATA_WIDTH=16,C_M_AXIS_VIDEO_TDATA_WIDTH=8,C_S_AXIS_VIDEO_FORMAT=0,C_M_AXIS_VIDEO_FORMAT=12,C_S_AXIS_VIDEO_TUSER_WIDTH=0,C_M_AXIS_VIDEO_TUSER_WIDTH=1,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_S_AXI_CLK_FREQ_HZ=100000000,C_ACTIVE_ROWS=1080,C_ACTIVE_COLS=1920,C_PATTERN_CONTROL=4106,C_MOTION_SPEED=0,C_CROSS_HAIRS=6553700,C_ZPLATE_HOR_CONTROL=30,C_ZPLATE_VER_CONTROL=1,C_BOX_SIZE=50,C_BOX_COLOR=0,C_STUCK_PIXEL_THRESH=0,C_NOISE_GAIN=0,C_BAYER_PHASE=2,C_HAS_INTC_IF=0,C_HAS_AXI4_LITE=1,C_HAS_VTIMING=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 aresetn_intf RST";
ATTRIBUTE X_INTERFACE_INFO OF irq: SIGNAL IS "xilinx.com:signal:interrupt:1.0 irq_intf INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_video_tuser: SIGNAL IS "xilinx.com:interface:axis:1.0 video_out TUSER";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s_axi_aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 s_axi_aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s_axi_aresetn_intf RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 ctrl RREADY";
BEGIN
U0 : v_tpg
GENERIC MAP (
C_S_AXIS_VIDEO_DATA_WIDTH => 8,
C_M_AXIS_VIDEO_DATA_WIDTH => 8,
C_S_AXIS_VIDEO_TDATA_WIDTH => 16,
C_M_AXIS_VIDEO_TDATA_WIDTH => 8,
C_S_AXIS_VIDEO_FORMAT => 0,
C_M_AXIS_VIDEO_FORMAT => 12,
C_S_AXIS_VIDEO_TUSER_WIDTH => 0,
C_M_AXIS_VIDEO_TUSER_WIDTH => 1,
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI_CLK_FREQ_HZ => 100000000,
C_ACTIVE_ROWS => 1080,
C_ACTIVE_COLS => 1920,
C_PATTERN_CONTROL => 4106,
C_MOTION_SPEED => 0,
C_CROSS_HAIRS => 6553700,
C_ZPLATE_HOR_CONTROL => 30,
C_ZPLATE_VER_CONTROL => 1,
C_BOX_SIZE => 50,
C_BOX_COLOR => 0,
C_STUCK_PIXEL_THRESH => 0,
C_NOISE_GAIN => 0,
C_BAYER_PHASE => 2,
C_HAS_INTC_IF => 0,
C_HAS_AXI4_LITE => 1,
C_HAS_VTIMING => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => aresetn,
irq => irq,
s_axis_video_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axis_video_tvalid => '0',
s_axis_video_tlast => '0',
s_axis_video_tuser => '0',
m_axis_video_tdata => m_axis_video_tdata,
m_axis_video_tvalid => m_axis_video_tvalid,
m_axis_video_tready => m_axis_video_tready,
m_axis_video_tlast => m_axis_video_tlast,
m_axis_video_tuser => m_axis_video_tuser,
s_axi_aclk => s_axi_aclk,
s_axi_aclken => s_axi_aclken,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
hsync_in => '0',
hblank_in => '0',
vsync_in => '1',
vblank_in => '0',
active_video_in => '0'
);
END tutorial_v_tpg_0_0_arch;
| gpl-2.0 |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/bd/tutorial/ip/tutorial_rst_processing_system7_0_100M_0/sim/tutorial_rst_processing_system7_0_100M_0.vhd | 1 | 5935 | -- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY tutorial_rst_processing_system7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END tutorial_rst_processing_system7_0_100M_0;
ARCHITECTURE tutorial_rst_processing_system7_0_100M_0_arch OF tutorial_rst_processing_system7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF tutorial_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END tutorial_rst_processing_system7_0_100M_0_arch;
| gpl-2.0 |
freecores/t48 | rtl/vhdl/system/t49_rom-e.vhd | 1 | 2538 | -------------------------------------------------------------------------------
--
-- T8x49 ROM
--
-- $Id: t49_rom-e.vhd,v 1.1 2006-06-21 00:59:15 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity t49_rom is
port (
clk_i : in std_logic;
rom_addr_i : in std_logic_vector(10 downto 0);
rom_data_o : out std_logic_vector( 7 downto 0)
);
end t49_rom;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
| gpl-2.0 |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/lib_srl_fifo_v1_0/292dd5ac/hdl/src/vhdl/srl_fifo_rbu_f.vhd | 11 | 15814 | -- srl_fifo_rbu_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2007-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_rbu_f.vhd
--
-- Description: A small-to-medium depth FIFO with optional
-- capability to back up and reread data. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write, and reread n.
-- - Flags: empty and full.
-- - The reread n command (executed by applying
-- a non-zero value, n, to signal Num_To_Reread
-- for one clock period) allows n
-- previously read elements to be restored to the FIFO,
-- limited, however, to the number of elements that have
-- not been overwritten. (It is the user's responsibility
-- to assure that the elements being restored are
-- actually in the FIFO storage; once the depth of the
-- FIFO has been written, the maximum number that can
-- be restored is equal to the vacancy.)
-- The reread capability does not cost extra LUTs or FFs.
-- - Commands may be asserted simultaneously.
-- However, if read and reread n are asserted
-- simultaneously, only the read is carried out.
-- - Overflow and underflow are detected and latched until
-- Reset. The state of the FIFO is undefined during
-- status of underflow or overflow.
-- Underflow can occur only by reading the FIFO when empty.
-- Overflow can occur either from a write, a reread n,
-- or a combination of both that would result in more
-- elements occupying the FIFO that its C_DEPTH.
-- - Any of the signals FIFO_Full, Underflow, or Overflow
-- left unconnected can be expected to be trimmed.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left with Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
-- This information can be used to generate additional
-- flags, if needed.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_rbu_f.vhd
-- dynshreg_f.vhd
-- cntr_incr_decr_addn_f.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/05/05 First Version. Derived from srl_fifo_rbu.
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v5_0
-- ~~~~~~
-- - Changed lib library version to v5_0
-- - Incorporated new disclaimer header
-- ^^^^^^
-- FLO 2008-11-25
-- ^^^^^^
-- Changed to functionally equivalent code to generate FIFO_Full. The new code
-- steers the current XST toward a better implementation. CR 496211.
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- predecessor value by # clks: "*_p#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std.">=";
use ieee.numeric_std.TO_UNSIGNED;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
library lib_srl_fifo_v1_0;
entity srl_fifo_rbu_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Full : out std_logic;
FIFO_Empty : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1);
Num_To_Reread : in std_logic_vector(0 to clog2(C_DEPTH)-1);
Underflow : out std_logic;
Overflow : out std_logic
);
end entity srl_fifo_rbu_f;
architecture imp of srl_fifo_rbu_f is
function bitwise_or(s: std_logic_vector) return std_logic is
variable v: std_logic := '0';
begin
for i in s'range loop v := v or s(i); end loop;
return v;
end bitwise_or;
constant ADDR_BITS : integer := clog2(C_DEPTH);
-- An extra bit will be carried as the empty flag.
signal addr_i : std_logic_vector(ADDR_BITS downto 0);
signal addr_i_p1 : std_logic_vector(ADDR_BITS downto 0);
signal num_to_reread_zeroext : std_logic_vector(ADDR_BITS downto 0);
signal fifo_empty_i : std_logic;
signal overflow_i : std_logic;
signal underflow_i : std_logic;
signal fifo_full_p1 : std_logic;
begin
fifo_empty_i <= addr_i(ADDR_BITS);
Addr(0 to ADDR_BITS-1) <= addr_i(ADDR_BITS-1 downto 0);
FIFO_Empty <= fifo_empty_i;
num_to_reread_zeroext <= '0' & Num_To_Reread;
----------------------------------------------------------------------------
-- The FIFO address counter. Addresses the next element to be read.
-- All ones when the FIFO is empty.
----------------------------------------------------------------------------
CNTR_INCR_DECR_ADDN_F_I : entity lib_srl_fifo_v1_0.cntr_incr_decr_addn_f
generic map (
C_SIZE => ADDR_BITS + 1,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
Incr => FIFO_Write,
Decr => FIFO_Read,
N_to_add => num_to_reread_zeroext,
Cnt => addr_i,
Cnt_p1 => addr_i_p1
);
----------------------------------------------------------------------------
-- The dynamic shift register that holds the FIFO elements.
----------------------------------------------------------------------------
DYNSHREG_F_I : entity lib_srl_fifo_v1_0.dynshreg_f
generic map (
C_DEPTH => C_DEPTH,
C_DWIDTH => C_DWIDTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Clken => FIFO_Write,
Addr => addr_i(ADDR_BITS-1 downto 0),
Din => Data_In,
Dout => Data_Out
);
----------------------------------------------------------------------------
-- Full flag.
----------------------------------------------------------------------------
fifo_full_p1 <= '1' when ( addr_i_p1
= std_logic_vector(
TO_UNSIGNED(C_DEPTH-1, ADDR_BITS+1)
)
)
else '0';
FULL_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset='1' then
FIFO_Full <= '0';
else
FIFO_Full <= fifo_full_p1;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Underflow detection.
----------------------------------------------------------------------------
UNDERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
underflow_i <= '0';
elsif underflow_i = '1' then
underflow_i <= '1'; -- Underflow sticks until reset
else
underflow_i <= fifo_empty_i and FIFO_Read;
end if;
end if;
end process;
Underflow <= underflow_i;
----------------------------------------------------------------------------
-- Overflow detection.
-- The only case of non-erroneous operation for which addr_i (including
-- the high-order bit used as the empty flag) taken as an unsigned value
-- may be greater than or equal to C_DEPTH is when the FIFO is empty.
-- No overflow is possible when FIFO_Read, since Num_To_Reread is
-- overriden in this case and the number elements can at most remain
-- unchanged (that being when there is a simultaneous FIFO_Write).
-- However, when there is no FIFO_Read and there is either a
-- FIFO_Write or a restoration of one or more read elements, or both, then
-- addr_i, extended by the carry-out bit, becoming greater than
-- or equal to C_DEPTH indicates an overflow.
----------------------------------------------------------------------------
OVERFLOW_PROCESS: process (Clk)
begin
if Clk'event and Clk='1' then
if Reset = '1' then
overflow_i <= '0';
elsif overflow_i = '1' then
overflow_i <= '1'; -- Overflow sticks until Reset
elsif FIFO_Read = '0' and
(FIFO_Write= '1' or bitwise_or(Num_To_Reread)='1') and
UNSIGNED(addr_i_p1) >= C_DEPTH then
overflow_i <= '1';
else
overflow_i <= '0';
end if;
end if;
end process;
Overflow <= overflow_i;
end architecture imp;
| gpl-2.0 |
sukinull/hls_stream | Vivado/example.hls/example.hls.srcs/sources_1/ipshared/xilinx.com/proc_sys_reset_v5_0/7820e39a/hdl/src/vhdl/lpf.vhd | 23 | 17838 | -------------------------------------------------------------------------------
-- lpf - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: lpf.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/08/01 -- First Release
--
-- KC 02/25/2002 -- Added Dcm_locked as an input
-- -- Added Power on reset srl_time_out
--
-- KC 08/26/2003 -- Added attribute statements for power on
-- reset SRL
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library lib_cdc_v1_0;
--use lib_cdc_v1_0.all;
library Unisim;
use Unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
--
-- Definition of Ports:
-- Slowest_sync_clk -- Clock
-- External_System_Reset -- External Reset Input
-- Auxiliary_System_Reset -- Auxiliary Reset Input
-- Dcm_locked -- DCM Locked, hold system in reset until 1
-- Lpf_reset -- Low Pass Filtered Output
--
-------------------------------------------------------------------------------
entity lpf is
generic(
C_EXT_RST_WIDTH : Integer;
C_AUX_RST_WIDTH : Integer;
C_EXT_RESET_HIGH : std_logic;
C_AUX_RESET_HIGH : std_logic
);
port(
MB_Debug_Sys_Rst : in std_logic;
Dcm_locked : in std_logic;
External_System_Reset : in std_logic;
Auxiliary_System_Reset : in std_logic;
Slowest_Sync_Clk : in std_logic;
Lpf_reset : out std_logic
);
end lpf;
architecture imp of lpf is
component SRL16 is
-- synthesis translate_off
generic (
INIT : bit_vector );
-- synthesis translate_on
port (D : in std_logic;
CLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16;
constant CLEAR : std_logic := '0';
signal exr_d1 : std_logic := '0'; -- delayed External_System_Reset
signal exr_lpf : std_logic_vector(0 to C_EXT_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal asr_d1 : std_logic := '0'; -- delayed Auxiliary_System_Reset
signal asr_lpf : std_logic_vector(0 to C_AUX_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal exr_and : std_logic := '0'; -- varible input width "and" gate
signal exr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal asr_and : std_logic := '0'; -- varible input width "and" gate
signal asr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal lpf_int : std_logic := '0'; -- internal Lpf_reset
signal lpf_exr : std_logic := '0';
signal lpf_asr : std_logic := '0';
signal srl_time_out : std_logic;
attribute INIT : string;
attribute INIT of POR_SRL_I: label is "FFFF";
begin
Lpf_reset <= lpf_int;
-------------------------------------------------------------------------------
-- Power On Reset Generation
-------------------------------------------------------------------------------
-- This generates a reset for the first 16 clocks after a power up
-------------------------------------------------------------------------------
POR_SRL_I: SRL16
-- synthesis translate_off
generic map (
INIT => X"FFFF")
-- synthesis translate_on
port map (
D => '0',
CLK => Slowest_sync_clk,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
Q => srl_time_out);
-------------------------------------------------------------------------------
-- LPF_OUTPUT_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
--
--ACTIVE_HIGH_LPF_EXT: if (C_EXT_RESET_HIGH = '1') generate
--begin
LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
lpf_int <= lpf_exr or lpf_asr or srl_time_out or not Dcm_locked;
end if;
end process LPF_OUTPUT_PROCESS;
--end generate ACTIVE_HIGH_LPF_EXT;
--ACTIVE_LOW_LPF_EXT: if (C_EXT_RESET_HIGH = '0') generate
--begin
--LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- lpf_int <= not (lpf_exr or
-- lpf_asr or
-- srl_time_out)or
-- not Dcm_locked;
-- end if;
-- end process;
--end generate ACTIVE_LOW_LPF_EXT;
EXR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if exr_and = '1' then
lpf_exr <= '1';
elsif (exr_and = '0' and exr_nand = '1') then
lpf_exr <= '0';
end if;
end if;
end process EXR_OUTPUT_PROCESS;
ASR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if asr_and = '1' then
lpf_asr <= '1';
elsif (asr_and = '0' and asr_nand = '1') then
lpf_asr <= '0';
end if;
end if;
end process ASR_OUTPUT_PROCESS;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_EXT: if (C_EXT_RESET_HIGH /= '0') generate
begin
-----------------------------------
exr_d1 <= External_System_Reset or MB_Debug_Sys_Rst;
ACT_HI_EXT: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-----------------------------------
end generate ACTIVE_HIGH_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_EXT: if (C_EXT_RESET_HIGH = '0') generate
begin
exr_d1 <= not External_System_Reset or MB_Debug_Sys_Rst;
-------------------------------------
ACT_LO_EXT: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_AUX: if (C_AUX_RESET_HIGH /= '0') generate
begin
asr_d1 <= Auxiliary_System_Reset;
-------------------------------------
ACT_HI_AUX: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_HIGH_AUX;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_AUX: if (C_AUX_RESET_HIGH = '0') generate
begin
-------------------------------------
asr_d1 <= not Auxiliary_System_Reset;
ACT_LO_AUX: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_AUX;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
EXT_LPF: for i in 1 to C_EXT_RST_WIDTH - 1 generate
begin
----------------------------------------
EXT_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
exr_lpf(i) <= exr_lpf(i-1);
end if;
end process;
----------------------------------------
end generate EXT_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
EXT_LPF_AND : process (exr_lpf)
Variable loop_and : std_logic;
Variable loop_nand : std_logic;
Begin
loop_and := '1';
loop_nand := '1';
for j in 0 to C_EXT_RST_WIDTH - 1 loop
loop_and := loop_and and exr_lpf(j);
loop_nand := loop_nand and not exr_lpf(j);
End loop;
exr_and <= loop_and;
exr_nand <= loop_nand;
end process;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
AUX_LPF: for k in 1 to C_AUX_RST_WIDTH - 1 generate
begin
----------------------------------------
AUX_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
asr_lpf(k) <= asr_lpf(k-1);
end if;
end process;
----------------------------------------
end generate AUX_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
AUX_LPF_AND : process (asr_lpf)
Variable aux_loop_and : std_logic;
Variable aux_loop_nand : std_logic;
Begin
aux_loop_and := '1';
aux_loop_nand := '1';
for m in 0 to C_AUX_RST_WIDTH - 1 loop
aux_loop_and := aux_loop_and and asr_lpf(m);
aux_loop_nand := aux_loop_nand and not asr_lpf(m);
End loop;
asr_and <= aux_loop_and;
asr_nand <= aux_loop_nand;
end process;
end imp;
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/cmpy_v6_0/hdl/cmpy_v6_0_synth.vhd | 3 | 25975 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 17488)
`protect data_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/lab_4/part_1/ip/fft/floating_point_v7_0/hdl/flt_recip/flt_recip_eval.vhd | 2 | 41947 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 29312)
`protect data_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/lab_4/part_1/ip/fft/floating_point_v7_0/hdl/shared/delay.vhd | 2 | 11968 | `protect begin_protected
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/mono_radio/ip/bram/blk_mem_gen_v8_2/hdl/blk_mem_gen_prim_width.vhd | 11 | 71859 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 51456)
`protect data_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/stereo_radio/ip/bram/blk_mem_gen_v8_2/hdl/blk_mem_gen_prim_width.vhd | 11 | 71859 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 51456)
`protect data_block
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| gpl-2.0 |
keith-epidev/VHDL-lib | top/lab_7/part_3/ip/clk_182/clk_182_stub.vhdl | 1 | 1109 | -- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Fri May 9 13:48:22 2014
-- Host : macbook running 64-bit Arch Linux
-- Command : write_vhdl -force -mode synth_stub
-- /home/keith/Documents/VHDL-lib/top/lab_7/part_3/ip/clk_182/clk_182_stub.vhdl
-- Design : clk_182
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk_182 is
Port (
clk_200MHz : in STD_LOGIC;
clk_182MHz : out STD_LOGIC;
locked : out STD_LOGIC
);
end clk_182;
architecture stub of clk_182 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_200MHz,clk_182MHz,locked";
begin
end;
| gpl-2.0 |
keith-epidev/VHDL-lib | top/lab_7/part_3/ip/xfft/xfft_v9_0/hdl/r2_tw_addr.vhd | 3 | 45947 | `protect begin_protected
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/mono_radio/ip/xfft/xfft_v9_0/hdl/r2_tw_addr.vhd | 3 | 45947 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 32272)
`protect data_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/lab_7/part_3/ip/xfft/c_addsub_v12_0/hdl/c_addsub_v12_0_fabric_legacy.vhd | 3 | 16399 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10400)
`protect data_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/lab_4/part_1/ip/clk_base/clk_base_funcsim.vhdl | 10 | 8525 | -- Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013
-- Date : Sat Mar 15 17:18:29 2014
-- Host : macbook running 64-bit Arch Linux
-- Command : write_vhdl -force -mode funcsim
-- /home/keith/Documents/VHDL-lib/top/lab_2/part_1/build/lab2_part1.srcs/sources_1/ip/clk_base/clk_base_funcsim.vhdl
-- Design : clk_base
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity clk_baseclk_base_clk_wiz is
port (
clk_raw : in STD_LOGIC;
clk_100MHz : out STD_LOGIC;
clk_250MHz : out STD_LOGIC;
locked : out STD_LOGIC
);
end clk_baseclk_base_clk_wiz;
architecture STRUCTURE of clk_baseclk_base_clk_wiz is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal clk_100MHz_clk_base : STD_LOGIC;
signal clk_250MHz_clk_base : STD_LOGIC;
signal clk_raw_clk_base : STD_LOGIC;
signal clkfbout_buf_clk_base : STD_LOGIC;
signal clkfbout_clk_base : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute box_type : string;
attribute box_type of clkf_buf : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute box_type of clkin1_ibufg : label is "PRIMITIVE";
attribute box_type of clkout1_buf : label is "PRIMITIVE";
attribute box_type of clkout2_buf : label is "PRIMITIVE";
attribute box_type of mmcm_adv_inst : label is "PRIMITIVE";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_clk_base,
O => clkfbout_buf_clk_base
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_raw,
O => clk_raw_clk_base
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_100MHz_clk_base,
O => clk_100MHz
);
clkout2_buf: unisim.vcomponents.BUFG
port map (
I => clk_250MHz_clk_base,
O => clk_250MHz
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 10.000000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 10.000000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 4,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.000000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_clk_base,
CLKFBOUT => clkfbout_clk_base,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_raw_clk_base,
CLKIN2 => \<const0>\,
CLKINSEL => \<const1>\,
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_100MHz_clk_base,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => clk_250MHz_clk_base,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6) => \<const0>\,
DADDR(5) => \<const0>\,
DADDR(4) => \<const0>\,
DADDR(3) => \<const0>\,
DADDR(2) => \<const0>\,
DADDR(1) => \<const0>\,
DADDR(0) => \<const0>\,
DCLK => \<const0>\,
DEN => \<const0>\,
DI(15) => \<const0>\,
DI(14) => \<const0>\,
DI(13) => \<const0>\,
DI(12) => \<const0>\,
DI(11) => \<const0>\,
DI(10) => \<const0>\,
DI(9) => \<const0>\,
DI(8) => \<const0>\,
DI(7) => \<const0>\,
DI(6) => \<const0>\,
DI(5) => \<const0>\,
DI(4) => \<const0>\,
DI(3) => \<const0>\,
DI(2) => \<const0>\,
DI(1) => \<const0>\,
DI(0) => \<const0>\,
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => \<const0>\,
LOCKED => locked,
PSCLK => \<const0>\,
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => \<const0>\,
PSINCDEC => \<const0>\,
PWRDWN => \<const0>\,
RST => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity clk_base is
port (
clk_raw : in STD_LOGIC;
clk_100MHz : out STD_LOGIC;
clk_250MHz : out STD_LOGIC;
locked : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of clk_base : entity is true;
attribute core_generation_info : string;
attribute core_generation_info of clk_base : entity is "clk_base,clk_wiz_v5_1,{component_name=clk_base,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
end clk_base;
architecture STRUCTURE of clk_base is
begin
U0: entity work.clk_baseclk_base_clk_wiz
port map (
clk_100MHz => clk_100MHz,
clk_250MHz => clk_250MHz,
clk_raw => clk_raw,
locked => locked
);
end STRUCTURE;
| gpl-2.0 |
keith-epidev/VHDL-lib | top/lab_2/part_1/ip/clk_base/clk_base_funcsim.vhdl | 10 | 8525 | -- Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013
-- Date : Sat Mar 15 17:18:29 2014
-- Host : macbook running 64-bit Arch Linux
-- Command : write_vhdl -force -mode funcsim
-- /home/keith/Documents/VHDL-lib/top/lab_2/part_1/build/lab2_part1.srcs/sources_1/ip/clk_base/clk_base_funcsim.vhdl
-- Design : clk_base
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity clk_baseclk_base_clk_wiz is
port (
clk_raw : in STD_LOGIC;
clk_100MHz : out STD_LOGIC;
clk_250MHz : out STD_LOGIC;
locked : out STD_LOGIC
);
end clk_baseclk_base_clk_wiz;
architecture STRUCTURE of clk_baseclk_base_clk_wiz is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal clk_100MHz_clk_base : STD_LOGIC;
signal clk_250MHz_clk_base : STD_LOGIC;
signal clk_raw_clk_base : STD_LOGIC;
signal clkfbout_buf_clk_base : STD_LOGIC;
signal clkfbout_clk_base : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute box_type : string;
attribute box_type of clkf_buf : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute box_type of clkin1_ibufg : label is "PRIMITIVE";
attribute box_type of clkout1_buf : label is "PRIMITIVE";
attribute box_type of clkout2_buf : label is "PRIMITIVE";
attribute box_type of mmcm_adv_inst : label is "PRIMITIVE";
begin
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_clk_base,
O => clkfbout_buf_clk_base
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_raw,
O => clk_raw_clk_base
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_100MHz_clk_base,
O => clk_100MHz
);
clkout2_buf: unisim.vcomponents.BUFG
port map (
I => clk_250MHz_clk_base,
O => clk_250MHz
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 10.000000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 10.000000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 4,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.000000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_clk_base,
CLKFBOUT => clkfbout_clk_base,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_raw_clk_base,
CLKIN2 => \<const0>\,
CLKINSEL => \<const1>\,
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_100MHz_clk_base,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => clk_250MHz_clk_base,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6) => \<const0>\,
DADDR(5) => \<const0>\,
DADDR(4) => \<const0>\,
DADDR(3) => \<const0>\,
DADDR(2) => \<const0>\,
DADDR(1) => \<const0>\,
DADDR(0) => \<const0>\,
DCLK => \<const0>\,
DEN => \<const0>\,
DI(15) => \<const0>\,
DI(14) => \<const0>\,
DI(13) => \<const0>\,
DI(12) => \<const0>\,
DI(11) => \<const0>\,
DI(10) => \<const0>\,
DI(9) => \<const0>\,
DI(8) => \<const0>\,
DI(7) => \<const0>\,
DI(6) => \<const0>\,
DI(5) => \<const0>\,
DI(4) => \<const0>\,
DI(3) => \<const0>\,
DI(2) => \<const0>\,
DI(1) => \<const0>\,
DI(0) => \<const0>\,
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => \<const0>\,
LOCKED => locked,
PSCLK => \<const0>\,
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => \<const0>\,
PSINCDEC => \<const0>\,
PWRDWN => \<const0>\,
RST => \<const0>\
);
end STRUCTURE;
library IEEE; use IEEE.STD_LOGIC_1164.ALL;
library UNISIM; use UNISIM.VCOMPONENTS.ALL;
entity clk_base is
port (
clk_raw : in STD_LOGIC;
clk_100MHz : out STD_LOGIC;
clk_250MHz : out STD_LOGIC;
locked : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of clk_base : entity is true;
attribute core_generation_info : string;
attribute core_generation_info of clk_base : entity is "clk_base,clk_wiz_v5_1,{component_name=clk_base,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
end clk_base;
architecture STRUCTURE of clk_base is
begin
U0: entity work.clk_baseclk_base_clk_wiz
port map (
clk_100MHz => clk_100MHz,
clk_250MHz => clk_250MHz,
clk_raw => clk_raw,
locked => locked
);
end STRUCTURE;
| gpl-2.0 |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fir/axi_utils_v2_0/hdl/axi_utils_comps.vhd | 10 | 35937 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/lab_4/part_1/ip/bram/blk_mem_gen_v8_1/blk_mem_gen_v8_1_synth_comp.vhd | 27 | 18409 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11888)
`protect data_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/lab_2/part_4/ip/dds/dds_compiler_v6_0/hdl/raster_accum.vhd | 6 | 51369 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/lab_4/part_1/ip/fir/fir_funcsim.vhdl | 1 | 23407728 | null | gpl-2.0 |
keith-epidev/VHDL-lib | top/mono_radio/ip/xfft/c_shift_ram_v12_0/hdl/c_shift_ram_speedmux.vhd | 3 | 17436 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11168)
`protect data_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/mono_radio/ip/multi_QI/mult_gen_v12_0/hdl/ccm_syncmem.vhd | 12 | 14797 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 9216)
`protect data_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/lab_4/part_1/ip/fft/xfft_v9_0/hdl/arith_shift3.vhd | 2 | 8402 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4480)
`protect data_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/mono_radio/ip/dds/dds_compiler_v6_0/hdl/dds_compiler_v6_0.vhd | 4 | 25173 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16896)
`protect data_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/xfft_v9_0/hdl/r22_memory.vhd | 3 | 11340 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6656)
`protect data_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/lab_4/part_1/ip/fft/xfft_v9_0/hdl/so_run_addr_gen_rotator.vhd | 2 | 225106 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 164896)
`protect data_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/mono_radio/ip/xfft/xbip_dsp48_addsub_v3_0/hdl/xbip_dsp48_addsub_rtl.vhd | 7 | 22928 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15232)
`protect data_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/mono_radio/ip/dds/xbip_dsp48_addsub_v3_0/hdl/xbip_dsp48_addsub_rtl.vhd | 7 | 22928 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15232)
`protect data_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/stereo_radio/ip/bram/blk_mem_gen_v8_2/hdl/blk_mem_gen_getinit_pkg.vhd | 11 | 62911 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 44832)
`protect data_block
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| gpl-2.0 |
keith-epidev/VHDL-lib | top/lab_7/part_3/ip/bram/blk_mem_gen_v8_2/hdl/blk_mem_gen_getinit_pkg.vhd | 11 | 62911 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 44832)
`protect data_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/mono_radio/ip/fir_lp_15kHz/xbip_utils_v3_0/hdl/xcc_utils_v3_0.vhd | 20 | 7255 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 3632)
`protect data_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/stereo_radio/ip/fir_bp_lr/xbip_utils_v3_0/hdl/xcc_utils_v3_0.vhd | 20 | 7255 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 3632)
`protect data_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/mono_radio/ip/xfft/xbip_utils_v3_0/hdl/xcc_utils_v3_0.vhd | 20 | 7255 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 3632)
`protect data_block
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| gpl-2.0 |
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| gpl-2.0 |
keith-epidev/VHDL-lib | top/mono_radio/ip/clk_adc/clk_adc.vhd | 4 | 4650 | -- file: clk_adc.vhd
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-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___250.000____236.250______50.0_______89.528_____85.928
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_____________250____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_adc is
port
(-- Clock in ports
clk_in1_p : in std_logic;
clk_in1_n : in std_logic;
-- Clock out ports
clk_250Mhz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end clk_adc;
architecture xilinx of clk_adc is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_adc,clk_wiz_v5_1,{component_name=clk_adc,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=4.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
component clk_adc_clk_wiz
port
(-- Clock in ports
clk_in1_p : in std_logic;
clk_in1_n : in std_logic;
-- Clock out ports
clk_250Mhz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end component;
begin
U0: clk_adc_clk_wiz
port map (
-- Clock in ports
clk_in1_p => clk_in1_p,
clk_in1_n => clk_in1_n,
-- Clock out ports
clk_250Mhz => clk_250Mhz,
-- Status and control signals
locked => locked
);
end xilinx;
| gpl-2.0 |
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/xbip_dsp48_wrapper_v3_0/hdl/xbip_dsp48a_wrapper_v3_0.vhd | 7 | 18409 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11888)
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| gpl-2.0 |
keith-epidev/VHDL-lib | top/stereo_radio/ip/multi_QI/mult_gen_v12_0/hdl/hybrid.vhd | 12 | 86278 | `protect begin_protected
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/lab_7/part_3/ip/xfft/xfft_v9_0/hdl/r4_control.vhd | 3 | 63948 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 45600)
`protect data_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/lab_7/part_3/ip/xfft/cmpy_v6_0/hdl/cmpy_mux2to1.vhd | 3 | 9091 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4992)
`protect data_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/mono_radio/ip/xfft/cmpy_v6_0/hdl/cmpy_mux2to1.vhd | 3 | 9091 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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BFI9aNXdYQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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xZySrgc3x8ZIdtP7y0o=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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CuR934CvAwaxXKgGZ2gh5P85nQ5Tp21bNMMzDw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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Ydv7bWufrtR2YIRsdgU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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DtaBlGekvQ+1z68BoGBwRkmTYjGwsroSsSzZIg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4992)
`protect data_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/xfft_v9_0/hdl/xfft_v9_0_b.vhd | 3 | 58761 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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72J2MmtuHQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 41760)
`protect data_block
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| gpl-2.0 |
keith-epidev/VHDL-lib | top/stereo_radio/ip/multi_fft/mult_gen_v12_0/hdl/cc_compare.vhd | 12 | 10907 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/dds/dds_compiler_v6_0/hdl/pipe_add.vhd | 6 | 8921 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4864)
`protect data_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/lab_4/part_1/ip/dds/dds_compiler_v6_0/hdl/pipe_add.vhd | 6 | 8921 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4864)
`protect data_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/lab_3/part_2/ip/dds/dds_compiler_v6_0/hdl/pipe_add.vhd | 6 | 8921 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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g4NRM1aTacHDo5dlg/0uBjh4pLfTG4usVOh/WsFncNHD9KYMc+mBZ7obB+yOaD96rEBGkNMyzocj
uKEXrtawvmlp0jAL3Ms=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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pER9+iDTaIyDS6dhnfavjAHFxkm4OV5VI6HLKmQ4tAkd2bZ0PkZiufMley0A1OS4NtoiTE2yMM0r
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4864)
`protect data_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/xfft_v9_0/hdl/cnt_sat.vhd | 2 | 12248 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7328)
`protect data_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/lab_7/part_3/ip/xfft/floating_point_v7_0/hdl/flt_exp/flt_exp_ccm.vhd | 3 | 19013 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12336)
`protect data_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/mono_radio/ip/xfft/floating_point_v7_0/hdl/flt_exp/flt_exp_ccm.vhd | 3 | 19013 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12336)
`protect data_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/mono_radio/ip/fir_lp_15kHz/fir_compiler_v7_1/hdl/muxf_bus.vhd | 8 | 8183 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4320)
`protect data_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/lab_4/part_1/ip/fir/fir_compiler_v7_1/hdl/fir_compiler_v7_1_viv.vhd | 2 | 86668 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 62416)
`protect data_block
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ZA==
`protect end_protected
| gpl-2.0 |
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