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tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc982.vhd | 4 | 1885 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc982.vhd,v 1.2 2001-10-26 16:30:29 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s03b00x00p05n01i00982ent IS
port (signal a,b : in integer; c,d : out integer);
END c06s03b00x00p05n01i00982ent;
ARCHITECTURE c06s03b00x00p05n01i00982arch OF c06s03b00x00p05n01i00982ent IS
BEGIN
TESTING: PROCESS
type some_record is
record
x1,x2,x3,x4,x5,x6,x7,x8 : integer;
y : boolean;
end record;
variable rec1,rec2,rec3 : some_record;
BEGIN
rec1.x5 := 5;
rec1.x7 := a;
rec1.y := true;
WAIT for 1 ns;
rec2 := rec1.all;
WAIT for 1 ns;
assert FALSE
report "***FAILED TEST: c06s03b00x00p05n01i00982 - Illegal record selected name."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s03b00x00p05n01i00982arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/non_compliant/analyzer_failure/tc3031.vhd | 4 | 1612 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3031.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ARCHITECTURE c11s04b00x00p02n01i03031arch OF c11s04b00x00p02n01i03031ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c11s04b00x00p02n01i03031 - A primary unit must be analyzed prior to the analysis of any corresponding secondary unit."
severity ERROR;
wait;
END PROCESS TESTING;
END c11s04b00x00p02n01i03031arch;
ENTITY c11s04b00x00p02n01i03031ent IS
END c11s04b00x00p02n01i03031ent;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/billowitch/compliant/tc782.vhd | 4 | 2350 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc782.vhd,v 1.2 2001-10-26 16:30:00 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x02p12n04i00782ent_a IS
port (
C2 : inout Bit;
C3 : linkage Bit;
C4 : out Bit;
C5 : Buffer Bit
);
END c01s01b01x02p12n04i00782ent_a;
ARCHITECTURE c01s01b01x02p12n04i00782arch_a OF c01s01b01x02p12n04i00782ent_a IS
BEGIN
END c01s01b01x02p12n04i00782arch_a;
ENTITY c01s01b01x02p12n04i00782ent IS
port (
A2 : inout Bit;
A3 : linkage Bit;
A4 : out Bit;
A5 : Buffer Bit
) ;
END c01s01b01x02p12n04i00782ent;
ARCHITECTURE c01s01b01x02p12n04i00782arch OF c01s01b01x02p12n04i00782ent IS
component c01s01b01x02p12n04i00782ent_b
port (
C2 : inout Bit;
C3 : linkage Bit;
C4 : out Bit;
C5 : Buffer Bit
);
end component;
for L : c01s01b01x02p12n04i00782ent_b use entity work.c01s01b01x02p12n04i00782ent_a(c01s01b01x02p12n04i00782arch_a);
BEGIN
L : c01s01b01x02p12n04i00782ent_b port map ( C2 => open, C3 => open, C4 => open, C5 => open );
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c01s01b01x02p12n04i00782"
severity NOTE;
wait;
END PROCESS TESTING;
END c01s01b01x02p12n04i00782arch;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_04_tb_04_03.vhd | 4 | 1583 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_04_tb_04_03.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity test_bench_04_03 is
end entity test_bench_04_03;
library ch4_pkgs;
use ch4_pkgs.pk_04_02.all;
architecture test_byte_swap_behavior of test_bench_04_03 is
signal input, output : halfword := x"0000";
begin
dut : entity work.byte_swap(behavior)
port map ( input => input, output => output );
stumulus : process is
begin
wait for 10 ns;
input <= x"ff00"; wait for 10 ns;
input <= x"00ff"; wait for 10 ns;
input <= x"aa33"; wait for 10 ns;
wait;
end process stumulus;
end architecture test_byte_swap_behavior;
| gpl-2.0 |
tgingold/ghdl | testsuite/vests/vhdl-93/ashenden/compliant/ch_20_ch_20_06.vhd | 4 | 7463 |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_20_ch_20_06.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ch_20_06 is
end entity ch_20_06;
----------------------------------------------------------------
use std.textio.all;
architecture test of ch_20_06 is
subtype encoding_type is bit_vector(1 downto 0);
attribute encoding : encoding_type;
begin
process1 : process is
-- code from book:
type controller_state is (idle, active, fail_safe);
type load_level is (idle, busy, overloaded);
attribute encoding of idle [ return controller_state ] : literal is b"00";
attribute encoding of active [ return controller_state ] : literal is b"01";
attribute encoding of fail_safe [ return controller_state ] : literal is b"10";
-- end of code from book
variable L : line;
begin
write(L, string'("process1"));
writeline(output, L);
write(L, idle [ return controller_state ] ' encoding);
writeline(output, L);
write(L, active [ return controller_state ] ' encoding);
writeline(output, L);
write(L, fail_safe [ return controller_state ] ' encoding);
writeline(output, L);
wait;
end process process1;
process2 : process is
type controller_state is (idle, active, fail_safe);
type load_level is (idle, busy, overloaded);
attribute encoding of idle : literal is b"11";
variable L : line;
begin
write(L, string'("process2"));
writeline(output, L);
write(L, idle [ return controller_state ] ' encoding);
writeline(output, L);
write(L, idle [ return load_level ] ' encoding);
writeline(output, L);
wait;
end process process2;
end architecture test;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-sp605/svga2ch7301c.vhd | 2 | 6789 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: svga2ch7301c
-- File: svga2ch7301c.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- [email protected]
--
-- Description: Converter inteneded to connect a SVGACTRL core to a Chrontel
-- CH7301C DVI transmitter. Multiplexes data and generates clocks.
-- Tailored for use on the Xilinx ML50x boards with Leon3/GRLIB
-- template designs.
--
-- This multiplexer has been developed for use with the Chrontel CH7301C DVI
-- transmitter. Supported multiplexed formats are, as in the CH7301 datasheet:
--
-- IDF Description
-- 0 12-bit multiplexed RGB input (24-bit color), (scheme 1)
-- 1 12-bit multiplexed RGB2 input (24-bit color), (scheme 2)
-- 2 8-bit multiplexed RGB input (16-bit color, 565)
-- 3 8-bit multiplexed RGB input (15-bit color, 555)
--
-- This core assumes a 100 MHz input clock on the 'clk' input.
--
-- If the generic 'dynamic' is non-zero the core uses the value vgao.bitdepth
-- to decide if multiplexing should be done according to IDF 0 or IDF 2.
-- vago.bitdepth = "11" gives IDF 0, others give IDF2.
-- The 'idf' generic is not used when the 'dynamic' generic is non-zero.
-- Note that if dynamic selection is enabled you will need to reconfigure
-- the DVI transmitter when the VGA core changes bit depth.
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.misc.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity svga2ch7301c is
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
vgao : in apbvga_out_type;
vgaclk : in std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end svga2ch7301c;
architecture rtl of svga2ch7301c is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
signal nvgaclk : std_ulogic;
signal vcc, gnd : std_logic;
signal d0, d1 : std_logic_vector(11 downto 0);
signal red, green, blue : std_logic_vector(7 downto 0);
signal lvgaclk, lclk40, lclk65, lclk40_65 : std_ulogic;
signal clkval : std_logic_vector(1 downto 0);
begin -- rtl
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------
-- RGB data multiplexer
-----------------------------------------------------------------------------
red <= vgao.video_out_r;
green <= vgao.video_out_g;
blue <= vgao.video_out_b;
static: if dynamic = 0 generate
idf0: if (idf = 0) generate
d0 <= green(3 downto 0) & blue(7 downto 0);
d1 <= red(7 downto 0) & green(7 downto 4);
end generate;
idf1: if (idf = 1) generate
d0 <= green(4 downto 2) & blue(7 downto 3) & green(0) & blue(2 downto 0);
d1 <= red(7 downto 3) & green(7 downto 5) & red(2 downto 0) & green(1);
end generate;
idf2: if (idf = 2) generate
d0(11 downto 4) <= green(4 downto 2) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= red(7 downto 3) & green(7 downto 5);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate;
idf3: if (idf = 3) generate
d0(11 downto 4) <= green(5 downto 3) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= '0' & red(7 downto 3) & green(7 downto 6);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate idf3;
-- DDR regs
dataregs: for i in 11 downto (4*(idf/2)) generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk, c2 => nvgaclk, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
nvgaclk <= not vgaclk;
nostatic: if dynamic /= 0 generate
d0 <= green(3 downto 0) & blue(7 downto 0) when vgao.bitdepth = "11" else
green(4 downto 2) & blue(7 downto 3) & "0000";
d1 <= red(7 downto 0) & green(7 downto 4) when vgao.bitdepth = "11" else
red(7 downto 3) & green(7 downto 5) & "0000";
dataregs: for i in 11 downto 0 generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk, c2 => nvgaclk, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
-----------------------------------------------------------------------------
-- Sync signals
-----------------------------------------------------------------------------
process (vgaclk)
begin -- process
if rising_edge(vgaclk) then
hsync <= vgao.hsync;
vsync <= vgao.vsync;
de <= vgao.blank;
end if;
end process;
-----------------------------------------------------------------------------
-- Clock generation
-----------------------------------------------------------------------------
ddroreg_p : ddr_oreg generic map (tech)
port map (q => dclk_p, c1 => vgaclk, c2 => nvgaclk, ce => vcc,
d1 => vcc, d2 => gnd, r => gnd, s => gnd);
ddroreg_n : ddr_oreg generic map (tech)
port map (q => dclk_n, c1 => vgaclk, c2 => nvgaclk, ce => vcc,
d1 => gnd, d2 => vcc, r => gnd, s => gnd);
end rtl;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-altera-ep2s60-ddr/testbench.vhd | 1 | 10590 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 8; -- rom data width (8/32)
romdepth : integer := 23; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 1 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal clkout, pllref : std_ulogic;
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(23 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_ulogic;
signal iosn : std_ulogic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal ssram_ce1n : std_logic;
signal ssram_ce2 : std_logic;
signal ssram_ce3n : std_logic;
signal ssram_wen : std_logic;
signal ssram_bw : std_logic_vector (0 to 3);
signal ssram_oen : std_ulogic;
signal ssaddr : std_logic_vector(20 downto 2);
signal ssdata : std_logic_vector(31 downto 0);
signal ssram_clk : std_ulogic;
signal ssram_adscn : std_ulogic;
signal ssram_adsp_n : std_ulogic;
signal ssram_adv_n : std_ulogic;
signal datazz : std_logic_vector(3 downto 0);
-- ddr memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clkin : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (1 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (1 downto 0); -- ddr dqs
signal ddr_dqs2 : std_logic_vector (1 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq, ddr_dq2 : std_logic_vector (15 downto 0); -- ddr data
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
--signal txd2, rxd2 : std_ulogic;
-- for smc lan chip
signal eth_aen : std_ulogic; -- for smsc eth
signal eth_readn : std_ulogic; -- for smsc eth
signal eth_writen : std_ulogic; -- for smsc eth
signal eth_nbe : std_logic_vector(3 downto 0); -- for smsc eth
signal eth_datacsn : std_ulogic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(31 downto 0);
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
ddr_clkin <= not clk after ct * 1 ns;
rst <= dsurst;
dsubren <= '1'; rxd1 <= '1';
dqs2delay : delay_wire
generic map(data_width => ddr_dqs'length, delay_atob => 3.0, delay_btoa => 1.0)
port map(a => ddr_dqs, b => ddr_dqs2);
ddr2delay : delay_wire
generic map(data_width => ddr_dq'length, delay_atob => 3.0, delay_btoa => 1.0)
port map(a => ddr_dq, b => ddr_dq2);
-- ddr_dqs <= (others => 'L');
d3 : entity work.leon3mp generic map (fabtech, memtech, padtech, clktech,
ncpu, disas, dbguart, pclow )
port map (rst, clk, error,
address, data, romsn, oen, writen, open, open,
ssram_ce1n, ssram_ce2, ssram_ce3n, ssram_wen, ssram_bw, ssram_oen, ssaddr, ssdata,
ssram_clk, ssram_adscn, ssram_adsp_n, ssram_adv_n, iosn,
ddr_clkin, ddr_clk, ddr_clkb, ddr_cke, ddr_csb, ddr_web, ddr_rasb,
ddr_casb, ddr_dm, ddr_dqs2, ddr_ad, ddr_ba, ddr_dq2,
dsubren, dsuact, rxd1, txd1,
eth_aen, eth_readn, eth_writen, eth_nbe);
ddr0 : mt46v16m16
generic map (index => -1, fname => sdramfile)
port map(
Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad,
Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
Dm => ddr_dm(1 downto 0));
datazz <= "HHHH";
ssram0 : cy7c1380d generic map (fname => sramfile)
port map(
ioDq(35 downto 32) => datazz, ioDq(31 downto 0) => ssdata,
iAddr => ssaddr(20 downto 2), iMode => gnd,
inGW => vcc, inBWE => ssram_wen, inADV => ssram_adv_n,
inADSP => ssram_adsp_n, inADSC => ssram_adscn,
iClk => ssram_clk,
inBwa => ssram_bw(3), inBwb => ssram_bw(2),
inBwc => ssram_bw(1), inBwd => ssram_bw(0),
inOE => ssram_oen, inCE1 => ssram_ce1n,
iCE2 => ssram_ce2, inCE3 => ssram_ce3n, iZz => gnd);
-- 8 bit prom
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24),
romsn, writen, oen);
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
sd <= buskeep(sd), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, open);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-2.0 |
borti4938/sd2snes | verilog/sd2snes_sdd1/Input_Manager.vhd | 2 | 17475 | ----------------------------------------------------------------------------------
-- Company: Traducciones Magno
-- Engineer: Magno
--
-- Create Date: 18.03.2018 18:59:09
-- Design Name:
-- Module Name: Input_Manager - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Input_Manager is
Port( clk : in STD_LOGIC;
-- control data
DMA_Conf_Valid : in STD_LOGIC;
DMA_In_Progress : in STD_LOGIC;
Header_Valid : out STD_LOGIC;
Header_BPP : out STD_LOGIC_VECTOR(1 downto 0);
Header_Context : out STD_LOGIC_VECTOR(1 downto 0);
-- data input from ROM
ROM_Data_tready : out STD_LOGIC;
ROM_Data_tvalid : in STD_LOGIC;
ROM_Data_tdata : in STD_LOGIC_VECTOR(15 downto 0);
ROM_Data_tkeep : in STD_LOGIC_VECTOR(1 downto 0);
-- Golomb decoded value
Decoded_Bit_tready : in STD_LOGIC;
Decoded_Bit_tuser : in STD_LOGIC_VECTOR(7 downto 0);
Decoded_Bit_tvalid : out STD_LOGIC;
Decoded_Bit_tdata : out STD_LOGIC;
Decoded_Bit_tlast : out STD_LOGIC );
end Input_Manager;
architecture Behavioral of Input_Manager is
COMPONENT FIFO_AXIS
Generic( FIFO_DEPTH : integer := 32 );
Port( clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din_tready : OUT STD_LOGIC;
din_tvalid : IN STD_LOGIC;
din_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
din_tkeep : IN STD_LOGIC_VECTOR(1 downto 0);
dout_tready : IN STD_LOGIC;
dout_tvalid : OUT STD_LOGIC;
dout_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC );
END COMPONENT;
COMPONENT Serializer
Port( clk : IN STD_LOGIC;
Rst : IN STD_LOGIC;
FIFO_tready : OUT STD_LOGIC;
FIFO_tvalid : IN STD_LOGIC;
FIFO_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Shift : IN STD_LOGIC;
Shift_cnt : IN STD_LOGIC_VECTOR(2 downto 0);
Serial_tvalid : OUT STD_LOGIC;
Serial_tdata : OUT STD_LOGIC_VECTOR(7 downto 0) );
END COMPONENT;
COMPONENT Golomb_N_Decoder
Generic( N : integer);
Port( clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din_tready : OUT STD_LOGIC;
din_tdata : IN STD_LOGIC_VECTOR(N DOWNTO 0);
din_tuser : OUT STD_LOGIC_VECTOR(2 downto 0);
dout_tready : IN STD_LOGIC;
dout_tdata : OUT STD_LOGIC;
dout_tlast : OUT STD_LOGIC);
END COMPONENT;
COMPONENT Golomb_0_Decoder
Port( clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din_tready : OUT STD_LOGIC;
din_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
din_tuser : OUT STD_LOGIC_VECTOR(2 downto 0);
dout_tready : IN STD_LOGIC;
dout_tdata : OUT STD_LOGIC;
dout_tlast : OUT STD_LOGIC);
END COMPONENT;
type TipoEstado is( WAIT_START, FILL_SERIALIZER, GET_HEADER, INIT_GOLOMB, WAIT_END);
signal estado : TipoEstado := WAIT_START;
signal Decoded_Bit_tvalid_i : STD_LOGIC := '0';
signal Decoded_Bit_tlast_i : STD_LOGIC := '0';
signal Decoded_Bit_tdata_i : STD_LOGIC := '0';
signal Decoded_Bit_tuser_i : STD_LOGIC_VECTOR(2 downto 0) := "000";
signal FIFO_tready : STD_LOGIC := '0';
signal FIFO_Full : STD_LOGIC := '1';
signal FIFO_tvalid : STD_LOGIC := '0';
signal FIFO_tdata : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal Bit_Shift_Rdy : STD_LOGIC := '0';
signal Bit_Shift_Cnt : STD_LOGIC_VECTOR(2 downto 0) := "000";
signal Bit_Serializer_tvalid : STD_LOGIC := '0';
signal Bit_Serializer_tdata : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal G0_Run_End : STD_LOGIC := '0';
signal G1_Run_End : STD_LOGIC := '0';
signal G2_Run_End : STD_LOGIC := '0';
signal G3_Run_End : STD_LOGIC := '0';
signal G4_Run_End : STD_LOGIC := '0';
signal G5_Run_End : STD_LOGIC := '0';
signal G6_Run_End : STD_LOGIC := '0';
signal G7_Run_End : STD_LOGIC := '0';
signal G0_din : STD_LOGIC_VECTOR(0 downto 0) := (others => '0');
signal G1_din : STD_LOGIC_VECTOR(1 downto 0) := (others => '0');
signal G2_din : STD_LOGIC_VECTOR(2 downto 0) := (others => '0');
signal G3_din : STD_LOGIC_VECTOR(3 downto 0) := (others => '0');
signal G4_din : STD_LOGIC_VECTOR(4 downto 0) := (others => '0');
signal G5_din : STD_LOGIC_VECTOR(5 downto 0) := (others => '0');
signal G6_din : STD_LOGIC_VECTOR(6 downto 0) := (others => '0');
signal G7_din : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal G0_shift : STD_LOGIC_VECTOR(2 downto 0) := (others => '0');
signal G1_shift : STD_LOGIC_VECTOR(2 downto 0) := (others => '0');
signal G2_shift : STD_LOGIC_VECTOR(2 downto 0) := (others => '0');
signal G3_shift : STD_LOGIC_VECTOR(2 downto 0) := (others => '0');
signal G4_shift : STD_LOGIC_VECTOR(2 downto 0) := (others => '0');
signal G5_shift : STD_LOGIC_VECTOR(2 downto 0) := (others => '0');
signal G6_shift : STD_LOGIC_VECTOR(2 downto 0) := (others => '0');
signal G7_shift : STD_LOGIC_VECTOR(2 downto 0) := (others => '0');
signal Decoded_G0_tready : STD_LOGIC := '0';
signal Decoded_G0_tdata : STD_LOGIC := '0';
signal Decoded_G0_tlast : STD_LOGIC := '0';
signal Decoded_G1_tready : STD_LOGIC := '0';
signal Decoded_G1_tdata : STD_LOGIC := '0';
signal Decoded_G1_tlast : STD_LOGIC := '0';
signal Decoded_G2_tready : STD_LOGIC := '0';
signal Decoded_G2_tdata : STD_LOGIC := '0';
signal Decoded_G2_tlast : STD_LOGIC := '0';
signal Decoded_G3_tready : STD_LOGIC := '0';
signal Decoded_G3_tdata : STD_LOGIC := '0';
signal Decoded_G3_tlast : STD_LOGIC := '0';
signal Decoded_G4_tready : STD_LOGIC := '0';
signal Decoded_G4_tdata : STD_LOGIC := '0';
signal Decoded_G4_tlast : STD_LOGIC := '0';
signal Decoded_G5_tready : STD_LOGIC := '0';
signal Decoded_G5_tdata : STD_LOGIC := '0';
signal Decoded_G5_tlast : STD_LOGIC := '0';
signal Decoded_G6_tready : STD_LOGIC := '0';
signal Decoded_G6_tdata : STD_LOGIC := '0';
signal Decoded_G6_tlast : STD_LOGIC := '0';
signal Decoded_G7_tready : STD_LOGIC := '0';
signal Decoded_G7_tdata : STD_LOGIC := '0';
signal Decoded_G7_tlast : STD_LOGIC := '0';
signal FSM_Reset : STD_LOGIC := '1';
signal FSM_Get_Header : STD_LOGIC := '0';
signal FSM_Load_Golomb : STD_LOGIC := '0';
signal Control_ILA : STD_LOGIC_VECTOR(35 downto 0);
signal DBG_Cnt : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
signal FIFO_Cnt : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
begin
-- FIFO for input words from ROM, that converts to byte data; FIFO is kept mid-full with 4 words
-- (64 bits); worst IO rate case is 8 output bits * 8 bits per G7 code = 64 bits = 8 byte
Input_Data : FIFO_AXIS
Generic map(32)
Port map(clk => clk,
srst => FSM_Reset,
din_tready => ROM_Data_tready,
din_tvalid => ROM_Data_tvalid,
din_tdata => ROM_Data_tdata,
din_tkeep => ROM_Data_tkeep,
dout_tready => FIFO_tready,
dout_tvalid => FIFO_tvalid,
dout_tdata => FIFO_tdata,
full => FIFO_Full);
-- convert input bytes to bitstream
Bitstream : Serializer
Port map(clk => clk,
Rst => FSM_Reset,
FIFO_tready => FIFO_tready,
FIFO_tvalid => FIFO_tvalid,
FIFO_tdata => FIFO_tdata,
Shift => Bit_Shift_Rdy,
Shift_cnt => Bit_Shift_Cnt,
Serial_tvalid => Bit_Serializer_tvalid,
Serial_tdata => Bit_Serializer_tdata );
-- process to register header configuration for decompression; one-cycle strobe signals
-- data is valid and decompression may start
Process( clk )
Begin
if rising_edge( clk ) then
if( FSM_Reset = '1' OR FSM_Get_Header = '0' ) then
Header_Valid <= '0';
else
Header_Valid <= '1';
Header_BPP <= Bit_Serializer_tdata(0) & Bit_Serializer_tdata(1);
Header_Context <= Bit_Serializer_tdata(2) & Bit_Serializer_tdata(3);
end if;
end if;
End Process;
-- serializer is updated when last bit in the run is out of any Golomb decoder or after reading header
Process( clk )
Begin
if rising_edge( clk ) then
if( FSM_Reset = '1' ) then
Bit_Shift_Rdy <= '0';
Bit_Shift_Cnt <= "000";
else
Bit_Shift_Rdy <= FSM_Load_Golomb OR G0_Run_End OR G1_Run_End OR G2_Run_End OR G3_Run_End OR
G4_Run_End OR G5_Run_End OR G6_Run_End OR G7_Run_End;
-- when header is already read, shift first 4 bits
if( FSM_Load_Golomb = '1' ) then
Bit_Shift_Cnt <= "011";
end if;
if( G0_Run_End = '1' ) then
Bit_Shift_Cnt <= G0_shift;
end if;
if( G1_Run_End = '1' ) then
Bit_Shift_Cnt <= G1_shift;
end if;
if( G2_Run_End = '1' ) then
Bit_Shift_Cnt <= G2_shift;
end if;
if( G3_Run_End = '1' ) then
Bit_Shift_Cnt <= G3_shift;
end if;
if( G4_Run_End = '1' ) then
Bit_Shift_Cnt <= G4_shift;
end if;
if( G5_Run_End = '1' ) then
Bit_Shift_Cnt <= G5_shift;
end if;
if( G6_Run_End = '1' ) then
Bit_Shift_Cnt <= G6_shift;
end if;
if( G7_Run_End = '1' ) then
Bit_Shift_Cnt <= G7_shift;
end if;
end if;
end if;
End Process;
-- select which Golomb decoder to request the bit to
Decoded_G0_tready <= Decoded_Bit_tuser(0) AND Decoded_Bit_tready;
Decoded_G1_tready <= Decoded_Bit_tuser(1) AND Decoded_Bit_tready;
Decoded_G2_tready <= Decoded_Bit_tuser(2) AND Decoded_Bit_tready;
Decoded_G3_tready <= Decoded_Bit_tuser(3) AND Decoded_Bit_tready;
Decoded_G4_tready <= Decoded_Bit_tuser(4) AND Decoded_Bit_tready;
Decoded_G5_tready <= Decoded_Bit_tuser(5) AND Decoded_Bit_tready;
Decoded_G6_tready <= Decoded_Bit_tuser(6) AND Decoded_Bit_tready;
Decoded_G7_tready <= Decoded_Bit_tuser(7) AND Decoded_Bit_tready;
-- data in for feeding Golomb decoders
G0_din <= Bit_Serializer_tdata(0 downto 0);
G1_din <= Bit_Serializer_tdata(1 downto 0);
G2_din <= Bit_Serializer_tdata(2 downto 0);
G3_din <= Bit_Serializer_tdata(3 downto 0);
G4_din <= Bit_Serializer_tdata(4 downto 0);
G5_din <= Bit_Serializer_tdata(5 downto 0);
G6_din <= Bit_Serializer_tdata(6 downto 0);
G7_din <= Bit_Serializer_tdata(7 downto 0);
-- Order 0 Golomb decoder
G0 : Golomb_0_Decoder
Port map(clk => clk,
rst => FSM_Reset,
din_tready => G0_Run_End,
din_tdata => G0_din,
din_tuser => G0_shift,
dout_tready => Decoded_G0_tready,
dout_tdata => Decoded_G0_tdata,
dout_tlast => Decoded_G0_tlast );
-- Order 1 Golomb decoder
G1 : Golomb_N_Decoder
Generic map( 1 )
Port map(clk => clk,
rst => FSM_Reset,
din_tready => G1_Run_End,
din_tdata => G1_din,
din_tuser => G1_shift,
dout_tready => Decoded_G1_tready,
dout_tdata => Decoded_G1_tdata,
dout_tlast => Decoded_G1_tlast );
-- Order 2 Golomb decoder
G2 : Golomb_N_Decoder
Generic map( 2 )
Port map(clk => clk,
rst => FSM_Reset,
din_tready => G2_Run_End,
din_tdata => G2_din,
din_tuser => G2_shift,
dout_tready => Decoded_G2_tready,
dout_tdata => Decoded_G2_tdata,
dout_tlast => Decoded_G2_tlast );
-- Order 3 Golomb decoder
G3 : Golomb_N_Decoder
Generic map( 3 )
Port map(clk => clk,
rst => FSM_Reset,
din_tready => G3_Run_End,
din_tdata => G3_din,
din_tuser => G3_shift,
dout_tready => Decoded_G3_tready,
dout_tdata => Decoded_G3_tdata,
dout_tlast => Decoded_G3_tlast );
-- Order 4 Golomb decoder
G4 : Golomb_N_Decoder
Generic map( 4 )
Port map(clk => clk,
rst => FSM_Reset,
din_tready => G4_Run_End,
din_tdata => G4_din,
din_tuser => G4_shift,
dout_tready => Decoded_G4_tready,
dout_tdata => Decoded_G4_tdata,
dout_tlast => Decoded_G4_tlast );
-- Order 5 Golomb decoder
G5 : Golomb_N_Decoder
Generic map( 5 )
Port map(clk => clk,
rst => FSM_Reset,
din_tready => G5_Run_End,
din_tdata => G5_din,
din_tuser => G5_shift,
dout_tready => Decoded_G5_tready,
dout_tdata => Decoded_G5_tdata,
dout_tlast => Decoded_G5_tlast );
-- Order 6 Golomb decoder
G6 : Golomb_N_Decoder
Generic map( 6 )
Port map(clk => clk,
rst => FSM_Reset,
din_tready => G6_Run_End,
din_tdata => G6_din,
din_tuser => G6_shift,
dout_tready => Decoded_G6_tready,
dout_tdata => Decoded_G6_tdata,
dout_tlast => Decoded_G6_tlast );
-- Order 7 Golomb decoder
G7 : Golomb_N_Decoder
Generic map( 7 )
Port map(clk => clk,
rst => FSM_Reset,
din_tready => G7_Run_End,
din_tdata => G7_din,
din_tuser => G7_shift,
dout_tready => Decoded_G7_tready,
dout_tdata => Decoded_G7_tdata,
dout_tlast => Decoded_G7_tlast );
Decoded_Bit_tvalid <= Decoded_Bit_tvalid_i;
Decoded_Bit_tdata <= Decoded_Bit_tdata_i;
Decoded_Bit_tlast <= Decoded_Bit_tlast_i;
Process(clk)
Begin
if rising_edge( clk ) then
if( FSM_Reset = '1' ) then
Decoded_Bit_tvalid_i <= '0';
Decoded_Bit_tdata_i <= '0';
Decoded_Bit_tlast_i <= '0';
else
Decoded_Bit_tvalid_i <= Decoded_Bit_tready;
-- multiplexor for routing Golomb decoded bit to module's output
if( Decoded_Bit_tready = '1' ) then
if( Decoded_Bit_tuser(0) = '1' ) then
Decoded_Bit_tdata_i <= Decoded_G0_tdata;
Decoded_Bit_tlast_i <= Decoded_G0_tlast;
end if;
if( Decoded_Bit_tuser(1) = '1' ) then
Decoded_Bit_tdata_i <= Decoded_G1_tdata;
Decoded_Bit_tlast_i <= Decoded_G1_tlast;
end if;
if( Decoded_Bit_tuser(2) = '1' ) then
Decoded_Bit_tdata_i <= Decoded_G2_tdata;
Decoded_Bit_tlast_i <= Decoded_G2_tlast;
end if;
if( Decoded_Bit_tuser(3) = '1' ) then
Decoded_Bit_tdata_i <= Decoded_G3_tdata;
Decoded_Bit_tlast_i <= Decoded_G3_tlast;
end if;
if( Decoded_Bit_tuser(4) = '1' ) then
Decoded_Bit_tdata_i <= Decoded_G4_tdata;
Decoded_Bit_tlast_i <= Decoded_G4_tlast;
end if;
if( Decoded_Bit_tuser(5) = '1' ) then
Decoded_Bit_tdata_i <= Decoded_G5_tdata;
Decoded_Bit_tlast_i <= Decoded_G5_tlast;
end if;
if( Decoded_Bit_tuser(6) = '1' ) then
Decoded_Bit_tdata_i <= Decoded_G6_tdata;
Decoded_Bit_tlast_i <= Decoded_G6_tlast;
end if;
if( Decoded_Bit_tuser(7) = '1' ) then
Decoded_Bit_tdata_i <= Decoded_G7_tdata;
Decoded_Bit_tlast_i <= Decoded_G7_tlast;
end if;
end if;
end if;
end if;
End Process;
-- FSM for controlling input data into the FIFO and serialized data to
-- Golomb decoders
Process( clk )
Begin
if rising_edge( clk ) then
case estado is
-- keep FIFO reset to avoid filling it with unneeded data;
-- when DMA configuration is valid, go to next step
when WAIT_START =>
if( DMA_Conf_Valid = '1' ) then
estado <= FILL_SERIALIZER;
end if;
-- wait for bit serializer to be ready
when FILL_SERIALIZER =>
if( Bit_Serializer_tvalid = '1' ) then
estado <= GET_HEADER;
end if;
-- read header from bitstream
when GET_HEADER =>
estado <= INIT_GOLOMB;
-- load Golomb decoders and header
when INIT_GOLOMB =>
estado <= WAIT_END;
-- monitor serializer's bit pointer to ask for new data; if DMA transfer
-- ends, go to reset state
when WAIT_END =>
if( DMA_In_Progress = '0' ) then
estado <= WAIT_START;
end if;
end case;
end if;
end Process;
-- reset FIFO while decompression is stopped
FSM_Reset <= '1' when estado = WAIT_START else '0';
-- enable register to capture header data
FSM_Get_Header <= '1' when estado = GET_HEADER else '0';
-- Golomb decoders are loaded with data at initialization
with estado select
FSM_Load_Golomb <= '1' when INIT_GOLOMB,
'0' when others;
end Behavioral;
| gpl-2.0 |
lynnieana/autosub_new_task_timingDemo | timingDemo/static/timingDemo_example.vhdl | 1 | 443 | ENTITY top IS END top;
ARCHITECTURE example OF top IS
SIGNAL w,x,y,z : integer := 0; -- initialised to 0 (zero)
BEGIN
p1 : PROCESS(z)
VARIABLE a : integer := 0; -- initialised to 0 (zero)
BEGIN
a := a + 100;
w <= w + 80;
x <= a + w AFTER 40 ns;
y <= a - w AFTER 60 ns;
END PROCESS;
p2: PROCESS
BEGIN
z <= (x + y) AFTER 70 ns;
--z <= x AFTER 70 ns;
WAIT ON x,y;
END PROCESS;
END example;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/jtag/jtagcom.vhd | 1 | 7731 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: jtagcom
-- File: jtagcom.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Modified: J. Gaisler, K. Glembo, J. Andersson - Aeroflex Gaisler
-- Description: JTAG Debug Interface with AHB master interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.libjtagcom.all;
use gaisler.misc.all;
entity jtagcom is
generic (
isel : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 2;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3;
reread : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
tapo : in tap_out_type;
tapi : out tap_in_type;
dmao : in ahb_dma_out_type;
dmai : out ahb_dma_in_type;
tck : in std_ulogic;
trst : in std_ulogic
);
attribute sync_set_reset of rst : signal is "true";
end;
architecture rtl of jtagcom is
constant ADDBITS : integer := 10;
constant NOCMP : boolean := (isel /= 0);
type state_type is (shft, ahb, nxt_shft);
type reg_type is record
addr : std_logic_vector(34 downto 0);
data : std_logic_vector(32 downto 0);
state : state_type;
tcktog: std_logic_vector(nsync-1 downto 0);
tcktog2: std_ulogic;
tdishft: std_ulogic;
trst : std_logic_vector(nsync-1 downto 0);
tdi : std_logic_vector(nsync-1 downto 0);
shift : std_logic_vector(nsync-1 downto 0);
shift2: std_ulogic;
upd : std_logic_vector(nsync-1 downto 0);
upd2 : std_ulogic;
asel : std_logic_vector(nsync-1 downto 0);
dsel : std_logic_vector(nsync-1 downto 0);
seq : std_ulogic;
holdn : std_ulogic;
end record;
type tckreg_type is record
tcktog: std_ulogic;
tdi: std_ulogic;
tdor: std_ulogic;
end record;
signal nexttdo: std_ulogic;
signal r, rin : reg_type;
signal tr: tckreg_type;
begin
comb : process (rst, r, tapo, dmao, tr)
variable v : reg_type;
variable redge0 : std_ulogic;
variable vdmai : ahb_dma_in_type;
variable asel, dsel : std_ulogic;
variable vtapi : tap_in_type;
variable write, seq : std_ulogic;
variable vnexttdo: std_ulogic;
begin
v := r;
if NOCMP then
asel := tapo.asel; dsel := tapo.dsel;
else
if tapo.inst = conv_std_logic_vector(ainst, 8) then asel := '1'; else asel := '0'; end if;
if tapo.inst = conv_std_logic_vector(dinst, 8) then dsel := '1'; else dsel := '0'; end if;
end if;
vtapi.en := asel or dsel;
vnexttdo := '0';
if asel='1' then
if tapo.shift='1' then
vnexttdo := r.addr(1);
else
vnexttdo := r.addr(0);
end if;
else
if tapo.shift='1' then
vnexttdo := r.data(1);
else
vnexttdo := r.data(0);
end if;
if reread /= 0 then vnexttdo := vnexttdo and r.holdn; end if;
end if;
nexttdo <= vnexttdo;
vtapi.tdo := tr.tdor;
write := r.addr(34); seq := r.seq;
v.tcktog(0) := r.tcktog(nsync-1); v.tcktog(nsync-1) := tr.tcktog;
v.tcktog2 := r.tcktog(0); v.shift2 := r.shift(0);
v.trst(0) := r.trst(nsync-1); v.trst(nsync-1) := tapo.reset;
v.tdi(0) := r.tdi(nsync-1); v.tdi(nsync-1) := tr.tdi;
v.shift(0) := r.shift(nsync-1); v.shift(nsync-1) := tapo.shift;
v.upd(0) := r.upd(nsync-1); v.upd(nsync-1) := tapo.upd;
v.upd2 := r.upd(0);
v.asel(0) := r.asel(nsync-1); v.asel(nsync-1) := asel;
v.dsel(0) := r.dsel(nsync-1); v.dsel(nsync-1) := dsel;
redge0 := r.tcktog2 xor r.tcktog(0);
v.tdishft := '0';
vdmai.address := r.addr(31 downto 0); vdmai.wdata := ahbdrivedata(r.data(31 downto 0));
vdmai.start := '0'; vdmai.burst := '0'; vdmai.write := write;
vdmai.busy := '0'; vdmai.irq := '0'; vdmai.size := '0' & r.addr(33 downto 32);
case r.state is
when shft =>
if (r.asel(0) or r.dsel(0)) = '1' then
if r.shift2 = '1' then
if redge0 = '1' then
if r.asel(0) = '1' then v.addr(33 downto 0) := r.addr(34 downto 1); end if;
if r.dsel(0) = '1' then v.data(31 downto 0) := r.data(32 downto 1); end if;
v.tdishft := '1'; -- Shift in TDI next AHB cycle
end if;
elsif r.upd2 = '1' then
if reread /= 0 then
v.data(32) := '0'; -- Transfer not done
end if;
if (r.asel(0) and not write) = '1' then v.state := ahb; end if;
if (r.dsel(0) and (write or (not write and seq))) = '1' then -- data register
v.state := ahb;
if (seq and not write) = '1' then
v.addr(ADDBITS-1 downto 2) := r.addr(ADDBITS-1 downto 2) + 1;
end if;
end if;
end if;
end if;
if r.tdishft='1' then
if r.asel(0)='1' then v.addr(34):=r.tdi(0); end if;
if r.dsel(0)='1' then v.data(32):=r.tdi(0); v.seq:=r.tdi(0); end if;
end if;
if reread /= 0 then v.holdn := '1'; end if;
vdmai.size := "000";
when ahb =>
if reread /= 0 and r.shift2 = '1' then v.holdn := '0'; end if;
if dmao.active = '1' then
if dmao.ready = '1' then
v.data(31 downto 0) := ahbreadword(dmao.rdata);
v.state := nxt_shft;
if reread /= 0 then
v.data(32) := '1'; -- Transfer done
end if;
if (write and seq) = '1' then
v.addr(ADDBITS-1 downto 2) := r.addr(ADDBITS-1 downto 2) + 1;
end if;
end if;
else
vdmai.start := '1';
end if;
when nxt_shft =>
if reread /= 0 then
v.holdn := (r.holdn or r.upd2) and not r.shift2;
if r.upd2 = '0' and r.shift2 = '0' and r.holdn = '1' then v.state := shft; end if;
else
if r.upd2 = '0' then v.state := shft; end if;
end if;
end case;
if (rst = '0') or (r.trst(0) = '1') then
v.state := shft; v.addr := (others => '0'); v.seq := '0';
end if;
if reread = 0 then v.holdn := '0'; end if;
rin <= v; dmai <= vdmai; tapi <= vtapi;
end process;
reg : process (clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
tckreg: process (tck,trst)
begin
if rising_edge(tck) then
tr.tcktog <= not tr.tcktog;
tr.tdi <= tapo.tdi;
tr.tdor <= nexttdo;
end if;
if trst='0' then
tr.tcktog <= '0';
tr.tdi <= '0';
tr.tdor <= '0';
end if;
end process;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-ml510/leon3mp.vhd | 1 | 51575 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2008 Jiri Gaisler, Jan Andersson, Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.pci.all;
use gaisler.ddrpkg.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
-- pragma translate_on
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
fpga_cpu_reset_b : in std_ulogic;
user_clksys : in std_ulogic; -- 100 MHz main clock
sysace_fpga_clk : in std_ulogic; -- 33 MHz
-- Flash
flash_we_b : out std_ulogic;
flash_wait : in std_ulogic;
flash_reset_b : out std_ulogic;
flash_oe_b : out std_ulogic;
flash_d : inout std_logic_vector(15 downto 0);
flash_clk : out std_ulogic;
flash_ce_b : out std_ulogic;
flash_adv_b : out std_logic;
flash_a : out std_logic_vector(21 downto 0);
--pragma translate_off
-- For debug output module
sram_bw : out std_ulogic;
sim_d : inout std_logic_vector(31 downto 16);
iosn : out std_ulogic;
--pragma translate_on
-- DDR2 slot 1
dimm1_ddr2_we_b : out std_ulogic;
dimm1_ddr2_s_b : out std_logic_vector(1 downto 0);
dimm1_ddr2_ras_b : out std_ulogic;
dimm1_ddr2_pll_clkin_p : out std_ulogic;
dimm1_ddr2_pll_clkin_n : out std_ulogic;
dimm1_ddr2_odt : out std_logic_vector(1 downto 0);
dimm1_ddr2_dqs_p : inout std_logic_vector(8 downto 0);
dimm1_ddr2_dqs_n : inout std_logic_vector(8 downto 0);
dimm1_ddr2_dqm : out std_logic_vector(8 downto 0);
dimm1_ddr2_dq : inout std_logic_vector(71 downto 0);
dimm1_ddr2_cke : out std_logic_vector(1 downto 0);
-- dimm1_ddr2_cb : inout std_logic_vector(7 downto 0);
dimm1_ddr2_cas_b : out std_ulogic;
dimm1_ddr2_ba : out std_logic_vector(2 downto 0);
dimm1_ddr2_a : out std_logic_vector(13 downto 0);
-- DDR2 slot 0
dimm0_ddr2_we_b : out std_ulogic;
dimm0_ddr2_s_b : out std_logic_vector(1 downto 0);
dimm0_ddr2_ras_b : out std_ulogic;
dimm0_ddr2_pll_clkin_p : out std_ulogic;
dimm0_ddr2_pll_clkin_n : out std_ulogic;
dimm0_ddr2_odt : out std_logic_vector(1 downto 0);
dimm0_ddr2_dqs_p : inout std_logic_vector(8 downto 0);
dimm0_ddr2_dqs_n : inout std_logic_vector(8 downto 0);
dimm0_ddr2_dqm : out std_logic_vector(8 downto 0);
dimm0_ddr2_dq : inout std_logic_vector(71 downto 0);
dimm0_ddr2_cke : out std_logic_vector(1 downto 0);
-- dimm0_ddr2_cb : inout std_logic_vector(7 downto 0);
dimm0_ddr2_cas_b : out std_ulogic;
dimm0_ddr2_ba : out std_logic_vector(2 downto 0);
dimm0_ddr2_a : out std_logic_vector(13 downto 0);
dimm0_ddr2_reset_n : out std_ulogic;
-- Ethernet PHY
phy0_txer : out std_ulogic;
phy0_txd : out std_logic_vector(3 downto 0);
phy0_txctl_txen : out std_ulogic;
phy0_txclk : in std_ulogic;
phy0_rxer : in std_ulogic;
phy0_rxd : in std_logic_vector(3 downto 0);
phy0_rxctl_rxdv : in std_ulogic;
phy0_rxclk : in std_ulogic;
phy0_reset : out std_ulogic;
phy0_mdio : inout std_logic;
phy0_mdc : out std_ulogic;
-- phy0_int : in std_ulogic;
-- System ACE MPU
sysace_mpa : out std_logic_vector(6 downto 0);
sysace_mpce : out std_ulogic;
sysace_mpirq : in std_ulogic;
sysace_mpoe : out std_ulogic;
sysace_mpwe : out std_ulogic;
sysace_mpd : inout std_logic_vector(15 downto 0);
-- GPIO/Green LEDs
dbg_led : inout std_logic_vector(3 downto 0);
-- Red/Green LEDs
opb_bus_error : out std_ulogic;
plb_bus_error : out std_ulogic;
-- LCD
-- fpga_lcd_rw : out std_ulogic;
-- fpga_lcd_rs : out std_ulogic;
-- fpga_lcd_e : out std_ulogic;
-- fpga_lcd_db : out std_logic_vector(7 downto 0);
-- DVI
dvi_xclk_p : out std_ulogic;
dvi_xclk_n : out std_ulogic;
dvi_v : out std_ulogic;
dvi_reset_b : out std_ulogic;
dvi_h : out std_ulogic;
dvi_gpio1 : inout std_logic;
dvi_de : out std_ulogic;
dvi_d : out std_logic_vector(11 downto 0);
-- PCI
pci_p_trdy_b : inout std_logic;
pci_p_stop_b : inout std_logic;
pci_p_serr_b : inout std_logic;
pci_p_rst_b : inout std_logic;
pci_p_req_b : in std_logic_vector(0 to 4);
pci_p_perr_b : inout std_logic;
pci_p_par : inout std_logic;
pci_p_lock_b : inout std_logic;
pci_p_irdy_b : inout std_logic;
pci_p_intd_b : in std_logic;
pci_p_intc_b : in std_logic;
pci_p_intb_b : in std_logic;
pci_p_inta_b : in std_logic;
pci_p_gnt_b : out std_logic_vector(0 to 4);
pci_p_frame_b : inout std_logic;
pci_p_devsel_b : inout std_logic;
pci_p_clk5_r : out std_ulogic;
pci_p_clk5 : in std_ulogic;
pci_p_clk4_r : out std_ulogic;
pci_p_clk3_r : out std_ulogic;
pci_p_clk1_r : out std_ulogic;
pci_p_clk0_r : out std_ulogic;
pci_p_cbe_b : inout std_logic_vector(3 downto 0);
pci_p_ad : inout std_logic_vector(31 downto 0);
-- pci_fpga_idsel : in std_ulogic;
sbr_pwg_rsm_rstj : inout std_logic;
sbr_nmi_r : in std_ulogic;
sbr_intr_r : in std_ulogic;
sbr_ide_rst_b : inout std_logic;
-- IIC/SMBus and sideband signals
iic_sda_dvi : inout std_logic;
iic_scl_dvi : inout std_logic;
fpga_sda : inout std_logic;
fpga_scl : inout std_logic;
iic_therm_b : in std_ulogic;
iic_reset_b : out std_ulogic;
iic_irq_b : in std_ulogic;
iic_alert_b : in std_ulogic;
-- SPI
spi_data_out : in std_logic;
spi_data_in : out std_ulogic;
spi_data_cs_b : out std_ulogic;
spi_clk : out std_ulogic;
-- UARTs
uart1_txd : out std_ulogic;
uart1_rxd : in std_ulogic;
uart1_rts_b : out std_ulogic;
uart1_cts_b : in std_ulogic;
uart0_txd : out std_ulogic;
uart0_rxd : in std_ulogic;
uart0_rts_b : out std_ulogic
-- uart0_cts_b : in std_ulogic
-- System monitor
-- test_mon_vrefp : in std_ulogic;
-- test_mon_vp0_p : in std_ulogic;
-- test_mon_vn0_n : in std_ulogic
-- test_mon_avdd : in std_ulogic
);
end;
architecture rtl of leon3mp is
component svga2ch7301c
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
vgao : in apbvga_out_type;
vgaclk_fb : in std_ulogic;
clk25_fb : in std_ulogic;
clk40_fb : in std_ulogic;
clk65_fb : in std_ulogic;
vgaclk : out std_ulogic;
clk25 : out std_ulogic;
clk40 : out std_ulogic;
clk65 : out std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
locked : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+
CFG_SVGA_ENABLE+CFG_PCI;
-- Set this constant to 1 to include an APB bridge with the Logan logic
-- analyzer attached to the PCI signals
constant CFG_LOGAN : integer := 0;
signal ddr0_clk_fb, ddr1_clk_fb : std_logic;
signal vcc, gnd : std_logic_vector(31 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal apbi, apbi1 : apb_slv_in_type;
signal apbo, apbo1 : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, clkm2x, rstn, rstraw, flashclkl : std_ulogic;
signal clkddr, clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2, cgi3 : clkgen_in_type;
signal cgo, cgo2, cgo3 : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal opb_bus_errorl, plb_bus_errorl : std_ulogic;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, lock0, lock1, lclk, clkml0, clkml1 : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal rst : std_ulogic;
signal egtx_clk_fb : std_ulogic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_ulogic;
signal vgao : apbvga_out_type;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal clk_sel : std_logic_vector(1 downto 0);
signal vgalock : std_ulogic;
signal clkvga, clkvga_p, clkvga_n : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
constant BOARD_FREQ_200 : integer := 200000; -- input frequency in KHz
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1;
-- DDR clock is 200 MHz clock unless CFG_DDR2SP_NOSYNC is set. If that config
-- option is set the DDR clock is 2x CPU clock.
constant DDR_FREQ : integer :=
BOARD_FREQ_200 - (BOARD_FREQ_200 - 2*CPU_FREQ)*CFG_DDR2SP_NOSYNC;
constant IOAEN : integer := CFG_DDR2SP;
signal stati : ahbstat_in_type;
signal ddr0_clkv : std_logic_vector(2 downto 0);
signal ddr0_clkbv : std_logic_vector(2 downto 0);
signal ddr1_clkv : std_logic_vector(2 downto 0);
signal ddr1_clkbv : std_logic_vector(2 downto 0);
signal clkace : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
signal sysmoni : grsysmon_in_type;
signal sysmono : grsysmon_out_type;
signal pciclk, pci_clk, pci_clk_fb : std_ulogic;
signal pci_arb_gnt : std_logic_vector(0 to 7);
signal pci_arb_req : std_logic_vector(0 to 7);
signal pci_arb_reql : std_logic_vector(0 to 4);
signal pci_reql : std_ulogic;
signal pci_host, pci_66 : std_ulogic;
signal pci_intv : std_logic_vector(3 downto 0);
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal clkma, clkmb, clkmc : std_ulogic;
signal clk0_tb, rst0_tb, rst0_tbn : std_ulogic;
signal phy_init_done : std_ulogic;
-- Logan signals
signal signals : std_logic_vector(63*CFG_LOGAN downto 0);
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clkml0 : signal is true;
attribute syn_preserve of clkml0 : signal is true;
attribute syn_keep of clkml1 : signal is true;
attribute syn_preserve of clkml1 : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute syn_keep of egtx_clk : signal is true;
attribute syn_preserve of egtx_clk : signal is true;
attribute syn_keep of clkvga : signal is true;
attribute syn_preserve of clkvga : signal is true;
attribute syn_keep of clk25 : signal is true;
attribute syn_preserve of clk25 : signal is true;
attribute syn_keep of clk40 : signal is true;
attribute syn_preserve of clk40 : signal is true;
attribute syn_keep of clk65 : signal is true;
attribute syn_preserve of clk65 : signal is true;
attribute syn_keep of phy_init_done : signal is true;
attribute syn_preserve of phy_init_done : signal is true;
attribute keep : boolean;
attribute keep of lock0 : signal is true;
attribute keep of lock1 : signal is true;
attribute keep of clkml0 : signal is true;
attribute keep of clkml1 : signal is true;
attribute keep of clkm : signal is true;
attribute keep of egtx_clk : signal is true;
attribute keep of clkvga : signal is true;
attribute keep of clk25 : signal is true;
attribute keep of clk40 : signal is true;
attribute keep of clk65 : signal is true;
attribute syn_noprune : boolean;
attribute syn_noprune of sysace_fpga_clk_pad : label is true;
begin
vcc <= (others => '1'); gnd <= (others => '0');
rst0_tbn <= not rst0_tb;
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
flashclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (flash_clk, flashclkl);
sysace_fpga_clk_pad : clkpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (sysace_fpga_clk, clkace);
pci_p_clk5_pad : clkpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (pci_p_clk5, pci_clk_fb);
pci_p_clk5_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk5_r, pci_clk);
pci_p_clk4_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk4_r, pci_clk);
pci_p_clk3_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk3_r, pci_clk);
pci_p_clk1_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk1_r, pci_clk);
pci_p_clk0_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk0_r, pci_clk);
clkgen0 : clkgen -- system clock generator
generic map (CFG_FABTECH, CFG_CLKMUL, CFG_CLKDIV, 1, 1,
1, CFG_PCIDLL, CFG_PCISYSCLK, BOARD_FREQ, 1)
port map (lclk, pci_clk_fb, clkmc, open, clkm2x, flashclkl, pciclk, cgi, cgo,
open, open, clk_200);
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= '0';
-- clkgen1 : clkgen -- Ethernet 1G PHY clock generator
-- generic map (CFG_FABTECH, 5, 4, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
-- port map (lclk, gnd(0), egtx_clk, open, open, open, open, cgi2, cgo2);
-- cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw; --cgi2.pllref <= egtx_clk_fb;
-- egtx_clk_pad : outpad generic map (tech => padtech)
-- port map (phy_gtx_clk, egtx_clk);
clkgen2 : clkgen -- PCI clock generator
generic map (CFG_FABTECH, 2, 6, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), pci_clk, open, open, open, open, cgi3, cgo3);
cgi3.pllctrl <= "00"; cgi3.pllrst <= rstraw; cgi3.pllref <= '0';
iic_reset_b_pad : outpad generic map (tech => padtech)
port map (iic_reset_b, rstn);
resetn_pad : inpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (fpga_cpu_reset_b, rst);
rst0 : rstgen -- reset generator
port map (rst, clkm, clklock, rstn, rstraw);
clklock <= lock0 and lock1 and cgo.clklock and cgo3.clklock;
clk_pad : clkpad generic map (tech => padtech, arch => 2, level => cmos, voltage => x25v)
port map (user_clksys, lclk);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, devid => XILINX_ML510,
ioen => IOAEN, nahbm => maxahbm, nahbs => 11 + CFG_LOGAN)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE,
CFG_TLB_REP, CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
opb_bus_errorl <= not dbgo(0).error;
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#D00#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsui.break <= not gpioo.val(0); -- Position on on GPIO DIP switch
plb_bus_errorl <= dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; plb_bus_errorl <= '0';
end generate;
opb_bus_error_pad : outpad generic map (tech => padtech)
port map (opb_bus_error, opb_bus_errorl);
plb_bus_error_pad : outpad generic map (tech => padtech)
port map (plb_bus_error, plb_bus_errorl);
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
end generate;
nodcom : if CFG_AHB_UART = 0 generate
duo.txd <= '0'; duo.rtsn <= '1';
end generate;
dsurx_pad : inpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (uart0_rxd, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (uart0_txd, duo.txd);
-- dsucts_pad : inpad generic map (tech => padtech, level => cmos, voltage => x33v)
-- port map (uart0_cts_b, dui.ctsn);
dsurts_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (uart0_rts_b, duo.rtsn);
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
memi.brdyn <= '1'; memi.bexcn <= '1';
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate
mctrl0 : mctrl generic map (hindex => 3, pindex => 0,
ramaddr => 0, rammask => 0, paddr => 0, srbanks => 0,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT,
sden => CFG_MCTRL_SDEN, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(3), apbi, apbo(0), wpo);
end generate;
nomctrl: if CFG_MCTRL_LEON2 = 0 generate
memo.address <= (others => '0'); memo.romsn <= (others => '1');
memo.oen <= '1'; memo.wrn <= (others => '1');
memo.vbdrive <= (others => '1'); memo.writen <= '1';
end generate;
flash_reset_b_pad : outpad generic map (tech => padtech)
port map (flash_reset_b, rstn);
-- flash_wait_pad : inpad generic map (tech => padtech)
-- port map (flash_wait, );
flash_adv_b_pad : outpad generic map (tech => padtech)
port map (flash_adv_b, gnd(0));
flash_a_pads : outpadv generic map (width => 22, tech => padtech)
port map (flash_a, memo.address(22 downto 1));
flash_ce_b_pad : outpad generic map (tech => padtech)
port map (flash_ce_b, memo.romsn(0));
flash_oe_b_pad : outpad generic map (tech => padtech)
port map (flash_oe_b, memo.oen);
--pragma translate_off
rwen_pad : outpad generic map (tech => padtech)
port map (sram_bw, memo.wrn(3));
sim_d_pads : iopadvv generic map (tech => padtech, width => 16)
port map (sim_d, memo.data(15 downto 0),
memo.vbdrive(15 downto 0), memi.data(15 downto 0));
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
--pragma translate_on
flash_we_b_pad : outpad generic map (tech => padtech)
port map (flash_we_b, memo.writen);
flash_d_pads : iopadvv generic map (tech => padtech, width => 16)
port map (flash_d, memo.data(31 downto 16),
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
dbg_led0_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (dbg_led(3), phy_init_done);
clkm <= clkma; clkma <= clkmb; clkmb <= clkmc;
ddrsp0 : if (CFG_DDR2SP /= 0) generate
phy_init_done <= '1';
-- DDR clock selection
-- If the synchronization registers are removed in the DDR controller, we
-- assume that the user wants to run at 2x the system clock. Otherwise the
-- DDR clock is generated from the 200 MHz clock.
ddrclkselarb: if CFG_DDR2SP_NOSYNC = 0 generate
BUFGDDR : BUFG port map (I => clk_200, O => clkddr);
end generate;
ddrclksel2x: if CFG_DDR2SP_NOSYNC /= 0 generate
clkddr <= clkm2x;
end generate;
dimm0_ddr2_reset_n_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (dimm0_ddr2_reset_n, rst);
-- Slot 0
ddrc0 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 0, haddr => 16#400#, hmask => 16#e00#, ioaddr => 1,
pwron => CFG_DDR2SP_INIT, MHz => DDR_FREQ/1000, TRFC => CFG_DDR2SP_TRFC,
clkmul => CFG_DDR2SP_FREQ/10 - (CFG_DDR2SP_FREQ/10-1)*CFG_DDR2SP_NOSYNC,
clkdiv => 20 - (19)*CFG_DDR2SP_NOSYNC, ahbfreq => CPU_FREQ/1000,
col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE, ddrbits => CFG_DDR2SP_DATAWIDTH,
ddelayb0 => CFG_DDR2SP_DELAY0, ddelayb1 => CFG_DDR2SP_DELAY1,
ddelayb2 => CFG_DDR2SP_DELAY2, ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4, ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6, ddelayb7 => CFG_DDR2SP_DELAY7,
readdly => 1, rskew => 0, oepol => 0,
dqsgating => 0, rstdel => 200, eightbanks => 1,
numidelctrl => 2 + CFG_DDR2SP_DATAWIDTH/64, norefclk => 0, odten => 3,
nosync => CFG_DDR2SP_NOSYNC)
port map (rst, rstn, clkddr, clkm, clk_200, lock0, clkml0, clkml0, ahbsi, ahbso(0),
ddr0_clkv, ddr0_clkbv, ddr0_clk_fb, ddr0_clk_fb,
dimm0_ddr2_cke, dimm0_ddr2_s_b, dimm0_ddr2_we_b, dimm0_ddr2_ras_b,
dimm0_ddr2_cas_b, dimm0_ddr2_dqm(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)),
dimm0_ddr2_dqs_p(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)),
dimm0_ddr2_dqs_n(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)), dimm0_ddr2_a,
dimm0_ddr2_ba(2 downto 0), dimm0_ddr2_dq(63 downto 32*(32/CFG_DDR2SP_DATAWIDTH)),
dimm0_ddr2_odt);
dimm0_ddr2_pll_clkin_p <= ddr0_clkv(0);
dimm0_ddr2_pll_clkin_n <= ddr0_clkbv(0);
-- Ground unused bank address and memory mask
-- dimm0_ddr2_ba_notused_pad : outpad generic map (tech => padtech, level => SSTL18_I)
-- port map (dimm0_ddr2_ba(2), gnd(0));
dimm0_ddr2_dqm_notused8_pad : outpad generic map (tech => padtech, level => SSTL18_I)
port map (dimm0_ddr2_dqm(8), gnd(0));
-- Tri-state unused data strobe
dimm0_dqsp_notused8_pad : iopad generic map (tech => padtech, level => SSTL18_II)
port map (dimm0_ddr2_dqs_p(8), gnd(0), vcc(0), open);
dimm0_dqsn_notused8_pad : iopad generic map (tech => padtech, level => SSTL18_II)
port map (dimm0_ddr2_dqs_n(8), gnd(0), vcc(0), open);
-- Tristate unused check bits
dimm0_cb_notused_pad : iopadv generic map (tech => padtech, width => 8, level => SSTL18_II)
port map (dimm0_ddr2_dq(71 downto 64), gnd(7 downto 0), vcc(0), open);
-- Handle signals not used with 32-bit interface
ddr032bit: if CFG_DDR2SP_DATAWIDTH /= 64 generate
dimm0_ddr2_dqm_notused30_pads : outpadv generic map (tech => padtech, width => 4, level => SSTL18_I)
port map (dimm0_ddr2_dqm(3 downto 0), gnd(3 downto 0));
dimm0_dqsp_notused30_pads : iopadv generic map (tech => padtech, width => 4, level => SSTL18_II)
port map (dimm0_ddr2_dqs_p(3 downto 0), gnd(3 downto 0), vcc(0), open);
dimm0_dqsn_notused30_pads : iopadv generic map (tech => padtech, width => 4, level => SSTL18_II)
port map (dimm0_ddr2_dqs_n(3 downto 0), gnd(3 downto 0), vcc(0), open);
dimm0_dq_notused_pads : iopadv generic map (tech => padtech, width => 32, level => SSTL18_II)
port map (dimm0_ddr2_dq(31 downto 0), gnd, vcc(0), open);
end generate;
-- Slot 1
ddrc1 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 1, haddr => 16#600#, hmask => 16#E00#, ioaddr => 2,
pwron => CFG_DDR2SP_INIT, MHz => DDR_FREQ/1000, TRFC => CFG_DDR2SP_TRFC,
clkmul => CFG_DDR2SP_FREQ/10 - (CFG_DDR2SP_FREQ/10-1)*CFG_DDR2SP_NOSYNC,
clkdiv => 20 - (19)*CFG_DDR2SP_NOSYNC, ahbfreq => CPU_FREQ/1000,
col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE, ddrbits => CFG_DDR2SP_DATAWIDTH,
ddelayb0 => CFG_DDR2SP_DELAY0, ddelayb1 => CFG_DDR2SP_DELAY1,
ddelayb2 => CFG_DDR2SP_DELAY2, ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4, ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6, ddelayb7 => CFG_DDR2SP_DELAY7,
readdly => 1, rskew => 0, oepol => 0,
dqsgating => 0, rstdel => 200, eightbanks => 1,
numidelctrl => 2 + CFG_DDR2SP_DATAWIDTH/64, norefclk => 0, odten => 3,
nosync => CFG_DDR2SP_NOSYNC)
port map (rst, rstn, clkddr, clkm, clk_200, lock1, clkml1, clkml1, ahbsi, ahbso(1),
ddr1_clkv, ddr1_clkbv, ddr1_clk_fb, ddr1_clk_fb,
dimm1_ddr2_cke, dimm1_ddr2_s_b, dimm1_ddr2_we_b, dimm1_ddr2_ras_b,
dimm1_ddr2_cas_b, dimm1_ddr2_dqm(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)),
dimm1_ddr2_dqs_p(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)),
dimm1_ddr2_dqs_n(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)), dimm1_ddr2_a,
dimm1_ddr2_ba(2 downto 0), dimm1_ddr2_dq(63 downto 32*(32/ CFG_DDR2SP_DATAWIDTH)),
dimm1_ddr2_odt);
dimm1_ddr2_pll_clkin_p <= ddr1_clkv(0);
dimm1_ddr2_pll_clkin_n <= ddr1_clkbv(0);
-- Ground unused bank address and memory mask
-- dimm1_ddr2_ba_notused_pad : outpad generic map (tech => padtech, level => SSTL18_I)
-- port map (dimm1_ddr2_ba(2), gnd(0));
dimm1_ddr2_dqm_notused8_pad : outpad generic map (tech => padtech, level => SSTL18_I)
port map (dimm1_ddr2_dqm(8), gnd(0));
-- Tri-state unused data strobe
dimm1_dqsp_notused8_pad : iopad generic map (tech => padtech, level => SSTL18_II)
port map (dimm1_ddr2_dqs_p(8), gnd(0), vcc(0), open);
dimm1_dqsn_notused8_pad : iopad generic map (tech => padtech, level => SSTL18_II)
port map (dimm1_ddr2_dqs_n(8), gnd(0), vcc(0), open);
-- Tristate unused check bits
dimm1_cb_notused_pad : iopadv generic map (tech => padtech, width => 8, level => SSTL18_II)
port map (dimm1_ddr2_dq(71 downto 64), gnd(7 downto 0), vcc(0), open);
-- Handle signals not used with 32-bit interface
ddr132bit: if CFG_DDR2SP_DATAWIDTH /= 64 generate
dimm1_ddr2_dqm_notused30_pads : outpadv generic map (tech => padtech, width => 4, level => SSTL18_I)
port map (dimm1_ddr2_dqm(3 downto 0), gnd(3 downto 0));
dimm1_dqsp_notused30_pads : iopadv generic map (tech => padtech, width => 4, level => SSTL18_II)
port map (dimm1_ddr2_dqs_p(3 downto 0), gnd(3 downto 0), vcc(0), open);
dimm1_dqsn_notused30_pads : iopadv generic map (tech => padtech, width => 4, level => SSTL18_II)
port map (dimm1_ddr2_dqs_n(3 downto 0), gnd(3 downto 0), vcc(0), open);
dimm1_dq_notused_pads : iopadv generic map (tech => padtech, width => 32, level => SSTL18_II)
port map (dimm1_ddr2_dq(31 downto 0), gnd, vcc(0), open);
end generate;
end generate;
-- noddr : if (CFG_DDR2SP = 0) generate lock0 <= '1'; lock1 <= '1'; end generate;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 5, hirq => 5,
haddr => 16#000#, hmask => 16#fff#, split => CFG_SPLIT)
port map (rstn, clkm, clkace, ahbsi, ahbso(5), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL = 0 generate
aceo <= gracectrl_none;
end generate nograce;
sysace_mpa_pads : outpadv generic map (width => 7, tech => padtech)
port map (sysace_mpa, aceo.addr);
sysace_mpce_pad : outpad generic map (tech => padtech)
port map (sysace_mpce, aceo.cen);
sysace_mpd_pads : iopadv generic map (tech => padtech, width => 16)
port map (sysace_mpd, aceo.do, aceo.doen, acei.di);
sysace_mpoe_pad : outpad generic map (tech => padtech)
port map (sysace_mpoe, aceo.oen);
sysace_mpwe_pad : outpad generic map (tech => padtech)
port map (sysace_mpwe, aceo.wen);
sysace_mpirq_pad : inpad generic map (tech => padtech)
port map (sysace_mpirq, acei.irq);
----------------------------------------------------------------------
--- AHB ROM ---------------------------------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 10, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map (rstn, clkm, ahbsi, ahbso(10));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 4, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(4), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
end generate;
noua1: if CFG_UART1_ENABLE = 0 generate u1o.txd <= '0'; u1o.rtsn <= '1'; end generate;
ua1rx_pad : inpad generic map (tech => padtech) port map (uart1_rxd, u1i.rxd);
ua1tx_pad : outpad generic map (tech => padtech) port map (uart1_txd, u1o.txd);
ua1cts_pad : inpad generic map (tech => padtech) port map (uart1_cts_b, u1i.ctsn);
ua1rts_pad : outpad generic map (tech => padtech) port map (uart1_rts_b, u1o.rtsn);
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 14, paddr => 14,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 40000, clk1 => 40000, clk2 => 25000, clk3 => 15385, burstlen => 6)
port map(rstn, clkm, clkvga, apbi, apbo(14), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
dvi0 : svga2ch7301c generic map (tech => fabtech, idf => 2)
port map (lclk, rstraw, clk_sel, vgao, clkvga, clk25, clk40, clk65,
clkvga, clk25, clk40, clk65, clkvga_p, clkvga_n,
vgalock, lcd_datal, lcd_hsyncl, lcd_vsyncl, lcd_del);
i2cdvi : i2cmst
generic map (pindex => 6, paddr => 6, pmask => 16#FFF#,
pirq => 6, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(6), dvi_i2ci, dvi_i2co);
end generate;
novga : if CFG_SVGA_ENABLE = 0 generate
apbo(14) <= apb_none; apbo(6) <= apb_none;
lcd_datal <= (others => '0'); clkvga_p <= '0'; clkvga_n <= '0';
lcd_hsyncl <= '0'; lcd_vsyncl <= '0'; lcd_del <= '0';
dvi_i2co.scloen <= '1'; dvi_i2co.sdaoen <= '1';
end generate;
dvi_d_pad : outpadv generic map (width => 12, tech => padtech)
port map (dvi_d, lcd_datal);
dvi_xclk_p_pad : outpad generic map (tech => padtech)
port map (dvi_xclk_p, clkvga_p);
dvi_xclk_n_pad : outpad generic map (tech => padtech)
port map (dvi_xclk_n, clkvga_n);
dvi_h_pad : outpad generic map (tech => padtech)
port map (dvi_h, lcd_hsyncl);
dvi_v_pad : outpad generic map (tech => padtech)
port map (dvi_v, lcd_vsyncl);
dvi_de_pad : outpad generic map (tech => padtech)
port map (dvi_de, lcd_del);
dvi_reset_b_pad : outpad generic map (tech => padtech)
port map (dvi_reset_b, rstn);
iic_scl_dvi_pad : iopad generic map (tech => padtech)
port map (iic_scl_dvi, dvi_i2co.scl, dvi_i2co.scloen, dvi_i2ci.scl);
iic_sda_dvi_pad : iopad generic map (tech => padtech)
port map (iic_sda_dvi, dvi_i2co.sda, dvi_i2co.sdaoen, dvi_i2ci.sda);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
end generate;
nogpio0: if CFG_GRGPIO_ENABLE = 0 generate
gpioo.oen <= (others => '1'); gpioo.val <= (others => '0');
gpioo.dout <= (others => '1');
end generate;
dbg_led_pads : iopadvv generic map (tech => padtech, width => 3, level => cmos, voltage => x33v)
port map (dbg_led(2 downto 0), gpioo.dout(2 downto 0), gpioo.oen(2 downto 0),
gpioi.din(2 downto 0));
dvi_gpio_pad : iopad generic map (tech => padtech)
port map (dvi_gpio1, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
iic_therm_b_pad : inpad generic map (tech => padtech)
port map (iic_therm_b, gpioi.din(9));
iic_irq_b_pad : inpad generic map (tech => padtech)
port map (iic_irq_b, gpioi.din(10));
iic_alert_b_pad : inpad generic map (tech => padtech)
port map (iic_alert_b, gpioi.din(11));
sbr_pwg_rsm_rstj_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (sbr_pwg_rsm_rstj, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
sbr_nmi_r_pad : inpad generic map (tech => padtech)
port map (sbr_nmi_r, gpioi.din(6));
sbr_intr_r_pad : inpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (sbr_intr_r, gpioi.din(5));
sbr_ide_rst_b_pad : iopad generic map (tech => padtech)
port map (sbr_ide_rst_b, gpioo.dout(8), gpioo.oen(8), gpioi.din(8));
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 9, paddr => 9, pmask => 16#FFF#,
pirq => 3, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(9), i2ci, i2co);
end generate;
noi2cm: if CFG_I2C_ENABLE = 0 generate
i2co.scloen <= '1'; i2co.sdaoen <= '1';
i2co.scl <= '0'; i2co.sda <= '0';
end generate;
i2c_scl_pad : iopad generic map (tech => padtech)
port map (fpga_scl, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech)
port map (fpga_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 10, paddr => 10, pmask => 16#fff#, pirq => 12,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => 0, netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(10), spii, spio, slvsel);
spii.spisel <= '1'; -- Master only
miso_pad : inpad generic map (tech => padtech)
port map (spi_data_out, spii.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_data_in, spio.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, spio.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (spi_data_cs_b, slvsel(0));
end generate spic;
nospi: if CFG_SPICTRL_ENABLE = 0 generate
miso_pad : inpad generic map (tech => padtech)
port map (spi_data_out, spii.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_data_in, vcc(0));
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, gnd(0));
slvsel_pad : outpad generic map (tech => padtech)
port map (spi_data_cs_b, vcc(0));
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 4, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(11), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (phy0_mdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2, level => cmos, voltage => x25v)
port map (phy0_txclk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2, level => cmos, voltage => x25v)
port map (phy0_rxclk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (phy0_rxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy0_rxctl_rxdv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy0_rxer, ethi.rx_er);
-- Collision detect and carrier sense are not connected on the
-- board.
ethi.rx_col <= '0';
ethi.rx_crs <= ethi.rx_dv;
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (phy0_txd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (phy0_txctl_txen, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy0_txer, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy0_mdc, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy0_reset, rstn);
-- ethi.gtx_clk <= egtx_clk;
end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
----------------------------------------------------------------------
pp : if CFG_PCI /= 0 generate
pci_mtf0 : if CFG_PCI = 2 generate -- master/target with fifo
pci0 : pci_mtf generic map (memtech => memtech,
hmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH,
fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
hslvndx => 7, pindex => 4, paddr => 4, haddr => 16#800#, hmask => 16#c00#,
ioaddr => 16#400#, irq => 5, irqmask => 16#F#, nsync => 2, hostrst => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(4),
ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH), ahbsi, ahbso(7));
end generate;
pci_mtf1 : if CFG_PCI = 3 generate -- master/target with fifo and DMA
dma : pcidma generic map (memtech => memtech,
dmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH+1,
dapbndx => 5, dapbaddr => 5, blength => blength,
mstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH,
fifodepth => log2(fifodepth), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
slvndx => 7, apbndx => 4, apbaddr => 4, haddr => 16#800#, hmask => 16#c00#,
ioaddr => 16#400#, irq => 5, irqmask => 16#F#, nsync => 2, hostrst => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbo(5),
ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH+1),
apbi, apbo(4), ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH),
ahbsi, ahbso(7));
end generate;
pci_trc0 : if CFG_PCITBUFEN /= 0 generate -- PCI trace buffer
pt0 : pcitrace generic map (depth => (6 + log2(CFG_PCITBUF/256)),
memtech => memtech, pindex => 12, paddr => 16#100#, pmask => 16#f00#)
port map (rstn, clkm, pciclk, pcii, apbi, apbo(12));
end generate;
pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
pciarb0 : pciarb generic map (pindex => 13, paddr => 13, nb_agents => CFG_PCI_ARB_NGNT,
apb_en => CFG_PCI_ARBAPB)
port map (clk => pciclk, rst_n => pcii.rst, req_n => pci_arb_req, frame_n => pcii.frame,
gnt_n => pci_arb_gnt, pclk => clkm, prst_n => rstn, apbi => apbi, apbo => apbo(13));
-- Internal connection of req(2)
pci_arb_req(0 to 4) <= pci_arb_reql(0 to 1) & pci_reql & pci_arb_reql(3 to 4);
pci_arb_req(5 to 7) <= (others => '1');
end generate;
end generate;
nopcia0: if CFG_PCI = 0 or CFG_PCI_ARB = 0 generate
pci_arb_gnt <= (others => '1');
end generate;
nopci_mtf: if CFG_PCI /= 2 and CFG_PCI /= 3 generate
pcio <= pci_out_none;
end generate;
pgnt_pad : outpadv generic map (tech => padtech, width => 5, level => pci33)
port map (pci_p_gnt_b, pci_arb_gnt(0 to 4));
preq_pad : inpadv generic map (tech => padtech, width => 5, level => pci33)
port map (pci_p_req_b, pci_arb_reql);
pcipads0 : pcipads -- PCI pads
generic map (padtech => padtech, host => 2, int => 14, no66 => 1, onchipreqgnt => 1,
drivereset => 1, constidsel => 1)
port map (pci_rst => pci_p_rst_b, pci_gnt => pci_arb_gnt(2), pci_idsel => '0', --pci_fpga_idsel,
pci_lock => pci_p_lock_b, pci_ad => pci_p_ad, pci_cbe => pci_p_cbe_b,
pci_frame => pci_p_frame_b, pci_irdy => pci_p_irdy_b, pci_trdy => pci_p_trdy_b,
pci_devsel => pci_p_devsel_b, pci_stop => pci_p_stop_b, pci_perr => pci_p_perr_b,
pci_par => pci_p_par, pci_req => pci_reql, pci_serr => pci_p_serr_b,
pci_host => pci_host, pci_66 => pci_66, pcii => pcii, pcio => pcio, pci_int => pci_intv);
pci_intv <= pci_p_intd_b & pci_p_intc_b & pci_p_intb_b & pci_p_inta_b;
pci_host <= '0'; -- Always host
pci_66 <= '0';
-----------------------------------------------------------------------
--- SYSTEM MONITOR ---------------------------------------------------
-----------------------------------------------------------------------
grsmon: if CFG_GRSYSMON = 1 generate
sysm0 : grsysmon generic map (tech => fabtech, hindex => 8,
hirq => 1, caddr => 16#003#, cmask => 16#fff#,
saddr => 16#004#, smask => 16#ffe#, split => CFG_SPLIT,
extconvst => 0, wrdalign => 1, INIT_40 => X"0000",
INIT_41 => X"0000", INIT_42 => X"0800", INIT_43 => X"0000",
INIT_44 => X"0000", INIT_45 => X"0000", INIT_46 => X"0000",
INIT_47 => X"0000", INIT_48 => X"0000", INIT_49 => X"0000",
INIT_4A => X"0000", INIT_4B => X"0000", INIT_4C => X"0000",
INIT_4D => X"0000", INIT_4E => X"0000", INIT_4F => X"0000",
INIT_50 => X"0000", INIT_51 => X"0000", INIT_52 => X"0000",
INIT_53 => X"0000", INIT_54 => X"0000", INIT_55 => X"0000",
INIT_56 => X"0000", INIT_57 => X"0000",
SIM_MONITOR_FILE => "sysmon.txt")
port map (rstn, clkm, ahbsi, ahbso(8), sysmoni, sysmono);
sysmoni.convst <= '0';
sysmoni.convstclk <= '0';
sysmoni.vauxn <= (others => '0');
sysmoni.vauxp <= (others => '0');
-- sysmoni.vn <= test_mon_vn0_n;
-- sysmoni.vp <= test_mon_vp0_p;
end generate grsmon;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 9, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(9));
end generate;
-----------------------------------------------------------------------
--- APB bridge with LOGAN --------------------------------------------
-----------------------------------------------------------------------
-- log: if CFG_LOGAN = 1 generate -- Logan is enabled by constant
-- -- declared above
-- apb0 : apbctrl -- AHB/APB bridge
-- generic map (hindex => 11, haddr => 16#F00#, nslaves => 1)
-- port map (rstn, clkm, ahbsi, ahbso(11), apbi1, apbo1);
-- logan0 : logan -- Logic analyzer
-- generic map (dbits => 64, depth => 4096, trigl => 2, usereg => 1,
-- usequal => 0, pindex => 0, paddr => 0, pmask => 16#F00#,
-- memtech => memtech)
-- port map (rstn, clkm, pciclk, apbi1, apbo1(0), signals);
-- signals(0) <= pcii.rst;
-- signals(1) <= pcii.gnt;
-- signals(2) <= pcii.idsel;
-- signals(34 downto 3) <= pcii.ad;
-- signals(38 downto 35) <= pcii.cbe;
-- signals(39) <= pcii.frame;
-- signals(40) <= pcii.irdy;
-- signals(41) <= pcii.trdy;
-- signals(42) <= pcii.devsel;
-- signals(43) <= pcii.stop;
-- signals(44) <= pcii.lock;
-- signals(45) <= pcii.perr;
-- signals(46) <= pcii.serr;
-- signals(47) <= pcii.par;
-- signals(48) <= pcii.host;
-- signals(49) <= pcii.pci66;
-- signals(53 downto 50) <= pcii.int;
-- signals(58 downto 54) <= pci_arb_gnt(0 to 4);
-- signals(63 downto 59) <= pci_arb_req(0 to 4);
-- end generate log;
nolog: if CFG_LOGAN /= 1 generate
signals <= (others => '0');
end generate nolog;
-----------------------------------------------------------------------
--- AHB DEBUG --------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG));
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (NCPU+CFG_AHB_UART+CFG_ETH+CFG_AHB_ETH+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => system_table(XILINX_ML510),
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-avnet-eval-xc4vlx60/testbench.vhd | 1 | 9282 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.config.all; -- configuration
use work.debug.all;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
use grlib.devices.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 10; -- system clock period
romwidth : integer := 16; -- rom data width (8/32)
romdepth : integer := 16 -- rom address depth
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal rst : std_logic := '1'; -- Reset
signal rstn: std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(22 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal oen : std_ulogic;
signal writen : std_ulogic;
signal iosn : std_ulogic;
-- ddr memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (1 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (1 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (15 downto 0); -- ddr data
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal rtsn, ctsn : std_ulogic;
signal error : std_logic;
signal pio : std_logic_vector(15 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal clk50 : std_ulogic := '1';
signal clk_200p : std_ulogic := '0';
signal clk_200n : std_ulogic := '1';
signal plllock : std_ulogic;
-- pulled up high, therefore std_logic
signal txd1, rxd1 : std_logic;
signal eth_macclk, etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic := '0';
signal erxd, etxd : std_logic_vector(3 downto 0) := (others => '0');
signal erxdt, etxdt : std_logic_vector(7 downto 0) := (others => '0');
signal emdc, emdio : std_logic; --dummy signal for the mdc,mdio in the phy which is not used
constant lresp : boolean := false;
signal resoutn : std_logic;
signal dsubren : std_ulogic;
signal dsuactn : std_ulogic;
begin
dsubren <= not dsubre;
-- clock and reset
clk <= not clk after ct * 1 ns;
clk50 <= not clk50 after 10 ns;
clk_200p <= not clk_200p after 2.5 ns;
clk_200n <= not clk_200n after 2.5 ns;
rst <= '1', '0' after 1000 ns;
rstn <= not rst;
dsuen <= '0'; dsubre <= '0'; rxd1 <= 'H';
address(0) <= '0';
ddr_dqs <= (others => 'L');
d3 : entity work.leon3mp
port map (
resetn => rst,
resoutn => resoutn,
clk_100mhz => clk,
clk_50mhz => clk50,
clk_200p => clk_200p,
clk_200n => clk_200n,
errorn => error,
address => address(22 downto 1),
data => data(31 downto 16),
testdata => data(15 downto 0),
ddr_clk0 => ddr_clk,
ddr_clk0b => ddr_clkb,
ddr_clk_fb => ddr_clk_fb,
ddr_cke0 => ddr_cke,
ddr_cs0b => ddr_csb,
ddr_web => ddr_web,
ddr_rasb => ddr_rasb,
ddr_casb => ddr_casb,
ddr_dm => ddr_dm,
ddr_dqs => ddr_dqs,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dq => ddr_dq,
sertx => dsutx,
serrx => dsurx,
rtsn => rtsn,
ctsn => ctsn,
dsuen => dsuen,
dsubre => dsubre,
dsuact => dsuactn,
oen => oen,
writen => writen,
iosn => iosn,
romsn => romsn(0),
emdio => emdio,
etx_clk => etx_clk,
erx_clk => erx_clk,
erxd => erxd,
erx_dv => erx_dv,
erx_er => erx_er,
erx_col => erx_col,
erx_crs => erx_crs,
etxd => etxd,
etx_en => etx_en,
etx_er => etx_er,
emdc => emdc
);
ddr_clk_fb <= ddr_clk;
u1 : mt46v16m16
generic map (index => -1, fname => sdramfile, fdelay => 300*CFG_MIG_DDR2)
port map(
Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad,
Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
Dm => ddr_dm(1 downto 0));
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i+4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), data(31-i*8 downto 24-i*8), romsn(0),
writen, oen);
end generate;
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
erxd <= erxdt(3 downto 0);
etxdt <= "0000" & etxd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0, address => 3)
port map(resoutn, emdio, etx_clk, erx_clk, erxdt, erx_dv,
erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, eth_macclk);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5 us;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
test0 : grtestmod
port map ( rstn, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/ec/ddr_ec.vhd | 1 | 2040 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr_ec
-- File: ddr_ec.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Lattice DDR regs
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library ec;
use ec.ODDRXB;
--pragma translate_on
entity ec_oddr_reg is
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end;
architecture rtl of ec_oddr_reg is
component ODDRXB
port(
DA : in STD_LOGIC;
DB : in STD_LOGIC;
CLK : in STD_LOGIC;
LSR : in STD_LOGIC;
Q : out STD_LOGIC
);
end component;
begin
U0 : ODDRXB port map( DA => D1, DB => D2, CLK => C1, LSR => R, Q => Q);
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/opencores/i2c/i2c_master_byte_ctrl.vhd | 4 | 13633 | ---------------------------------------------------------------------
---- ----
---- WISHBONE revB2 compl. I2C Master Core; byte-controller ----
---- ----
---- ----
---- Author: Richard Herveille ----
---- [email protected] ----
---- www.asics.ws ----
---- ----
---- Downloaded from: http://www.opencores.org/projects/i2c/ ----
---- ----
---------------------------------------------------------------------
---- ----
---- Copyright (C) 2000 Richard Herveille ----
---- [email protected] ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
---- ----
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
---- POSSIBILITY OF SUCH DAMAGE. ----
---- ----
---------------------------------------------------------------------
-- CVS Log
--
-- $Id: i2c_master_byte_ctrl.vhd,v 1.5 2004/02/18 11:41:48 rherveille Exp $
--
-- $Date: 2004/02/18 11:41:48 $
-- $Revision: 1.5 $
-- $Author: rherveille $
-- $Locker: $
-- $State: Exp $
--
-- Change History:
-- $Log: i2c_master_byte_ctrl.vhd,v $
-- Revision 1.5 2004/02/18 11:41:48 rherveille
-- Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.
--
-- Revision 1.4 2003/08/09 07:01:13 rherveille
-- Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
-- Fixed a potential bug in the byte controller's host-acknowledge generation.
--
-- Revision 1.3 2002/12/26 16:05:47 rherveille
-- Core is now a Multimaster I2C controller.
--
-- Revision 1.2 2002/11/30 22:24:37 rherveille
-- Cleaned up code
--
-- Revision 1.1 2001/11/05 12:02:33 rherveille
-- Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
-- Code updated, is now up-to-date to doc. rev.0.4.
-- Added headers.
--
-- Modified by Jan Andersson ([email protected]:.
-- Changed std_logic_arith to numeric_std.
-- Propagate filter generic
--
------------------------------------------
-- Byte controller section
------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity i2c_master_byte_ctrl is
generic (filter : integer; dynfilt : integer);
port (
clk : in std_logic;
rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
ena : in std_logic; -- core enable signal
clk_cnt : in std_logic_vector(15 downto 0); -- 4x SCL
-- input signals
start,
stop,
read,
write,
ack_in : std_logic;
din : in std_logic_vector(7 downto 0);
filt : in std_logic_vector((filter-1)*dynfilt downto 0);
-- output signals
cmd_ack : out std_logic; -- command done
ack_out : out std_logic;
i2c_busy : out std_logic; -- arbitration lost
i2c_al : out std_logic; -- i2c bus busy
dout : out std_logic_vector(7 downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end entity i2c_master_byte_ctrl;
architecture structural of i2c_master_byte_ctrl is
component i2c_master_bit_ctrl is
generic (filter : integer; dynfilt : integer);
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
ena : in std_logic; -- core enable signal
clk_cnt : in std_logic_vector(15 downto 0); -- clock prescale value
cmd : in std_logic_vector(3 downto 0);
cmd_ack : out std_logic; -- command done
busy : out std_logic; -- i2c bus busy
al : out std_logic; -- arbitration lost
din : in std_logic;
dout : out std_logic;
filt : in std_logic_vector((filter-1)*dynfilt downto 0);
-- i2c lines
scl_i : in std_logic; -- i2c clock line input
scl_o : out std_logic; -- i2c clock line output
scl_oen : out std_logic; -- i2c clock line output enable, active low
sda_i : in std_logic; -- i2c data line input
sda_o : out std_logic; -- i2c data line output
sda_oen : out std_logic -- i2c data line output enable, active low
);
end component i2c_master_bit_ctrl;
-- commands for bit_controller block
constant I2C_CMD_NOP : std_logic_vector(3 downto 0) := "0000";
constant I2C_CMD_START : std_logic_vector(3 downto 0) := "0001";
constant I2C_CMD_STOP : std_logic_vector(3 downto 0) := "0010";
constant I2C_CMD_READ : std_logic_vector(3 downto 0) := "0100";
constant I2C_CMD_WRITE : std_logic_vector(3 downto 0) := "1000";
-- signals for bit_controller
signal core_cmd : std_logic_vector(3 downto 0);
signal core_ack, core_txd, core_rxd : std_logic;
signal al : std_logic;
-- signals for shift register
signal sr : std_logic_vector(7 downto 0); -- 8bit shift register
signal shift, ld : std_logic;
-- signals for state machine
signal go, host_ack : std_logic;
-- Added init value to dcnt to prevent simulation meta-value
-- - [email protected]
-- removed init value as it is not compatible with Formality
-- - [email protected]
signal dcnt : std_logic_vector(2 downto 0)
-- pragma translate_off
:= (others => '0')
-- pragma translate_on
; -- data counter
signal cnt_done : std_logic;
begin
-- hookup bit_controller
bit_ctrl: i2c_master_bit_ctrl
generic map (filter, dynfilt)
port map(
clk => clk,
rst => rst,
nReset => nReset,
ena => ena,
clk_cnt => clk_cnt,
cmd => core_cmd,
cmd_ack => core_ack,
busy => i2c_busy,
al => al,
din => core_txd,
dout => core_rxd,
filt => filt,
scl_i => scl_i,
scl_o => scl_o,
scl_oen => scl_oen,
sda_i => sda_i,
sda_o => sda_o,
sda_oen => sda_oen
);
i2c_al <= al;
-- generate host-command-acknowledge
cmd_ack <= host_ack;
-- generate go-signal
go <= (read or write or stop) and not host_ack;
-- assign Dout output to shift-register
dout <= sr;
-- generate shift register
shift_register: process(clk, nReset)
begin
if (nReset = '0') then
sr <= (others => '0');
elsif (clk'event and clk = '1') then
if (rst = '1') then
sr <= (others => '0');
elsif (ld = '1') then
sr <= din;
elsif (shift = '1') then
sr <= (sr(6 downto 0) & core_rxd);
end if;
end if;
end process shift_register;
-- generate data-counter
data_cnt: process(clk, nReset)
begin
if (nReset = '0') then
dcnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (rst = '1') then
dcnt <= (others => '0');
elsif (ld = '1') then
dcnt <= (others => '1'); -- load counter with 7
elsif (shift = '1') then
dcnt <= dcnt -1;
end if;
end if;
end process data_cnt;
cnt_done <= '1' when (dcnt = "000") else '0';
--
-- state machine
--
statemachine : block
type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop);
signal c_state : states;
begin
--
-- command interpreter, translate complex commands into simpler I2C commands
--
nxt_state_decoder: process(clk, nReset)
begin
if (nReset = '0') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1' or al = '1') then
core_cmd <= I2C_CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
host_ack <= '0';
c_state <= st_idle;
ack_out <= '0';
else
-- initialy reset all signal
core_txd <= sr(7);
shift <= '0';
ld <= '0';
host_ack <= '0';
case c_state is
when st_idle =>
if (go = '1') then
if (start = '1') then
c_state <= st_start;
core_cmd <= I2C_CMD_START;
elsif (read = '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
elsif (write = '1') then
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
else -- stop
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
end if;
ld <= '1';
end if;
when st_start =>
if (core_ack = '1') then
if (read = '1') then
c_state <= st_read;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write;
core_cmd <= I2C_CMD_WRITE;
end if;
ld <= '1';
end if;
when st_write =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_READ;
else
c_state <= st_write; -- stay in same state
core_cmd <= I2C_CMD_WRITE; -- write next bit
shift <= '1';
end if;
end if;
when st_read =>
if (core_ack = '1') then
if (cnt_done = '1') then
c_state <= st_ack;
core_cmd <= I2C_CMD_WRITE;
else
c_state <= st_read; -- stay in same state
core_cmd <= I2C_CMD_READ; -- read next bit
end if;
shift <= '1';
core_txd <= ack_in;
end if;
when st_ack =>
if (core_ack = '1') then
-- check for stop; Should a STOP command be generated ?
if (stop = '1') then
c_state <= st_stop;
core_cmd <= I2C_CMD_STOP;
else
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
-- assign ack_out output to core_rxd (contains last received bit)
ack_out <= core_rxd;
core_txd <= '1';
else
core_txd <= ack_in;
end if;
when st_stop =>
if (core_ack = '1') then
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
-- generate command acknowledge signal
host_ack <= '1';
end if;
when others => -- illegal states
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
report ("Byte controller entered illegal state.");
end case;
end if;
end if;
end process nxt_state_decoder;
end block statemachine;
end architecture structural;
| gpl-2.0 |
borti4938/sd2snes | verilog/sd2snes_sdd1/Test_Top_SDD1.vhd | 2 | 50000 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18.03.2018 22:42:12
-- Design Name:
-- Module Name: Test_FIFO_Input - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.math_real.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Test_Top_SDD1 is
-- Port ( );
end Test_Top_SDD1;
architecture Behavioral of Test_Top_SDD1 is
constant SD2SNES_PERIOD : time := 10.416 ns;
constant CLK_PERIOD : time := 46.56 ns;
constant PHI2_PERIOD : time := 6*CLK_PERIOD;
constant tBAS : time := 33 ns;
constant tADS : time := 30 ns;
constant tMDS : time := 30 ns;
constant tLATCH : time := 25 ns;
constant tDECODER : time := 25 ns;
constant ROM_tACCESS : time := 70 ns;
COMPONENT SDD1
Port( MCLK : in STD_LOGIC;
SNES_CPU_CLK : in STD_LOGIC;
SNES_REFRESH : in STD_LOGIC;
RESET : in STD_LOGIC;
SRAM_CS : out STD_LOGIC;
ROM_OE : out STD_LOGIC;
ROM_CS : out STD_LOGIC;
ROM_ADDR : out STD_LOGIC_VECTOR (21 downto 0);
ROM_DATA : in STD_LOGIC_VECTOR (15 downto 0);
SNES_ADDR : in STD_LOGIC_VECTOR (23 downto 0);
SNES_DATA_IN : in STD_LOGIC_VECTOR (7 downto 0);
SNES_DATA_OUT : out STD_LOGIC_VECTOR (7 downto 0);
SNES_RD : in STD_LOGIC;
SNES_WR : in STD_LOGIC;
SNES_WR_End : in STD_LOGIC );
END COMPONENT;
type bit_vector_file is file of bit_vector;
type bytes_file is file of integer;
file comp_data : bit_vector_file;
file descomp_data : bytes_file;
shared variable Size : integer := 0;
type ROM_Array_t is array(65535 downto 0) of STD_LOGIC_VECTOR(15 downto 0);
signal MaskROM_0 : ROM_Array_t := (others => (others => '0'));
signal MaskROM_1 : ROM_Array_t := (others => (others => '0'));
signal SD2SNES_CLK : STD_LOGIC := '0';
signal MCLK : STD_LOGIC := '0';
signal CPU_CLK : STD_LOGIC := '0';
signal RESET : STD_LOGIC := '0';
signal SRAM_CS : STD_LOGIC := '1';
signal ROM_OE : STD_LOGIC := '1';
signal ROM_CS : STD_LOGIC := '1';
signal ROM_ADDR : STD_LOGIC_VECTOR(21 downto 0) := (others => '0');
signal ROM_DATA : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
signal SNES_RD : STD_LOGIC := '1';
signal SNES_WR : STD_LOGIC := '1';
signal SNES_WR_Strobe : STD_LOGIC := '0';
signal SNES_ADDR : STD_LOGIC_VECTOR(23 downto 0) := (others => '0');
signal SNES_DATA_IN : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal SNES_DATA_OUT : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal CPU_RD_CYCLE : STD_LOGIC := '0';
signal CPU_WR_CYCLE : STD_LOGIC := '0';
signal CPU_ADDR : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
signal CPU_BANK : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal CPU_DATA : STD_LOGIC_VECTOR(7 downto 0) := (others => 'Z');
signal CPU_VDA : STD_LOGIC := '0';
signal CPU_VPA : STD_LOGIC := '0';
signal ROM_Data_tready : STD_LOGIC := '0';
signal ROM_Data_tvalid : STD_LOGIC := '0';
signal ROM_Data_tdata : STD_LOGIC_VECTOR(7 downto 0) := (others => '0');
signal DMA_Data_tvalid_Pipe : STD_LOGIC_VECTOR(1 downto 0) := "00";
signal DMA_Data_tvalid : STD_LOGIC := '0';
signal DMA_Data_dword : STD_LOGIC_VECTOR(31 downto 0) := (others => '0');
signal Instruction_Addr : STD_LOGIC_VECTOR(23 downto 0) := (others => '0');
signal Compressed_Addr : STD_LOGIC_VECTOR(23 downto 0) := (others => '0');
signal Compressed_Size : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
signal Start_Decompression : STD_LOGIC := '0';
signal End_Decompression : STD_LOGIC := '0';
begin
uut : SDD1
Port map(MCLK => SD2SNES_CLK,
RESET => RESET,
SNES_CPU_CLK => CPU_CLK,
SNES_REFRESH => '0',
SRAM_CS => SRAM_CS,
ROM_OE => ROM_OE,
ROM_CS => ROM_CS,
ROM_ADDR => ROM_ADDR,
ROM_DATA => ROM_DATA,
SNES_ADDR => SNES_ADDR,
SNES_DATA_IN => SNES_DATA_IN,
SNES_DATA_OUT => SNES_DATA_OUT,
SNES_RD => SNES_RD,
SNES_WR => SNES_WR,
SNES_WR_End => SNES_WR_Strobe );
Process
variable next_vector : bit_vector (0 downto 0);
variable actual_len : natural;
Begin
--Size := 4194304;
--file_open(comp_data, "StarOcean.smc", READ_MODE);
--Size := 3072;
--file_open(comp_data, "sdd1_chunk_0000.bin", READ_MODE);
--Size := 4034;
--file_open(comp_data, "sdd1_chunk_1100.bin", READ_MODE);
Size := 6144;
file_open(comp_data, "sdd1_chunk_0xFED27F.bin", READ_MODE);
--Size := 2084;
--file_open(comp_data, "sdd1_chunk_0xFFD0AB.bin", READ_MODE);
--Size := 768;
--file_open(comp_data, "sdd1_chunk_0xDE84AC.bin", READ_MODE);
--Size := 896;
--file_open(comp_data, "sdd1_chunk_0xDE9AF5.bin", READ_MODE);
file_open(descomp_data, "StarOcean_core.smc", WRITE_MODE);
-- read full ROM from file to memory
for i in 0 to (Size/2)-1 loop
-- read word from file
if not endfile(comp_data) then
read(comp_data, next_vector, actual_len);
if actual_len > next_vector'length then
report "vector too long";
else
MaskROM_0(i)(7 downto 0) <= conv_std_logic_vector(bit'pos(next_vector(0)),8);
end if;
read(comp_data, next_vector, actual_len);
if actual_len > next_vector'length then
report "vector too long";
else
MaskROM_0(i)(15 downto 8) <= conv_std_logic_vector(bit'pos(next_vector(0)),8);
end if;
end if;
wait for 1ps;
end loop;
-- for i in 0 to 1048575 loop
-- -- read word from file
-- if not endfile(comp_data) then
-- read(comp_data, next_vector, actual_len);
-- if actual_len > next_vector'length then
-- report "vector too long";
-- else
-- MaskROM_1(i)(7 downto 0) <= conv_std_logic_vector(bit'pos(next_vector(0)),8);
-- end if;
-- read(comp_data, next_vector, actual_len);
-- if actual_len > next_vector'length then
-- report "vector too long";
-- else
-- MaskROM_1(i)(15 downto 8) <= conv_std_logic_vector(bit'pos(next_vector(0)),8);
-- end if;
-- end if;
-- wait for 1 ps;
-- end loop;
-- begin reset
RESET <= '0';
wait for 1 us;
RESET <= '1';
wait until falling_edge(MCLK);
wait for 100 ns;
wait until falling_edge(CPU_CLK);
wait for (PHI2_PERIOD-CLK_PERIOD/2);
-- decompress from $DBA078, size $0C00, code $C0238E
Instruction_Addr <= X"C0238E";
--Compressed_Addr <= X"DBA078";
Compressed_Addr <= X"C00000";
Compressed_Size <= conv_std_logic_Vector(Size, 16);
Start_Decompression <= '1';
wait until (End_Decompression = '1');
Start_Decompression <= '0';
--assert false report "NONE. End of simulation." severity failure;
wait;
End Process;
-- process to generate instructions to SDD1 core from real ROM
Process
variable Instruction_Addr_i : STD_LOGIC_VECTOR(23 downto 0);
Begin
wait until (Start_Decompression = '1');
SNES_WR_Strobe <= '0';
End_Decompression <= '0';
Instruction_Addr_i := Instruction_Addr;
-- STA $4800 = $01
-- PHI2 CYCLE 0
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 1
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 2
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 3
SNES_ADDR <= X"004800";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004800";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004800";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004800";
SNES_DATA_IN <= X"01";
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004800";
SNES_DATA_IN <= X"01";
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004800";
SNES_DATA_IN <= X"01";
SNES_RD <= '1';
SNES_WR <= '0';
SNES_WR_Strobe <= '1';
wait until falling_edge(MCLK);
-- STX $4302 = $A078
Instruction_Addr_i := Instruction_Addr_i+3;
-- PHI2 CYCLE 0
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
SNES_WR_Strobe <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 1
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 2
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 3
SNES_ADDR <= X"004302";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004302";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004302";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004302";
SNES_DATA_IN <= Compressed_Addr(7 downto 0);
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004302";
SNES_DATA_IN <= Compressed_Addr(7 downto 0);
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004302";
SNES_DATA_IN <= Compressed_Addr(7 downto 0);
SNES_RD <= '1';
SNES_WR <= '0';
SNES_WR_Strobe <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 4
SNES_ADDR <= X"004303";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
SNES_WR_Strobe <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004303";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004303";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004303";
SNES_DATA_IN <= Compressed_Addr(15 downto 8);
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004303";
SNES_DATA_IN <= Compressed_Addr(15 downto 8);
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004303";
SNES_DATA_IN <= Compressed_Addr(15 downto 8);
SNES_RD <= '1';
SNES_WR <= '0';
SNES_WR_Strobe <= '1';
wait until falling_edge(MCLK);
-- STA $4304 = $DB
Instruction_Addr_i := Instruction_Addr_i+3;
-- PHI2 CYCLE 0
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
SNES_WR_Strobe <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 1
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 2
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 3
SNES_ADDR <= X"004304";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004304";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004304";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004304";
SNES_DATA_IN <= Compressed_Addr(23 downto 16);
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004304";
SNES_DATA_IN <= Compressed_Addr(23 downto 16);
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004304";
SNES_DATA_IN <= Compressed_Addr(23 downto 16);
SNES_RD <= '1';
SNES_WR <= '0';
SNES_WR_Strobe <= '1';
wait until falling_edge(MCLK);
-- STX $4305 = $0C00
Instruction_Addr_i := Instruction_Addr_i+3;
-- PHI2 CYCLE 0
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
SNES_WR_Strobe <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 1
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 2
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 3
SNES_ADDR <= X"004305";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004305";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004305";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004305";
SNES_DATA_IN <= Compressed_Size(7 downto 0);
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004305";
SNES_DATA_IN <= Compressed_Size(7 downto 0);
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004305";
SNES_DATA_IN <= Compressed_Size(7 downto 0);
SNES_RD <= '1';
SNES_WR <= '0';
SNES_WR_Strobe <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 4
SNES_ADDR <= X"004306";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
SNES_WR_Strobe <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004306";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004306";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004306";
SNES_DATA_IN <= Compressed_Size(15 downto 8);
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004306";
SNES_DATA_IN <= Compressed_Size(15 downto 8);
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004306";
SNES_DATA_IN <= Compressed_Size(15 downto 8);
SNES_RD <= '1';
SNES_WR <= '0';
SNES_WR_Strobe <= '1';
wait until falling_edge(MCLK);
-- STA $4801 = $01
Instruction_Addr_i := Instruction_Addr_i+3;
-- PHI2 CYCLE 0
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
SNES_WR_Strobe <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 1
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 2
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 3
SNES_ADDR <= X"004801";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004801";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004801";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004801";
SNES_DATA_IN <= X"01";
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004801";
SNES_DATA_IN <= X"01";
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"004801";
SNES_DATA_IN <= X"01";
SNES_RD <= '1';
SNES_WR <= '0';
SNES_WR_Strobe <= '1';
wait until falling_edge(MCLK);
-- PHA
Instruction_Addr_i := Instruction_Addr_i+3;
-- PHI2 CYCLE 0
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
SNES_WR_Strobe <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 1 (IO)
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 2 (SLOW)
SNES_ADDR <= X"0001F0";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"0001F0";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"0001F0";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"0001F0";
SNES_DATA_IN <= X"01";
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"0001F0";
SNES_DATA_IN <= X"01";
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"0001F0";
SNES_DATA_IN <= X"01";
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"0001F0";
SNES_DATA_IN <= X"01";
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"0001F0";
SNES_DATA_IN <= X"01";
SNES_RD <= '1';
SNES_WR <= '0';
SNES_WR_Strobe <= '1';
wait until falling_edge(MCLK);
-- PLA
Instruction_Addr_i := Instruction_Addr_i+1;
-- PHI2 CYCLE 0
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
SNES_WR_Strobe <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 1 (IO)
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 2 (IO)
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 3 (SLOW)
SNES_ADDR <= X"0001F0";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"0001F0";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"0001F0";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"0001F0";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"0001F0";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"0001F0";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"0001F0";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"0001F0";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- STA $420B = $01
Instruction_Addr_i := Instruction_Addr_i+1;
-- PHI2 CYCLE 0
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 1
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 2
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i+2;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- PHI2 CYCLE 3
SNES_ADDR <= X"00420B";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"00420B";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"00420B";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"00420B";
SNES_DATA_IN <= X"01";
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"00420B";
SNES_DATA_IN <= X"01";
SNES_RD <= '1';
SNES_WR <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= X"00420B";
SNES_DATA_IN <= X"01";
SNES_RD <= '1';
SNES_WR <= '0';
SNES_WR_Strobe <= '1';
wait until falling_edge(MCLK);
-- STZ $4800 = $00
Instruction_Addr_i := Instruction_Addr_i+3;
-- PHI2 CYCLE 0
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
SNES_WR_Strobe <= '0';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Instruction_Addr_i;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- DMA pre-sync (0 to 7 cycles)
SNES_ADDR <= Instruction_Addr_i+1;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- DMA setup (8 cycles)
SNES_ADDR <= X"00FFFF";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"00FFFF";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"00FFFF";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"00FFFF";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"00FFFF";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"00FFFF";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"00FFFF";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= X"00FFFF";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
-- DMA transfer
for i in 1 to conv_integer(Compressed_Size) loop
DMA_Data_tvalid <= '0';
SNES_ADDR <= Compressed_Addr;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Compressed_Addr;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Compressed_Addr;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Compressed_Addr;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Compressed_Addr;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Compressed_Addr;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Compressed_Addr;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
wait until falling_edge(MCLK);
SNES_ADDR <= Compressed_Addr;
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '0';
SNES_WR <= '1';
DMA_Data_tvalid <= '1';
wait until falling_edge(MCLK);
end loop;
SNES_ADDR <= X"C00000";
SNES_DATA_IN <= (others => 'Z');
SNES_RD <= '1';
SNES_WR <= '1';
DMA_Data_tvalid <= '0';
End_Decompression <= '1';
wait until (Start_Decompression = '0');
End Process;
-- read from MaskROM
process( ROM_OE, ROM_CS, ROM_ADDR )
Begin
if( ROM_CS = '0' AND ROM_OE = '0' ) then
ROM_DATA <= MaskROM_0(conv_integer(ROM_ADDR)) after ROM_tACCESS;
else
ROM_DATA <= (others => 'Z') after 15 ns;
end if;
End Process;
-- output data file
process( SD2SNES_CLK )
variable valor : integer;
variable DMA_Data_Idx : integer := 0;
begin
if rising_edge( SD2SNES_CLK ) then
DMA_Data_tvalid_Pipe <= DMA_Data_tvalid_Pipe(0) & DMA_Data_tvalid;
if( DMA_Data_tvalid_Pipe = "01" ) then
if( DMA_Data_Idx = 3 ) then
-- write word to disk
valor := conv_integer(SNES_DATA_OUT & DMA_Data_dword(31 downto 8));
write(descomp_data, valor);
DMA_Data_Idx := 0;
else
DMA_Data_dword <= SNES_DATA_OUT & DMA_Data_dword(31 downto 8);
DMA_Data_Idx := DMA_Data_Idx + 1;
end if;
end if;
end if;
end process;
-- clock generator
Process
Begin
MCLK <= '0';
wait for CLK_PERIOD/2;
MCLK <= '1';
wait for CLK_PERIOD/2;
End Process;
Process
Begin
CPU_CLK <= '1';
wait for PHI2_PERIOD/2;
CPU_CLK <= '0';
wait for PHI2_PERIOD/2;
End Process;
Process
Begin
wait for 3ns;
loop
SD2SNES_CLK <= '1';
wait for SD2SNES_PERIOD/2;
SD2SNES_CLK <= '0';
wait for SD2SNES_PERIOD/2;
end loop;
End Process;
end Behavioral;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/unisim/memory_unisim.vhd | 1 | 26997 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: mem_xilinx_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory generators for Xilinx rams
------------------------------------------------------------------------------
-- parametrisable sync ram generator using UNISIM RAMB16 block rams
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
--pragma translate_off
library unisim;
use unisim.RAMB16_S36_S36;
use unisim.RAMB16_S36;
use unisim.RAMB16_S18;
use unisim.RAMB16_S9;
use unisim.RAMB16_S4;
use unisim.RAMB16_S2;
use unisim.RAMB16_S1;
--pragma translate_on
entity unisim_syncram is
generic ( abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture behav of unisim_syncram is
component RAMB16_S36_S36
port (
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
component RAMB16_S1
port (
DO : out std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (13 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (0 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S2
port (
DO : out std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (12 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (1 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S4
port (
DO : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (11 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (3 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S9
port (
DO : out std_logic_vector (7 downto 0);
DOP : out std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (10 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (7 downto 0);
DIP : in std_logic_vector (0 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S18
port (
DO : out std_logic_vector (15 downto 0);
DOP : out std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (9 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (15 downto 0);
DIP : in std_logic_vector (1 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S36
port (
DO : out std_logic_vector (31 downto 0);
DOP : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (8 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (31 downto 0);
DIP : in std_logic_vector (3 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component generic_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic);
end component;
signal gnd : std_ulogic;
signal do, di : std_logic_vector(dbits+72 downto 0);
signal xa, ya : std_logic_vector(19 downto 0);
begin
gnd <= '0'; dataout <= do(dbits-1 downto 0); di(dbits-1 downto 0) <= datain;
di(dbits+72 downto dbits) <= (others => '0'); xa(abits-1 downto 0) <= address;
xa(19 downto abits) <= (others => '0'); ya(abits-1 downto 0) <= address;
ya(19 downto abits) <= (others => '1');
a0 : if (abits <= 5) and (GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) = 0) generate
r0 : generic_syncram generic map (abits, dbits)
port map (clk, address, datain, do(dbits-1 downto 0), write);
do(dbits+72 downto dbits) <= (others => '0');
end generate;
a8 : if ((abits > 5 or GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) /= 0) and
(abits <= 8)) generate
x : for i in 0 to ((dbits-1)/72) generate
r0 : RAMB16_S36_S36 port map (
do(i*72+36+31 downto i*72+36), do(i*72+31 downto i*72),
do(i*72+36+32+3 downto i*72+36+32), do(i*72+32+3 downto i*72+32),
xa(8 downto 0), ya(8 downto 0), clk, clk,
di(i*72+36+31 downto i*72+36), di(i*72+31 downto i*72),
di(i*72+36+32+3 downto i*72+36+32), di(i*72+32+3 downto i*72+32),
enable, enable, gnd, gnd, write, write);
end generate;
do(dbits+72 downto 72*(((dbits-1)/72)+1)) <= (others => '0');
end generate;
a9 : if (abits = 9) generate
x : for i in 0 to ((dbits-1)/36) generate
r : RAMB16_S36 port map ( do(((i+1)*36)-5 downto i*36),
do(((i+1)*36)-1 downto i*36+32), xa(8 downto 0), clk,
di(((i+1)*36)-5 downto i*36), di(((i+1)*36)-1 downto i*36+32),
enable, gnd, write);
end generate;
do(dbits+72 downto 36*(((dbits-1)/36)+1)) <= (others => '0');
end generate;
a10 : if (abits = 10) generate
x : for i in 0 to ((dbits-1)/18) generate
r : RAMB16_S18 port map ( do(((i+1)*18)-3 downto i*18),
do(((i+1)*18)-1 downto i*18+16), xa(9 downto 0), clk,
di(((i+1)*18)-3 downto i*18), di(((i+1)*18)-1 downto i*18+16),
enable, gnd, write);
end generate;
do(dbits+72 downto 18*(((dbits-1)/18)+1)) <= (others => '0');
end generate;
a11 : if abits = 11 generate
x : for i in 0 to ((dbits-1)/9) generate
r : RAMB16_S9 port map ( do(((i+1)*9)-2 downto i*9),
do(((i+1)*9)-1 downto i*9+8), xa(10 downto 0), clk,
di(((i+1)*9)-2 downto i*9), di(((i+1)*9)-1 downto i*9+8),
enable, gnd, write);
end generate;
do(dbits+72 downto 9*(((dbits-1)/9)+1)) <= (others => '0');
end generate;
a12 : if abits = 12 generate
x : for i in 0 to ((dbits-1)/4) generate
r : RAMB16_S4 port map ( do(((i+1)*4)-1 downto i*4), xa(11 downto 0),
clk, di(((i+1)*4)-1 downto i*4), enable, gnd, write);
end generate;
do(dbits+72 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
end generate;
a13 : if abits = 13 generate
x : for i in 0 to ((dbits-1)/2) generate
r : RAMB16_S2 port map ( do(((i+1)*2)-1 downto i*2), xa(12 downto 0),
clk, di(((i+1)*2)-1 downto i*2), enable, gnd, write);
end generate;
do(dbits+72 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
end generate;
a14 : if abits = 14 generate
x : for i in 0 to (dbits-1) generate
r : RAMB16_S1 port map ( do((i+1)-1 downto i), xa(13 downto 0),
clk, di((i+1)-1 downto i), enable, gnd, write);
end generate;
do(dbits+72 downto dbits) <= (others => '0');
end generate;
a15 : if abits > 14 generate
x: generic_syncram generic map (abits, dbits)
port map (clk, address, datain, do(dbits-1 downto 0), write);
do(dbits+72 downto dbits) <= (others => '0');
end generate;
-- pragma translate_off
-- a_to_high : if abits > 14 generate
-- x : process
-- begin
-- assert false
-- report "Address depth larger than 14 not supported for unisim_syncram"
-- severity failure;
-- wait;
-- end process;
-- end generate;
-- pragma translate_on
end;
LIBRARY ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
library unisim;
use unisim.RAMB16_S36_S36;
use unisim.RAMB16_S18_S18;
use unisim.RAMB16_S9_S9;
use unisim.RAMB16_S4_S4;
use unisim.RAMB16_S2_S2;
use unisim.RAMB16_S1_S1;
--pragma translate_on
entity unisim_syncram_dp is
generic (
abits : integer := 4; dbits : integer := 32
);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic);
end;
architecture behav of unisim_syncram_dp is
component RAMB16_S4_S4
port (
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S1_S1
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (13 downto 0);
ADDRB : in std_logic_vector (13 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S2_S2
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (12 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S9_S9
port (
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S18_S18
port (
DOA : out std_logic_vector (15 downto 0);
DOB : out std_logic_vector (15 downto 0);
DOPA : out std_logic_vector (1 downto 0);
DOPB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (9 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (15 downto 0);
DIB : in std_logic_vector (15 downto 0);
DIPA : in std_logic_vector (1 downto 0);
DIPB : in std_logic_vector (1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
component RAMB16_S36_S36
port (
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
signal gnd, vcc : std_ulogic;
signal do1, do2, di1, di2 : std_logic_vector(dbits+36 downto 0);
signal addr1, addr2 : std_logic_vector(19 downto 0);
begin
gnd <= '0'; vcc <= '1';
dataout1 <= do1(dbits-1 downto 0); dataout2 <= do2(dbits-1 downto 0);
di1(dbits-1 downto 0) <= datain1; di1(dbits+36 downto dbits) <= (others => '0');
di2(dbits-1 downto 0) <= datain2; di2(dbits+36 downto dbits) <= (others => '0');
addr1(abits-1 downto 0) <= address1; addr1(19 downto abits) <= (others => '0');
addr2(abits-1 downto 0) <= address2; addr2(19 downto abits) <= (others => '0');
a9 : if abits <= 9 generate
x : for i in 0 to ((dbits-1)/36) generate
r0 : RAMB16_S36_S36 port map (
do1(((i+1)*36)-5 downto i*36), do2(((i+1)*36)-5 downto i*36),
do1(((i+1)*36)-1 downto i*36+32), do2(((i+1)*36)-1 downto i*36+32),
addr1(8 downto 0), addr2(8 downto 0), clk1, clk2,
di1(((i+1)*36)-5 downto i*36), di2(((i+1)*36)-5 downto i*36),
di1(((i+1)*36)-1 downto i*36+32), di2(((i+1)*36)-1 downto i*36+32),
enable1, enable2, gnd, gnd, write1, write2);
-- vcc, vcc, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 36*(((dbits-1)/36)+1)) <= (others => '0');
do2(dbits+36 downto 36*(((dbits-1)/36)+1)) <= (others => '0');
end generate;
a10 : if abits = 10 generate
x : for i in 0 to ((dbits-1)/18) generate
r0 : RAMB16_S18_S18 port map (
do1(((i+1)*18)-3 downto i*18), do2(((i+1)*18)-3 downto i*18),
do1(((i+1)*18)-1 downto i*18+16), do2(((i+1)*18)-1 downto i*18+16),
addr1(9 downto 0), addr2(9 downto 0), clk1, clk2,
di1(((i+1)*18)-3 downto i*18), di2(((i+1)*18)-3 downto i*18),
di1(((i+1)*18)-1 downto i*18+16), di2(((i+1)*18)-1 downto i*18+16),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 18*(((dbits-1)/18)+1)) <= (others => '0');
do2(dbits+36 downto 18*(((dbits-1)/18)+1)) <= (others => '0');
end generate;
a11 : if abits = 11 generate
x : for i in 0 to ((dbits-1)/9) generate
r0 : RAMB16_S9_S9 port map (
do1(((i+1)*9)-2 downto i*9), do2(((i+1)*9)-2 downto i*9),
do1(((i+1)*9)-1 downto i*9+8), do2(((i+1)*9)-1 downto i*9+8),
addr1(10 downto 0), addr2(10 downto 0), clk1, clk2,
di1(((i+1)*9)-2 downto i*9), di2(((i+1)*9)-2 downto i*9),
di1(((i+1)*9)-1 downto i*9+8), di2(((i+1)*9)-1 downto i*9+8),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 9*(((dbits-1)/9)+1)) <= (others => '0');
do2(dbits+36 downto 9*(((dbits-1)/9)+1)) <= (others => '0');
end generate;
a12 : if abits = 12 generate
x : for i in 0 to ((dbits-1)/4) generate
r0 : RAMB16_S4_S4 port map (
do1(((i+1)*4)-1 downto i*4), do2(((i+1)*4)-1 downto i*4),
addr1(11 downto 0), addr2(11 downto 0), clk1, clk2,
di1(((i+1)*4)-1 downto i*4), di2(((i+1)*4)-1 downto i*4),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
do2(dbits+36 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
end generate;
a13 : if abits = 13 generate
x : for i in 0 to ((dbits-1)/2) generate
r0 : RAMB16_S2_S2 port map (
do1(((i+1)*2)-1 downto i*2), do2(((i+1)*2)-1 downto i*2),
addr1(12 downto 0), addr2(12 downto 0), clk1, clk2,
di1(((i+1)*2)-1 downto i*2), di2(((i+1)*2)-1 downto i*2),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
do2(dbits+36 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
end generate;
a14 : if abits = 14 generate
x : for i in 0 to ((dbits-1)/1) generate
r0 : RAMB16_S1_S1 port map (
do1(((i+1)*1)-1 downto i*1), do2(((i+1)*1)-1 downto i*1),
addr1(13 downto 0), addr2(13 downto 0), clk1, clk2,
di1(((i+1)*1)-1 downto i*1), di2(((i+1)*1)-1 downto i*1),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto dbits) <= (others => '0');
do2(dbits+36 downto dbits) <= (others => '0');
end generate;
-- pragma translate_off
a_to_high : if abits > 14 generate
x : process
begin
assert false
report "Address depth larger than 14 not supported for unisim_syncram_dp"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
entity unisim_syncram_2p is
generic (abits : integer := 6; dbits : integer := 8; sepclk : integer := 0;
wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end;
architecture behav of unisim_syncram_2p is
component unisim_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component generic_syncram_2p
generic (abits : integer := 8; dbits : integer := 32; sepclk : integer := 0);
port (
rclk : in std_ulogic;
wclk : in std_ulogic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_ulogic;
q: out std_logic_vector (dbits -1 downto 0)
);
end component;
signal write2, renable2 : std_ulogic;
signal datain2 : std_logic_vector((dbits-1) downto 0);
begin
-- nowf: if wrfst = 0 generate
write2 <= '0'; renable2 <= renable; datain2 <= (others => '0');
-- end generate;
-- wf : if wrfst = 1 generate
-- write2 <= '0' when (waddress /= raddress) else write;
-- renable2 <= renable or write2; datain2 <= datain;
-- end generate;
a0 : if abits <= 5 and GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) = 0 generate
x0 : generic_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, wclk, raddress, waddress, datain, write, dataout);
end generate;
a6 : if abits > 5 or GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) /= 0 generate
x0 : unisim_syncram_dp generic map (abits, dbits)
port map (wclk, waddress, datain, open, write, write,
rclk, raddress, datain2, dataout, renable2, write2);
end generate;
end;
-- parametrisable sync ram generator using unisim block rams
library ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
library unisim;
use unisim.RAMB16_S36_S36;
--pragma translate_on
entity unisim_syncram64 is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63 downto 0);
dataout : out std_logic_vector (63 downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0)
);
end;
architecture behav of unisim_syncram64 is
component unisim_syncram
generic ( abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component RAMB16_S36_S36
port (
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
signal gnd : std_logic_vector(3 downto 0);
signal xa, ya : std_logic_vector(19 downto 0);
begin
gnd <= "0000";
xa(abits-1 downto 0) <= address; xa(19 downto abits) <= (others => '0');
ya(abits-1 downto 0) <= address; ya(19 downto abits) <= (others => '1');
a8 : if abits <= 8 generate
r0 : RAMB16_S36_S36 port map (
dataout(63 downto 32), dataout(31 downto 0), open, open,
xa(8 downto 0), ya(8 downto 0), clk, clk,
datain(63 downto 32), datain(31 downto 0), gnd, gnd,
enable(1), enable(0), gnd(0), gnd(0), write(1), write(0));
end generate;
a9 : if abits > 8 generate
x1 : unisim_syncram generic map ( abits, 32)
port map (clk, address, datain(63 downto 32), dataout(63 downto 32),
enable(1), write(1));
x2 : unisim_syncram generic map ( abits, 32)
port map (clk, address, datain(31 downto 0), dataout(31 downto 0),
enable(0), write(0));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
entity unisim_syncram128 is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (3 downto 0);
write : in std_logic_vector (3 downto 0)
);
end;
architecture behav of unisim_syncram128 is
component unisim_syncram64 is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63 downto 0);
dataout : out std_logic_vector (63 downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0)
);
end component;
begin
x0 : unisim_syncram64 generic map (abits)
port map (clk, address, datain(127 downto 64), dataout(127 downto 64),
enable(3 downto 2), write(3 downto 2));
x1 : unisim_syncram64 generic map (abits)
port map (clk, address, datain(63 downto 0), dataout(63 downto 0),
enable(1 downto 0), write(1 downto 0));
end;
library ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
library unisim;
use unisim.RAMB16_S36_S36;
--pragma translate_on
entity unisim_syncram128bw is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0)
);
end;
architecture behav of unisim_syncram128bw is
component unisim_syncram
generic ( abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component RAMB16_S9_S9
port (
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
signal gnd : std_logic_vector(3 downto 0);
signal xa, ya : std_logic_vector(19 downto 0);
begin
gnd <= "0000";
xa(abits-1 downto 0) <= address; xa(19 downto abits) <= (others => '0');
ya(abits-1 downto 0) <= address; ya(19 downto abits) <= (others => '1');
a11 : if abits <= 10 generate
x0 : for i in 0 to 7 generate
r0 : RAMB16_S9_S9 port map (
dataout(i*8+7+64 downto i*8+64), dataout(i*8+7 downto i*8), open, open,
xa(10 downto 0), ya(10 downto 0), clk, clk,
datain(i*8+7+64 downto i*8+64), datain(i*8+7 downto i*8), gnd(0 downto 0), gnd(0 downto 0),
enable(i+8), enable(i), gnd(0), gnd(0), write(i+8), write(i));
end generate;
end generate;
a12 : if abits > 10 generate
x0 : for i in 0 to 15 generate
x2 : unisim_syncram generic map ( abits, 8)
port map (clk, address, datain(i*8+7 downto i*8),
dataout(i*8+7 downto i*8), enable(i), write(i));
end generate;
end generate;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/umc18/pads_umc18.vhd | 1 | 8514 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: umcpads_gen
-- File: umcpads_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: UMC pad wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package umcpads is
-- input pad
component ICMT3V port( A : in std_logic; Z : out std_logic); end component;
-- input pad with pull-up
component ICMT3VPU port( A : in std_logic; Z : out std_logic); end component;
-- input pad with pull-down
component ICMT3VPD port( A : in std_logic; Z : out std_logic); end component;
-- schmitt input pad
component ISTRT3V port( A : in std_logic; Z : out std_logic); end component;
-- output pads
component OCM3V4 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V12 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V24 port( Z : out std_logic; A : in std_logic); end component;
-- tri-state output pads
component OCMTR4 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR12 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR24 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
-- bidirectional pads
component BICM3V4 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V12 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V24 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.ICMT3V;
use umc18.ICMT3VPU;
use umc18.ICMT3VPD;
use umc18.ISTRT3V;
-- pragma translate_on
entity umc_inpad is
generic (level : integer := 0; voltage : integer := 0; filter : integer := 0);
port (pad : in std_logic; o : out std_logic);
end;
architecture rtl of umc_inpad is
component ICMT3V port( A : in std_logic; Z : out std_logic); end component;
component ICMT3VPU port( A : in std_logic; Z : out std_logic); end component;
component ICMT3VPD port( A : in std_logic; Z : out std_logic); end component;
component ISTRT3V port( A : in std_logic; Z : out std_logic); end component;
begin
norm : if filter = 0 generate
ip : ICMT3V port map (a => pad, z => o);
end generate;
pu : if filter = pullup generate
ip : ICMT3VPU port map (a => pad, z => o);
end generate;
pd : if filter = pulldown generate
ip : ICMT3VPD port map (a => pad, z => o);
end generate;
sch : if filter = schmitt generate
ip : ISTRT3V port map (a => pad, z => o);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.BICM3V4;
use umc18.BICM3V12;
use umc18.BICM3V24;
-- pragma translate_on
entity umc_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end ;
architecture rtl of umc_iopad is
component BICM3V4 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V12 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V24 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
begin
f4 : if (strength <= 4) generate
op : BICM3V4 port map (a => i, en => en, io => pad, z => o);
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : BICM3V12 port map (a => i, en => en, io => pad, z => o);
end generate;
f24 : if (strength > 16) generate
op : BICM3V24 port map (a => i, en => en, io => pad, z => o);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.OCM3V4;
use umc18.OCM3V12;
use umc18.OCM3V24;
-- pragma translate_on
entity umc_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end ;
architecture rtl of umc_outpad is
component OCM3V4 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V12 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V24 port( Z : out std_logic; A : in std_logic); end component;
begin
f4 : if (strength <= 4) generate
op : OCM3V4 port map (a => i, z => pad);
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : OCM3V12 port map (a => i, z => pad);
end generate;
f24 : if (strength > 12) generate
op : OCM3V24 port map (a => i, z => pad);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.OCMTR4;
use umc18.OCMTR12;
use umc18.OCMTR24;
-- pragma translate_on
entity umc_toutpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end ;
architecture rtl of umc_toutpad is
component OCMTR4 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR12 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR24 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
begin
f4 : if (strength <= 4) generate
op : OCMTR4 port map (a => i, en => en, z => pad);
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : OCMTR12 port map (a => i, en => en, z => pad);
end generate;
f24 : if (strength > 12) generate
op : OCMTR24 port map (a => i, en => en, z => pad);
end generate;
end;
library umc18;
-- pragma translate_off
use umc18.LVDS_Driver;
use umc18.LVDS_Receiver;
use umc18.LVDS_Biasmodule;
-- pragma translate_on
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity umc_lvds_combo is
generic (voltage : integer := 0; width : integer := 1);
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
odval, osval, en : in std_logic_vector(0 to width-1);
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
idval, isval : out std_logic_vector(0 to width-1);
lvdsref : in std_logic);
end ;
architecture rtl of umc_lvds_combo is
component LVDS_Driver port ( A, Vref, HI : in std_logic; Z, ZN : out std_logic); end component;
component LVDS_Receiver port ( A, AN : in std_logic; Z : out std_logic); end component;
component LVDS_Biasmodule port ( RefR : in std_logic; Vref, HI : out std_logic); end component;
signal vref, hi : std_logic;
begin
lvds_bias: LVDS_Biasmodule port map (lvdsref, vref, hi);
swloop : for i in 0 to width-1 generate
spw_rxd_pad : LVDS_Receiver port map (idpadp(i), idpadn(i), idval(i));
spw_rxs_pad : LVDS_Receiver port map (ispadp(i), ispadn(i), isval(i));
spw_txd_pad : LVDS_Driver port map (odval(i), vref, hi, odpadp(i), odpadn(i));
spw_txs_pad : LVDS_Driver port map (osval(i), vref, hi, ospadp(i), ospadn(i));
end generate;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/tech/unisim/ise/simple_simprim.vhd | 4 | 5477 |
library ieee;
use ieee.std_logic_1164.all;
package simple_simprim is
component ramb4_generic
generic ( abits : integer := 10; dbits : integer := 8 );
port (DI : in std_logic_vector (dbits-1 downto 0);
EN : in std_ulogic;
WE : in std_ulogic;
RST : in std_ulogic;
CLK : in std_ulogic;
ADDR : in std_logic_vector (abits-1 downto 0);
DO : out std_logic_vector (dbits-1 downto 0)
);
end component;
component ramb4_sx_sx
generic (abits : integer := 10; dbits : integer := 8 );
port (DIA : in std_logic_vector (dbits-1 downto 0);
DIB : in std_logic_vector (dbits-1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic;
RSTA : in std_ulogic;
RSTB : in std_ulogic;
CLKA : in std_ulogic;
CLKB : in std_ulogic;
ADDRA : in std_logic_vector (abits-1 downto 0);
ADDRB : in std_logic_vector (abits-1 downto 0);
DOA : out std_logic_vector (dbits-1 downto 0);
DOB : out std_logic_vector (dbits-1 downto 0)
);
end component;
component ramb16_sx
generic (abits : integer := 10; dbits : integer := 8 );
port (
DO : out std_logic_vector (dbits-1 downto 0);
ADDR : in std_logic_vector (abits-1 downto 0);
DI : in std_logic_vector (dbits-1 downto 0);
EN : in std_ulogic;
CLK : in std_ulogic;
WE : in std_ulogic;
SSR : in std_ulogic);
end component;
component ram16_sx_sx
generic (abits : integer := 10; dbits : integer := 8 );
port (
DOA : out std_logic_vector (dbits-1 downto 0);
DOB : out std_logic_vector (dbits-1 downto 0);
ADDRA : in std_logic_vector (abits-1 downto 0);
CLKA : in std_ulogic;
DIA : in std_logic_vector (dbits-1 downto 0);
ENA : in std_ulogic;
WEA : in std_ulogic;
ADDRB : in std_logic_vector (abits-1 downto 0);
CLKB : in std_ulogic;
DIB : in std_logic_vector (dbits-1 downto 0);
ENB : in std_ulogic;
WEB : in std_ulogic);
end component;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ramb4_generic is
generic ( abits : integer := 10; dbits : integer := 8 );
port (DI : in std_logic_vector (dbits-1 downto 0);
EN : in std_ulogic;
WE : in std_ulogic;
RST : in std_ulogic;
CLK : in std_ulogic;
ADDR : in std_logic_vector (abits-1 downto 0);
DO : out std_logic_vector (dbits-1 downto 0)
);
end;
architecture behavioral of ramb4_generic is
type mem is array(0 to (2**abits -1))
of std_logic_vector((dbits -1) downto 0);
begin
main : process(clk)
variable memarr : mem;
begin
if rising_edge(clk)then
if (en = '1') and not (is_x(addr)) then
do <= memarr(to_integer(unsigned(addr)));
end if;
if (we and en) = '1' then
if not is_x(addr) then
memarr(to_integer(unsigned(addr))) := di;
end if;
end if;
end if;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ramb16_sx is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
DO : out std_logic_vector (dbits-1 downto 0);
ADDR : in std_logic_vector (abits-1 downto 0);
DI : in std_logic_vector (dbits-1 downto 0);
EN : in std_ulogic;
CLK : in std_ulogic;
WE : in std_ulogic;
SSR : in std_ulogic
);
end;
architecture behav of ramb16_sx is
begin
rp : process(clk)
subtype dword is std_logic_vector(dbits-1 downto 0);
type dregtype is array (0 to 2**abits -1) of DWord;
variable rfd : dregtype := (others => (others => '0'));
begin
if rising_edge(clk) and not is_x (addr) then
if en = '1' then
do <= rfd(to_integer(unsigned(addr)));
if we = '1' then rfd(to_integer(unsigned(addr))) := di; end if;
end if;
end if;
end process;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ram16_sx_sx is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
DOA : out std_logic_vector (dbits-1 downto 0);
DOB : out std_logic_vector (dbits-1 downto 0);
ADDRA : in std_logic_vector (abits-1 downto 0);
CLKA : in std_ulogic;
DIA : in std_logic_vector (dbits-1 downto 0);
ENA : in std_ulogic;
WEA : in std_ulogic;
ADDRB : in std_logic_vector (abits-1 downto 0);
CLKB : in std_ulogic;
DIB : in std_logic_vector (dbits-1 downto 0);
ENB : in std_ulogic;
WEB : in std_ulogic
);
end;
architecture behav of ram16_sx_sx is
signal async : std_ulogic := '0';
begin
ramproc : process(clka, clkb)
subtype dword is std_logic_vector(dbits-1 downto 0);
type dregtype is array (0 to 2**abits -1) of DWord;
variable rfd : dregtype := (others => (others => '0'));
begin
if rising_edge(clka) and not is_x (addra) then
if ena = '1' then
if wea = '1' then
rfd(to_integer(unsigned(addra))) := dia;
end if;
doa <= rfd(to_integer(unsigned(addra)));
else
doa <= (others => '1');
end if;
end if;
if rising_edge(clkb) and not is_x (addrb) then
if enb = '1' then
if web = '1' then
rfd(to_integer(unsigned(addrb))) := dib;
end if;
dob <= rfd(to_integer(unsigned(addrb)));
else
dob <= (others => '1');
end if;
end if;
end process;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/pci/grpci1/pci_mt.vhd | 1 | 28846 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pci_mt
-- File: pci_mt.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Alf Vaerneus - Gaisler Research
-- Description: Simple PCI master and target interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.pci.all;
use gaisler.pcilib.all;
entity pci_mt is
generic (
hmstndx : integer := 0;
abits : integer := 21;
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
master : integer := 1; -- Enable PCI Master
hslvndx : integer := 0;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
nsync : integer range 1 to 2 := 1; -- 1 or 2 sync regs between clocks
oepol : integer := 0
);
port(
rst : in std_logic;
clk : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of pci_mt is
constant REVISION : amba_version_type := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_PCISBRG, 0, REVISION, 0),
4 => ahb_membar(haddr, '0', '0', hmask),
5 => ahb_iobar (ioaddr, 16#E00#),
others => zero32);
constant CSYNC : integer := nsync-1;
constant MADDR_WIDTH : integer := abits;
constant HADDR_WIDTH : integer := 28;
type pci_input_type is record
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
frame : std_logic;
devsel : std_logic;
idsel : std_logic;
trdy : std_logic;
irdy : std_logic;
par : std_logic;
stop : std_logic;
rst : std_logic;
gnt : std_logic;
end record;
type ahbs_input_type is record
haddr : std_logic_vector(HADDR_WIDTH - 1 downto 0);
htrans : std_logic_vector(1 downto 0);
hwrite : std_logic;
hsize : std_logic_vector(1 downto 0);
hburst : std_logic_vector(2 downto 0);
hwdata : std_logic_vector(31 downto 0);
hsel : std_logic;
hiosel : std_logic;
hready : std_logic;
end record;
type pci_target_state_type is (idle, b_busy, s_data, backoff, turn_ar);
type pci_master_state_type is (idle, addr, m_data, turn_ar, s_tar, dr_bus);
type pci_config_command_type is record
ioen : std_logic; -- I/O access enable
men : std_logic; -- Memory access enable
msen : std_logic; -- Master enable
spcen : std_logic; -- Special cycle enable
mwie : std_logic; -- Memory write and invalidate enable
vgaps : std_logic; -- VGA palette snooping enable
per : std_logic; -- Parity error response enable
wcc : std_logic; -- Address stepping enable
serre : std_logic; -- Enable SERR# driver
fbtbe : std_logic; -- Fast back-to-back enable
end record;
type pci_config_status_type is record
c66mhz : std_logic; -- 66MHz capability
udf : std_logic; -- UDF supported
fbtbc : std_logic; -- Fast back-to-back capability
dped : std_logic; -- Data parity error detected
dst : std_logic_vector(1 downto 0); -- DEVSEL timing
sta : std_logic; -- Signaled target abort
rta : std_logic; -- Received target abort
rma : std_logic; -- Received master abort
sse : std_logic; -- Signaled system error
dpe : std_logic; -- Detected parity error
end record;
type pci_reg_type is record
addr : std_logic_vector(MADDR_WIDTH-1 downto 0);
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
lcbe : std_logic_vector(3 downto 0);
t_state : pci_target_state_type; -- PCI target state machine
m_state : pci_master_state_type; -- PCI master state machine
csel : std_logic; -- Configuration chip select
msel : std_logic; -- Memory hit
read : std_logic;
devsel : std_logic; -- PCI device select
trdy : std_logic; -- Target ready
irdy : std_logic; -- Master ready
stop : std_logic; -- Target stop request
par : std_logic; -- PCI bus parity
req : std_logic; -- Master bus request
oe_par : std_logic;
oe_ad : std_logic;
oe_trdy : std_logic;
oe_devsel: std_logic;
oe_ctrl : std_logic;
oe_cbe : std_logic;
oe_stop : std_logic;
oe_frame : std_logic;
oe_irdy : std_logic;
oe_req : std_logic;
noe_par : std_logic;
noe_ad : std_logic;
noe_trdy : std_logic;
noe_devsel: std_logic;
noe_ctrl : std_logic;
noe_cbe : std_logic;
noe_stop : std_logic;
noe_frame : std_logic;
noe_irdy : std_logic;
noe_req : std_logic;
request : std_logic; -- Request from Back-end
frame : std_logic; -- Master frame
bar0 : std_logic_vector(31 downto MADDR_WIDTH);
page : std_logic_vector(31 downto MADDR_WIDTH-1);
comm : pci_config_command_type;
stat : pci_config_status_type;
laddr : std_logic_vector(31 downto 0);
ldata : std_logic_vector(31 downto 0);
pwrite : std_logic;
hwrite : std_logic;
start : std_logic;
hreq : std_logic;
hreq_ack : std_logic_vector(csync downto 0);
preq : std_logic_vector(csync downto 0);
preq_ack : std_logic;
rready : std_logic_vector(csync downto 0);
wready : std_logic_vector(csync downto 0);
sync : std_logic_vector(csync downto 0);
pabort : std_logic;
mcnt : std_logic_vector(2 downto 0);
maddr : std_logic_vector(31 downto 0);
mdata : std_logic_vector(31 downto 0);
stop_req : std_logic;
end record;
type cpu_master_state_type is (idle, sync1, busy, sync2);
type cpu_slave_state_type is (idle, getd, req, sync, read, sync2, t_done);
type cpu_reg_type is record
tdata : std_logic_vector(31 downto 0); -- Target data
maddr : std_logic_vector(31 downto 0); -- Master data
mdata : std_logic_vector(31 downto 0); -- Master data
be : std_logic_vector(3 downto 0);
m_state : cpu_master_state_type; -- AMBA master state machine
s_state : cpu_slave_state_type; -- AMBA slave state machine
start : std_logic_vector(csync downto 0);
hreq : std_logic_vector(csync downto 0);
hreq_ack : std_logic;
preq : std_logic;
preq_ack : std_logic_vector(csync downto 0);
sync : std_logic;
hwrite : std_logic; -- AHB write on PCI
pabort : std_logic_vector(csync downto 0);
perror : std_logic;
rready : std_logic;
wready : std_logic;
hrdata : std_logic_vector(31 downto 0);
hresp : std_logic_vector(1 downto 0);
pciba : std_logic_vector(3 downto 0);
end record;
signal clk_int : std_logic;
signal pr : pci_input_type;
signal hr : ahbs_input_type;
signal r, rin : pci_reg_type;
signal r2, r2in : cpu_reg_type;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal roe_ad, rioe_ad : std_logic_vector(31 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of roe_ad : signal is true;
begin
-- Back-end state machine (AHB clock domain)
comb : process (rst, r2, r, dmao, hr, ahbsi)
variable vdmai : ahb_dma_in_type;
variable v : cpu_reg_type;
variable request : std_logic;
variable hready : std_logic;
variable hresp, hsize, htrans : std_logic_vector(1 downto 0);
variable p_done : std_logic;
begin
v := r2;
vdmai.start := '0'; vdmai.burst := '0'; vdmai.size := "010";
vdmai.address := r.laddr; v.sync := '1';
vdmai.wdata := ahbdrivedata(r.ldata); vdmai.write := r.pwrite;
v.start(0) := r2.start(csync); v.start(csync) := r.start;
v.hreq(0) := r2.hreq(csync); v.hreq(csync) := r.hreq;
v.pabort(0) := r2.pabort(csync); v.pabort(csync) := r.pabort;
v.preq_ack(0) := r2.preq_ack(csync); v.preq_ack(csync) := r.preq_ack;
hready := '1'; hresp := HRESP_OKAY; request := '0';
hsize := "10"; htrans := "00";
p_done := r2.hreq(0) or r2.pabort(0);
---- *** APB register access *** ----
--if (apbi.psel and apbi.penable and apbi.pwrite) = '1' then
--v.pciba := apbi.pwdata(31 downto 28);
--end if;
--apbo.prdata <= r2.pciba & addzero;
if hr.hiosel = '1' then
if hr.hwrite = '1' then v.pciba := ahbreadword(ahbsi.hwdata)(31 downto 28); end if;
v.hrdata := r2.pciba & addzero(27 downto 0);
end if;
---- *** AHB MASTER *** ----
case r2.m_state is
when idle =>
v.sync := '0';
if r2.start(0) = '1' then
if r.pwrite = '1' then v.m_state := sync1; v.wready := '0';
else v.m_state := busy; vdmai.start := '1'; end if;
end if;
when sync1 =>
if r2.start(0) = '0' then v.m_state := busy; vdmai.start := '1'; end if;
when busy =>
if dmao.active = '1' then
if dmao.ready = '1' then
v.rready := not r.pwrite; v.tdata := dmao.rdata(31 downto 0); v.m_state := sync2;
end if;
else vdmai.start := '1'; end if;
when sync2 =>
if r2.start(0) = '0' then
v.m_state := idle; v.wready := '1'; v.rready := '0';
end if;
end case;
---- *** AHB MASTER END *** ----
---- *** AHB SLAVE *** ----
if MASTER = 1 then
if (hr.hready and hr.hsel) = '1' then
hsize := hr.hsize; htrans := hr.htrans;
if (hr.htrans(1) and r.comm.msen) = '1' then request := '1'; end if;
end if;
if (request = '1' and r2.s_state = idle) then
v.maddr := r2.pciba & hr.haddr;
v.hwrite := hr.hwrite;
case hsize is
when "00" => v.be := "1110"; -- Decode byte enable
when "01" => v.be := "1100";
when "10" => v.be := "0000";
when others => v.be := "1111";
end case;
elsif r2.s_state = getd and r2.hwrite = '1' then
v.mdata := hr.hwdata;
end if;
if r2.hreq(0) = '1' then v.hrdata := r.ldata; end if;
if r2.preq_ack(0) = '1' then v.preq := '0'; end if;
if r2.pabort(0) = '1' then v.perror := '1'; end if;
if p_done = '0' then v.hreq_ack := '0'; end if;
-- AHB slave state machine
case r2.s_state is
when idle => if request = '1' then v.s_state := getd; end if;
when getd => v.s_state := req; v.preq := '1';
when req => if r2.preq_ack(0) = '1' then v.s_state := sync; end if;
when sync => if r2.preq_ack(0) = '0' then v.s_state := read; end if;
when read =>
if p_done = '1' then v.hreq_ack := '1'; v.s_state := sync2; end if;
when sync2 => if p_done = '0' then v.s_state := t_done; end if;
when t_done => if request = '1' then v.s_state := idle; end if;
when others => v.s_state := idle;
end case;
if request = '1' then
if r2.s_state = t_done then
if r2.perror = '1' then hresp := HRESP_ERROR;
else hresp := HRESP_OKAY; end if;
v.perror := '0';
else hresp := HRESP_RETRY; end if;
end if;
if r.comm.msen = '0' then hresp := HRESP_ERROR; end if; -- Master disabled
if htrans(1) = '0' then hresp := HRESP_OKAY; end if; -- Response OK for BUSY and IDLE
if (hresp /= HRESP_OKAY and (hr.hready and hr.hsel) = '1') then -- insert one wait cycle
hready := '0';
end if;
if hr.hready = '0' then hresp := r2.hresp; end if;
v.hresp := hresp;
end if;
---- *** AHB SLAVE END *** ----
if rst = '0' then
v.s_state := idle; v.rready := '0'; v.wready := '1';
v.m_state := idle; v.preq := '0'; v.hreq_ack := '0';
v.perror := '0'; v.be := (others => '1');
v.pciba := (others => '0'); v.hresp := (others => '0');
end if;
r2in <= v; dmai <= vdmai;
ahbso.hready <= hready;
ahbso.hresp <= hresp;
ahbso.hrdata <= ahbdrivedata(r2.hrdata);
end process;
ahbso.hconfig <= hconfig when MASTER = 1 else (others => zero32);
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hindex <= hslvndx;
-- PCI target core (PCI clock domain)
pcicomb : process(pcii.rst, pr, pcii, r, r2, roe_ad)
variable v : pci_reg_type;
variable chit, mhit, hit, ready, cwrite : std_logic;
variable cdata, cwdata : std_logic_vector(31 downto 0);
variable comp : std_logic; -- Last transaction cycle on PCI bus
variable iready : std_logic;
variable mto : std_logic;
variable tad, mad : std_logic_vector(31 downto 0);
-- variable cbe : std_logic_vector(3 downto 0);
variable caddr : std_logic_vector(7 downto 2);
variable voe_ad : std_logic_vector(31 downto 0);
variable oe_par : std_logic;
variable oe_ad : std_logic;
variable oe_ctrl : std_logic;
variable oe_trdy : std_logic;
variable oe_devsel: std_logic;
variable oe_cbe : std_logic;
variable oe_stop : std_logic;
variable oe_frame : std_logic;
variable oe_irdy : std_logic;
variable oe_req : std_logic;
begin
-- Process defaults
v := r; v.trdy := '1'; v.stop := '1'; v.frame := '1';
v.oe_ad := '1'; v.devsel := '1'; v.oe_frame := '1';
v.irdy := '1'; v.req := '1'; voe_ad := roe_ad;
v.oe_req := '0'; v.oe_cbe := '1'; v.oe_irdy := '1';
v.rready(0) := r.rready(csync); v.rready(csync) := r2.rready;
v.wready(0) := r.wready(csync); v.wready(csync) := r2.wready;
v.sync(0) := r.sync(csync); v.sync(csync) := r2.sync;
v.preq(0) := r.preq(csync); v.preq(csync) := r2.preq;
v.hreq_ack(0) := r.hreq_ack(csync); v.hreq_ack(csync) := r2.hreq_ack;
comp := '0'; mto := '0'; tad := r.ad; mad := r.ad; v.stop_req := '0';
--cbe := r.cbe;
----- *** PCI TARGET *** --------
-- address decoding
if (r.t_state = s_data) and ((pr.irdy or r.trdy or r.read) = '0') then
cwrite := r.csel;
if ((r.msel and r.addr(MADDR_WIDTH-1)) = '1') and (pr.cbe = "0000") then
v.page := pr.ad(31 downto MADDR_WIDTH-1);
end if;
if (pr.cbe = "0000") and (r.addr(MADDR_WIDTH-1) = '1') then
end if;
else cwrite := '0'; end if;
cdata := (others => '0'); caddr := r.addr(7 downto 2);
case caddr is
when "000000" => -- 0x00, device & vendor id
cdata := conv_std_logic_vector(DEVICE_ID, 16) &
conv_std_logic_vector(VENDOR_ID, 16);
when "000001" => -- 0x04, status & command
cdata(1) := r.comm.men; cdata(2) := r.comm.msen; cdata(25) := '1';
cdata(28) := r.stat.rta; cdata(29) := r.stat.rma;
when "000010" => -- 0x08, class code & revision
when "000011" => -- 0x0c, latency & cacheline size
when "000100" => -- 0x10, BAR0
cdata(31 downto MADDR_WIDTH) := r.bar0;
when others =>
end case;
cwdata := pr.ad;
if pr.cbe(3) = '1' then cwdata(31 downto 24) := cdata(31 downto 24); end if;
if pr.cbe(2) = '1' then cwdata(23 downto 16) := cdata(23 downto 16); end if;
if pr.cbe(1) = '1' then cwdata(15 downto 8) := cdata(15 downto 8); end if;
if pr.cbe(0) = '1' then cwdata( 7 downto 0) := cdata( 7 downto 0); end if;
if cwrite = '1' then
case caddr is
when "000001" => -- 0x04, status & command
v.comm.men := cwdata(1);
v.comm.msen := cwdata(2);
v.stat.rta := r.stat.rta and not cwdata(28);
v.stat.rma := r.stat.rma and not cwdata(29);
when "000100" => -- 0x10, BAR0
v.bar0 := cwdata(31 downto MADDR_WIDTH);
when others =>
end case;
end if;
if (((pr.cbe = pci_config_read) or (pr.cbe = pci_config_write))
and (pr.ad(1 downto 0) = "00"))
then chit := '1'; else chit := '0'; end if;
if ((pr.cbe = pci_memory_read) or (pr.cbe = pci_memory_write))
and (r.bar0 = pr.ad(31 downto MADDR_WIDTH))
and (r.bar0 /= zero(31 downto MADDR_WIDTH))
then mhit := '1'; else mhit := '0'; end if;
hit := r.csel or r.msel;
ready := r.csel or (r.rready(0) and r.read) or (r.wready(0) and not r.read and not r.start) or
r.addr(MADDR_WIDTH-1);
-- target state machine
case r.t_state is
when idle =>
if pr.frame = '0' then v.t_state := b_busy; end if; -- !HIT ?
v.addr := pr.ad(MADDR_WIDTH-1 downto 0); -- v.cbe := pr.cbe;
v.csel := pr.idsel and chit;
v.msel := r.comm.men and mhit; v.read := not pr.cbe(0);
if (r.sync(0) and r.start and r.pwrite) = '1' then v.start := '0'; end if;
when turn_ar =>
if pr.frame = '1' then v.t_state := idle; end if;
if pr.frame = '0' then v.t_state := b_busy; end if; -- !HIT ?
v.addr := pr.ad(MADDR_WIDTH-1 downto 0); -- v.cbe := pr.cbe;
v.csel := pr.idsel and chit;
v.msel := r.comm.men and mhit; v.read := not pr.cbe(0);
if (r.sync(0) and r.start and r.pwrite) = '1' then v.start := '0'; end if;
when b_busy =>
if hit = '1' then
v.t_state := s_data; v.trdy := not ready; v.stop := pr.frame and ready;
v.devsel := '0';
else
v.t_state := backoff;
end if;
when s_data =>
v.stop := r.stop; v.devsel := '0';
v.trdy := r.trdy or not pcii.irdy;
if (pcii.frame and not pcii.irdy) = '1' then
v.t_state := turn_ar; v.stop := '1'; v.trdy := '1'; v.devsel := '1';
end if;
when backoff =>
if pr.frame = '1' then v.t_state := idle; end if;
end case;
if ((r.t_state = s_data) or (r.t_state = turn_ar)) and
(((pr.irdy or pr.trdy) = '0') or
((not pr.irdy and not pr.stop and pr.trdy and not r.start and r.wready(0)) = '1'))
then
if (pr.trdy and r.read)= '0' then v.start := '0'; end if;
if (r.start = '0') and ((r.msel and not r.addr(MADDR_WIDTH-1)) = '1') and
(((pr.trdy and r.read and not r.rready(0)) or (not pr.trdy and not r.read)) = '1')
then
v.laddr := r.page & r.addr(MADDR_WIDTH-2 downto 0);
v.ldata := pr.ad; v.pwrite := not r.read; v.start := '1';
end if;
end if;
-- if (v.t_state = s_data) and (r.read = '1') then v.oe_ad := '0'; end if;
-- v.oe_par := r.oe_ad;
if r.csel = '1' then tad := cdata;
elsif r.addr(MADDR_WIDTH-1) = '1' then
tad(31 downto MADDR_WIDTH-1) := r.page;
tad(MADDR_WIDTH-2 downto 0) := (others => '0');
else tad := r2.tdata; end if;
if (v.t_state = s_data) or (r.t_state = s_data) then
v.oe_ctrl := '0';
else v.oe_ctrl := '1'; end if;
----- *** PCI TARGET END*** --------
----- *** PCI MASTER *** --------
if MASTER = 1 then
if r.preq(0) = '1' then
if (r.m_state = idle or r.m_state = dr_bus) and r.request = '0' and r.hreq = '0' then
v.request := '1';
v.hwrite := r2.hwrite;
v.lcbe := r2.be;
v.mdata := r2.mdata;
v.maddr :=r2.maddr;
end if;
end if;
if r.hreq_ack(0) = '1' then v.hreq := '0'; v.pabort := '0'; end if;
if r.preq(0) = '0' then v.preq_ack := '0'; end if;
comp := not(pcii.trdy or pcii.irdy);
if ((pr.irdy and not pr.frame) or (pr.devsel and r.frame and not r.oe_frame)) = '1' then -- Covers both master timeout and devsel timeout
if r.mcnt /= "000" then v.mcnt := r.mcnt - 1;
else mto := '1'; end if;
else v.mcnt := (others => '1'); end if;
-- PCI master state machine
case r.m_state is
when idle => -- Master idle
if (pr.gnt = '0' and (pr.frame and pr.irdy) = '1') then
if r.request = '1' then v.m_state := addr; v.preq_ack := '1';
else v.m_state := dr_bus; end if;
end if;
when addr => -- Always one address cycle at the beginning of an transaction
v.m_state := m_data;
when m_data => -- Master transfers data
--if (r.request and not pr.gnt and pr.frame and not pr.trdy -- Not supporting address stepping!
--and pr.stop and l_cycle and sa) = '1' then
--v.m_state <= addr;
v.hreq := comp;
if (pr.frame = '0') or ((pr.frame and pcii.trdy and pcii.stop and not mto) = '1') then
v.m_state := m_data;
elsif ((pr.frame and (mto or not pcii.stop)) = '1') then
v.m_state := s_tar;
else v.m_state := turn_ar; v.request := '0'; end if;
when turn_ar => -- Transaction complete
if (r.request and not pr.gnt) = '1' then v.m_state := addr;
elsif (r.request or pr.gnt) = '0' then v.m_state := dr_bus;
else v.m_state := idle; end if;
when s_tar => -- Stop was asserted
v.request := pr.trdy and not pr.stop and not pr.devsel;
v.stop_req := '1';
if (pr.stop or pr.devsel or pr.trdy) = '0' then -- Disconnect with data
v.m_state := turn_ar;
elsif pr.gnt = '0' then
v.pabort := not v.request;
v.m_state := dr_bus;
else v.m_state := idle; v.pabort := not v.request; end if;
when dr_bus => -- Drive bus when parked on this agent
if (r.request = '1' and (pcii.gnt or r.req) = '0') then v.m_state := addr; v.preq_ack := '1';
elsif pcii.gnt = '1' then v.m_state := idle; end if;
end case;
if v.m_state = addr then mad := r.maddr; else mad := r.mdata; end if;
if (pr.irdy or pr.trdy or r.hwrite) = '0' then v.ldata := pr.ad; end if;
-- Target abort
if ((pr.devsel and pr.trdy and not pr.gnt and not pr.stop) = '1') then v.stat.rta := '1'; end if;
-- Master abort
if mto = '1' then v.stat.rma := '1'; end if;
-- Drive FRAME# and IRDY#
if (v.m_state = addr or v.m_state = m_data) then v.oe_frame := '0'; end if;
-- Drive CBE#
if (v.m_state = addr or v.m_state = m_data or v.m_state = dr_bus) then v.oe_cbe := '0'; end if;
-- Drive IRDY# (FRAME# delayed one pciclk)
v.oe_irdy := r.oe_frame;
-- FRAME# assert
if v.m_state = addr then v.frame := '0'; end if; -- Only single transfers valid
-- IRDY# assert
if v.m_state = m_data then v.irdy := '0'; end if;
-- REQ# assert
if (v.request = '1' and (v.m_state = idle or r.m_state = idle) and (v.stop_req or r.stop_req) = '0') then v.req := '0'; end if;
-- C/BE# assert
if v.m_state = addr then v.cbe := "011" & r.hwrite; else v.cbe := r.lcbe; end if;
end if;
----- *** PCI MASTER END *** --------
----- *** SHARED BUS SIGNALS *** -------
-- Drive PAR
v.oe_par := r.oe_ad; --Delayed one clock
v.par := xorv(r.ad & r.cbe); -- Default asserted by master
v.ad := mad; -- Default asserted by master
-- Master
if (v.m_state = addr or (v.m_state = m_data and r.hwrite = '1') or v.m_state = dr_bus) then
v.oe_ad := '0';
end if;
-- Drive AD
-- Target
if r.read = '1' then
if v.t_state = s_data then
v.oe_ad := '0';
v.ad := tad;
elsif r.t_state = s_data then
v.par := xorv(r.ad & pcii.cbe);
end if;
end if;
v.oe_stop := v.oe_ctrl; v.oe_devsel := v.oe_ctrl; v.oe_trdy := v.oe_ctrl;
v.noe_ad := not v.oe_ad; v.noe_ctrl := not v.oe_ctrl;
v.noe_par := not v.oe_par; v.noe_req := not v.oe_req;
v.noe_frame := not v.oe_frame; v.noe_cbe := not v.oe_cbe;
v.noe_irdy := not v.oe_irdy;
v.noe_stop := not v.oe_ctrl; v.noe_devsel := not v.oe_ctrl;
v.noe_trdy := not v.oe_ctrl;
if oepol = 0 then
voe_ad := (others => v.oe_ad);
oe_ad := r.oe_ad; oe_ctrl := r.oe_ctrl; oe_par := r.oe_par;
oe_req := r.oe_req; oe_frame := r.oe_frame; oe_cbe := r.oe_cbe;
oe_irdy := r.oe_irdy; oe_stop := r.oe_stop; oe_trdy := r.oe_trdy;
oe_devsel := r.oe_devsel;
else
voe_ad := (others => v.noe_ad);
oe_ad := r.noe_ad; oe_ctrl := r.noe_ctrl; oe_par := r.noe_par;
oe_req := r.noe_req; oe_frame := r.noe_frame; oe_cbe := r.noe_cbe;
oe_irdy := r.noe_irdy; oe_stop := r.noe_stop; oe_trdy := r.noe_trdy;
oe_devsel := r.noe_devsel;
end if;
----- *** SHARED BUS SIGNALS END *** -------
if pr.rst = '0' then
v.t_state := idle; v.m_state := idle; v.comm.men := '0'; v.start := '0';
v.bar0 := (others => '0'); v.msel := '0'; v.csel := '0';
v.page := (others => '0'); v.page(31 downto 30) := "01"; v.par := '0';
v.hwrite := '0'; v.request := '0'; v.comm.msen := '0';
v.laddr := (others => '0'); v.ldata := (others => '0');
v.hreq := '0'; v.preq_ack := '0'; v.pabort := '0';
v.mcnt := (others => '1'); v.maddr := (others => '0');
v.lcbe := (others => '0'); v.mdata := (others => '0');
v.pwrite := '0'; v.stop_req := '0';
v.stat.rta := '0'; v.stat.rma := '0';
end if;
rin <= v;
rioe_ad <= voe_ad;
pcio.reqen <= oe_req;
pcio.req <= r.req;
pcio.frameen <= oe_frame;
pcio.frame <= r.frame;
pcio.irdyen <= oe_irdy;
pcio.irdy <= r.irdy;
pcio.cbeen <= (others => oe_cbe);
pcio.cbe <= r.cbe;
pcio.vaden <= roe_ad;
pcio.aden <= oe_ad;
pcio.ad <= r.ad;
pcio.trdy <= r.trdy;
pcio.ctrlen <= oe_ctrl;
pcio.trdyen <= oe_trdy;
pcio.devselen <= oe_devsel;
pcio.stopen <= oe_stop;
pcio.stop <= r.stop;
pcio.devsel <= r.devsel;
pcio.par <= r.par;
pcio.paren <= oe_par;
pcio.rst <= '1';
end process;
pcir : process (pciclk, pcii.rst)
begin
if rising_edge (pciclk) then
pr.ad <= to_x01(pcii.ad);
pr.cbe <= to_x01(pcii.cbe);
pr.devsel <= to_x01(pcii.devsel);
pr.frame <= to_x01(pcii.frame);
pr.idsel <= to_x01(pcii.idsel);
pr.irdy <= to_x01(pcii.irdy);
pr.trdy <= to_x01(pcii.trdy);
pr.par <= to_x01(pcii.par);
pr.stop <= to_x01(pcii.stop);
pr.rst <= to_x01(pcii.rst);
pr.gnt <= to_x01(pcii.gnt);
r <= rin;
roe_ad <= rioe_ad;
end if;
if pcii.rst = '0' then -- asynch reset required
r.oe_ad <= '1'; r.oe_ctrl <= '1'; r.oe_par <= '1'; r.oe_stop <= '1';
r.oe_req <= '1'; r.oe_frame <= '1'; r.oe_cbe <= '1'; r.oe_irdy <= '1';
r.oe_trdy <= '1'; r.oe_devsel <= '1';
r.noe_ad <= '0'; r.noe_ctrl <= '0'; r.noe_par <= '0'; r.noe_req <= '0';
r.noe_frame <= '0'; r.noe_cbe <= '0'; r.noe_irdy <= '0'; r.noe_stop <= '0';
r.noe_trdy <= '0'; r.noe_devsel <= '0';
if oepol = 0 then roe_ad <= (others => '1');
else roe_ad <= (others => '0'); end if;
end if;
end process;
cpur : process (rst,clk)
begin
if rising_edge (clk) then
hr.haddr <= ahbsi.haddr(HADDR_WIDTH - 1 downto 0);
hr.htrans <= ahbsi.htrans;
hr.hwrite <= ahbsi.hwrite;
hr.hsize <= ahbsi.hsize(1 downto 0);
hr.hburst <= ahbsi.hburst;
hr.hwdata <= ahbreadword(ahbsi.hwdata);
hr.hsel <= ahbsi.hsel(hslvndx) and ahbsi.hmbsel(0);
hr.hiosel <= ahbsi.hsel(hslvndx) and ahbsi.hmbsel(1);
hr.hready <= ahbsi.hready;
r2 <= r2in;
end if;
end process;
oe0 : if oepol = 0 generate
pcio.perren <= '1';
pcio.serren <= '1';
pcio.inten <= '1';
pcio.vinten <= (others => '1');
pcio.locken <= '1';
end generate;
oe1 : if oepol = 1 generate
pcio.perren <= '0';
pcio.serren <= '0';
pcio.inten <= '0';
pcio.vinten <= (others => '0');
pcio.locken <= '0';
end generate;
pcio.perr <= '1';
pcio.serr <= '1';
pcio.int <= '1';
msttgt : if MASTER = 1 generate
ahbmst0 : ahbmst generic map (hindex => hmstndx, devid => GAISLER_PCISBRG)
port map (rst, clk, dmai, dmao, ahbmi, ahbmo);
-- pragma translate_off
bootmsg : report_version
generic map ("pci_mt" & tost(hslvndx) &
": Simple 32-bit PCI Bridge, rev " & tost(REVISION) &
", " & tost(2**abits/2**20) & " Mbyte PCI memory BAR" );
-- pragma translate_on
end generate;
tgtonly : if MASTER = 0 generate
ahbmst0 : ahbmst generic map (hindex => hmstndx, devid => GAISLER_PCITRG)
port map (rst, clk, dmai, dmao, ahbmi, ahbmo);
-- pragma translate_off
bootmsg : report_version
generic map ("pci_mt" & tost(hmstndx) &
": Simple 32-bit Bridge, target-only, rev " & tost(REVISION) &
", " & tost(2**abits/2**20) & " Mbyte PCI memory BAR" );
-- pragma translate_on
end generate;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/tech/stratixiii/simprims/stratixiii_atoms.vhd | 2 | 954499 | -- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 9.0 Build 235 03/01/2009
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package stratixiii_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE stratixiii_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function int2bit (arg : boolean) return std_logic;
function int2bit (arg : integer) return std_logic;
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function calc_sum_len( widtha : integer; widthb : integer) return integer;
end stratixiii_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body stratixiii_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function calc_sum_len( widtha : integer; widthb : integer) return integer is
variable result: integer;
begin
if(widtha >= widthb) then
result := widtha + 1;
else
result := widthb + 1;
end if;
return result;
end calc_sum_len;
end stratixiii_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package stratixiii_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end stratixiii_pllpack;
package body stratixiii_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1300;
constant MIN_VCO : integer := 300;
constant MAX_OFFSET : real := 0.004;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable closest_vco_step_value : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
variable clk0_div_factor_real : real;
variable clk1_div_factor_real : real;
variable clk2_div_factor_real : real;
variable clk3_div_factor_real : real;
variable clk4_div_factor_real : real;
variable clk5_div_factor_real : real;
variable clk6_div_factor_real : real;
variable clk7_div_factor_real : real;
variable clk8_div_factor_real : real;
variable clk9_div_factor_real : real;
variable clk0_div_factor_int : integer;
variable clk1_div_factor_int : integer;
variable clk2_div_factor_int : integer;
variable clk3_div_factor_int : integer;
variable clk4_div_factor_int : integer;
variable clk5_div_factor_int : integer;
variable clk6_div_factor_int : integer;
variable clk7_div_factor_int : integer;
variable clk8_div_factor_int : integer;
variable clk9_div_factor_int : integer;
begin
vco_period := vco_phase_shift_step * 8;
i_pre_m := 0;
i_pre_n := 0;
closest_vco_step_value := 0;
LOOP_1 : for i_n_out in 1 to MAX_N loop
for i_m_out in 1 to MAX_M loop
clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out);
clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out);
clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out);
clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out);
clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out);
clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out);
clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out);
clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out);
clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out);
clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out);
clk0_div_factor_int := integer(clk0_div_factor_real);
clk1_div_factor_int := integer(clk1_div_factor_real);
clk2_div_factor_int := integer(clk2_div_factor_real);
clk3_div_factor_int := integer(clk3_div_factor_real);
clk4_div_factor_int := integer(clk4_div_factor_real);
clk5_div_factor_int := integer(clk5_div_factor_real);
clk6_div_factor_int := integer(clk6_div_factor_real);
clk7_div_factor_int := integer(clk7_div_factor_real);
clk8_div_factor_int := integer(clk8_div_factor_real);
clk9_div_factor_int := integer(clk9_div_factor_real);
if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and
((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and
((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and
((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and
((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and
((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and
((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and
((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and
((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and
((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) )
then
if ((i_m_out /= 0) and (i_n_out /= 0))
then
pfd_freq := 1000000 / (inclock_period * i_n_out);
vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out);
vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out);
if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) )
then
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
exit LOOP_1;
else
if (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step))
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
closest_vco_step_value := vco_ps_step_value;
end if;
end if;
end if;
end if;
end if;
end loop;
end loop;
if ((i_pre_m /= 0) and (i_pre_n /= 0))
then
find_simple_integer_fraction(i_pre_m, i_pre_n,
MAX_N, m, n);
else
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end if;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif (M9 = 3) then
R := 9;
elsif ((M9 <= 10) and (M9 > 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable r_real : real := 1.0;
variable r: integer := 1;
begin
r_real := real(clk_divide * M)/ real(clk_mult * N);
r := integer(r_real);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
if (R = 0) then
R := 1;
end if;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end stratixiii_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of stratixiii_dffe : entity is TRUE;
end stratixiii_dffe;
-- architecture body --
architecture behave of stratixiii_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- stratixiii_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of stratixiii_mux21 : entity is TRUE;
end stratixiii_mux21;
architecture AltVITAL of stratixiii_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- stratixiii_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of stratixiii_mux41 : entity is TRUE;
end stratixiii_mux41;
architecture AltVITAL of stratixiii_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- stratixiii_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixiii_atom_pack.all;
-- entity declaration --
entity stratixiii_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of stratixiii_and1 : entity is TRUE;
end stratixiii_and1;
-- architecture body --
architecture AltVITAL of stratixiii_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
-------------------------------------------------------------------
--
-- Entity Name : stratixiii_jtag
--
-- Description : Stratix JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_jtag is
generic (
lpm_type : string := "stratixiii_jtag"
);
port (
tms : in std_logic;
tck : in std_logic;
tdi : in std_logic;
ntrst : in std_logic;
tdoutap : in std_logic;
tdouser : in std_logic;
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end stratixiii_jtag;
architecture architecture_jtag of stratixiii_jtag is
begin
end architecture_jtag;
-------------------------------------------------------------------
--
-- Entity Name : stratixiii_crcblock
--
-- Description : Stratix CRCBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_crcblock is
generic (
oscillator_divider : integer := 1;
crc_deld_disable : string := "off";
error_delay : integer := 0 ;
error_dra_dl_bypass : string := "off";
lpm_type : string := "stratixiii_crcblock"
);
port (
clk : in std_logic;
shiftnld : in std_logic;
crcerror : out std_logic;
regout : out std_logic
);
end stratixiii_crcblock;
architecture architecture_crcblock of stratixiii_crcblock is
begin
end architecture_crcblock;
---------------------------------------------------------------------
--
-- Entity Name : stratixiii_lcell_comb
--
-- Description : Stratix III LCELL_COMB VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_lcell_comb is
generic (
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
shared_arith : string := "off";
extended_lut : string := "off";
dont_touch : string := "off";
lpm_type : string := "stratixiii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_datae : VitalDelayType01 := DefPropDelay01;
tipd_dataf : VitalDelayType01 := DefPropDelay01;
tipd_datag : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_sharein : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
datae : in std_logic := '0';
dataf : in std_logic := '0';
datag : in std_logic := '0';
cin : in std_logic := '0';
sharein : in std_logic := '0';
combout : out std_logic;
sumout : out std_logic;
cout : out std_logic;
shareout : out std_logic
);
attribute VITAL_LEVEL0 of stratixiii_lcell_comb : entity is TRUE;
end stratixiii_lcell_comb;
architecture vital_lcell_comb of stratixiii_lcell_comb is
attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE;
signal dataa_ipd : std_logic;
signal datab_ipd : std_logic;
signal datac_ipd : std_logic;
signal datad_ipd : std_logic;
signal datae_ipd : std_logic;
signal dataf_ipd : std_logic;
signal datag_ipd : std_logic;
signal cin_ipd : std_logic;
signal sharein_ipd : std_logic;
signal f2_input3 : std_logic;
-- sub masks
signal f0_mask : std_logic_vector(15 downto 0);
signal f1_mask : std_logic_vector(15 downto 0);
signal f2_mask : std_logic_vector(15 downto 0);
signal f3_mask : std_logic_vector(15 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (datae_ipd, datae, tipd_datae);
VitalWireDelay (dataf_ipd, dataf, tipd_dataf);
VitalWireDelay (datag_ipd, datag, tipd_datag);
VitalWireDelay (cin_ipd, cin, tipd_cin);
VitalWireDelay (sharein_ipd, sharein, tipd_sharein);
end block;
f0_mask <= lut_mask(15 downto 0);
f1_mask <= lut_mask(31 downto 16);
f2_mask <= lut_mask(47 downto 32);
f3_mask <= lut_mask(63 downto 48);
f2_input3 <= datag_ipd WHEN (extended_lut = "on") ELSE datac_ipd;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
datae_ipd, dataf_ipd, f2_input3, cin_ipd,
sharein_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable sumout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
variable shareout_VitalGlitchData : VitalGlitchDataType;
-- sub lut outputs
variable f0_out : std_logic;
variable f1_out : std_logic;
variable f2_out : std_logic;
variable f3_out : std_logic;
-- muxed output
variable g0_out : std_logic;
variable g1_out : std_logic;
-- internal variables
variable f2_f : std_logic;
variable adder_input2 : std_logic;
-- output variables
variable combout_tmp : std_logic;
variable sumout_tmp : std_logic;
variable cout_tmp : std_logic;
-- temp variable for NCVHDL
variable lut_mask_var : std_logic_vector(63 downto 0) := (OTHERS => '1');
begin
lut_mask_var := lut_mask;
------------------------
-- Timing Check Section
------------------------
f0_out := VitalMUX(data => f0_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
f1_out := VitalMUX(data => f1_mask,
dselect => (datad_ipd,
f2_input3,
datab_ipd,
dataa_ipd));
f2_out := VitalMUX(data => f2_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
f3_out := VitalMUX(data => f3_mask,
dselect => (datad_ipd,
f2_input3,
datab_ipd,
dataa_ipd));
-- combout
if (extended_lut = "on") then
if (datae_ipd = '0') then
g0_out := f0_out;
g1_out := f2_out;
elsif (datae_ipd = '1') then
g0_out := f1_out;
g1_out := f3_out;
else
g0_out := 'X';
g1_out := 'X';
end if;
if (dataf_ipd = '0') then
combout_tmp := g0_out;
elsif ((dataf_ipd = '1') or (g0_out = g1_out))then
combout_tmp := g1_out;
else
combout_tmp := 'X';
end if;
else
combout_tmp := VitalMUX(data => lut_mask_var,
dselect => (dataf_ipd,
datae_ipd,
datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
end if;
-- sumout and cout
f2_f := VitalMUX(data => f2_mask,
dselect => (dataf_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
if (shared_arith = "on") then
adder_input2 := sharein_ipd;
else
adder_input2 := NOT f2_f;
end if;
sumout_tmp := cin_ipd XOR f0_out XOR adder_input2;
cout_tmp := (cin_ipd AND f0_out) OR (cin_ipd AND adder_input2) OR
(f0_out AND adder_input2);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => combout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (datae_ipd'last_event, tpd_datae_combout, TRUE),
5 => (dataf_ipd'last_event, tpd_dataf_combout, TRUE),
6 => (datag_ipd'last_event, tpd_datag_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => sumout,
OutSignalName => "SUMOUT",
OutTemp => sumout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_sumout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_sumout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_sumout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_sumout, TRUE),
4 => (dataf_ipd'last_event, tpd_dataf_sumout, TRUE),
5 => (cin_ipd'last_event, tpd_cin_sumout, TRUE),
6 => (sharein_ipd'last_event, tpd_sharein_sumout, TRUE)),
GlitchData => sumout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => cout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cout, TRUE),
4 => (dataf_ipd'last_event, tpd_dataf_cout, TRUE),
5 => (cin_ipd'last_event, tpd_cin_cout, TRUE),
6 => (sharein_ipd'last_event, tpd_sharein_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => shareout,
OutSignalName => "SHAREOUT",
OutTemp => f2_out,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_shareout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_shareout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_shareout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_shareout, TRUE)),
GlitchData => shareout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_comb;
---------------------------------------------------------------------
--
-- Entity Name : stratixiii_routing_wire
--
-- Description : Stratix III Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of stratixiii_routing_wire : entity is TRUE;
end stratixiii_routing_wire;
ARCHITECTURE behave of stratixiii_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiii_lvds_tx_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for registering the enable inputs.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
ENTITY stratixiii_lvds_tx_reg is
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic;
d : IN std_logic;
clrn : IN std_logic;
prn : IN std_logic
);
attribute VITAL_LEVEL0 of stratixiii_lvds_tx_reg : ENTITY is TRUE;
END stratixiii_lvds_tx_reg;
ARCHITECTURE vital_titan_lvds_tx_reg of stratixiii_lvds_tx_reg is
attribute VITAL_LEVEL0 of vital_titan_lvds_tx_reg : architecture is TRUE;
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal ena_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (d_ipd, d, tipd_d);
end block;
process (clk_ipd, clrn, prn)
variable q_tmp : std_logic := '0';
variable q_VitalGlitchData : VitalGlitchDataType;
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d_ipd,
TestSignalName => "d",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT ena_ipd) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiii_lvds_tx_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_tmp := '1';
elsif (clrn = '0') then
q_tmp := '0';
elsif (clk_ipd'event and clk_ipd = '1') then
if (ena_ipd = '1') then
q_tmp := d_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_titan_lvds_tx_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : stratixiii_lvds_tx_parallel_register
--
-- Description : Register for the 10 data input channels of the Stratix III
-- LVDS Tx
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
USE std.textio.all;
ENTITY stratixiii_lvds_tx_parallel_register is
GENERIC ( channel_width : integer := 10;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT ( clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
END stratixiii_lvds_tx_parallel_register;
ARCHITECTURE vital_tx_reg of stratixiii_lvds_tx_parallel_register is
signal clk_ipd : std_logic;
signal enable_ipd : std_logic;
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (enable_ipd, enable, tipd_enable);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
VITAL: process (clk_ipd, enable_ipd, datain_ipd, devpor, devclrn)
variable Tviol_datain_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable i : integer := 0;
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if (now = 0 ns) then
dataout_tmp := (OTHERS => '0');
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiii_lvds_tx_parallel_register",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1') then
if (enable_ipd = '1') then
dataout_tmp := datain_ipd;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay(
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
end vital_tx_reg;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : stratixiii_lvds_tx_out_block
--
-- Description : Negative-edge triggered register on the Tx output.
-- Also, optionally generates an identical/inverted output clock
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
USE std.textio.all;
ENTITY stratixiii_lvds_tx_out_block is
GENERIC ( bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk : in std_logic;
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
END stratixiii_lvds_tx_out_block;
ARCHITECTURE vital_tx_out_block of stratixiii_lvds_tx_out_block is
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
signal inv_clk : integer;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process (clk_ipd, datain_ipd, devpor, devclrn)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable dataout_tmp : std_logic;
begin
if (now = 0 ns) then
dataout_tmp := '0';
else
if (bypass_serializer = "false") then
if (use_falling_clock_edge = "false") then
dataout_tmp := datain_ipd;
end if;
if (clk_ipd'event and clk_ipd = '0') then
if (use_falling_clock_edge = "true") then
dataout_tmp := datain_ipd;
end if;
end if;
else
if (invert_clock = "false") then
dataout_tmp := clk_ipd;
else
dataout_tmp := NOT (clk_ipd);
end if;
if (invert_clock = "false") then
inv_clk <= 0;
else
inv_clk <= 1;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
if (bypass_serializer = "false") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout, TRUE),
1 => (clk_ipd'last_event, tpd_clk_dataout_negedge, use_falling_clock_edge = "true")),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
if (bypass_serializer = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
end process;
end vital_tx_out_block;
--////////////////////////////////////////////////////////////////////////////
--
-- Entity name : stratixiii_lvds_transmitter
--
-- Description : Timing simulation model for the Stratix III LVDS Tx WYSIWYG.
-- It instantiates the following sub-modules :
-- 1) primitive DFFE
-- 2) Stratix III_lvds_tx_parallel_register and
-- 3) Stratix III_lvds_tx_out_block
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
USE std.textio.all;
USE work.stratixiii_lvds_tx_parallel_register;
USE work.stratixiii_lvds_tx_out_block;
USE work.stratixiii_lvds_tx_reg;
ENTITY stratixiii_lvds_transmitter is
GENERIC ( channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
use_serial_data_input : String := "false";
use_post_dpa_serial_data_input : String := "false";
is_used_as_outclk : String := "false";
tx_output_path_delay_engineering_bits : Integer := -1;
enable_dpaclk_to_lvdsout : string := "off";
preemphasis_setting : integer := 0;
vod_setting : integer := 0;
differential_drive : integer := 0;
lpm_type : string := "stratixiii_lvds_transmitter";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_dpaclkin_dataout : VitalDelayType01 := DefPropDelay01;
tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_dpaclkin : VitalDelayType01 := DefpropDelay01;
tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk0 : in std_logic;
enable0 : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
dpaclkin : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic;
serialfdbkout : out std_logic
);
end stratixiii_lvds_transmitter;
ARCHITECTURE vital_transmitter_atom of stratixiii_lvds_transmitter is
signal clk0_ipd : std_logic;
signal serialdatain_ipd : std_logic;
signal postdpaserialdatain_ipd : std_logic;
signal dpaclkin_ipd : std_logic;
signal input_data : std_logic_vector(channel_width - 1 downto 0);
signal txload0 : std_logic;
signal shift_out : std_logic;
signal clk0_dly0 : std_logic;
signal clk0_dly1 : std_logic;
signal clk0_dly2 : std_logic;
signal datain_dly : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly1 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly2 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly3 : std_logic_vector(channel_width - 1 downto 0);
signal datain_dly4 : std_logic_vector(channel_width - 1 downto 0);
signal vcc : std_logic := '1';
signal tmp_dataout : std_logic;
COMPONENT stratixiii_lvds_tx_parallel_register
GENERIC ( channel_width : integer := 10;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01)
);
PORT ( clk : in std_logic;
enable : in std_logic;
datain : in std_logic_vector(channel_width - 1 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector(channel_width - 1 downto 0)
);
END COMPONENT;
COMPONENT stratixiii_lvds_tx_out_block
GENERIC ( bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk : in std_logic;
datain : in std_logic;
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic
);
END COMPONENT;
COMPONENT stratixiii_lvds_tx_reg
GENERIC (TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01
);
PORT ( q : out STD_LOGIC := '0';
d : in STD_LOGIC := '1';
clrn : in STD_LOGIC := '1';
prn : in STD_LOGIC := '1';
clk : in STD_LOGIC := '0';
ena : in STD_LOGIC := '1'
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (serialdatain_ipd, serialdatain, tipd_serialdatain);
VitalWireDelay (dpaclkin_ipd, dpaclkin, tipd_dpaclkin);
VitalWireDelay (postdpaserialdatain_ipd, postdpaserialdatain, tipd_postdpaserialdatain);
end block;
txload0_reg: stratixiii_lvds_tx_reg
PORT MAP (d => enable0,
clrn => vcc,
prn => vcc,
ena => vcc,
clk => clk0_dly2,
q => txload0
);
input_reg: stratixiii_lvds_tx_parallel_register
GENERIC MAP ( channel_width => channel_width)
PORT MAP ( clk => txload0,
enable => vcc,
datain => datain_dly,
dataout => input_data,
devclrn => devclrn,
devpor => devpor
);
output_module: stratixiii_lvds_tx_out_block
GENERIC MAP ( bypass_serializer => bypass_serializer,
use_falling_clock_edge => use_falling_clock_edge,
invert_clock => invert_clock)
PORT MAP ( clk => clk0_dly2,
datain => shift_out,
dataout => tmp_dataout,
devclrn => devclrn,
devpor => devpor
);
clk_delay: process (clk0_ipd, datain)
begin
clk0_dly0 <= clk0_ipd;
datain_dly1 <= datain;
end process;
clk_delay1: process (clk0_dly0, datain_dly1)
begin
clk0_dly1 <= clk0_dly0;
datain_dly2 <= datain_dly1;
end process;
clk_delay2: process (clk0_dly1, datain_dly2)
begin
clk0_dly2 <= clk0_dly1;
datain_dly3 <= datain_dly2;
end process;
data_delay: process (datain_dly3)
begin
datain_dly4 <= datain_dly3;
end process;
data_delay1: process (datain_dly4)
begin
datain_dly <= datain_dly4;
end process;
VITAL: process (clk0_ipd, devclrn, devpor)
variable dataout_VitalGlitchData : VitalGlitchDataType;
variable i : integer := 0;
variable shift_data : std_logic_vector(channel_width-1 downto 0);
begin
if (now = 0 ns) then
shift_data := (OTHERS => '0');
end if;
if ((devpor = '0') or (devclrn = '0')) then
shift_data := (OTHERS => '0');
else
if (bypass_serializer = "false") then
if (clk0_ipd'event and clk0_ipd = '1') then
if (txload0 = '1') then
shift_data := input_data;
end if;
shift_out <= shift_data(channel_width - 1);
for i in channel_width-1 downto 1 loop
shift_data(i) := shift_data(i - 1);
end loop;
end if;
end if;
end if;
end process;
process (serialdatain_ipd,
postdpaserialdatain_ipd,
dpaclkin_ipd,
tmp_dataout
)
variable dataout_tmp : std_logic := '0';
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
if (serialdatain_ipd'event and use_serial_data_input = "true") then
dataout_tmp := serialdatain_ipd;
elsif (postdpaserialdatain_ipd'event and use_post_dpa_serial_data_input = "true") then
dataout_tmp := postdpaserialdatain_ipd;
elsif (dpaclkin_ipd'event and enable_dpaclk_to_lvdsout = "on") then
dataout_tmp := dpaclkin_ipd;
else
dataout_tmp := tmp_dataout;
end if;
----------------------
-- Path Delay Section
----------------------
if (use_serial_data_input = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (serialdatain_ipd'last_event, tpd_serialdatain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
elsif (use_post_dpa_serial_data_input = "true") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (postdpaserialdatain_ipd'last_event, tpd_postdpaserialdatain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
elsif (enable_dpaclk_to_lvdsout = "on") then
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (dpaclkin_ipd'last_event, tpd_dpaclkin_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
else
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (0 => (tmp_dataout'last_event, DefPropDelay01, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end if;
end process;
end vital_transmitter_atom;
--
--
-- STRATIXIII_RUBLOCK Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_rublock is
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "stratixiii_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
end stratixiii_rublock;
architecture architecture_rublock of stratixiii_rublock is
begin
end architecture_rublock;
----------------------------------------------------------------------------
-- Module Name : stratixiii_ram_register
-- Description : Register module for RAM inputs/outputs
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
ENTITY stratixiii_ram_register IS
GENERIC (
width : INTEGER := 1;
preset : STD_LOGIC := '0';
tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_stall : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END stratixiii_ram_register;
ARCHITECTURE reg_arch OF stratixiii_ram_register IS
SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
SIGNAL clk_ipd : STD_LOGIC;
SIGNAL ena_ipd : STD_LOGIC;
SIGNAL aclr_ipd : STD_LOGIC;
SIGNAL stall_ipd : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
loopbits : FOR i in d'RANGE GENERATE
VitalWireDelay (d_ipd(i), d(i), tipd_d(i));
END GENERATE;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (stall_ipd, stall, tipd_stall);
END BLOCK;
-- REMTITAN PROCESS (d_ipd,ena_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
PROCESS (d_ipd,ena_ipd,stall_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
VARIABLE Tviol_clk_ena : STD_ULOGIC := '0';
VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0';
VARIABLE Tviol_data_clk : STD_ULOGIC := '0';
VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_stall : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_ena : STD_ULOGIC := '0';
VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
VARIABLE CQDelay : TIME := 0 ns;
VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset);
BEGIN
IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN
q_reg := (OTHERS => preset);
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1' AND stall_ipd = '0') THEN
q_reg := d_ipd;
END IF;
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_stall,
TestSignal => stall_ipd,
TestSignalName => "stall",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_stall_clk_noedge_posedge,
SetupLow => tsetup_stall_clk_noedge_posedge,
HoldHigh => thold_stall_clk_noedge_posedge,
HoldLow => thold_stall_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_aclr,
TimingData => TimingData_clk_aclr,
TestSignal => aclr_ipd,
TestSignalName => "aclr",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_aclr_clk_noedge_posedge,
SetupLow => tsetup_aclr_clk_noedge_posedge,
HoldHigh => thold_aclr_clk_noedge_posedge,
HoldLow => thold_aclr_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => d_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_ena,
PeriodData => PeriodData_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
PulseWidthHigh => tpw_ena_posedge,
HeaderMsg => "/RAM Register VitalPeriodPulseCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
-- Path Delay Selection
CQDelay := SelectDelay (
Paths => (
(0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE),
1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE))
)
);
q <= TRANSPORT q_reg AFTER CQDelay;
END PROCESS;
aclrout <= aclr_ipd;
END reg_arch;
----------------------------------------------------------------------------
-- Module Name : stratixiii_ram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
ENTITY stratixiii_ram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF stratixiii_ram_pulse_generator:ENTITY IS TRUE;
END stratixiii_ram_pulse_generator;
ARCHITECTURE pgen_arch OF stratixiii_ram_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
IF (delaywrite = '1') THEN
state <= '1' AFTER 1 NS; -- delayed write
ELSE
state <= '1';
END IF;
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
USE work.stratixiii_ram_register;
USE work.stratixiii_ram_pulse_generator;
ENTITY stratixiii_ram_block IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
enable_ecc : STRING := "false";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
lpm_type : string := "stratixiii_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
clock_duty_cycle_dependence : STRING := "Auto";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
mem_init5 : BIT_VECTOR := X"0";
mem_init6 : BIT_VECTOR := X"0";
mem_init7 : BIT_VECTOR := X"0";
mem_init8 : BIT_VECTOR := X"0";
mem_init9 : BIT_VECTOR := X"0";
mem_init10 : BIT_VECTOR := X"0";
mem_init11 : BIT_VECTOR := X"0";
mem_init12 : BIT_VECTOR := X"0";
mem_init13 : BIT_VECTOR := X"0";
mem_init14 : BIT_VECTOR := X"0";
mem_init15 : BIT_VECTOR := X"0";
mem_init16 : BIT_VECTOR := X"0";
mem_init17 : BIT_VECTOR := X"0";
mem_init18 : BIT_VECTOR := X"0";
mem_init19 : BIT_VECTOR := X"0";
mem_init20 : BIT_VECTOR := X"0";
mem_init21 : BIT_VECTOR := X"0";
mem_init22 : BIT_VECTOR := X"0";
mem_init23 : BIT_VECTOR := X"0";
mem_init24 : BIT_VECTOR := X"0";
mem_init25 : BIT_VECTOR := X"0";
mem_init26 : BIT_VECTOR := X"0";
mem_init27 : BIT_VECTOR := X"0";
mem_init28 : BIT_VECTOR := X"0";
mem_init29 : BIT_VECTOR := X"0";
mem_init30 : BIT_VECTOR := X"0";
mem_init31 : BIT_VECTOR := X"0";
mem_init32 : BIT_VECTOR := X"0";
mem_init33 : BIT_VECTOR := X"0";
mem_init34 : BIT_VECTOR := X"0";
mem_init35 : BIT_VECTOR := X"0";
mem_init36 : BIT_VECTOR := X"0";
mem_init37 : BIT_VECTOR := X"0";
mem_init38 : BIT_VECTOR := X"0";
mem_init39 : BIT_VECTOR := X"0";
mem_init40 : BIT_VECTOR := X"0";
mem_init41 : BIT_VECTOR := X"0";
mem_init42 : BIT_VECTOR := X"0";
mem_init43 : BIT_VECTOR := X"0";
mem_init44 : BIT_VECTOR := X"0";
mem_init45 : BIT_VECTOR := X"0";
mem_init46 : BIT_VECTOR := X"0";
mem_init47 : BIT_VECTOR := X"0";
mem_init48 : BIT_VECTOR := X"0";
mem_init49 : BIT_VECTOR := X"0";
mem_init50 : BIT_VECTOR := X"0";
mem_init51 : BIT_VECTOR := X"0";
mem_init52 : BIT_VECTOR := X"0";
mem_init53 : BIT_VECTOR := X"0";
mem_init54 : BIT_VECTOR := X"0";
mem_init55 : BIT_VECTOR := X"0";
mem_init56 : BIT_VECTOR := X"0";
mem_init57 : BIT_VECTOR := X"0";
mem_init58 : BIT_VECTOR := X"0";
mem_init59 : BIT_VECTOR := X"0";
mem_init60 : BIT_VECTOR := X"0";
mem_init61 : BIT_VECTOR := X"0";
mem_init62 : BIT_VECTOR := X"0";
mem_init63 : BIT_VECTOR := X"0";
mem_init64 : BIT_VECTOR := X"0";
mem_init65 : BIT_VECTOR := X"0";
mem_init66 : BIT_VECTOR := X"0";
mem_init67 : BIT_VECTOR := X"0";
mem_init68 : BIT_VECTOR := X"0";
mem_init69 : BIT_VECTOR := X"0";
mem_init70 : BIT_VECTOR := X"0";
mem_init71 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
eccstatus : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
dftout : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := "000000000";
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END stratixiii_ram_block;
ARCHITECTURE block_arch OF stratixiii_ram_block IS
COMPONENT stratixiii_ram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT stratixiii_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS
VARIABLE c: INTEGER;
BEGIN
IF (condition) THEN c := a; ELSE c := b; END IF;
RETURN c;
END;
SUBTYPE port_type IS BOOLEAN;
CONSTANT primary : port_type := TRUE;
CONSTANT secondary : port_type := FALSE;
CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width);
CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a;
CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom");
CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port");
CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port");
CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port");
CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1)
AND (port_a_data_width /= port_b_data_width);
CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1,
cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width))));
CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width);
CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width);
CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width);
CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width);
CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width;
CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width;
CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED");
CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED");
CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT ram_type : BOOLEAN := FALSE;
TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC;
CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0');
-- Hardware write modes
CONSTANT dual_clock : BOOLEAN := (operation_mode = "dual_port" OR
operation_mode = "bidir_dual_port") AND
(port_b_address_clock = "clock1");
CONSTANT both_new_data_same_port : BOOLEAN := (
((port_a_read_during_write_mode = "new_data_no_nbe_read") OR
(port_a_read_during_write_mode = "dont_care")) AND
((port_b_read_during_write_mode = "new_data_no_nbe_read") OR
(port_b_read_during_write_mode = "dont_care"))
);
SIGNAL hw_write_mode_a : STRING(3 DOWNTO 1);
SIGNAL hw_write_mode_b : STRING(3 DOWNTO 1);
SIGNAL delay_write_pulse_a : STD_LOGIC ;
SIGNAL delay_write_pulse_b : STD_LOGIC ;
CONSTANT be_mask_write_a : BOOLEAN := (port_a_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT be_mask_write_b : BOOLEAN := (port_b_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT old_data_write_a : BOOLEAN := (port_a_read_during_write_mode = "old_data");
CONSTANT old_data_write_b : BOOLEAN := (port_b_read_during_write_mode = "old_data");
SIGNAL read_before_write_a : BOOLEAN;
SIGNAL read_before_write_b : BOOLEAN;
-- -------- internal signals ---------
-- clock / clock enable
SIGNAL clk_a_in,clk_b_in : STD_LOGIC;
SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC;
SIGNAL clk_a_out,clk_b_out : STD_LOGIC;
SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC;
SIGNAL clkena_out_c0, clkena_out_c1 : STD_LOGIC;
SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC;
SIGNAL clk_a_rena, clk_a_wena : STD_LOGIC;
SIGNAL clk_a_core : STD_LOGIC;
SIGNAL clk_b_rena, clk_b_wena : STD_LOGIC;
SIGNAL clk_b_core : STD_LOGIC;
SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0);
-- asynch clear
TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr_reg, dataout_b_clr_reg : STD_LOGIC;
SIGNAL dataout_a_clr_reg_in, dataout_b_clr_reg_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_out, dataout_b_clr_reg_out : one_bit_bus_type;
SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC;
SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC;
SIGNAL we_a_clr,re_a_clr,we_b_clr,re_b_clr : STD_LOGIC;
SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC;
SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC;
SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC;
SIGNAL we_a_clr_in,re_a_clr_in,we_b_clr_in,re_b_clr_in : STD_LOGIC;
SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type;
SIGNAL clear_asserted_during_write : clear_vec_type;
-- port A registers
SIGNAL we_a_reg : STD_LOGIC;
SIGNAL re_a_reg : STD_LOGIC;
SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type;
SIGNAL re_a_reg_in,re_a_reg_out : one_bit_bus_type;
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0);
-- port B registers
SIGNAL we_b_reg, re_b_reg : STD_LOGIC;
SIGNAL re_b_reg_in,re_b_reg_out,we_b_reg_in,we_b_reg_out : one_bit_bus_type;
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0);
SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0);
-- pulses
TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec;
SIGNAL rw_pulse : pulse_vec;
SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC;
SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC;
SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC;
SIGNAL rwpgen_a_clkena,rwpgen_b_clkena : STD_LOGIC;
-- registered address
SIGNAL addr_prime_reg,addr_sec_reg : INTEGER;
-- input/output
SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0);
-- overlapping location write
SIGNAL dual_write : BOOLEAN;
-- byte enable mask write
TYPE be_mask_write_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
SIGNAL be_mask_write : be_mask_write_vec;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0);
TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type;
TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X')));
CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X'));
CONSTANT col_x : mem_col_type := (OTHERS => 'X');
SIGNAL mem_data : mem_row_type;
SIGNAL old_mem_data : mem_row_type;
SIGNAL mem_unit_data : mem_col_type;
-- latches
TYPE read_latch_rec IS RECORD
prime : mem_row_type;
sec : mem_col_type;
END RECORD;
SIGNAL read_latch : read_latch_rec;
-- (row,column) coordinates
SIGNAL row_sec,col_sec : INTEGER;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type;
TYPE mask_rec IS RECORD
prime : mask_prime_type;
sec : mask_sec_type;
END RECORD;
SIGNAL mask_vector : mask_rec;
SIGNAL mask_vector_common : mem_col_type;
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
mode : port_type;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_rec IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_rec := (
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X')),
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X'))
);
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
END IF;
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END IF;
END LOOP;
RETURN mask;
END get_mask;
-- port active for read/write
SIGNAL active_a_core_in_vec,active_b_core_in_vec,active_a_core_out,active_b_core_out : one_bit_bus_type;
SIGNAL active_a_in,active_b_in : STD_LOGIC;
SIGNAL active_write_a : BOOLEAN;
SIGNAL active_write_b : BOOLEAN;
SIGNAL active_b_in_c0,active_b_core_in_c0,active_b_in_c1,active_b_core_in_c1 : STD_LOGIC;
SIGNAL active_a_core_in,active_b_core_in : STD_LOGIC;
SIGNAL active_a_core, active_b_core : BOOLEAN;
SIGNAL wire_vcc : STD_LOGIC := '1';
SIGNAL wire_gnd : STD_LOGIC := '0';
BEGIN
-- memory initialization
init_mem <= TRUE;
-- hardware write modes
hw_write_mode_a <= "R+W" WHEN ((port_a_read_during_write_mode = "old_data") OR
(port_a_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
hw_write_mode_b <= "R+W" WHEN ((port_b_read_during_write_mode = "old_data") OR
(port_b_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
delay_write_pulse_a <= '0' WHEN (mode_is_dp AND mixed_port_feed_through_mode = "dont_care") ELSE '1' WHEN (hw_write_mode_a /= " FW") ELSE '0';
delay_write_pulse_b <= '1' WHEN (hw_write_mode_b /= " FW") ELSE '0' ;
read_before_write_a <= (hw_write_mode_a = "R+W");
read_before_write_b <= (hw_write_mode_b = "R+W");
-- -------- core logic ---------------
clk_a_in <= clk0;
clk_a_wena <= '0' WHEN (port_a_write_enable_clock = "none") ELSE clk_a_in;
clk_a_rena <= '0' WHEN (port_a_read_enable_clock = "none") ELSE clk_a_in;
clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in;
clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1;
clk_b_in <= clk0 WHEN (port_b_address_clock = "clock0") ELSE clk1;
clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE
clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1;
clk_b_wena <= '0' WHEN (port_b_write_enable_clock = "none") ELSE
clk0 WHEN (port_b_write_enable_clock = "clock0") ELSE
clk1;
clk_b_rena <= '0' WHEN (port_b_read_enable_clock = "none") ELSE
clk0 WHEN (port_b_read_enable_clock = "clock0") ELSE
clk1;
clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1;
addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0;
addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE
clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1;
datain_a_clr_in <= '0';
datain_b_clr_in <= '0';
dataout_a_clr <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1;
dataout_b_clr <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1;
byteena_a_clr_in <= '0';
byteena_b_clr_in <= '0';
we_a_clr_in <= '0';
re_a_clr_in <= '0';
we_b_clr_in <= '0';
re_b_clr_in <= '0';
active_a_in <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_a_core_in <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
be_mask_write(primary_port_is_a) <= be_mask_write_a;
be_mask_write(primary_port_is_b) <= be_mask_write_b;
active_b_in_c0 <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_b_in_c1 <= '1' WHEN (clk1_input_clock_enable = "none") ELSE
ena1 WHEN (clk1_input_clock_enable = "ena1") ELSE
ena3;
active_b_in <= active_b_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_in_c1;
active_b_core_in_c0 <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
active_b_core_in_c1 <= '1' WHEN (clk1_core_clock_enable = "none") ELSE
ena1 WHEN (clk1_core_clock_enable = "ena1") ELSE
ena3;
active_b_core_in <= active_b_core_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_core_in_c1;
active_write_a <= (byteena_a_reg /= bytes_a_disabled);
active_write_b <= (byteena_b_reg /= bytes_b_disabled);
-- Store core clock enable value for delayed write
-- port A core active
active_a_core_in_vec(0) <= active_a_core_in;
active_core_port_a : stratixiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_a_core_in_vec,
clk => clk_a_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_a_core_out
);
active_a_core <= (active_a_core_out(0) = '1');
-- port B core active
active_b_core_in_vec(0) <= active_b_core_in;
active_core_port_b : stratixiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_b_core_in_vec,
clk => clk_b_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_b_core_out
);
active_b_core <= (active_b_core_out(0) = '1');
-- ------ A input registers
-- write enable
we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe;
we_a_register : stratixiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => we_a_reg_in,
clk => clk_a_wena,
aclr => we_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_core_in,
q => we_a_reg_out,
aclrout => we_a_clr
);
we_a_reg <= we_a_reg_out(0);
-- read enable
re_a_reg_in(0) <= portare;
re_a_register : stratixiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => re_a_reg_in,
clk => clk_a_rena,
aclr => re_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_core_in,
q => re_a_reg_out,
aclrout => re_a_clr
);
re_a_reg <= re_a_reg_out(0);
-- address
addr_a_register : stratixiii_ram_register
GENERIC MAP ( width => port_a_address_width )
PORT MAP (
d => portaaddr,
clk => clk_a_in,
aclr => addr_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portaaddrstall,
ena => active_a_in,
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data
datain_a_register : stratixiii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => portadatain,
clk => clk_a_in,
aclr => datain_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable
byteena_a_register : stratixiii_ram_register
GENERIC MAP (
width => port_a_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portabyteenamasks,
clk => clk_a_byteena,
aclr => byteena_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- ------ B input registers
-- read enable
re_b_reg_in(0) <= portbre;
re_b_register : stratixiii_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => re_b_reg_in,
clk => clk_b_in,
aclr => re_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_core_in,
q => re_b_reg_out,
aclrout => re_b_clr
);
re_b_reg <= re_b_reg_out(0);
-- write enable
we_b_reg_in(0) <= portbwe;
we_b_register : stratixiii_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => we_b_reg_in,
clk => clk_b_in,
aclr => we_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_core_in,
q => we_b_reg_out,
aclrout => we_b_clr
);
we_b_reg <= we_b_reg_out(0);
-- address
addr_b_register : stratixiii_ram_register
GENERIC MAP ( width => port_b_address_width )
PORT MAP (
d => portbaddr,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portbaddrstall,
ena => active_b_in,
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data
datain_b_register : stratixiii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => portbdatain,
clk => clk_b_in,
aclr => datain_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => datain_b_reg,
aclrout => datain_b_clr
);
-- byte enable
byteena_b_register : stratixiii_ram_register
GENERIC MAP (
width => port_b_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portbbyteenamasks,
clk => clk_b_byteena,
aclr => byteena_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => byteena_b_reg,
aclrout => byteena_b_clr
);
datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg;
addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg);
datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg;
addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg);
-- Write pulse generation
wpgen_a_clk <= clk_a_in;
wpgen_a_clkena <= '1' WHEN (active_a_core AND active_write_a AND (we_a_reg = '1')) ELSE '0';
wpgen_a : stratixiii_ram_pulse_generator
PORT MAP (
clk => wpgen_a_clk,
ena => wpgen_a_clkena,
delaywrite => delay_write_pulse_a,
pulse => write_pulse(primary_port_is_a),
cycle => write_cycle_a
);
wpgen_b_clk <= clk_b_in;
wpgen_b_clkena <= '1' WHEN (active_b_core AND active_write_b AND mode_is_bdp AND (we_b_reg = '1')) ELSE '0';
wpgen_b : stratixiii_ram_pulse_generator
PORT MAP (
clk => wpgen_b_clk,
ena => wpgen_b_clkena,
delaywrite => delay_write_pulse_b,
pulse => write_pulse(primary_port_is_b),
cycle => write_cycle_b
);
-- Read pulse generation
rpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '0')) ELSE '0';
rpgen_a : stratixiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rpgen_a_clkena,
cycle => clk_a_core,
pulse => read_pulse(primary_port_is_a)
);
rpgen_b_clkena <= '1' WHEN ((mode_is_dp OR mode_is_bdp) AND active_b_core AND (re_b_reg = '1') AND (we_b_reg = '0')) ELSE '0';
rpgen_b : stratixiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rpgen_b_clkena,
cycle => clk_b_core,
pulse => read_pulse(primary_port_is_b)
);
-- Read-during-Write pulse generation
rwpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '1') AND read_before_write_a) ELSE '0';
rwpgen_a : stratixiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rwpgen_a_clkena,
pulse => rw_pulse(primary_port_is_a)
);
rwpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (re_b_reg = '1') AND (we_b_reg = '1') AND read_before_write_b) ELSE '0';
rwpgen_b : stratixiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rwpgen_b_clkena,
pulse => rw_pulse(primary_port_is_b)
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (byteena_a_reg,byteena_b_reg)
VARIABLE mask : mask_rec;
BEGIN
IF (byteena_a_reg'EVENT) THEN
mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a);
IF (primary_port_is_a) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
IF (byteena_b_reg'EVENT) THEN
mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b);
IF (primary_port_is_b) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
END PROCESS mask_create;
-- (row,col) coordinates
row_sec <= addr_sec_reg / num_cols;
col_sec <= addr_sec_reg mod num_cols;
mem_rw : PROCESS (init_mem,
write_pulse,read_pulse,read_pulse_feedthru,
rw_pulse,
mem_invalidate,mem_invalidate_loc,read_latch_invalidate)
-- mem init
TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
VARIABLE addr_range_init,row,col,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init71'length + mem_init70'length + mem_init69'length + mem_init68'length + mem_init67'length + mem_init66'length +
mem_init65'length + mem_init64'length + mem_init63'length + mem_init62'length + mem_init61'length +
mem_init60'length + mem_init59'length + mem_init58'length + mem_init57'length + mem_init56'length +
mem_init55'length + mem_init54'length + mem_init53'length + mem_init52'length + mem_init51'length +
mem_init50'length + mem_init49'length + mem_init48'length + mem_init47'length + mem_init46'length +
mem_init45'length + mem_init44'length + mem_init43'length + mem_init42'length + mem_init41'length +
mem_init40'length + mem_init39'length + mem_init38'length + mem_init37'length + mem_init36'length +
mem_init35'length + mem_init34'length + mem_init33'length + mem_init32'length + mem_init31'length +
mem_init30'length + mem_init29'length + mem_init28'length + mem_init27'length + mem_init26'length +
mem_init25'length + mem_init24'length + mem_init23'length + mem_init22'length + mem_init21'length +
mem_init20'length + mem_init19'length + mem_init18'length + mem_init17'length + mem_init16'length +
mem_init15'length + mem_init14'length + mem_init13'length + mem_init12'length + mem_init11'length +
mem_init10'length + mem_init9'length + mem_init8'length + mem_init7'length + mem_init6'length +
mem_init5'length + mem_init4'length + mem_init3'length + mem_init2'length + mem_init1'length +
mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_row_type;
VARIABLE old_mem_data_p : mem_row_type;
VARIABLE row_prime,col_prime : INTEGER;
VARIABLE access_same_location : BOOLEAN;
VARIABLE read_during_write : rw_type;
BEGIN
read_during_write := (FALSE,FALSE);
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output latches to 0
IF (primary_port_is_a) THEN
dataout_prime <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF;
ELSE
dataout_sec <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF;
END IF;
IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN
mem_val := (OTHERS => (OTHERS => (OTHERS => '0')));
END IF;
IF (primary_port_is_a) THEN
addr_range_init := port_a_last_address - port_a_first_address + 1;
ELSE
addr_range_init := port_b_last_address - port_b_first_address + 1;
END IF;
IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN
mem_init := mem_init71 & mem_init70 & mem_init69 & mem_init68 & mem_init67 & mem_init66 &
mem_init65 & mem_init64 & mem_init63 & mem_init62 & mem_init61 &
mem_init60 & mem_init59 & mem_init58 & mem_init57 & mem_init56 &
mem_init55 & mem_init54 & mem_init53 & mem_init52 & mem_init51 &
mem_init50 & mem_init49 & mem_init48 & mem_init47 & mem_init46 &
mem_init45 & mem_init44 & mem_init43 & mem_init42 & mem_init41 &
mem_init40 & mem_init39 & mem_init38 & mem_init37 & mem_init36 &
mem_init35 & mem_init34 & mem_init33 & mem_init32 & mem_init31 &
mem_init30 & mem_init29 & mem_init28 & mem_init27 & mem_init26 &
mem_init25 & mem_init24 & mem_init23 & mem_init22 & mem_init21 &
mem_init20 & mem_init19 & mem_init18 & mem_init17 & mem_init16 &
mem_init15 & mem_init14 & mem_init13 & mem_init12 & mem_init11 &
mem_init10 & mem_init9 & mem_init8 & mem_init7 & mem_init6 &
mem_init5 & mem_init4 & mem_init3 & mem_init2 & mem_init1 &
mem_init0;
mem_init_std := to_stdlogicvector(mem_init) ((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
FOR col IN 0 to num_cols - 1 LOOP
index := row * data_width;
mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO
index + col*data_unit_width);
END LOOP;
END LOOP;
END IF;
mem <= mem_val;
END IF;
access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec);
-- Read before Write stage 1 : read data from memory
-- Read before Write stage 2 : send data to output
IF (rw_pulse(primary)'EVENT) THEN
IF (rw_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
ELSE
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = 'X') THEN
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END IF;
END LOOP;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
END IF;
IF (rw_pulse(secondary)'EVENT) THEN
IF (rw_pulse(secondary) = '1') THEN
read_latch.sec <= mem(row_sec)(col_sec);
ELSE
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = 'X') THEN
dataout_sec(i) <= read_latch.sec(i);
END IF;
END LOOP;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
END IF;
-- Write stage 1 : X to buffer
-- Write stage 2 : actual data to memory
IF (write_pulse(primary)'EVENT) THEN
IF (write_pulse(primary) = '1') THEN
old_mem_data_p := mem(addr_prime_reg);
mem_data_p := mem(addr_prime_reg);
FOR i IN 0 TO num_cols - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR
mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width);
END LOOP;
read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1');
IF (read_during_write(secondary)) THEN
read_latch.sec <= old_mem_data_p(col_sec);
ELSE
mem_data <= mem_data_p;
END IF;
ELSIF (clear_asserted_during_write(primary) /= '1') THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i);
ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
IF (write_pulse(secondary)'EVENT) THEN
IF (write_pulse(secondary) = '1') THEN
read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1');
IF (read_during_write(primary)) THEN
read_latch.prime <= mem(addr_prime_reg);
read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
ELSE
mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
END IF;
IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN
mask_vector_common <=
mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND
mask_vector.sec(inverse);
dual_write <= TRUE;
END IF;
ELSIF (clear_asserted_during_write(secondary) /= '1') THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
mem(row_sec)(col_sec)(i) <= datain_sec_reg(i);
ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN
mem(row_sec)(col_sec)(i) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
-- Simultaneous write
IF (dual_write AND write_pulse = "00") THEN
mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common;
dual_write <= FALSE;
END IF;
-- Read stage 1 : read data
-- Read stage 2 : send data to output
IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN
IF (read_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
IF (access_same_location AND write_pulse(secondary) = '1') THEN
read_latch.prime(col_sec) <= mem_unit_data;
END IF;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN
IF (read_pulse(secondary) = '1') THEN
IF (access_same_location AND write_pulse(primary) = '1') THEN
read_latch.sec <= mem_data(col_sec);
ELSE
read_latch.sec <= mem(row_sec)(col_sec);
END IF;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
-- Same port feed thru
IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
dataout_prime(i) <= datain_prime_reg(i);
END IF;
END LOOP;
ELSE
dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal);
END IF;
END IF;
IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
dataout_sec(i) <= datain_sec_reg(i);
END IF;
END LOOP;
ELSE
dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal);
END IF;
END IF;
-- Async clear
IF (mem_invalidate'EVENT) THEN
IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN
mem <= mem_x;
END IF;
END IF;
IF (mem_invalidate_loc'EVENT) THEN
IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF;
IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF;
END IF;
IF (read_latch_invalidate'EVENT) THEN
IF (read_latch_invalidate(primary)) THEN
read_latch.prime <= row_x;
END IF;
IF (read_latch_invalidate(secondary)) THEN
read_latch.sec <= col_x;
END IF;
END IF;
END PROCESS mem_rw;
-- Same port feed through
ftpgen_a_clkena <= '1' WHEN (active_a_core AND (NOT mode_is_dp) AND (NOT old_data_write_a) AND (we_a_reg = '1') AND (re_a_reg = '1')) ELSE '0';
ftpgen_a : stratixiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => ftpgen_a_clkena,
pulse => read_pulse_feedthru(primary_port_is_a)
);
ftpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (NOT old_data_write_b) AND (we_b_reg = '1') AND (re_b_reg = '1')) ELSE '0';
ftpgen_b : stratixiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => ftpgen_b_clkena,
pulse => read_pulse_feedthru(primary_port_is_b)
);
-- Asynch clear events
clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr)
BEGIN
IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (re_a_reg = '1') THEN
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_a;
clear_b : PROCESS(addr_b_clr,we_b_clr,datain_b_clr)
BEGIN
IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF ((mode_is_dp OR mode_is_bdp) AND re_b_reg = '1') THEN
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_b_clr'EVENT AND we_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_b;
-- Clear mux registers (Latch Clear)
-- Port A output register clear
dataout_a_clr_reg_in(0) <= dataout_a_clr;
aclr_a_mux_register : stratixiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_a_clr_reg_in,
clk => clk_a_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_a_clr_reg_out
);
dataout_a_clr_reg <= dataout_a_clr_reg_out(0);
-- Port B output register clear
dataout_b_clr_reg_in(0) <= dataout_b_clr;
aclr_b_mux_register : stratixiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_b_clr_reg_in,
clk => clk_b_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_b_clr_reg_out
);
dataout_b_clr_reg <= dataout_b_clr_reg_out(0);
-- ------ Output registers
clkena_out_c0 <= '1' WHEN (clk0_output_clock_enable = "none") ELSE ena0;
clkena_out_c1 <= '1' WHEN (clk1_output_clock_enable = "none") ELSE ena1;
clkena_a_out <= clkena_out_c0 WHEN (port_a_data_out_clock = "clock0") ELSE clkena_out_c1;
clkena_b_out <= clkena_out_c0 WHEN (port_b_data_out_clock = "clock0") ELSE clkena_out_c1;
dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec;
dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
dataout_prime WHEN primary_port_is_b ELSE dataout_sec;
dataout_a_register : stratixiii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => dataout_a,
clk => clk_a_out,
aclr => dataout_a_clr,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_a_out,
q => dataout_a_reg
);
dataout_b_register : stratixiii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_b_out,
q => dataout_b_reg
);
portadataout <= dataout_a_reg WHEN (out_a_is_reg) ELSE
(OTHERS => '0') WHEN ((dataout_a_clr = '1') OR (dataout_a_clr_reg = '1')) ELSE
dataout_a;
portbdataout <= dataout_b_reg WHEN (out_b_is_reg) ELSE
(OTHERS => '0') WHEN ((dataout_b_clr = '1') OR (dataout_b_clr_reg = '1')) ELSE
dataout_b;
eccstatus <= (OTHERS => '0');
dftout <= (OTHERS => '0');
END block_arch;
---------------------------------------------------------------------
--
-- Entity Name : stratixiii_ff
--
-- Description : Stratix III FF VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_and1;
entity stratixiii_ff is
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "stratixiii_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of stratixiii_ff : entity is TRUE;
end stratixiii_ff;
architecture vital_lcell_ff of stratixiii_ff is
attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
component stratixiii_and1
generic (XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
port (Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end component;
begin
ddelaybuffer: stratixiii_and1
port map(IN1 => d_ipd,
Y => d_dly);
asdatadelaybuffer: stratixiii_and1
port map(IN1 => asdata_ipd,
Y => asdata_dly);
asdatadelaybuffer1: stratixiii_and1
port map(IN1 => asdata_dly,
Y => asdata_dly1);
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iq := '0';
elsif (power_up = "high") then
iq := '1';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then
iq := '0';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly1;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
2 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
3 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_ff;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for Stratix III CLKSELECT Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- STRATIXIII_CLKSELECT Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_clkselect is
generic (
lpm_type : STRING := "stratixiii_clkselect";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tpd_inclk_outclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_clkselect_outclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
outclk : out std_logic
);
attribute VITAL_LEVEL0 of stratixiii_clkselect : entity is TRUE;
end stratixiii_clkselect;
architecture vital_clkselect of stratixiii_clkselect is
attribute VITAL_LEVEL0 of vital_clkselect : architecture is TRUE;
signal inclk_ipd : std_logic_vector(3 downto 0);
signal clkselect_ipd : std_logic_vector(1 downto 0);
signal clkmux_out : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (inclk_ipd(0), inclk(0), tipd_inclk(0));
VitalWireDelay (inclk_ipd(1), inclk(1), tipd_inclk(1));
VitalWireDelay (inclk_ipd(2), inclk(2), tipd_inclk(2));
VitalWireDelay (inclk_ipd(3), inclk(3), tipd_inclk(3));
VitalWireDelay (clkselect_ipd(0), clkselect(0), tipd_clkselect(0));
VitalWireDelay (clkselect_ipd(1), clkselect(1), tipd_clkselect(1));
end block;
process(inclk_ipd, clkselect_ipd)
variable outclk_VitalGlitchData : VitalGlitchDataType;
variable tmp : std_logic;
begin
if (clkselect_ipd = "11") then
tmp := inclk_ipd(3);
elsif (clkselect_ipd = "10") then
tmp := inclk_ipd(2);
elsif (clkselect_ipd = "01") then
tmp := inclk_ipd(1);
else
tmp := inclk_ipd(0);
end if;
clkmux_out <= tmp;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01
(
OutSignal => outclk,
OutSignalName => "OUTCLOCK",
OutTemp => tmp,
Paths => (0 => (inclk_ipd(0)'last_event, tpd_inclk_outclk(0), TRUE),
1 => (inclk_ipd(1)'last_event, tpd_inclk_outclk(1), TRUE),
2 => (inclk_ipd(2)'last_event, tpd_inclk_outclk(2), TRUE),
3 => (inclk_ipd(3)'last_event, tpd_inclk_outclk(3), TRUE),
4 => (clkselect_ipd(0)'last_event, tpd_clkselect_outclk(0), TRUE),
5 => (clkselect_ipd(1)'last_event, tpd_clkselect_outclk(1), TRUE)),
GlitchData => outclk_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
end process;
end vital_clkselect;
--/////////////////////////////////////////////////////////////////////////////
--
-- stratixiii_and2 Model
-- Description : Simulation model for a simple two input AND gate.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.stratixiii_atom_pack.all;
-- entity declaration --
entity stratixiii_and2 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tpd_IN2_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC;
IN2 : in STD_LOGIC);
attribute VITAL_LEVEL0 of stratixiii_and2 : entity is TRUE;
end stratixiii_and2;
-- architecture body --
architecture AltVITAL of stratixiii_and2 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
SIGNAL IN2_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd, IN2_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd) AND TO_X01(IN2_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => ( 0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE),
1 => (IN2_ipd'last_event, tpd_IN2_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixiii_ena_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for the gated clock generation
-- Powers upto 1.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_ena_reg is
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of stratixiii_ena_reg : entity is TRUE;
end stratixiii_ena_reg;
ARCHITECTURE behave of stratixiii_ena_reg is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
end block;
VITALtiming : process (clk_ipd, prn, clrn)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '1';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((clrn) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiii_ena_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' and (ena = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for Stratix III CLKCTRL Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- Stratix III_CLKCTRL Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_ena_reg;
use work.stratixiii_and2;
entity stratixiii_clkena is
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "stratixiii_clkena";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic := '0';
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
enaout : out std_logic;
outclk : out std_logic
);
attribute VITAL_LEVEL0 of stratixiii_clkena : entity is TRUE;
end stratixiii_clkena;
architecture vital_clkena of stratixiii_clkena is
attribute VITAL_LEVEL0 of vital_clkena : architecture is TRUE;
component stratixiii_and2
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tpd_IN2_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC;
IN2 : in STD_LOGIC);
end component;
component stratixiii_ena_reg
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end component;
signal inclk_ipd : std_logic;
signal inclk_inv : std_logic;
signal ena_ipd : std_logic;
signal cereg_clr : std_logic;
signal cereg1_out : std_logic;
signal cereg2_out : std_logic;
signal ena_out : std_logic;
signal vcc : std_logic := '1';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (inclk_ipd, inclk, tipd_inclk);
end block;
inclk_inv <= NOT inclk_ipd;
extena_reg1 : stratixiii_ena_reg
port map (
clk => inclk_inv,
ena => vcc,
d => ena_ipd,
clrn => vcc,
prn => devpor,
q => cereg1_out
);
extena_reg2 : stratixiii_ena_reg
port map (
clk => inclk_inv,
ena => vcc,
d => cereg1_out,
clrn => vcc,
prn => devpor,
q => cereg2_out
);
ena_out <= cereg1_out WHEN (ena_register_mode = "falling edge") ELSE
ena_ipd WHEN (ena_register_mode = "none") ELSE cereg2_out;
outclk_and : stratixiii_and2
port map (
IN1 => inclk_ipd,
IN2 => ena_out,
Y => outclk
);
enaout_and : stratixiii_and2
port map (
IN1 => vcc,
IN2 => ena_out,
Y => enaout
);
end vital_clkena;
----------------------------------------------------------------------------
-- Module Name : stratixiii_mlab_cell_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
ENTITY stratixiii_mlab_cell_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (1 ps,1 ps);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF stratixiii_mlab_cell_pulse_generator:ENTITY IS TRUE;
END stratixiii_mlab_cell_pulse_generator;
ARCHITECTURE pgen_arch OF stratixiii_mlab_cell_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
state <= '1';
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
USE work.stratixiii_mlab_cell_pulse_generator;
ENTITY stratixiii_mlab_cell IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
logical_ram_name : STRING := "lutram";
init_file : STRING := "UNUSED";
data_interleave_offset_in_bits : INTEGER := 1;
logical_ram_depth : INTEGER := 0;
logical_ram_width : INTEGER := 0;
first_address : INTEGER := 0;
last_address : INTEGER := 0;
first_bit_number : INTEGER := 0;
data_width : INTEGER := 1;
address_width : INTEGER := 1;
byte_enable_mask_width : INTEGER := 1;
byte_size : INTEGER := 1;
lpm_type : string := "stratixiii_mlab_cell";
lpm_hint : string := "true";
mixed_port_feed_through_mode : string := "dont_care";
mem_init0 : BIT_VECTOR := X"0";
-- --------- VITAL PARAMETERS --------
tipd_clk0 : VitalDelayType01 := DefPropDelay01;
tipd_ena0 : VitalDelayType01 := DefPropDelay01;
tipd_portaaddr : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portbaddr : VitalDelayArrayType01(7 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_portabyteenamasks : VitalDelayArrayType01(20 DOWNTO 0) := (OTHERS => DefPropDelay01);
tsetup_portaaddr_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_portabyteenamasks_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena0_clk0_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_portaaddr_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_portabyteenamasks_clk0_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ena0_clk0_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_portbaddr_portbdataout : VitalDelayType01 := DefPropDelay01
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (OTHERS => '0');
portabyteenamasks : IN STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbaddr : IN STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0) := (OTHERS => '0');
clk0 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
portbdataout : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0)
);
END stratixiii_mlab_cell;
ARCHITECTURE block_arch OF stratixiii_mlab_cell IS
COMPONENT stratixiii_mlab_cell_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
CONSTANT port_byte_size : INTEGER := data_width / byte_enable_mask_width;
-- -------- internal signals ---------
-- Write address
SIGNAL write_address : INTEGER := 0;
SIGNAL read_address : INTEGER := 0;
-- pulses
SIGNAL write_pulse, write_cycle, write_clock : STD_LOGIC;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
TYPE mem_type IS ARRAY ((2 ** address_width) - 1 DOWNTO 0) OF mem_word_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_write IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
SIGNAL mask_vector : mask_write := (
normal => (OTHERS => '0'),
inverse => (OTHERS => 'X')
);
-- output
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_write IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_write := (normal => (OTHERS => '0'),inverse => (OTHERS => 'X'));
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
mask(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
mask(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END LOOP;
RETURN mask;
END get_mask;
SIGNAL clk0_ipd : STD_LOGIC;
SIGNAL ena0_ipd : STD_LOGIC;
SIGNAL portaaddr_ipd : STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0);
SIGNAL portbaddr_ipd : STD_LOGIC_VECTOR(address_width - 1 DOWNTO 0);
SIGNAL portabyteenamasks_ipd : STD_LOGIC_VECTOR(byte_enable_mask_width - 1 DOWNTO 0);
SIGNAL ena0_reg : STD_LOGIC := '0';
BEGIN
-- interconnect delays
WireDelay : BLOCK
BEGIN
loopbits_ad : FOR i in portaaddr'RANGE GENERATE
VitalWireDelay (portaaddr_ipd(i), portaaddr(i), tipd_portaaddr(i));
VitalWireDelay (portbaddr_ipd(i), portbaddr(i), tipd_portbaddr(i));
END GENERATE;
loopbits_be : FOR j in portabyteenamasks'RANGE GENERATE
VitalWireDelay (portabyteenamasks_ipd(j), portabyteenamasks(j), tipd_portabyteenamasks(j));
END GENERATE;
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (ena0_ipd, ena0, tipd_ena0);
END BLOCK;
-- setup/hold checks
setup_hold_checks: PROCESS (ena0_reg,portaaddr_ipd,portabyteenamasks_ipd,clk0_ipd,ena0_ipd)
VARIABLE Tviol_clk_enable : STD_ULOGIC := '0';
VARIABLE Tviol_clk_address : STD_ULOGIC := '0';
VARIABLE Tviol_clk_bemasks : STD_ULOGIC := '0';
VARIABLE TimingData_clk_enable : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_address : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_bemasks : VitalTimingDataType := VitalTimingDataInit;
BEGIN
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_enable,
TimingData => TimingData_clk_enable,
TestSignal => ena0_ipd,
TestSignalName => "ena0",
RefSignal => clk0_ipd,
RefSignalName => "clk0",
SetupHigh => tsetup_ena0_clk0_noedge_posedge,
SetupLow => tsetup_ena0_clk0_noedge_posedge,
HoldHigh => thold_ena0_clk0_noedge_posedge,
HoldLow => thold_ena0_clk0_noedge_posedge,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => "/LUTRAM VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_address,
TimingData => TimingData_clk_address,
TestSignal => portaaddr_ipd,
TestSignalName => "portaaddr",
RefSignal => clk0_ipd,
RefSignalName => "clk0",
SetupHigh => tsetup_portaaddr_clk0_noedge_negedge,
SetupLow => tsetup_portaaddr_clk0_noedge_negedge,
HoldHigh => thold_portaaddr_clk0_noedge_negedge,
HoldLow => thold_portaaddr_clk0_noedge_negedge,
CheckEnabled => (ena0_reg = '1'),
RefTransition => '\',
HeaderMsg => "/LUTRAM VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_bemasks,
TimingData => TimingData_clk_bemasks,
TestSignal => portabyteenamasks_ipd,
TestSignalName => "portabyteenamasks",
RefSignal => clk0_ipd,
RefSignalName => "clk0",
SetupHigh => tsetup_portabyteenamasks_clk0_noedge_negedge,
SetupLow => tsetup_portabyteenamasks_clk0_noedge_negedge,
HoldHigh => thold_portabyteenamasks_clk0_noedge_negedge,
HoldLow => thold_portabyteenamasks_clk0_noedge_negedge,
CheckEnabled => (ena0_reg = '1'),
RefTransition => '\',
HeaderMsg => "/LUTRAM VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
END PROCESS setup_hold_checks;
-- latch CE signal
PROCESS (clk0_ipd)
BEGIN
IF (clk0_ipd'EVENT AND clk0_ipd = '1') THEN
ena0_reg <= ena0_ipd;
END IF;
END PROCESS;
-- output path delay
PROCESS (portbaddr_ipd)
VARIABLE CQDelay : TIME := 0 ns;
BEGIN
CQDelay := SelectDelay(
( 1 => ( portbaddr_ipd'LAST_EVENT, tpd_portbaddr_portbdataout, TRUE ) )
);
read_address <= TRANSPORT alt_conv_integer(portbaddr_ipd) AFTER CQDelay;
END PROCESS;
-- memory initialization
init_mem <= TRUE;
write_clock <= NOT clk0_ipd;
write_address <= alt_conv_integer(portaaddr_ipd);
-- Write pulse generation (neg edge)
wpgen_a : stratixiii_mlab_cell_pulse_generator
PORT MAP (
clk => write_clock,
ena => ena0_reg,
pulse => write_pulse,
cycle => write_cycle
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (portabyteenamasks_ipd)
VARIABLE mask : mask_write;
BEGIN
IF (portabyteenamasks_ipd'EVENT) THEN
mask := get_mask(portabyteenamasks_ipd,byte_enable_mask_width,port_byte_size);
mask_vector <= mask;
END IF;
END PROCESS mask_create;
mem_rw : PROCESS (init_mem, write_pulse)
-- mem init
VARIABLE addr_range_init,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((last_address - first_address + 1)*data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_word_type;
BEGIN
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output to 0
mem_val := (OTHERS => (OTHERS => '0'));
IF (init_file /= "UNUSED" AND init_file /= "unused") THEN
addr_range_init := last_address - first_address + 1;
mem_init := mem_init0;
mem_init_std := to_stdlogicvector(mem_init)((last_address - first_address + 1)*data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
index := row * data_width;
mem_val(row) := mem_init_std(index + data_width -1 DOWNTO index );
END LOOP;
END IF;
mem <= mem_val;
END IF;
-- Write stage 1 : X to memory
-- Write stage 2 : actual data to memory
IF (write_pulse'EVENT) THEN
IF (write_pulse = '1') THEN
mem_data_p := mem(write_address);
FOR i IN 0 TO data_width - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR mask_vector(inverse)(i);
END LOOP;
mem(write_address) <= mem_data_p;
ELSIF (write_pulse = '0') THEN
mem_data_p := mem(write_address);
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector(normal)(i) = '0') THEN
mem(write_address)(i) <= portadatain(i);
mem_data_p(i) := portadatain(i);
ELSIF (mask_vector(inverse)(i) = 'X') THEN
mem(write_address)(i) <= 'X';
mem_data_p(i) := 'X';
END IF;
END LOOP;
END IF;
END IF;
END PROCESS mem_rw;
-- Continuous read
portbdataout <= mem(read_address);
END block_arch;
---------------------------------------------------------------------
--
-- Entity Name : stratixiii_io_ibuf
--
-- Description : Stratix III IO Ibuf VHDL simulation model
--
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_io_ibuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "stratixiii_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
dynamicterminationcontrol : IN std_logic := '0';
o : OUT std_logic
);
END stratixiii_io_ibuf;
ARCHITECTURE arch OF stratixiii_io_ibuf IS
SIGNAL i_ipd : std_logic := '0';
SIGNAL ibar_ipd : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL out_tmp : std_logic;
SIGNAL prev_value : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (ibar_ipd, ibar, tipd_ibar);
end block;
PROCESS(i_ipd, ibar_ipd)
BEGIN
IF (differential_mode = "false") THEN
IF (i_ipd = '1') THEN
o_tmp <= '1';
prev_value <= '1';
ELSIF (i_ipd = '0') THEN
o_tmp <= '0';
prev_value <= '0';
ELSE
o_tmp <= i_ipd;
END IF;
ELSE
IF (( i_ipd = '0' ) and (ibar_ipd = '1')) then
o_tmp <= '0';
ELSIF (( i_ipd = '1' ) and (ibar_ipd = '0')) then
o_tmp <= '1';
ELSIF((( i_ipd = '1' ) and (ibar_ipd = '1')) or (( i_ipd = '0' ) and (ibar_ipd = '0')))then
o_tmp <= 'X';
ELSE
o_tmp <= 'X';
END IF;
END IF;
END PROCESS;
out_tmp <= prev_value when (bus_hold = "true") else
'Z' when((o_tmp = 'Z') AND (simulate_z_as = "Z")) else
'X' when((o_tmp = 'Z') AND (simulate_z_as = "X")) else
'1' when((o_tmp = 'Z') AND (simulate_z_as = "vcc")) else
'0' when((o_tmp = 'Z') AND (simulate_z_as = "gnd")) else
o_tmp;
----------------------
-- Path Delay Section
----------------------
PROCESS( out_tmp)
variable output_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => out_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (ibar_ipd'last_event, tpd_ibar_o, TRUE)),
GlitchData => output_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : stratixiii_io_obuf
--
-- Description : Stratix III IO Obuf VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_io_obuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_dynamicterminationcontrol : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
shift_series_termination_control : string := "false";
sim_dynamic_termination_control_is_connected : string := "false";
bus_hold : string := "false";
lpm_type : string := "stratixiii_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
dynamicterminationcontrol : IN std_logic := '0';
seriesterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0');
parallelterminationcontrol : IN std_logic_vector(13 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END stratixiii_io_obuf;
ARCHITECTURE arch OF stratixiii_io_obuf IS
--INTERNAL Signals
SIGNAL i_ipd : std_logic := '0';
SIGNAL oe_ipd : std_logic := '0';
SIGNAL dynamicterminationcontrol_ipd : std_logic := '0';
SIGNAL out_tmp : std_logic := 'Z';
SIGNAL out_tmp_bar : std_logic;
SIGNAL prev_value : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL obar_tmp : std_logic;
SIGNAL o_tmp1 : std_logic;
SIGNAL obar_tmp1 : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (dynamicterminationcontrol_ipd, dynamicterminationcontrol, tipd_dynamicterminationcontrol);
end block;
PROCESS( i_ipd, oe_ipd)
BEGIN
IF (oe_ipd = '1') THEN
IF (open_drain_output = "true") THEN
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
END IF;
ELSE
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
IF (i_ipd = '1') THEN
out_tmp <= '1';
out_tmp_bar <= '0';
prev_value <= '1';
ELSE
out_tmp <= i_ipd;
out_tmp_bar <= i_ipd;
END IF;
END IF;
END IF;
ELSE
IF (oe_ipd = '0') THEN
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
ELSE
out_tmp <= 'X';
out_tmp_bar <= 'X';
END IF;
END IF;
END PROCESS;
o_tmp1 <= prev_value WHEN (bus_hold = "true") ELSE out_tmp;
obar_tmp1 <= NOT prev_value WHEN (bus_hold = "true") ELSE out_tmp_bar;
o_tmp <= 'X' when (( oe_ipd = '1') and (dynamicterminationcontrol = '1') and (sim_dynamic_termination_control_is_connected = "true")) else o_tmp1 WHEN (devoe = '1') ELSE 'Z';
obar_tmp <= 'X' when (( oe_ipd = '1') and (dynamicterminationcontrol = '1')and (sim_dynamic_termination_control_is_connected = "true")) else obar_tmp1 WHEN (devoe = '1') ELSE 'Z';
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (oe_ipd'last_event, tpd_oe_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE),
1 => (oe_ipd'last_event, tpd_oe_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
-----------------------------------------------------------------------
--
-- Entity Name : stratixiii_ddio_in
--
-- Description : Stratix III DDIO_IN VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_ddio_in IS
generic(
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkn : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_clkn : string := "false";
lpm_type : string := "stratixiii_ddio_in"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
clkn : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
regoutlo : OUT std_logic;
regouthi : OUT std_logic;
dfflo : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiii_ddio_in;
ARCHITECTURE arch OF stratixiii_ddio_in IS
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL datain_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL clkn_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL ddioreg_clk : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL regout_tmp_hi : std_logic;
SIGNAL regout_tmp_lo : std_logic;
SIGNAL regouthi_tmp : std_logic;
SIGNAL regoutlo_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (clkn_ipd, clkn, tipd_clkn);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
ddioreg_clk <= NOT clk_ipd WHEN (use_clkn = "false") ELSE clkn_ipd;
--Decode the control values for the DDIO registers
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
--DDIO High Register
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datain_ipd,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => regout_tmp_hi,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datain_ipd,
clk => ddioreg_clk,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
ddioreg_lo1 : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dfflo_tmp,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => regout_tmp_lo,
devpor => devpor,
devclrn => devclrn
);
regouthi <= regout_tmp_hi ;
regoutlo <= regout_tmp_lo ;
dfflo <= dfflo_tmp ;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : stratixiii_ddio_oe
--
-- Description : Stratix III DDIO_OE VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_ddio_oe IS
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "stratixiii_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiii_ddio_oe;
ARCHITECTURE arch OF stratixiii_ddio_oe IS
component stratixiii_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL oe_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
signal nclk : std_logic;
signal dataout_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
nclk <= NOT clk_ipd;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => oe_ipd,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dffhi_tmp,
clk => nclk,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
--registered output
or_gate : stratixiii_mux21
port map (
A => dffhi_tmp,
B => dfflo_tmp,
S => dfflo_tmp,
MO => dataout
);
dfflo <= dfflo_tmp ;
dffhi <= dffhi_tmp ;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : stratixiii_ddio_out
--
-- Description : Stratix III DDIO_OUT VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_ddio_out IS
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
half_rate_mode : string := "false";
use_new_clocking_model : string := "false";
lpm_type : string := "stratixiii_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic_vector(1 downto 0) ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiii_ddio_out;
ARCHITECTURE arch OF stratixiii_ddio_out IS
component stratixiii_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL datainlo_ipd : std_logic := '0';
SIGNAL datainhi_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL clkhi_ipd : std_logic := '0';
SIGNAL clklo_ipd : std_logic := '0';
SIGNAL muxsel_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
SIGNAL dataout_tmp : std_logic;
Signal mux_sel : std_logic;
Signal mux_hi : std_logic;
Signal dffhi1_tmp : std_logic;
Signal sel_mux_hi_in : std_logic;
signal nclk : std_logic;
signal clk1 : std_logic;
signal clk_hi : std_logic;
signal clk_lo : std_logic;
signal clk_hr : std_logic;
signal muxsel1 : std_logic;
signal muxsel2: std_logic;
signal clk2 : std_logic;
signal muxsel_tmp: std_logic;
signal sel_mux_lo_in : std_logic;
signal datainlo_tmp : std_logic;
signal datainhi_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (datainlo_ipd, datainlo, tipd_datainlo);
VitalWireDelay (datainhi_ipd, datainhi, tipd_datainhi);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (clkhi_ipd, clkhi, tipd_clkhi);
VitalWireDelay (clklo_ipd, clklo, tipd_clklo);
VitalWireDelay (muxsel_ipd, muxsel, tipd_muxsel);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
nclk <= NOT clk_ipd;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
process(clk_ipd)
begin
clk1 <= clk_ipd;
end process;
process(muxsel_ipd)
begin
muxsel1 <= muxsel_ipd;
end process;
--DDIO HIGH Register
clk_hi <= clkhi_ipd when(use_new_clocking_model = "true") else clk_ipd;
datainhi_tmp <= datainhi;
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainhi_tmp,
clk => clk_hi,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
clk_lo <= clklo_ipd when(use_new_clocking_model = "true") else clk_ipd;
datainlo_tmp <= datainlo;
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainlo_tmp,
clk => clk_lo,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
clk_hr <= NOT clkhi_ipd when(use_new_clocking_model = "true") else NOT clk_ipd;
ddioreg_hi1 : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dffhi_tmp,
clk => clk_hr,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi1_tmp,
devpor => devpor,
devclrn => devclrn
);
muxsel2 <= muxsel1;
clk2 <= clk1;
mux_sel <= muxsel2 when(use_new_clocking_model = "true") else clk2;
muxsel_tmp <= mux_sel;
sel_mux_lo_in <= dfflo_tmp;
sel_mux_hi_in <= dffhi1_tmp when(half_rate_mode = "true") else dffhi_tmp;
sel_mux : stratixiii_mux21
port map (
A => sel_mux_lo_in,
B => sel_mux_hi_in,
S => muxsel_tmp,
MO => dataout
);
dfflo <= dfflo_tmp;
dffhi(0) <= dffhi_tmp;
dffhi(1) <= dffhi1_tmp;
END arch;
-- --------------------------------------------------------------------
-- Module Name: stratixiii_rt_sm
-- Description: Parallel Termination State Machine
-- --------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
ENTITY stratixiii_rt_sm IS
PORT (
rup : IN std_logic;
rdn : IN std_logic;
clk : IN std_logic;
clken : IN std_logic;
clr : IN std_logic;
rtena : IN std_logic;
rscaldone : IN std_logic;
rtoffsetp : OUT std_logic_vector(3 DOWNTO 0);
rtoffsetn : OUT std_logic_vector(3 DOWNTO 0);
caldone : OUT std_logic;
sel_rup_vref : OUT std_logic_vector(2 DOWNTO 0);
sel_rdn_vref : OUT std_logic_vector(2 DOWNTO 0));
END stratixiii_rt_sm;
ARCHITECTURE stratixiii_rt_sm_rtl OF stratixiii_rt_sm IS
CONSTANT STRATIXIII_RTOCT_WAIT : std_logic_vector(4 DOWNTO 0) := "00000";
CONSTANT RUP_VREF_M_RDN_VER_M : std_logic_vector(4 DOWNTO 0) := "00001";
CONSTANT RUP_VREF_L_RDN_VER_L : std_logic_vector(4 DOWNTO 0) := "00010";
CONSTANT RUP_VREF_H_RDN_VER_H : std_logic_vector(4 DOWNTO 0) := "00011";
CONSTANT RUP_VREF_L_RDN_VER_H : std_logic_vector(4 DOWNTO 0) := "00100";
CONSTANT RUP_VREF_H_RDN_VER_L : std_logic_vector(4 DOWNTO 0) := "00101";
CONSTANT STRATIXIII_RTOCT_INC_PN : std_logic_vector(4 DOWNTO 0) := "01000";
CONSTANT STRATIXIII_RTOCT_DEC_PN : std_logic_vector(4 DOWNTO 0) := "01001";
CONSTANT STRATIXIII_RTOCT_INC_P : std_logic_vector(4 DOWNTO 0) := "01010";
CONSTANT STRATIXIII_RTOCT_DEC_P : std_logic_vector(4 DOWNTO 0) := "01011";
CONSTANT STRATIXIII_RTOCT_INC_N : std_logic_vector(4 DOWNTO 0) := "01100";
CONSTANT STRATIXIII_RTOCT_DEC_N : std_logic_vector(4 DOWNTO 0) := "01101";
CONSTANT STRATIXIII_RTOCT_SWITCH_REG: std_logic_vector(4 DOWNTO 0) := "10001";
CONSTANT STRATIXIII_RTOCT_DONE : std_logic_vector(4 DOWNTO 0) := "11111";
-- interface
SIGNAL nclr : std_logic := '1'; -- for synthesis
SIGNAL rtcalclk : std_logic;
SIGNAL caldone_sig : std_logic := '0';
-- sm
SIGNAL current_state : std_logic_vector(4 DOWNTO 0) := "00000";
SIGNAL next_state : std_logic_vector(4 DOWNTO 0) := "00000";
SIGNAL sel_rup_vref_h_d : std_logic := '0';
SIGNAL sel_rup_vref_h : std_logic := '0';
SIGNAL sel_rup_vref_m_d : std_logic := '1';
SIGNAL sel_rup_vref_m : std_logic := '1';
SIGNAL sel_rup_vref_l_d : std_logic := '0';
SIGNAL sel_rup_vref_l : std_logic := '0';
SIGNAL sel_rdn_vref_h_d : std_logic := '0';
SIGNAL sel_rdn_vref_h : std_logic := '0';
SIGNAL sel_rdn_vref_m_d : std_logic := '1';
SIGNAL sel_rdn_vref_m : std_logic := '1';
SIGNAL sel_rdn_vref_l_d : std_logic := '0';
SIGNAL sel_rdn_vref_l : std_logic := '0';
SIGNAL switch_region_d : std_logic := '0';
SIGNAL switch_region : std_logic := '0';
SIGNAL cmpup : std_logic := '0';
SIGNAL cmpdn : std_logic := '0';
SIGNAL rt_sm_done_d : std_logic := '0';
SIGNAL rt_sm_done : std_logic := '0';
-- cnt
SIGNAL p_cnt_d : std_logic_vector(2 DOWNTO 0) := "000";
SIGNAL p_cnt : std_logic_vector(2 DOWNTO 0) := "000";
SIGNAL n_cnt_d : std_logic_vector(2 DOWNTO 0) := "000";
SIGNAL n_cnt : std_logic_vector(2 DOWNTO 0) := "000";
SIGNAL p_cnt_sub_d : std_logic := '0';
SIGNAL p_cnt_sub : std_logic := '0';
SIGNAL n_cnt_sub_d : std_logic := '0';
SIGNAL n_cnt_sub : std_logic := '0';
BEGIN
-- primary output - MSB is sign bit
rtoffsetp <= p_cnt_sub & p_cnt ;
rtoffsetn <= n_cnt_sub & n_cnt ;
caldone <= caldone_sig;
caldone_sig <= rt_sm_done WHEN (rtena = '1') ELSE '1';
sel_rup_vref <= sel_rup_vref_h & sel_rup_vref_m & sel_rup_vref_l ;
sel_rdn_vref <= sel_rdn_vref_h & sel_rdn_vref_m & sel_rdn_vref_l ;
-- input interface
nclr <= NOT clr ;
rtcalclk <= ((rscaldone AND clken) AND (NOT caldone_sig)) AND clk ;
-- latch registers - rising on everything except cmpup and cmpdn
-- cmpup/dn
PROCESS
BEGIN
WAIT UNTIL (rtcalclk'EVENT AND rtcalclk = '0') OR (nclr'EVENT AND nclr = '0');
IF (nclr = '0') THEN
cmpup <= '0';
cmpdn <= '0';
ELSE
cmpup <= rup;
cmpdn <= rdn;
END IF;
END PROCESS;
-- other regisers
PROCESS
BEGIN
WAIT UNTIL (rtcalclk'EVENT AND rtcalclk = '1') OR (clr'EVENT AND clr = '1');
IF (clr = '1') THEN
current_state <= STRATIXIII_RTOCT_WAIT;
switch_region <= '0';
rt_sm_done <= '0';
p_cnt <= "000";
p_cnt_sub <= '0';
n_cnt <= "000";
n_cnt_sub <= '0';
sel_rup_vref_h <= '0';
sel_rup_vref_m <= '1';
sel_rup_vref_l <= '0';
sel_rdn_vref_h <= '0';
sel_rdn_vref_m <= '1';
sel_rdn_vref_l <= '0';
ELSE
current_state <= next_state;
switch_region <= switch_region_d;
rt_sm_done <= rt_sm_done_d;
p_cnt <= p_cnt_d;
p_cnt_sub <= p_cnt_sub_d;
n_cnt <= n_cnt_d;
n_cnt_sub <= n_cnt_sub_d;
sel_rup_vref_h <= sel_rup_vref_h_d;
sel_rup_vref_m <= sel_rup_vref_m_d;
sel_rup_vref_l <= sel_rup_vref_l_d;
sel_rdn_vref_h <= sel_rdn_vref_h_d;
sel_rdn_vref_m <= sel_rdn_vref_m_d;
sel_rdn_vref_l <= sel_rdn_vref_l_d;
END IF;
END PROCESS;
-- state machine
PROCESS(current_state, rtena, cmpup, cmpdn, p_cnt, n_cnt, switch_region)
variable p_cnt_d_var, n_cnt_d_var : std_logic_vector(2 DOWNTO 0);
variable p_cnt_sub_d_var, n_cnt_sub_d_var : std_logic;
BEGIN
p_cnt_d_var := p_cnt;
n_cnt_d_var := n_cnt;
p_cnt_sub_d_var := '0';
n_cnt_sub_d_var := '0';
CASE current_state IS
WHEN STRATIXIII_RTOCT_WAIT =>
IF (rtena = '0') THEN
next_state <= STRATIXIII_RTOCT_WAIT;
ELSE
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
WHEN RUP_VREF_M_RDN_VER_M =>
IF (cmpup = '0' AND cmpdn = '0') THEN
next_state <= RUP_VREF_L_RDN_VER_L;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '1';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '1';
ELSE
IF (cmpup = '1' AND cmpdn = '1') THEN
next_state <= RUP_VREF_H_RDN_VER_H;
sel_rup_vref_h_d <= '1';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '1';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '0';
ELSE
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= STRATIXIII_RTOCT_INC_PN;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '0';
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '0';
ELSE
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= STRATIXIII_RTOCT_DEC_PN;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '1';
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '1';
END IF;
END IF;
END IF;
END IF;
WHEN RUP_VREF_L_RDN_VER_L =>
IF (cmpup = '1' AND cmpdn = '1') THEN
next_state <= STRATIXIII_RTOCT_DONE;
ELSE
IF (cmpup = '0') THEN
next_state <= STRATIXIII_RTOCT_DEC_N;
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '1';
ELSE
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= STRATIXIII_RTOCT_INC_P;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '0';
END IF;
END IF;
END IF;
WHEN RUP_VREF_H_RDN_VER_H =>
IF (cmpup = '0' AND cmpdn = '0') THEN
next_state <= STRATIXIII_RTOCT_DONE;
ELSE
IF (cmpup = '1') THEN
next_state <= STRATIXIII_RTOCT_INC_N;
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '0';
ELSE
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= STRATIXIII_RTOCT_DEC_P;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '1';
END IF;
END IF;
END IF;
WHEN RUP_VREF_L_RDN_VER_H =>
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= STRATIXIII_RTOCT_DONE;
ELSE
IF (cmpup = '1' AND switch_region = '1') THEN
next_state <= STRATIXIII_RTOCT_DEC_P;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '1';
ELSE
IF (cmpup = '0' AND switch_region = '1') THEN
next_state <= STRATIXIII_RTOCT_DEC_N;
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '1';
ELSE
IF ((switch_region = '0') AND (cmpup = '0' OR cmpdn = '1')) THEN
next_state <= STRATIXIII_RTOCT_SWITCH_REG;
switch_region_d <= '1';
END IF;
END IF;
END IF;
END IF;
WHEN RUP_VREF_H_RDN_VER_L =>
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= STRATIXIII_RTOCT_DONE;
ELSE
IF (cmpup = '1' AND switch_region = '1') THEN
next_state <= STRATIXIII_RTOCT_INC_N;
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '0';
ELSE
IF (cmpup = '0' AND switch_region = '1') THEN
next_state <= STRATIXIII_RTOCT_INC_P;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '0';
ELSE
IF ((switch_region = '0') AND (cmpup = '1' OR cmpdn = '0')) THEN
next_state <= STRATIXIII_RTOCT_SWITCH_REG;
switch_region_d <= '1';
END IF;
END IF;
END IF;
END IF;
WHEN STRATIXIII_RTOCT_INC_PN =>
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= STRATIXIII_RTOCT_INC_PN;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '0';
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '0';
ELSE
IF (cmpup = '0' AND cmpdn = '0') THEN
next_state <= RUP_VREF_L_RDN_VER_L;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '1';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '1';
ELSE
IF (cmpup = '1' AND cmpdn = '1') THEN
next_state <= RUP_VREF_H_RDN_VER_H;
sel_rup_vref_h_d <= '1';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '1';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '0';
ELSE
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= RUP_VREF_L_RDN_VER_H;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '1';
sel_rdn_vref_h_d <= '1';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
END IF;
END IF;
WHEN STRATIXIII_RTOCT_DEC_PN =>
IF (cmpup = '0' AND cmpdn = '1') THEN
next_state <= STRATIXIII_RTOCT_DEC_PN;
p_cnt_d_var := p_cnt_d_var + 1;
p_cnt_sub_d_var := '1';
n_cnt_d_var := n_cnt_d_var + 1;
n_cnt_sub_d_var := '1';
ELSE
IF (cmpup = '0' AND cmpdn = '0') THEN
next_state <= RUP_VREF_L_RDN_VER_L;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '1';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '1';
ELSE
IF (cmpup = '1' AND cmpdn = '1') THEN
next_state <= RUP_VREF_H_RDN_VER_H;
sel_rup_vref_h_d <= '1';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '1';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '0';
ELSE
IF (cmpup = '1' AND cmpdn = '0') THEN
next_state <= RUP_VREF_H_RDN_VER_L;
sel_rup_vref_h_d <= '1';
sel_rup_vref_m_d <= '0';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '0';
sel_rdn_vref_l_d <= '1';
END IF;
END IF;
END IF;
END IF;
----------------- same action begin
WHEN STRATIXIII_RTOCT_INC_P =>
IF (switch_region = '1') THEN
next_state <= STRATIXIII_RTOCT_DONE;
ELSE
IF (switch_region = '0') THEN
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
WHEN STRATIXIII_RTOCT_DEC_P =>
IF (switch_region = '1') THEN
next_state <= STRATIXIII_RTOCT_DONE;
ELSE
IF (switch_region = '0') THEN
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
WHEN STRATIXIII_RTOCT_INC_N =>
IF (switch_region = '1') THEN
next_state <= STRATIXIII_RTOCT_DONE;
ELSE
IF (switch_region = '0') THEN
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
WHEN STRATIXIII_RTOCT_DEC_N =>
IF (switch_region = '1') THEN
next_state <= STRATIXIII_RTOCT_DONE;
ELSE
IF (switch_region = '0') THEN
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
END IF;
END IF;
----------------- same action end
WHEN STRATIXIII_RTOCT_SWITCH_REG =>
next_state <= RUP_VREF_M_RDN_VER_M;
sel_rup_vref_h_d <= '0';
sel_rup_vref_m_d <= '1';
sel_rup_vref_l_d <= '0';
sel_rdn_vref_h_d <= '0';
sel_rdn_vref_m_d <= '1';
sel_rdn_vref_l_d <= '0';
WHEN STRATIXIII_RTOCT_DONE =>
next_state <= STRATIXIII_RTOCT_DONE;
rt_sm_done_d <= '1';
WHEN OTHERS =>
next_state <= STRATIXIII_RTOCT_WAIT;
END CASE;
-- case(current_state)
-- schedule the outputs
p_cnt_d <= p_cnt_d_var;
n_cnt_d <= n_cnt_d_var;
p_cnt_sub_d <= p_cnt_sub_d_var;
n_cnt_sub_d <= n_cnt_sub_d_var;
END PROCESS;
END stratixiii_rt_sm_rtl;
-------------------------------------------------------------------------------
-- Module Name: stratixiii_termination_aux_clock_div
-- Description: auxilary clock divider module
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY stratixiii_termination_aux_clock_div IS
GENERIC (
clk_divide_by : INTEGER := 1;
extra_latency : INTEGER := 0
);
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC := '0';
clkout : OUT STD_LOGIC
);
END stratixiii_termination_aux_clock_div;
ARCHITECTURE oct_clock_div_arch OF stratixiii_termination_aux_clock_div IS
SIGNAL clk_edges : INTEGER := -1;
SIGNAL div_n_register : STD_LOGIC_VECTOR(2 * extra_latency DOWNTO 0)
:= (OTHERS => '0');
BEGIN
PROCESS(clk,reset)
VARIABLE div_n : STD_LOGIC_VECTOR(2 * extra_latency DOWNTO 0) := (OTHERS => '0');
VARIABLE m : INTEGER := 0;
VARIABLE running_clk_edge : INTEGER := -1;
BEGIN
running_clk_edge := clk_edges;
IF (reset = '1') THEN
clk_edges <= -1;
m := 0;
div_n := (OTHERS => '0');
ELSE
IF (clk'EVENT) THEN
IF (running_clk_edge = -1) THEN
m := 0;
div_n(0) := clk;
IF (clk = '1') THEN running_clk_edge := 0; END IF;
ELSIF (running_clk_edge mod clk_divide_by = 0) THEN
div_n(0) := NOT div_n(0);
END IF;
IF (running_clk_edge >= 0 OR clk = '1') THEN
clk_edges <= (running_clk_edge + 1) mod (2 * clk_divide_by);
END IF;
END IF;
END IF;
m := 0;
div_n_register(m) <= div_n(m);
WHILE (m < 2 * extra_latency) LOOP
div_n_register(m+1) <= div_n_register(m);
m := m + 1;
END LOOP;
END PROCESS;
clkout <= div_n_register(2 * extra_latency);
END oct_clock_div_arch;
-------------------------------------------------------------------------------
--
-- Module Name : stratixiii_termination
--
-- Description : Stratix III Termination Atom
-- Verilog simulation model
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.ALL;
USE IEEE.VITAL_Primitives.ALL;
use work.stratixiii_atom_pack.all;
USE WORK.stratixiii_termination_aux_clock_div;
USE WORK.stratixiii_rt_sm;
ENTITY stratixiii_termination IS
GENERIC (
runtime_control : STRING := "false";
allow_serial_data_from_core : STRING := "false";
power_down : STRING := "true";
enable_parallel_termination : STRING := "false";
test_mode : STRING := "false";
enable_calclk_divider : STRING := "false"; -- replaced by below
clock_divider_enable : STRING := "false";
enable_pwrupmode_enser_for_usrmode : STRING := "false";
bypass_enser_logic : STRING := "false";
bypass_rt_calclk : STRING := "false";
enable_rt_scan_mode : STRING := "false";
enable_loopback : STRING := "false";
force_rtcalen_for_pllbiasen : STRING := "false";
enable_rt_sm_loopback : STRING := "false";
select_vrefl_values : integer := 0;
select_vrefh_values : integer := 0;
divide_intosc_by : integer := 2;
use_usrmode_clear_for_configmode : STRING := "false";
tipd_rup : VitalDelayType01 := DefpropDelay01;
tipd_rdn : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationclear : VitalDelayType01 := DefpropDelay01;
tipd_terminationenable : VitalDelayType01 := DefpropDelay01;
tipd_serializerenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationcontrolin : VitalDelayType01 := DefpropDelay01;
tipd_otherserializerenable : VitalDelayArrayType01(8 downto 0) := (OTHERS => DefPropDelay01);
lpm_type : STRING := "stratixiii_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
terminationenable : IN std_logic := '1';
serializerenable : IN std_logic := '0';
terminationcontrolin : IN std_logic := '0';
scanin : IN std_logic := '0';
scanen : IN std_logic := '0';
otherserializerenable : IN std_logic_vector(8 DOWNTO 0) := (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
incrup : OUT std_logic;
incrdn : OUT std_logic;
serializerenableout : OUT std_logic;
terminationcontrol : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
scanout : OUT std_logic;
shiftregisterprobe : OUT std_logic);
END stratixiii_termination;
ARCHITECTURE stratixiii_oct_arch OF stratixiii_termination IS
COMPONENT stratixiii_termination_aux_clock_div
GENERIC (
clk_divide_by : INTEGER := 1;
extra_latency : INTEGER := 0
);
PORT (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC := '0';
clkout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT stratixiii_rt_sm
PORT (
rup : IN std_logic;
rdn : IN std_logic;
clk : IN std_logic;
clken : IN std_logic;
clr : IN std_logic;
rtena : IN std_logic;
rscaldone : IN std_logic;
rtoffsetp : OUT std_logic_vector(3 DOWNTO 0);
rtoffsetn : OUT std_logic_vector(3 DOWNTO 0);
caldone : OUT std_logic;
sel_rup_vref : OUT std_logic_vector(2 DOWNTO 0);
sel_rdn_vref : OUT std_logic_vector(2 DOWNTO 0)
);
END COMPONENT;
-- HW outputs
SIGNAL compout_rup_core : std_logic;
SIGNAL compout_rdn_core : std_logic;
SIGNAL ser_data_io : std_logic;
SIGNAL ser_data_core : std_logic;
-- HW inputs
SIGNAL usr_clk : std_logic;
SIGNAL cal_clk : std_logic;
SIGNAL rscal_clk : std_logic;
SIGNAL cal_clken : std_logic;
SIGNAL cal_nclr : std_logic;
-- legality check on enser
SIGNAL enser_checked : std_logic := '0';
-- Shift Register
SIGNAL sreg_bit_out : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL sreg_bit_out_tmp0 : std_logic := '0';
SIGNAL sreg_vshift_bit_tmp : std_logic := '0';
SIGNAL sreg_vshift_bit_out : std_logic := '0';
SIGNAL sreg_rscaldone_prev : std_logic := '0';
SIGNAL sreg_rscaldone_prev1 : std_logic := '0';
SIGNAL sregn_rscaldone_out : std_logic := '0';
SIGNAL sreg_bit6_prev : std_logic := '1';
-- nreg before SA-ADC
SIGNAL regn_rup_in : std_logic;
SIGNAL regn_rdn_in : std_logic;
SIGNAL regn_compout_rup : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL regn_compout_rdn : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
-- SA-ADC
SIGNAL sa_octcaln_out : std_logic_vector(6 DOWNTO 0); -- RUP - NMOS
SIGNAL sa_octcalp_out : std_logic_vector(6 DOWNTO 0); -- RDN - PMOS
SIGNAL sa_octcaln_in : std_logic_vector(6 DOWNTO 0);
SIGNAL sa_octcalp_in : std_logic_vector(6 DOWNTO 0);
-- ENSER
SIGNAL enser_out : std_logic;
SIGNAL enser_gen_out : std_logic;
SIGNAL enser_cnt : INTEGER := 0;
-- RT State Machine
SIGNAL rtsm_rup_in : std_logic;
SIGNAL rtsm_rdn_in : std_logic;
SIGNAL rtsm_rtena_in : std_logic;
SIGNAL rtsm_rscaldone_in : std_logic;
SIGNAL rtsm_caldone_out : std_logic;
SIGNAL rtsm_rtoffsetp_out : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtsm_rtoffsetn_out : std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtsm_sel_rup_vref_out : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtsm_sel_rdn_vref_out : std_logic_vector(2 DOWNTO 0) := (OTHERS => '0');
-- RT Adder/Sub
SIGNAL rtas_rs_rpcdp_in : std_logic_vector(6 DOWNTO 0);
SIGNAL rtas_rs_rpcdn_in : std_logic_vector(6 DOWNTO 0);
SIGNAL rtas_rtoffsetp_in : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtas_rtoffsetn_in : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtas_rs_rpcdp_out : std_logic_vector(6 DOWNTO 0);
SIGNAL rtas_rs_rpcdn_out : std_logic_vector(6 DOWNTO 0);
SIGNAL rtas_rt_rpcdp_out : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
SIGNAL rtas_rt_rpcdn_out : std_logic_vector(6 DOWNTO 0) := (OTHERS => '0');
-- P2S
SIGNAL p2s_rs_rpcdp_in : std_logic_vector(6 DOWNTO 0);
SIGNAL p2s_rs_rpcdn_in : std_logic_vector(6 DOWNTO 0);
SIGNAL p2s_rt_rpcdp_in : std_logic_vector(6 DOWNTO 0);
SIGNAL p2s_rt_rpcdn_in : std_logic_vector(6 DOWNTO 0);
SIGNAL p2s_enser_in : std_logic;
SIGNAL p2s_clk_in : std_logic;
SIGNAL p2s_ser_data_out : std_logic;
SIGNAL p2s_parallel_reg : std_logic_vector(27 DOWNTO 0) := (OTHERS => '0');
SIGNAL p2s_serial_reg : std_logic := '0';
SIGNAL p2s_index : integer := 27;
-- used to set SA outputs
SIGNAL temp_xhdl10 : std_logic;
SIGNAL temp_xhdl12 : std_logic;
SIGNAL temp_xhdl14 : std_logic;
SIGNAL temp_xhdl16 : std_logic;
SIGNAL temp_xhdl18 : std_logic;
SIGNAL temp_xhdl20 : std_logic;
SIGNAL temp_xhdl22 : std_logic;
SIGNAL temp_xhdl24 : std_logic;
SIGNAL temp_xhdl26 : std_logic;
SIGNAL temp_xhdl28 : std_logic;
SIGNAL temp_xhdl30 : std_logic;
SIGNAL temp_xhdl32 : std_logic;
SIGNAL temp_xhdl34 : std_logic;
SIGNAL temp_xhdl36 : std_logic;
SIGNAL MY_GND : std_logic := '0';
-- timing
SIGNAL rup_ipd : std_logic;
SIGNAL rdn_ipd : std_logic;
SIGNAL terminationclock_ipd : std_logic;
SIGNAL terminationclear_ipd : std_logic;
SIGNAL terminationenable_ipd : std_logic;
SIGNAL serializerenable_ipd : std_logic;
SIGNAL terminationcontrolin_ipd : std_logic;
SIGNAL otherserializerenable_ipd : std_logic_vector(8 DOWNTO 0);
BEGIN
-- primary outputs
incrup <= terminationenable_ipd WHEN (enable_loopback = "true") ELSE compout_rup_core;
incrdn <= terminationclear_ipd WHEN (enable_loopback = "true") ELSE compout_rdn_core;
terminationcontrol <= ser_data_io;
terminationcontrolprobe <= serializerenable_ipd WHEN (enable_loopback = "true") ELSE ser_data_core;
shiftregisterprobe <= terminationclock_ipd WHEN (enable_loopback = "true") ELSE sreg_vshift_bit_out;
serializerenableout <= serializerenable;
compout_rup_core <= rup ;
compout_rdn_core <= rdn ;
ser_data_io <= terminationcontrolin WHEN (allow_serial_data_from_core = "true") ELSE p2s_ser_data_out;
ser_data_core <= p2s_ser_data_out ;
-- primary inputs
usr_clk <= terminationclock ;
cal_nclr <= '1' WHEN (terminationclear = '1') ELSE '0';
cal_clken <= '1' WHEN (terminationenable = '1' AND serializerenable = '1') ELSE '0';
-- divide by 100 clock
m_gen_calclk : stratixiii_termination_aux_clock_div
GENERIC MAP (
clk_divide_by => 100,
extra_latency => 0)
PORT MAP (
clk => usr_clk,
reset => MY_GND,
clkout => cal_clk);
rscal_clk <= cal_clk AND (NOT sregn_rscaldone_out) ;
-- legality check on enser
PROCESS
BEGIN
WAIT UNTIL (usr_clk'EVENT AND usr_clk = '1');
IF (serializerenable = '1' AND cal_clken = '0') THEN
IF (otherserializerenable(0) = '1' OR
otherserializerenable(1) = '1' OR
otherserializerenable(2) = '1' OR
otherserializerenable(3) = '1' OR
otherserializerenable(4) = '1' OR
otherserializerenable(5) = '1' OR
otherserializerenable(6) = '1' OR
otherserializerenable(7) = '1' OR
otherserializerenable(8) = '1') THEN
IF (enser_checked = '0') THEN
assert false
report "serializizerable and some bits of otherserializerenable are asserted at data transfer time"
severity warning;
enser_checked <= '1';
END IF;
ELSE
enser_checked <= '0'; -- for another check
END IF;
ELSE
enser_checked <= '0'; -- for another check
END IF;
END PROCESS;
-- SHIFT regiter
PROCESS
BEGIN
WAIT UNTIL (rscal_clk'EVENT AND rscal_clk = '1') OR (cal_nclr'EVENT AND cal_nclr = '1');
IF (cal_nclr = '1') THEN
sreg_bit6_prev <= '1';
sreg_bit_out <= "0000000";
sreg_vshift_bit_out <= '0';
sreg_vshift_bit_tmp <= '0';
sreg_bit_out_tmp0 <= '0';
sreg_rscaldone_prev <= '0';
sreg_rscaldone_prev1 <= '0';
ELSE
IF (cal_clken = '1') THEN
sreg_bit_out(6) <= sreg_bit6_prev;
sreg_bit_out(5) <= sreg_bit_out(6);
sreg_bit_out(4) <= sreg_bit_out(5);
sreg_bit_out(3) <= sreg_bit_out(4);
sreg_bit_out(2) <= sreg_bit_out(3);
sreg_bit_out(1) <= sreg_bit_out(2);
sreg_bit_out_tmp0 <= sreg_bit_out(1);
sreg_vshift_bit_tmp <= sreg_bit_out_tmp0;
sreg_bit_out(0) <= sreg_bit_out(1) OR sreg_vshift_bit_tmp;
sreg_vshift_bit_out <= sreg_bit_out_tmp0 OR sreg_vshift_bit_tmp;
sreg_bit6_prev <= '0';
END IF;
END IF;
-- might falling outside of 10 cycles
IF (sreg_vshift_bit_tmp = '1') THEN
sreg_rscaldone_prev <= '1';
END IF;
sreg_rscaldone_prev1 <= sreg_rscaldone_prev;
END PROCESS;
PROCESS
BEGIN
WAIT UNTIL (rscal_clk'EVENT AND rscal_clk = '0') OR (cal_nclr'EVENT AND cal_nclr = '1');
IF (cal_nclr = '1') THEN
sregn_rscaldone_out <= '0';
ELSE -- if (cal_clken == 1'b1) - outside of 10 cycles
IF (sreg_rscaldone_prev1 = '1' AND sregn_rscaldone_out = '0') THEN
sregn_rscaldone_out <= '1';
END IF;
END IF;
END PROCESS;
-- nreg and SA-ADC:
--
-- RDN_vol < ref_voltage < RUP_voltage
-- after reset, ref_voltage=VCCN/2; after ref_voltage_shift, ref_voltage=neighbor(VCCN/2)
-- at 0 code, RUP=VCCN so voltage_compare_out for RUP = 0
-- RDN=GND so voltage compare out for RDN = 0
regn_rup_in <= rup ;
regn_rdn_in <= rdn ;
PROCESS
BEGIN
WAIT UNTIL (cal_nclr'EVENT AND cal_nclr = '1') OR (rscal_clk'EVENT AND rscal_clk = '0');
IF (cal_nclr = '1') THEN
regn_compout_rup <= "0000000";
regn_compout_rdn <= "0000000";
ELSE
-- rup
IF (sreg_bit_out(0) = '1') THEN
regn_compout_rup(0) <= regn_rup_in;
END IF;
IF (sreg_bit_out(1) = '1') THEN
regn_compout_rup(1) <= regn_rup_in;
END IF;
IF (sreg_bit_out(2) = '1') THEN
regn_compout_rup(2) <= regn_rup_in;
END IF;
IF (sreg_bit_out(3) = '1') THEN
regn_compout_rup(3) <= regn_rup_in;
END IF;
IF (sreg_bit_out(4) = '1') THEN
regn_compout_rup(4) <= regn_rup_in;
END IF;
IF (sreg_bit_out(5) = '1') THEN
regn_compout_rup(5) <= regn_rup_in;
END IF;
IF (sreg_bit_out(6) = '1') THEN
regn_compout_rup(6) <= regn_rup_in;
END IF;
-- rdn
IF (sreg_bit_out(0) = '1') THEN
regn_compout_rdn(0) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(1) = '1') THEN
regn_compout_rdn(1) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(2) = '1') THEN
regn_compout_rdn(2) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(3) = '1') THEN
regn_compout_rdn(3) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(4) = '1') THEN
regn_compout_rdn(4) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(5) = '1') THEN
regn_compout_rdn(5) <= regn_rdn_in;
END IF;
IF (sreg_bit_out(6) = '1') THEN
regn_compout_rdn(6) <= regn_rdn_in;
END IF;
END IF;
END PROCESS;
sa_octcaln_in <= sreg_bit_out ;
sa_octcalp_in <= sreg_bit_out ;
-- RUP - octcaln_in == 1 = (pin_voltage < ref_voltage): clear the bit setting
temp_xhdl10 <= '1' WHEN (sa_octcaln_in(0) = '1') ELSE sa_octcaln_out(0);
sa_octcaln_out(0) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(0) = '1') ELSE temp_xhdl10;
temp_xhdl12 <= '1' WHEN (sa_octcaln_in(1) = '1') ELSE sa_octcaln_out(1);
sa_octcaln_out(1) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(1) = '1') ELSE temp_xhdl12;
temp_xhdl14 <= '1' WHEN (sa_octcaln_in(2) = '1') ELSE sa_octcaln_out(2);
sa_octcaln_out(2) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(2) = '1') ELSE temp_xhdl14;
temp_xhdl16 <= '1' WHEN (sa_octcaln_in(3) = '1') ELSE sa_octcaln_out(3);
sa_octcaln_out(3) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(3) = '1') ELSE temp_xhdl16;
temp_xhdl18 <= '1' WHEN (sa_octcaln_in(4) = '1') ELSE sa_octcaln_out(4);
sa_octcaln_out(4) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(4) = '1') ELSE temp_xhdl18;
temp_xhdl20 <= '1' WHEN (sa_octcaln_in(5) = '1') ELSE sa_octcaln_out(5);
sa_octcaln_out(5) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(5) = '1') ELSE temp_xhdl20;
temp_xhdl22 <= '1' WHEN (sa_octcaln_in(6) = '1') ELSE sa_octcaln_out(6);
sa_octcaln_out(6) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rup(6) = '1') ELSE temp_xhdl22;
temp_xhdl24 <= '1' WHEN (sa_octcalp_in(0) = '1') ELSE sa_octcalp_out(0);
sa_octcalp_out(0) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(0) = '1') ELSE temp_xhdl24;
temp_xhdl26 <= '1' WHEN (sa_octcalp_in(1) = '1') ELSE sa_octcalp_out(1);
sa_octcalp_out(1) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(1) = '1') ELSE temp_xhdl26;
temp_xhdl28 <= '1' WHEN (sa_octcalp_in(2) = '1') ELSE sa_octcalp_out(2);
sa_octcalp_out(2) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(2) = '1') ELSE temp_xhdl28;
temp_xhdl30 <= '1' WHEN (sa_octcalp_in(3) = '1') ELSE sa_octcalp_out(3);
sa_octcalp_out(3) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(3) = '1') ELSE temp_xhdl30;
temp_xhdl32 <= '1' WHEN (sa_octcalp_in(4) = '1') ELSE sa_octcalp_out(4);
sa_octcalp_out(4) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(4) = '1') ELSE temp_xhdl32;
temp_xhdl34 <= '1' WHEN (sa_octcalp_in(5) = '1') ELSE sa_octcalp_out(5);
sa_octcalp_out(5) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(5) = '1') ELSE temp_xhdl34;
temp_xhdl36 <= '1' WHEN (sa_octcalp_in(6) = '1') ELSE sa_octcalp_out(6);
sa_octcalp_out(6) <= '0' WHEN (cal_nclr = '1' OR regn_compout_rdn(6) = '1') ELSE temp_xhdl36;
-- ENSER
enser_out <= serializerenable WHEN (runtime_control = "true" OR bypass_enser_logic = "true") ELSE enser_gen_out;
enser_gen_out <= '1' WHEN (enser_cnt > 0 AND enser_cnt < 31) ELSE '0';
PROCESS
BEGIN
WAIT UNTIL (usr_clk'EVENT AND usr_clk = '1') OR (sregn_rscaldone_out'EVENT AND sregn_rscaldone_out = '1');
IF (sregn_rscaldone_out = '0') THEN
enser_cnt <= 0;
ELSE
IF (enser_cnt < 63) THEN
enser_cnt <= enser_cnt + 1;
END IF;
END IF;
END PROCESS;
-- RT SM
rtsm_rup_in <= rup ;
rtsm_rdn_in <= rdn ;
rtsm_rtena_in <= '1' WHEN (enable_parallel_termination = "true") ELSE '0';
rtsm_rscaldone_in <= sregn_rscaldone_out ;
m_rt_sm : stratixiii_rt_sm
PORT MAP (
rup => rtsm_rup_in,
rdn => rtsm_rdn_in,
clk => cal_clk,
clken => cal_clken,
clr => cal_nclr,
rtena => rtsm_rtena_in,
rscaldone => rtsm_rscaldone_in,
rtoffsetp => rtsm_rtoffsetp_out,
rtoffsetn => rtsm_rtoffsetn_out,
caldone => rtsm_caldone_out,
sel_rup_vref => rtsm_sel_rup_vref_out,
sel_rdn_vref => rtsm_sel_rdn_vref_out
);
-- RT Adder/Sub
rtas_rs_rpcdp_in <= sa_octcalp_out ;
rtas_rs_rpcdn_in <= sa_octcaln_out ;
rtas_rtoffsetp_in <= "0000" & rtsm_rtoffsetp_out(2 DOWNTO 0);
rtas_rtoffsetn_in <="0000" & rtsm_rtoffsetn_out(2 DOWNTO 0);
rtas_rs_rpcdp_out <= rtas_rs_rpcdp_in ;
rtas_rs_rpcdn_out <= rtas_rs_rpcdn_in ;
rtas_rt_rpcdn_out <= (rtas_rs_rpcdn_in + rtas_rtoffsetn_in) WHEN (rtsm_rtoffsetn_out(3) = '0') ELSE
(rtas_rs_rpcdn_in - rtas_rtoffsetn_in);
rtas_rt_rpcdp_out <= (rtas_rs_rpcdp_in + rtas_rtoffsetp_in) WHEN (rtsm_rtoffsetp_out(3) = '0') ELSE
(rtas_rs_rpcdp_in - rtas_rtoffsetp_in);
-- P2S
p2s_rs_rpcdp_in <= rtas_rs_rpcdp_out ;
p2s_rs_rpcdn_in <= rtas_rs_rpcdn_out ;
p2s_rt_rpcdp_in <= rtas_rt_rpcdp_out;
p2s_rt_rpcdn_in <= rtas_rt_rpcdn_out;
p2s_enser_in <= enser_out ;
p2s_clk_in <= usr_clk ;
p2s_ser_data_out <= p2s_serial_reg ;
-- load - clken
PROCESS
BEGIN
WAIT UNTIL (p2s_clk_in'EVENT AND p2s_clk_in = '1') OR (cal_nclr'EVENT AND cal_nclr = '1');
IF (cal_nclr = '1') THEN
p2s_parallel_reg <= "0000000000000000000000000000";
ELSE
IF (cal_clken = '1') THEN
p2s_parallel_reg <= p2s_rs_rpcdp_in & p2s_rs_rpcdn_in & p2s_rt_rpcdp_in & p2s_rt_rpcdn_in;
END IF;
END IF;
END PROCESS;
-- shift - enser
PROCESS
BEGIN
WAIT UNTIL (p2s_clk_in'EVENT AND p2s_clk_in = '1') OR (cal_nclr'EVENT AND cal_nclr = '1');
IF (cal_nclr = '1') THEN
p2s_serial_reg <= '0';
p2s_index <= 27;
ELSE
IF (p2s_enser_in = '1' AND cal_clken = '0') THEN
p2s_serial_reg <= p2s_parallel_reg(p2s_index);
IF (p2s_index > 0) THEN
p2s_index <= p2s_index - 1;
END IF;
END IF;
END IF;
END PROCESS;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (rup_ipd, rup, tipd_rup);
VitalWireDelay (rdn_ipd, rdn, tipd_rdn);
VitalWireDelay (terminationclock_ipd, terminationclock, tipd_terminationclock);
VitalWireDelay (terminationclear_ipd, terminationclear, tipd_terminationclear);
VitalWireDelay (terminationenable_ipd, terminationenable, tipd_terminationenable);
VitalWireDelay (serializerenable_ipd, serializerenable, tipd_serializerenable);
VitalWireDelay (terminationcontrolin_ipd, terminationcontrolin, tipd_terminationcontrolin);
VitalWireDelay (otherserializerenable_ipd(0), otherserializerenable(0), tipd_otherserializerenable(0));
VitalWireDelay (otherserializerenable_ipd(1), otherserializerenable(1), tipd_otherserializerenable(1));
VitalWireDelay (otherserializerenable_ipd(2), otherserializerenable(2), tipd_otherserializerenable(2));
VitalWireDelay (otherserializerenable_ipd(3), otherserializerenable(3), tipd_otherserializerenable(3));
VitalWireDelay (otherserializerenable_ipd(4), otherserializerenable(4), tipd_otherserializerenable(4));
VitalWireDelay (otherserializerenable_ipd(5), otherserializerenable(5), tipd_otherserializerenable(5));
VitalWireDelay (otherserializerenable_ipd(6), otherserializerenable(6), tipd_otherserializerenable(6));
VitalWireDelay (otherserializerenable_ipd(7), otherserializerenable(7), tipd_otherserializerenable(7));
VitalWireDelay (otherserializerenable_ipd(8), otherserializerenable(8), tipd_otherserializerenable(8));
end block;
END stratixiii_oct_arch;
-------------------------------------------------------------------------------
--
-- Module Name : stratixiii_termination_logic
--
-- Description : Stratix III Termination Logic Atom
-- Verilog simulation model
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.VITAL_Timing.ALL;
USE IEEE.VITAL_Primitives.ALL;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_termination_logic IS
GENERIC (
tipd_serialloadenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_parallelloadenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationdata : VitalDelayType01 := DefpropDelay01;
test_mode : string := "false";
lpm_type : string := "stratixiii_termination_logic");
PORT (
serialloadenable : IN std_logic := '0';
terminationclock : IN std_logic := '0';
parallelloadenable : IN std_logic := '0';
terminationdata : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
seriesterminationcontrol : OUT std_logic_vector(13 DOWNTO 0);
parallelterminationcontrol : OUT std_logic_vector(13 DOWNTO 0));
END stratixiii_termination_logic;
ARCHITECTURE stratixiii_oct_logic_arch OF stratixiii_termination_logic IS
CONSTANT xhdl_timescale : time := 1 ps;
SIGNAL usr_clk : std_logic;
SIGNAL rs_reg : std_logic_vector(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL rt_reg : std_logic_vector(13 DOWNTO 0) := (OTHERS => '0');
SIGNAL hold_reg : std_logic_vector(27 DOWNTO 0) := (OTHERS => '0');
SIGNAL shift_index : integer := 27;
-- timing
SIGNAL serialloadenable_ipd : std_logic;
SIGNAL terminationclock_ipd : std_logic;
SIGNAL parallelloadenable_ipd : std_logic;
SIGNAL terminationdata_ipd : std_logic;
BEGIN
seriesterminationcontrol <= rs_reg;
parallelterminationcontrol <= rt_reg;
usr_clk <= terminationclock AFTER 11 * xhdl_timescale;
PROCESS
BEGIN
WAIT UNTIL (usr_clk'EVENT AND usr_clk = '1');
IF (serialloadenable = '0') THEN
shift_index <= 27;
ELSE
hold_reg(shift_index) <= terminationdata;
IF (shift_index > 0) THEN
shift_index <= shift_index - 1;
END IF;
END IF;
END PROCESS;
PROCESS
BEGIN
WAIT UNTIL (parallelloadenable'EVENT AND parallelloadenable = '1');
IF (parallelloadenable = '1') THEN
rs_reg <= hold_reg(27 DOWNTO 14);
rt_reg <= hold_reg(13 DOWNTO 0);
END IF;
END PROCESS;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (serialloadenable_ipd, serialloadenable, tipd_serialloadenable);
VitalWireDelay (terminationclock_ipd, terminationclock, tipd_terminationclock);
VitalWireDelay (parallelloadenable_ipd, parallelloadenable, tipd_parallelloadenable);
VitalWireDelay (terminationdata_ipd, terminationdata, tipd_terminationdata);
end block;
END stratixiii_oct_logic_arch;
-------------------------------------------------------------------------------
-- utilities common for ddr
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package stratixiii_atom_ddr_pack is
function dll_unsigned2bin (in_int : integer) return std_logic_vector;
end stratixiii_atom_ddr_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body stratixiii_atom_ddr_pack is
-- truncate input integer to get 6 LSB bits
function dll_unsigned2bin (in_int : integer) return std_logic_vector is
variable tmp_int, i : integer;
variable tmp_bit : integer;
variable result : std_logic_vector(5 downto 0) := "000000";
begin
tmp_int := in_int;
for i in 0 to 5 loop
tmp_bit := tmp_int MOD 2;
if (tmp_bit = 1) then
result(i) := '1';
else
result(i) := '0';
end if;
tmp_int := tmp_int/2;
end loop;
return result;
end dll_unsigned2bin;
end stratixiii_atom_ddr_pack;
-------------------------------------------------------------------------------
-- auxilary module for ddr
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY stratixiii_dll_gray_encoder IS
GENERIC ( width : integer := 6 );
PORT ( mbin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
gout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END stratixiii_dll_gray_encoder;
ARCHITECTURE stratixiii_dll_gray_encoder_arch OF stratixiii_dll_gray_encoder IS
SIGNAL greg : STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
gout <= greg;
PROCESS(mbin)
VARIABLE i : INTEGER := 0;
BEGIN
greg(width-1) <= mbin(width-1);
IF (width > 1) THEN
i := width - 2;
WHILE (i >= 0) LOOP
greg(i) <= mbin(i+1) XOR mbin(i);
i := i - 1;
END LOOP;
END IF;
END PROCESS;
END stratixiii_dll_gray_encoder_arch;
-------------------------------------------------------------------------------
-- auxilary module for ddr
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY stratixiii_dll_gray_decoder IS
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END stratixiii_dll_gray_decoder;
ARCHITECTURE stratixiii_dll_gray_decoder_arch OF stratixiii_dll_gray_decoder IS
SIGNAL breg : STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
bout <= breg;
PROCESS(gin)
VARIABLE i : INTEGER := 0;
VARIABLE bvar : STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
bvar(width-1) := gin(width-1);
IF (width > 1) THEN
i := width - 2;
WHILE (i >= 0) LOOP
bvar(i) := bvar(i+1) XOR gin(i);
i := i - 1;
END LOOP;
END IF;
breg <= bvar;
END PROCESS;
END stratixiii_dll_gray_decoder_arch;
-------------------------------------------------------------------------------
-- Module Name: stratixiii_ddr_delay_chain_s
-- Description: auxilary module - delay chain-setting
-------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_dll_gray_decoder;
ENTITY stratixiii_ddr_delay_chain_s IS
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END stratixiii_ddr_delay_chain_s;
ARCHITECTURE stratixiii_ddr_delay_chain_s_arch OF stratixiii_ddr_delay_chain_s IS
COMPONENT stratixiii_dll_gray_decoder
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
SIGNAL clk_delay : INTEGER := 0;
SIGNAL delayed_clk : STD_LOGIC := '0';
SIGNAL delayctrl_bin : STD_LOGIC_VECTOR (5 DOWNTO 0) := (OTHERS => '0');
SIGNAL delayctrlin_in : STD_LOGIC_VECTOR (5 DOWNTO 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
BEGIN
delayctrlin_in(0) <= '1' WHEN (delayctrlin(0) = '1') ELSE '0';
delayctrlin_in(1) <= '1' WHEN (delayctrlin(1) = '1') ELSE '0';
delayctrlin_in(2) <= '1' WHEN (delayctrlin(2) = '1') ELSE '0';
delayctrlin_in(3) <= '1' WHEN (delayctrlin(3) = '1') ELSE '0';
delayctrlin_in(4) <= '1' WHEN (delayctrlin(4) = '1') ELSE '0';
delayctrlin_in(5) <= '1' WHEN (delayctrlin(5) = '1') ELSE '0';
phasectrlin_in(0) <= '1' WHEN (phasectrlin(0) = '1') ELSE '0';
phasectrlin_in(1) <= '1' WHEN (phasectrlin(1) = '1') ELSE '0';
phasectrlin_in(2) <= '1' WHEN (phasectrlin(2) = '1') ELSE '0';
phasectrlin_in(3) <= '1' WHEN (phasectrlin(3) = '1') ELSE '0';
-- decoder
mdr_delayctrl_in_dec : stratixiii_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => delayctrlin_in, bout => delayctrl_bin);
PROCESS(delayctrl_bin, phasectrlin_in)
variable sim_intrinsic_delay : INTEGER := 0;
variable acell_delay : INTEGER := 0;
variable delay_chain_len : INTEGER := 0;
BEGIN
IF (delay_buffer_mode = "low") THEN
sim_intrinsic_delay := sim_low_buffer_intrinsic_delay;
ELSE
sim_intrinsic_delay := sim_high_buffer_intrinsic_delay;
END IF;
-- cell
acell_delay := sim_intrinsic_delay + alt_conv_integer(delayctrl_bin) * sim_buffer_delay_increment;
-- no of cells
IF (use_phasectrlin = "false") THEN
delay_chain_len := phase_setting;
ELSIF (alt_conv_integer(phasectrlin_in) > phasectrlin_limit) THEN
delay_chain_len := 0;
ELSE
delay_chain_len := alt_conv_integer(phasectrlin_in);
END IF;
-- total delay - added extra 1 ps for resolving racing
clk_delay <= delay_chain_len * acell_delay + 1;
IF ((use_phasectrlin = "true") AND (alt_conv_integer(phasectrlin_in) > phasectrlin_limit)) THEN
assert false report "Warning: DDR phasesetting has invalid phasectrlin setting" severity warning;
END IF;
END PROCESS; -- generating delays
delayed_clk <= transport clk after (clk_delay * 1 ps);
delayed_clkout <= delayed_clk;
END stratixiii_ddr_delay_chain_s_arch;
-------------------------------------------------------------------------------
-- based on dffeas
-------------------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_ddr_io_reg is
generic(
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port(
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of stratixiii_ddr_io_reg : entity is TRUE;
end stratixiii_ddr_io_reg;
architecture vital_titan_ddr_io_reg of stratixiii_ddr_io_reg is
attribute VITAL_LEVEL0 of vital_titan_ddr_io_reg : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal prn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
begin
d_dly <= d_ipd;
asdata_dly <= asdata_ipd;
asdata_dly1 <= asdata_dly;
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (prn_ipd, prn, tipd_prn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process ( clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, prn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if ((power_up = "low") or (power_up = "DONT_CARE")) then
iq := '0';
elsif (power_up = "high") then
iq := '1';
else
iq := '0';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiii_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiii_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiii_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiii_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01( (NOT clrn_ipd) OR
(NOT prn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/stratixiii_ddr_io_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then
iq := '0';
elsif (prn_ipd = '0') then
iq := '1';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly1;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_negedge, TRUE),
1 => (prn_ipd'last_event, tpd_prn_q_negedge, TRUE),
2 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
3 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
4 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_titan_ddr_io_reg;
-------------------------------------------------------------------------------
--
-- Entity Name : Stratix III_dll
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_pllpack.all;
use work.stratixiii_atom_ddr_pack.all;
use work.stratixiii_dll_gray_encoder;
ENTITY stratixiii_dll is
GENERIC (
input_frequency : string := "0 ps";
delay_buffer_mode : string := "low";
delay_chain_length : integer := 12;
delayctrlout_mode : string := "normal";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
dual_phase_comparators : string := "true";
sim_valid_lock : integer := 16;
sim_valid_lockcount : integer := 0; -- 10000 = 1000 + 100*dllcounter
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
static_delay_ctrl : integer := 0;
lpm_type : string := "stratixiii_dll";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_upndnin : VitalDelayType01 := DefpropDelay01;
tipd_upndninclkena : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
upndnin : IN std_logic := '1';
upndninclkena : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
delayctrlout : OUT std_logic_vector(5 DOWNTO 0);
dqsupdate : OUT std_logic;
offsetdelayctrlout : OUT std_logic_vector(5 DOWNTO 0);
offsetdelayctrlclkout : OUT std_logic;
upndnout : OUT std_logic
);
END stratixiii_dll;
ARCHITECTURE vital_titandll of stratixiii_dll is
COMPONENT stratixiii_dll_gray_encoder
GENERIC ( width : integer := 6 );
PORT ( mbin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
gout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
signal clk_in : std_logic := '0';
signal aload_in_buf : std_logic := '0';
signal upndn_in : std_logic := '0';
signal upndninclkena_in : std_logic := '1';
signal delayctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal offsetdelayctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal upndn_out : std_logic := '0';
signal dqsupdate_out : std_logic := '0';
signal para_delay_buffer_mode : std_logic_vector (1 DOWNTO 0) := "01";
signal para_delayctrlout_mode : std_logic_vector (1 DOWNTO 0) := "00";
signal para_static_delay_ctrl : integer := 0;
signal para_jitter_reduction : std_logic := '0';
signal para_use_upndnin : std_logic := '0';
signal para_use_upndninclkena : std_logic := '1';
-- INTERNAL NETS AND VARIABLES
-- for functionality - by modules
signal sim_buffer_intrinsic_delay : INTEGER := 0;
-- two reg on the de-assertion of dll
SIGNAL aload_in : std_logic := '0';
SIGNAL aload_reg1 : std_logic := '1';
SIGNAL aload_reg2 : std_logic := '1';
-- delay and offset control out resolver
signal dr_delayctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_delayctrl_int : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offsetctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_dllcount_in : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_clk8_in : std_logic := '0';
signal dr_aload_in : std_logic := '0';
signal dr_reg_dllcount : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_delay_ctrl_gray : std_logic_vector (5 DOWNTO 0) := "000000";
-- delay chain setting counter
signal dc_dllcount_out_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal dc_dllcount_out_vec : std_logic_vector (5 DOWNTO 0) := "000000";
signal dc_dllcount_out : integer := 0;
signal dc_dqsupdate_out : std_logic := '0';
signal dc_upndn_in : std_logic := '1';
signal dc_aload_in : std_logic := '0';
signal dc_upndnclkena_in : std_logic := '1';
signal dc_clk8_in : std_logic := '0';
signal dc_clk1_in : std_logic := '0';
signal dc_dlltolock_in : std_logic := '0';
signal dc_reg_dllcount : integer := 0;
signal dc_reg_dlltolock_pulse : std_logic := '0';
-- jitter reduction counter
signal jc_upndn_out : std_logic := '0';
signal jc_upndnclkena_out : std_logic := '1';
signal jc_clk8_in : std_logic := '0';
signal jc_upndn_in : std_logic := '1';
signal jc_aload_in : std_logic := '0';
signal jc_clkena_in : std_logic := '1'; -- new in stratixiii
signal jc_count : integer := 8;
signal jc_reg_upndn : std_logic := '0';
signal jc_reg_upndnclkena : std_logic := '0';
-- phase comparator
signal pc_lock : std_logic := '0'; -- new in stratixiii
signal pc_upndn_out : std_logic := '1';
signal pc_dllcount_in : integer := 0;
signal pc_clk1_in : std_logic := '0';
signal pc_clk8_in : std_logic := '0';
signal pc_aload_in : std_logic := '0';
signal pc_reg_upndn : std_logic := '1';
signal pc_delay : integer := 0;
signal pc_lock_reg : std_logic := '0'; -- new in stratixiii
signal pc_comp_range : integer := 0; -- new in stratixiii
-- clock generator
signal cg_clk_in : std_logic := '0';
signal cg_aload_in : std_logic := '0';
signal cg_clk1_out : std_logic := '0';
signal cg_clk8a_out : std_logic := '0';
signal cg_clk8b_out : std_logic := '0';
-- por: 000
signal cg_reg_1 : std_logic := '0';
signal cg_rega_2 : std_logic := '0';
signal cg_rega_3 : std_logic := '0';
-- por: 010
signal cg_regb_2 : std_logic := '1';
signal cg_regb_3 : std_logic := '0';
-- for violation checks
signal dll_to_lock : std_logic := '0';
signal input_period : integer := 10000;
signal clk_in_last_value : std_logic := 'X';
begin
-- paramters
input_period <= dqs_str2int(input_frequency);
para_static_delay_ctrl <= static_delay_ctrl;
para_use_upndnin <= '1' WHEN use_upndnin = "true" ELSE '0';
para_jitter_reduction <= '1' WHEN jitter_reduction = "true" ELSE '0';
para_use_upndninclkena <= '1' WHEN use_upndninclkena = "true" ELSE '0';
para_delay_buffer_mode <= "00" WHEN delay_buffer_mode = "auto" ELSE "01" WHEN delay_buffer_mode = "low" ELSE "10";
para_delayctrlout_mode <= "01" WHEN delayctrlout_mode = "test" ELSE "10" WHEN delayctrlout_mode="normal" ELSE "11" WHEN delayctrlout_mode="static" ELSE "00";
sim_buffer_intrinsic_delay <= sim_low_buffer_intrinsic_delay WHEN (delay_buffer_mode = "low") ELSE
sim_high_buffer_intrinsic_delay;
-- violation check block
process (clk_in)
variable got_first_rising_edge : std_logic := '0';
variable got_first_falling_edge : std_logic := '0';
variable per_violation : std_logic := '0';
variable duty_violation : std_logic := '0';
variable sent_per_violation : std_logic := '0';
variable sent_duty_violation : std_logic := '0';
variable clk_in_last_rising_edge : time := 0 ps;
variable clk_in_last_falling_edge : time := 0 ps;
variable input_period_ps : time := 10000 ps;
variable duty_cycle : time := 5000 ps;
variable clk_in_period : time := 10000 ps;
variable clk_in_duty_cycle : time := 5000 ps;
variable clk_per_tolerance : time := 2 ps;
variable half_cycles_to_lock : integer := 1;
variable init : boolean := true;
begin
if (init) then
input_period_ps := dqs_str2int(input_frequency) * 1 ps;
if (input_period_ps = 0 ps) then
assert false report "Need to specify ps scale in simulation command" severity error;
end if;
duty_cycle := input_period_ps/2;
clk_per_tolerance := 2 ps;
half_cycles_to_lock := 0;
init := false;
end if;
if (clk_in'event and clk_in = '1') then -- rising edge
if (got_first_rising_edge = '0') then
got_first_rising_edge := '1';
else -- subsequent rising
-- check for clock period and duty cycle violation
clk_in_period := now - clk_in_last_rising_edge;
clk_in_duty_cycle := now - clk_in_last_falling_edge;
if ((clk_in_period < (input_period_ps - clk_per_tolerance)) or (clk_in_period > (input_period_ps + clk_per_tolerance))) then
per_violation := '1';
if (sent_per_violation /= '1') then
sent_per_violation := '1';
assert false report "Input clock frequency violation." severity warning;
end if;
elsif ((clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1 ps)) or (clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1 ps))) then
duty_violation := '1';
if (sent_duty_violation /= '1') then
sent_duty_violation := '1';
assert false report "Input clock duty cycle violation." severity warning;
end if;
else
if (per_violation = '1') then
sent_per_violation := '0';
assert false report "Input clock frequency now matches specified clock frequency." severity warning;
end if;
per_violation := '0';
duty_violation := '0';
end if;
end if;
if (per_violation = '0' and duty_violation = '0' and dll_to_lock = '0') then
half_cycles_to_lock := half_cycles_to_lock + 1;
if (half_cycles_to_lock >= sim_valid_lock) then
dll_to_lock <= '1';
assert false report "DLL to lock to incoming clock" severity note;
end if;
end if;
clk_in_last_rising_edge := now;
elsif (clk_in'event and clk_in = '0') then -- falling edge
got_first_falling_edge := '1';
if (got_first_rising_edge = '1') then
-- duty cycle check
clk_in_duty_cycle := now - clk_in_last_rising_edge;
if ((clk_in_duty_cycle < (duty_cycle - clk_per_tolerance/2 - 1 ps)) or (clk_in_duty_cycle > (duty_cycle + clk_per_tolerance/2 + 1 ps))) then
duty_violation := '1';
if (sent_duty_violation /= '1') then
sent_duty_violation := '1';
assert false report "Input clock duty cycle violation." severity warning;
end if;
else
duty_violation := '0';
end if;
if (dll_to_lock = '0' and duty_violation = '0') then
half_cycles_to_lock := half_cycles_to_lock + 1;
end if;
end if;
clk_in_last_falling_edge := now;
elsif (got_first_falling_edge = '1' or got_first_rising_edge = '1') then
-- switches from 1, 0 to X
half_cycles_to_lock := 0;
got_first_rising_edge := '0';
got_first_falling_edge := '0';
if (dll_to_lock = '1') then
dll_to_lock <= '0';
assert false report "Illegal value detected on input clock. DLL will lose lock." severity warning;
else
assert false report "Illegal value detected on input clock." severity warning;
end if;
end if;
clk_in_last_value <= clk_in;
end process ; -- violation check
-- outputs
delayctrl_out <= dr_delayctrl_out;
offsetdelayctrl_out <= dr_offsetctrl_out;
offsetdelayctrlclkout <= dr_clk8_in;
dqsupdate_out <= cg_clk8a_out;
upndn_out <= pc_upndn_out;
-- two registers on aload path --------------------------------------------
aload_in <= (aload_in_buf OR aload_reg2);
process(clk_in)
begin
if (clk_in = '0' and clk_in'event) then
aload_reg2 <= aload_reg1;
aload_reg1 <= aload_in_buf;
end if;
end process;
-- Delay and offset ctrl out resolver -------------------------------------
-------- convert calculations into integer
-- inputs
dr_clk8_in <= not cg_clk8b_out;
dr_dllcount_in <= dc_dllcount_out_gray;
dr_aload_in <= aload_in;
mdll_count_enc : stratixiii_dll_gray_encoder
GENERIC MAP (width => 6)
PORT MAP (mbin => dc_dllcount_out_vec, gout => dc_dllcount_out_gray);
dc_dllcount_out_vec <= dll_unsigned2bin(dc_dllcount_out);
-- outputs
dr_delayctrl_out <= dr_reg_dllcount;
dr_offsetctrl_out <= dr_delayctrl_int;
-- assumed para_static_delay_ctrl is gray-coded
para_static_delay_ctrl_gray <= dll_unsigned2bin(para_static_delay_ctrl);
dr_delayctrl_int <= para_static_delay_ctrl_gray WHEN (delayctrlout_mode = "static") ELSE
dr_dllcount_in;
-- model
process(dr_clk8_in, dr_aload_in)
begin
if (dr_aload_in = '1' and dr_aload_in'event) then
dr_reg_dllcount <= "000000";
elsif (dr_clk8_in = '1' and dr_clk8_in'event and dr_aload_in /= '1') then
dr_reg_dllcount <= dr_delayctrl_int;
end if;
end process;
-- Delay Setting Control Counter ------------------------------------------
--inputs
dc_dlltolock_in <= dll_to_lock;
dc_aload_in <= aload_in;
dc_clk1_in <= cg_clk1_out;
dc_clk8_in <= not cg_clk8b_out;
dc_upndnclkena_in <= upndninclkena WHEN (para_use_upndninclkena = '1') ELSE
jc_upndnclkena_out WHEN (para_jitter_reduction = '1') ELSE
(not pc_lock) WHEN (dual_phase_comparators = "true") ELSE
'1';
dc_upndn_in <= upndnin WHEN (para_use_upndnin = '1') ELSE
jc_upndn_out WHEN (para_jitter_reduction = '1') ELSE
pc_upndn_out;
-- outputs
dc_dllcount_out <= dc_reg_dllcount; -- needs to turn into gray counter
-- dll counter logic
process(dc_clk8_in, dc_aload_in, dc_dlltolock_in)
variable dc_var_dllcount : integer := 64;
variable init : boolean := true;
begin
if (init) then
if (delay_buffer_mode = "low") then
dc_var_dllcount := 32;
else
dc_var_dllcount := 16;
end if;
init := false;
end if;
if (dc_aload_in = '1' and dc_aload_in'event) then
if (delay_buffer_mode = "low") then
dc_var_dllcount := 32;
else
dc_var_dllcount := 16;
end if;
elsif (dc_aload_in /= '1' and dc_dlltolock_in = '1' and dc_reg_dlltolock_pulse /= '1' and
dc_upndnclkena_in = '1' and para_use_upndnin = '0') then
dc_var_dllcount := sim_valid_lockcount;
dc_reg_dlltolock_pulse <= '1';
elsif (dc_aload_in /= '1' and
dc_upndnclkena_in = '1' and dc_clk8_in'event and dc_clk8_in = '1') then -- posedge clk
if (dc_upndn_in = '1') then
if ((para_delay_buffer_mode = "01" and dc_var_dllcount < 63) or
(para_delay_buffer_mode /= "01" and dc_var_dllcount < 31)) then
dc_var_dllcount := dc_var_dllcount + 1;
end if;
elsif (dc_upndn_in = '0') then
if (dc_var_dllcount > 0) then
dc_var_dllcount := dc_var_dllcount - 1;
end if;
end if;
end if; -- rising clock
-- schedule signal dc_reg_dllcount
dc_reg_dllcount <= dc_var_dllcount;
end process;
-- Jitter reduction counter -----------------------------------------------
-- inputs
jc_clk8_in <= not cg_clk8b_out;
jc_upndn_in <= pc_upndn_out;
jc_aload_in <= aload_in;
-- new in stratixiii
jc_clkena_in <= '1' WHEN (dual_phase_comparators = "false") ELSE (not pc_lock);
-- outputs
jc_upndn_out <= jc_reg_upndn;
jc_upndnclkena_out <= jc_reg_upndnclkena;
-- Model
process (jc_clk8_in, jc_aload_in)
begin
if (jc_aload_in = '1' and jc_aload_in'event) then
jc_count <= 8;
elsif (jc_aload_in /= '1' and jc_clk8_in'event and jc_clk8_in = '1') then
if (jc_clkena_in = '1') then
if (jc_count = 12) then
jc_reg_upndn <= '1';
jc_reg_upndnclkena <= '1';
jc_count <= 8;
elsif (jc_count = 4) then
jc_reg_upndn <= '0';
jc_reg_upndnclkena <= '1';
jc_count <= 8;
else -- increment/decrement counter
jc_reg_upndnclkena <= '0';
if (jc_upndn_in = '1') then
jc_count <= jc_count + 1;
elsif (jc_upndn_in = '0') then
jc_count <= jc_count - 1;
end if;
end if;
else -- not clkena
jc_reg_upndnclkena <= '0';
end if;
end if;
end process;
-- Phase comparator -------------------------------------------------------
-- inputs
pc_clk1_in <= cg_clk1_out;
pc_clk8_in <= cg_clk8b_out; -- positive
pc_dllcount_in <= dc_dllcount_out; -- for phase loop calculation
pc_aload_in <= aload_in;
-- outputs
pc_upndn_out <= pc_reg_upndn;
pc_lock <= pc_lock_reg;
-- parameter used
-- sim_loop_intrinsic_delay, sim_loop_delay_increment
pc_comp_range <= (3*delay_chain_length*sim_buffer_delay_increment)/2;
-- Model
process (pc_clk8_in, pc_aload_in)
variable pc_var_delay : integer := 0;
begin
if (pc_aload_in = '1' and pc_aload_in'event) then
pc_var_delay := 0;
elsif (pc_aload_in /= '1' and pc_clk8_in'event and pc_clk8_in = '1' ) then
pc_var_delay := delay_chain_length * (sim_buffer_intrinsic_delay + sim_buffer_delay_increment * pc_dllcount_in);
pc_delay <= pc_var_delay;
if (dual_phase_comparators = "false") then
if (pc_var_delay > input_period) then
pc_reg_upndn <= '0';
else
pc_reg_upndn <= '1';
end if;
else -- use dual phase
if (pc_var_delay < (input_period - pc_comp_range/2)) then
pc_reg_upndn <= '1';
pc_lock_reg <= '0';
elsif (pc_var_delay <= (input_period + pc_comp_range/2)) then
pc_reg_upndn <= '0';
pc_lock_reg <= '1';
else
pc_reg_upndn <= '0';
pc_lock_reg <= '0';
end if;
end if;
end if;
end process;
-- Clock Generator -------------------------------------------------------
-- inputs
cg_clk_in <= clk_in;
cg_aload_in <= aload_in;
-- outputs
cg_clk8a_out <= cg_rega_3;
cg_clk8b_out <= cg_regb_3;
cg_clk1_out <= '0' WHEN cg_aload_in = '1' ELSE cg_clk_in;
-- Model
process(cg_clk1_out, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_reg_1 <= '0';
elsif (cg_aload_in /= '1' and cg_clk1_out = '1' and cg_clk1_out'event) then
cg_reg_1 <= not cg_reg_1;
end if;
end process;
process(cg_reg_1, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_rega_2 <= '0';
cg_regb_2 <= '1';
elsif (cg_aload_in /= '1' and cg_reg_1 = '1' and cg_reg_1'event) then
cg_rega_2 <= not cg_rega_2;
cg_regb_2 <= not cg_regb_2;
end if;
end process;
process (cg_rega_2, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_rega_3 <= '0';
elsif (cg_aload_in /= '1' and cg_rega_2 = '1' and cg_rega_2'event) then
cg_rega_3 <= not cg_rega_3;
end if;
end process;
process (cg_regb_2, cg_aload_in)
begin
if (cg_aload_in = '1' and cg_aload_in'event) then
cg_regb_3 <= '0';
elsif (cg_aload_in /= '1' and cg_regb_2 = '1' and cg_regb_2'event) then
cg_regb_3 <= not cg_regb_3;
end if;
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (aload_in_buf, aload, tipd_aload);
VitalWireDelay (upndn_in, upndnin, tipd_upndnin);
VitalWireDelay (upndninclkena_in, upndninclkena, tipd_upndninclkena);
end block;
------------------------
-- Timing Check Section
------------------------
VITALtiming : process (clk_in, upndn_in, upndninclkena_in,
delayctrl_out, offsetdelayctrl_out, dqsupdate_out, upndn_out)
variable Tviol_upndnin_clk : std_ulogic := '0';
variable Tviol_upndninclkena_clk : std_ulogic := '0';
variable TimingData_upndnin_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_upndninclkena_clk : VitalTimingDataType := VitalTimingDataInit;
variable delayctrlout_VitalGlitchDataArray : VitalGlitchDataArrayType(5 downto 0);
variable upndnout_VitalGlitchData : VitalGlitchDataType;
begin
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_upndnin_clk,
TimingData => TimingData_upndnin_clk,
TestSignal => upndn_in,
TestSignalName => "UPNDNIN",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_upndnin_clk_noedge_posedge,
SetupLow => tsetup_upndnin_clk_noedge_posedge,
HoldHigh => thold_upndnin_clk_noedge_posedge,
HoldLow => thold_upndnin_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_upndninclkena_clk,
TimingData => TimingData_upndninclkena_clk,
TestSignal => upndninclkena_in,
TestSignalName => "UPNDNINCLKENA",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_upndninclkena_clk_noedge_posedge,
SetupLow => tsetup_upndninclkena_clk_noedge_posedge,
HoldHigh => thold_upndninclkena_clk_noedge_posedge,
HoldLow => thold_upndninclkena_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_DLL",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
----------------------
-- Path Delay Section
----------------------
offsetdelayctrlout <= offsetdelayctrl_out;
dqsupdate <= dqsupdate_out;
VitalPathDelay01 (
OutSignal => upndnout,
OutSignalName => "UPNDNOUT",
OutTemp => upndn_out,
Paths => (0 => (clk_in'last_event, tpd_clk_upndnout_posedge, TRUE)),
GlitchData => upndnout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(0),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(0),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(0), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(0),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(1),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(1),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(1), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(1),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(2),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(2),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(2), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(2),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(3),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(3),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(3), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(3),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(4),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(4),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(4), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(4),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => delayctrlout(5),
OutSignalName => "DELAYCTRLOUT",
OutTemp => delayctrl_out(5),
Paths => (0 => (clk_in'last_event, tpd_clk_delayctrlout_posedge(5), TRUE)),
GlitchData => delayctrlout_VitalGlitchDataArray(5),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process; -- vital timing
end vital_titandll;
-------------------------------------------------------------------------------
--
-- Entity Name : Stratix III_dll_offset_ctrl
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
USE work.stratixiii_pllpack.all;
use work.stratixiii_atom_ddr_pack.all;
use work.stratixiii_dll_gray_encoder;
use work.stratixiii_dll_gray_decoder;
ENTITY stratixiii_dll_offset_ctrl is
GENERIC (
use_offset : string := "false";
static_offset : string := "0";
delay_buffer_mode : string := "low";
lpm_type : string := "stratixiii_dll_offset_ctrl";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetdelayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_addnsub : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_offsetctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
offsetdelayctrlin : IN std_logic_vector(5 DOWNTO 0) := "000000";
offset : IN std_logic_vector(5 DOWNTO 0) := "000000";
addnsub : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
offsettestout : OUT std_logic_vector(5 DOWNTO 0);
offsetctrlout : OUT std_logic_vector(5 DOWNTO 0)
);
END stratixiii_dll_offset_ctrl;
ARCHITECTURE vital_titanoffset of stratixiii_dll_offset_ctrl is
COMPONENT stratixiii_dll_gray_encoder
GENERIC ( width : integer := 6 );
PORT ( mbin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
gout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiii_dll_gray_decoder
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
signal clk_in : std_logic := '0';
signal aload_in : std_logic := '0';
signal offset_in : std_logic_vector(5 DOWNTO 0) := "000000";
signal offsetdelayctrlin_in : std_logic_vector(5 DOWNTO 0) := "000000";
signal addnsub_in : std_logic := '0';
signal offsetctrl_out : std_logic_vector(5 DOWNTO 0) := "000000";
signal para_delay_buffer_mode : std_logic_vector (1 DOWNTO 0) := "01";
signal para_use_offset : std_logic := '0';
signal para_static_offset : integer := 0;
signal para_static_offset_pos : integer := 0;
-- INTERNAL NETS AND VARIABLES
-- for functionality - by modules
-- two reg on the de-assertion of aload
SIGNAL aload_reg1 : std_logic := '1';
SIGNAL aload_reg2 : std_logic := '1';
-- delay and offset control out resolver
signal dr_offsetctrl_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offsettest_out : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offsetctrl_out_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_addnsub_in : std_logic := '1';
signal dr_clk8_in : std_logic := '0';
signal dr_aload_in : std_logic := '0';
signal dr_offset_in_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_delayctrl_in_gray : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_offset_vec_pos : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_offset_gray : std_logic_vector (5 DOWNTO 0) := "000000"; -- signed in 2's complement
-- docoder
signal dr_delayctrl_in_bin : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offset_in_bin : std_logic_vector (5 DOWNTO 0) := "000000";
signal dr_offset_in_bin_pos : std_logic_vector (5 DOWNTO 0) := "000000"; -- for over/underflow check
signal para_static_offset_bin : std_logic_vector (5 DOWNTO 0) := "000000";
signal para_static_offset_bin_pos : std_logic_vector (5 DOWNTO 0) := "000000"; -- for over/underflow check
signal dr_reg_offset : std_logic_vector (5 DOWNTO 0) := "000000";
begin
-- paramters
para_delay_buffer_mode <= "01" WHEN delay_buffer_mode = "low" ELSE "00";
para_use_offset <= '1' WHEN use_offset = "true" ELSE '0';
para_static_offset <= dqs_str2int(static_offset); -- signed int
para_static_offset_pos <= para_static_offset WHEN (para_static_offset > 0) ELSE (-1)*para_static_offset;
-- outputs
offsetctrl_out <= dr_offsetctrl_out_gray;
offsettestout <= dr_offsettest_out;
-- two registers on aload path --------------------------------------------
-- it should be user clock to DLL, not the /8 clock of offsetctrl
process(clk_in)
begin
if (clk_in = '0' and clk_in'event) then
aload_reg2 <= aload_reg1;
aload_reg1 <= aload_in;
end if;
end process;
-- Delay and offset ctrl out resolver -------------------------------------
-- inputs
dr_clk8_in <= clk_in;
dr_addnsub_in <= addnsub_in;
dr_aload_in <= aload_in; -- aload_in | aload_reg2;
dr_delayctrl_in_gray <= offsetdelayctrlin_in;
dr_offset_in_gray <= offset_in;
para_static_offset_vec_pos <= dll_unsigned2bin(para_static_offset_pos);
para_static_offset_gray <= ("111111" - para_static_offset_vec_pos + "000001") WHEN (para_static_offset < 0) ELSE para_static_offset_vec_pos;
-- outputs
dr_offsetctrl_out <= dr_reg_offset;
moffsetctrl_out_enc : stratixiii_dll_gray_encoder
GENERIC MAP (width => 6)
PORT MAP (mbin => dr_reg_offset, gout => dr_offsetctrl_out_gray);
dr_offsettest_out <= para_static_offset_gray WHEN (use_offset = "false") ELSE offset_in;
-- model
-- decoders
mdr_delayctrl_in_dec : stratixiii_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => dr_delayctrl_in_gray, bout => dr_delayctrl_in_bin);
mdr_offset_in_dec : stratixiii_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => dr_offset_in_gray, bout => dr_offset_in_bin);
mpara_static_offset_dec : stratixiii_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => para_static_offset_gray, bout => para_static_offset_bin);
-- get postive value of decoded offset for over/underflow check
para_static_offset_bin_pos <= ("111111" - para_static_offset_bin + "000001") WHEN (para_static_offset < 0) ELSE para_static_offset_bin;
dr_offset_in_bin_pos <= ("111111" - dr_offset_in_bin + "000001") WHEN ((use_offset = "true") AND (addnsub_in = '0')) ELSE dr_offset_in_bin;
-- generating dr_reg_offset
process(dr_clk8_in, dr_aload_in)
begin
if (dr_aload_in = '1' and dr_aload_in'event) then
dr_reg_offset <= "000000";
elsif (dr_aload_in /= '1' and dr_clk8_in = '1' and dr_clk8_in'event) then
if (use_offset = "true") then
if (dr_addnsub_in = '1') then
if (dr_delayctrl_in_bin < "111111" - dr_offset_in_bin) then
dr_reg_offset <= dr_delayctrl_in_bin + dr_offset_in_bin;
else
dr_reg_offset <= "111111";
end if;
elsif (dr_addnsub_in = '0') then
if (dr_delayctrl_in_bin > dr_offset_in_bin_pos) then
dr_reg_offset <= dr_delayctrl_in_bin + dr_offset_in_bin; -- same as - *_pos
else
dr_reg_offset <= "000000";
end if;
end if;
else
if (para_static_offset >= 0) then -- do not use a + b < "11111" as it does not check overflow
if ((para_static_offset_bin < "111111") AND (dr_delayctrl_in_bin < "111111" - para_static_offset_bin )) then
dr_reg_offset <= dr_delayctrl_in_bin + para_static_offset_bin;
else
dr_reg_offset <= "111111";
end if;
else
if ((para_static_offset_bin_pos < "111111") AND (dr_delayctrl_in_bin > para_static_offset_bin_pos)) then
dr_reg_offset <= dr_delayctrl_in_bin + para_static_offset_bin; -- same as - *_pos
else
dr_reg_offset <= "000000";
end if;
end if;
end if;
end if; -- rising clock
end process ; -- generating dr_reg_offset
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (aload_in, aload, tipd_aload);
VitalWireDelay (addnsub_in, addnsub, tipd_addnsub);
VitalWireDelay (offset_in(0), offset(0), tipd_offset(0));
VitalWireDelay (offset_in(1), offset(1), tipd_offset(1));
VitalWireDelay (offset_in(2), offset(2), tipd_offset(2));
VitalWireDelay (offset_in(3), offset(3), tipd_offset(3));
VitalWireDelay (offset_in(4), offset(4), tipd_offset(4));
VitalWireDelay (offset_in(5), offset(5), tipd_offset(5));
VitalWireDelay (offsetdelayctrlin_in(0), offsetdelayctrlin(0), tipd_offsetdelayctrlin(0));
VitalWireDelay (offsetdelayctrlin_in(1), offsetdelayctrlin(1), tipd_offsetdelayctrlin(1));
VitalWireDelay (offsetdelayctrlin_in(2), offsetdelayctrlin(2), tipd_offsetdelayctrlin(2));
VitalWireDelay (offsetdelayctrlin_in(3), offsetdelayctrlin(3), tipd_offsetdelayctrlin(3));
VitalWireDelay (offsetdelayctrlin_in(4), offsetdelayctrlin(4), tipd_offsetdelayctrlin(4));
VitalWireDelay (offsetdelayctrlin_in(5), offsetdelayctrlin(5), tipd_offsetdelayctrlin(5));
end block;
------------------------
-- Timing Check Section
------------------------
VITALtiming : process (clk_in, offset_in, addnsub_in,
offsetctrl_out)
variable Tviol_offset_clk : std_ulogic := '0';
variable Tviol_addnsub_clk : std_ulogic := '0';
variable TimingData_offset_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_addnsub_clk : VitalTimingDataType := VitalTimingDataInit;
variable offsetctrlout_VitalGlitchDataArray : VitalGlitchDataArrayType(5 downto 0);
begin
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_offset_clk,
TimingData => TimingData_offset_clk,
TestSignal => offset_in,
TestSignalName => "OFFSET",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_offset_clk_noedge_posedge(0),
SetupLow => tsetup_offset_clk_noedge_posedge(0),
HoldHigh => thold_offset_clk_noedge_posedge(0),
HoldLow => thold_offset_clk_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_OFFSETCTRL",
XOn => XOn,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_addnsub_clk,
TimingData => TimingData_addnsub_clk,
TestSignal => addnsub_in,
TestSignalName => "ADDNSUB",
RefSignal => clk_in,
RefSignalName => "CLK",
SetupHigh => tsetup_addnsub_clk_noedge_posedge,
SetupLow => tsetup_addnsub_clk_noedge_posedge,
HoldHigh => thold_addnsub_clk_noedge_posedge,
HoldLow => thold_addnsub_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_OFFSETCTRL",
XOn => XOn,
MsgOn => MsgOnChecks );
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => offsetctrlout(0),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(0),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(0), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(0),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(1),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(1),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(1), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(1),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(2),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(2),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(2), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(2),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(3),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(3),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(3), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(3),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(4),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(4),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(4), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(4),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => offsetctrlout(5),
OutSignalName => "offsetctrlOUT",
OutTemp => offsetctrl_out(5),
Paths => (0 => (clk_in'last_event, tpd_clk_offsetctrlout_posedge(5), TRUE)),
GlitchData => offsetctrlout_VitalGlitchDataArray(5),
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process; -- vital timing
end vital_titanoffset;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_dqs_delay_chain
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_dll_gray_decoder;
ENTITY stratixiii_dqs_delay_chain IS
GENERIC (
dqs_input_frequency : string := "unused" ;
use_phasectrlin : string := "false";
phase_setting : integer := 0;
delay_buffer_mode : string := "low";
dqs_phase_shift : integer := 0;
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
-- DFT added in WYS 1.33
test_enable : string := "false";
test_select : integer := 0;
-- SIM only
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiii_dqs_delay_chain";
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_offsetctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_dqsupdateen : VitalDelayType01 := DefpropDelay01;
tipd_phasectrlin : VitalDelayArrayType01(2 downto 0) := (OTHERS => DefPropDelay01);
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tsetup_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_delayctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offsetctrlin_dqsupdateen_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsin : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
offsetctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
dqsupdateen : IN std_logic := '1';
phasectrlin : IN std_logic_vector(2 downto 0) := (OTHERS => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT std_logic;
dffin : OUT std_logic
);
END;
ARCHITECTURE stratixiii_dqs_delay_chain_arch OF stratixiii_dqs_delay_chain IS
-- component section
COMPONENT stratixiii_dll_gray_decoder
GENERIC ( width : integer := 6 );
PORT ( gin : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0) := (OTHERS => '0');
bout : OUT STD_LOGIC_VECTOR (width-1 DOWNTO 0)
);
END COMPONENT;
-- signal section
SIGNAL delayctrl_bin : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL offsetctrl_bin : std_logic_vector(5 downto 0) := (OTHERS => '0');
-- offsetctrl after "dqs_offsetctrl_enable" mux
SIGNAL offsetctrl_mux : std_logic_vector(5 downto 0) := (OTHERS => '0');
-- reged outputs of delay count
SIGNAL delayctrl_reg : std_logic_vector(5 downto 0) := (OTHERS => '1');
SIGNAL offsetctrl_reg : std_logic_vector(5 downto 0) := (OTHERS => '1');
-- delay count after latch enable mux
SIGNAL delayctrl_reg_mux : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL offsetctrl_reg_mux : std_logic_vector(5 downto 0) := (OTHERS => '0');
-- timing outputs
SIGNAL tmp_dqsbusout : STD_LOGIC := '0';
SIGNAL dqs_delay : INTEGER := 0;
-- timing inputs
SIGNAL dqsin_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL offsetctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL dqsupdateen_in : std_logic := '1';
SIGNAL phasectrlin_in : std_logic_vector(2 downto 0) := (OTHERS => '0');
SIGNAL test_bus : std_logic_vector(12 downto 0);
SIGNAL test_lpbk : std_logic;
SIGNAL tmp_dqsin : std_logic;
BEGIN
PROCESS(dqsupdateen_in)
BEGIN
IF (dqsupdateen_in = '1') THEN
delayctrl_reg <= delayctrlin_in;
offsetctrl_reg <= offsetctrl_mux;
END IF;
END PROCESS;
offsetctrl_mux <= offsetctrlin_in WHEN (dqs_offsetctrl_enable = "true") ELSE delayctrlin_in;
-- mux after reg
delayctrl_reg_mux <= delayctrl_reg WHEN (dqs_ctrl_latches_enable = "true") ELSE delayctrlin_in;
offsetctrl_reg_mux <= offsetctrl_reg WHEN (dqs_ctrl_latches_enable = "true") ELSE offsetctrl_mux;
mdelayctrlin_dec : stratixiii_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => delayctrl_reg_mux, bout => delayctrl_bin);
moffsetctrlin_dec : stratixiii_dll_gray_decoder
GENERIC MAP (width => 6)
PORT MAP (gin => offsetctrl_reg_mux, bout => offsetctrl_bin);
PROCESS (delayctrl_bin, offsetctrl_bin, phasectrlin_in)
variable sim_intrinsic_delay : INTEGER := 0;
variable tmp_delayctrl : std_logic_vector(5 downto 0) := (OTHERS => '0');
variable tmp_offsetctrl : std_logic_vector(5 downto 0) := (OTHERS => '0');
variable acell_delay : INTEGER := 0;
variable aoffsetcell_delay : INTEGER := 0;
variable delay_chain_len : INTEGER := 0;
BEGIN
IF (delay_buffer_mode = "low") THEN
sim_intrinsic_delay := sim_low_buffer_intrinsic_delay;
ELSE
sim_intrinsic_delay := sim_high_buffer_intrinsic_delay;
END IF;
IF (delay_buffer_mode = "high" AND delayctrl_bin(5) = '1') THEN
tmp_delayctrl := "011111";
ELSE
tmp_delayctrl := delayctrl_bin;
END IF;
IF (delay_buffer_mode = "high" AND offsetctrl_bin(5) = '1') THEN
tmp_offsetctrl := "011111";
ELSE
tmp_offsetctrl := offsetctrl_bin;
END IF;
-- cell
acell_delay := sim_intrinsic_delay + alt_conv_integer(tmp_delayctrl) * sim_buffer_delay_increment;
IF (dqs_offsetctrl_enable = "true") THEN
aoffsetcell_delay := sim_intrinsic_delay + alt_conv_integer(tmp_offsetctrl)*sim_buffer_delay_increment;
ELSE
aoffsetcell_delay := acell_delay;
END IF;
-- no of cells
IF (use_phasectrlin = "false") THEN
delay_chain_len := phase_setting;
ELSIF (phasectrlin_in(2) = '1') THEN
delay_chain_len := 0;
ELSE
delay_chain_len := alt_conv_integer(phasectrlin_in) + 1;
END IF;
-- total delay
IF (delay_chain_len = 0) THEN
dqs_delay <= 0;
ELSE
dqs_delay <= (delay_chain_len - 1)*acell_delay + aoffsetcell_delay;
END IF;
END PROCESS; -- generating delays
-- test bus loopback
test_bus <= (not dqsupdateen_in) & offsetctrl_reg_mux & delayctrl_reg_mux;
test_lpbk <= test_bus(test_select) WHEN ((0 <= test_select) AND (test_select <= 12)) ELSE 'Z';
tmp_dqsin <= (test_lpbk AND dqsin) WHEN (test_enable = "true") ELSE dqsin_in;
tmp_dqsbusout <= transport tmp_dqsin after (dqs_delay * 1 ps);
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (dqsin_in, dqsin, tipd_dqsin);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_offsetctrlin : FOR i in offsetctrlin'RANGE GENERATE
VitalWireDelay (offsetctrlin_in(i), offsetctrlin(i), tipd_offsetctrlin(i));
END GENERATE;
VitalWireDelay (dqsupdateen_in, dqsupdateen, tipd_dqsupdateen);
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
end block;
-----------------------------------
-- Timing Check Section
-----------------------------------
VITAL_timing_check: PROCESS (dqsupdateen_in,offsetctrlin_in,delayctrlin_in)
variable Tviol_dqsupdateen_offsetctrlin : std_ulogic := '0';
variable TimingData_dqsupdateen_offsetctrlin : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_dqsupdateen_delayctrlin : std_ulogic := '0';
variable TimingData_dqsupdateen_delayctrlin : VitalTimingDataType := VitalTimingDataInit;
BEGIN
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
Violation => Tviol_dqsupdateen_offsetctrlin,
TimingData => TimingData_dqsupdateen_offsetctrlin,
TestSignal => offsetctrlin_in,
TestSignalName => "offsetctrlin",
RefSignal => dqsupdateen_in,
RefSignalName => "dqsupdateen",
SetupHigh => tsetup_offsetctrlin_dqsupdateen_noedge_posedge(0),
SetupLow => tsetup_offsetctrlin_dqsupdateen_noedge_posedge(0),
HoldHigh => thold_offsetctrlin_dqsupdateen_noedge_posedge(0),
HoldLow => thold_offsetctrlin_dqsupdateen_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_DQS_DELAY_CHAIN",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_dqsupdateen_delayctrlin,
TimingData => TimingData_dqsupdateen_delayctrlin,
TestSignal => delayctrlin_in,
TestSignalName => "delayctrlin",
RefSignal => dqsupdateen_in,
RefSignalName => "dqsupdateen",
SetupHigh => tsetup_delayctrlin_dqsupdateen_noedge_posedge(0),
SetupLow => tsetup_delayctrlin_dqsupdateen_noedge_posedge(0),
HoldHigh => thold_delayctrlin_dqsupdateen_noedge_posedge(0),
HoldLow => thold_delayctrlin_dqsupdateen_noedge_posedge(0),
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_DQS_DELAY_CHAIN",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
END IF;
END PROCESS; -- timing check
--------------------------------------
-- Path Delay Section
--------------------------------------
VITAL_path_delays: PROCESS (tmp_dqsbusout)
variable dqsbusout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dqsbusout,
OutSignalName => "dqsbusout",
OutTemp => tmp_dqsbusout,
Paths => (0 => (dqsin_in'last_event, tpd_dqsin_dqsbusout, TRUE)),
GlitchData => dqsbusout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS; -- Path Delays
END stratixiii_dqs_delay_chain_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_dqs_enable
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_dqs_enable IS
GENERIC (
lpm_type : string := "stratixiii_dqs_enable";
tipd_dqsin : VitalDelayType01 := DefpropDelay01;
tipd_dqsenable : VitalDelayType01 := DefpropDelay01;
tpd_dqsin_dqsbusout : VitalDelayType01 := DefPropDelay01;
tpd_dqsenable_dqsbusout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsin : IN std_logic := '0';
dqsenable : IN std_logic := '1';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusout : OUT std_logic
);
END;
ARCHITECTURE stratixiii_dqs_enable_arch OF stratixiii_dqs_enable IS
-- component section
-- signal section
SIGNAL ena_reg : STD_LOGIC := '1';
-- timing output
SIGNAL tmp_dqsbusout : std_logic := '0';
-- timing input
SIGNAL dqsin_in : std_logic := '0';
SIGNAL dqsenable_in : std_logic := '1';
BEGIN
tmp_dqsbusout <= ena_reg AND dqsin_in;
PROCESS(tmp_dqsbusout, dqsenable_in)
BEGIN
IF (dqsenable_in = '1') THEN
ena_reg <= '1';
ELSIF (tmp_dqsbusout'event AND tmp_dqsbusout = '0') THEN
ena_reg <= '0';
END IF;
END PROCESS;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (dqsin_in, dqsin, tipd_dqsin);
VitalWireDelay (dqsenable_in, dqsenable, tipd_dqsenable);
end block;
--------------------------------------
-- Path Delay Section
--------------------------------------
VITAL_path_delays: PROCESS (tmp_dqsbusout)
variable dqsbusout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dqsbusout,
OutSignalName => "dqsbusout",
OutTemp => tmp_dqsbusout,
Paths => (0 => (dqsin_in'last_event, tpd_dqsin_dqsbusout, TRUE),
1 => (dqsenable_in'last_event, tpd_dqsenable_dqsbusout, TRUE)),
GlitchData => dqsbusout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS; -- Path Delays
END stratixiii_dqs_enable_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_dqs_enable_ctrl
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_ddr_io_reg;
use work.stratixiii_ddr_delay_chain_s;
ENTITY stratixiii_dqs_enable_ctrl IS
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
level_dqs_enable : string := "false";
delay_dqs_enable_by_half_cycle : string := "false";
add_phase_transfer_reg : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiii_dqs_enable_ctrl";
tipd_dqsenablein : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
dqsenablein : IN std_logic := '1';
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsenableout : OUT std_logic;
dffin : OUT std_logic;
dffextenddqsenable : OUT std_logic
);
END;
ARCHITECTURE stratixiii_dqs_enable_ctrl_arch OF stratixiii_dqs_enable_ctrl IS
-- component section
COMPONENT stratixiii_ddr_delay_chain_s
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END COMPONENT;
component stratixiii_ddr_io_reg
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
-- int signals
SIGNAL phasectrl_clkout : std_logic := '0';
SIGNAL delayed_clk : std_logic := '0';
SIGNAL dqsenablein_reg_q : std_logic := '0';
SIGNAL dqsenablein_level_ena : std_logic := '0';
-- transfer delay
SIGNAL dqsenablein_reg_dly : std_logic := '0';
SIGNAL phasetransferdelay_mux_out : std_logic := '0';
SIGNAL dqsenable_delayed_regp : std_logic := '0';
SIGNAL dqsenable_delayed_regn : std_logic := '0';
SIGNAL m_vcc : std_logic := '1';
SIGNAL m_gnd : std_logic := '0';
SIGNAL not_clk_in : std_logic := '1';
SIGNAL not_delayed_clk : std_logic := '1';
-- timing output
SIGNAL tmp_dqsenableout : std_logic := '1';
-- timing input
SIGNAL dqsenablein_in : std_logic := '1';
SIGNAL clk_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
SIGNAL enaphasetransferreg_in : std_logic := '0';
SIGNAL phaseinvertctrl_in : std_logic := '0';
BEGIN
-- delay chain
m_delay_chain : stratixiii_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting,
use_phasectrlin => use_phasectrlin,
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => phasectrl_clkout
);
delayed_clk <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
phasectrl_clkout WHEN (invert_phase = "false") ELSE
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = '1') ELSE
phasectrl_clkout;
not_clk_in <= not clk_in;
not_delayed_clk <= not delayed_clk;
dqsenablein_reg : stratixiii_ddr_io_reg
PORT MAP(
d => dqsenablein_in,
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => m_gnd,
asdata => m_gnd,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dqsenablein_reg_q
);
dqsenable_transfer_reg : stratixiii_ddr_io_reg
PORT MAP (
d => dqsenablein_reg_q,
clk => not_delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => m_gnd,
asdata => m_gnd,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dqsenablein_reg_dly
);
-- add phase transfer mux
phasetransferdelay_mux_out <= dqsenablein_reg_dly WHEN (add_phase_transfer_reg = "true") ELSE
dqsenablein_reg_q WHEN (add_phase_transfer_reg = "false") ELSE
dqsenablein_reg_dly WHEN (enaphasetransferreg_in = '1') ELSE
dqsenablein_reg_q;
dqsenablein_level_ena <= phasetransferdelay_mux_out WHEN (level_dqs_enable = "true") ELSE dqsenablein_in;
dqsenableout_reg : stratixiii_ddr_io_reg
PORT MAP(
d => dqsenablein_level_ena,
clk => delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => m_gnd,
asdata => m_gnd,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dqsenable_delayed_regp
);
dqsenableout_extend_reg : stratixiii_ddr_io_reg
PORT MAP(
d => dqsenable_delayed_regp,
clk => not_delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => m_gnd,
asdata => m_gnd,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dqsenable_delayed_regn
);
tmp_dqsenableout <= dqsenable_delayed_regp WHEN (delay_dqs_enable_by_half_cycle = "false") ELSE
(dqsenable_delayed_regp AND dqsenable_delayed_regn);
dqsenableout <= tmp_dqsenableout;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (dqsenablein_in, dqsenablein, tipd_dqsenablein);
VitalWireDelay (clk_in, clk, tipd_clk);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
VitalWireDelay (enaphasetransferreg_in, enaphasetransferreg, tipd_enaphasetransferreg);
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
end block;
END stratixiii_dqs_enable_ctrl_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_delay_chain
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_delay_chain IS
GENERIC (
sim_delayctrlin_rising_delay_0 : integer := 0;
sim_delayctrlin_rising_delay_1 : integer := 50;
sim_delayctrlin_rising_delay_2 : integer := 100;
sim_delayctrlin_rising_delay_3 : integer := 150;
sim_delayctrlin_rising_delay_4 : integer := 200;
sim_delayctrlin_rising_delay_5 : integer := 250;
sim_delayctrlin_rising_delay_6 : integer := 300;
sim_delayctrlin_rising_delay_7 : integer := 350;
sim_delayctrlin_rising_delay_8 : integer := 400;
sim_delayctrlin_rising_delay_9 : integer := 450;
sim_delayctrlin_rising_delay_10 : integer := 500;
sim_delayctrlin_rising_delay_11 : integer := 550;
sim_delayctrlin_rising_delay_12 : integer := 600;
sim_delayctrlin_rising_delay_13 : integer := 650;
sim_delayctrlin_rising_delay_14 : integer := 700;
sim_delayctrlin_rising_delay_15 : integer := 750;
sim_delayctrlin_falling_delay_0 : integer := 0;
sim_delayctrlin_falling_delay_1 : integer := 50;
sim_delayctrlin_falling_delay_2 : integer := 100;
sim_delayctrlin_falling_delay_3 : integer := 150;
sim_delayctrlin_falling_delay_4 : integer := 200;
sim_delayctrlin_falling_delay_5 : integer := 250;
sim_delayctrlin_falling_delay_6 : integer := 300;
sim_delayctrlin_falling_delay_7 : integer := 350;
sim_delayctrlin_falling_delay_8 : integer := 400;
sim_delayctrlin_falling_delay_9 : integer := 450;
sim_delayctrlin_falling_delay_10 : integer := 500;
sim_delayctrlin_falling_delay_11 : integer := 550;
sim_delayctrlin_falling_delay_12 : integer := 600;
sim_delayctrlin_falling_delay_13 : integer := 650;
sim_delayctrlin_falling_delay_14 : integer := 700;
sim_delayctrlin_falling_delay_15 : integer := 750;
use_delayctrlin : string := "true";
delay_setting : integer := 0;
-- new in STRATIXIV ww30.2008
sim_finedelayctrlin_falling_delay_0 : integer := 0;
sim_finedelayctrlin_falling_delay_1 : integer := 25;
sim_finedelayctrlin_rising_delay_0 : integer := 0;
sim_finedelayctrlin_rising_delay_1 : integer := 25;
use_finedelayctrlin : string := "false";
lpm_type : string := "stratixiii_delay_chain";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
delayctrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
finedelayctrlin : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic
);
END;
ARCHITECTURE stratixiii_delay_chain_arch OF stratixiii_delay_chain IS
-- type def
type delay_chain_int_vec is array (natural range <>) of integer;
-- component section
-- signal section
SIGNAL rising_dly : INTEGER := 0;
SIGNAL falling_dly : INTEGER := 0;
SIGNAL delayctrlin_in : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
SIGNAL finedelayctrlin_in : STD_LOGIC := '0';
-- timing inputs
SIGNAL tmp_dataout : std_logic := '0';
-- timing inputs
SIGNAL datain_in : std_logic := '0';
BEGIN
-- filtering X/U etc.
delayctrlin_in(0) <= '1' WHEN (delayctrlin(0) = '1') ELSE '0';
delayctrlin_in(1) <= '1' WHEN (delayctrlin(1) = '1') ELSE '0';
delayctrlin_in(2) <= '1' WHEN (delayctrlin(2) = '1') ELSE '0';
delayctrlin_in(3) <= '1' WHEN (delayctrlin(3) = '1') ELSE '0';
finedelayctrlin_in <= '1' WHEN (finedelayctrlin = '1') ELSE '0';
-- generate dynamic delay table and dynamic delay
process(delayctrlin_in, finedelayctrlin_in)
variable init : boolean := true;
variable dly_table_rising : delay_chain_int_vec(15 downto 0) := (OTHERS => 0);
variable dly_table_falling : delay_chain_int_vec(15 downto 0) := (OTHERS => 0);
variable finedly_table_rising : delay_chain_int_vec(1 downto 0) := (OTHERS => 0);
variable finedly_table_falling : delay_chain_int_vec(1 downto 0) := (OTHERS => 0);
variable dly_setting : integer := 0;
variable finedly_setting : integer := 0;
begin
if (init) then
dly_table_rising(0) := sim_delayctrlin_rising_delay_0;
dly_table_rising(1) := sim_delayctrlin_rising_delay_1;
dly_table_rising(2) := sim_delayctrlin_rising_delay_2;
dly_table_rising(3) := sim_delayctrlin_rising_delay_3;
dly_table_rising(4) := sim_delayctrlin_rising_delay_4;
dly_table_rising(5) := sim_delayctrlin_rising_delay_5;
dly_table_rising(6) := sim_delayctrlin_rising_delay_6;
dly_table_rising(7) := sim_delayctrlin_rising_delay_7;
dly_table_rising(8) := sim_delayctrlin_rising_delay_8;
dly_table_rising(9) := sim_delayctrlin_rising_delay_9;
dly_table_rising(10) := sim_delayctrlin_rising_delay_10;
dly_table_rising(11) := sim_delayctrlin_rising_delay_11;
dly_table_rising(12) := sim_delayctrlin_rising_delay_12;
dly_table_rising(13) := sim_delayctrlin_rising_delay_13;
dly_table_rising(14) := sim_delayctrlin_rising_delay_14;
dly_table_rising(15) := sim_delayctrlin_rising_delay_15;
dly_table_falling(0) := sim_delayctrlin_falling_delay_0;
dly_table_falling(1) := sim_delayctrlin_falling_delay_1;
dly_table_falling(2) := sim_delayctrlin_falling_delay_2;
dly_table_falling(3) := sim_delayctrlin_falling_delay_3;
dly_table_falling(4) := sim_delayctrlin_falling_delay_4;
dly_table_falling(5) := sim_delayctrlin_falling_delay_5;
dly_table_falling(6) := sim_delayctrlin_falling_delay_6;
dly_table_falling(7) := sim_delayctrlin_falling_delay_7;
dly_table_falling(8) := sim_delayctrlin_falling_delay_8;
dly_table_falling(9) := sim_delayctrlin_falling_delay_9;
dly_table_falling(10) := sim_delayctrlin_falling_delay_10;
dly_table_falling(11) := sim_delayctrlin_falling_delay_11;
dly_table_falling(12) := sim_delayctrlin_falling_delay_12;
dly_table_falling(13) := sim_delayctrlin_falling_delay_13;
dly_table_falling(14) := sim_delayctrlin_falling_delay_14;
dly_table_falling(15) := sim_delayctrlin_falling_delay_15;
finedly_table_rising(0) := sim_finedelayctrlin_rising_delay_0;
finedly_table_rising(1) := sim_finedelayctrlin_rising_delay_1;
finedly_table_falling(0) := sim_finedelayctrlin_falling_delay_0;
finedly_table_falling(1) := sim_finedelayctrlin_falling_delay_1;
init := false;
end if;
IF (use_delayctrlin = "false") THEN
dly_setting := delay_setting;
ELSE
dly_setting := alt_conv_integer(delayctrlin_in);
END IF;
IF (finedelayctrlin_in = '1') THEN
finedly_setting := 1;
ELSE
finedly_setting := 0;
END IF;
IF (use_finedelayctrlin = "true") THEN
rising_dly <= dly_table_rising(dly_setting) + finedly_table_rising(finedly_setting);
falling_dly <= dly_table_falling(dly_setting) + finedly_table_falling(finedly_setting);
ELSE
rising_dly <= dly_table_rising(dly_setting);
falling_dly <= dly_table_falling(dly_setting);
END IF;
end process; -- generating dynamic delays
PROCESS(datain_in)
BEGIN
if (datain_in = '0') then
tmp_dataout <= transport datain_in after (falling_dly * 1 ps);
else
tmp_dataout <= transport datain_in after (rising_dly * 1 ps);
end if;
END PROCESS;
----------------------------------
-- Path Delay Section
----------------------------------
VITAL: process(tmp_dataout)
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => tmp_dataout,
Paths => (0 => (datain_in'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
END stratixiii_delay_chain_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_io_clock_divider
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_ddr_delay_chain_s;
ENTITY stratixiii_io_clock_divider IS
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
use_masterin : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiii_io_clock_divider";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_phaseselect : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
tipd_masterin : VitalDelayType01 := DefpropDelay01;
tpd_clk_clkout : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
clk : IN std_logic := '0';
phaseselect : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
phaseinvertctrl : IN std_logic := '0';
masterin : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
clkout : OUT std_logic;
slaveout : OUT std_logic
);
END;
ARCHITECTURE stratixiii_io_clock_divider_arch OF stratixiii_io_clock_divider IS
-- component section
COMPONENT stratixiii_ddr_delay_chain_s
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END COMPONENT;
-- int signals
SIGNAL phasectrl_clkout : STD_LOGIC := '0';
SIGNAL delayed_clk : STD_LOGIC := '0';
SIGNAL divided_clk_in : STD_LOGIC := '0';
SIGNAL divided_clk : STD_LOGIC := '0';
-- timing outputs
SIGNAL tmp_clkout : STD_LOGIC := '0';
-- timing inputs
SIGNAL clk_in : std_logic := '0';
SIGNAL phaseselect_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
SIGNAL phaseinvertctrl_in : std_logic := '0';
SIGNAL masterin_in : std_logic := '0';
BEGIN
-- delay chain
m_delay_chain : stratixiii_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting,
use_phasectrlin => use_phasectrlin,
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => phasectrl_clkout
);
delayed_clk <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
phasectrl_clkout WHEN (invert_phase = "false") ELSE
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = '1') ELSE
phasectrl_clkout;
divided_clk_in <= masterin_in WHEN (use_masterin = "true") ELSE divided_clk;
PROCESS (delayed_clk)
BEGIN
if (delayed_clk = '1') then
divided_clk <= not divided_clk_in;
end if;
END PROCESS;
tmp_clkout <= (not divided_clk) WHEN (phaseselect_in = '1') ELSE divided_clk;
slaveout <= divided_clk;
----------------------------------
-- Path Delay Section
----------------------------------
VITAL: process(tmp_clkout)
variable clkout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => clkout,
OutSignalName => "clkout",
OutTemp => tmp_clkout,
Paths => (0 => (clk_in'last_event, tpd_clk_clkout, TRUE)),
GlitchData => clkout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (phaseselect_in, phaseselect, tipd_phaseselect);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
VitalWireDelay (masterin_in, masterin, tipd_masterin);
end block;
END stratixiii_io_clock_divider_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_output_phase_alignment
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_ddr_io_reg;
use work.stratixiii_ddr_delay_chain_s;
ENTITY stratixiii_output_phase_alignment IS
GENERIC (
operation_mode : string := "ddio_out";
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
add_output_cycle_delay : string := "false";
use_delayed_clock : string := "false";
add_phase_transfer_reg : string := "false";
use_phasectrl_clock : string := "true";
use_primary_clock : string := "true";
invert_phase : string := "false";
bypass_input_register : string := "false";
phase_setting_for_delayed_clock : integer := 2;
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
-- new in STRATIXIV: ww30.2008
duty_cycle_delay_mode : string := "none";
sim_dutycycledelayctrlin_falling_delay_0 : integer := 0 ;
sim_dutycycledelayctrlin_falling_delay_1 : integer := 25 ;
sim_dutycycledelayctrlin_falling_delay_10 : integer := 250 ;
sim_dutycycledelayctrlin_falling_delay_11 : integer := 275 ;
sim_dutycycledelayctrlin_falling_delay_12 : integer := 300 ;
sim_dutycycledelayctrlin_falling_delay_13 : integer := 325 ;
sim_dutycycledelayctrlin_falling_delay_14 : integer := 350 ;
sim_dutycycledelayctrlin_falling_delay_15 : integer := 375 ;
sim_dutycycledelayctrlin_falling_delay_2 : integer := 50 ;
sim_dutycycledelayctrlin_falling_delay_3 : integer := 75 ;
sim_dutycycledelayctrlin_falling_delay_4 : integer := 100 ;
sim_dutycycledelayctrlin_falling_delay_5 : integer := 125 ;
sim_dutycycledelayctrlin_falling_delay_6 : integer := 150 ;
sim_dutycycledelayctrlin_falling_delay_7 : integer := 175 ;
sim_dutycycledelayctrlin_falling_delay_8 : integer := 200 ;
sim_dutycycledelayctrlin_falling_delay_9 : integer := 225 ;
sim_dutycycledelayctrlin_rising_delay_0 : integer := 0 ;
sim_dutycycledelayctrlin_rising_delay_1 : integer := 25 ;
sim_dutycycledelayctrlin_rising_delay_10 : integer := 250 ;
sim_dutycycledelayctrlin_rising_delay_11 : integer := 275 ;
sim_dutycycledelayctrlin_rising_delay_12 : integer := 300 ;
sim_dutycycledelayctrlin_rising_delay_13 : integer := 325 ;
sim_dutycycledelayctrlin_rising_delay_14 : integer := 350 ;
sim_dutycycledelayctrlin_rising_delay_15 : integer := 375 ;
sim_dutycycledelayctrlin_rising_delay_2 : integer := 50 ;
sim_dutycycledelayctrlin_rising_delay_3 : integer := 75 ;
sim_dutycycledelayctrlin_rising_delay_4 : integer := 100 ;
sim_dutycycledelayctrlin_rising_delay_5 : integer := 125 ;
sim_dutycycledelayctrlin_rising_delay_6 : integer := 150 ;
sim_dutycycledelayctrlin_rising_delay_7 : integer := 175 ;
sim_dutycycledelayctrlin_rising_delay_8 : integer := 200 ;
sim_dutycycledelayctrlin_rising_delay_9 : integer := 225 ;
lpm_type : string := "stratixiii_output_phase_alignment";
tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_sreset : VitalDelayType01 := DefpropDelay01;
tipd_clkena : VitalDelayType01 := DefpropDelay01;
tipd_enaoutputcycledelay : VitalDelayType01 := DefpropDelay01;
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0');
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
clkena : IN std_logic := '1';
enaoutputcycledelay : IN std_logic := '0';
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
delaymode : IN std_logic := '0'; -- new in STRATIXIV: ww30.2008
dutycycledelayctrlin: IN std_logic_vector(3 downto 0) := (OTHERS => '0');
dataout : OUT std_logic;
dffin : OUT std_logic_vector(1 downto 0);
dff1t : OUT std_logic_vector(1 downto 0);
dffddiodataout : OUT std_logic
);
END;
ARCHITECTURE stratixiii_output_phase_alignment_arch OF stratixiii_output_phase_alignment IS
-- type def
type delay_chain_int_vec is array (natural range <>) of integer;
-- component section
COMPONENT stratixiii_ddr_delay_chain_s
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END COMPONENT;
component stratixiii_ddr_io_reg
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
-- int signals on clock paths
SIGNAL clk_in_delayed: STD_LOGIC := '0';
SIGNAL clk_in_mux: STD_LOGIC := '0';
SIGNAL phasectrl_clkout: STD_LOGIC := '0';
SIGNAL phaseinvertctrl_out: STD_LOGIC := '0';
SIGNAL m_vcc: STD_LOGIC := '1';
SIGNAL m_gnd: STD_LOGIC := '0';
-- IO registers
-- common
SIGNAL adatasdata_in_r : STD_LOGIC := '0'; -- sync reset - common for transfer and output reg
SIGNAL sclr_in_r : STD_LOGIC := '0';
SIGNAL sload_in_r : STD_LOGIC := '0';
SIGNAL sclr_in : STD_LOGIC := '0';
SIGNAL sload_in : STD_LOGIC := '0';
SIGNAL adatasdata_in : STD_LOGIC := '0';
SIGNAL clrn_in_r : STD_LOGIC := '1'; -- async reset - common for all registers
SIGNAL prn_in_r : STD_LOGIC := '1';
SIGNAL datain_q: STD_LOGIC := '0';
SIGNAL ddio_datain_q: STD_LOGIC := '0';
SIGNAL cycledelay_q: STD_LOGIC := '0';
SIGNAL ddio_cycledelay_q: STD_LOGIC := '0';
SIGNAL cycledelay_mux_out: STD_LOGIC := '0';
SIGNAL ddio_cycledelay_mux_out: STD_LOGIC := '0';
SIGNAL bypass_input_reg_mux_out : STD_LOGIC := '0';
SIGNAL ddio_bypass_input_reg_mux_out : STD_LOGIC := '0';
SIGNAL not_clk_in_mux: STD_LOGIC := '0';
SIGNAL ddio_out_clk_mux: STD_LOGIC := '0';
SIGNAL ddio_out_lo_q: STD_LOGIC := '0';
SIGNAL ddio_out_hi_q: STD_LOGIC := '0';
-- transfer delay now by negative clk
SIGNAL transfer_q: STD_LOGIC := '0';
SIGNAL ddio_transfer_q: STD_LOGIC := '0';
-- Duty Cycle Delay
SIGNAL dcd_in : STD_LOGIC := '0';
SIGNAL dcd_out : STD_LOGIC := '0';
SIGNAL dcd_both : STD_LOGIC := '0';
SIGNAL dcd_both_gnd : STD_LOGIC := '0';
SIGNAL dcd_both_vcc : STD_LOGIC := '0';
SIGNAL dcd_fallnrise : STD_LOGIC := '0';
SIGNAL dcd_fallnrise_gnd : STD_LOGIC := '0';
SIGNAL dcd_fallnrise_vcc : STD_LOGIC := '0';
SIGNAL dcd_rising_dly : INTEGER := 0;
SIGNAL dcd_falling_dly : INTEGER := 0;
SIGNAL dlyclk_clk: STD_LOGIC := '0';
SIGNAL dlyclk_d: STD_LOGIC := '0';
SIGNAL dlyclk_q: STD_LOGIC := '0';
SIGNAL ddio_dlyclk_d: STD_LOGIC := '0';
SIGNAL ddio_dlyclk_q: STD_LOGIC := '0';
SIGNAL dlyclk_clkena_in: STD_LOGIC := '0'; -- shared
SIGNAL dlyclk_extended_q: STD_LOGIC := '0';
SIGNAL dlyclk_extended_clk: STD_LOGIC := '0';
SIGNAL normal_dataout: STD_LOGIC := '0';
SIGNAL extended_dataout: STD_LOGIC := '0';
SIGNAL ddio_dataout: STD_LOGIC := '0';
SIGNAL tmp_dataout: STD_LOGIC := '0';
-- timing inputs
SIGNAL datain_in : std_logic_vector(1 downto 0) := (OTHERS => '0');
SIGNAL clk_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
SIGNAL areset_in : std_logic := '0';
SIGNAL sreset_in : std_logic := '0';
SIGNAL clkena_in : std_logic := '1';
SIGNAL enaoutputcycledelay_in : std_logic := '0';
SIGNAL enaphasetransferreg_in : std_logic := '0';
SIGNAL phaseinvertctrl_in : std_logic := '0';
SIGNAL delaymode_in: std_logic := '0';
SIGNAL dutycycledelayctrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
BEGIN
-- filtering X/U etc.
delaymode_in <= '1' WHEN (delaymode = '1') ELSE '0';
dutycycledelayctrlin_in(0) <= '1' WHEN (dutycycledelayctrlin(0) = '1') ELSE '0';
dutycycledelayctrlin_in(1) <= '1' WHEN (dutycycledelayctrlin(1) = '1') ELSE '0';
dutycycledelayctrlin_in(2) <= '1' WHEN (dutycycledelayctrlin(2) = '1') ELSE '0';
dutycycledelayctrlin_in(3) <= '1' WHEN (dutycycledelayctrlin(3) = '1') ELSE '0';
-- delay chain for clk_in delay
m_clk_in_delay_chain : stratixiii_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting_for_delayed_clock,
use_phasectrlin => "false",
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => clk_in_delayed
);
-- clock source for datain and cycle delay registers
clk_in_mux <= clk_in_delayed WHEN (use_delayed_clock = "true") ELSE clk_in;
-- delay chain for phase control
m_delay_chain : stratixiii_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting,
use_phasectrlin => use_phasectrlin,
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
phasectrlin_limit => 10,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => phasectrl_clkout
);
-- primary outputs
normal_dataout <= dlyclk_q;
extended_dataout <= dlyclk_q OR dlyclk_extended_q; -- oe port is active low
ddio_dataout <= ddio_out_hi_q WHEN (ddio_out_clk_mux = '1') ELSE ddio_out_lo_q;
tmp_dataout <= ddio_dataout WHEN (operation_mode = "ddio_out") ELSE
extended_dataout WHEN (operation_mode = "extended_oe" OR operation_mode = "extended_rtena") ELSE
normal_dataout WHEN (operation_mode = "output" OR operation_mode = "oe" OR operation_mode = "rtena") ELSE
'Z';
dataout <= tmp_dataout;
ddio_out_clk_mux <= dlyclk_clk after 1 ps; -- symbolic T4 to remove glitch on data_h
ddio_out_lo_q <= dlyclk_q after 2 ps; -- symbolic 2 T4 to remove glitch on data_l
ddio_out_hi_q <= ddio_dlyclk_q;
-- resolve reset modes
PROCESS(areset_in)
BEGIN
IF (async_mode = "clear") THEN
clrn_in_r <= not areset_in;
prn_in_r <= '1';
ELSIF (async_mode = "preset") THEN
prn_in_r <= not areset_in;
clrn_in_r <= '1';
END IF;
END PROCESS;
PROCESS(sreset_in)
BEGIN
IF (sync_mode = "clear") THEN
sclr_in_r <= sreset_in;
adatasdata_in_r <= '0';
sload_in_r <= '0';
ELSIF (sync_mode = "preset") THEN
sload_in_r <= sreset_in;
adatasdata_in_r <= '1';
sclr_in_r <= '0';
END IF;
END PROCESS;
sclr_in <= '0' WHEN (operation_mode = "rtena" OR operation_mode = "extended_rtena") ELSE sclr_in_r;
sload_in <= '0' WHEN (operation_mode = "rtena" OR operation_mode = "extended_rtena") ELSE sload_in_r;
adatasdata_in <= adatasdata_in_r;
dlyclk_clkena_in <= '1' WHEN (operation_mode = "rtena" OR operation_mode = "extended_rtena") ELSE clkena_in;
-- Datain Register
datain_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(0),
clk => clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => datain_q
);
-- DDIO Datain Register
ddio_datain_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(1),
clk => clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => ddio_datain_q
);
-- Cycle Delay Register
cycledelay_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_q,
clk => clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => cycledelay_q
);
-- DDIO Cycle Delay Register
ddio_cycledelay_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => ddio_datain_q,
clk => clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => ddio_cycledelay_q
);
-- enaoutputcycledelay data path mux
cycledelay_mux_out <= cycledelay_q WHEN (add_output_cycle_delay = "true") ELSE
datain_q WHEN (add_output_cycle_delay = "false") ELSE
cycledelay_q WHEN (enaoutputcycledelay_in = m_vcc) ELSE
datain_q;
-- input register bypass mux
bypass_input_reg_mux_out <= datain_in(0) WHEN (bypass_input_register = "true") ELSE cycledelay_mux_out;
--assign #300 transfer_q = cycledelay_mux_out;
-- transfer delay is implemented with negative register in rev1.26
transferdelay_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => bypass_input_reg_mux_out,
clk => not_clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => transfer_q
);
-- add phase transfer data path mux
dlyclk_d <= transfer_q WHEN (add_phase_transfer_reg = "true") ELSE
bypass_input_reg_mux_out WHEN (add_phase_transfer_reg = "false") ELSE
transfer_q WHEN (enaphasetransferreg_in = m_vcc) ELSE
bypass_input_reg_mux_out;
-- clock mux for the output register
phaseinvertctrl_out <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
phasectrl_clkout WHEN (invert_phase = "false") ELSE
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = m_vcc) ELSE
phasectrl_clkout;
-- Duty Cycle Delay
dcd_in <= phaseinvertctrl_out WHEN (use_phasectrl_clock = "true") ELSE clk_in_mux;
PROCESS(dutycycledelayctrlin_in)
variable init : boolean := true;
variable dcd_table_rising : delay_chain_int_vec(15 downto 0) := (OTHERS => 0);
variable dcd_table_falling : delay_chain_int_vec(15 downto 0) := (OTHERS => 0);
variable dcd_dly_setting : integer := 0;
begin
if (init) then
dcd_table_rising(0) := sim_dutycycledelayctrlin_rising_delay_0;
dcd_table_rising(1) := sim_dutycycledelayctrlin_rising_delay_1;
dcd_table_rising(2) := sim_dutycycledelayctrlin_rising_delay_2;
dcd_table_rising(3) := sim_dutycycledelayctrlin_rising_delay_3;
dcd_table_rising(4) := sim_dutycycledelayctrlin_rising_delay_4;
dcd_table_rising(5) := sim_dutycycledelayctrlin_rising_delay_5;
dcd_table_rising(6) := sim_dutycycledelayctrlin_rising_delay_6;
dcd_table_rising(7) := sim_dutycycledelayctrlin_rising_delay_7;
dcd_table_rising(8) := sim_dutycycledelayctrlin_rising_delay_8;
dcd_table_rising(9) := sim_dutycycledelayctrlin_rising_delay_9;
dcd_table_rising(10) := sim_dutycycledelayctrlin_rising_delay_10;
dcd_table_rising(11) := sim_dutycycledelayctrlin_rising_delay_11;
dcd_table_rising(12) := sim_dutycycledelayctrlin_rising_delay_12;
dcd_table_rising(13) := sim_dutycycledelayctrlin_rising_delay_13;
dcd_table_rising(14) := sim_dutycycledelayctrlin_rising_delay_14;
dcd_table_rising(15) := sim_dutycycledelayctrlin_rising_delay_15;
dcd_table_falling(0) := sim_dutycycledelayctrlin_falling_delay_0;
dcd_table_falling(1) := sim_dutycycledelayctrlin_falling_delay_1;
dcd_table_falling(2) := sim_dutycycledelayctrlin_falling_delay_2;
dcd_table_falling(3) := sim_dutycycledelayctrlin_falling_delay_3;
dcd_table_falling(4) := sim_dutycycledelayctrlin_falling_delay_4;
dcd_table_falling(5) := sim_dutycycledelayctrlin_falling_delay_5;
dcd_table_falling(6) := sim_dutycycledelayctrlin_falling_delay_6;
dcd_table_falling(7) := sim_dutycycledelayctrlin_falling_delay_7;
dcd_table_falling(8) := sim_dutycycledelayctrlin_falling_delay_8;
dcd_table_falling(9) := sim_dutycycledelayctrlin_falling_delay_9;
dcd_table_falling(10) := sim_dutycycledelayctrlin_falling_delay_10;
dcd_table_falling(11) := sim_dutycycledelayctrlin_falling_delay_11;
dcd_table_falling(12) := sim_dutycycledelayctrlin_falling_delay_12;
dcd_table_falling(13) := sim_dutycycledelayctrlin_falling_delay_13;
dcd_table_falling(14) := sim_dutycycledelayctrlin_falling_delay_14;
dcd_table_falling(15) := sim_dutycycledelayctrlin_falling_delay_15;
init := false;
end if;
dcd_dly_setting := alt_conv_integer(dutycycledelayctrlin_in);
dcd_rising_dly <= dcd_table_rising(dcd_dly_setting);
dcd_falling_dly <= dcd_table_falling(dcd_dly_setting);
end process; -- generating dynamic delays
PROCESS(dcd_in)
BEGIN
dcd_both_gnd <= dcd_in;
if (dcd_in = '0') then
dcd_both_vcc <= transport dcd_in after (dcd_falling_dly * 1 ps);
else
dcd_both_vcc <= transport dcd_in after (dcd_rising_dly * 1 ps);
end if;
END PROCESS;
PROCESS(dcd_in)
BEGIN
if (dcd_in = '0') then
dcd_fallnrise_gnd <= transport dcd_in after (dcd_falling_dly * 1 ps);
else
dcd_fallnrise_vcc <= transport dcd_in after (dcd_rising_dly * 1 ps);
end if;
END PROCESS;
dcd_both <= dcd_both_vcc WHEN (delaymode_in = '1') ELSE dcd_both_gnd;
dcd_fallnrise <= dcd_fallnrise_vcc WHEN (delaymode_in = '1') ELSE dcd_fallnrise_gnd;
dlyclk_clk <= dcd_both WHEN (duty_cycle_delay_mode = "both") ELSE
dcd_fallnrise WHEN (duty_cycle_delay_mode = "fallnrise") ELSE dcd_in;
-- Output Register clocked by phasectrl_clk
dlyclk_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dlyclk_d,
clk => dlyclk_clk,
ena => dlyclk_clkena_in,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => dlyclk_q
);
-- enaoutputcycledelay data path mux
ddio_cycledelay_mux_out <= ddio_cycledelay_q WHEN (add_output_cycle_delay = "true") ELSE
ddio_datain_q WHEN (add_output_cycle_delay = "false") ELSE
ddio_cycledelay_q WHEN (enaoutputcycledelay_in = m_vcc) ELSE
ddio_datain_q;
-- input register bypass mux
ddio_bypass_input_reg_mux_out <= datain_in(1) WHEN (bypass_input_register = "true") ELSE ddio_cycledelay_mux_out;
--assign #300 ddio_transfer_q = ddio_cycledelay_mux_out;
-- transfer delay is implemented with negative register in rev1.26
not_clk_in_mux <= not clk_in_mux;
ddio_transferdelay_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => ddio_bypass_input_reg_mux_out,
clk => not_clk_in_mux,
ena => m_vcc,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => ddio_transfer_q
);
-- add phase transfer data path mux
ddio_dlyclk_d <= ddio_transfer_q WHEN (add_phase_transfer_reg = "true") ELSE
ddio_bypass_input_reg_mux_out WHEN (add_phase_transfer_reg = "false") ELSE
ddio_transfer_q WHEN (enaphasetransferreg_in = m_vcc) ELSE
ddio_bypass_input_reg_mux_out;
-- Output Register clocked by phasectrl_clk
ddio_dlyclk_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => ddio_dlyclk_d,
clk => dlyclk_clk,
ena => dlyclk_clkena_in,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => ddio_dlyclk_q
);
-- Extension Register
dlyclk_extended_clk <= not dlyclk_clk;
dlyclk_extended_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dlyclk_q,
clk => dlyclk_extended_clk,
ena => dlyclk_clkena_in,
clrn => clrn_in_r,
prn => prn_in_r,
aload => m_gnd,
asdata => adatasdata_in,
sclr => sclr_in,
sload => sload_in,
devclrn => devclrn,
devpor => devpor,
q => dlyclk_extended_q
);
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
loopbits_datain : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_in(i), datain(i), tipd_datain(i));
END GENERATE;
VitalWireDelay (clk_in, clk, tipd_clk);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
VitalWireDelay (areset_in, areset, tipd_areset);
VitalWireDelay (sreset_in, sreset, tipd_sreset);
VitalWireDelay (clkena_in, clkena, tipd_clkena);
VitalWireDelay (enaoutputcycledelay_in, enaoutputcycledelay, tipd_enaoutputcycledelay);
VitalWireDelay (enaphasetransferreg_in, enaphasetransferreg, tipd_enaphasetransferreg);
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
end block;
END stratixiii_output_phase_alignment_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_input_phase_alignment
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_ddr_io_reg;
use work.stratixiii_ddr_delay_chain_s;
ENTITY stratixiii_input_phase_alignment IS
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
power_up : string := "low";
async_mode : string := "none";
add_input_cycle_delay : string := "false";
bypass_output_register : string := "false";
add_phase_transfer_reg : string := "false";
invert_phase : string := "false";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
lpm_type : string := "stratixiii_input_phase_alignment";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_delayctrlin : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_phasectrlin : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_enainputcycledelay : VitalDelayType01 := DefpropDelay01;
tipd_enaphasetransferreg : VitalDelayType01 := DefpropDelay01;
tipd_phaseinvertctrl : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 downto 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 downto 0) := (OTHERS => '0');
areset : IN std_logic := '0';
enainputcycledelay : IN std_logic := '0';
enaphasetransferreg : IN std_logic := '0';
phaseinvertctrl : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic;
dffin : OUT std_logic;
dff1t : OUT std_logic
);
END;
ARCHITECTURE stratixiii_input_phase_alignment_arch OF stratixiii_input_phase_alignment IS
-- component section
COMPONENT stratixiii_ddr_delay_chain_s
GENERIC (
use_phasectrlin : string := "true";
phase_setting : integer := 0;
delay_buffer_mode : string := "high";
sim_low_buffer_intrinsic_delay : integer := 350;
sim_high_buffer_intrinsic_delay : integer := 175;
sim_buffer_delay_increment : integer := 10;
phasectrlin_limit : integer := 7
);
PORT (
clk : IN std_logic := '0';
delayctrlin : IN std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
phasectrlin : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '0');
delayed_clkout : OUT std_logic
);
END COMPONENT;
component stratixiii_ddr_io_reg
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
-- int signals
SIGNAL phasectrl_clkout : STD_LOGIC := '0';
SIGNAL delayed_clk : STD_LOGIC := '0';
SIGNAL not_delayed_clk : STD_LOGIC := '1';
SIGNAL m_vcc: STD_LOGIC := '1';
SIGNAL m_gnd: STD_LOGIC := '0';
-- IO registers
-- common
SIGNAL adatasdata_in_r : STD_LOGIC := '0';
SIGNAL aload_in_r : STD_LOGIC := '0';
SIGNAL datain_q : STD_LOGIC := '0';
SIGNAL cycledelay_q : STD_LOGIC := '0';
SIGNAL cycledelay_mux_out : STD_LOGIC := '0';
SIGNAL cycledelay_mux_out_dly : STD_LOGIC := '0';
SIGNAL dlyclk_d : STD_LOGIC := '0';
SIGNAL dlyclk_q : STD_LOGIC := '0';
SIGNAL tmp_dataout : STD_LOGIC := '0';
-- timing inputs
SIGNAL datain_in : std_logic := '0';
SIGNAL clk_in : std_logic := '0';
SIGNAL delayctrlin_in : std_logic_vector(5 downto 0) := (OTHERS => '0');
SIGNAL phasectrlin_in : std_logic_vector(3 downto 0) := (OTHERS => '0');
SIGNAL areset_in : std_logic := '0';
SIGNAL enainputcycledelay_in : std_logic := '0';
SIGNAL enaphasetransferreg_in : std_logic := '0';
SIGNAL phaseinvertctrl_in : std_logic := '0';
BEGIN
m_clk_in_delay_chain : stratixiii_ddr_delay_chain_s
GENERIC MAP (
phase_setting => phase_setting,
use_phasectrlin => use_phasectrlin,
delay_buffer_mode => delay_buffer_mode,
sim_low_buffer_intrinsic_delay => sim_low_buffer_intrinsic_delay,
sim_high_buffer_intrinsic_delay => sim_high_buffer_intrinsic_delay,
sim_buffer_delay_increment => sim_buffer_delay_increment
)
PORT MAP(
clk => clk_in,
delayctrlin => delayctrlin_in,
phasectrlin => phasectrlin_in,
delayed_clkout => phasectrl_clkout
);
delayed_clk <= (not phasectrl_clkout) WHEN (invert_phase = "true") ELSE
phasectrl_clkout WHEN (invert_phase = "false") ELSE
(not phasectrl_clkout) WHEN (phaseinvertctrl_in = '1') ELSE
phasectrl_clkout;
-- primary output
dataout <= tmp_dataout;
tmp_dataout <= dlyclk_d WHEN (bypass_output_register = "true") ELSE dlyclk_q;
-- add phase transfer data path mux
dlyclk_d <= cycledelay_mux_out_dly WHEN (add_phase_transfer_reg = "true") ELSE
cycledelay_mux_out WHEN (add_phase_transfer_reg = "false") ELSE
cycledelay_mux_out_dly WHEN (enaphasetransferreg_in = '1') ELSE
cycledelay_mux_out;
-- enaoutputcycledelay data path mux
cycledelay_mux_out <= cycledelay_q WHEN (add_input_cycle_delay = "true") ELSE
datain_q WHEN (add_input_cycle_delay = "false") ELSE
cycledelay_q WHEN (enainputcycledelay_in = '1') ELSE
datain_q;
-- resolve reset modes
PROCESS (areset_in)
BEGIN
if (async_mode = "clear") then
aload_in_r <= areset_in;
adatasdata_in_r <= '0';
elsif (async_mode = "preset") then
aload_in_r <= areset_in;
adatasdata_in_r <= '1';
else -- async_mode = "none"
adatasdata_in_r <= 'Z';
end if;
END PROCESS;
-- Datain Register
datain_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in,
clk => delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => datain_q
);
-- Cycle Delay Register
cycledelay_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_q,
clk => delayed_clk,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => cycledelay_q
);
-- assign #300 cycledelay_mux_out_dly = cycledelay_mux_out; replaced by neg reg
-- Transfer Register - clocked by negative edge
not_delayed_clk <= not delayed_clk;
transfer_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => cycledelay_mux_out,
clk => not_delayed_clk, -- ~delayed_clk
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => cycledelay_mux_out_dly
);
-- Register clocked by actually by clk_in
dlyclk_reg : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dlyclk_d,
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dlyclk_q
);
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (datain_in, datain, tipd_datain);
VitalWireDelay (clk_in, clk, tipd_clk);
loopbits_delayctrlin : FOR i in delayctrlin'RANGE GENERATE
VitalWireDelay (delayctrlin_in(i), delayctrlin(i), tipd_delayctrlin(i));
END GENERATE;
loopbits_phasectrlin : FOR i in phasectrlin'RANGE GENERATE
VitalWireDelay (phasectrlin_in(i), phasectrlin(i), tipd_phasectrlin(i));
END GENERATE;
VitalWireDelay (areset_in, areset, tipd_areset);
VitalWireDelay (enainputcycledelay_in, enainputcycledelay, tipd_enainputcycledelay);
VitalWireDelay (enaphasetransferreg_in, enaphasetransferreg, tipd_enaphasetransferreg);
VitalWireDelay (phaseinvertctrl_in, phaseinvertctrl, tipd_phaseinvertctrl);
end block;
END stratixiii_input_phase_alignment_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_half_rate_input
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
use work.stratixiii_ddr_io_reg;
ENTITY stratixiii_half_rate_input IS
GENERIC (
power_up : string := "low";
async_mode : string := "none";
use_dataoutbypass : string := "false";
lpm_type : string := "stratixiii_half_rate_input";
tipd_datain : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_directin : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_areset : VitalDelayType01 := DefpropDelay01;
tipd_dataoutbypass : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic_vector(1 downto 0) := (OTHERS => '0');
directin : IN std_logic := '0';
clk : IN std_logic := '0';
areset : IN std_logic := '0';
dataoutbypass: IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dataout : OUT std_logic_vector(3 downto 0);
dffin : OUT std_logic
);
END;
ARCHITECTURE stratixiii_half_rate_input_arch OF stratixiii_half_rate_input IS
-- component section
component stratixiii_ddr_io_reg
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
SIGNAL m_vcc: STD_LOGIC := '1';
SIGNAL m_gnd: STD_LOGIC := '0';
-- IO SIGNAListers
-- common
SIGNAL neg_clk_in : STD_LOGIC := '0';
SIGNAL adatasdata_in_r : STD_LOGIC := '0';
SIGNAL aload_in_r : STD_LOGIC := '0';
-- low_bank = {1, 0} - capturing datain at falling edge then sending at falling rise
-- high_bank = {3, 2} - output of SIGNALister datain at rising
SIGNAL high_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
SIGNAL low_bank : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
SIGNAL low_bank_low : STD_LOGIC := '0';
SIGNAL low_bank_high : STD_LOGIC := '0';
SIGNAL high_bank_low : STD_LOGIC := '0';
SIGNAL high_bank_high: STD_LOGIC := '0';
SIGNAL dataout_reg_n : STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
SIGNAL tmp_dataout : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
-- delayed version to ensure 1 latency as expected in functional sim
SIGNAL datain_in : std_logic_vector(1 downto 0) := (OTHERS => '0');
-- timing inputs
SIGNAL datain_ipd : std_logic_vector(1 downto 0) := (OTHERS => '0');
SIGNAL directin_in : std_logic := '0';
SIGNAL clk_in : std_logic := '0';
SIGNAL areset_in : std_logic := '0';
SIGNAL dataoutbypass_in: std_logic := '0';
BEGIN
-- primary input
datain_in <= transport datain_ipd after 2 ps;
-- primary output
dataout <= tmp_dataout;
tmp_dataout(3) <= directin_in WHEN (dataoutbypass_in = '0' AND use_dataoutbypass = "true") ELSE high_bank_high;
tmp_dataout(2) <= directin_in WHEN (dataoutbypass_in = '0' AND use_dataoutbypass = "true") ELSE high_bank_low;
tmp_dataout(1) <= low_bank(1);
tmp_dataout(0) <= low_bank(0);
low_bank <= low_bank_high & low_bank_low;
high_bank <= high_bank_high & high_bank_low;
-- resolve reset modes
PROCESS(areset_in)
BEGIN
if (async_mode = "clear") then
aload_in_r <= areset_in;
adatasdata_in_r <= '0';
elsif (async_mode = "preset") then
aload_in_r <= areset_in;
adatasdata_in_r <= '1';
else -- async_mode = "none"
adatasdata_in_r <= 'Z';
end if;
END PROCESS;
neg_clk_in <= not clk_in;
-- datain_1 - H
reg1_h : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(1),
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => high_bank_high
);
-- datain_0 - H
reg0_h : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(0),
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => high_bank_low
);
-- datain_1 - L (n)
reg1_l_n : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(1),
clk => neg_clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dataout_reg_n(1)
);
-- datain_1 - L
reg1_l : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dataout_reg_n(1),
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => low_bank_high
);
-- datain_0 - L (n)
reg0_l_n : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => datain_in(0),
clk => neg_clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => dataout_reg_n(0)
);
-- datain_0 - L
reg0_l : stratixiii_ddr_io_reg
GENERIC MAP (power_up => power_up)
PORT MAP(
d => dataout_reg_n(0),
clk => clk_in,
ena => m_vcc,
clrn => m_vcc,
prn => m_vcc,
aload => aload_in_r,
asdata => adatasdata_in_r,
sclr => m_gnd,
sload => m_gnd,
devclrn => devclrn,
devpor => devpor,
q => low_bank_low
);
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
loopbits_datain : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
VitalWireDelay (directin_in, directin, tipd_directin);
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (areset_in, areset, tipd_areset);
VitalWireDelay (dataoutbypass_in, dataoutbypass, tipd_dataoutbypass);
end block;
END stratixiii_half_rate_input_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_io_config
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_io_config IS
GENERIC (
enhanced_mode : string := "false";
lpm_type : string := "stratixiii_io_config";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_update : VitalDelayType01 := DefpropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
update : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
-- new STRATIXIV: ww30.2008
dutycycledelaymode : OUT std_logic;
dutycycledelaysettings : OUT std_logic_vector(3 downto 0);
outputfinedelaysetting1 : OUT std_logic;
outputfinedelaysetting2 : OUT std_logic;
outputonlydelaysetting2 : OUT std_logic_vector(2 downto 0);
outputonlyfinedelaysetting2 : OUT std_logic;
padtoinputregisterfinedelaysetting : OUT std_logic;
padtoinputregisterdelaysetting : OUT std_logic_vector(3 downto 0);
outputdelaysetting1 : OUT std_logic_vector(3 downto 0);
outputdelaysetting2 : OUT std_logic_vector(2 downto 0);
dataout : OUT std_logic
);
END;
ARCHITECTURE stratixiii_io_config_arch OF stratixiii_io_config IS
-- component section
SIGNAL shift_reg : std_logic_vector(10 downto 0) := (OTHERS => '0');
SIGNAL output_reg : std_logic_vector(10 downto 0) := (OTHERS => '0');
SIGNAL tmp_output : std_logic_vector(10 downto 0) := (OTHERS => '0');
SIGNAL enhance_shift_reg : std_logic_vector(22 downto 0) := (OTHERS => '0');
SIGNAL enhance_output_reg : std_logic_vector(22 downto 0) := (OTHERS => '0');
SIGNAL enhance_tmp_output : std_logic_vector(22 downto 0) := (OTHERS => '0');
-- timing outputs
SIGNAL tmp_dataout : std_logic := '0';
-- timing inputs
SIGNAL datain_in : std_logic := '0';
SIGNAL clk_in : std_logic := '0';
SIGNAL ena_in : std_logic := '0';
SIGNAL update_in : std_logic := '0';
BEGIN
-- primary outputs
tmp_dataout <= enhance_shift_reg(22) WHEN (enhanced_mode = "true") ELSE shift_reg(10);
-- bit order changed in wys revision 1.32
outputdelaysetting1 <= tmp_output(3 DOWNTO 0);
outputdelaysetting2 <= tmp_output(6 DOWNTO 4);
padtoinputregisterdelaysetting <= tmp_output(10 DOWNTO 7);
-- padtoinputregisterdelaysetting <= tmp_output(3 DOWNTO 0);
-- outputdelaysetting1 <= tmp_output(7 DOWNTO 4);
-- outputdelaysetting2 <= tmp_output(10 DOWNTO 8);
tmp_output <= output_reg;
outputdelaysetting1 <= enhance_tmp_output(3 DOWNTO 0) WHEN (enhanced_mode = "true") ELSE tmp_output(3 DOWNTO 0);
outputdelaysetting2 <= enhance_tmp_output(6 DOWNTO 4) WHEN (enhanced_mode = "true") ELSE tmp_output(6 DOWNTO 4);
padtoinputregisterdelaysetting <= enhance_tmp_output(10 DOWNTO 7) WHEN (enhanced_mode = "true") ELSE tmp_output(10 DOWNTO 7);
outputfinedelaysetting1 <= enhance_tmp_output(11) WHEN (enhanced_mode = "true") ELSE '0';
outputfinedelaysetting2 <= enhance_tmp_output(12) WHEN (enhanced_mode = "true") ELSE '0';
padtoinputregisterfinedelaysetting <= enhance_tmp_output(13) WHEN (enhanced_mode = "true") ELSE '0';
outputonlyfinedelaysetting2 <= enhance_tmp_output(14) WHEN (enhanced_mode = "true") ELSE '0';
outputonlydelaysetting2 <= enhance_tmp_output(17 DOWNTO 15) WHEN (enhanced_mode = "true") ELSE "000";
dutycycledelaymode <= enhance_tmp_output(18) WHEN (enhanced_mode = "true") ELSE '0';
dutycycledelaysettings <= enhance_tmp_output(22 DOWNTO 19) WHEN (enhanced_mode = "true") ELSE "0000";
tmp_output <= output_reg;
enhance_tmp_output <= enhance_output_reg;
PROCESS(clk_in)
BEGIN
if (clk_in = '1' AND ena_in = '1') then
shift_reg(0) <= datain_in;
shift_reg(10 DOWNTO 1) <= shift_reg(9 DOWNTO 0);
enhance_shift_reg(0) <= datain_in;
enhance_shift_reg(22 DOWNTO 1) <= enhance_shift_reg(21 DOWNTO 0);
end if;
END PROCESS;
PROCESS(clk_in)
BEGIN
if (clk_in = '1' AND update_in = '1') then
output_reg <= shift_reg;
enhance_output_reg <= enhance_shift_reg;
end if;
END PROCESS;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (datain_in, datain, tipd_datain);
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (ena_in, ena, tipd_ena);
VitalWireDelay (update_in, update, tipd_update);
end block;
-----------------------------------
-- Timing Check Section
-----------------------------------
VITAL_timing_check: PROCESS (clk_in,datain_in,ena_in,update_in)
variable Tviol_clk_datain : std_ulogic := '0';
variable TimingData_clk_datain : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_clk_ena : std_ulogic := '0';
variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_clk_update : std_ulogic := '0';
variable TimingData_clk_update : VitalTimingDataType := VitalTimingDataInit;
BEGIN
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
Violation => Tviol_clk_datain,
TimingData => TimingData_clk_datain,
TestSignal => datain_in,
TestSignalName => "Datain",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_in,
TestSignalName => "Ena",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_clk_update,
TimingData => TimingData_clk_update,
TestSignal => update_in,
TestSignalName => "Update",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
END IF;
END PROCESS; -- timing check
--------------------------------------
-- Path Delay Section
--------------------------------------
VITAL_path_delays: PROCESS (tmp_dataout)
variable dataout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "Dataout",
OutTemp => tmp_dataout,
Paths => (0 => (clk_in'last_event, tpd_clk_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS; -- Path Delays
END stratixiii_io_config_arch;
-------------------------------------------------------------------------------
--
-- Entity Name : stratixiii_dqs_config
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_dqs_config IS
GENERIC (
enhanced_mode : string := "false";
lpm_type : string := "stratixiii_dqs_config";
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_update : VitalDelayType01 := DefpropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*"
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
ena : IN std_logic := '0';
update : IN std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1';
dqsbusoutfinedelaysetting : OUT std_logic; -- new in STRATIXIV
dqsenablefinedelaysetting : OUT std_logic; -- new in STRATIXIV
dqsbusoutdelaysetting : OUT std_logic_vector(3 downto 0);
dqsinputphasesetting : OUT std_logic_vector(2 downto 0);
dqsenablectrlphasesetting : OUT std_logic_vector(3 downto 0);
dqsoutputphasesetting : OUT std_logic_vector(3 downto 0);
dqoutputphasesetting : OUT std_logic_vector(3 downto 0);
resyncinputphasesetting : OUT std_logic_vector(3 downto 0);
dividerphasesetting : OUT std_logic;
enaoctcycledelaysetting : OUT std_logic;
enainputcycledelaysetting : OUT std_logic;
enaoutputcycledelaysetting: OUT std_logic;
dqsenabledelaysetting : OUT std_logic_vector(2 downto 0);
octdelaysetting1 : OUT std_logic_vector(3 downto 0);
octdelaysetting2 : OUT std_logic_vector(2 downto 0);
enadataoutbypass : OUT std_logic;
enadqsenablephasetransferreg : OUT std_logic;
enaoctphasetransferreg : OUT std_logic;
enaoutputphasetransferreg : OUT std_logic;
enainputphasetransferreg : OUT std_logic;
resyncinputphaseinvert : OUT std_logic;
dqsenablectrlphaseinvert : OUT std_logic;
dqoutputphaseinvert : OUT std_logic;
dqsoutputphaseinvert : OUT std_logic;
dataout : OUT std_logic
);
END;
ARCHITECTURE stratixiii_dqs_config_arch OF stratixiii_dqs_config IS
-- component section
SIGNAL shift_reg : STD_LOGIC_VECTOR (47 DOWNTO 0) := (OTHERS => '0');
SIGNAL output_reg : STD_LOGIC_VECTOR (47 DOWNTO 0) := (OTHERS => '0');
SIGNAL tmp_output : STD_LOGIC_VECTOR (47 DOWNTO 0) := (OTHERS => '0');
-- timing outputs
SIGNAL tmp_dataout : std_logic := '0';
-- timing inputs
SIGNAL datain_in : std_logic := '0';
SIGNAL clk_in : std_logic := '0';
SIGNAL ena_in : std_logic := '0';
SIGNAL update_in : std_logic := '0';
BEGIN
-- primary outputs
tmp_dataout <= shift_reg(47) WHEN (enhanced_mode = "true")ELSE shift_reg(45);
dqsbusoutdelaysetting <= tmp_output(3 DOWNTO 0);
dqsinputphasesetting <= tmp_output(6 DOWNTO 4);
dqsenablectrlphasesetting <= tmp_output(10 DOWNTO 7);
dqsoutputphasesetting <= tmp_output(14 DOWNTO 11);
dqoutputphasesetting <= tmp_output(18 DOWNTO 15);
resyncinputphasesetting <= tmp_output(22 DOWNTO 19);
dividerphasesetting <= tmp_output(23);
enaoctcycledelaysetting <= tmp_output(24);
enainputcycledelaysetting <= tmp_output(25);
enaoutputcycledelaysetting<= tmp_output(26);
dqsenabledelaysetting <= tmp_output(29 DOWNTO 27);
octdelaysetting1 <= tmp_output(33 DOWNTO 30);
octdelaysetting2 <= tmp_output(36 DOWNTO 34);
enadataoutbypass <= tmp_output(37);
enadqsenablephasetransferreg <= tmp_output(38); -- new in 1.23
enaoctphasetransferreg <= tmp_output(39); -- new in 1.23
enaoutputphasetransferreg <= tmp_output(40); -- new in 1.23
enainputphasetransferreg <= tmp_output(41); -- new in 1.23
resyncinputphaseinvert <= tmp_output(42); -- new in 1.26
dqsenablectrlphaseinvert <= tmp_output(43); -- new in 1.26
dqoutputphaseinvert <= tmp_output(44); -- new in 1.26
dqsoutputphaseinvert <= tmp_output(45); -- new in 1.26
-- new in STRATIXIV: ww30.2008
dqsbusoutfinedelaysetting <= tmp_output(46) WHEN (enhanced_mode = "true") ELSE '0';
dqsenablefinedelaysetting <= tmp_output(47) WHEN (enhanced_mode = "true") ELSE '0';
tmp_output <= output_reg;
PROCESS(clk_in)
begin
if (clk_in = '1' AND ena_in = '1') then
shift_reg(0) <= datain_in;
shift_reg(47 DOWNTO 1) <= shift_reg(46 DOWNTO 0);
end if;
end process;
PROCESS(clk_in)
begin
if (clk_in = '1' AND update_in = '1') then
output_reg <= shift_reg;
end if;
end process;
--------------------
-- INPUT PATH DELAYS
--------------------
WireDelay : block
begin
VitalWireDelay (datain_in, datain, tipd_datain);
VitalWireDelay (clk_in, clk, tipd_clk);
VitalWireDelay (ena_in, ena, tipd_ena);
VitalWireDelay (update_in, update, tipd_update);
end block;
-----------------------------------
-- Timing Check Section
-----------------------------------
VITAL_timing_check: PROCESS (clk_in,datain_in,ena_in,update_in)
variable Tviol_clk_datain : std_ulogic := '0';
variable TimingData_clk_datain : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_clk_ena : std_ulogic := '0';
variable TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_clk_update : std_ulogic := '0';
variable TimingData_clk_update : VitalTimingDataType := VitalTimingDataInit;
BEGIN
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
Violation => Tviol_clk_datain,
TimingData => TimingData_clk_datain,
TestSignal => datain_in,
TestSignalName => "Datain",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_in,
TestSignalName => "Ena",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
VitalSetupHoldCheck (
Violation => Tviol_clk_update,
TimingData => TimingData_clk_update,
TestSignal => update_in,
TestSignalName => "Update",
RefSignal => clk_in,
RefSignalName => "clk",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
RefTransition => '/',
HeaderMsg => InstancePath & "/STRATIXIII_IO_CONFIG",
XOn => XOnChecks,
MsgOn => MsgOnChecks
);
END IF;
END PROCESS; -- timing check
--------------------------------------
-- Path Delay Section
--------------------------------------
VITAL_path_delays: PROCESS (tmp_dataout)
variable dataout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "Dataout",
OutTemp => tmp_dataout,
Paths => (0 => (clk_in'last_event, tpd_clk_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
END PROCESS; -- Path Delays
END stratixiii_dqs_config_arch;
-------------------------------------------------------------------------------
-- Module Name: stratixiii_mac_bit_register --
-- Description: Stratix III MAC single bit register --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_mac_bit_register IS
GENERIC (
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic
);
END stratixiii_mac_bit_register;
ARCHITECTURE arch OF stratixiii_mac_bit_register IS
SIGNAL datain_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL aclr_ipd : std_logic := '0';
SIGNAL sload_ipd : std_logic := '1';
SIGNAL dataout_tmp : std_logic := '0';
SIGNAL dataout_reg : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
end block;
PROCESS(clk_ipd, datain_ipd, sload_ipd, aclr_ipd)
variable Tviol_datain_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
VARIABLE CQDelay : TIME := 0 ns;
BEGIN
IF (aclr_ipd = '1') THEN
dataout_reg <= '0';
ELSIF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (sload_ipd = '1') THEN
dataout_reg <= datain_ipd;
ELSE
dataout_reg <= dataout_reg;
END IF;
END IF;
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge,
SetupLow => tsetup_datain_clk_noedge_posedge,
HoldHigh => thold_datain_clk_noedge_posedge,
HoldLow => thold_datain_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT aclr_ipd) OR
(sload_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC Register VitalSetupHoldCheck",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT aclr_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC Register VitalSetupHoldCheck",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
END PROCESS;
dataout_tmp <= datain_ipd WHEN bypass_register = '1' ELSE dataout_reg;
PROCESS(dataout_tmp)
variable dataout_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => dataout_tmp,
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
END PROCESS;
END arch;
-------------------------------------------------------------------------------
-- Module Name: stratixiii_mac_register --
-- Description: Stratix III MAC variable width register --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_mac_register IS
GENERIC (
data_width : integer := 18;
tipd_datain : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tsetup_datain_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_datain_clk_noedge_posedge : VitalDelayArrayType(71 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
datain : IN std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width - 1 DOWNTO 0)
);
END stratixiii_mac_register;
ARCHITECTURE arch OF stratixiii_mac_register IS
SIGNAL datain_ipd : std_logic_vector(data_width -1 downto 0) := (others => '0');
SIGNAL clk_ipd : std_logic := '0';
SIGNAL aclr_ipd : std_logic := '0';
SIGNAL sload_ipd : std_logic := '1';
SIGNAL dataout_tmp : std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
SIGNAL dataout_reg : std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
g1 :for i in datain'range generate
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
end block;
PROCESS(clk_ipd, datain_ipd, sload_ipd, aclr_ipd)
BEGIN
IF (aclr_ipd = '1') THEN
dataout_reg <= (OTHERS => '0');
ELSIF (clk_ipd'EVENT AND clk_ipd = '1') THEN
IF (sload_ipd = '1') THEN
dataout_reg <= datain_ipd;
ELSE
dataout_reg <= dataout_reg;
END IF;
END IF;
END process;
sh: block
begin
g0 : for i in datain'range generate
process(datain_ipd(i),clk_ipd,sload_ipd)
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(71 downto 0);
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_datain_clk : std_ulogic := '0';
variable TimingData_datain_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
begin
VitalSetupHoldCheck (
Violation => Tviol_datain_clk,
TimingData => TimingData_datain_clk,
TestSignal => datain_ipd(i),
TestSignalName => "DATAIN(i)",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_datain_clk_noedge_posedge(i),
SetupLow => tsetup_datain_clk_noedge_posedge(i),
HoldHigh => thold_datain_clk_noedge_posedge(i),
HoldLow => thold_datain_clk_noedge_posedge(i),
CheckEnabled => TO_X01((NOT aclr_ipd) OR
(sload_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT aclr_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/MAC_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
END PROCESS;
end generate g0;
end block;
dataout_tmp <= datain_ipd WHEN bypass_register = '1' ELSE dataout_reg;
PathDelay : block
begin
g1 : for i in dataout'range generate
PROCESS (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE );
end process;
end generate;
end block;
END arch;
-------------------------------------------------------------------------------
-- Module Name: stratixiii_mac_multiplier --
-- Description: Stratix III MAC signed multiplier --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_mac_multiplier IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
tipd_dataa : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36-1 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0)
);
END stratixiii_mac_multiplier;
ARCHITECTURE arch OF stratixiii_mac_multiplier IS
constant dataout_width : integer := dataa_width + datab_width;
SIGNAL product : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
SIGNAL abs_product : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
SIGNAL abs_a : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
SIGNAL abs_b : std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
SIGNAL dataout_tmp : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
SIGNAL product_sign : std_logic := '0';
SIGNAL dataa_sign : std_logic := '0';
SIGNAL datab_sign : std_logic := '0';
SIGNAL dataa_ipd : std_logic_vector(dataa_width -1 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(datab_width -1 DOWNTO 0) := (others => '0');
SIGNAL signa_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signb, tipd_signb);
end block;
dataa_sign <= dataa_ipd(dataa_width - 1) AND signa_ipd ;
datab_sign <= datab_ipd(datab_width - 1) AND signb_ipd ;
product_sign <= dataa_sign XOR datab_sign ;
abs_a <= (NOT dataa_ipd + '1') WHEN dataa_sign = '1' ELSE dataa_ipd;
abs_b <= (NOT datab_ipd + '1') WHEN datab_sign = '1' ELSE datab_ipd;
abs_product <= abs_a * abs_b ;
dataout_tmp <= (NOT abs_product + 1) WHEN product_sign = '1' ELSE abs_product;
PathDelay : block
begin
do : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (signa'last_event, tpd_signa_dataout(i), TRUE),
3 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do;
end block;
END arch;
----------------------------------------------------------------------------------
-- Module Name: stratixiii_mac_mult_atom --
-- Description: Simulation model for stratixiii mac mult atom. --
-- This model instantiates the following components. --
-- 1.stratixiii_mac_bit_register. --
-- 2.stratixiii_mac_register. --
-- 3.stratixiii_mac_multiplier. --
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_mac_mult IS
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
scanouta_clock : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
scanouta_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_type : string := "stratixiii_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0);
scanouta : OUT std_logic_vector(dataa_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiii_mac_mult;
ARCHITECTURE arch OF stratixiii_mac_mult IS
constant dataout_width : integer := dataa_width + datab_width;
COMPONENT stratixiii_mac_bit_register
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT stratixiii_mac_register
GENERIC (
data_width : integer := 18
);
PORT (
datain : IN std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width - 1 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiii_mac_multiplier
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(dataa_width + datab_width - 1 DOWNTO 0)
);
END COMPONENT;
--Internal signals to instantiate the dataa input register unit
SIGNAL dataa_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL dataa_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL dataa_clk : std_logic := '0';
SIGNAL dataa_aclr : std_logic := '0';
SIGNAL dataa_sload : std_logic := '0';
SIGNAL dataa_bypass_register : std_logic := '0';
SIGNAL dataa_in_reg : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
SIGNAL dataa_in : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
--Internal signals to instantiate the datab input register unit
SIGNAL datab_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL datab_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL datab_clk : std_logic := '0';
SIGNAL datab_aclr : std_logic := '0';
SIGNAL datab_sload : std_logic := '0';
SIGNAL datab_bypass_register : std_logic := '0';
SIGNAL datab_in_reg : std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
SIGNAL datab_in : std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
--Internal signals to instantiate the signa input register unit
SIGNAL signa_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk : std_logic := '0';
SIGNAL signa_aclr : std_logic := '0';
SIGNAL signa_sload : std_logic := '0';
SIGNAL signa_bypass_register : std_logic := '0';
SIGNAL signa_in_reg : std_logic := '0';
SIGNAL signa_in : std_logic := '0';
--Internal signbls to instantiate the signb input register unit
SIGNAL signb_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk : std_logic := '0';
SIGNAL signb_aclr : std_logic := '0';
SIGNAL signb_sload : std_logic := '0';
SIGNAL signb_bypass_register : std_logic := '0';
SIGNAL signb_in_reg : std_logic := '0';
SIGNAL signb_in : std_logic := '0';
--Internal scanoutals to instantiate the scanouta input register unit
SIGNAL scanouta_clk_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL scanouta_aclr_value : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL scanouta_clk : std_logic := '0';
SIGNAL scanouta_aclr : std_logic := '0';
SIGNAL scanouta_sload : std_logic := '0';
SIGNAL scanouta_bypass_register : std_logic := '0';
SIGNAL scanouta_tmp : std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
--Internal Signals to instantiate the mac multiplier
SIGNAL signa_mult : std_logic := '0';
SIGNAL signb_mult : std_logic := '0';
SIGNAL dataout_tmp : std_logic_vector(dataout_width - 1 DOWNTO 0):= (others => '0');
BEGIN
--Instantiate the dataa input Register
dataa_clk_value <= "0000" WHEN ((dataa_clock = "0") or (dataa_clock = "none"))
ELSE "0001" WHEN (dataa_clock = "1")
ELSE "0010" WHEN (dataa_clock = "2")
ELSE "0011" WHEN (dataa_clock = "3")
ELSE "0000" ;
dataa_aclr_value <= "0000" WHEN ((dataa_clear = "0") or (dataa_clear = "none"))
ELSE "0001" WHEN (dataa_clear = "1")
ELSE "0010" WHEN (dataa_clear = "2")
ELSE "0011" WHEN (dataa_clear = "3")
ELSE "0000" ;
dataa_clk <= '1' WHEN clk(conv_integer(dataa_clk_value)) = '1' ELSE '0';
dataa_aclr <= '1' WHEN (aclr(conv_integer(dataa_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
dataa_sload <= '1' WHEN ena(conv_integer(dataa_clk_value)) = '1' ELSE '0';
dataa_bypass_register <= '1' WHEN (dataa_clock = "none") ELSE '0';
dataa_in <= dataa;
dataa_input_register : stratixiii_mac_register
GENERIC MAP (
data_width => dataa_width
)
PORT MAP (
datain => dataa_in,
clk => dataa_clk,
aclr => dataa_aclr,
sload => dataa_sload,
bypass_register => dataa_bypass_register,
dataout => dataa_in_reg
);
--Instantiate the datab input Register
datab_clk_value <= "0000" WHEN ((datab_clock = "0") or (datab_clock = "none"))
ELSE "0001" WHEN (datab_clock = "1")
ELSE "0010" WHEN (datab_clock = "2")
ELSE "0011" WHEN (datab_clock = "3")
ELSE "0000" ;
datab_aclr_value <= "0000" WHEN ((datab_clear = "0") or (datab_clear = "none"))
ELSE "0001" WHEN (datab_clear = "1")
ELSE "0010" WHEN (datab_clear = "2")
ELSE "0011" WHEN (datab_clear = "3")
ELSE "0000" ;
datab_clk <= '1' WHEN clk(conv_integer(datab_clk_value)) = '1' ELSE '0';
datab_aclr <= '1' WHEN (aclr(conv_integer(datab_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
datab_sload <= '1' WHEN ena(conv_integer(datab_clk_value)) = '1' ELSE '0';
datab_bypass_register <= '1' WHEN (datab_clock = "none") ELSE '0';
datab_in <= datab;
datab_input_register : stratixiii_mac_register
GENERIC MAP (
data_width => datab_width
)
PORT MAP (
datain => datab_in,
clk => datab_clk,
aclr => datab_aclr,
sload => datab_sload,
bypass_register => datab_bypass_register,
dataout => datab_in_reg
);
--Instantiate the signa input Register
signa_clk_value <= "0000" WHEN ((signa_clock = "0") or (signa_clock = "none"))
ELSE "0001" WHEN (signa_clock = "1")
ELSE "0010" WHEN (signa_clock = "2")
ELSE "0011" WHEN (signa_clock = "3")
ELSE "0000" ;
signa_aclr_value <= "0000" WHEN ((signa_clear = "0") or (signa_clear = "none"))
ELSE "0001" WHEN (signa_clear = "1")
ELSE "0010" WHEN (signa_clear = "2")
ELSE "0011" WHEN (signa_clear = "3")
ELSE "0000" ;
signa_clk <= '1' WHEN clk(conv_integer(signa_clk_value)) = '1' ELSE '0';
signa_aclr <= '1' WHEN (aclr(conv_integer(signa_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
signa_sload <= '1' WHEN ena(conv_integer(signa_clk_value)) = '1' ELSE '0';
signa_bypass_register <= '1' WHEN (signa_clock = "none") ELSE '0';
signa_in <= signa;
signa_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => signa_in,
clk => signa_clk,
aclr => signa_aclr,
sload => signa_sload,
bypass_register => signa_bypass_register,
dataout => signa_in_reg
);
--Instantiate the signb input Register
signb_clk_value <= "0000" WHEN ((signb_clock = "0") or (signb_clock = "none"))
ELSE "0001" WHEN (signb_clock = "1")
ELSE "0010" WHEN (signb_clock = "2")
ELSE "0011" WHEN (signb_clock = "3")
ELSE "0000" ;
signb_aclr_value <= "0000" WHEN ((signb_clear = "0") or (signb_clear = "none"))
ELSE "0001" WHEN (signb_clear = "1")
ELSE "0010" WHEN (signb_clear = "2")
ELSE "0011" WHEN (signb_clear = "3")
ELSE "0000" ;
signb_clk <= '1' WHEN clk(conv_integer(signb_clk_value)) = '1' ELSE '0';
signb_aclr <= '1' WHEN (aclr(conv_integer(signb_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
signb_sload <= '1' WHEN ena(conv_integer(signb_clk_value)) = '1' ELSE '0';
signb_bypass_register <= '1' WHEN (signb_clock = "none") ELSE '0';
signb_in <= signb;
signb_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => signb_in,
clk => signb_clk,
aclr => signb_aclr,
sload => signb_sload,
bypass_register => signb_bypass_register,
dataout => signb_in_reg
);
--Instantiate the scanouta input Register
scanouta_clk_value <= "0000" WHEN ((scanouta_clock = "0") or (scanouta_clock = "none"))
ELSE "0001" WHEN (scanouta_clock = "1")
ELSE "0010" WHEN (scanouta_clock = "2")
ELSE "0011" WHEN (scanouta_clock = "3")
ELSE "0000" ;
scanouta_aclr_value <= "0000" WHEN ((scanouta_clear = "0") or (scanouta_clear = "none"))
ELSE "0001" WHEN (scanouta_clear = "1")
ELSE "0010" WHEN (scanouta_clear = "2")
ELSE "0011" WHEN (scanouta_clear = "3")
ELSE "0000" ;
scanouta_clk <= '1' WHEN clk(conv_integer(scanouta_clk_value)) = '1' ELSE '0';
scanouta_aclr <= '1' WHEN (aclr(conv_integer(scanouta_aclr_value)) OR (NOT devclrn) OR (NOT devpor)) = '1' ELSE '0';
scanouta_sload <= '1' WHEN ena(conv_integer(scanouta_clk_value)) = '1' ELSE '0';
scanouta_bypass_register <= '1' WHEN (scanouta_clock = "none") ELSE '0';
scanouta_input_register : stratixiii_mac_register
GENERIC MAP (
data_width => dataa_width
)
PORT MAP (
datain => dataa_in_reg,
clk => scanouta_clk,
aclr => scanouta_aclr,
sload => scanouta_sload,
bypass_register => scanouta_bypass_register,
dataout => scanouta
);
--Instantiate mac_multiplier block
signa_mult <= '0' WHEN (signa_internally_grounded = "true") ELSE signa_in_reg;
signb_mult <= '0' WHEN (signb_internally_grounded = "true") ELSE signb_in_reg;
mac_multiplier : stratixiii_mac_multiplier
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width
)
PORT MAP (
dataa => dataa_in_reg,
datab => datab_in_reg,
signa => signa_mult,
signb => signb_mult,
dataout => dataout
);
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiii_fsa_isse --
-- Description: Stratix III first stage adder input selection and sign extension block. --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_fsa_isse IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
datac_width : integer := 36;
datad_width : integer := 36;
chainin_width : integer := 44;
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
operation_mode : string := "output_only"
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0);
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0);
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0);
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0);
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0);
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataa_out : OUT std_logic_vector(71 DOWNTO 0);
datab_out : OUT std_logic_vector(71 DOWNTO 0);
datac_out : OUT std_logic_vector(71 DOWNTO 0);
datad_out : OUT std_logic_vector(71 DOWNTO 0);
chainin_out : OUT std_logic_vector(71 DOWNTO 0);
operation : OUT std_logic_vector(3 DOWNTO 0)
);
END stratixiii_fsa_isse;
ARCHITECTURE arch OF stratixiii_fsa_isse IS
signal dataa_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal datab_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal datac_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal datad_out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
signal chainin_out_tmp: std_logic_vector(71 DOWNTO 0) := (others => '0');
signal sign :std_logic := '0';
BEGIN
operation <= "0000" WHEN (operation_mode = "output_only") ELSE
"0001" WHEN (operation_mode = "one_level_adder") ELSE
"0010" WHEN (operation_mode = "loopback") ELSE
"0011" WHEN (operation_mode = "accumulator") ELSE
"0100" WHEN (operation_mode = "accumulator_chain_out") ELSE
"0101" WHEN (operation_mode = "two_level_adder") ELSE
"0110" WHEN (operation_mode = "two_level_adder_chain_out") ELSE
"0111" WHEN (operation_mode = "36_bit_multiply") ELSE
"1000" WHEN (operation_mode = "shift") ELSE
"1001" WHEN (operation_mode = "double") ELSE "0000";
sign <= signa or signb;
PROCESS( dataa,datab,datac,datad,chainin,signa,signb)
variable active_signb : std_logic := '0';
variable active_signc : std_logic := '0';
variable active_signd : std_logic := '0';
variable read_new_param : std_logic := '0';
variable datab_out_tim_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datac_out_tim_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datad_out_tim_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datab_out_fun_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datac_out_fun_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable datad_out_fun_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
IF ( multa_signa_internally_grounded = "false" AND multa_signb_internally_grounded = "false"
AND multb_signa_internally_grounded = "false" AND multb_signb_internally_grounded = "false"
AND multc_signa_internally_grounded = "false" AND multc_signb_internally_grounded = "false"
AND multd_signa_internally_grounded = "false" AND multd_signb_internally_grounded = "false") THEN
read_new_param := '0' ;
ELSE
read_new_param := '1' ;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift") or (operation_mode = "double")) THEN
if (multb_signb_internally_grounded = "false" AND multb_signa_internally_grounded = "true") then
active_signb := signb;
elsif(multb_signb_internally_grounded = "true" AND multb_signa_internally_grounded = "false" ) then
active_signb := signa;
elsif(multb_signb_internally_grounded = "false" AND multb_signa_internally_grounded = "false") then
active_signb := sign;
else
active_signb := '0';
end if;
ELSE
active_signb := sign;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift") or (operation_mode = "double")) THEN
if (multc_signb_internally_grounded = "false" AND multc_signa_internally_grounded = "true") then
active_signc := signb;
elsif(multc_signb_internally_grounded = "true" AND multc_signa_internally_grounded = "false" ) then
active_signc := signa;
elsif(multc_signb_internally_grounded = "false" AND multc_signa_internally_grounded = "false") then
active_signc := sign;
else
active_signc := '0';
end if;
ELSE
active_signc := sign;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift") or (operation_mode = "double")) THEN
if (multd_signb_internally_grounded = "false" AND multd_signa_internally_grounded = "true") then
active_signd := signb;
elsif(multd_signb_internally_grounded = "true" AND multd_signa_internally_grounded = "false" ) then
active_signd := signa;
elsif(multd_signb_internally_grounded = "false" AND multd_signa_internally_grounded = "false") then
active_signd := sign;
else
active_signd := '0';
end if;
ELSE
active_signd := sign;
END IF;
IF (dataa(dataa_width - 1) = '1' AND sign = '1') THEN
dataa_out_tmp <= sxt(dataa(dataa_width - 1 DOWNTO 0), 72);
ELSE
dataa_out_tmp <= ext(dataa(dataa_width - 1 DOWNTO 0), 72);
END IF;
IF (datab(datab_width - 1) = '1' AND active_signb = '1') THEN
datab_out_tim_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_tim_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
IF (datac(datac_width - 1) = '1' AND active_signc = '1') THEN
datac_out_tim_tmp := sxt(datac(datac_width - 1 DOWNTO 0), 72);
ELSE
datac_out_tim_tmp := ext(datac(datac_width - 1 DOWNTO 0), 72);
END IF;
IF (datad(datad_width - 1) = '1' AND active_signd = '1') THEN
datad_out_tim_tmp := sxt(datad(datad_width - 1 DOWNTO 0), 72);
ELSE
datad_out_tim_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift")) THEN
IF(datab(datab_width - 1) = '1' AND signb = '1') THEN
datab_out_fun_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_fun_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
ELSIF(operation_mode = "double") THEN
IF(datab(datab_width - 1) = '1' AND signa = '1') THEN
datab_out_fun_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_fun_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (datab(datab_width - 1) = '1' AND sign = '1') THEN
datab_out_fun_tmp := sxt(datab(datab_width - 1 DOWNTO 0), 72);
ELSE
datab_out_fun_tmp := ext(datab(datab_width - 1 DOWNTO 0), 72);
END IF;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift")) THEN
IF (datac(datac_width - 1) = '1' AND signa = '1') THEN
datac_out_fun_tmp := sxt(datac(datac_width - 1 DOWNTO 0), 72);
ELSE
datac_out_fun_tmp := ext(datac(datac_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (datac(datac_width - 1) = '1' AND sign = '1') THEN
datac_out_fun_tmp := sxt(datac(datac_width - 1 DOWNTO 0), 72);
ELSE
datac_out_fun_tmp := ext(datac(datac_width - 1 DOWNTO 0), 72);
END IF;
END IF;
IF ((operation_mode = "36_bit_multiply") or (operation_mode = "shift")) THEN
datad_out_fun_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
ELSIF(operation_mode = "double")THEN
IF (datad(datad_width - 1) = '1' AND signa = '1') THEN
datad_out_fun_tmp := sxt(datad(datad_width - 1 DOWNTO 0), 72);
ELSE
datad_out_fun_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
END IF;
ELSE
IF (datad(datad_width - 1) = '1' AND sign = '1') THEN
datad_out_fun_tmp := sxt(datad(datad_width - 1 DOWNTO 0), 72);
ELSE
datad_out_fun_tmp := ext(datad(datad_width - 1 DOWNTO 0), 72);
END IF;
END IF;
IF (chainin(chainin_width - 1) = '1') THEN
chainin_out_tmp <= sxt(chainin(chainin_width - 1 DOWNTO 0), 72);
ELSE
chainin_out_tmp <= ext(chainin(chainin_width - 1 DOWNTO 0), 72);
END IF;
IF(read_new_param = '1') THEN
datab_out_tmp <= datab_out_tim_tmp;
datac_out_tmp <= datac_out_tim_tmp;
datad_out_tmp <= datad_out_tim_tmp;
ELSE
datab_out_tmp <= datab_out_fun_tmp;
datac_out_tmp <= datac_out_fun_tmp;
datad_out_tmp <= datad_out_fun_tmp;
END IF;
END process;
dataa_out <= dataa_out_tmp;
datab_out <= datab_out_tmp;
datac_out <= datac_out_tmp;
datad_out <= datad_out_tmp;
chainin_out <= chainin_out_tmp;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiii_first_stage_add_sub --
-- Description: Stratix III First Stage Adder Subtractor Unit --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_first_stage_add_sub IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
fsa_mode : string := "add";
tipd_dataa : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_sign : VitalDelayType01 :=DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_sign_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END stratixiii_first_stage_add_sub;
ARCHITECTURE arch OF stratixiii_first_stage_add_sub IS
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL abs_b : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL abs_a : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign_a : std_logic := '0';
SIGNAL sign_b : std_logic := '0';
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign_ipd : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
VitalWireDelay (sign_ipd, sign, tipd_sign);
end block;
PROCESS
BEGIN
WAIT UNTIL dataa_ipd'EVENT OR datab_ipd'EVENT OR sign_ipd'EVENT OR operation'EVENT;
IF ((operation = "0111") OR (operation = "1000")or (operation = "1001")) THEN --36 std_logic multiply, shift and add
dataout_tmp <= dataa_ipd(53 DOWNTO 36) & dataa_ipd(35 DOWNTO 0) & "000000000000000000" + datab_ipd;
ELSE
IF(fsa_mode = "add")THEN
IF (sign_ipd = '1') THEN
dataout_tmp <= signed(dataa_ipd) + signed(datab_ipd);
ELSE
dataout_tmp <= unsigned(dataa_ipd) + unsigned(datab_ipd);
END IF;
ELSE
IF (sign_ipd = '1') THEN
dataout_tmp <= signed(dataa_ipd) - signed(datab_ipd);
ELSE
dataout_tmp <= unsigned(dataa_ipd) - unsigned(datab_ipd);
END IF;
END IF;
END IF;
END process ;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (sign'last_event, tpd_sign_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiii_second_stage_add_accum --
-- Description: Stratix III Second stage Adder and Accumulator/Decimator Unit --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_second_stage_add_accum IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
ssa_mode : string := "add";
tipd_dataa : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_accumin : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_sign : VitalDelayType01 :=DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_accumin_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_sign_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_dataa_overflow : VitalDelayType01 := DefPropDelay01;
tpd_datab_overflow : VitalDelayType01 := DefPropDelay01;
tpd_accumin_overflow : VitalDelayType01 := DefPropDelay01;
tpd_sign_overflow : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
accumin : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic
);
END stratixiii_second_stage_add_accum;
ARCHITECTURE arch OF stratixiii_second_stage_add_accum IS
constant accum_width : integer := dataa_width + 7;
SIGNAL dataout_temp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataa_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL accum_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL overflow_tmp : std_logic := '0';
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL accumin_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
g3 :for i in accumin'range generate
VitalWireDelay (accumin_ipd(i), accumin(i), tipd_accumin(i));
end generate;
VitalWireDelay (sign_ipd, sign, tipd_sign);
end block;
PROCESS
Variable dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
WAIT UNTIL dataa_ipd'EVENT OR datab_ipd'EVENT OR sign_ipd'EVENT OR accumin_ipd'EVENT OR operation'EVENT;
IF (operation = "0011" OR operation = "0100") THEN --Accumultor or Accumulator chainout
IF(ssa_mode = "add")THEN
IF (sign_ipd = '1') THEN
dataout_tmp := signed(sxt(accumin_ipd(accum_width-1 downto 0),72)) + signed(sxt(dataa_ipd(accum_width-1 downto 0),72)) + signed(sxt(datab_ipd(accum_width-1 downto 0),72));
ELSE
dataout_tmp := unsigned(ext(accumin_ipd(accum_width-1 downto 0),72)) + unsigned(ext(dataa_ipd(accum_width-1 downto 0),72)) + unsigned(ext(datab_ipd(accum_width-1 downto 0),72));
END IF;
ELSE
IF (sign_ipd = '1') THEN
dataout_tmp := signed(accumin_ipd) - signed(dataa_ipd)- signed(datab_ipd);
ELSE
dataout_tmp := unsigned(accumin_ipd) - unsigned(dataa_ipd)- unsigned(datab_ipd);
END IF;
END IF;
IF(sign_ipd = '1')THEN
overflow_tmp <= dataout_tmp(accum_width) xor dataout_tmp(accum_width -1);
ELSE
IF(ssa_mode = "add")THEN
overflow_tmp <= dataout_tmp(accum_width);
ELSE
overflow_tmp <= 'X';
END IF;
END IF;
ELSIF (operation = "0101" OR operation = "0110") THEN -- two level adder or two level with chainout
overflow_tmp <= '0';
IF (sign_ipd = '1') THEN
dataout_tmp := signed(dataa_ipd) + signed(datab_ipd);
ELSE
dataout_tmp := unsigned(dataa_ipd) + unsigned(datab_ipd);
END IF;
ELSIF ((operation = "0111") OR (operation = "1000")) THEN --36 std_logic multiply; shift and add
dataout_tmp(71 DOWNTO 0) := dataa_ipd(53 DOWNTO 0) & "000000000000000000" + datab_ipd;
overflow_tmp <= '0';
ELSIF ((operation = "1001")) THEN --double mode
dataout_tmp(71 DOWNTO 0) := dataa_ipd + datab_ipd;
overflow_tmp <= '0';
END IF;
dataout_temp <= dataout_tmp;
END PROCESS;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_temp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_temp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (accumin_ipd'last_event, tpd_accumin_dataout(i), TRUE),
3 => (sign'last_event, tpd_sign_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
process(overflow_tmp)
VARIABLE overflow_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => overflow,
OutSignalName => "overflow",
OutTemp => overflow_tmp,
paths => (0 => (dataa_ipd'last_event, tpd_dataa_overflow, TRUE),
1 => (datab_ipd'last_event, tpd_datab_overflow, TRUE),
2 => (accumin_ipd'last_event, tpd_accumin_overflow, TRUE),
3 => (sign'last_event, tpd_sign_overflow, TRUE)),
GlitchData => overflow_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE
);
end process;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiii_round_block --
-- Description: Stratix III round block --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_round_block IS
GENERIC (
round_mode : string := "nearest_integer";
round_width : integer := 15;
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0):= (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END stratixiii_round_block;
ARCHITECTURE arch OF stratixiii_round_block IS
signal out_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
dataout <= out_tmp ;
PROCESS(datain,round,datain_width)
variable i : integer ;
variable j : integer ;
variable sign : std_logic ;
variable result_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
variable dataout_value : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
if(round = '0')then
dataout_value := datain;
else
dataout_value := datain;
j := 0;
sign := '0';
IF( conv_integer(datain_width) > round_width) THEN
for i in ((conv_integer(datain_width)) - round_width) to (conv_integer(datain_width) -1) loop
result_tmp(j) := datain(i);
j := j + 1;
END LOOP;
for i in 0 to (conv_integer(datain_width) - round_width -2) loop
sign := sign or datain(i);
dataout_value(i) := 'X';
END LOOP;
dataout_value((conv_integer(datain_width)) - round_width -1) := 'X';
IF (datain(conv_integer(datain_width) - round_width -1) = '0') THEN -- fractional < 0.5
dataout_tmp := result_tmp;
ELSE
IF ((datain(conv_integer(datain_width) - round_width -1) = '1') AND (sign = '1')) THEN --fractional > 0.5
dataout_tmp := result_tmp + '1';
ELSE
IF (round_mode = "nearest_even") THEN --unbiased rounding
IF(result_tmp(0) = '1') THEN --check for odd integer
dataout_tmp := result_tmp + '1' ;
ELSE
dataout_tmp := result_tmp;
END IF;
ELSE --biased rounding
dataout_tmp := result_tmp + '1';
END IF;
END IF;
END IF;
j := conv_integer(datain_width) - round_width;
FOR i IN 0 to (round_width -1)LOOP
dataout_value(j) := dataout_tmp(i);
j := j + 1;
END LOOP;
ELSE
dataout_value := datain;
END IF;
end if;
out_tmp <= dataout_value;
END PROCESS;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiii_saturate_block --
-- Description: Stratix III saturation block --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_saturate_block IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
saturate_width : integer := 15;
round_width : integer := 15;
saturate_mode : string := " asymmetric";
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
saturate : IN std_logic := '0';
round : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0):= (others => '0');
saturation_overflow : OUT std_logic
);
END stratixiii_saturate_block;
ARCHITECTURE arch OF stratixiii_saturate_block IS
constant accum_width : integer := dataa_width + 8;
SIGNAL saturation_overflow_tmp : std_logic := '0';
signal msb : std_logic := '0';
signal sign : std_logic := '0';
signal min : std_logic_vector(71 downto 0):=(others => '1');
signal max : std_logic_vector(71 downto 0):=(others => '0');
signal dataout_tmp : std_logic_vector(71 DOWNTO 0):= (others => '0');
SIGNAL i : integer;
BEGIN
sign <= signa OR signb ;
msb <= datain(accum_width) when ((operation_mode = "accumulator") or (operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out"))
ELSE datain(dataa_width +1) when(operation_mode = "two_level_adder")
ELSE datain(dataa_width) when((operation_mode = "one_level_adder")or (operation_mode = "loopback"))
ELSE datain(dataa_width -1);
dataout <= dataout_tmp ;
saturation_overflow <= saturation_overflow_tmp ;
PROCESS(datain,datain_width,round,saturate,sign,msb)
variable saturation_temp : std_logic := '0';
variable sign_tmp : std_logic := '1';
variable data_tmp : std_logic := '0';
BEGIN
IF (saturate = '0') THEN
dataout_tmp <= datain;
saturation_overflow_tmp <= '0';
ELSE
saturation_temp := '0';
data_tmp := '0';
sign_tmp := '1';
IF (round = '1') THEN
for i in 0 to (conv_integer(datain_width) - round_width -1) LOOP
min(i) <= 'X';
max(i) <= 'X';
END LOOP;
END IF;
IF (saturate_mode = "symmetric") THEN
for i in 0 to (conv_integer(datain_width) - round_width -1) LOOP
min(i) <= 'X';
IF (round = '1') THEN
max(i) <= 'X';
ELSE
max(i) <= '1';
END IF;
END LOOP;
for i in (conv_integer(datain_width) - round_width) to (conv_integer(datain_width) - saturate_width -1) LOOP
data_tmp := data_tmp or datain(i);
max(i) <= '1';
min(i) <= '0';
END LOOP;
min(conv_integer(datain_width) - round_width) <= '1';
END IF;
IF (saturate_mode = "asymmetric") THEN
for i in 0 to (conv_integer(datain_width) - saturate_width -1) LOOP
max(i) <= '1';
min(i) <= '0';
END LOOP;
END IF;
if((saturate_width = 1))then
IF (msb /= datain(conv_integer(datain_width)-1)) THEN
saturation_temp := '1';
ELSE
sign_tmp := sign_tmp and datain(conv_integer(datain_width)-1);
END IF;
else
for i in (conv_integer(datain_width) - saturate_width) to (conv_integer(datain_width)-1) LOOP
sign_tmp := sign_tmp and datain(i);
IF (datain(conv_integer(datain_width)-1) /= datain(i)) THEN
saturation_temp := '1';
end if;
END LOOP;
end if;
-- Trigger the saturation overflow for data=-2^n in case of symmetric saturation.
if((sign_tmp ='1') and (data_tmp = '0') and (saturate_mode = "symmetric")) then
saturation_temp := '1';
end if;
saturation_overflow_tmp <= saturation_temp;
IF (saturation_temp = '1') THEN
IF ((operation_mode = "output_only")or (operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out")) THEN
IF (msb = '1') THEN
dataout_tmp <= min;
ELSE
dataout_tmp <= max;
END IF;
ELSE
IF (sign = '1') THEN
IF (msb = '1') THEN
dataout_tmp <= min;
ELSE
dataout_tmp <= max;
END IF;
ELSE
dataout_tmp <= (others => 'X');
END IF;
END IF;
ELSE
dataout_tmp <= datain;
END IF;
END IF;
END PROCESS;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiii_round_saturate_block --
-- Description: Stratix III round and saturation Unit. --
-- This unit instantiated the following components. --
-- 1.stratixiii_round_block. --
-- 2.stratixiii_saturate_block. --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_round_saturate_block IS
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
saturate_width : integer := 15;
round_width : integer := 15;
saturate_mode : string := " asymmetric";
round_mode : string := "nearest_integer";
operation_mode : string := "output_only" ;
tipd_datain : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_round : VitalDelayType01 :=DefPropDelay01;
tipd_saturate : VitalDelayType01 :=DefPropDelay01;
tipd_signa : VitalDelayType01 :=DefPropDelay01;
tipd_signb : VitalDelayType01 :=DefPropDelay01;
tpd_datain_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_round_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_saturate_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_datain_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_round_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_saturate_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signa_saturationoverflow : VitalDelayType01 := DefPropDelay01;
tpd_signb_saturationoverflow : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0);
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
saturationoverflow : OUT std_logic
);
END stratixiii_round_saturate_block;
ARCHITECTURE arch OF stratixiii_round_saturate_block IS
COMPONENT stratixiii_round_block
GENERIC (
round_mode : string := "nearest_integer";
round_width : integer := 15;
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiii_saturate_block
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
saturate_mode : string := " asymmetric";
saturate_width : integer := 15;
round_width : integer := 15;
operation_mode : string := "output_only"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
saturate : IN std_logic := '0';
round : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
saturation_overflow : OUT std_logic
);
END COMPONENT;
SIGNAL dataout_round : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL saturate_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_saturate : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datain_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL signa_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
SIGNAL round_ipd : std_logic := '0';
SIGNAL saturate_ipd : std_logic := '0';
SIGNAL saturationoverflow_tmp : std_logic := '0';
BEGIN
WireDelay : block
begin
g1 :for i in datain'range generate
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signb, tipd_signb);
VitalWireDelay (round_ipd, round, tipd_round);
VitalWireDelay (saturate_ipd, saturate, tipd_saturate);
end block;
round_unit : stratixiii_round_block
GENERIC MAP (
operation_mode => operation_mode,
round_width => round_width,
round_mode => round_mode
)
PORT MAP (
datain => datain_ipd,
round => round_ipd,
datain_width => datain_width,
dataout => dataout_round
);
saturate_unit : stratixiii_saturate_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
operation_mode => operation_mode,
saturate_mode => saturate_mode,
saturate_width =>saturate_width,
round_width =>round_width
)
PORT MAP (
datain => dataout_round,
saturate => saturate_ipd,
round => round_ipd,
signa => signa_ipd,
signb => signb_ipd,
datain_width => datain_width,
dataout => dataout_saturate,
saturation_overflow => saturationoverflow_tmp
);
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_saturate(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_saturate(i),
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout(i), TRUE),
1 => (round_ipd'last_event, tpd_round_dataout(i), TRUE),
2 => (saturate_ipd'last_event, tpd_saturate_dataout(i), TRUE),
3 => (signa'last_event, tpd_signa_dataout(i), TRUE),
4 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
process(saturationoverflow_tmp)
VARIABLE saturationoverflow_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => saturationoverflow,
OutSignalName => "saturationoverflow",
OutTemp => saturationoverflow_tmp,
Paths => (0 => (datain_ipd'last_event, tpd_datain_saturationoverflow, TRUE),
1 => (round_ipd'last_event, tpd_round_saturationoverflow, TRUE),
2 => (saturate_ipd'last_event, tpd_saturate_saturationoverflow, TRUE),
3 => (signa'last_event, tpd_signa_saturationoverflow, TRUE),
4 => (signb'last_event, tpd_signb_saturationoverflow, TRUE)),
GlitchData => saturationoverflow_VitalGlitchData,
Mode => DefGlitchMode,
XOn => TRUE,
MsgOn => TRUE
);
end process;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiii_rotate_shift_block --
-- Description: Stratix III roate and shift Unit. --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_rotate_shift_block IS
GENERIC (
dataa_width : integer := 32;
datab_width : integer := 32;
tipd_datain : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_rotate : VitalDelayType01 :=DefPropDelay01;
tipd_shiftright : VitalDelayType01 :=DefPropDelay01;
tipd_signa : VitalDelayType01 :=DefPropDelay01;
tipd_signb : VitalDelayType01 :=DefPropDelay01;
tpd_datain_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_rotate_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_shiftright_dataout: VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(71 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END stratixiii_rotate_shift_block;
ARCHITECTURE arch OF stratixiii_rotate_shift_block IS
signal dataout_tmp : std_logic_vector(71 downto 0) := (others => '0');
SIGNAL datain_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL signa_ipd : std_logic := '0';
SIGNAL signb_ipd : std_logic := '0';
SIGNAL rotate_ipd : std_logic := '0';
SIGNAL shiftright_ipd : std_logic := '0';
SIGNAL sign : std_logic;
BEGIN
WireDelay : block
begin
g1 :for i in datain'range generate
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signa, tipd_signa);
VitalWireDelay (rotate_ipd, rotate, tipd_rotate);
VitalWireDelay (shiftright_ipd, shiftright, tipd_shiftright);
end block;
PROCESS
BEGIN
WAIT UNTIL datain_ipd'EVENT OR rotate_ipd'EVENT OR shiftright_ipd'EVENT;
sign <= signa_ipd xor signb_ipd;
dataout_tmp <= datain;
IF ((rotate_ipd = '0') AND (shiftright_ipd = '0')) THEN
dataout_tmp(39 downto 8) <= datain_ipd(39 downto 8);
ELSIF ((rotate_ipd = '0') AND (shiftright_ipd = '1')) THEN --shift right
dataout_tmp(39 downto 8) <= datain_ipd(71 downto 40);
ELSIF((rotate_ipd = '1') AND (shiftright_ipd = '0')) THEN
dataout_tmp(39 downto 8) <= datain_ipd(39 downto 8) OR datain_ipd(71 downto 40);
ELSE
dataout_tmp <= datain_ipd;
END IF;
END PROCESS;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (datain_ipd'last_event, tpd_datain_dataout(i), TRUE),
1 => (rotate_ipd'last_event, tpd_rotate_dataout(i), TRUE),
2 => (shiftright_ipd'last_event, tpd_shiftright_dataout(i), TRUE),
3 => (signa'last_event, tpd_signa_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
end block;
END arch;
--------------------------------------------------------------------------------------------------
-- Module Name: stratixiii_carry_chain_adder --
-- Description: Stratix III carry Chain Adder --
--------------------------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_carry_chain_adder IS
GENERIC(
tipd_dataa : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(71 downto 0) := (OTHERS => DefPropDelay01);
tpd_dataa_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(72*72-1 downto 0) := (others => DefPropDelay01);
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
dataout : OUT STD_LOGIC_vector(71 DOWNTO 0)
);
END stratixiii_carry_chain_adder;
ARCHITECTURE arch OF stratixiii_carry_chain_adder IS
SIGNAL dataa_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_ipd : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
BEGIN
WireDelay : block
begin
g1 :for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 :for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
end block;
dataout_tmp <= (dataa_ipd(71 downto 45) & dataa_ipd(43) & dataa_ipd(43 downto 0)) + (datab_ipd(71 downto 45) & datab_ipd(43) & datab_ipd(43 downto 0)) ;
PathDelay : block
begin
do1 : for i in dataout'range generate
process(dataout_tmp(i))
VARIABLE dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE
);
end process;
end generate do1;
end block;
END arch;
----------------------------------------------------------------------------------
-- Module Name: stratixiii_mac_out_atom --
-- Description: Simulation model for stratixiii mac out atom --
-- This model instantiates the following components --
-- 1.stratixiii_mac_bit_register --
-- 2.stratixiii_mac_register --
-- 3.stratixiii_fsa_isse --
-- 4.stratixiii_first_stage_add_sub --
-- 5.stratixiii_second_stage_add_accum --
-- 6.stratixiii_round_saturate_block --
-- 7.stratixiii_rotate_shift_block --
-- 8.stratixiii_carry_chain_adder --
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
ENTITY stratixiii_mac_out IS
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
chainin_width : integer := 1;
round_width : integer := 15;
round_chain_out_width : integer := 15;
saturate_width : integer := 15;
saturate_chain_out_width : integer := 15;
first_adder0_clock : string := "none";
first_adder0_clear : string := "none";
first_adder1_clock : string := "none";
first_adder1_clear : string := "none";
second_adder_clock : string := "none";
second_adder_clear : string := "none";
output_clock : string := "none";
output_clear : string := "none";
signa_clock : string := "none";
signa_clear : string := "none";
signb_clock : string := "none";
signb_clear : string := "none";
round_clock : string := "none";
round_clear : string := "none";
roundchainout_clock : string := "none";
roundchainout_clear : string := "none";
saturate_clock : string := "none";
saturate_clear : string := "none";
saturatechainout_clock : string := "none";
saturatechainout_clear : string := "none";
zeroacc_clock : string := "none";
zeroacc_clear : string := "none";
zeroloopback_clock : string := "none";
zeroloopback_clear : string := "none";
rotate_clock : string := "none";
rotate_clear : string := "none";
shiftright_clock : string := "none";
shiftright_clear : string := "none";
signa_pipeline_clock : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clock : string := "none";
signb_pipeline_clear : string := "none";
round_pipeline_clock : string := "none";
round_pipeline_clear : string := "none";
roundchainout_pipeline_clock : string := "none";
roundchainout_pipeline_clear : string := "none";
saturate_pipeline_clock : string := "none";
saturate_pipeline_clear : string := "none";
saturatechainout_pipeline_clock: string := "none";
saturatechainout_pipeline_clear: string := "none";
zeroacc_pipeline_clock : string := "none";
zeroacc_pipeline_clear : string := "none";
zeroloopback_pipeline_clock : string := "none";
zeroloopback_pipeline_clear : string := "none";
rotate_pipeline_clock : string := "none";
rotate_pipeline_clear : string := "none";
shiftright_pipeline_clock : string := "none";
shiftright_pipeline_clear : string := "none";
roundchainout_output_clock : string := "none";
roundchainout_output_clear : string := "none";
saturatechainout_output_clock : string := "none";
saturatechainout_output_clear : string := "none";
zerochainout_output_clock : string := "none";
zerochainout_output_clear : string := "none";
zeroloopback_output_clock : string := "none";
zeroloopback_output_clear : string := "none";
rotate_output_clock : string := "none";
rotate_output_clear : string := "none";
shiftright_output_clock : string := "none";
shiftright_output_clear : string := "none";
first_adder0_mode : string := "add";
first_adder1_mode : string := "add";
acc_adder_operation : string := "add";
round_mode : string := "nearest_integer";
round_chain_out_mode : string := "nearest_integer";
saturate_mode : string := "asymmetric";
saturate_chain_out_mode : string := "asymmetric";
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
lpm_type : string := "stratixiii_mac_out";
dataout_width : integer:=72
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '1');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '1');
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0):= (others => '1');
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0):= (others => '1');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0):= (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
zeroacc : IN std_logic := '0';
roundchainout : IN std_logic := '0';
saturatechainout : IN std_logic := '0';
zerochainout : IN std_logic := '0';
zeroloopback : IN std_logic := '0';
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
loopbackout : OUT std_logic_vector(17 DOWNTO 0):= (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic := '0';
saturatechainoutoverflow: OUT std_logic := '0';
dftout : OUT std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1'
);
END stratixiii_mac_out;
ARCHITECTURE arch OF stratixiii_mac_out IS
COMPONENT stratixiii_mac_bit_register
PORT (
datain : IN std_logic := '0';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT stratixiii_mac_register
GENERIC (
data_width : integer := 18
);
PORT (
datain : IN std_logic_vector(data_width - 1 DOWNTO 0) := (others => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
sload : IN std_logic := '0';
bypass_register : IN std_logic := '0';
dataout : OUT std_logic_vector(data_width - 1 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiii_fsa_isse
GENERIC (
datab_width : integer := 36;
dataa_width : integer := 36;
chainin_width : integer := 44;
operation_mode : string := "output_only";
datad_width : integer := 36;
multa_signa_internally_grounded : string := "false";
multa_signb_internally_grounded : string := "false";
multb_signa_internally_grounded : string := "false";
multb_signb_internally_grounded : string := "false";
multc_signa_internally_grounded : string := "false";
multc_signb_internally_grounded : string := "false";
multd_signa_internally_grounded : string := "false";
multd_signb_internally_grounded : string := "false";
datac_width : integer := 36
);
PORT (
dataa : IN std_logic_vector(dataa_width - 1 DOWNTO 0):= (others => '0');
datab : IN std_logic_vector(datab_width - 1 DOWNTO 0):= (others => '0');
datac : IN std_logic_vector(datac_width - 1 DOWNTO 0):= (others => '0');
datad : IN std_logic_vector(datad_width - 1 DOWNTO 0):= (others => '0');
chainin : IN std_logic_vector(chainin_width - 1 DOWNTO 0):= (others => '0');
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataa_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
datab_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
datac_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
datad_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
chainin_out : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
operation : OUT std_logic_vector(3 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiii_first_stage_add_sub
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
fsa_mode : string := "add"
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiii_second_stage_add_accum
GENERIC (
dataa_width : integer := 36;
datab_width : integer := 36;
ssa_mode : string := "add"
);
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
accumin : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
sign : IN std_logic := '0';
operation : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
overflow : OUT std_logic
);
END COMPONENT;
COMPONENT stratixiii_round_saturate_block
GENERIC (
datab_width : integer := 36;
dataa_width : integer := 36;
saturate_mode : string := " asymmetric";
saturate_width : integer := 15;
round_width : integer := 15;
operation_mode : string := "output_only";
round_mode : string := "nearest_integer"
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
round : IN std_logic := '0';
saturate : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
datain_width : IN std_logic_vector(7 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0) := (others => '0');
saturationoverflow : OUT std_logic
);
END COMPONENT;
COMPONENT stratixiii_rotate_shift_block
GENERIC (
datab_width : integer := 32;
dataa_width : integer := 32
);
PORT (
datain : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
rotate : IN std_logic := '0';
shiftright : IN std_logic := '0';
signa : IN std_logic := '0';
signb : IN std_logic := '0';
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
COMPONENT stratixiii_carry_chain_adder
PORT (
dataa : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
datab : IN std_logic_vector(71 DOWNTO 0) := (others => '0');
dataout : OUT std_logic_vector(71 DOWNTO 0)
);
END COMPONENT;
--signals for zeroloopback input register
SIGNAL zeroloopback_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_clk_ir : std_logic := '0';
SIGNAL zeroloopback_aclr_ir : std_logic := '0';
SIGNAL zeroloopback_sload_ir : std_logic := '0';
SIGNAL zeroloopback_bypass_register_ir : std_logic := '0';
SIGNAL zeroloopback_in_reg : std_logic := '0';
SIGNAL zeroloopback_in : std_logic := '0';
--signals for zeroacc input register
SIGNAL zeroacc_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_clk_ir : std_logic := '0';
SIGNAL zeroacc_aclr_ir : std_logic := '0';
SIGNAL zeroacc_sload_ir : std_logic := '0';
SIGNAL zeroacc_bypass_register_ir : std_logic := '0';
SIGNAL zeroacc_in_reg : std_logic := '0';
SIGNAL zeroacc_in : std_logic := '0';
--Signals for signa input register
SIGNAL signa_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk_ir : std_logic := '0';
SIGNAL signa_aclr_ir : std_logic := '0';
SIGNAL signa_sload_ir : std_logic := '0';
SIGNAL signa_bypass_register_ir : std_logic := '0';
SIGNAL signa_in_reg : std_logic := '0';
SIGNAL signa_in : std_logic := '0';
--signals for signb input register
SIGNAL signb_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk_ir : std_logic := '0';
SIGNAL signb_aclr_ir : std_logic := '0';
SIGNAL signb_sload_ir : std_logic := '0';
SIGNAL signb_bypass_register_ir : std_logic := '0';
SIGNAL signb_in_reg : std_logic := '0';
SIGNAL signb_in : std_logic := '0';
--signals for rotate input register
SIGNAL rotate_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_clk_ir : std_logic := '0';
SIGNAL rotate_aclr_ir : std_logic := '0';
SIGNAL rotate_sload_ir : std_logic := '0';
SIGNAL rotate_bypass_register_ir: std_logic := '0';
SIGNAL rotate_in_reg : std_logic := '0';
SIGNAL rotate_in : std_logic := '0';
--signals for shiftright input register
SIGNAL shiftright_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_clk_ir : std_logic := '0';
SIGNAL shiftright_aclr_ir : std_logic := '0';
SIGNAL shiftright_sload_ir : std_logic := '0';
SIGNAL shiftright_bypass_register_ir : std_logic := '0';
SIGNAL shiftright_in_reg : std_logic := '0';
SIGNAL shiftright_in : std_logic := '0';
--signals for round input register
SIGNAL round_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_clk_ir : std_logic := '0';
SIGNAL round_aclr_ir : std_logic := '0';
SIGNAL round_sload_ir : std_logic := '0';
SIGNAL round_bypass_register_ir : std_logic := '0';
SIGNAL round_in_reg : std_logic := '0';
SIGNAL round_in : std_logic := '0';
--signals for saturate input register
SIGNAL saturate_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_clk_ir : std_logic := '0';
SIGNAL saturate_aclr_ir : std_logic := '0';
SIGNAL saturate_sload_ir : std_logic := '0';
SIGNAL saturate_bypass_register_ir : std_logic := '0';
SIGNAL saturate_in_reg : std_logic := '0';
SIGNAL saturate_in : std_logic := '0';
--signals for roundchainout input register
SIGNAL roundchainout_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_clk_ir : std_logic := '0';
SIGNAL roundchainout_aclr_ir : std_logic := '0';
SIGNAL roundchainout_sload_ir : std_logic := '0';
SIGNAL roundchainout_bypass_register_ir: std_logic := '0';
SIGNAL roundchainout_in_reg : std_logic := '0';
SIGNAL roundchainout_in : std_logic := '0';
--signals for saturatechainout input register
SIGNAL saturatechainout_clkval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_aclrval_ir : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_clk_ir : std_logic := '0';
SIGNAL saturatechainout_aclr_ir : std_logic := '0';
SIGNAL saturatechainout_sload_ir: std_logic := '0';
SIGNAL saturatechainout_bypass_register_ir: std_logic := '0';
SIGNAL saturatechainout_in_reg : std_logic := '0';
SIGNAL saturatechainout_in : std_logic := '0';
--signals for fsa_input_interface
SIGNAL dataa_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datab_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datac_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL datad_fsa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL chainin_coa_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL operation : std_logic_vector(3 DOWNTO 0) := (others => '0');
--Signals for First Stage Adder units
SIGNAL dataout_fsa0 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL fsa_pip_datain1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_fsa1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL overflow_fsa0 : std_logic := '0';
SIGNAL overflow_fsa1 : std_logic := '0';
--signals for zeroloopback pipeline register
SIGNAL zeroloopback_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_clk_pip : std_logic := '0';
SIGNAL zeroloopback_aclr_pip : std_logic := '0';
SIGNAL zeroloopback_sload_pip : std_logic := '0';
SIGNAL zeroloopback_bypass_register_pip: std_logic := '0';
SIGNAL zeroloopback_pip_reg : std_logic := '0';
--signals for zeroacc pipeline register
SIGNAL zeroacc_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroacc_clk_pip : std_logic := '0';
SIGNAL zeroacc_aclr_pip : std_logic := '0';
SIGNAL zeroacc_sload_pip : std_logic := '0';
SIGNAL zeroacc_bypass_register_pip : std_logic := '0';
SIGNAL zeroacc_pip_reg : std_logic := '0';
--Signals for signa pipeline register
SIGNAL signa_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signa_clk_pip : std_logic := '0';
SIGNAL signa_aclr_pip : std_logic := '0';
SIGNAL signa_sload_pip : std_logic := '0';
SIGNAL signa_bypass_register_pip: std_logic := '0';
SIGNAL signa_pip_reg : std_logic := '0';
--signals for signb pipeline register
SIGNAL signb_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL signb_clk_pip : std_logic := '0';
SIGNAL signb_aclr_pip : std_logic := '0';
SIGNAL signb_sload_pip : std_logic := '0';
SIGNAL signb_bypass_register_pip: std_logic := '0';
SIGNAL signb_pip_reg : std_logic := '0';
--signals for rotate pipeline register
SIGNAL rotate_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_clk_pip : std_logic := '0';
SIGNAL rotate_aclr_pip : std_logic := '0';
SIGNAL rotate_sload_pip : std_logic := '0';
SIGNAL rotate_bypass_register_pip : std_logic := '0';
SIGNAL rotate_pip_reg : std_logic := '0';
--signals for shiftright pipeline register
SIGNAL shiftright_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_clk_pip : std_logic := '0';
SIGNAL shiftright_aclr_pip : std_logic := '0';
SIGNAL shiftright_sload_pip : std_logic := '0';
SIGNAL shiftright_bypass_register_pip : std_logic := '0';
SIGNAL shiftright_pip_reg : std_logic := '0';
--signals for round pipeline register
SIGNAL round_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL round_clk_pip : std_logic := '0';
SIGNAL round_aclr_pip : std_logic := '0';
SIGNAL round_sload_pip : std_logic := '0';
SIGNAL round_bypass_register_pip: std_logic := '0';
SIGNAL round_pip_reg : std_logic := '0';
--signals for saturate pipeline register
SIGNAL saturate_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturate_clk_pip : std_logic := '0';
SIGNAL saturate_aclr_pip : std_logic := '0';
SIGNAL saturate_sload_pip : std_logic := '0';
SIGNAL saturate_bypass_register_pip : std_logic := '0';
SIGNAL saturate_pip_reg : std_logic := '0';
--signals for roundchainout pipeline register
SIGNAL roundchainout_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_aclrval_pip: std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_clk_pip : std_logic := '0';
SIGNAL roundchainout_aclr_pip : std_logic := '0';
SIGNAL roundchainout_sload_pip : std_logic := '0';
SIGNAL roundchainout_bypass_register_pip: std_logic := '0';
SIGNAL roundchainout_pip_reg : std_logic := '0';
--signals for saturatechainout pipeline register
SIGNAL saturatechainout_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_clk_pip : std_logic := '0';
SIGNAL saturatechainout_aclr_pip: std_logic := '0';
SIGNAL saturatechainout_sload_pip : std_logic := '0';
SIGNAL saturatechainout_bypass_register_pip: std_logic := '0';
SIGNAL saturatechainout_pip_reg : std_logic := '0';
--signals for fsa0 pipeline register
SIGNAL fsa0_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa0_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa0_clk_pip : std_logic := '0';
SIGNAL fsa0_aclr_pip : std_logic := '0';
SIGNAL fsa0_sload_pip : std_logic := '0';
SIGNAL fsa0_bypass_register_pip : std_logic := '0';
SIGNAL fsa0_pip_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
--signals for fsa1 pipeline register
SIGNAL fsa1_clkval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa1_aclrval_pip : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL fsa1_clk_pip : std_logic := '0';
SIGNAL fsa1_aclr_pip : std_logic := '0';
SIGNAL fsa1_sload_pip : std_logic := '0';
SIGNAL fsa1_bypass_register_pip : std_logic := '0';
SIGNAL fsa1_pip_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
--Signals for second stage adder
SIGNAL ssa_accum_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL ssa_sign : std_logic := '0';
SIGNAL ssa_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL ssa_overflow : std_logic := '0';
--Signals for RS block
SIGNAL rs_datain : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_of : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_saturation_overflow : std_logic := '0';
SIGNAL ssa_datain_width : std_logic_vector(7 DOWNTO 0);
SIGNAL ssa_round_width : std_logic_vector(3 DOWNTO 0) := (others => '0');
--signals for zeroloopback output register
SIGNAL zeroloopback_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zeroloopback_clk_or : std_logic := '0';
SIGNAL zeroloopback_aclr_or : std_logic := '0';
SIGNAL zeroloopback_sload_or : std_logic := '0';
SIGNAL zeroloopback_bypass_register_or : std_logic := '0';
SIGNAL zeroloopback_out_reg : std_logic := '0';
--signals for zerochainout output register
SIGNAL zerochainout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zerochainout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL zerochainout_clk_or : std_logic := '0';
SIGNAL zerochainout_aclr_or : std_logic := '0';
SIGNAL zerochainout_sload_or : std_logic := '0';
SIGNAL zerochainout_bypass_register_or : std_logic := '0';
SIGNAL zerochainout_out_reg : std_logic := '0';
--Signals for saturation_overflow output register
SIGNAL rs_saturation_overflow_in : std_logic := '0';
SIGNAL saturation_overflow_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturation_overflow_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturation_overflow_clk_or : std_logic := '0';
SIGNAL saturation_overflow_aclr_or : std_logic := '0';
SIGNAL saturation_overflow_sload_or : std_logic := '0';
SIGNAL saturation_overflow_bypass_register_or: std_logic := '0';
SIGNAL saturation_overflow_out_reg : std_logic := '0';
--signals for rs_dataout output register
SIGNAL rs_dataout_in : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clkval_or_co : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_aclrval_or_co : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clkval_or_o : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_aclrval_or_o : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rs_dataout_clk_or : std_logic := '0';
SIGNAL rs_dataout_aclr_or : std_logic := '0';
SIGNAL rs_dataout_sload_or : std_logic := '0';
SIGNAL rs_dataout_bypass_register_or_co : std_logic := '0';
SIGNAL rs_dataout_bypass_register_or_o : std_logic := '0';
SIGNAL rs_dataout_bypass_register_or : std_logic := '0';
SIGNAL rs_dataout_out_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL rs_saturation_overflow_out_reg : std_logic := '0';
--signals for rotate output register
SIGNAL rotate_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL rotate_clk_or : std_logic := '0';
SIGNAL rotate_aclr_or : std_logic := '0';
SIGNAL rotate_sload_or : std_logic := '0';
SIGNAL rotate_bypass_register_or: std_logic := '0';
SIGNAL rotate_out_reg : std_logic := '0';
--signals for shiftright output register
SIGNAL shiftright_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL shiftright_clk_or : std_logic := '0';
SIGNAL shiftright_aclr_or : std_logic := '0';
SIGNAL shiftright_sload_or : std_logic := '0';
SIGNAL shiftright_bypass_register_or : std_logic := '0';
SIGNAL shiftright_out_reg : std_logic := '0';
--signals for roundchainout output register
SIGNAL roundchainout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL roundchainout_clk_or : std_logic := '0';
SIGNAL roundchainout_aclr_or : std_logic := '0';
SIGNAL roundchainout_sload_or : std_logic := '0';
SIGNAL roundchainout_bypass_register_or: std_logic := '0';
SIGNAL roundchainout_out_reg : std_logic := '0';
--signals for saturatechainout output register
SIGNAL saturatechainout_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL saturatechainout_clk_or : std_logic := '0';
SIGNAL saturatechainout_aclr_or : std_logic := '0';
SIGNAL saturatechainout_sload_or: std_logic := '0';
SIGNAL saturatechainout_bypass_register_or: std_logic := '0';
SIGNAL saturatechainout_out_reg : std_logic := '0';
--Signals for chainout Adder RS Block
SIGNAL coa_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL coa_round_width : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL coa_rs_dataout : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL coa_rs_saturation_overflow : std_logic := '0';
--signals for control signals for COA output register
SIGNAL coa_reg_clkval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL coa_reg_aclrval_or : std_logic_vector(3 DOWNTO 0) := (others => '0');
SIGNAL coa_reg_clk_or : std_logic := '0';
SIGNAL coa_reg_aclr_or : std_logic := '0';
SIGNAL coa_reg_sload_or : std_logic := '0';
SIGNAL coa_reg_bypass_register_or : std_logic := '0';
SIGNAL coa_reg_out_reg : std_logic := '0';
SIGNAL coa_rs_saturation_overflow_out_reg: std_logic := '0';
SIGNAL coa_rs_saturationchainout_overflow_out_reg: std_logic := '0';
SIGNAL coa_rs_dataout_out_reg : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL dataout_shift_rot : std_logic_vector(71 DOWNTO 0):= (others => '0');
SIGNAL dataout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL loopbackout_tmp : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL saturation_overflow_tmp : std_logic := '0';
SIGNAL saturationchainout_overflow_tmp : std_logic := '0';
SIGNAL rs_dataout_tmp1 : std_logic_vector(71 DOWNTO 0) := (others => '0');
SIGNAL sign : std_logic := '0';
BEGIN
process(rs_dataout, rs_saturation_overflow, saturate_pip_reg)
variable rs_tmp : std_logic_vector(71 downto 0):= (others => '0');
begin
rs_tmp := rs_dataout;
if (((operation_mode = "output_only")or (operation_mode = "one_level_adder") or(operation_mode = "loopback")) and (dataa_width > 1) and (saturate_pip_reg = '1'))then
rs_tmp(dataa_width -1) := rs_saturation_overflow ;
end if;
rs_dataout_of <= rs_tmp;
end process;
--Instantiate the zeroloopback input Register
zeroloopback_clkval_ir <= "0000" WHEN ((zeroloopback_clock = "0") or (zeroloopback_clock = "none"))
ELSE "0001" WHEN (zeroloopback_clock = "1")
ELSE "0010" WHEN (zeroloopback_clock = "2")
ELSE "0011" WHEN (zeroloopback_clock = "3")
ELSE "0000" ;
zeroloopback_aclrval_ir <= "0000" WHEN ((zeroloopback_clear = "0") or (zeroloopback_clear = "none"))
ELSE "0001" WHEN (zeroloopback_clear = "1")
ELSE "0010" WHEN (zeroloopback_clear = "2")
ELSE "0011" WHEN (zeroloopback_clear = "3")
ELSE "0000" ;
zeroloopback_clk_ir <= '1' WHEN clk(conv_integer(zeroloopback_clkval_ir)) = '1' ELSE '0';
zeroloopback_aclr_ir <= '1' WHEN (aclr(conv_integer(zeroloopback_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroloopback_sload_ir <= '1' WHEN ena(conv_integer(zeroloopback_clkval_ir)) = '1' ELSE '0';
zeroloopback_bypass_register_ir <= '1' WHEN (zeroloopback_clock = "none") ELSE '0';
zeroloopback_in <= zeroloopback;
zeroloopback_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => zeroloopback_in,
clk => zeroloopback_clk_ir,
aclr => zeroloopback_aclr_ir,
sload => zeroloopback_sload_ir,
bypass_register => zeroloopback_bypass_register_ir,
dataout => zeroloopback_in_reg
);
--Instantiate the zeroacc input Register
zeroacc_clkval_ir <= "0000" WHEN ((zeroacc_clock = "0") or (zeroacc_clock = "none"))
ELSE "0001" WHEN (zeroacc_clock = "1")
ELSE "0010" WHEN (zeroacc_clock = "2")
ELSE "0011" WHEN (zeroacc_clock = "3")
ELSE "0000" ;
zeroacc_aclrval_ir <= "0000" WHEN ((zeroacc_clear = "0") or (zeroacc_clear = "none"))
ELSE "0001" WHEN (zeroacc_clear = "1")
ELSE "0010" WHEN (zeroacc_clear = "2")
ELSE "0011" WHEN (zeroacc_clear = "3")
ELSE "0000" ;
zeroacc_clk_ir <= '1' WHEN clk(conv_integer(zeroacc_clkval_ir)) = '1' ELSE '0';
zeroacc_aclr_ir <= '1' WHEN (aclr(conv_integer(zeroacc_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroacc_sload_ir <= '1' WHEN ena(conv_integer(zeroacc_clkval_ir)) = '1' ELSE '0';
zeroacc_bypass_register_ir <= '1' WHEN (zeroacc_clock = "none") ELSE '0';
zeroacc_in <= zeroacc;
zeroacc_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => zeroacc_in,
clk => zeroacc_clk_ir,
aclr => zeroacc_aclr_ir,
sload => zeroacc_sload_ir,
bypass_register => zeroacc_bypass_register_ir,
dataout => zeroacc_in_reg
);
--Instantiate the signa input Register
signa_clkval_ir <= "0000" WHEN ((signa_clock = "0") or (signa_clock = "none"))
ELSE "0001" WHEN (signa_clock = "1")
ELSE "0010" WHEN (signa_clock = "2")
ELSE "0011" WHEN (signa_clock = "3")
ELSE "0000" ;
signa_aclrval_ir <= "0000" WHEN ((signa_clear = "0") or (signa_clear = "none"))
ELSE "0001" WHEN (signa_clear = "1")
ELSE "0010" WHEN (signa_clear = "2")
ELSE "0011" WHEN (signa_clear = "3")
ELSE "0000" ;
signa_clk_ir <= '1' WHEN clk(conv_integer(signa_clkval_ir)) = '1' ELSE '0';
signa_aclr_ir <= '1' WHEN (aclr(conv_integer(signa_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signa_sload_ir <= '1' WHEN ena(conv_integer(signa_clkval_ir)) = '1' ELSE '0';
signa_bypass_register_ir <= '1' WHEN (signa_clock = "none") ELSE '0';
signa_in <= signa;
signa_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => signa_in,
clk => signa_clk_ir,
aclr => signa_aclr_ir,
sload => signa_sload_ir,
bypass_register => signa_bypass_register_ir,
dataout => signa_in_reg
);
--Instantiate the signb input Register
signb_clkval_ir <= "0000" WHEN ((signb_clock = "0") or (signb_clock = "none"))
ELSE "0001" WHEN (signb_clock = "1")
ELSE "0010" WHEN (signb_clock = "2")
ELSE "0011" WHEN (signb_clock = "3")
ELSE "0000" ;
signb_aclrval_ir <= "0000" WHEN ((signb_clear = "0") or (signb_clear = "none"))
ELSE "0001" WHEN (signb_clear = "1")
ELSE "0010" WHEN (signb_clear = "2")
ELSE "0011" WHEN (signb_clear = "3")
ELSE "0000" ;
signb_clk_ir <= '1' WHEN clk(conv_integer(signb_clkval_ir)) = '1' ELSE '0';
signb_aclr_ir <= '1' WHEN (aclr(conv_integer(signb_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signb_sload_ir <= '1' WHEN ena(conv_integer(signb_clkval_ir)) = '1' ELSE '0';
signb_bypass_register_ir <= '1' WHEN (signb_clock = "none") ELSE '0';
signb_in <= signb;
signb_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => signb_in,
clk => signb_clk_ir,
aclr => signb_aclr_ir,
sload => signb_sload_ir,
bypass_register => signb_bypass_register_ir,
dataout => signb_in_reg
);
--Instantiate the rotate input Register
rotate_clkval_ir <= "0000" WHEN ((rotate_clock = "0") or (rotate_clock = "none"))
ELSE "0001" WHEN (rotate_clock = "1")
ELSE "0010" WHEN (rotate_clock = "2")
ELSE "0011" WHEN (rotate_clock = "3")
ELSE "0000" ;
rotate_aclrval_ir <= "0000" WHEN ((rotate_clear = "0") or (rotate_clear = "none"))
ELSE "0001" WHEN (rotate_clear = "1")
ELSE "0010" WHEN (rotate_clear = "2")
ELSE "0011" WHEN (rotate_clear = "3")
ELSE "0000" ;
rotate_clk_ir <= '1' WHEN clk(conv_integer(rotate_clkval_ir)) = '1' ELSE '0';
rotate_aclr_ir <= '1' WHEN (aclr(conv_integer(rotate_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rotate_sload_ir <= '1' WHEN ena(conv_integer(rotate_clkval_ir)) = '1' ELSE '0';
rotate_bypass_register_ir <= '1' WHEN (rotate_clock = "none") ELSE '0';
rotate_in <= rotate;
rotate_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => rotate_in,
clk => rotate_clk_ir,
aclr => rotate_aclr_ir,
sload => rotate_sload_ir,
bypass_register => rotate_bypass_register_ir,
dataout => rotate_in_reg
);
--Instantiate the shiftright input Register
shiftright_clkval_ir <= "0000" WHEN ((shiftright_clock = "0") or (shiftright_clock = "none"))
ELSE "0001" WHEN (shiftright_clock = "1")
ELSE "0010" WHEN (shiftright_clock = "2")
ELSE "0011" WHEN (shiftright_clock = "3")
ELSE "0000" ;
shiftright_aclrval_ir <= "0000" WHEN ((shiftright_clear = "0") or (shiftright_clear = "none"))
ELSE "0001" WHEN (shiftright_clear = "1")
ELSE "0010" WHEN (shiftright_clear = "2")
ELSE "0011" WHEN (shiftright_clear = "3")
ELSE "0000" ;
shiftright_clk_ir <= '1' WHEN clk(conv_integer(shiftright_clkval_ir)) = '1' ELSE '0';
shiftright_aclr_ir <= '1' WHEN (aclr(conv_integer(shiftright_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0' ;
shiftright_sload_ir <= '1' WHEN ena(conv_integer(shiftright_clkval_ir)) = '1' ELSE '0';
shiftright_bypass_register_ir <= '1' WHEN (shiftright_clock = "none") ELSE '0';
shiftright_in <= shiftright;
shiftright_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => shiftright_in,
clk => shiftright_clk_ir,
aclr => shiftright_aclr_ir,
sload => shiftright_sload_ir,
bypass_register => shiftright_bypass_register_ir,
dataout => shiftright_in_reg
);
--Instantiate the round input Register
round_clkval_ir <= "0000" WHEN ((round_clock = "0") or (round_clock = "none"))
ELSE "0001" WHEN (round_clock = "1")
ELSE "0010" WHEN (round_clock = "2")
ELSE "0011" WHEN (round_clock = "3")
ELSE "0000" ;
round_aclrval_ir <= "0000" WHEN ((round_clear = "0") or (round_clear = "none"))
ELSE "0001" WHEN (round_clear = "1")
ELSE "0010" WHEN (round_clear = "2")
ELSE "0011" WHEN (round_clear = "3")
ELSE "0000" ;
round_clk_ir <= '1' WHEN clk(conv_integer(round_clkval_ir)) = '1' ELSE '0';
round_aclr_ir <= '1' WHEN (aclr(conv_integer(round_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
round_sload_ir <= '1' WHEN ena(conv_integer(round_clkval_ir)) = '1' ELSE '0';
round_bypass_register_ir <= '1' WHEN (round_clock = "none") ELSE '0';
round_in <= round;
round_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => round_in,
clk => round_clk_ir,
aclr => round_aclr_ir,
sload => round_sload_ir,
bypass_register => round_bypass_register_ir,
dataout => round_in_reg
);
--Instantiate the saturate input Register
saturate_clkval_ir <= "0000" WHEN ((saturate_clock = "0") or (saturate_clock = "none"))
ELSE "0001" WHEN (saturate_clock = "1")
ELSE "0010" WHEN (saturate_clock = "2")
ELSE "0011" WHEN (saturate_clock = "3")
ELSE "0000" ;
saturate_aclrval_ir <= "0000" WHEN ((saturate_clear = "0") or (saturate_clear = "none"))
ELSE "0001" WHEN (saturate_clear = "1")
ELSE "0010" WHEN (saturate_clear = "2")
ELSE "0011" WHEN (saturate_clear = "3")
ELSE "0000" ;
saturate_clk_ir <= '1' WHEN clk(conv_integer(saturate_clkval_ir)) = '1' ELSE '0';
saturate_aclr_ir <= '1' WHEN (aclr(conv_integer(saturate_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturate_sload_ir <= '1' WHEN ena(conv_integer(saturate_clkval_ir)) = '1' ELSE '0';
saturate_bypass_register_ir <= '1' WHEN (saturate_clock = "none") ELSE '0';
saturate_in <= saturate;
saturate_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => saturate_in,
clk => saturate_clk_ir,
aclr => saturate_aclr_ir,
sload => saturate_sload_ir,
bypass_register => saturate_bypass_register_ir,
dataout => saturate_in_reg
);
--Instantiate the roundchainout input Register
roundchainout_clkval_ir <= "0000" WHEN ((roundchainout_clock = "0") or (roundchainout_clock = "none"))
ELSE "0001" WHEN (roundchainout_clock = "1")
ELSE "0010" WHEN (roundchainout_clock = "2")
ELSE "0011" WHEN (roundchainout_clock = "3")
ELSE "0000" ;
roundchainout_aclrval_ir <= "0000" WHEN ((roundchainout_clear = "0") or (roundchainout_clear = "none"))
ELSE "0001" WHEN (roundchainout_clear = "1")
ELSE "0010" WHEN (roundchainout_clear = "2")
ELSE "0011" WHEN (roundchainout_clear = "3")
ELSE "0000" ;
roundchainout_clk_ir <= '1' WHEN clk(conv_integer(roundchainout_clkval_ir)) = '1' ELSE '0';
roundchainout_aclr_ir <= '1' WHEN (aclr(conv_integer(roundchainout_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
roundchainout_sload_ir <= '1' WHEN ena(conv_integer(roundchainout_clkval_ir)) = '1' ELSE '0';
roundchainout_bypass_register_ir <= '1' WHEN (roundchainout_clock = "none") ELSE '0';
roundchainout_in <= roundchainout;
roundchainout_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => roundchainout_in,
clk => roundchainout_clk_ir,
aclr => roundchainout_aclr_ir,
sload => roundchainout_sload_ir,
bypass_register => roundchainout_bypass_register_ir,
dataout => roundchainout_in_reg
);
--Instantiate the saturatechainout input Register
saturatechainout_clkval_ir <= "0000" WHEN ((saturatechainout_clock = "0") or (saturatechainout_clock = "none"))
ELSE "0001" WHEN (saturatechainout_clock = "1")
ELSE "0010" WHEN (saturatechainout_clock = "2")
ELSE "0011" WHEN (saturatechainout_clock = "3")
ELSE "0000" ;
saturatechainout_aclrval_ir <= "0000" WHEN ((saturatechainout_clear = "0") or (saturatechainout_clear = "none"))
ELSE "0001" WHEN (saturatechainout_clear = "1")
ELSE "0010" WHEN (saturatechainout_clear = "2")
ELSE "0011" WHEN (saturatechainout_clear = "3")
ELSE "0000" ;
saturatechainout_clk_ir <= '1' WHEN clk(conv_integer(saturatechainout_clkval_ir)) = '1' ELSE '0';
saturatechainout_aclr_ir <= '1' WHEN (aclr(conv_integer(saturatechainout_aclrval_ir)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturatechainout_sload_ir <= '1' WHEN ena(conv_integer(saturatechainout_clkval_ir)) = '1' ELSE '0';
saturatechainout_bypass_register_ir <= '1' WHEN (saturatechainout_clock = "none") ELSE '0';
saturatechainout_in <= saturatechainout;
saturatechainout_input_register : stratixiii_mac_bit_register
PORT MAP (
datain => saturatechainout_in,
clk => saturatechainout_clk_ir,
aclr => saturatechainout_aclr_ir,
sload => saturatechainout_sload_ir,
bypass_register => saturatechainout_bypass_register_ir,
dataout => saturatechainout_in_reg
);
--Instantiate the First level adder interface and sign extension block
sign <= signa_in_reg OR signb_in_reg ;
fsa_interface : stratixiii_fsa_isse
GENERIC MAP (
chainin_width => chainin_width,
dataa_width => dataa_width,
datab_width => datab_width,
datac_width => datac_width,
datad_width => datad_width,
operation_mode => operation_mode,
multa_signa_internally_grounded => multa_signa_internally_grounded,
multa_signb_internally_grounded => multa_signb_internally_grounded,
multb_signa_internally_grounded => multb_signa_internally_grounded,
multb_signb_internally_grounded => multb_signb_internally_grounded,
multc_signa_internally_grounded => multc_signa_internally_grounded,
multc_signb_internally_grounded => multc_signb_internally_grounded,
multd_signa_internally_grounded => multd_signa_internally_grounded,
multd_signb_internally_grounded => multd_signb_internally_grounded
)
PORT MAP (
dataa => dataa,
datab => datab,
datac => datac,
datad => datad,
chainin => chainin,
signa => signa_in_reg,
signb => signb_in_reg,
dataa_out => dataa_fsa_in,
datab_out => datab_fsa_in,
datac_out => datac_fsa_in,
datad_out => datad_fsa_in,
chainin_out => chainin_coa_in,
operation => operation
);
--Instantiate First Stage Adder/Subtractor Unit0
fsaunit0 : stratixiii_first_stage_add_sub
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
fsa_mode => first_adder0_mode
)
PORT MAP (
dataa => dataa_fsa_in,
datab => datab_fsa_in,
sign => sign,
operation => operation,
dataout => dataout_fsa0
);
--Instantiate First Stage Adder/Subtractor Unit1
fsaunit1 : stratixiii_first_stage_add_sub
GENERIC MAP (
dataa_width => datac_width,
datab_width => datad_width,
fsa_mode => first_adder1_mode
)
PORT MAP (
dataa => datac_fsa_in,
datab => datad_fsa_in,
sign => sign,
operation => operation,
dataout => dataout_fsa1
);
--Instantiate the zeroloopback pipeline Register
zeroloopback_clkval_pip <= "0000" WHEN ((zeroloopback_pipeline_clock = "0") or (zeroloopback_pipeline_clock = "none"))
ELSE "0001" WHEN (zeroloopback_pipeline_clock = "1")
ELSE "0010" WHEN (zeroloopback_pipeline_clock = "2")
ELSE "0011" WHEN (zeroloopback_pipeline_clock = "3")
ELSE "0000" ;
zeroloopback_aclrval_pip <= "0000" WHEN ((zeroloopback_pipeline_clear = "0") or (zeroloopback_pipeline_clear = "none"))
ELSE "0001" WHEN (zeroloopback_pipeline_clear = "1")
ELSE "0010" WHEN (zeroloopback_pipeline_clear = "2")
ELSE "0011" WHEN (zeroloopback_pipeline_clear = "3")
ELSE "0000" ;
zeroloopback_clk_pip <= '1' WHEN clk(conv_integer(zeroloopback_clkval_pip)) = '1' ELSE '0';
zeroloopback_aclr_pip <= '1' WHEN (aclr(conv_integer(zeroloopback_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroloopback_sload_pip <= '1' WHEN ena(conv_integer(zeroloopback_clkval_pip)) = '1' ELSE '0';
zeroloopback_bypass_register_pip <= '1' WHEN (zeroloopback_pipeline_clock = "none") ELSE '0';
zeroloopback_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => zeroloopback_in_reg,
clk => zeroloopback_clk_pip,
aclr => zeroloopback_aclr_pip,
sload => zeroloopback_sload_pip,
bypass_register => zeroloopback_bypass_register_pip,
dataout => zeroloopback_pip_reg
);
--Instantiate the zeroacc pipeline Register
zeroacc_clkval_pip <= "0000" WHEN ((zeroacc_pipeline_clock = "0") or (zeroacc_pipeline_clock = "none"))
ELSE "0001" WHEN (zeroacc_pipeline_clock = "1")
ELSE "0010" WHEN (zeroacc_pipeline_clock = "2")
ELSE "0011" WHEN (zeroacc_pipeline_clock = "3")
ELSE "0000" ;
zeroacc_aclrval_pip <= "0000" WHEN ((zeroacc_pipeline_clear = "0") or (zeroacc_pipeline_clear = "none"))
ELSE "0001" WHEN (zeroacc_pipeline_clear = "1")
ELSE "0010" WHEN (zeroacc_pipeline_clear = "2")
ELSE "0011" WHEN (zeroacc_pipeline_clear = "3")
ELSE "0000" ;
zeroacc_clk_pip <= '1' WHEN clk(conv_integer(zeroacc_clkval_pip)) = '1' ELSE '0';
zeroacc_aclr_pip <= '1' WHEN (aclr(conv_integer(zeroacc_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroacc_sload_pip <= '1' WHEN ena(conv_integer(zeroacc_clkval_pip)) = '1' ELSE '0';
zeroacc_bypass_register_pip <= '1' WHEN (zeroacc_pipeline_clock = "none") ELSE '0';
zeroacc_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => zeroacc_in_reg,
clk => zeroacc_clk_pip,
aclr => zeroacc_aclr_pip,
sload => zeroacc_sload_pip,
bypass_register => zeroacc_bypass_register_pip,
dataout => zeroacc_pip_reg
);
--Instantiate the signa pipeline Register
signa_clkval_pip <= "0000" WHEN ((signa_pipeline_clock = "0") or (signa_pipeline_clock = "none"))
ELSE "0001" WHEN (signa_pipeline_clock = "1")
ELSE "0010" WHEN (signa_pipeline_clock = "2")
ELSE "0011" WHEN (signa_pipeline_clock = "3")
ELSE "0000" ;
signa_aclrval_pip <= "0000" WHEN ((signa_pipeline_clear = "0") or (signa_pipeline_clear = "none"))
ELSE "0001" WHEN (signa_pipeline_clear = "1")
ELSE "0010" WHEN (signa_pipeline_clear = "2")
ELSE "0011" WHEN (signa_pipeline_clear = "3")
ELSE "0000" ;
signa_clk_pip <= '1' WHEN clk(conv_integer(signa_clkval_pip)) = '1' ELSE '0';
signa_aclr_pip <= '1' WHEN (aclr(conv_integer(signa_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signa_sload_pip <= '1' WHEN ena(conv_integer(signa_clkval_pip)) = '1' ELSE '0';
signa_bypass_register_pip <= '1' WHEN (signa_pipeline_clock = "none") ELSE '0';
signa_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => signa_in_reg,
clk => signa_clk_pip,
aclr => signa_aclr_pip,
sload => signa_sload_pip,
bypass_register => signa_bypass_register_pip,
dataout => signa_pip_reg
);
--Instantiate the signb pipeline Register
signb_clkval_pip <= "0000" WHEN ((signb_pipeline_clock = "0") or (signb_pipeline_clock = "none"))
ELSE "0001" WHEN (signb_pipeline_clock = "1")
ELSE "0010" WHEN (signb_pipeline_clock = "2")
ELSE "0011" WHEN (signb_pipeline_clock = "3")
ELSE "0000" ;
signb_aclrval_pip <= "0000" WHEN ((signb_pipeline_clear = "0") or (signb_pipeline_clear = "none"))
ELSE "0001" WHEN (signb_pipeline_clear = "1")
ELSE "0010" WHEN (signb_pipeline_clear = "2")
ELSE "0011" WHEN (signb_pipeline_clear = "3")
ELSE "0000" ;
signb_clk_pip <= '1' WHEN clk(conv_integer(signb_clkval_pip)) = '1' ELSE '0';
signb_aclr_pip <= '1' WHEN (aclr(conv_integer(signb_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
signb_sload_pip <= '1' WHEN ena(conv_integer(signb_clkval_pip)) = '1' ELSE '0';
signb_bypass_register_pip <= '1' WHEN (signb_pipeline_clock = "none") ELSE '0';
signb_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => signb_in_reg,
clk => signb_clk_pip,
aclr => signb_aclr_pip,
sload => signb_sload_pip,
bypass_register => signb_bypass_register_pip,
dataout => signb_pip_reg
);
--Instantiate the rotate pipeline Register
rotate_clkval_pip <= "0000" WHEN ((rotate_pipeline_clock = "0") or (rotate_pipeline_clock = "none"))
ELSE "0001" WHEN (rotate_pipeline_clock = "1")
ELSE "0010" WHEN (rotate_pipeline_clock = "2")
ELSE "0011" WHEN (rotate_pipeline_clock = "3")
ELSE "0000" ;
rotate_aclrval_pip <= "0000" WHEN ((rotate_pipeline_clear = "0") or (rotate_pipeline_clear = "none"))
ELSE "0001" WHEN (rotate_pipeline_clear = "1")
ELSE "0010" WHEN (rotate_pipeline_clear = "2")
ELSE "0011" WHEN (rotate_pipeline_clear = "3")
ELSE "0000" ;
rotate_clk_pip <= '1' WHEN clk(conv_integer(rotate_clkval_pip)) = '1' ELSE '0';
rotate_aclr_pip <= '1' WHEN (aclr(conv_integer(rotate_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rotate_sload_pip <= '1' WHEN ena(conv_integer(rotate_clkval_pip)) = '1' ELSE '0';
rotate_bypass_register_pip <= '1' WHEN (rotate_pipeline_clock = "none") ELSE '0';
rotate_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => rotate_in_reg,
clk => rotate_clk_pip,
aclr => rotate_aclr_pip,
sload => rotate_sload_pip,
bypass_register => rotate_bypass_register_pip,
dataout => rotate_pip_reg
);
--Instantiate the shiftright pipeline Register
shiftright_clkval_pip <= "0000" WHEN ((shiftright_pipeline_clock = "0") or (shiftright_pipeline_clock = "none"))
ELSE "0001" WHEN (shiftright_pipeline_clock = "1")
ELSE "0010" WHEN (shiftright_pipeline_clock = "2")
ELSE "0011" WHEN (shiftright_pipeline_clock = "3")
ELSE "0000" ;
shiftright_aclrval_pip <= "0000" WHEN ((shiftright_pipeline_clear = "0") or (shiftright_pipeline_clear = "none"))
ELSE "0001" WHEN (shiftright_pipeline_clear = "1")
ELSE "0010" WHEN (shiftright_pipeline_clear = "2")
ELSE "0011" WHEN (shiftright_pipeline_clear = "3")
ELSE "0000" ;
shiftright_clk_pip <= '1' WHEN clk(conv_integer(shiftright_clkval_pip)) = '1' ELSE '0';
shiftright_aclr_pip <= '1' WHEN (aclr(conv_integer(shiftright_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
shiftright_sload_pip <= '1' WHEN ena(conv_integer(shiftright_clkval_pip)) = '1' ELSE '0';
shiftright_bypass_register_pip <= '1' WHEN (shiftright_pipeline_clock = "none") ELSE '0';
shiftright_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => shiftright_in_reg,
clk => shiftright_clk_pip,
aclr => shiftright_aclr_pip,
sload => shiftright_sload_pip,
bypass_register => shiftright_bypass_register_pip,
dataout => shiftright_pip_reg
);
--Instantiate the round pipeline Register
round_clkval_pip <= "0000" WHEN ((round_pipeline_clock = "0") or (round_pipeline_clock = "none"))
ELSE "0001" WHEN (round_pipeline_clock = "1")
ELSE "0010" WHEN (round_pipeline_clock = "2")
ELSE "0011" WHEN (round_pipeline_clock = "3")
ELSE "0000" ;
round_aclrval_pip <= "0000" WHEN ((round_pipeline_clear = "0") or (round_pipeline_clear = "none"))
ELSE "0001" WHEN (round_pipeline_clear = "1")
ELSE "0010" WHEN (round_pipeline_clear = "2")
ELSE "0011" WHEN (round_pipeline_clear = "3")
ELSE "0000" ;
round_clk_pip <= '1' WHEN clk(conv_integer(round_clkval_pip)) = '1' ELSE '0';
round_aclr_pip <= '1' WHEN (aclr(conv_integer(round_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
round_sload_pip <= '1' WHEN ena(conv_integer(round_clkval_pip)) = '1' ELSE '0';
round_bypass_register_pip <= '1' WHEN (round_pipeline_clock = "none") ELSE '0';
round_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => round_in_reg,
clk => round_clk_pip,
aclr => round_aclr_pip,
sload => round_sload_pip,
bypass_register => round_bypass_register_pip,
dataout => round_pip_reg
);
--Instantiate the saturate pipeline Register
saturate_clkval_pip <= "0000" WHEN ((saturate_pipeline_clock = "0") or (saturate_pipeline_clock = "none"))
ELSE "0001" WHEN (saturate_pipeline_clock = "1")
ELSE "0010" WHEN (saturate_pipeline_clock = "2")
ELSE "0011" WHEN (saturate_pipeline_clock = "3")
ELSE "0000" ;
saturate_aclrval_pip <= "0000" WHEN ((saturate_pipeline_clear = "0") or (saturate_pipeline_clear = "none"))
ELSE "0001" WHEN (saturate_pipeline_clear = "1")
ELSE "0010" WHEN (saturate_pipeline_clear = "2")
ELSE "0011" WHEN (saturate_pipeline_clear = "3")
ELSE "0000" ;
saturate_clk_pip <= '1' WHEN clk(conv_integer(saturate_clkval_pip)) = '1' ELSE '0';
saturate_aclr_pip <= '1' WHEN (aclr(conv_integer(saturate_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturate_sload_pip <= '1' WHEN ena(conv_integer(saturate_clkval_pip)) = '1' ELSE '0';
saturate_bypass_register_pip <= '1' WHEN (saturate_pipeline_clock = "none") ELSE '0';
saturate_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => saturate_in_reg,
clk => saturate_clk_pip,
aclr => saturate_aclr_pip,
sload => saturate_sload_pip,
bypass_register => saturate_bypass_register_pip,
dataout => saturate_pip_reg
);
--Instantiate the roundchainout pipeline Register
roundchainout_clkval_pip <= "0000" WHEN ((roundchainout_pipeline_clock = "0") or (roundchainout_pipeline_clock = "none"))
ELSE "0001" WHEN (roundchainout_pipeline_clock = "1")
ELSE "0010" WHEN (roundchainout_pipeline_clock = "2")
ELSE "0011" WHEN (roundchainout_pipeline_clock = "3")
ELSE "0000" ;
roundchainout_aclrval_pip <= "0000" WHEN ((roundchainout_pipeline_clear = "0") or (roundchainout_pipeline_clear = "none"))
ELSE "0001" WHEN (roundchainout_pipeline_clear = "1")
ELSE "0010" WHEN (roundchainout_pipeline_clear = "2")
ELSE "0011" WHEN (roundchainout_pipeline_clear = "3")
ELSE "0000" ;
roundchainout_clk_pip <= '1' WHEN clk(conv_integer(roundchainout_clkval_pip)) = '1' ELSE '0';
roundchainout_aclr_pip <= '1' WHEN (aclr(conv_integer(roundchainout_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
roundchainout_sload_pip <= '1' WHEN ena(conv_integer(roundchainout_clkval_pip)) = '1' ELSE '0';
roundchainout_bypass_register_pip <= '1' WHEN (roundchainout_pipeline_clock = "none") ELSE '0';
roundchainout_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => roundchainout_in_reg,
clk => roundchainout_clk_pip,
aclr => roundchainout_aclr_pip,
sload => roundchainout_sload_pip,
bypass_register => roundchainout_bypass_register_pip,
dataout => roundchainout_pip_reg
);
--Instantiate the saturatechainout pipeline Register
saturatechainout_clkval_pip <= "0000" WHEN ((saturatechainout_pipeline_clock = "0") or (saturatechainout_pipeline_clock = "none"))
ELSE "0001" WHEN (saturatechainout_pipeline_clock = "1")
ELSE "0010" WHEN (saturatechainout_pipeline_clock = "2")
ELSE "0011" WHEN (saturatechainout_pipeline_clock = "3")
ELSE "0000" ;
saturatechainout_aclrval_pip <= "0000" WHEN ((saturatechainout_pipeline_clear = "0") or (saturatechainout_pipeline_clear = "none"))
ELSE "0001" WHEN (saturatechainout_pipeline_clear = "1")
ELSE "0010" WHEN (saturatechainout_pipeline_clear = "2")
ELSE "0011" WHEN (saturatechainout_pipeline_clear = "3")
ELSE "0000" ;
saturatechainout_clk_pip <= '1' WHEN clk(conv_integer(saturatechainout_clkval_pip)) = '1' ELSE '0';
saturatechainout_aclr_pip <= '1' WHEN (aclr(conv_integer(saturatechainout_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturatechainout_sload_pip <= '1' WHEN ena(conv_integer(saturatechainout_clkval_pip)) = '1' ELSE '0';
saturatechainout_bypass_register_pip <= '1' WHEN (saturatechainout_pipeline_clock = "none") ELSE '0';
saturatechainout_pipeline_register : stratixiii_mac_bit_register
PORT MAP (
datain => saturatechainout_in_reg,
clk => saturatechainout_clk_pip,
aclr => saturatechainout_aclr_pip,
sload => saturatechainout_sload_pip,
bypass_register => saturatechainout_bypass_register_pip,
dataout => saturatechainout_pip_reg
);
-- Instantiate fsa0 dataout pipline register
fsa_pip_datain1 <= dataa_fsa_in WHEN (operation_mode = "output_only") ELSE dataout_fsa0;
fsa0_clkval_pip <= "0000" WHEN ((first_adder0_clock = "0") or (first_adder0_clock = "none"))
ELSE "0001" WHEN (first_adder0_clock = "1")
ELSE "0010" WHEN (first_adder0_clock = "2")
ELSE "0011" WHEN (first_adder0_clock = "3")
ELSE "0000" ;
fsa0_aclrval_pip <= "0000" WHEN ((first_adder0_clear = "0") or (first_adder0_clear = "none"))
ELSE "0001" WHEN (first_adder0_clear = "1")
ELSE "0010" WHEN (first_adder0_clear = "2")
ELSE "0011" WHEN (first_adder0_clear = "3")
ELSE "0000" ;
fsa0_clk_pip <= '1' WHEN clk(conv_integer(fsa0_clkval_pip)) = '1' ELSE '0';
fsa0_aclr_pip <= '1' WHEN (aclr(conv_integer(fsa0_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
fsa0_sload_pip <= '1' WHEN ena(conv_integer(fsa0_clkval_pip)) = '1' ELSE '0';
fsa0_bypass_register_pip <= '1' WHEN (first_adder0_clock = "none") ELSE '0';
fsa0_pipeline_register : stratixiii_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => fsa_pip_datain1,
clk => fsa0_clk_pip,
aclr => fsa0_aclr_pip,
sload => fsa0_sload_pip,
bypass_register => fsa0_bypass_register_pip,
dataout => fsa0_pip_reg
);
-- Instantiate fsa1 dataout pipline register
fsa1_clkval_pip <= "0000" WHEN ((first_adder1_clock = "0") or (first_adder1_clock = "none"))
ELSE "0001" WHEN (first_adder1_clock = "1")
ELSE "0010" WHEN (first_adder1_clock = "2")
ELSE "0011" WHEN (first_adder1_clock = "3")
ELSE "0000" ;
fsa1_aclrval_pip <= "0000" WHEN ((first_adder1_clear = "0") or (first_adder1_clear = "none"))
ELSE "0001" WHEN (first_adder1_clear = "1")
ELSE "0010" WHEN (first_adder1_clear = "2")
ELSE "0011" WHEN (first_adder1_clear = "3")
ELSE "0000" ;
fsa1_clk_pip <= '1' WHEN clk(conv_integer(fsa1_clkval_pip)) = '1' ELSE '0';
fsa1_aclr_pip <= '1' WHEN (aclr(conv_integer(fsa1_aclrval_pip)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
fsa1_sload_pip <= '1' WHEN ena(conv_integer(fsa1_clkval_pip)) = '1' ELSE '0';
fsa1_bypass_register_pip <= '1' WHEN (first_adder1_clock = "none") ELSE '0';
fsa1_pipeline_register : stratixiii_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => dataout_fsa1,
clk => fsa1_clk_pip,
aclr => fsa1_aclr_pip,
sload => fsa1_sload_pip,
bypass_register => fsa1_bypass_register_pip,
dataout => fsa1_pip_reg
);
--Instantiate the second level adder/accumulator block
ssa_accum_in <= rs_dataout_out_reg WHEN (NOT zeroacc_pip_reg) = '1' ELSE (others => '0');
ssa_sign <= signa_pip_reg OR signb_pip_reg ;
ssa_unit : stratixiii_second_stage_add_accum
GENERIC MAP (
dataa_width => dataa_width + 1,
datab_width => datac_width + 1,
ssa_mode => acc_adder_operation
)
PORT MAP (
dataa => fsa0_pip_reg,
datab => fsa1_pip_reg,
accumin => ssa_accum_in,
sign => ssa_sign,
operation => operation,
dataout => ssa_dataout,
overflow => ssa_overflow
);
-- Instantiate round and saturation block
rs_datain <= fsa0_pip_reg when ((operation_mode = "output_only") or (operation_mode = "one_level_adder")or(operation_mode = "loopback"))
ELSE ssa_dataout ;
ssa_datain_width <= CONV_STD_LOGIC_VECTOR(dataa_width + 8,8) when ((operation_mode = "accumulator") or(operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out"))
ELSE CONV_STD_LOGIC_VECTOR(dataa_width +2,8) when(operation_mode = "two_level_adder")
ELSE CONV_STD_LOGIC_VECTOR(dataa_width + datab_width,8) when ((operation_mode = "shift" ) or (operation_mode = "36_bit_multiply" ))
ELSE CONV_STD_LOGIC_VECTOR(dataa_width + 8,8) when ((operation_mode = "double" ))
ELSE CONV_STD_LOGIC_VECTOR(dataa_width,8);
rs_block : stratixiii_round_saturate_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
operation_mode => operation_mode,
round_mode => round_mode,
saturate_mode => saturate_mode,
saturate_width => saturate_width,
round_width => round_width
)
PORT MAP (
datain => rs_datain,
round => round_pip_reg,
saturate => saturate_pip_reg,
signa => signa_pip_reg,
signb => signb_pip_reg,
datain_width => ssa_datain_width,
dataout => rs_dataout,
saturationoverflow => rs_saturation_overflow
);
--Instantiate the zeroloopback output Register
zeroloopback_clkval_or <= "0000" WHEN ((zeroloopback_output_clock = "0") or (zeroloopback_output_clock = "none"))
ELSE "0001" WHEN (zeroloopback_output_clock = "1")
ELSE "0010" WHEN (zeroloopback_output_clock = "2")
ELSE "0011" WHEN (zeroloopback_output_clock = "3")
ELSE "0000" ;
zeroloopback_aclrval_or <= "0000" WHEN ((zeroloopback_output_clear = "0") or (zeroloopback_output_clear = "none"))
ELSE "0001" WHEN (zeroloopback_output_clear = "1")
ELSE "0010" WHEN (zeroloopback_output_clear = "2")
ELSE "0011" WHEN (zeroloopback_output_clear = "3")
ELSE "0000" ;
zeroloopback_clk_or <= '1' WHEN clk(conv_integer(zeroloopback_clkval_or)) = '1' ELSE '0';
zeroloopback_aclr_or <= '1' WHEN (aclr(conv_integer(zeroloopback_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zeroloopback_sload_or <= '1' WHEN ena(conv_integer(zeroloopback_clkval_or)) = '1' ELSE '0';
zeroloopback_bypass_register_or <= '1' WHEN (zeroloopback_output_clock = "none") ELSE '0';
zeroloopback_output_register : stratixiii_mac_bit_register
PORT MAP (
datain => zeroloopback_pip_reg,
clk => zeroloopback_clk_or,
aclr => zeroloopback_aclr_or,
sload => zeroloopback_sload_or,
bypass_register => zeroloopback_bypass_register_or,
dataout => zeroloopback_out_reg
);
--Instantiate the zerochainout output Register
zerochainout_clkval_or <= "0000" WHEN ((zerochainout_output_clock = "0") or (zerochainout_output_clock = "none"))
ELSE "0001" WHEN (zerochainout_output_clock = "1")
ELSE "0010" WHEN (zerochainout_output_clock = "2")
ELSE "0011" WHEN (zerochainout_output_clock = "3")
ELSE "0000" ;
zerochainout_aclrval_or <= "0000" WHEN ((zerochainout_output_clear = "0") or (zerochainout_output_clear = "none"))
ELSE "0001" WHEN (zerochainout_output_clear = "1")
ELSE "0010" WHEN (zerochainout_output_clear = "2")
ELSE "0011" WHEN (zerochainout_output_clear = "3")
ELSE "0000" ;
zerochainout_clk_or <= '1' WHEN clk(conv_integer(zerochainout_clkval_or)) = '1' ELSE '0';
zerochainout_aclr_or <= '1' WHEN (aclr(conv_integer(zerochainout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
zerochainout_sload_or <= '1' WHEN ena(conv_integer(zerochainout_clkval_or)) = '1' ELSE '0';
zerochainout_bypass_register_or <= '1' WHEN (zerochainout_output_clock = "none") ELSE '0';
zerochainout_output_register : stratixiii_mac_bit_register
PORT MAP (
datain => zerochainout,
clk => zerochainout_clk_or,
aclr => zerochainout_aclr_or,
sload => zerochainout_sload_or,
bypass_register => zerochainout_bypass_register_or,
dataout => zerochainout_out_reg
);
-- Instantiate Round_Saturate dataout output register
rs_dataout_clkval_or_co <= "0000" WHEN ((second_adder_clock = "0") or (second_adder_clock = "none"))
ELSE "0001" WHEN (second_adder_clock = "1")
ELSE "0010" WHEN (second_adder_clock = "2")
ELSE "0011" WHEN (second_adder_clock = "3")
ELSE "0000" ;
rs_dataout_aclrval_or_co <= "0000" WHEN ((second_adder_clear = "0") or (second_adder_clear = "none"))
ELSE "0001" WHEN (second_adder_clear = "1")
ELSE "0010" WHEN (second_adder_clear = "2")
ELSE "0011" WHEN (second_adder_clear = "3")
ELSE "0000" ;
rs_dataout_clkval_or_o <= "0000" WHEN ((output_clock = "0") or (output_clock = "none"))
ELSE "0001" WHEN (output_clock = "1")
ELSE "0010" WHEN (output_clock = "2")
ELSE "0011" WHEN (output_clock = "3")
ELSE "0000" ;
rs_dataout_aclrval_or_o <= "0000" WHEN ((output_clear = "0") or (output_clear = "none"))
ELSE "0001" WHEN (output_clear = "1")
ELSE "0010" WHEN (output_clear = "2")
ELSE "0011" WHEN (output_clear = "3")
ELSE "0000" ;
rs_dataout_aclrval_or <= rs_dataout_aclrval_or_co WHEN ((operation_mode = "two_level_adder_chain_out") or (operation_mode = "accumulator_chain_out" ))
ELSE rs_dataout_aclrval_or_o;
rs_dataout_clkval_or <= rs_dataout_clkval_or_co WHEN ((operation_mode = "two_level_adder_chain_out") or (operation_mode = "accumulator_chain_out" ))
ELSE rs_dataout_clkval_or_o;
rs_dataout_bypass_register_or_co <= '1' WHEN (second_adder_clock = "none") ELSE '0';
rs_dataout_bypass_register_or_o <= '1' WHEN (output_clock = "none") ELSE '0';
rs_dataout_clk_or <= '1' WHEN clk(conv_integer(rs_dataout_clkval_or)) = '1' ELSE '0';
rs_dataout_aclr_or <= '1' WHEN (aclr(conv_integer(rs_dataout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rs_dataout_sload_or <= '1' WHEN ena(conv_integer(rs_dataout_clkval_or)) = '1' ELSE '0';
rs_dataout_bypass_register_or <= rs_dataout_bypass_register_or_co WHEN ((operation_mode = "two_level_adder_chain_out") or (operation_mode = "accumulator_chain_out" ))
ELSE rs_dataout_bypass_register_or_o;
rs_dataout_in <= ssa_dataout WHEN ((operation_mode = "36_bit_multiply") OR (operation_mode = "shift")) ELSE rs_dataout_of;
rs_dataout_output_register : stratixiii_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => rs_dataout_in,
clk => rs_dataout_clk_or,
aclr => rs_dataout_aclr_or,
sload => rs_dataout_sload_or,
bypass_register => rs_dataout_bypass_register_or,
dataout => rs_dataout_out_reg
);
-- Instantiate Round_Saturate saturation_overflow output register
rs_saturation_overflow_in <= rs_saturation_overflow WHEN (saturate_pip_reg = '1') ELSE ssa_overflow;
rs_saturation_overflow_output_register : stratixiii_mac_bit_register
PORT MAP (
datain => rs_saturation_overflow_in,
clk => rs_dataout_clk_or,
aclr => rs_dataout_aclr_or,
sload => rs_dataout_sload_or,
bypass_register => rs_dataout_bypass_register_or,
dataout => rs_saturation_overflow_out_reg
);
--Instantiate the rotate output Register
rotate_clkval_or <= "0000" WHEN ((rotate_output_clock = "0") or (rotate_output_clock = "none"))
ELSE "0001" WHEN (rotate_output_clock = "1")
ELSE "0010" WHEN (rotate_output_clock = "2")
ELSE "0011" WHEN (rotate_output_clock = "3")
ELSE "0000" ;
rotate_aclrval_or <= "0000" WHEN ((rotate_output_clear = "0") or (rotate_output_clear = "none"))
ELSE "0001" WHEN (rotate_output_clear = "1")
ELSE "0010" WHEN (rotate_output_clear = "2")
ELSE "0011" WHEN (rotate_output_clear = "3")
ELSE "0000" ;
rotate_clk_or <= '1' WHEN clk(conv_integer(rotate_clkval_or)) = '1' ELSE '0';
rotate_aclr_or <= '1' WHEN (aclr(conv_integer(rotate_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
rotate_sload_or <= '1' WHEN ena(conv_integer(rotate_clkval_or)) = '1' ELSE '0';
rotate_bypass_register_or <= '1' WHEN (rotate_output_clock = "none") ELSE '0';
rotate_output_register : stratixiii_mac_bit_register
PORT MAP (
datain => rotate_pip_reg,
clk => rotate_clk_or,
aclr => rotate_aclr_or,
sload => rotate_sload_or,
bypass_register => rotate_bypass_register_or,
dataout => rotate_out_reg
);
--Instantiate the shiftright output Register
shiftright_output_register : stratixiii_mac_bit_register
PORT MAP (
datain => shiftright_pip_reg,
clk => shiftright_clk_or,
aclr => shiftright_aclr_or,
sload => shiftright_sload_or,
bypass_register => shiftright_bypass_register_or,
dataout => shiftright_out_reg
);
shiftright_clkval_or <= "0000" WHEN ((shiftright_output_clock = "0") or (shiftright_output_clock = "none"))
ELSE "0001" WHEN (shiftright_output_clock = "1")
ELSE "0010" WHEN (shiftright_output_clock = "2")
ELSE "0011" WHEN (shiftright_output_clock = "3")
ELSE "0000" ;
shiftright_aclrval_or <= "0000" WHEN ((shiftright_output_clear = "0") or (shiftright_output_clear = "none"))
ELSE "0001" WHEN (shiftright_output_clear = "1")
ELSE "0010" WHEN (shiftright_output_clear = "2")
ELSE "0011" WHEN (shiftright_output_clear = "3")
ELSE "0000" ;
shiftright_clk_or <= '1' WHEN clk(conv_integer(shiftright_clkval_or)) = '1' ELSE '0';
shiftright_aclr_or <= '1' WHEN (aclr(conv_integer(shiftright_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
shiftright_sload_or <= '1' WHEN ena(conv_integer(shiftright_clkval_or)) = '1' ELSE '0';
shiftright_bypass_register_or <= '1' WHEN (shiftright_output_clock = "none") ELSE '0';
--Instantiate the roundchainout output Register
roundchainout_clkval_or <= "0000" WHEN ((roundchainout_output_clock = "0") or (roundchainout_output_clock = "none"))
ELSE "0001" WHEN (roundchainout_output_clock = "1")
ELSE "0010" WHEN (roundchainout_output_clock = "2")
ELSE "0011" WHEN (roundchainout_output_clock = "3")
ELSE "0000" ;
roundchainout_aclrval_or <= "0000" WHEN ((roundchainout_output_clear = "0") or (roundchainout_output_clear = "none"))
ELSE "0001" WHEN (roundchainout_output_clear = "1")
ELSE "0010" WHEN (roundchainout_output_clear = "2")
ELSE "0011" WHEN (roundchainout_output_clear = "3")
ELSE "0000" ;
roundchainout_clk_or <= '1' WHEN clk(conv_integer(roundchainout_clkval_or)) = '1' ELSE '0';
roundchainout_aclr_or <= '1' WHEN (aclr(conv_integer(roundchainout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
roundchainout_sload_or <= '1' WHEN ena(conv_integer(roundchainout_clkval_or)) = '1' ELSE '0';
roundchainout_bypass_register_or <= '1' WHEN (roundchainout_output_clock = "none") ELSE '0';
roundchainout_output_register : stratixiii_mac_bit_register
PORT MAP (
datain => roundchainout_pip_reg,
clk => roundchainout_clk_or,
aclr => roundchainout_aclr_or,
sload => roundchainout_sload_or,
bypass_register => roundchainout_bypass_register_or,
dataout => roundchainout_out_reg
);
--Instantiate the saturatechainout output Register
saturatechainout_clkval_or <= "0000" WHEN ((saturatechainout_output_clock = "0") or (saturatechainout_output_clock = "none"))
ELSE "0001" WHEN (saturatechainout_output_clock = "1")
ELSE "0010" WHEN (saturatechainout_output_clock = "2")
ELSE "0011" WHEN (saturatechainout_output_clock = "3")
ELSE "0000" ;
saturatechainout_aclrval_or <= "0000" WHEN ((saturatechainout_output_clear = "0") or (saturatechainout_output_clear = "none"))
ELSE "0001" WHEN (saturatechainout_output_clear = "1")
ELSE "0010" WHEN (saturatechainout_output_clear = "2")
ELSE "0011" WHEN (saturatechainout_output_clear = "3")
ELSE "0000" ;
saturatechainout_clk_or <= '1' WHEN clk(conv_integer(saturatechainout_clkval_or)) = '1' ELSE '0';
saturatechainout_aclr_or <= '1' WHEN (aclr(conv_integer(saturatechainout_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
saturatechainout_sload_or <= '1' WHEN ena(conv_integer(saturatechainout_clkval_or)) = '1' ELSE '0';
saturatechainout_bypass_register_or <= '1' WHEN (saturatechainout_output_clock = "none") ELSE '0';
saturatechainout_output_register : stratixiii_mac_bit_register
PORT MAP (
datain => saturatechainout_pip_reg,
clk => saturatechainout_clk_or,
aclr => saturatechainout_aclr_or,
sload => saturatechainout_sload_or,
bypass_register => saturatechainout_bypass_register_or,
dataout => saturatechainout_out_reg
);
--Instantiate the Carry chainout Adder
chainout_adder : stratixiii_carry_chain_adder
PORT MAP (
dataa => rs_dataout_out_reg,
datab => chainin_coa_in,
dataout => coa_dataout
);
--Instantiate the carry chainout adder RS Block
coa_rs_block : stratixiii_round_saturate_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width,
operation_mode => operation_mode,
round_mode => round_chain_out_mode,
saturate_mode => saturate_chain_out_mode,
saturate_width => saturate_chain_out_width,
round_width => round_chain_out_width
)
PORT MAP (
datain => coa_dataout,
round => roundchainout_out_reg,
saturate => saturatechainout_out_reg,
signa => signa_pip_reg,
signb => signb_pip_reg,
datain_width => ssa_datain_width,
dataout => coa_rs_dataout,
saturationoverflow => coa_rs_saturation_overflow
);
--Instantiate the rs_saturation_overflow output register (after COA)
coa_reg_clkval_or <= "0000" WHEN ((output_clock = "0") or (output_clock = "none"))
ELSE "0001" WHEN (output_clock = "1")
ELSE "0010" WHEN (output_clock = "2")
ELSE "0011" WHEN (output_clock = "3")
ELSE "0000" ;
coa_reg_aclrval_or <= "0000" WHEN ((output_clear = "0") or (output_clear = "none"))
ELSE "0001" WHEN (output_clear = "1")
ELSE "0010" WHEN (output_clear = "2")
ELSE "0011" WHEN (output_clear = "3")
ELSE "0000" ;
coa_reg_clk_or <= '1' WHEN clk(conv_integer(coa_reg_clkval_or)) = '1' ELSE '0';
coa_reg_aclr_or <= '1' WHEN (aclr(conv_integer(coa_reg_aclrval_or)) OR NOT devclrn OR NOT devpor) = '1' ELSE '0';
coa_reg_sload_or <= '1' WHEN ena(conv_integer(coa_reg_clkval_or)) = '1' ELSE '0';
coa_reg_bypass_register_or <= '1' WHEN (output_clock = "none") ELSE '0';
coa_rs_saturation_overflow_register : stratixiii_mac_bit_register
PORT MAP (
datain => rs_saturation_overflow_out_reg,
clk => coa_reg_clk_or,
aclr => coa_reg_aclr_or,
sload => coa_reg_sload_or,
bypass_register => '1',
dataout => coa_rs_saturation_overflow_out_reg
);
--Instantiate the rs_saturationchainout_overflow output register
coa_rs_saturationchainout_overflow_register : stratixiii_mac_bit_register
PORT MAP (
datain => coa_rs_saturation_overflow,
clk => coa_reg_clk_or,
aclr => coa_reg_aclr_or,
sload => coa_reg_sload_or,
bypass_register => coa_reg_bypass_register_or,
dataout => coa_rs_saturationchainout_overflow_out_reg
);
-- Instantiate the coa_rs_dataout output register
coa_rs_dataout_register : stratixiii_mac_register
GENERIC MAP (
data_width => 72
)
PORT MAP (
datain => coa_rs_dataout,
clk => coa_reg_clk_or,
aclr => coa_reg_aclr_or,
sload => coa_reg_sload_or,
bypass_register => coa_reg_bypass_register_or,
dataout => coa_rs_dataout_out_reg
);
--Instantiate the shift/Rotate Unit
shift_rot_unit : stratixiii_rotate_shift_block
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width
)
PORT MAP (
datain => rs_dataout_out_reg,
rotate => rotate_out_reg,
shiftright => shiftright_out_reg,
signa => signa_pip_reg,
signb => signb_pip_reg,
dataout => dataout_shift_rot
);
--Assign the dataout depENDing on the mode of operation
dataout_tmp <= coa_rs_dataout_out_reg when((operation_mode = "accumulator_chain_out")or(operation_mode = "two_level_adder_chain_out"))
ELSE dataout_shift_rot when (operation_mode = "shift")
ELSE rs_dataout_out_reg;
--Assign the loopbackout for loopback mode
loopbackout_tmp <= rs_dataout_out_reg when((operation_mode = "loopback") and (zeroloopback_out_reg = '0'))
ELSE (others => '0');
--Assign the saturation overflow output
saturation_overflow_tmp <= rs_saturation_overflow_out_reg when((operation_mode = "accumulator") or(operation_mode = "two_level_adder"))
ELSE coa_rs_saturation_overflow_out_reg when((operation_mode = "accumulator_chain_out")or(operation_mode = "two_level_adder_chain_out"))
ELSE '0';
--Assign the saturationchainout overflow output
saturationchainout_overflow_tmp <= coa_rs_saturationchainout_overflow_out_reg when((operation_mode = "accumulator_chain_out") or(operation_mode = "two_level_adder_chain_out"))
ELSE '0';
dataout <= (others => '0') WHEN (((operation_mode = "accumulator_chain_out")or(operation_mode = "two_level_adder_chain_out")) and (zerochainout_out_reg = '1'))
ELSE dataout_tmp;
loopbackout <= loopbackout_tmp(35 downto 18);
overflow <= saturation_overflow_tmp;
saturatechainoutoverflow <= saturationchainout_overflow_tmp;
END arch;
----------------------------------------------------------------------------
-- Module Name : stratixiii_io_pad
-- Description : Simulation model for stratixiii IO pad
----------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
ENTITY stratixiii_io_pad IS
GENERIC (
lpm_type : string := "stratixiii_io_pad");
PORT (
--INPUT PORTS
padin : IN std_logic := '0'; -- Input Pad
--OUTPUT PORTS
padout : OUT std_logic); -- Output Pad
END stratixiii_io_pad;
ARCHITECTURE arch OF stratixiii_io_pad IS
BEGIN
padout <= padin;
END arch;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixiii_mn_cntr
--
-- Description : Timing simulation model for the M and N counter. This is a
-- common model for the input counter and the loop feedback
-- counter of the StratixII PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY stratixiii_mn_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END stratixiii_mn_cntr;
ARCHITECTURE behave of stratixiii_mn_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixiii_scale_cntr
--
-- Description : Timing simulation model for the output scale-down counters.
-- This is a common model for the C0, C1, C2, C3, C4 and C5
-- output counters of the StratixII PLL.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY stratixiii_scale_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0;
cout : OUT std_logic
);
END stratixiii_scale_cntr;
ARCHITECTURE behave of stratixiii_scale_cntr is
begin
process (clk, reset)
variable tmp_cout : std_logic := '0';
variable count : integer := 1;
variable output_shift_count : integer := 1;
variable first_rising_edge : boolean := false;
begin
if (reset = '1') then
count := 1;
output_shift_count := 1;
tmp_cout := '0';
first_rising_edge := false;
elsif (clk'event) then
if (mode = " off") then
tmp_cout := '0';
elsif (mode = "bypass") then
tmp_cout := clk;
first_rising_edge := true;
elsif (not first_rising_edge) then
if (clk = '1') then
if (output_shift_count = initial) then
tmp_cout := clk;
first_rising_edge := true;
else
output_shift_count := output_shift_count + 1;
end if;
end if;
elsif (output_shift_count < initial) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
end if;
else
count := count + 1;
if (mode = " even" and (count = (high*2) + 1)) then
tmp_cout := '0';
elsif (mode = " odd" and (count = high*2)) then
tmp_cout := '0';
elsif (count = (high + low)*2 + 1) then
tmp_cout := '1';
count := 1; -- reset count
end if;
end if;
end if;
cout <= transport tmp_cout;
end process;
end behave;
--BEGIN MF PORTING DELETE
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixiii_pll_reg
--
-- Description : Simulation model for a simple DFF.
-- This is required for the generation of the bit slip-signals.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY stratixiii_pll_reg is
PORT( clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end stratixiii_pll_reg;
ARCHITECTURE behave of stratixiii_pll_reg is
begin
process (clk, prn, clrn)
variable q_reg : std_logic := '0';
begin
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk'event and clk = '1' and (ena = '1')) then
q_reg := D;
end if;
Q <= q_reg;
end process;
end behave;
--END MF PORTING DELETE
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : stratixiii_pll
--
-- Description : Timing simulation model for the StratixII PLL.
-- In the functional mode, it is also the model for the altpll
-- megafunction.
--
-- Limitations : Does not support Spread Spectrum and Bandwidth.
--
-- Outputs : Up to 10 output clocks, each defined by its own set of
-- parameters. Locked output (active high) indicates when the
-- PLL locks. clkbad and activeclock are used for
-- clock switchover to indicate which input clock has gone
-- bad, when the clock switchover initiates and which input
-- clock is being used as the reference, respectively.
-- scandataout is the data output of the serial scan chain.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE STD.TEXTIO.all;
USE work.stratixiii_atom_pack.all;
USE work.stratixiii_pllpack.all;
USE work.stratixiii_mn_cntr;
USE work.stratixiii_scale_cntr;
USE work.stratixiii_dffe;
USE work.stratixiii_pll_reg;
-- New Features : The list below outlines key new features in STRATIXIII:
-- 1. Dynamic Phase Reconfiguration
-- 2. Dynamic PLL Reconfiguration (different protocol)
-- 3. More output counters
ENTITY stratixiii_pll is
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
dpa_multiply_by : integer := 0;
dpa_divide_by : integer := 0;
dpa_divider : integer := 0;
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 0;
clk5_divide_by : integer := 0;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
clk6_output_frequency : integer := 0;
clk6_multiply_by : integer := 0;
clk6_divide_by : integer := 0;
clk6_phase_shift : string := "0";
clk6_duty_cycle : integer := 50;
clk7_output_frequency : integer := 0;
clk7_multiply_by : integer := 0;
clk7_divide_by : integer := 0;
clk7_phase_shift : string := "0";
clk7_duty_cycle : integer := 50;
clk8_output_frequency : integer := 0;
clk8_multiply_by : integer := 0;
clk8_divide_by : integer := 0;
clk8_phase_shift : string := "0";
clk8_duty_cycle : integer := 50;
clk9_output_frequency : integer := 0;
clk9_multiply_by : integer := 0;
clk9_divide_by : integer := 0;
clk9_phase_shift : string := "0";
clk9_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
c6_high : integer := 1;
c6_low : integer := 1;
c6_initial : integer := 1;
c6_mode : string := "bypass";
c6_ph : integer := 0;
c7_high : integer := 1;
c7_low : integer := 1;
c7_initial : integer := 1;
c7_mode : string := "bypass";
c7_ph : integer := 0;
c8_high : integer := 1;
c8_low : integer := 1;
c8_initial : integer := 1;
c8_mode : string := "bypass";
c8_ph : integer := 0;
c9_high : integer := 1;
c9_low : integer := 1;
c9_initial : integer := 1;
c9_mode : string := "bypass";
c9_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
clk5_counter : string := "unused";
clk6_counter : string := "unused";
clk7_counter : string := "unused";
clk8_counter : string := "unused";
clk9_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
c6_use_casc_in : string := "off";
c7_use_casc_in : string := "off";
c8_use_casc_in : string := "off";
c9_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
c5_test_source : integer := -1;
c6_test_source : integer := -1;
c7_test_source : integer := -1;
c8_test_source : integer := -1;
c9_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "stratixiii_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk6_use_even_counter_mode : string := "off";
clk7_use_even_counter_mode : string := "off";
clk8_use_even_counter_mode : string := "off";
clk9_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
clk6_use_even_counter_value : string := "off";
clk7_use_even_counter_value : string := "off";
clk8_use_even_counter_value : string := "off";
clk9_use_even_counter_value : string := "off";
-- Test only
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_c6_delay_chain_bits : integer := 0;
test_counter_c7_delay_chain_bits : integer := 0;
test_counter_c8_delay_chain_bits : integer := 0;
test_counter_c9_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
dpa_output_clock_phase_shift : integer := 0;
test_counter_c3_sclk_delay_chain_bits : integer := -1;
test_counter_c4_sclk_delay_chain_bits : integer := -1;
test_counter_c5_lden_delay_chain_bits : integer := -1;
test_counter_c6_lden_delay_chain_bits : integer := -1;
auto_settings : string := "true";
-- Simulation only generics
family_name : string := "StratixIII";
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(3 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(9 downto 0);
phasecounterselect : in std_logic_vector(3 downto 0) := "0000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END stratixiii_pll;
ARCHITECTURE vital_pll of stratixiii_pll is
TYPE int_array is ARRAY(NATURAL RANGE <>) of integer;
TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6);
TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9);
TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic;
-- internal advanced parameter signals
signal i_vco_min : integer := vco_min * (vco_post_scale/2);
signal i_vco_max : integer := vco_max * (vco_post_scale/2);
signal i_vco_center : integer;
signal i_pfd_min : integer;
signal i_pfd_max : integer;
signal c_ph_val : int_array(0 to 9) := (OTHERS => 0);
signal c_ph_val_tmp : int_array(0 to 9) := (OTHERS => 0);
signal c_high_val : int_array(0 to 9) := (OTHERS => 1);
signal c_low_val : int_array(0 to 9) := (OTHERS => 1);
signal c_initial_val : int_array(0 to 9) := (OTHERS => 1);
signal c_mode_val : str_array(0 to 9);
signal clk_num : str_array(0 to 9);
-- old values
signal c_high_val_old : int_array(0 to 9) := (OTHERS => 1);
signal c_low_val_old : int_array(0 to 9) := (OTHERS => 1);
signal c_ph_val_old : int_array(0 to 9) := (OTHERS => 0);
signal c_mode_val_old : str_array(0 to 9);
-- hold registers
signal c_high_val_hold : int_array(0 to 9) := (OTHERS => 1);
signal c_low_val_hold : int_array(0 to 9) := (OTHERS => 1);
signal c_ph_val_hold : int_array(0 to 9) := (OTHERS => 0);
signal c_mode_val_hold : str_array(0 to 9);
-- temp registers
signal sig_c_ph_val_tmp : int_array(0 to 9) := (OTHERS => 0);
signal c_ph_val_orig : int_array(0 to 9) := (OTHERS => 0);
signal i_clk9_counter : integer := 9;
signal i_clk8_counter : integer := 8;
signal i_clk7_counter : integer := 7;
signal i_clk6_counter : integer := 6;
signal i_clk5_counter : integer := 5;
signal real_lock_high : integer := 0;
signal i_clk4_counter : integer := 4;
signal i_clk3_counter : integer := 3;
signal i_clk2_counter : integer := 2;
signal i_clk1_counter : integer := 1;
signal i_clk0_counter : integer := 0;
signal i_charge_pump_current : integer;
signal i_loop_filter_r : integer;
-- end internal advanced parameter signals
-- CONSTANTS
CONSTANT SCAN_CHAIN : integer := 144;
CONSTANT GPP_SCAN_CHAIN : integer := 234;
CONSTANT FAST_SCAN_CHAIN : integer := 180;
CONSTANT cntrs : str_array(9 downto 0) := (" C9", " C8", " C7", " C6", " C5", " C4", " C3", " C2", " C1", " C0");
CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2");
CONSTANT loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
CONSTANT num_phase_taps : integer := 8;
-- signals
signal vcc : std_logic := '1';
signal fbclk : std_logic;
signal refclk : std_logic;
signal vco_over : std_logic := '0';
signal vco_under : std_logic := '1';
signal pll_locked : boolean := false;
signal c_clk : std_logic_array(0 to 9);
signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0');
-- signals to assign values to counter params
signal m_val : integer := 1;
signal n_val : integer := 1;
signal m_ph_val : integer := 0;
signal m_ph_initial : integer := 0;
signal m_ph_val_tmp : integer := 0;
signal m_initial_val : integer := m_initial;
signal m_mode_val : string(1 to 6) := " ";
signal n_mode_val : string(1 to 6) := " ";
signal lfc_val : integer := 0;
signal vco_cur : integer := vco_post_scale;
signal cp_curr_val : integer := 0;
signal lfr_val : string(1 to 2) := " ";
signal cp_curr_old_bit_setting : integer := charge_pump_current_bits;
signal cp_curr_val_bit_setting : std_logic_vector(2 downto 0) := (OTHERS => '0');
signal lfr_old_bit_setting : integer := loop_filter_r_bits;
signal lfr_val_bit_setting : std_logic_vector(4 downto 0) := (OTHERS => '0');
signal lfc_old_bit_setting : integer := loop_filter_c_bits;
signal lfc_val_bit_setting : std_logic_vector(1 downto 0) := (OTHERS => '0');
signal pll_reconfig_display_full_setting : boolean := FALSE; -- display full setting, change to true
-- old values
signal m_val_old : integer := 1;
signal n_val_old : integer := 1;
signal m_mode_val_old : string(1 to 6) := " ";
signal n_mode_val_old : string(1 to 6) := " ";
signal m_ph_val_old : integer := 0;
signal lfc_old : integer := 0;
signal vco_old : integer := 0;
signal cp_curr_old : integer := 0;
signal lfr_old : string(1 to 2) := " ";
signal num_output_cntrs : integer := 10;
signal scanclk_period : time := 1 ps;
signal scan_data : std_logic_vector(0 to 233) := (OTHERS => '0');
signal clk_pfd : std_logic_vector(0 to 9);
signal clk0_tmp : std_logic;
signal clk1_tmp : std_logic;
signal clk2_tmp : std_logic;
signal clk3_tmp : std_logic;
signal clk4_tmp : std_logic;
signal clk5_tmp : std_logic;
signal clk6_tmp : std_logic;
signal clk7_tmp : std_logic;
signal clk8_tmp : std_logic;
signal clk9_tmp : std_logic;
signal update_conf_latches : std_logic := '0';
signal update_conf_latches_reg : std_logic := '0';
signal clkin : std_logic := '0';
signal gate_locked : std_logic := '0';
signal pfd_locked : std_logic := '0';
signal lock : std_logic := '0';
signal about_to_lock : boolean := false;
signal reconfig_err : boolean := false;
signal inclk_c0 : std_logic;
signal inclk_c1 : std_logic;
signal inclk_c2 : std_logic;
signal inclk_c3 : std_logic;
signal inclk_c4 : std_logic;
signal inclk_c5 : std_logic;
signal inclk_c6 : std_logic;
signal inclk_c7 : std_logic;
signal inclk_c8 : std_logic;
signal inclk_c9 : std_logic;
signal inclk_m : std_logic;
signal devpor : std_logic;
signal devclrn : std_logic;
signal inclk0_ipd : std_logic;
signal inclk1_ipd : std_logic;
signal pfdena_ipd : std_logic;
signal areset_ipd : std_logic;
signal fbin_ipd : std_logic;
signal scanclk_ipd : std_logic;
signal scanclkena_ipd, scanclkena_reg : std_logic;
signal scandata_ipd : std_logic;
signal clkswitch_ipd : std_logic;
signal phasecounterselect_ipd : std_logic_vector(3 downto 0);
signal phaseupdown_ipd : std_logic;
signal phasestep_ipd : std_logic;
signal configupdate_ipd : std_logic;
-- registered signals
signal sig_offset : time := 0 ps;
signal sig_refclk_time : time := 0 ps;
signal sig_fbclk_period : time := 0 ps;
signal sig_vco_period_was_phase_adjusted : boolean := false;
signal sig_phase_adjust_was_scheduled : boolean := false;
signal sig_stop_vco : std_logic := '0';
signal sig_m_times_vco_period : time := 0 ps;
signal sig_new_m_times_vco_period : time := 0 ps;
signal sig_got_refclk_posedge : boolean := false;
signal sig_got_fbclk_posedge : boolean := false;
signal sig_got_second_refclk : boolean := false;
signal m_delay : integer := 0;
signal n_delay : integer := 0;
signal inclk1_tmp : std_logic := '0';
signal reset_low : std_logic := '0';
-- Phase Reconfig
SIGNAL phasecounterselect_reg : std_logic_vector(3 DOWNTO 0);
SIGNAL phaseupdown_reg : std_logic := '0';
SIGNAL phasestep_reg : std_logic := '0';
SIGNAL phasestep_high_count : integer := 0;
SIGNAL update_phase : std_logic := '0';
signal scandataout_tmp : std_logic := '0';
signal scandata_in : std_logic := '0';
signal scandata_out : std_logic := '0';
signal scandone_tmp : std_logic := '1';
signal initiate_reconfig : std_logic := '0';
signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n;
signal schedule_vco : std_logic := '0';
signal areset_ena_sig : std_logic := '0';
signal pll_in_test_mode : boolean := false;
signal pll_has_just_been_reconfigured : boolean := false;
signal inclk_c_from_vco : std_logic_array(0 to 9);
signal inclk_m_from_vco : std_logic;
SIGNAL inclk0_period : time := 0 ps;
SIGNAL last_inclk0_period : time := 0 ps;
SIGNAL last_inclk0_edge : time := 0 ps;
SIGNAL first_inclk0_edge_detect : STD_LOGIC := '0';
SIGNAL inclk1_period : time := 0 ps;
SIGNAL last_inclk1_period : time := 0 ps;
SIGNAL last_inclk1_edge : time := 0 ps;
SIGNAL first_inclk1_edge_detect : STD_LOGIC := '0';
COMPONENT stratixiii_mn_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END COMPONENT;
COMPONENT stratixiii_scale_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0
);
END COMPONENT;
COMPONENT stratixiii_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
COMPONENT stratixiii_pll_reg
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0));
VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1));
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (fbin_ipd, fbin, tipd_fbin);
VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena);
VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk);
VitalWireDelay (scanclkena_ipd, scanclkena, tipd_scanclkena);
VitalWireDelay (scandata_ipd, scandata, tipd_scandata);
VitalWireDelay (configupdate_ipd, configupdate, tipd_configupdate);
VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch);
VitalWireDelay (phaseupdown_ipd, phaseupdown, tipd_phaseupdown);
VitalWireDelay (phasestep_ipd, phasestep, tipd_phasestep);
VitalWireDelay (phasecounterselect_ipd(0), phasecounterselect(0), tipd_phasecounterselect(0));
VitalWireDelay (phasecounterselect_ipd(1), phasecounterselect(1), tipd_phasecounterselect(1));
VitalWireDelay (phasecounterselect_ipd(2), phasecounterselect(2), tipd_phasecounterselect(2));
VitalWireDelay (phasecounterselect_ipd(3), phasecounterselect(3), tipd_phasecounterselect(3));
end block;
inclk_m <= fbclk when m_test_source = 0 else
refclk when m_test_source = 1 else
inclk_m_from_vco;
areset_ena_sig <= areset_ipd or sig_stop_vco;
pll_in_test_mode <= true when (m_test_source /= -1 or c0_test_source /= -1 or
c1_test_source /= -1 or c2_test_source /= -1 or
c3_test_source /= -1 or c4_test_source /= -1 or
c5_test_source /= -1 or c6_test_source /= -1 or
c7_test_source /= -1 or c8_test_source /= -1 or
c9_test_source /= -1)
else
false;
real_lock_high <= lock_high WHEN (sim_gate_lock_device_behavior = "on") ELSE 0;
m1 : stratixiii_mn_cntr
port map ( clk => inclk_m,
reset => areset_ena_sig,
cout => fbclk,
initial_value => m_initial_val,
modulus => m_val,
time_delay => m_delay
);
-- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed
-- in different simulation deltas.
inclk1_tmp <= inclk1_ipd;
-- Calculate the inclk0 period
PROCESS
VARIABLE inclk0_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk0_ipd'EVENT AND inclk0_ipd = '1');
IF (first_inclk0_edge_detect = '0') THEN
first_inclk0_edge_detect <= '1';
ELSE
last_inclk0_period <= inclk0_period;
inclk0_period_tmp := NOW - last_inclk0_edge;
END IF;
last_inclk0_edge <= NOW;
inclk0_period <= inclk0_period_tmp;
END PROCESS;
-- Calculate the inclk1 period
PROCESS
VARIABLE inclk1_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk1_ipd'EVENT AND inclk1_ipd = '1');
IF (first_inclk1_edge_detect = '0') THEN
first_inclk1_edge_detect <= '1';
ELSE
last_inclk1_period <= inclk1_period;
inclk1_period_tmp := NOW - last_inclk1_edge;
END IF;
last_inclk1_edge <= NOW;
inclk1_period <= inclk1_period_tmp;
END PROCESS;
process (inclk0_ipd, inclk1_tmp, clkswitch_ipd)
variable input_value : std_logic := '0';
variable current_clock : integer := 0;
variable clk0_count, clk1_count : integer := 0;
variable clk0_is_bad, clk1_is_bad : std_logic := '0';
variable primary_clk_is_bad : boolean := false;
variable current_clk_is_bad : boolean := false;
variable got_curr_clk_falling_edge_after_clkswitch : boolean := false;
variable switch_over_count : integer := 0;
variable active_clock : std_logic := '0';
variable external_switch : boolean := false;
variable diff_percent_period : integer := 0;
variable buf : line;
variable switch_clock : boolean := false;
begin
if (now = 0 ps) then
if (switch_over_type = "manual" and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
end if;
end if;
if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then
external_switch := true;
elsif (switch_over_type = "manual") then
if (clkswitch_ipd'event and clkswitch_ipd = '1') then
switch_clock := true;
elsif (clkswitch_ipd'event and clkswitch_ipd = '0') then
switch_clock := false;
end if;
end if;
if (switch_clock = true) then
if (inclk0_ipd'event or inclk1_tmp'event) then
if (current_clock = 0) then
current_clock := 1;
active_clock := '1';
clkin <= transport inclk1_tmp;
elsif (current_clock = 1) then
current_clock := 0;
active_clock := '0';
clkin <= transport inclk0_ipd;
end if;
switch_clock := false;
end if;
end if;
-- save the current inclk event value
if (inclk0_ipd'event) then
input_value := inclk0_ipd;
elsif (inclk1_tmp'event) then
input_value := inclk1_tmp;
end if;
-- check if either input clk is bad
if (inclk0_ipd'event and inclk0_ipd = '1') then
clk0_count := clk0_count + 1;
clk0_is_bad := '0';
clk1_count := 0;
if (clk0_count > 2) then
-- no event on other clk for 2 cycles
clk1_is_bad := '1';
if (current_clock = 1) then
current_clk_is_bad := true;
end if;
end if;
end if;
if (inclk1_tmp'event and inclk1_tmp = '1') then
clk1_count := clk1_count + 1;
clk1_is_bad := '0';
clk0_count := 0;
if (clk1_count > 2) then
-- no event on other clk for 2 cycles
clk0_is_bad := '1';
if (current_clock = 0) then
current_clk_is_bad := true;
end if;
end if;
end if;
-- check if the bad clk is the primary clock
if (clk0_is_bad = '1') then
primary_clk_is_bad := true;
else
primary_clk_is_bad := false;
end if;
-- actual switching
if (inclk0_ipd'event and current_clock = 0) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk0_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk0_ipd;
end if;
else
clkin <= transport inclk0_ipd;
end if;
elsif (inclk1_tmp'event and current_clock = 1) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk1_tmp = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk1_tmp;
end if;
else
clkin <= transport inclk1_tmp;
end if;
else
if (input_value = '1' and enable_switch_over_counter = "on" and primary_clk_is_bad) then
switch_over_count := switch_over_count + 1;
end if;
if ((input_value = '0')) then
if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then
got_curr_clk_falling_edge_after_clkswitch := false;
if(inclk0_period > inclk1_period) then
diff_percent_period := (( inclk0_period - inclk1_period ) * 100) / inclk1_period;
else
diff_percent_period := (( inclk1_period - inclk0_period ) * 100) / inclk0_period;
end if;
if((diff_percent_period > 20)and ( switch_over_type = "auto")) then
WRITE(buf,string'("Warning : The input clock frequencies specified for the specified PLL are too far apart for auto-switch-over feature to work properly. Please make sure that the clock frequencies are 20 percent apart for correct functionality."));
writeline(output, buf);
end if;
if (current_clock = 0) then
current_clock := 1;
else
current_clock := 0;
end if;
active_clock := not active_clock;
switch_over_count := 0;
external_switch := false;
current_clk_is_bad := false;
else
if(switch_over_type = "auto") then
if(current_clock = 0 and clk0_is_bad = '1' and clk1_is_bad = '0' ) then
current_clock := 1;
active_clock := not active_clock;
end if;
if(current_clock = 1 and clk0_is_bad = '0' and clk1_is_bad = '1' ) then
current_clock := 0;
active_clock := not active_clock;
end if;
end if;
end if;
end if;
end if;
-- schedule outputs
clkbad(0) <= clk0_is_bad;
clkbad(1) <= clk1_is_bad;
activeclock <= active_clock;
end process;
n1 : stratixiii_mn_cntr
port map (
clk => clkin,
reset => areset_ipd,
cout => refclk,
initial_value => n_val,
modulus => n_val);
inclk_c0 <= refclk when c0_test_source = 1 else
fbclk when c0_test_source = 0 else
inclk_c_from_vco(0);
c0 : stratixiii_scale_cntr
port map (
clk => inclk_c0,
reset => areset_ena_sig,
cout => c_clk(0),
initial => c_initial_val(0),
high => c_high_val(0),
low => c_low_val(0),
mode => c_mode_val(0),
ph_tap => c_ph_val(0));
inclk_c1 <= refclk when c1_test_source = 1 else
fbclk when c1_test_source = 0 else
c_clk(0) when c1_use_casc_in = "on" else
inclk_c_from_vco(1);
c1 : stratixiii_scale_cntr
port map (
clk => inclk_c1,
reset => areset_ena_sig,
cout => c_clk(1),
initial => c_initial_val(1),
high => c_high_val(1),
low => c_low_val(1),
mode => c_mode_val(1),
ph_tap => c_ph_val(1));
inclk_c2 <= refclk when c2_test_source = 1 else
fbclk when c2_test_source = 0 else
c_clk(1) when c2_use_casc_in = "on" else
inclk_c_from_vco(2);
c2 : stratixiii_scale_cntr
port map (
clk => inclk_c2,
reset => areset_ena_sig,
cout => c_clk(2),
initial => c_initial_val(2),
high => c_high_val(2),
low => c_low_val(2),
mode => c_mode_val(2),
ph_tap => c_ph_val(2));
inclk_c3 <= refclk when c3_test_source = 1 else
fbclk when c3_test_source = 0 else
c_clk(2) when c3_use_casc_in = "on" else
inclk_c_from_vco(3);
c3 : stratixiii_scale_cntr
port map (
clk => inclk_c3,
reset => areset_ena_sig,
cout => c_clk(3),
initial => c_initial_val(3),
high => c_high_val(3),
low => c_low_val(3),
mode => c_mode_val(3),
ph_tap => c_ph_val(3));
inclk_c4 <= refclk when c4_test_source = 1 else
fbclk when c4_test_source = 0 else
c_clk(3) when (c4_use_casc_in = "on") else
inclk_c_from_vco(4);
c4 : stratixiii_scale_cntr
port map (
clk => inclk_c4,
reset => areset_ena_sig,
cout => c_clk(4),
initial => c_initial_val(4),
high => c_high_val(4),
low => c_low_val(4),
mode => c_mode_val(4),
ph_tap => c_ph_val(4));
inclk_c5 <= refclk when c5_test_source = 1 else
fbclk when c5_test_source = 0 else
c_clk(4) when c5_use_casc_in = "on" else
inclk_c_from_vco(5);
c5 : stratixiii_scale_cntr
port map (
clk => inclk_c5,
reset => areset_ena_sig,
cout => c_clk(5),
initial => c_initial_val(5),
high => c_high_val(5),
low => c_low_val(5),
mode => c_mode_val(5),
ph_tap => c_ph_val(5));
inclk_c6 <= refclk when c6_test_source = 1 else
fbclk when c6_test_source = 0 else
c_clk(5) when c6_use_casc_in = "on" else
inclk_c_from_vco(6);
c6 : stratixiii_scale_cntr
port map (
clk => inclk_c6,
reset => areset_ena_sig,
cout => c_clk(6),
initial => c_initial_val(6),
high => c_high_val(6),
low => c_low_val(6),
mode => c_mode_val(6),
ph_tap => c_ph_val(6));
inclk_c7 <= refclk when c7_test_source = 1 else
fbclk when c7_test_source = 0 else
c_clk(6) when c7_use_casc_in = "on" else
inclk_c_from_vco(7);
c7 : stratixiii_scale_cntr
port map (
clk => inclk_c7,
reset => areset_ena_sig,
cout => c_clk(7),
initial => c_initial_val(7),
high => c_high_val(7),
low => c_low_val(7),
mode => c_mode_val(7),
ph_tap => c_ph_val(7));
inclk_c8 <= refclk when c8_test_source = 1 else
fbclk when c8_test_source = 0 else
c_clk(7) when c8_use_casc_in = "on" else
inclk_c_from_vco(8);
c8 : stratixiii_scale_cntr
port map (
clk => inclk_c8,
reset => areset_ena_sig,
cout => c_clk(8),
initial => c_initial_val(8),
high => c_high_val(8),
low => c_low_val(8),
mode => c_mode_val(8),
ph_tap => c_ph_val(8));
inclk_c9 <= refclk when c9_test_source = 1 else
fbclk when c9_test_source = 0 else
c_clk(8) when c9_use_casc_in = "on" else
inclk_c_from_vco(9);
c9 : stratixiii_scale_cntr
port map (
clk => inclk_c9,
reset => areset_ena_sig,
cout => c_clk(9),
initial => c_initial_val(9),
high => c_high_val(9),
low => c_low_val(9),
mode => c_mode_val(9),
ph_tap => c_ph_val(9));
process(scandone_tmp, lock)
begin
if (scandone_tmp'event and (scandone_tmp = '1')) then
pll_has_just_been_reconfigured <= true;
elsif (lock'event and (lock = '1')) then
pll_has_just_been_reconfigured <= false;
end if;
end process;
process(inclk_c0, inclk_c1, areset_ipd, sig_stop_vco)
variable c0_got_first_rising_edge : boolean := false;
variable c0_count : integer := 2;
variable c0_initial_count : integer := 1;
variable c0_tmp, c1_tmp : std_logic := '0';
variable c1_got_first_rising_edge : boolean := false;
variable c1_count : integer := 2;
variable c1_initial_count : integer := 1;
begin
if (areset_ipd = '1' or sig_stop_vco = '1') then
c0_count := 2;
c1_count := 2;
c0_initial_count := 1;
c1_initial_count := 1;
c0_got_first_rising_edge := false;
c1_got_first_rising_edge := false;
else
if (not c0_got_first_rising_edge) then
if (inclk_c0'event and inclk_c0 = '1') then
if (c0_initial_count = c_initial_val(0)) then
c0_got_first_rising_edge := true;
else
c0_initial_count := c0_initial_count + 1;
end if;
end if;
elsif (inclk_c0'event) then
c0_count := c0_count + 1;
if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then
c0_count := 1;
end if;
end if;
if (inclk_c0'event and inclk_c0 = '0') then
if (c0_count = 1) then
c0_tmp := '1';
c0_got_first_rising_edge := false;
else
c0_tmp := '0';
end if;
end if;
if (not c1_got_first_rising_edge) then
if (inclk_c1'event and inclk_c1 = '1') then
if (c1_initial_count = c_initial_val(1)) then
c1_got_first_rising_edge := true;
else
c1_initial_count := c1_initial_count + 1;
end if;
end if;
elsif (inclk_c1'event) then
c1_count := c1_count + 1;
if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then
c1_count := 1;
end if;
end if;
if (inclk_c1'event and inclk_c1 = '0') then
if (c1_count = 1) then
c1_tmp := '1';
c1_got_first_rising_edge := false;
else
c1_tmp := '0';
end if;
end if;
end if;
end process;
locked <= pfd_locked WHEN (test_bypass_lock_detect = "on") ELSE
lock;
process (scandone_tmp)
variable buf : line;
begin
if (scandone_tmp'event and scandone_tmp = '1') then
if (reconfig_err = false) then
ASSERT false REPORT "PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note;
write (buf, string'(" N modulus = "));
write (buf, n_val);
write (buf, string'(" ( "));
write (buf, n_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M modulus = "));
write (buf, m_val);
write (buf, string'(" ( "));
write (buf, m_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M ph_tap = "));
write (buf, m_ph_val);
write (buf, string'(" ( "));
write (buf, m_ph_val_old);
write (buf, string'(" )"));
writeline (output, buf);
for i in 0 to (num_output_cntrs-1) loop
write (buf, clk_num(i));
write (buf, string'(" : "));
write (buf, cntrs(i));
write (buf, string'(" : high = "));
write (buf, c_high_val(i));
write (buf, string'(" ("));
write (buf, c_high_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , low = "));
write (buf, c_low_val(i));
write (buf, string'(" ("));
write (buf, c_low_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , mode = "));
write (buf, c_mode_val(i));
write (buf, string'(" ("));
write (buf, c_mode_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , phase tap = "));
write (buf, c_ph_val(i));
write (buf, string'(" ("));
write (buf, c_ph_val_old(i));
write (buf, string'(") "));
writeline(output, buf);
end loop;
IF (pll_reconfig_display_full_setting) THEN
write (buf, string'(" Charge Pump Current (uA) = "));
write (buf, cp_curr_val);
write (buf, string'(" ( "));
write (buf, cp_curr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (pF) = "));
write (buf, lfc_val);
write (buf, string'(" ( "));
write (buf, lfc_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (Kohm) = "));
write (buf, lfr_val);
write (buf, string'(" ( "));
write (buf, lfr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
ELSE
write (buf, string'(" Charge Pump Current (bit setting) = "));
write (buf, alt_conv_integer(cp_curr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, cp_curr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (bit setting) = "));
write (buf, alt_conv_integer(lfc_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfc_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (bit setting) = "));
write (buf, alt_conv_integer(lfr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
END IF;
cp_curr_old_bit_setting <= alt_conv_integer(cp_curr_val_bit_setting);
lfc_old_bit_setting <= alt_conv_integer(lfc_val_bit_setting);
lfr_old_bit_setting <= alt_conv_integer(lfr_val_bit_setting);
else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning;
end if;
end if;
end process;
update_conf_latches <= configupdate_ipd;
process (scandone_tmp,areset_ipd,update_conf_latches, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), c_clk(5), c_clk(6), c_clk(7), c_clk(8), c_clk(9), vco_out, fbclk, scanclk_ipd)
variable init : boolean := true;
variable low, high : std_logic_vector(7 downto 0);
variable low_fast, high_fast : std_logic_vector(3 downto 0);
variable mode : string(1 to 6) := "bypass";
variable is_error : boolean := false;
variable m_tmp, n_tmp : std_logic_vector(8 downto 0);
variable lfr_val_tmp : string(1 to 2) := " ";
variable c_high_val_tmp,c_hval : int_array(0 to 9) := (OTHERS => 1);
variable c_low_val_tmp,c_lval : int_array(0 to 9) := (OTHERS => 1);
variable c_mode_val_tmp : str_array(0 to 9);
variable m_val_tmp : integer := 0;
variable c0_rising_edge_transfer_done : boolean := false;
variable c1_rising_edge_transfer_done : boolean := false;
variable c2_rising_edge_transfer_done : boolean := false;
variable c3_rising_edge_transfer_done : boolean := false;
variable c4_rising_edge_transfer_done : boolean := false;
variable c5_rising_edge_transfer_done : boolean := false;
variable c6_rising_edge_transfer_done : boolean := false;
variable c7_rising_edge_transfer_done : boolean := false;
variable c8_rising_edge_transfer_done : boolean := false;
variable c9_rising_edge_transfer_done : boolean := false;
-- variables for scaling of multiply_by and divide_by values
variable i_clk0_mult_by : integer := 1;
variable i_clk0_div_by : integer := 1;
variable i_clk1_mult_by : integer := 1;
variable i_clk1_div_by : integer := 1;
variable i_clk2_mult_by : integer := 1;
variable i_clk2_div_by : integer := 1;
variable i_clk3_mult_by : integer := 1;
variable i_clk3_div_by : integer := 1;
variable i_clk4_mult_by : integer := 1;
variable i_clk4_div_by : integer := 1;
variable i_clk5_mult_by : integer := 1;
variable i_clk5_div_by : integer := 1;
variable i_clk6_mult_by : integer := 1;
variable i_clk6_div_by : integer := 1;
variable i_clk7_mult_by : integer := 1;
variable i_clk7_div_by : integer := 1;
variable i_clk8_mult_by : integer := 1;
variable i_clk8_div_by : integer := 1;
variable i_clk9_mult_by : integer := 1;
variable i_clk9_div_by : integer := 1;
variable max_d_value : integer := 1;
variable new_multiplier : integer := 1;
-- internal variables for storing the phase shift number.(used in lvds mode only)
variable i_clk0_phase_shift : integer := 1;
variable i_clk1_phase_shift : integer := 1;
variable i_clk2_phase_shift : integer := 1;
-- user to advanced variables
variable max_neg_abs : integer := 0;
variable i_m_initial : integer;
variable i_m : integer := 1;
variable i_n : integer := 1;
variable i_c_high : int_array(0 to 9);
variable i_c_low : int_array(0 to 9);
variable i_c_initial : int_array(0 to 9);
variable i_c_ph : int_array(0 to 9);
variable i_c_mode : str_array(0 to 9);
variable i_m_ph : integer;
variable output_count : integer;
variable new_divisor : integer;
variable clk0_cntr : string(1 to 6) := " c0";
variable clk1_cntr : string(1 to 6) := " c1";
variable clk2_cntr : string(1 to 6) := " c2";
variable clk3_cntr : string(1 to 6) := " c3";
variable clk4_cntr : string(1 to 6) := " c4";
variable clk5_cntr : string(1 to 6) := " c5";
variable clk6_cntr : string(1 to 6) := " c6";
variable clk7_cntr : string(1 to 6) := " c7";
variable clk8_cntr : string(1 to 6) := " c8";
variable clk9_cntr : string(1 to 6) := " c9";
variable fbk_cntr : string(1 to 2);
variable fbk_cntr_index : integer;
variable start_bit : integer;
variable quiet_time : time := 0 ps;
variable slowest_clk_old : time := 0 ps;
variable slowest_clk_new : time := 0 ps;
variable i : integer := 0;
variable j : integer := 0;
variable scanread_active_edge : time := 0 ps;
variable got_first_scanclk : boolean := false;
variable scanclk_last_rising_edge : time := 0 ps;
variable current_scan_data : std_logic_vector(0 to 233) := (OTHERS => '0');
variable index : integer := 0;
variable Tviol_scandata_scanclk : std_ulogic := '0';
variable TimingData_scandata_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_scanclkena_scanclk : std_ulogic := '0';
variable TimingData_scanclkena_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable scan_chain_length : integer := GPP_SCAN_CHAIN;
variable tmp_rem : integer := 0;
variable scanclk_cycles : integer := 0;
variable lfc_tmp : std_logic_vector(1 downto 0);
variable lfr_tmp : std_logic_vector(5 downto 0);
variable lfr_int : integer := 0;
variable n_hi,n_lo,m_hi,m_lo : std_logic_vector(7 downto 0);
variable buf : line;
variable buf_scan_data : STD_LOGIC_VECTOR(0 TO 1) := (OTHERS => '0');
variable buf_scan_data_2 : STD_LOGIC_VECTOR(0 TO 2) := (OTHERS => '0');
function slowest_clk (
C0 : integer; C0_mode : string(1 to 6);
C1 : integer; C1_mode : string(1 to 6);
C2 : integer; C2_mode : string(1 to 6);
C3 : integer; C3_mode : string(1 to 6);
C4 : integer; C4_mode : string(1 to 6);
C5 : integer; C5_mode : string(1 to 6);
C6 : integer; C6_mode : string(1 to 6);
C7 : integer; C7_mode : string(1 to 6);
C8 : integer; C8_mode : string(1 to 6);
C9 : integer; C9_mode : string(1 to 6);
refclk : time; m_mod : integer) return time is
variable max_modulus : integer := 1;
variable q_period : time := 0 ps;
variable refclk_int : integer := 0;
begin
if (C0_mode /= "bypass" and C0_mode /= " off") then
max_modulus := C0;
end if;
if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then
max_modulus := C1;
end if;
if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then
max_modulus := C2;
end if;
if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then
max_modulus := C3;
end if;
if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then
max_modulus := C4;
end if;
if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then
max_modulus := C5;
end if;
if (C6 > max_modulus and C6_mode /= "bypass" and C6_mode /= " off") then
max_modulus := C6;
end if;
if (C7 > max_modulus and C7_mode /= "bypass" and C7_mode /= " off") then
max_modulus := C7;
end if;
if (C8 > max_modulus and C8_mode /= "bypass" and C8_mode /= " off") then
max_modulus := C8;
end if;
if (C9 > max_modulus and C9_mode /= "bypass" and C9_mode /= " off") then
max_modulus := C9;
end if;
refclk_int := refclk / 1 ps;
if (m_mod /= 0) then
q_period := (refclk_int * max_modulus / m_mod) * 1 ps;
end if;
return (2*q_period);
end slowest_clk;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function extract_cntr_string (arg:string) return string is
variable str : string(1 to 6) := " c0";
begin
if (arg = "c0") then
str := " c0";
elsif (arg = "c1") then
str := " c1";
elsif (arg = "c2") then
str := " c2";
elsif (arg = "c3") then
str := " c3";
elsif (arg = "c4") then
str := " c4";
elsif (arg = "c5") then
str := " c5";
elsif (arg = "c6") then
str := " c6";
elsif (arg = "c7") then
str := " c7";
elsif (arg = "c8") then
str := " c8";
elsif (arg = "c9") then
str := " c9";
else str := " c0";
end if;
return str;
end extract_cntr_string;
function extract_cntr_index (arg:string) return integer is
variable index : integer := 0;
begin
if (arg(6) = '0') then
index := 0;
elsif (arg(6) = '1') then
index := 1;
elsif (arg(6) = '2') then
index := 2;
elsif (arg(6) = '3') then
index := 3;
elsif (arg(6) = '4') then
index := 4;
elsif (arg(6) = '5') then
index := 5;
elsif (arg(6) = '6') then
index := 6;
elsif (arg(6) = '7') then
index := 7;
elsif (arg(6) = '8') then
index := 8;
else index := 9;
end if;
return index;
end extract_cntr_index;
function output_cntr_num (arg:string) return string is
variable str : string(1 to 6) := "unused";
begin
if (arg = "c0") then
str := " clk0";
elsif (arg = "c1") then
str := " clk1";
elsif (arg = "c2") then
str := " clk2";
elsif (arg = "c3") then
str := " clk3";
elsif (arg = "c4") then
str := " clk4";
elsif (arg = "c5") then
str := " clk5";
elsif (arg = "c6") then
str := " clk6";
elsif (arg = "c7") then
str := " clk7";
elsif (arg = "c8") then
str := " clk8";
elsif (arg = "c9") then
str := " clk9";
else str := "unused";
end if;
return str;
end output_cntr_num;
begin
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val <= i_c_ph;
END IF;
if (init) then
if (m = 0) then
clk9_cntr := " c9";
clk8_cntr := " c8";
clk7_cntr := " c7";
clk6_cntr := " c6";
clk5_cntr := " c5";
clk4_cntr := " c4";
clk3_cntr := " c3";
clk2_cntr := " c2";
clk1_cntr := " c1";
clk0_cntr := " c0";
else
clk9_cntr := extract_cntr_string(clk9_counter);
clk8_cntr := extract_cntr_string(clk8_counter);
clk7_cntr := extract_cntr_string(clk7_counter);
clk6_cntr := extract_cntr_string(clk6_counter);
clk5_cntr := extract_cntr_string(clk5_counter);
clk4_cntr := extract_cntr_string(clk4_counter);
clk3_cntr := extract_cntr_string(clk3_counter);
clk2_cntr := extract_cntr_string(clk2_counter);
clk1_cntr := extract_cntr_string(clk1_counter);
clk0_cntr := extract_cntr_string(clk0_counter);
end if;
clk_num(9) <= output_cntr_num(clk9_counter);
clk_num(8) <= output_cntr_num(clk8_counter);
clk_num(7) <= output_cntr_num(clk7_counter);
clk_num(6) <= output_cntr_num(clk6_counter);
clk_num(5) <= output_cntr_num(clk5_counter);
clk_num(4) <= output_cntr_num(clk4_counter);
clk_num(3) <= output_cntr_num(clk3_counter);
clk_num(2) <= output_cntr_num(clk2_counter);
clk_num(1) <= output_cntr_num(clk1_counter);
clk_num(0) <= output_cntr_num(clk0_counter);
i_clk0_counter <= extract_cntr_index(clk0_cntr);
i_clk1_counter <= extract_cntr_index(clk1_cntr);
i_clk2_counter <= extract_cntr_index(clk2_cntr);
i_clk3_counter <= extract_cntr_index(clk3_cntr);
i_clk4_counter <= extract_cntr_index(clk4_cntr);
i_clk5_counter <= extract_cntr_index(clk5_cntr);
i_clk6_counter <= extract_cntr_index(clk6_cntr);
i_clk7_counter <= extract_cntr_index(clk7_cntr);
i_clk8_counter <= extract_cntr_index(clk8_cntr);
i_clk9_counter <= extract_cntr_index(clk9_cntr);
if (m = 0) then -- convert user parameters to advanced
-- set the limit of the divide_by value that can be returned by
-- the following function.
max_d_value := 500;
-- scale down the multiply_by and divide_by values provided by the design
-- before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
find_simple_integer_fraction(clk5_multiply_by, clk5_divide_by,
max_d_value, i_clk5_mult_by, i_clk5_div_by);
find_simple_integer_fraction(clk6_multiply_by, clk6_divide_by,
max_d_value, i_clk6_mult_by, i_clk6_div_by);
find_simple_integer_fraction(clk7_multiply_by, clk7_divide_by,
max_d_value, i_clk7_mult_by, i_clk7_div_by);
find_simple_integer_fraction(clk8_multiply_by, clk8_divide_by,
max_d_value, i_clk8_mult_by, i_clk8_div_by);
find_simple_integer_fraction(clk9_multiply_by, clk9_divide_by,
max_d_value, i_clk9_mult_by, i_clk9_div_by);
if (vco_frequency_control = "manual_phase") then
find_m_and_n_4_manual_phase(inclk0_input_frequency, vco_phase_shift_step,
i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
i_clk5_mult_by,i_clk6_mult_by,
i_clk7_mult_by,i_clk8_mult_by,i_clk9_mult_by,
i_clk0_div_by, i_clk1_div_by,
i_clk2_div_by, i_clk3_div_by,
i_clk4_div_by,
i_clk5_div_by,i_clk6_div_by,
i_clk7_div_by,i_clk8_div_by,i_clk9_div_by,
clk0_counter, clk1_counter,
clk2_counter, clk3_counter,
clk4_counter,
clk5_counter,clk6_counter,
clk7_counter,clk8_counter,clk9_counter,
i_m, i_n);
elsif (((pll_type = "fast") or (pll_type = "lvds") OR (pll_type = "left_right")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then
i_n := vco_divide_by;
i_m := vco_multiply_by;
else
i_n := 1;
if (((pll_type = "fast") or (pll_type = "left_right")) and (compensate_clock = "lvdsclk")) then
i_m := i_clk0_mult_by;
else
i_m := lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
i_clk5_mult_by,i_clk6_mult_by,
i_clk7_mult_by,i_clk8_mult_by,i_clk9_mult_by,
inclk0_input_frequency);
end if;
end if;
if (pll_type = "flvds") then
-- Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier := clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier;
i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier;
i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier;
else
i_clk0_phase_shift := str2int(clk0_phase_shift);
i_clk1_phase_shift := str2int(clk1_phase_shift);
i_clk2_phase_shift := str2int(clk2_phase_shift);
end if;
max_neg_abs := maxnegabs(i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
str2int(clk5_phase_shift),
str2int(clk6_phase_shift),
str2int(clk7_phase_shift),
str2int(clk8_phase_shift),
str2int(clk9_phase_shift)
);
i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n);
i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(5) := counter_ph(get_phase_degree(ph_adjust(str2int(clk5_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(6) := counter_ph(get_phase_degree(ph_adjust(str2int(clk6_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(7) := counter_ph(get_phase_degree(ph_adjust(str2int(clk7_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(8) := counter_ph(get_phase_degree(ph_adjust(str2int(clk8_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(9) := counter_ph(get_phase_degree(ph_adjust(str2int(clk9_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_high(5) := counter_high(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_c_high(6) := counter_high(output_counter_value(i_clk6_div_by,
i_clk6_mult_by, i_m, i_n), clk6_duty_cycle);
i_c_high(7) := counter_high(output_counter_value(i_clk7_div_by,
i_clk7_mult_by, i_m, i_n), clk7_duty_cycle);
i_c_high(8) := counter_high(output_counter_value(i_clk8_div_by,
i_clk8_mult_by, i_m, i_n), clk8_duty_cycle);
i_c_high(9) := counter_high(output_counter_value(i_clk9_div_by,
i_clk9_mult_by, i_m, i_n), clk9_duty_cycle);
i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low(5) := counter_low(output_counter_value(i_clk5_div_by,
i_clk5_mult_by, i_m, i_n), clk5_duty_cycle);
i_c_low(6) := counter_low(output_counter_value(i_clk6_div_by,
i_clk6_mult_by, i_m, i_n), clk6_duty_cycle);
i_c_low(7) := counter_low(output_counter_value(i_clk7_div_by,
i_clk7_mult_by, i_m, i_n), clk7_duty_cycle);
i_c_low(8) := counter_low(output_counter_value(i_clk8_div_by,
i_clk8_mult_by, i_m, i_n), clk8_duty_cycle);
i_c_low(9) := counter_low(output_counter_value(i_clk9_div_by,
i_clk9_mult_by, i_m, i_n), clk9_duty_cycle);
i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n);
i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(5) := counter_initial(get_phase_degree(ph_adjust(str2int(clk5_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(6) := counter_initial(get_phase_degree(ph_adjust(str2int(clk6_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(7) := counter_initial(get_phase_degree(ph_adjust(str2int(clk7_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(8) := counter_initial(get_phase_degree(ph_adjust(str2int(clk8_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(9) := counter_initial(get_phase_degree(ph_adjust(str2int(clk9_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
i_c_mode(5) := counter_mode(clk5_duty_cycle, output_counter_value(i_clk5_div_by, i_clk5_mult_by, i_m, i_n));
i_c_mode(6) := counter_mode(clk6_duty_cycle, output_counter_value(i_clk6_div_by, i_clk6_mult_by, i_m, i_n));
i_c_mode(7) := counter_mode(clk7_duty_cycle, output_counter_value(i_clk7_div_by, i_clk7_mult_by, i_m, i_n));
i_c_mode(8) := counter_mode(clk8_duty_cycle, output_counter_value(i_clk8_div_by, i_clk8_mult_by, i_m, i_n));
i_c_mode(9) := counter_mode(clk9_duty_cycle, output_counter_value(i_clk9_div_by, i_clk9_mult_by, i_m, i_n));
else -- m /= 0
i_n := n;
i_m := m;
i_m_initial := m_initial;
i_m_ph := m_ph;
i_c_ph(0) := c0_ph;
i_c_ph(1) := c1_ph;
i_c_ph(2) := c2_ph;
i_c_ph(3) := c3_ph;
i_c_ph(4) := c4_ph;
i_c_ph(5) := c5_ph;
i_c_ph(6) := c6_ph;
i_c_ph(7) := c7_ph;
i_c_ph(8) := c8_ph;
i_c_ph(9) := c9_ph;
i_c_high(0) := c0_high;
i_c_high(1) := c1_high;
i_c_high(2) := c2_high;
i_c_high(3) := c3_high;
i_c_high(4) := c4_high;
i_c_high(5) := c5_high;
i_c_high(6) := c6_high;
i_c_high(7) := c7_high;
i_c_high(8) := c8_high;
i_c_high(9) := c9_high;
i_c_low(0) := c0_low;
i_c_low(1) := c1_low;
i_c_low(2) := c2_low;
i_c_low(3) := c3_low;
i_c_low(4) := c4_low;
i_c_low(5) := c5_low;
i_c_low(6) := c6_low;
i_c_low(7) := c7_low;
i_c_low(8) := c8_low;
i_c_low(9) := c9_low;
i_c_initial(0) := c0_initial;
i_c_initial(1) := c1_initial;
i_c_initial(2) := c2_initial;
i_c_initial(3) := c3_initial;
i_c_initial(4) := c4_initial;
i_c_initial(5) := c5_initial;
i_c_initial(6) := c6_initial;
i_c_initial(7) := c7_initial;
i_c_initial(8) := c8_initial;
i_c_initial(9) := c9_initial;
i_c_mode(0) := translate_string(c0_mode);
i_c_mode(1) := translate_string(c1_mode);
i_c_mode(2) := translate_string(c2_mode);
i_c_mode(3) := translate_string(c3_mode);
i_c_mode(4) := translate_string(c4_mode);
i_c_mode(5) := translate_string(c5_mode);
i_c_mode(6) := translate_string(c6_mode);
i_c_mode(7) := translate_string(c7_mode);
i_c_mode(8) := translate_string(c8_mode);
i_c_mode(9) := translate_string(c9_mode);
end if; -- user to advanced conversion.
m_initial_val <= i_m_initial;
n_val <= i_n;
m_val <= i_m;
if (i_m = 1) then
m_mode_val <= "bypass";
else
m_mode_val <= " ";
end if;
if (i_n = 1) then
n_mode_val <= "bypass";
else
n_mode_val <= " ";
end if;
m_ph_val <= i_m_ph;
m_ph_initial <= i_m_ph;
m_val_tmp := i_m;
for i in 0 to 9 loop
if (i_c_mode(i) = "bypass") then
if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then
i_c_high(i) := 16;
i_c_low(i) := 16;
else
i_c_high(i) := 256;
i_c_low(i) := 256;
end if;
end if;
c_ph_val(i) <= i_c_ph(i);
c_initial_val(i) <= i_c_initial(i);
c_high_val(i) <= i_c_high(i);
c_low_val(i) <= i_c_low(i);
c_mode_val(i) <= i_c_mode(i);
c_high_val_tmp(i) := i_c_high(i);
c_hval(i) := i_c_high(i);
c_low_val_tmp(i) := i_c_low(i);
c_lval(i) := i_c_low(i);
c_mode_val_tmp(i) := i_c_mode(i);
c_ph_val_orig(i) <= i_c_ph(i);
c_high_val_hold(i) <= i_c_high(i);
c_low_val_hold(i) <= i_c_low(i);
c_mode_val_hold(i) <= i_c_mode(i);
end loop;
if (pll_type = "fast" OR (pll_type = "left_right")) then
scan_chain_length := FAST_SCAN_CHAIN;
else
scan_chain_length := GPP_SCAN_CHAIN;
end if;
if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then
num_output_cntrs <= 7;
else
num_output_cntrs <= 10;
end if;
init := false;
elsif (scandone_tmp'EVENT AND scandone_tmp = '1') then
c0_rising_edge_transfer_done := false;
c1_rising_edge_transfer_done := false;
c2_rising_edge_transfer_done := false;
c3_rising_edge_transfer_done := false;
c4_rising_edge_transfer_done := false;
c5_rising_edge_transfer_done := false;
c6_rising_edge_transfer_done := false;
c7_rising_edge_transfer_done := false;
c8_rising_edge_transfer_done := false;
c9_rising_edge_transfer_done := false;
update_conf_latches_reg <= '0';
elsif (update_conf_latches'event and update_conf_latches = '1') then
initiate_reconfig <= '1';
elsif (areset_ipd'event AND areset_ipd = '1') then
if (scandone_tmp = '0') then scandone_tmp <= '1' AFTER scanclk_period; end if;
elsif (scanclk_ipd'event and scanclk_ipd = '1') then
IF (initiate_reconfig = '1') THEN
initiate_reconfig <= '0';
ASSERT false REPORT "PLL Reprogramming Initiated" severity note;
update_conf_latches_reg <= update_conf_latches;
reconfig_err <= false;
scandone_tmp <= '0';
cp_curr_old <= cp_curr_val;
lfc_old <= lfc_val;
lfr_old <= lfr_val;
vco_old <= vco_cur;
-- LF unused : bit 0,1
-- LF Capacitance : bits 2,3 : all values are legal
buf_scan_data := scan_data(2 TO 3);
IF ((pll_type = "fast") OR (pll_type = "lvds") OR (pll_type = "left_right")) THEN
lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(buf_scan_data));
ELSE
lfc_val <= loop_filter_c_arr(alt_conv_integer(buf_scan_data));
END IF;
-- LF Resistance : bits 4-8
-- valid values - 00000,00100,10000,10100,11000,11011,11100,11110
IF (scan_data(4 TO 8) = "00000") THEN
lfr_val <= "20";
ELSIF (scan_data(4 TO 8) = "00100") THEN
lfr_val <= "16";
ELSIF (scan_data(4 TO 8) = "10000") THEN
lfr_val <= "12";
ELSIF (scan_data(4 TO 8) = "10100") THEN
lfr_val <= "08";
ELSIF (scan_data(4 TO 8) = "11000") THEN
lfr_val <= "06";
ELSIF (scan_data(4 TO 8) = "11011") THEN
lfr_val <= "04";
ELSIF (scan_data(4 TO 8) = "11100") THEN
lfr_val <= "02";
ELSE
lfr_val <= "01";
END IF;
-- VCO post scale assignment
if (scan_data(9) = '1') then -- vco_post_scale = 1
i_vco_max <= vco_max/2;
i_vco_min <= vco_min/2;
vco_cur <= 1;
else
i_vco_max <= vco_max;
i_vco_min <= vco_min;
vco_cur <= 2;
end if;
-- CP
-- Bit 9 : CRBYPASS
-- Bit 10-14 : unused
-- Bits 15-17 : all values are legal
buf_scan_data_2 := scan_data(15 TO 17);
cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(buf_scan_data_2));
-- save old values for display info.
cp_curr_val_bit_setting <= scan_data(15 TO 17);
lfc_val_bit_setting <= scan_data(2 TO 3);
lfr_val_bit_setting <= scan_data(4 TO 8);
m_val_old <= m_val;
n_val_old <= n_val;
m_mode_val_old <= m_mode_val;
n_mode_val_old <= n_mode_val;
WHILE (i < num_output_cntrs) LOOP
c_high_val_old(i) <= c_high_val(i);
c_low_val_old(i) <= c_low_val(i);
c_mode_val_old(i) <= c_mode_val(i);
i := i + 1;
END LOOP;
-- M counter
-- 1. Mode - bypass (bit 18)
IF (scan_data(18) = '1') THEN
m_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 27)
ELSIF (scan_data(27) = '1') THEN
m_mode_val <= " odd";
ELSE
m_mode_val <= " even";
END IF;
-- 2. High (bit 19-26)
m_hi := scan_data(19 TO 26);
-- 4. Low (bit 28-35)
m_lo := scan_data(28 TO 35);
-- N counter
-- 1. Mode - bypass (bit 36)
IF (scan_data(36) = '1') THEN
n_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 45)
ELSIF (scan_data(45) = '1') THEN
n_mode_val <= " odd";
ELSE
n_mode_val <= " even";
END IF;
-- 2. High (bit 37-44)
n_hi := scan_data(37 TO 44);
-- 4. Low (bit 46-53)
n_lo := scan_data(46 TO 53);
-- C counters (start bit 54) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low
i := 0;
WHILE (i < num_output_cntrs) LOOP
-- 1. Mode - bypass
IF (scan_data(54 + i * 18 + 0) = '1') THEN
c_mode_val_tmp(i) := "bypass";
-- 3. Mode - odd/even
ELSIF (scan_data(54 + i * 18 + 9) = '1') THEN
c_mode_val_tmp(i) := " odd";
ELSE
c_mode_val_tmp(i) := " even";
END IF;
-- 2. Hi
high := scan_data(54 + i * 18 + 1 TO 54 + i * 18 + 8);
c_hval(i) := alt_conv_integer(high);
IF (c_hval(i) /= 0) THEN
c_high_val_tmp(i) := c_hval(i);
ELSE
c_high_val_tmp(i) := alt_conv_integer("000000001");
END IF;
-- 4. Low
low := scan_data(54 + i * 18 + 10 TO 54 + i * 18 + 17);
c_lval(i) := alt_conv_integer(low);
IF (c_lval(i) /= 0) THEN
c_low_val_tmp(i) := c_lval(i);
ELSE
c_low_val_tmp(i) := alt_conv_integer("000000001");
END IF;
i := i + 1;
END LOOP;
-- Legality Checks
-- M counter value
IF(scan_data(18) /= '1') THEN
IF ((m_hi /= m_lo) and (scan_data(27) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The M counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (m_hi /= "00000000") THEN
m_val_tmp := alt_conv_integer(m_hi) + alt_conv_integer(m_lo);
ELSE
m_val_tmp := alt_conv_integer("000000001");
END IF;
ELSE
m_val_tmp := alt_conv_integer("10000000");
END IF;
-- N counter value
IF(scan_data(36) /= '1') THEN
IF ((n_hi /= n_lo)and (scan_data(45) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The N counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (n_hi /= "00000000") THEN
n_val <= alt_conv_integer(n_hi) + alt_conv_integer(n_lo);
ELSE
n_val <= alt_conv_integer("000000001");
END IF;
ELSE
n_val <= alt_conv_integer("10000000");
END IF;
-- TODO : Give warnings/errors in the following cases?
-- 1. Illegal counter values (error)
-- 2. Change of mode (warning)
-- 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0)
END IF;
end if;
if (fbclk'event and fbclk = '1') then
m_val <= m_val_tmp;
end if;
if (update_conf_latches_reg = '1') then
if (scanclk_ipd'event and scanclk_ipd = '1') then
c0_rising_edge_transfer_done := true;
c_high_val(0) <= c_high_val_tmp(0);
c_mode_val(0) <= c_mode_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c1_rising_edge_transfer_done := true;
c_high_val(1) <= c_high_val_tmp(1);
c_mode_val(1) <= c_mode_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c2_rising_edge_transfer_done := true;
c_high_val(2) <= c_high_val_tmp(2);
c_mode_val(2) <= c_mode_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(3) <= c_high_val_tmp(3);
c_mode_val(3) <= c_mode_val_tmp(3);
c3_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(4) <= c_high_val_tmp(4);
c_mode_val(4) <= c_mode_val_tmp(4);
c4_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(5) <= c_high_val_tmp(5);
c_mode_val(5) <= c_mode_val_tmp(5);
c5_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(6) <= c_high_val_tmp(6);
c_mode_val(6) <= c_mode_val_tmp(6);
c6_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(7) <= c_high_val_tmp(7);
c_mode_val(7) <= c_mode_val_tmp(7);
c7_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(8) <= c_high_val_tmp(8);
c_mode_val(8) <= c_mode_val_tmp(8);
c8_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(9) <= c_high_val_tmp(9);
c_mode_val(9) <= c_mode_val_tmp(9);
c9_rising_edge_transfer_done := true;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c0_rising_edge_transfer_done) then
c_low_val(0) <= c_low_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c1_rising_edge_transfer_done) then
c_low_val(1) <= c_low_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c2_rising_edge_transfer_done) then
c_low_val(2) <= c_low_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c3_rising_edge_transfer_done) then
c_low_val(3) <= c_low_val_tmp(3);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c4_rising_edge_transfer_done) then
c_low_val(4) <= c_low_val_tmp(4);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c5_rising_edge_transfer_done) then
c_low_val(5) <= c_low_val_tmp(5);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c6_rising_edge_transfer_done) then
c_low_val(6) <= c_low_val_tmp(6);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c7_rising_edge_transfer_done) then
c_low_val(7) <= c_low_val_tmp(7);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c8_rising_edge_transfer_done) then
c_low_val(8) <= c_low_val_tmp(8);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c9_rising_edge_transfer_done) then
c_low_val(9) <= c_low_val_tmp(9);
end if;
if (update_phase = '1') then
if (vco_out(0)'event and vco_out(0) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 0) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 0) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(1)'event and vco_out(1) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 1) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 1) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(2)'event and vco_out(2) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 2) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 2) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(3)'event and vco_out(3) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 3) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 3) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(4)'event and vco_out(4) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 4) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 4) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(5)'event and vco_out(5) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 5) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 5) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(6)'event and vco_out(6) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 6) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 6) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(7)'event and vco_out(7) = '0') then
for i in 0 to 9 loop
if (c_ph_val(i) = 7) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 7) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
end if;
if (vco_out(0)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 0) then
inclk_c_from_vco(i) <= vco_out(0);
end if;
end loop;
if (m_ph_val = 0) then
inclk_m_from_vco <= vco_out(0);
end if;
end if;
if (vco_out(1)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 1) then
inclk_c_from_vco(i) <= vco_out(1);
end if;
end loop;
if (m_ph_val = 1) then
inclk_m_from_vco <= vco_out(1);
end if;
end if;
if (vco_out(2)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 2) then
inclk_c_from_vco(i) <= vco_out(2);
end if;
end loop;
if (m_ph_val = 2) then
inclk_m_from_vco <= vco_out(2);
end if;
end if;
if (vco_out(3)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 3) then
inclk_c_from_vco(i) <= vco_out(3);
end if;
end loop;
if (m_ph_val = 3) then
inclk_m_from_vco <= vco_out(3);
end if;
end if;
if (vco_out(4)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 4) then
inclk_c_from_vco(i) <= vco_out(4);
end if;
end loop;
if (m_ph_val = 4) then
inclk_m_from_vco <= vco_out(4);
end if;
end if;
if (vco_out(5)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 5) then
inclk_c_from_vco(i) <= vco_out(5);
end if;
end loop;
if (m_ph_val = 5) then
inclk_m_from_vco <= vco_out(5);
end if;
end if;
if (vco_out(6)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 6) then
inclk_c_from_vco(i) <= vco_out(6);
end if;
end loop;
if (m_ph_val = 6) then
inclk_m_from_vco <= vco_out(6);
end if;
end if;
if (vco_out(7)'event) then
for i in 0 to 9 loop
if (c_ph_val(i) = 7) then
inclk_c_from_vco(i) <= vco_out(7);
end if;
end loop;
if (m_ph_val = 7) then
inclk_m_from_vco <= vco_out(7);
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_scandata_scanclk,
TimingData => TimingData_scandata_scanclk,
TestSignal => scandata_ipd,
TestSignalName => "scandata",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scandata_scanclk_noedge_negedge,
SetupLow => tsetup_scandata_scanclk_noedge_negedge,
HoldHigh => thold_scandata_scanclk_noedge_negedge,
HoldLow => thold_scandata_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/stratixiii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_scanclkena_scanclk,
TimingData => TimingData_scanclkena_scanclk,
TestSignal => scanclkena_ipd,
TestSignalName => "scanclkena",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scanclkena_scanclk_noedge_negedge,
SetupLow => tsetup_scanclkena_scanclk_noedge_negedge,
HoldHigh => thold_scanclkena_scanclk_noedge_negedge,
HoldLow => thold_scanclkena_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/stratixiii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (scanclk_ipd'event AND scanclk_ipd = '0' AND now > 0 ps) then
scanclkena_reg <= scanclkena_ipd;
if (scanclkena_reg = '1') then
scandata_in <= scandata_ipd;
scandata_out <= scandataout_tmp;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1' and now > 0 ps) then
if (got_first_scanclk) then
scanclk_period <= now - scanclk_last_rising_edge;
else
got_first_scanclk := true;
end if;
if (scanclkena_reg = '1') then
for j in scan_chain_length - 1 downto 1 loop
scan_data(j) <= scan_data(j-1);
end loop;
scan_data(0) <= scandata_in;
end if;
scanclk_last_rising_edge := now;
end if;
end process;
-- PLL Phase Reconfiguration
PROCESS(scanclk_ipd, areset_ipd,phasestep_ipd)
VARIABLE i : INTEGER := 0;
VARIABLE c_ph : INTEGER := 0;
VARIABLE m_ph : INTEGER := 0;
VARIABLE select_counter : INTEGER := 0;
BEGIN
IF (NOW = 0 ps) THEN
m_ph_val_tmp <= m_ph_initial;
END IF;
-- Latch phase enable (same as phasestep) on neg edge of scan clock
IF (scanclk_ipd'EVENT AND scanclk_ipd = '0') THEN
phasestep_reg <= phasestep_ipd;
END IF;
IF (phasestep_ipd'EVENT and phasestep_ipd = '1') THEN
IF (update_phase = '0') THEN
phasestep_high_count <= 0; -- phase adjustments must be 1 cycle apart
-- if not, next phasestep cycle is skipped
END IF;
END IF;
-- revert counter phase tap values to POF programmed values
-- if PLL is reset
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val_tmp <= c_ph_val_orig;
m_ph_val_tmp <= m_ph_initial;
END IF;
IF (scanclk_ipd'EVENT AND scanclk_ipd = '1') THEN
IF (phasestep_reg = '1') THEN
IF (phasestep_high_count = 1) THEN
phasecounterselect_reg <= phasecounterselect_ipd;
phaseupdown_reg <= phaseupdown_ipd;
-- start reconfiguration
IF (phasecounterselect_ipd < "1100") THEN -- no counters selected
IF (phasecounterselect_ipd = "0000") THEN
i := 0;
WHILE (i < num_output_cntrs) LOOP
c_ph := c_ph_val(i);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(i) <= c_ph;
i := i + 1;
END LOOP;
ELSIF (phasecounterselect_ipd = "0001") THEN
m_ph := m_ph_val;
IF (phaseupdown_ipd = '1') THEN
m_ph := (m_ph + 1) mod num_phase_taps;
ELSIF (m_ph = 0) THEN
m_ph := num_phase_taps - 1;
ELSE
m_ph := (m_ph - 1) mod num_phase_taps;
END IF;
m_ph_val_tmp <= m_ph;
ELSE
select_counter := alt_conv_integer(phasecounterselect_ipd) - 2;
c_ph := c_ph_val(select_counter);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(select_counter) <= c_ph;
END IF;
update_phase <= '1','0' AFTER (0.5 * scanclk_period);
END IF;
END IF;
phasestep_high_count <= phasestep_high_count + 1;
END IF;
END IF;
END PROCESS;
scandataout_tmp <= scan_data(FAST_SCAN_CHAIN-2) when (pll_type = "fast" or pll_type = "lvds" or pll_type = "left_right") else scan_data(GPP_SCAN_CHAIN-2);
process (schedule_vco, areset_ipd, pfdena_ipd, refclk, fbclk)
variable sched_time : time := 0 ps;
TYPE time_array is ARRAY (0 to 7) of time;
variable init : boolean := true;
variable refclk_period : time;
variable m_times_vco_period : time;
variable new_m_times_vco_period : time;
variable phase_shift : time_array := (OTHERS => 0 ps);
variable last_phase_shift : time_array := (OTHERS => 0 ps);
variable l_index : integer := 1;
variable cycle_to_adjust : integer := 0;
variable stop_vco : boolean := false;
variable locked_tmp : std_logic := '0';
variable pll_is_locked : boolean := false;
variable cycles_pfd_low : integer := 0;
variable cycles_pfd_high : integer := 0;
variable cycles_to_lock : integer := 0;
variable cycles_to_unlock : integer := 0;
variable got_first_refclk : boolean := false;
variable got_second_refclk : boolean := false;
variable got_first_fbclk : boolean := false;
variable refclk_time : time := 0 ps;
variable fbclk_time : time := 0 ps;
variable first_fbclk_time : time := 0 ps;
variable fbclk_period : time := 0 ps;
variable first_schedule : boolean := true;
variable vco_val : std_logic := '0';
variable vco_period_was_phase_adjusted : boolean := false;
variable phase_adjust_was_scheduled : boolean := false;
variable loop_xplier : integer;
variable loop_initial : integer := 0;
variable loop_ph : integer := 0;
variable loop_time_delay : integer := 0;
variable initial_delay : time := 0 ps;
variable vco_per : time;
variable tmp_rem : integer;
variable my_rem : integer;
variable fbk_phase : integer := 0;
variable pull_back_M : integer := 0;
variable total_pull_back : integer := 0;
variable fbk_delay : integer := 0;
variable offset : time := 0 ps;
variable tmp_vco_per : integer := 0;
variable high_time : time;
variable low_time : time;
variable got_refclk_posedge : boolean := false;
variable got_fbclk_posedge : boolean := false;
variable inclk_out_of_range : boolean := false;
variable no_warn : boolean := false;
variable ext_fbk_cntr_modulus : integer := 1;
variable init_clks : boolean := true;
variable pll_is_in_reset : boolean := false;
variable buf : line;
begin
if (init) then
-- jump-start the VCO
-- add 1 ps delay to ensure all signals are updated to initial
-- values
schedule_vco <= transport not schedule_vco after 1 ps;
init := false;
end if;
if (schedule_vco'event) then
if (init_clks) then
refclk_period := inclk0_input_frequency * n_val * 1 ps;
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
init_clks := false;
end if;
sched_time := 0 ps;
for i in 0 to 7 loop
last_phase_shift(i) := phase_shift(i);
end loop;
cycle_to_adjust := 0;
l_index := 1;
m_times_vco_period := new_m_times_vco_period;
end if;
-- areset was asserted
if (areset_ipd'event and areset_ipd = '1') then
assert false report family_name & " PLL was reset" severity note;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
end if;
if (schedule_vco'event and (areset_ipd = '1' or stop_vco)) then
if (areset_ipd = '1') then
pll_is_in_reset := true;
got_first_refclk := false;
got_second_refclk := false;
end if;
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after last_phase_shift(i);
phase_shift(i) := 0 ps;
last_phase_shift(i) := 0 ps;
end loop;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
got_first_refclk := false;
got_second_refclk := false;
refclk_time := 0 ps;
got_first_fbclk := false;
fbclk_time := 0 ps;
first_fbclk_time := 0 ps;
fbclk_period := 0 ps;
first_schedule := true;
vco_val := '0';
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
elsif ((schedule_vco'event or areset_ipd'event) and areset_ipd = '0' and (not stop_vco) and now > 0 ps) then
-- note areset deassert time
-- note it as refclk_time to prevent false triggering
-- of stop_vco after areset
if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then
refclk_time := now;
pll_is_in_reset := false;
locked_tmp := '0';
end if;
-- calculate loop_xplier : this will be different from m_val
-- in external_feedback_mode
loop_xplier := m_val;
loop_initial := m_initial_val - 1;
loop_ph := m_ph_val;
-- convert initial value to delay
initial_delay := (loop_initial * m_times_vco_period)/loop_xplier;
-- convert loop ph_tap to delay
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier;
if (my_rem /= 0) then
tmp_vco_per := tmp_vco_per + 1;
end if;
fbk_phase := (loop_ph * tmp_vco_per)/8;
pull_back_M := initial_delay/1 ps + fbk_phase;
total_pull_back := pull_back_M;
if (simulation_type = "timing") then
total_pull_back := total_pull_back + pll_compensation_delay;
end if;
while (total_pull_back > refclk_period/1 ps) loop
total_pull_back := total_pull_back - refclk_period/1 ps;
end loop;
if (total_pull_back > 0) then
offset := refclk_period - (total_pull_back * 1 ps);
end if;
fbk_delay := total_pull_back - fbk_phase;
if (fbk_delay < 0) then
offset := offset - (fbk_phase * 1 ps);
fbk_delay := total_pull_back;
end if;
-- assign m_delay
m_delay <= transport fbk_delay after 1 ps;
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
for i in 1 to loop_xplier loop
-- adjust cycles
tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier;
if (my_rem /= 0 and l_index <= my_rem) then
tmp_rem := (loop_xplier * l_index) rem my_rem;
cycle_to_adjust := (loop_xplier * l_index) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
if (cycle_to_adjust = i) then
tmp_vco_per := tmp_vco_per + 1;
l_index := l_index + 1;
end if;
-- calculate high and low periods
vco_per := tmp_vco_per * 1 ps;
high_time := (tmp_vco_per/2) * 1 ps;
if (tmp_vco_per rem 2 /= 0) then
high_time := high_time + 1 ps;
end if;
low_time := vco_per - high_time;
-- schedule the rising and falling edges
for j in 1 to 2 loop
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
if (first_schedule) then
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
else
vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k));
end if;
end loop;
end loop;
end loop;
-- schedule once more
if (first_schedule) then
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
end loop;
first_schedule := false;
end if;
schedule_vco <= transport not schedule_vco after sched_time;
if (vco_period_was_phase_adjusted) then
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := true;
vco_per := m_times_vco_period/loop_xplier;
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
end loop;
end if;
end if;
-- Bypass lock detect
if (refclk'event and refclk = '1' and areset_ipd = '0') then
if (test_bypass_lock_detect = "on") then
if (pfdena_ipd = '1') then
cycles_pfd_low := 0;
if (pfd_locked = '0') then
if (cycles_pfd_high = lock_high) then
assert false report family_name & " PLL locked in test mode on PFD enable assertion." severity warning;
pfd_locked <= '1';
end if;
cycles_pfd_high := cycles_pfd_high + 1;
end if;
end if;
if (pfdena_ipd = '0') then
cycles_pfd_high := 0;
if (pfd_locked = '1') then
if (cycles_pfd_low = lock_low) then
assert false report family_name & " PLL lost lock in test mode on PFD enable de-assertion." severity warning;
pfd_locked <= '0';
end if;
cycles_pfd_low := cycles_pfd_low + 1;
end if;
end if;
end if;
if (refclk'event and refclk = '1' and areset_ipd = '0') then
got_refclk_posedge := true;
if (not got_first_refclk) then
got_first_refclk := true;
else
got_second_refclk := true;
refclk_period := now - refclk_time;
-- check if incoming freq. will cause VCO range to be
-- exceeded
if ( (i_vco_max /= 0 and i_vco_min /= 0 and pfdena_ipd = '1') and
(((refclk_period/1 ps)/loop_xplier > i_vco_max) or
((refclk_period/1 ps)/loop_xplier < i_vco_min)) ) then
if (pll_is_locked) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
if (inclk_out_of_range) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
elsif (not no_warn) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning;
no_warn := true;
end if;
inclk_out_of_range := true;
else
vco_over <= '0';
vco_under <= '0';
inclk_out_of_range := false;
no_warn := false;
end if;
end if;
end if;
if (stop_vco) then
stop_vco := false;
schedule_vco <= not schedule_vco;
end if;
refclk_time := now;
else
got_refclk_posedge := false;
end if;
-- Update M counter value on feedback clock edge
if (fbclk'event and fbclk = '1') then
got_fbclk_posedge := true;
if (not got_first_fbclk) then
got_first_fbclk := true;
else
fbclk_period := now - fbclk_time;
end if;
-- need refclk_period here, so initialized to proper value above
if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or
( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = false) or
( (now - refclk_time > 50 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = true) ) then
stop_vco := true;
-- reset
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
if (pll_is_locked) then
pll_is_locked := false;
locked_tmp := '0';
assert false report family_name & " PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame." severity note;
if ((i_vco_max = 0) and (i_vco_min = 0)) then
assert false report "Please run timing simulation to check whether the input clock is operating within the supported VCO range or not." severity note;
end if;
end if;
cycles_to_lock := 0;
cycles_to_unlock := 0;
first_schedule := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
fbclk_time := now;
else
got_fbclk_posedge := false;
end if;
if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then
-- now we know actual incoming period
if ( abs(fbclk_time - refclk_time) <= 5 ps or
(got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
-- considered in phase
if (cycles_to_lock = real_lock_high) then
if (not pll_is_locked) then
assert false report family_name & " PLL locked to incoming clock" severity note;
end if;
pll_is_locked := true;
locked_tmp := '1';
cycles_to_unlock := 0;
end if;
-- increment lock counter only if second part of above
-- time check is NOT true
if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window)) then
cycles_to_lock := cycles_to_lock + 1;
end if;
-- adjust m_times_vco_period
new_m_times_vco_period := refclk_period;
else
-- if locked, begin unlock
if (pll_is_locked) then
cycles_to_unlock := cycles_to_unlock + 1;
if (cycles_to_unlock = lock_low) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
end if;
end if;
if ( abs(refclk_period - fbclk_period) <= 2 ps ) then
-- frequency is still good
if (now = fbclk_time and (not phase_adjust_was_scheduled)) then
if ( abs(fbclk_time - refclk_time) > refclk_period/2) then
new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted := true;
else
new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted := true;
end if;
end if;
else
phase_adjust_was_scheduled := false;
new_m_times_vco_period := refclk_period;
end if;
end if;
end if;
if (pfdena_ipd = '0') then
if (pll_is_locked) then
locked_tmp := 'X';
end if;
pll_is_locked := false;
cycles_to_lock := 0;
end if;
-- give message only at time of deassertion
if (pfdena_ipd'event and pfdena_ipd = '0') then
assert false report "PFDENA deasserted." severity note;
elsif (pfdena_ipd'event and pfdena_ipd = '1') then
got_first_refclk := false;
got_second_refclk := false;
refclk_time := now;
end if;
if (reconfig_err) then
lock <= '0';
else
lock <= locked_tmp;
end if;
-- signal to calculate quiet_time
sig_refclk_period <= refclk_period;
if (stop_vco = true) then
sig_stop_vco <= '1';
else
sig_stop_vco <= '0';
end if;
pll_locked <= pll_is_locked;
end process;
clk0_tmp <= c_clk(i_clk0_counter);
clk_pfd(0) <= clk0_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(0) <= clk_pfd(0) WHEN (test_bypass_lock_detect = "on") ELSE
clk0_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else
'X';
clk1_tmp <= c_clk(i_clk1_counter);
clk_pfd(1) <= clk1_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(1) <= clk_pfd(1) WHEN (test_bypass_lock_detect = "on") ELSE
clk1_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk2_tmp <= c_clk(i_clk2_counter);
clk_pfd(2) <= clk2_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(2) <= clk_pfd(2) WHEN (test_bypass_lock_detect = "on") ELSE
clk2_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk3_tmp <= c_clk(i_clk3_counter);
clk_pfd(3) <= clk3_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(3) <= clk_pfd(3) WHEN (test_bypass_lock_detect = "on") ELSE
clk3_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk4_tmp <= c_clk(i_clk4_counter);
clk_pfd(4) <= clk4_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(4) <= clk_pfd(4) WHEN (test_bypass_lock_detect = "on") ELSE
clk4_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk5_tmp <= c_clk(i_clk5_counter);
clk_pfd(5) <= clk5_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(5) <= clk_pfd(5) WHEN (test_bypass_lock_detect = "on") ELSE
clk5_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk6_tmp <= c_clk(i_clk6_counter);
clk_pfd(6) <= clk6_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(6) <= clk_pfd(6) WHEN (test_bypass_lock_detect = "on") ELSE
clk6_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk7_tmp <= c_clk(i_clk7_counter);
clk_pfd(7) <= clk7_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(7) <= clk_pfd(7) WHEN (test_bypass_lock_detect = "on") ELSE
clk7_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk8_tmp <= c_clk(i_clk8_counter);
clk_pfd(8) <= clk8_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(8) <= clk_pfd(8) WHEN (test_bypass_lock_detect = "on") ELSE
clk8_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk9_tmp <= c_clk(i_clk9_counter);
clk_pfd(9) <= clk9_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(9) <= clk_pfd(9) WHEN (test_bypass_lock_detect = "on") ELSE
clk9_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
scandataout <= scandata_out;
scandone <= NOT scandone_tmp;
phasedone <= NOT update_phase;
vcooverrange <= 'Z' WHEN (vco_range_detector_high_bits = -1) ELSE vco_over;
vcounderrange <= 'Z' WHEN (vco_range_detector_low_bits = -1) ELSE vco_under;
fbout <= fbclk;
end vital_pll;
-- END ARCHITECTURE VITAL_PLL
-------------------------------------------------------------------
--
-- Entity Name : stratixiii_asmiblock
--
-- Description : Stratix III ASMIBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_asmiblock is
generic (
lpm_type : string := "stratixiii_asmiblock"
);
port (
dclkin : in std_logic := '0';
scein : in std_logic := '0';
sdoin : in std_logic := '0';
data0in : in std_logic := '0';
oe : in std_logic := '0';
dclkout : out std_logic;
sceout : out std_logic;
sdoout : out std_logic;
data0out: out std_logic
);
end stratixiii_asmiblock;
architecture architecture_asmiblock of stratixiii_asmiblock is
begin
end architecture_asmiblock; -- end of stratixiii_asmiblock
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiii_lvds_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for registering the enable inputs.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
ENTITY stratixiii_lvds_reg is
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := True;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END stratixiii_lvds_reg;
ARCHITECTURE vital_titan_lvds_reg of stratixiii_lvds_reg is
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal ena_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (d_ipd, d, tipd_d);
end block;
process (clk_ipd, d_ipd, clrn, prn)
variable q_tmp : std_logic := '0';
variable q_VitalGlitchData : VitalGlitchDataType;
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (prn = '0') then
q_tmp := '1';
elsif (clrn = '0') then
q_tmp := '0';
elsif (clk_ipd'event and clk_ipd = '1') then
if (ena_ipd = '1') then
q_tmp := d_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_tmp,
Paths => (1 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_titan_lvds_reg;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiii_lvds_rx_fifo_sync_ram
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
--USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
ENTITY stratixiii_lvds_rx_fifo_sync_ram is
PORT ( clk : IN std_logic;
datain : IN std_logic := '0';
writereset : IN std_logic := '0';
waddr : IN std_logic_vector(2 DOWNTO 0) := "000";
raddr : IN std_logic_vector(2 DOWNTO 0) := "000";
we : IN std_logic := '0';
dataout : OUT std_logic
);
END stratixiii_lvds_rx_fifo_sync_ram;
ARCHITECTURE vital_arm_lvds_rx_fifo_sync_ram OF stratixiii_lvds_rx_fifo_sync_ram IS
-- INTERNAL SIGNALS
signal dataout_tmp : std_logic;
signal ram_d : std_logic_vector(0 TO 5);
signal ram_q : std_logic_vector(0 TO 5);
signal data_reg : std_logic_vector(0 TO 5);
begin
dataout <= dataout_tmp;
process (clk, writereset)
variable initial : boolean := true;
begin
if (initial) then
for i in 0 to 5 loop
ram_q(i) <= '0';
end loop;
initial := false;
end if;
if (writereset = '1') then
for i in 0 to 5 loop
ram_q(i) <= '0';
end loop;
elsif (clk'event and clk = '1') then
for i in 0 to 5 loop
ram_q(i) <= ram_d(i);
end loop;
end if;
end process;
process (we, data_reg, ram_q)
begin
if (we = '1') then
ram_d <= data_reg;
else
ram_d <= ram_q;
end if;
end process;
data_reg(0) <= datain when (waddr = "000") else ram_q(0) ;
data_reg(1) <= datain when (waddr = "001") else ram_q(1) ;
data_reg(2) <= datain when (waddr = "010") else ram_q(2) ;
data_reg(3) <= datain when (waddr = "011") else ram_q(3) ;
data_reg(4) <= datain when (waddr = "100") else ram_q(4) ;
data_reg(5) <= datain when (waddr = "101") else ram_q(5) ;
process (ram_q, we, waddr, raddr)
variable initial : boolean := true;
begin
if (initial) then
dataout_tmp <= '0';
initial := false;
end if;
case raddr is
when "000" =>
dataout_tmp <= ram_q(0);
when "001" =>
dataout_tmp <= ram_q(1);
when "010" =>
dataout_tmp <= ram_q(2);
when "011" =>
dataout_tmp <= ram_q(3);
when "100" =>
dataout_tmp <= ram_q(4);
when "101" =>
dataout_tmp <= ram_q(5);
when others =>
dataout_tmp <= '0';
end case;
end process;
END vital_arm_lvds_rx_fifo_sync_ram;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiii_lvds_rx_fifo
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
USE work.stratixiii_lvds_rx_fifo_sync_ram;
ENTITY stratixiii_lvds_rx_fifo is
GENERIC ( channel_width : integer := 10;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_wclk : VitalDelayType01 := DefpropDelay01;
tipd_rclk : VitalDelayType01 := DefpropDelay01;
tipd_dparst : VitalDelayType01 := DefpropDelay01;
tipd_fiforst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_rclk_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_dparst_dataout_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( wclk : IN std_logic:= '0';
rclk : IN std_logic:= '0';
dparst : IN std_logic := '0';
fiforst : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic
);
END stratixiii_lvds_rx_fifo;
ARCHITECTURE vital_arm_lvds_rx_fifo of stratixiii_lvds_rx_fifo is
-- INTERNAL SIGNALS
signal datain_in : std_logic;
signal rclk_in : std_logic;
signal dparst_in : std_logic;
signal fiforst_in : std_logic;
signal wclk_in : std_logic;
signal ram_datain : std_logic;
signal ram_dataout : std_logic;
signal wrPtr : std_logic_vector(2 DOWNTO 0);
signal rdPtr : std_logic_vector(2 DOWNTO 0);
signal rdAddr : std_logic_vector(2 DOWNTO 0);
signal ram_we : std_logic;
signal write_side_sync_reset : std_logic;
signal read_side_sync_reset : std_logic;
COMPONENT stratixiii_lvds_rx_fifo_sync_ram
PORT ( clk : IN std_logic;
datain : IN std_logic := '0';
writereset : IN std_logic := '0';
waddr : IN std_logic_vector(2 DOWNTO 0) := "000";
raddr : IN std_logic_vector(2 DOWNTO 0) := "000";
we : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (wclk_in, wclk, tipd_wclk);
VitalWireDelay (rclk_in, rclk, tipd_rclk);
VitalWireDelay (dparst_in, dparst, tipd_dparst);
VitalWireDelay (fiforst_in, fiforst, tipd_fiforst);
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
rdAddr <= rdPtr ;
s_fifo_ram : stratixiii_lvds_rx_fifo_sync_ram
PORT MAP ( clk => wclk_in,
datain => ram_datain,
writereset => write_side_sync_reset,
waddr => wrPtr,
raddr => rdAddr,
we => ram_we,
dataout => ram_dataout
);
process (wclk_in, dparst_in)
variable initial : boolean := true;
begin
if (initial) then
wrPtr <= "000";
write_side_sync_reset <= '0';
ram_we <= '0';
ram_datain <= '0';
initial := false;
end if;
if (dparst_in = '1' or (fiforst_in = '1' and wclk_in'event and wclk_in = '1')) then
write_side_sync_reset <= '1';
ram_datain <= '0';
wrPtr <= "000";
ram_we <= '0';
elsif (dparst_in = '0' and (fiforst_in = '0' and wclk_in'event and wclk_in = '1')) then
write_side_sync_reset <= '0';
end if;
if (wclk_in'event and wclk_in = '1' and write_side_sync_reset = '0' and fiforst_in = '0' and dparst_in = '0') then
ram_datain <= datain_in;
ram_we <= '1';
case wrPtr is
when "000" => wrPtr <= "001";
when "001" => wrPtr <= "010";
when "010" => wrPtr <= "011";
when "011" => wrPtr <= "100";
when "100" => wrPtr <= "101";
when "101" => wrPtr <= "000";
when others => wrPtr <= "000";
end case;
end if;
end process;
process (rclk_in, dparst_in)
variable initial : boolean := true;
variable dataout_tmp : std_logic := '0';
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
if (initial) then
rdPtr <= "011";
read_side_sync_reset <= '0';
dataout_tmp := '0';
initial := false;
end if;
if (dparst_in = '1' or (fiforst_in = '1' and rclk_in'event and rclk_in = '1')) then
read_side_sync_reset <= '1';
rdPtr <= "011";
dataout_tmp := '0';
elsif (dparst_in = '0' and (fiforst_in = '0' and rclk_in'event and rclk_in = '1')) then
read_side_sync_reset <= '0';
end if;
if (rclk_in'event and rclk_in = '1' and read_side_sync_reset = '0' and fiforst_in = '0' and dparst_in = '0') then
case rdPtr is
when "000" => rdPtr <= "001";
when "001" => rdPtr <= "010";
when "010" => rdPtr <= "011";
when "011" => rdPtr <= "100";
when "100" => rdPtr <= "101";
when "101" => rdPtr <= "000";
when others => rdPtr <= "000";
end case;
dataout_tmp := ram_dataout;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
Outsignal => dataout,
OutsignalName => "DATAOUT",
OutTemp => dataout_tmp,
Paths => (1 => (rclk_in'last_event, tpd_rclk_dataout_posedge, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
END vital_arm_lvds_rx_fifo;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiii_lvds_rx_bitslip
--
-- Description :
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
USE work.stratixiii_lvds_reg;
ENTITY stratixiii_lvds_rx_bitslip is
GENERIC ( channel_width : integer := 10;
bitslip_rollover : integer := 12;
x_on_bitslip : string := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_bslipcntl : VitalDelayType01 := DefpropDelay01;
tipd_bsliprst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_bsliprst_bslipmax_posedge: VitalDelayType01 := DefPropDelay01;
tpd_clk0_bslipmax_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic := '0';
bslipcntl : IN std_logic := '0';
bsliprst : IN std_logic := '0';
datain : IN std_logic := '0';
bslipmax : OUT std_logic;
dataout : OUT std_logic
);
END stratixiii_lvds_rx_bitslip;
ARCHITECTURE vital_arm_lvds_rx_bitslip OF stratixiii_lvds_rx_bitslip IS
-- INTERNAL SIGNALS
signal clk0_in : std_logic;
signal bslipcntl_in : std_logic;
signal bsliprst_in : std_logic;
signal datain_in : std_logic;
signal slip_count : integer := 0;
signal dataout_tmp : std_logic;
signal bitslip_arr : std_logic_vector(11 DOWNTO 0) := "000000000000";
signal bslipcntl_reg : std_logic;
signal vcc : std_logic := '1';
signal slip_data : std_logic := '0';
signal start_corrupt_bits : std_logic := '0';
signal num_corrupt_bits : integer := 0;
COMPONENT stratixiii_lvds_reg
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk0_in, clk0, tipd_clk0);
VitalWireDelay (bslipcntl_in, bslipcntl, tipd_bslipcntl);
VitalWireDelay (bsliprst_in, bsliprst, tipd_bsliprst);
VitalWireDelay (datain_in, datain, tipd_datain);
end block;
bslipcntlreg : stratixiii_lvds_reg
PORT MAP ( d => bslipcntl_in,
clk => clk0_in,
ena => vcc,
clrn => vcc,
prn => vcc,
q => bslipcntl_reg
);
-- 4-bit slip counter and 12-bit shift register
process (bslipcntl_reg, bsliprst_in, clk0_in)
variable initial : boolean := true;
variable bslipmax_tmp : std_logic := '0';
variable bslipmax_VitalGlitchData : VitalGlitchDataType;
begin
if (bsliprst_in = '1') then
slip_count <= 0;
bslipmax_tmp := '0';
-- bitslip_arr <= (OTHERS => '0');
if (bsliprst_in'event and bsliprst_in = '1' and bsliprst_in'last_value = '0') then
ASSERT false report "Bit Slip Circuit was reset. Serial Data stream will have 0 latency" severity note;
end if;
else
if (bslipcntl_reg'event and bslipcntl_reg = '1' and bslipcntl_reg'last_value = '0') then
if (x_on_bitslip = "on") then
start_corrupt_bits <= '1';
end if;
num_corrupt_bits <= 0;
if (slip_count = bitslip_rollover) then
ASSERT false report "Rollover occurred on Bit Slip circuit. Serial data stream will have 0 latency." severity note;
slip_count <= 0;
bslipmax_tmp := '0';
else
slip_count <= slip_count + 1;
if ((slip_count + 1) = bitslip_rollover) then
ASSERT false report "The Bit Slip circuit has reached the maximum Bit Slip limit. Rollover will occur on the next slip." severity note;
bslipmax_tmp := '1';
end if;
end if;
elsif (bslipcntl_reg'event and bslipcntl_reg = '0' and bslipcntl_reg'last_value = '1') then
start_corrupt_bits <= '0';
num_corrupt_bits <= 0;
end if;
end if;
if (clk0_in'event and clk0_in = '1' and clk0_in'last_value = '0') then
bitslip_arr(0) <= datain_in;
for i in 0 to (bitslip_rollover - 1) loop
bitslip_arr(i + 1) <= bitslip_arr(i);
end loop;
if (start_corrupt_bits = '1') then
num_corrupt_bits <= num_corrupt_bits + 1;
end if;
if (num_corrupt_bits+1 = 3) then
start_corrupt_bits <= '0';
end if;
end if;
-- end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
Outsignal => bslipmax,
OutsignalName => "BSLIPMAX",
OutTemp => bslipmax_tmp,
Paths => (1 => (clk0_in'last_event, tpd_clk0_bslipmax_posedge, TRUE),
2 => (bsliprst_in'last_event, tpd_bsliprst_bslipmax_posedge, TRUE)),
GlitchData => bslipmax_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
slip_data <= bitslip_arr(slip_count);
dataoutreg : stratixiii_lvds_reg
PORT MAP ( d => slip_data,
clk => clk0_in,
ena => vcc,
clrn => vcc,
prn => vcc,
q => dataout_tmp
);
dataout <= dataout_tmp when start_corrupt_bits = '0' else
'X' when start_corrupt_bits = '1' and num_corrupt_bits < 3 else
dataout_tmp;
END vital_arm_lvds_rx_bitslip;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiii_lvds_rx_deser
--
-- Description : Timing simulation model for the stratixiii LVDS RECEIVER
-- DESERIALIZER. This module receives serial data and outputs
-- parallel data word of width = channel width
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
ENTITY stratixiii_lvds_rx_deser IS
GENERIC ( channel_width : integer := 4;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiii_lvds_rx_deser;
ARCHITECTURE vital_arm_lvds_rx_deser OF stratixiii_lvds_rx_deser IS
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal datain_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process (clk_ipd, devpor, devclrn)
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
variable i : integer := 0;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if (devclrn = '0' or devpor = '0') then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0') then
for i in channel_width - 1 DOWNTO 1 loop
dataout_tmp(i) := dataout_tmp(i - 1);
end loop;
dataout_tmp(0) := datain_ipd;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay (
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= TRANSPORT dataout_tmp AFTER CQDelay;
end process;
END vital_arm_lvds_rx_deser;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiii_lvds_rx_parallel_reg
--
-- Description : Timing simulation model for the stratixiii LVDS RECEIVER
-- PARALLEL REGISTER. The data width equals max. channel width,
-- which is 10.
--
--////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
ENTITY stratixiii_lvds_rx_parallel_reg IS
GENERIC ( channel_width : integer := 4;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_enable : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tpd_clk_dataout_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk : IN std_logic;
enable : IN std_logic := '1';
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0);
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiii_lvds_rx_parallel_reg;
ARCHITECTURE vital_arm_lvds_rx_parallel_reg OF stratixiii_lvds_rx_parallel_reg IS
-- INTERNAL SIGNALS
signal clk_ipd : std_logic;
signal datain_ipd : std_logic_vector(channel_width - 1 downto 0);
signal enable_ipd : std_logic;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (enable_ipd, enable, tipd_enable);
loopbits : FOR i in datain'RANGE GENERATE
VitalWireDelay (datain_ipd(i), datain(i), tipd_datain(i));
END GENERATE;
end block;
VITAL: process (clk_ipd, devpor, devclrn)
variable dataout_tmp : std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
variable i : integer := 0;
variable dataout_VitalGlitchDataArray : VitalGlitchDataArrayType(9 downto 0);
variable CQDelay : TIME := 0 ns;
begin
if ((devpor = '0') or (devclrn = '0')) then
dataout_tmp := (OTHERS => '0');
else
if (clk_ipd'event and clk_ipd = '1') then
if (enable_ipd = '1') then
dataout_tmp := datain_ipd;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
CQDelay := SelectDelay (
(1 => (clk_ipd'last_event, tpd_clk_dataout_posedge, TRUE))
);
dataout <= dataout_tmp AFTER CQDelay;
end process;
END vital_arm_lvds_rx_parallel_reg;
-------------------------------------------------------------------------------
--
-- Module Name : stratixiii_pclk_divider
--
-- Description : Simulation model for a clock divider
-- output clock is divided by value specified
-- in the parameter clk_divide_by
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY stratixiii_pclk_divider IS
GENERIC (
clk_divide_by : integer := 1);
PORT (
clkin : IN std_logic;
lloaden : OUT std_logic;
clkout : OUT std_logic);
END stratixiii_pclk_divider;
ARCHITECTURE arch OF stratixiii_pclk_divider IS
SIGNAL lloaden_tmp : std_logic := '0';
SIGNAL clkout_tmp : std_logic := '0';
SIGNAL cnt : std_logic_vector(4 DOWNTO 0):= (others => '0');
BEGIN
clkout <= clkin WHEN (clk_divide_by = 1) ELSE clkout_tmp;
lloaden <= lloaden_tmp;
PROCESS(clkin)
variable count : std_logic := '0';
variable start : std_logic := '0';
variable prev_load : std_logic := '0';
BEGIN
IF(clkin = '1') THEN
count := '1';
END IF;
if( count = '1') then
IF (cnt < clk_divide_by) THEN
clkout_tmp <= '0';
cnt <= cnt + "00001";
ELSE
IF (cnt = (2 * clk_divide_by - 1)) THEN
cnt <= "00000";
ELSE
clkout_tmp <= '1';
cnt <= cnt + "00001";
END IF;
END IF;
end if;
END PROCESS;
process( clkin, cnt )
begin
if( cnt =( 2*clk_divide_by -2) )then
lloaden_tmp <= '1';
else
if(cnt = 0)then
lloaden_tmp <= '0';
end if;
end if;
end process;
END arch;
-------------------------------------------------------------------------------
--
-- Module Name : stratixiii_select_ini_phase_dpaclk
--
-- Description : Simulation model for selecting the initial phase of the dpa clock
--
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.ALL;
ENTITY stratixiii_select_ini_phase_dpaclk IS
GENERIC(
initial_phase_select : integer := 0
);
PORT (
clkin : IN STD_LOGIC;
loaden : IN STD_LOGIC;
enable : IN STD_LOGIC;
clkout : OUT STD_LOGIC;
loadenout : OUT STD_LOGIC
);
END stratixiii_select_ini_phase_dpaclk;
ARCHITECTURE trans OF stratixiii_select_ini_phase_dpaclk IS
SIGNAL clk_period : time := 0 ps;
SIGNAL last_clk_period : time := 0 ps;
SIGNAL last_clkin_edge : time := 0 ps;
SIGNAL first_clkin_edge_detect : STD_LOGIC := '0';
SIGNAL clk0_tmp : STD_LOGIC;
SIGNAL clk1_tmp : STD_LOGIC;
SIGNAL clk2_tmp : STD_LOGIC;
SIGNAL clk3_tmp : STD_LOGIC;
SIGNAL clk4_tmp : STD_LOGIC;
SIGNAL clk5_tmp : STD_LOGIC;
SIGNAL clk6_tmp : STD_LOGIC;
SIGNAL clk7_tmp : STD_LOGIC;
SIGNAL loaden0_tmp : STD_LOGIC;
SIGNAL loaden1_tmp : STD_LOGIC;
SIGNAL loaden2_tmp : STD_LOGIC;
SIGNAL loaden3_tmp : STD_LOGIC;
SIGNAL loaden4_tmp : STD_LOGIC;
SIGNAL loaden5_tmp : STD_LOGIC;
SIGNAL loaden6_tmp : STD_LOGIC;
SIGNAL loaden7_tmp : STD_LOGIC;
SIGNAL clkout_tmp : STD_LOGIC;
SIGNAL loadenout_tmp : STD_LOGIC;
BEGIN
clkout_tmp <= clk1_tmp when (initial_phase_select = 1) else
clk2_tmp when (initial_phase_select = 2) else
clk3_tmp when (initial_phase_select = 3) else
clk4_tmp when (initial_phase_select = 4) else
clk5_tmp when (initial_phase_select = 5) else
clk6_tmp when (initial_phase_select = 6) else
clk7_tmp when (initial_phase_select = 7) else
clk0_tmp;
clkout <= clkout_tmp when enable = '1' else clkin;
loadenout_tmp <= loaden1_tmp when (initial_phase_select = 1) else
loaden2_tmp when (initial_phase_select = 2) else
loaden3_tmp when (initial_phase_select = 3) else
loaden4_tmp when (initial_phase_select = 4) else
loaden5_tmp when (initial_phase_select = 5) else
loaden6_tmp when (initial_phase_select = 6) else
loaden7_tmp when (initial_phase_select = 7) else
loaden0_tmp;
loadenout <= loadenout_tmp when enable = '1' else loaden;
-- Calculate the clock period
PROCESS
VARIABLE clk_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (clkin'EVENT AND clkin = '1');
IF (first_clkin_edge_detect = '0') THEN
first_clkin_edge_detect <= '1';
ELSE
last_clk_period <= clk_period;
clk_period_tmp := NOW - last_clkin_edge;
END IF;
last_clkin_edge <= NOW;
clk_period <= clk_period_tmp;
END PROCESS;
-- Generate the phase shifted signals
PROCESS (clkin)
BEGIN
clk0_tmp <= clkin;
clk1_tmp <= TRANSPORT clkin after (clk_period * 0.125) ;
clk2_tmp <= TRANSPORT clkin after (clk_period * 0.25) ;
clk3_tmp <= TRANSPORT clkin after (clk_period * 0.375) ;
clk4_tmp <= TRANSPORT clkin after (clk_period * 0.5) ;
clk5_tmp <= TRANSPORT clkin after (clk_period * 0.625) ;
clk6_tmp <= TRANSPORT clkin after (clk_period * 0.75) ;
clk7_tmp <= TRANSPORT clkin after (clk_period * 0.875) ;
END PROCESS;
PROCESS (loaden)
BEGIN
loaden0_tmp <= clkin;
loaden1_tmp <= TRANSPORT loaden after (clk_period * 0.125) ;
loaden2_tmp <= TRANSPORT loaden after (clk_period * 0.25) ;
loaden3_tmp <= TRANSPORT loaden after (clk_period * 0.375) ;
loaden4_tmp <= TRANSPORT loaden after (clk_period * 0.5) ;
loaden5_tmp <= TRANSPORT loaden after (clk_period * 0.625) ;
loaden6_tmp <= TRANSPORT loaden after (clk_period * 0.75) ;
loaden7_tmp <= TRANSPORT loaden after (clk_period * 0.875) ;
END PROCESS;
END trans;
-------------------------------------------------------------------------------
--
-- Module Name : stratixiii_dpa_retime_block
--
-- Description : Simulation model for generating the retimed clock,data and loaden.
-- Each of the signals has 8 different phase shifted versions.
--
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.ALL;
ENTITY stratixiii_dpa_retime_block IS
PORT (
clkin : IN STD_LOGIC;
datain : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk0 : OUT STD_LOGIC;
clk1 : OUT STD_LOGIC;
clk2 : OUT STD_LOGIC;
clk3 : OUT STD_LOGIC;
clk4 : OUT STD_LOGIC;
clk5 : OUT STD_LOGIC;
clk6 : OUT STD_LOGIC;
clk7 : OUT STD_LOGIC;
data0 : OUT STD_LOGIC;
data1 : OUT STD_LOGIC;
data2 : OUT STD_LOGIC;
data3 : OUT STD_LOGIC;
data4 : OUT STD_LOGIC;
data5 : OUT STD_LOGIC;
data6 : OUT STD_LOGIC;
data7 : OUT STD_LOGIC;
lock : OUT STD_LOGIC
);
END stratixiii_dpa_retime_block;
ARCHITECTURE trans OF stratixiii_dpa_retime_block IS
SIGNAL clk_period : time := 0 ps;
SIGNAL last_clk_period : time := 0 ps;
SIGNAL last_clkin_edge : time := 0 ps;
SIGNAL first_clkin_edge_detect : STD_LOGIC := '0';
SIGNAL clk0_tmp : STD_LOGIC;
SIGNAL clk1_tmp : STD_LOGIC;
SIGNAL clk2_tmp : STD_LOGIC;
SIGNAL clk3_tmp : STD_LOGIC;
SIGNAL clk4_tmp : STD_LOGIC;
SIGNAL clk5_tmp : STD_LOGIC;
SIGNAL clk6_tmp : STD_LOGIC;
SIGNAL clk7_tmp : STD_LOGIC;
SIGNAL data0_tmp : STD_LOGIC;
SIGNAL data1_tmp : STD_LOGIC;
SIGNAL data2_tmp : STD_LOGIC;
SIGNAL data3_tmp : STD_LOGIC;
SIGNAL data4_tmp : STD_LOGIC;
SIGNAL data5_tmp : STD_LOGIC;
SIGNAL data6_tmp : STD_LOGIC;
SIGNAL data7_tmp : STD_LOGIC;
SIGNAL lock_tmp : STD_LOGIC := '0';
BEGIN
clk0 <= '0' WHEN reset = '1' ELSE clk0_tmp;
clk1 <= '0' WHEN reset = '1' ELSE clk1_tmp;
clk2 <= '0' WHEN reset = '1' ELSE clk2_tmp;
clk3 <= '0' WHEN reset = '1' ELSE clk3_tmp;
clk4 <= '0' WHEN reset = '1' ELSE clk4_tmp;
clk5 <= '0' WHEN reset = '1' ELSE clk5_tmp;
clk6 <= '0' WHEN reset = '1' ELSE clk6_tmp;
clk7 <= '0' WHEN reset = '1' ELSE clk7_tmp;
data0 <= '0' WHEN reset = '1' ELSE data0_tmp;
data1 <= '0' WHEN reset = '1' ELSE data1_tmp;
data2 <= '0' WHEN reset = '1' ELSE data2_tmp;
data3 <= '0' WHEN reset = '1' ELSE data3_tmp;
data4 <= '0' WHEN reset = '1' ELSE data4_tmp;
data5 <= '0' WHEN reset = '1' ELSE data5_tmp;
data6 <= '0' WHEN reset = '1' ELSE data6_tmp;
data7 <= '0' WHEN reset = '1' ELSE data7_tmp;
lock <= '0' WHEN reset = '1' ELSE lock_tmp;
-- Calculate the clock period
PROCESS
VARIABLE clk_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (clkin'EVENT AND clkin = '1');
IF (first_clkin_edge_detect = '0') THEN
first_clkin_edge_detect <= '1';
ELSE
last_clk_period <= clk_period;
clk_period_tmp := NOW - last_clkin_edge;
END IF;
IF (((clk_period_tmp = last_clk_period) OR (clk_period_tmp = last_clk_period + 1 ps) OR (clk_period_tmp = last_clk_period - 1 ps)) AND (clk_period_tmp /= 0 ps ) AND (last_clk_period /= 0 ps)) THEN
lock_tmp <= '1';
ELSE
lock_tmp <= '0';
END IF;
last_clkin_edge <= NOW;
clk_period <= clk_period_tmp;
END PROCESS;
-- Generate the phase shifted signals
PROCESS (clkin)
BEGIN
clk0_tmp <= clkin;
clk1_tmp <= TRANSPORT clkin after (clk_period * 0.125) ;
clk2_tmp <= TRANSPORT clkin after (clk_period * 0.25) ;
clk3_tmp <= TRANSPORT clkin after (clk_period * 0.375) ;
clk4_tmp <= TRANSPORT clkin after (clk_period * 0.5) ;
clk5_tmp <= TRANSPORT clkin after (clk_period * 0.625) ;
clk6_tmp <= TRANSPORT clkin after (clk_period * 0.75) ;
clk7_tmp <= TRANSPORT clkin after (clk_period * 0.875) ;
END PROCESS;
PROCESS (datain)
BEGIN
data0_tmp <= datain;
data1_tmp <= TRANSPORT datain after (clk_period * 0.125) ;
data2_tmp <= TRANSPORT datain after (clk_period * 0.25) ;
data3_tmp <= TRANSPORT datain after (clk_period * 0.375) ;
data4_tmp <= TRANSPORT datain after (clk_period * 0.5) ;
data5_tmp <= TRANSPORT datain after (clk_period * 0.625) ;
data6_tmp <= TRANSPORT datain after (clk_period * 0.75) ;
data7_tmp <= TRANSPORT datain after (clk_period * 0.875) ;
END PROCESS;
END trans;
-------------------------------------------------------------------------------
--
-- Module Name : stratixiii_dpa_block
--
-- Description : Simulation model for selecting the retimed data, clock and loaden
-- depending on the PPM varaiation and direction of shift.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE work.stratixiii_dpa_retime_block;
ENTITY stratixiii_dpa_block IS
GENERIC (
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : STRING := "off";
enable_soft_cdr_mode: STRING := "on"
);
PORT (
clkin : IN STD_LOGIC;
dpareset : IN STD_LOGIC;
dpahold : IN STD_LOGIC;
datain : IN STD_LOGIC;
clkout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC;
dpalock : OUT STD_LOGIC
);
END stratixiii_dpa_block;
ARCHITECTURE trans OF stratixiii_dpa_block IS
COMPONENT stratixiii_dpa_retime_block
PORT (
clkin : IN STD_LOGIC;
datain : IN STD_LOGIC;
reset : IN STD_LOGIC;
clk0 : OUT STD_LOGIC;
clk1 : OUT STD_LOGIC;
clk2 : OUT STD_LOGIC;
clk3 : OUT STD_LOGIC;
clk4 : OUT STD_LOGIC;
clk5 : OUT STD_LOGIC;
clk6 : OUT STD_LOGIC;
clk7 : OUT STD_LOGIC;
data0 : OUT STD_LOGIC;
data1 : OUT STD_LOGIC;
data2 : OUT STD_LOGIC;
data3 : OUT STD_LOGIC;
data4 : OUT STD_LOGIC;
data5 : OUT STD_LOGIC;
data6 : OUT STD_LOGIC;
data7 : OUT STD_LOGIC;
lock : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL clk0_tmp : STD_LOGIC;
SIGNAL clk1_tmp : STD_LOGIC;
SIGNAL clk2_tmp : STD_LOGIC;
SIGNAL clk3_tmp : STD_LOGIC;
SIGNAL clk4_tmp : STD_LOGIC;
SIGNAL clk5_tmp : STD_LOGIC;
SIGNAL clk6_tmp : STD_LOGIC;
SIGNAL clk7_tmp : STD_LOGIC;
SIGNAL data0_tmp : STD_LOGIC;
SIGNAL data1_tmp : STD_LOGIC;
SIGNAL data2_tmp : STD_LOGIC;
SIGNAL data3_tmp : STD_LOGIC;
SIGNAL data4_tmp : STD_LOGIC;
SIGNAL data5_tmp : STD_LOGIC;
SIGNAL data6_tmp : STD_LOGIC;
SIGNAL data7_tmp : STD_LOGIC;
SIGNAL select_xhdl1 : STD_LOGIC_VECTOR(2 DOWNTO 0) := (others => '0');
SIGNAL clkout_tmp : STD_LOGIC;
SIGNAL dataout_tmp : STD_LOGIC;
SIGNAL counter_reset_value : INTEGER ;
SIGNAL count_value : INTEGER ;
SIGNAL i : INTEGER := 0;
SIGNAL dpalock_xhdl0 : STD_LOGIC;
BEGIN
-- Drive referenced outputs
dpalock <= dpalock_xhdl0;
dataout <= dataout_tmp when (enable_soft_cdr_mode = "on") else datain;
clkout <= clkout_tmp when (enable_soft_cdr_mode = "on") else clkin;
data_clock_retime : stratixiii_dpa_retime_block
PORT MAP (
clkin => clkin,
datain => datain,
reset => dpareset,
clk0 => clk0_tmp,
clk1 => clk1_tmp,
clk2 => clk2_tmp,
clk3 => clk3_tmp,
clk4 => clk4_tmp,
clk5 => clk5_tmp,
clk6 => clk6_tmp,
clk7 => clk7_tmp,
data0 => data0_tmp,
data1 => data1_tmp,
data2 => data2_tmp,
data3 => data3_tmp,
data4 => data4_tmp,
data5 => data5_tmp,
data6 => data6_tmp,
data7 => data7_tmp,
lock => dpalock_xhdl0
);
PROCESS (clkin, dpareset, dpahold)
variable initial : boolean := true;
variable ppm_tmp : integer;
BEGIN
if(initial) then
if(net_ppm_variation = 0) then
ppm_tmp := 1;
else
ppm_tmp := net_ppm_variation;
end if;
if(net_ppm_variation = 0) then
counter_reset_value <= 1;
count_value <= 1;
initial := false;
else
counter_reset_value <= 1000000 / (ppm_tmp * 8);
count_value <= 1000000 / (ppm_tmp * 8);
initial := false;
end if;
end if;
IF (clkin'EVENT AND clkin = '1') THEN
IF(net_ppm_variation = 0) THEN
select_xhdl1 <= "000";
ELSE
IF (dpareset = '1') THEN
i <= 0;
select_xhdl1 <= "000";
ELSE
IF (dpahold = '0') THEN
IF (i < count_value) THEN
i <= i + 1;
ELSE
select_xhdl1 <= select_xhdl1 + "001";
i <= 0;
END IF;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (select_xhdl1, clk0_tmp, clk1_tmp, clk2_tmp, clk3_tmp, clk4_tmp, clk5_tmp, clk6_tmp, clk7_tmp,
data0_tmp, data1_tmp, data2_tmp, data3_tmp, data4_tmp, data5_tmp, data6_tmp, data7_tmp)
BEGIN
if (select_xhdl1 = "000") then
clkout_tmp <= clk0_tmp;
dataout_tmp <= data0_tmp;
elsif (select_xhdl1 = "001") then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk1_tmp;
dataout_tmp <= data1_tmp;
else
clkout_tmp <= clk7_tmp;
dataout_tmp <= data7_tmp;
end if;
elsif (select_xhdl1 = "010") then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk2_tmp;
dataout_tmp <= data2_tmp;
else
clkout_tmp <= clk6_tmp;
dataout_tmp <= data6_tmp;
end if;
elsif (select_xhdl1 = "011")then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk3_tmp;
dataout_tmp <= data3_tmp;
else
clkout_tmp <= clk5_tmp;
dataout_tmp <= data5_tmp;
end if;
elsif (select_xhdl1 = "100")then
clkout_tmp <= clk4_tmp;
dataout_tmp <= data4_tmp;
elsif (select_xhdl1 = "101")then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk5_tmp;
dataout_tmp <= data5_tmp;
else
clkout_tmp <= clk3_tmp;
dataout_tmp <= data3_tmp;
end if;
elsif (select_xhdl1 = "110") then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk6_tmp;
dataout_tmp <= data6_tmp;
else
clkout_tmp <= clk2_tmp;
dataout_tmp <= data2_tmp;
end if;
elsif (select_xhdl1 = "111")then
if( is_negative_ppm_drift = "off")then
clkout_tmp <= clk7_tmp;
dataout_tmp <= data7_tmp;
else
clkout_tmp <= clk1_tmp;
dataout_tmp <= data1_tmp;
end if;
else
clkout_tmp <= clk0_tmp;
dataout_tmp <= data0_tmp;
end if;
END PROCESS;
END trans;
--/////////////////////////////////////////////////////////////////////////////
--
-- Module Name : stratixiii_LVDS_RECEIVER
--
-- Description : Timing simulation model for the stratixiii LVDS RECEIVER
-- atom. This module instantiates the following sub-modules :
-- 1) stratixiii_lvds_rx_fifo
-- 2) stratixiii_lvds_rx_bitslip
-- 3) DFFEs for the LOADEN signals
-- 4) stratixiii_lvds_rx_parallel_reg
-- 5) stratixiii_pclk_divider
-- 6) stratixiii_select_ini_phase_dpaclk
-- 7) stratixiii_dpa_block
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.stratixiii_atom_pack.all;
USE work.stratixiii_lvds_rx_bitslip;
USE work.stratixiii_lvds_rx_fifo;
USE work.stratixiii_lvds_rx_deser;
USE work.stratixiii_lvds_rx_parallel_reg;
USE work.stratixiii_lvds_reg;
USE work.stratixiii_pclk_divider;
USE work.stratixiii_select_ini_phase_dpaclk;
USE work.stratixiii_dpa_block;
ENTITY stratixiii_lvds_receiver IS
GENERIC ( channel_width : integer := 10;
data_align_rollover : integer := 2;
enable_dpa : string := "off";
lose_lock_on_one_change : string := "off";
reset_fifo_at_first_lock : string := "on";
align_to_rising_edge_only : string := "on";
use_serial_feedback_input : string := "off";
dpa_debug : string := "off";
enable_soft_cdr : string := "off";
dpa_output_clock_phase_shift : INTEGER := 0 ;
enable_dpa_initial_phase_selection : string := "off";
dpa_initial_phase_value : INTEGER := 0;
enable_dpa_align_to_rising_edge_only : string := "off";
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : string := "off";
rx_input_path_delay_engineering_bits : INTEGER := -1;
x_on_bitslip : string := "on";
lpm_type : string := "stratixiii_lvds_receiver";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01;
tipd_dpahold : VitalDelayType01 := DefpropDelay01;
tipd_dpaswitch : VitalDelayType01 := DefpropDelay01;
tipd_fiforeset : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_bitslipreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfbk : VitalDelayType01 := DefpropDelay01;
tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic;
datain : IN std_logic := '0';
enable0 : IN std_logic := '0';
dpareset : IN std_logic := '0';
dpahold : IN std_logic := '0';
dpaswitch : IN std_logic := '0';
fiforeset : IN std_logic := '0';
bitslip : IN std_logic := '0';
bitslipreset : IN std_logic := '0';
serialfbk : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dpalock : OUT std_logic:= '0';
bitslipmax : OUT std_logic;
serialdataout : OUT std_logic;
postdpaserialdataout : OUT std_logic;
divfwdclk : OUT std_logic;
dpaclkout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END stratixiii_lvds_receiver;
ARCHITECTURE vital_arm_lvds_receiver OF stratixiii_lvds_receiver IS
COMPONENT stratixiii_lvds_rx_bitslip
GENERIC ( channel_width : integer := 10;
bitslip_rollover : integer := 12;
x_on_bitslip : string := "on";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_bslipcntl : VitalDelayType01 := DefpropDelay01;
tipd_bsliprst : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tpd_bsliprst_bslipmax_posedge: VitalDelayType01 := DefPropDelay01;
tpd_clk0_bslipmax_posedge: VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic := '0';
bslipcntl : IN std_logic := '0';
bsliprst : IN std_logic := '0';
datain : IN std_logic := '0';
bslipmax : OUT std_logic;
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT stratixiii_lvds_rx_fifo
GENERIC ( channel_width : integer := 10
);
PORT ( wclk : IN std_logic := '0';
rclk : IN std_logic := '0';
fiforst : IN std_logic := '0';
dparst : IN std_logic := '0';
datain : IN std_logic := '0';
dataout : OUT std_logic
);
END COMPONENT;
COMPONENT stratixiii_lvds_rx_deser
GENERIC ( channel_width : integer := 4
);
PORT ( clk : IN std_logic;
datain : IN std_logic;
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
COMPONENT stratixiii_lvds_rx_parallel_reg
GENERIC ( channel_width : integer := 4
);
PORT ( clk : IN std_logic;
enable : IN std_logic := '1';
datain : IN std_logic_vector(channel_width - 1 DOWNTO 0);
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
COMPONENT stratixiii_lvds_reg
GENERIC ( MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_ena : VitalDelayType01 := DefpropDelay01;
tipd_d : VitalDelayType01 := DefpropDelay01;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( q : OUT std_logic;
clk : IN std_logic;
ena : IN std_logic := '1';
d : IN std_logic;
clrn : IN std_logic := '1';
prn : IN std_logic := '1'
);
END COMPONENT;
COMPONENT stratixiii_pclk_divider
GENERIC (
clk_divide_by : integer := 1);
PORT (
clkin : IN std_logic;
lloaden : OUT std_logic;
clkout : OUT std_logic);
END COMPONENT;
COMPONENT stratixiii_select_ini_phase_dpaclk
GENERIC(
initial_phase_select : integer := 0
);
PORT (
clkin : IN STD_LOGIC;
loaden : IN STD_LOGIC;
enable : IN STD_LOGIC;
loadenout : OUT STD_LOGIC;
clkout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT stratixiii_dpa_block
GENERIC (
net_ppm_variation : INTEGER := 0;
is_negative_ppm_drift : STRING := "off";
enable_soft_cdr_mode: STRING := "on"
);
PORT (
clkin : IN STD_LOGIC;
dpareset : IN STD_LOGIC;
dpahold : IN STD_LOGIC;
datain : IN STD_LOGIC;
clkout : OUT STD_LOGIC;
dataout : OUT STD_LOGIC;
dpalock : OUT STD_LOGIC
);
END COMPONENT;
-- INTERNAL SIGNALS
signal bitslip_ipd : std_logic;
signal bitslipreset_ipd : std_logic;
signal clk0_ipd : std_logic;
signal datain_ipd : std_logic;
signal dpahold_ipd : std_logic;
signal dpareset_ipd : std_logic;
signal dpaswitch_ipd : std_logic;
signal enable0_ipd : std_logic;
signal fiforeset_ipd : std_logic;
signal serialfbk_ipd : std_logic;
signal fifo_wclk : std_logic;
signal fifo_rclk : std_logic;
signal fifo_datain : std_logic;
signal fifo_dataout : std_logic;
signal fifo_reset : std_logic;
signal slip_datain : std_logic;
signal slip_dataout : std_logic;
signal bitslip_reset : std_logic;
-- wire deser_dataout;
signal dpa_clk : std_logic;
signal dpa_rst : std_logic;
signal datain_reg : std_logic;
signal datain_reg_neg : std_logic;
signal datain_reg_tmp : std_logic;
signal deser_dataout : std_logic_vector(channel_width - 1 DOWNTO 0);
signal reset_fifo : std_logic;
signal gnd : std_logic := '0';
signal vcc : std_logic := '1';
signal in_reg_data : std_logic;
signal slip_datain_tmp : std_logic;
signal s_bitslip_clk : std_logic;
signal loaden : std_logic;
signal ini_dpa_clk : std_logic;
signal ini_dpa_load : std_logic;
signal ini_phase_select_enable : std_logic;
signal dpa_clk_shift : std_logic;
signal dpa_data_shift : std_logic;
signal lloaden : std_logic;
signal lock_tmp : std_logic;
signal divfwdclk_tmp : std_logic;
signal dpa_is_locked : std_logic;
signal dpareg0_out : std_logic;
signal dpareg1_out : std_logic;
signal xhdl_12 : std_logic;
signal rxload : std_logic;
signal clk0_tmp : std_logic;
signal clk0_tmp_neg : std_logic;
begin
WireDelay : block
begin
VitalWireDelay (clk0_ipd, clk0, tipd_clk0);
VitalWireDelay (datain_ipd, datain, tipd_datain);
VitalWireDelay (enable0_ipd, enable0, tipd_enable0);
VitalWireDelay (dpareset_ipd, dpareset, tipd_dpareset);
VitalWireDelay (dpahold_ipd, dpahold, tipd_dpahold);
VitalWireDelay (dpaswitch_ipd, dpaswitch, tipd_dpaswitch);
VitalWireDelay (fiforeset_ipd, fiforeset, tipd_fiforeset);
VitalWireDelay (bitslip_ipd, bitslip, tipd_bitslip);
VitalWireDelay (bitslipreset_ipd, bitslipreset, tipd_bitslipreset);
VitalWireDelay (serialfbk_ipd, serialfbk, tipd_serialfbk);
end block;
process (clk0_ipd, dpareset_ipd,lock_tmp )
variable dpalock_VitalGlitchData : VitalGlitchDataType;
variable initial : boolean := true;
begin
if (initial) then
if (reset_fifo_at_first_lock = "on") then
reset_fifo <= '1';
else
reset_fifo <= '0';
end if;
initial := false;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => dpalock,
OutSignalName => "DPALOCK",
OutTemp => dpa_is_locked,
Paths => (1 => (clk0_ipd'last_event, tpd_clk0_dpalock_posedge, enable_dpa = "on")),
GlitchData => dpalock_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
if(lock_tmp = '1') then
reset_fifo <= '0';
else
reset_fifo <= '1';
end if;
end process;
xhdl_12 <= devclrn OR devpor;
-- input register in non-DPA mode for sampling incoming data
in_reg : stratixiii_lvds_reg
PORT MAP (
d => in_reg_data,
clk => clk0_tmp,
ena => vcc,
clrn => xhdl_12,
prn => vcc,
q => datain_reg
);
in_reg_data <= serialfbk_ipd WHEN (use_serial_feedback_input = "on") ELSE datain_ipd;
clk0_tmp <= clk0_ipd;
clk0_tmp_neg <= not clk0_ipd;
neg_reg : stratixiii_lvds_reg
PORT MAP (
d => in_reg_data,
clk => clk0_tmp_neg,
ena => vcc,
clrn => xhdl_12,
prn => vcc,
q => datain_reg_neg
);
datain_reg_tmp <= datain_reg WHEN (align_to_rising_edge_only = "on") ELSE datain_reg_neg;
-- dpa initial phase select
ini_clk_phase_select: stratixiii_select_ini_phase_dpaclk
GENERIC MAP(
initial_phase_select => dpa_initial_phase_value
)
PORT MAP(
clkin => clk0_ipd,
loaden => enable0_ipd,
enable => ini_phase_select_enable,
loadenout=>ini_dpa_load,
clkout => ini_dpa_clk
);
ini_phase_select_enable <= '1' when (enable_dpa_initial_phase_selection = "on") else '0';
-- DPA circuitary
dpareg0 : stratixiii_lvds_reg
PORT MAP (
d => in_reg_data,
clk => ini_dpa_clk,
clrn => vcc,
prn => vcc,
ena => vcc,
q => dpareg0_out
);
dpareg1 : stratixiii_lvds_reg
PORT MAP ( d => dpareg0_out,
clk => ini_dpa_clk,
clrn => vcc,
prn => vcc,
ena => vcc,
q => dpareg1_out
);
dpa_circuit: stratixiii_dpa_block
GENERIC MAP(
net_ppm_variation => net_ppm_variation,
is_negative_ppm_drift => is_negative_ppm_drift,
enable_soft_cdr_mode => enable_soft_cdr
)
PORT MAP(
clkin => ini_dpa_clk,
dpareset => dpareset_ipd,
dpahold => dpahold_ipd,
datain => dpareg1_out,
clkout => dpa_clk_shift,
dataout => dpa_data_shift,
dpalock => lock_tmp
);
dpa_clk <= dpa_clk_shift when ((enable_soft_cdr = "on") or (enable_dpa = "on")) else '0' ;
dpa_rst <= dpareset_ipd when ((enable_soft_cdr = "on") or (enable_dpa = "on")) else '0' ;
-- PCLK and lloaden generation
clk_forward: stratixiii_pclk_divider
GENERIC MAP (
clk_divide_by => channel_width )
PORT MAP(
clkin => dpa_clk,
lloaden => lloaden,
clkout => divfwdclk_tmp
);
-- FIFO
s_fifo : stratixiii_lvds_rx_fifo
GENERIC MAP ( channel_width => channel_width
)
PORT MAP ( wclk => dpa_clk,
rclk => fifo_rclk,
fiforst => fifo_reset,
dparst => dpa_rst,
datain => fifo_datain,
dataout => fifo_dataout
);
fifo_rclk <= clk0_ipd WHEN (enable_dpa = "on") ELSE gnd ;
fifo_wclk <= dpa_clk ;
fifo_datain <= dpa_data_shift WHEN (enable_dpa = "on") ELSE gnd ;
fifo_reset <= (NOT devpor) OR (NOT devclrn) OR fiforeset_ipd OR dpa_rst OR reset_fifo ;
-- Bit Slip
s_bslip : stratixiii_lvds_rx_bitslip
GENERIC MAP ( bitslip_rollover => data_align_rollover,
channel_width => channel_width,
x_on_bitslip => x_on_bitslip
)
PORT MAP ( clk0 => s_bitslip_clk,
bslipcntl => bitslip_ipd,
bsliprst => bitslip_reset,
datain => slip_datain,
bslipmax => bitslipmax,
dataout => slip_dataout
);
bitslip_reset <= (NOT devpor) OR (NOT devclrn) OR bitslipreset_ipd ;
slip_datain_tmp <= fifo_dataout when (enable_dpa = "on" and dpaswitch_ipd = '1') else datain_reg_tmp ;
slip_datain <= dpa_data_shift when(enable_soft_cdr = "on") else slip_datain_tmp;
s_bitslip_clk <= dpa_clk when (enable_soft_cdr = "on") else clk0_ipd;
-- DESERIALISER
rxload_reg : stratixiii_lvds_reg
PORT MAP ( d => loaden,
clk => s_bitslip_clk,
ena => vcc,
clrn => vcc,
prn => vcc,
q => rxload
);
loaden <= lloaden when (enable_soft_cdr = "on") else ini_dpa_load;
s_deser : stratixiii_lvds_rx_deser
GENERIC MAP (channel_width => channel_width
)
PORT MAP (clk => s_bitslip_clk,
datain => slip_dataout,
devclrn => devclrn,
devpor => devpor,
dataout => deser_dataout
);
output_reg : stratixiii_lvds_rx_parallel_reg
GENERIC MAP ( channel_width => channel_width
)
PORT MAP ( clk => s_bitslip_clk,
enable => rxload,
datain => deser_dataout,
devpor => devpor,
devclrn => devclrn,
dataout => dataout
);
dpa_is_locked <= gnd;
dpaclkout <= dpa_clk_shift;
postdpaserialdataout <= dpa_data_shift ;
serialdataout <= datain_ipd;
divfwdclk <= divfwdclk_tmp ;
END vital_arm_lvds_receiver;
----------------------------------------------------------------------------------
--Module Name: stratixiii_pseudo_diff_out --
--Description: Simulation model for Stratix III Pseudo Differential --
-- Output Buffer --
----------------------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_pseudo_diff_out IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "stratixiii_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END stratixiii_pseudo_diff_out;
ARCHITECTURE arch OF stratixiii_pseudo_diff_out IS
SIGNAL i_ipd : std_logic ;
SIGNAL o_tmp : std_logic ;
SIGNAL obar_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
end block;
PROCESS( i_ipd)
BEGIN
IF (i_ipd = '0') THEN
o_tmp <= '0';
obar_tmp <= '1';
ELSE
IF (i_ipd = '1') THEN
o_tmp <= '1';
obar_tmp <= '0';
ELSE
o_tmp <= i_ipd;
obar_tmp <= i_ipd;
END IF;
END IF;
END PROCESS;
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
--------------------------------------------------------------
--
-- Entity Name : stratixiii_bias_logic
--
-- Description : STRATIXIII Bias Block's Logic Block
-- VHDL simulation model
--
--------------------------------------------------------------
LIBRARY IEEE;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use IEEE.std_logic_1164.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_bias_logic IS
GENERIC (
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
mainclk : out std_logic := '0';
updateclk : out std_logic := '0';
capture : out std_logic := '0';
update : out std_logic := '0'
);
attribute VITAL_LEVEL0 of stratixiii_bias_logic : ENTITY IS TRUE;
end stratixiii_bias_logic;
ARCHITECTURE vital_bias_logic of stratixiii_bias_logic IS
attribute VITAL_LEVEL0 of vital_bias_logic : ARCHITECTURE IS TRUE;
signal clk_ipd : std_logic := '0';
signal shiftnld_ipd : std_logic := '0';
signal captnupdt_ipd : std_logic := '0';
begin
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (shiftnld_ipd, shiftnld, tipd_shiftnld);
VitalWireDelay (captnupdt_ipd, captnupdt, tipd_captnupdt);
end block;
process (clk_ipd, shiftnld_ipd, captnupdt_ipd)
variable select_tmp : std_logic_vector(1 DOWNTO 0) := (others => '0');
begin
select_tmp := captnupdt_ipd & shiftnld_ipd;
case select_tmp IS
when "10"|"11" =>
mainclk <= '0';
updateclk <= clk_ipd;
capture <= '1';
update <= '0';
when "01" =>
mainclk <= '0';
updateclk <= clk_ipd;
capture <= '0';
update <= '0';
when "00" =>
mainclk <= clk_ipd;
updateclk <= '0';
capture <= '0';
update <= '1';
when others =>
mainclk <= '0';
updateclk <= '0';
capture <= '0';
update <= '0';
end case;
end process;
end vital_bias_logic;
--------------------------------------------------------------
--
-- Entity Name : stratixiii_bias_generator
--
-- Description : STRATIXIII Bias Generator VHDL simulation model
--
--------------------------------------------------------------
LIBRARY IEEE;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use IEEE.std_logic_1164.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_bias_generator IS
GENERIC (
tipd_din : VitalDelayType01 := DefPropDelay01;
tipd_mainclk : VitalDelayType01 := DefPropDelay01;
tipd_updateclk : VitalDelayType01 := DefPropDelay01;
tipd_update : VitalDelayType01 := DefPropDelay01;
tipd_capture : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
din : in std_logic := '0';
mainclk : in std_logic := '0';
updateclk : in std_logic := '0';
capture : in std_logic := '0';
update : in std_logic := '0';
dout : out std_logic := '0'
);
attribute VITAL_LEVEL0 of stratixiii_bias_generator : ENTITY IS TRUE;
end stratixiii_bias_generator;
ARCHITECTURE vital_bias_generator of stratixiii_bias_generator IS
attribute VITAL_LEVEL0 of vital_bias_generator : ARCHITECTURE IS TRUE;
CONSTANT TOTAL_REG : integer := 252;
signal din_ipd : std_logic := '0';
signal mainclk_ipd : std_logic := '0';
signal updateclk_ipd : std_logic := '0';
signal update_ipd : std_logic := '0';
signal capture_ipd : std_logic := '0';
signal generator_reg : std_logic_vector((TOTAL_REG - 1) DOWNTO 0) := (others => '0');
signal update_reg : std_logic_vector((TOTAL_REG - 1) DOWNTO 0) := (others => '0');
signal dout_tmp : std_logic := '0';
signal i : integer := 0;
begin
WireDelay : block
begin
VitalWireDelay (din_ipd, din, tipd_din);
VitalWireDelay (mainclk_ipd, mainclk, tipd_mainclk);
VitalWireDelay (updateclk_ipd, updateclk, tipd_updateclk);
VitalWireDelay (update_ipd, update, tipd_update);
VitalWireDelay (capture_ipd, capture, tipd_capture);
end block;
process (mainclk_ipd)
begin
if (mainclk_ipd'event AND (mainclk_ipd = '1') AND (mainclk_ipd'last_value = '0')) then
if ((capture_ipd = '0') AND (update_ipd = '1')) then
for i in 0 to (TOTAL_REG - 1)
loop
generator_reg(i) <= update_reg(i);
end loop;
end if;
end if;
end process;
process (updateclk_ipd)
begin
if (updateclk_ipd'event AND (updateclk_ipd = '1') AND (updateclk_ipd'last_value = '0')) then
dout_tmp <= update_reg(TOTAL_REG - 1);
if ((capture_ipd = '0') AND (update_ipd = '0')) then
for i in 1 to (TOTAL_REG - 1)
loop
update_reg(i) <= update_reg(i - 1);
end loop;
update_reg(0) <= din_ipd;
elsif ((capture_ipd = '1') AND (update_ipd = '0')) then
for i in 1 to (TOTAL_REG - 1)
loop
update_reg(i) <= generator_reg(i);
end loop;
end if;
end if;
end process;
dout <= dout_tmp;
end vital_bias_generator;
--------------------------------------------------------------
--
-- Entity Name : stratixiii_bias_block
--
-- Description : STRATIXIII Bias Block VHDL simulation model
--
--------------------------------------------------------------
LIBRARY IEEE;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use IEEE.std_logic_1164.all;
use work.stratixiii_atom_pack.all;
ENTITY stratixiii_bias_block IS
GENERIC (
lpm_type : string := "stratixiii_bias_block";
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
tipd_din : VitalDelayType01 := DefPropDelay01;
tsetup_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_din_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_shiftnld_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_captnupdt_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_dout_posedge : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
din : in std_logic := '0';
dout : out std_logic := '0'
);
attribute VITAL_LEVEL0 of stratixiii_bias_block : ENTITY IS TRUE;
end stratixiii_bias_block;
ARCHITECTURE vital_bias_block of stratixiii_bias_block IS
COMPONENT stratixiii_bias_logic
GENERIC (
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_shiftnld : VitalDelayType01 := DefPropDelay01;
tipd_captnupdt : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
clk : in std_logic := '0';
shiftnld : in std_logic := '0';
captnupdt : in std_logic := '0';
mainclk : out std_logic := '0';
updateclk : out std_logic := '0';
capture : out std_logic := '0';
update : out std_logic := '0'
);
end COMPONENT;
COMPONENT stratixiii_bias_generator
GENERIC (
tipd_din : VitalDelayType01 := DefPropDelay01;
tipd_mainclk : VitalDelayType01 := DefPropDelay01;
tipd_updateclk : VitalDelayType01 := DefPropDelay01;
tipd_update : VitalDelayType01 := DefPropDelay01;
tipd_capture : VitalDelayType01 := DefPropDelay01;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks
);
PORT (
din : in std_logic := '0';
mainclk : in std_logic := '0';
updateclk : in std_logic := '0';
capture : in std_logic := '0';
update : in std_logic := '0';
dout : out std_logic := '0'
);
end COMPONENT;
signal mainclk_wire : std_logic := '0';
signal updateclk_wire : std_logic := '0';
signal capture_wire : std_logic := '0';
signal update_wire : std_logic := '0';
begin
logic_block : stratixiii_bias_logic
PORT MAP (
clk => clk,
shiftnld => shiftnld,
captnupdt => captnupdt,
mainclk => mainclk_wire,
updateclk => updateclk_wire,
capture => capture_wire,
update => update_wire
);
bias_generator : stratixiii_bias_generator
PORT MAP (
din => din,
mainclk => mainclk_wire,
updateclk => updateclk_wire,
capture => capture_wire,
update => update_wire,
dout => dout
);
end vital_bias_block;
-------------------------------------------------------------------
--
-- Entity Name : stratixiii_tsdblock
--
-- Description : Stratix III TSDBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.stratixiii_atom_pack.all;
entity stratixiii_tsdblock is
generic (
poi_cal_temperature : integer := 85;
clock_divider_enable : string := "on";
clock_divider_value : integer := 40;
sim_tsdcalo : integer := 0;
user_offset_enable : string := "off";
lpm_type : string := "stratixiii_tsdblock"
);
port (
offset : in std_logic_vector(5 downto 0) := (OTHERS => '0');
clk : in std_logic := '0';
ce : in std_logic := '0';
clr : in std_logic := '0';
testin : in std_logic_vector(7 downto 0) := (OTHERS => '0');
tsdcalo : out std_logic_vector(7 downto 0);
tsdcaldone : out std_logic;
fdbkctrlfromcore : in std_logic := '0';
compouttest : in std_logic := '0';
tsdcompout : out std_logic;
offsetout : out std_logic_vector(5 downto 0)
);
end stratixiii_tsdblock;
architecture architecture_tsdblock of stratixiii_tsdblock is
begin
end architecture_tsdblock; -- end of stratixiii_tsdblock
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/srmmu/libmmu.vhd | 1 | 11294 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: leon3
-- File: leon3.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU component declaration
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
package libmmu is
component mmu
generic (
tech : integer range 0 to NTECH := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
mmupgsz : integer range 0 to 5 := 0;
ramcbits : integer := 1
);
port (
rst : in std_logic;
clk : in std_logic;
mmudci : in mmudc_in_type;
mmudco : out mmudc_out_type;
mmuici : in mmuic_in_type;
mmuico : out mmuic_out_type;
mcmmo : in memory_mm_out_type;
mcmmi : out memory_mm_in_type;
ramcclk : in std_ulogic := '0';
ramcin : in std_logic_vector(2*ramcbits-1 downto 0) := (others => '0');
ramcout : out std_logic_vector(2*ramcbits-1 downto 0)
);
end component;
function TLB_CreateCamWrite( two_data : std_logic_vector(31 downto 0);
read : std_logic;
lvl : std_logic_vector(1 downto 0);
ctx : std_logic_vector(M_CTX_SZ-1 downto 0);
vaddr : std_logic_vector(31 downto 0)
) return tlbcam_reg;
procedure TLB_CheckFault( ACC : in std_logic_vector(2 downto 0);
isid : in mmu_idcache;
su : in std_logic;
read : in std_logic;
fault_pro : out std_logic;
fault_pri : out std_logic );
procedure TLB_MergeData( mmupgsz : in integer range 0 to 5;
mmctrl : in mmctrl_type1;
LVL : in std_logic_vector(1 downto 0);
PTE : in std_logic_vector(31 downto 0);
data : in std_logic_vector(31 downto 0);
transdata : out std_logic_vector(31 downto 0));
function TLB_CreateCamTrans( vaddr : std_logic_vector(31 downto 0);
read : std_logic;
ctx : std_logic_vector(M_CTX_SZ-1 downto 0)
) return tlbcam_tfp;
function TLB_CreateCamFlush( data : std_logic_vector(31 downto 0);
ctx : std_logic_vector(M_CTX_SZ-1 downto 0)
) return tlbcam_tfp;
subtype mmu_gpsz_typ is integer range 0 to 3;
function MMU_getpagesize( mmupgsz : in integer range 0 to 4;
mmctrl : in mmctrl_type1
) return mmu_gpsz_typ;
end;
package body libmmu is
procedure TLB_CheckFault( ACC : in std_logic_vector(2 downto 0);
isid : in mmu_idcache;
su : in std_logic;
read : in std_logic;
fault_pro : out std_logic;
fault_pri : out std_logic ) is
variable c_isd : std_logic;
begin
fault_pro := '0';
fault_pri := '0';
-- use '0' == icache '1' == dcache
if isid = id_icache then
c_isd := '0';
else
c_isd := '1';
end if;
--# fault, todo: should we flush on a fault?
case ACC is
when "000" => fault_pro := (not c_isd) or (not read);
when "001" => fault_pro := (not c_isd);
when "010" => fault_pro := (not read);
when "011" => null;
when "100" => fault_pro := (c_isd);
when "101" => fault_pro := (not c_isd) or ((not read) and (not su));
when "110" => fault_pri := (not su);
fault_pro := (not read);
when "111" => fault_pri := (not su);
when others => null;
end case;
end;
procedure TLB_MergeData( mmupgsz : in integer range 0 to 5;
mmctrl : in mmctrl_type1;
LVL : in std_logic_vector(1 downto 0);
PTE : in std_logic_vector(31 downto 0);
data : in std_logic_vector(31 downto 0);
transdata : out std_logic_vector(31 downto 0) ) is
variable pagesize : integer range 0 to 3;
begin
--# merge data
transdata := (others => '0');
pagesize := MMU_getpagesize(mmupgsz, mmctrl);
case pagesize is
when 1 =>
-- 8k
case LVL is
when LVL_PAGE => transdata := PTE(P8K_PTE_PPN32PAG_U downto P8K_PTE_PPN32PAG_D) & data(P8K_VA_OFFPAG_U downto P8K_VA_OFFPAG_D);
when LVL_SEGMENT => transdata := PTE(P8K_PTE_PPN32SEG_U downto P8K_PTE_PPN32SEG_D) & data(P8K_VA_OFFSEG_U downto P8K_VA_OFFSEG_D);
when LVL_REGION => transdata := PTE(P8K_PTE_PPN32REG_U downto P8K_PTE_PPN32REG_D) & data(P8K_VA_OFFREG_U downto P8K_VA_OFFREG_D);
when LVL_CTX => transdata := data(P8K_VA_OFFCTX_U downto P8K_VA_OFFCTX_D);
when others => transdata := (others => 'X');
end case;
when 2 =>
-- 16k
case LVL is
when LVL_PAGE => transdata := PTE(P16K_PTE_PPN32PAG_U downto P16K_PTE_PPN32PAG_D) & data(P16K_VA_OFFPAG_U downto P16K_VA_OFFPAG_D);
when LVL_SEGMENT => transdata := PTE(P16K_PTE_PPN32SEG_U downto P16K_PTE_PPN32SEG_D) & data(P16K_VA_OFFSEG_U downto P16K_VA_OFFSEG_D);
when LVL_REGION => transdata := PTE(P16K_PTE_PPN32REG_U downto P16K_PTE_PPN32REG_D) & data(P16K_VA_OFFREG_U downto P16K_VA_OFFREG_D);
when LVL_CTX => transdata := data(P16K_VA_OFFCTX_U downto P16K_VA_OFFCTX_D);
when others => transdata := (others => 'X');
end case;
when 3 =>
-- 32k
case LVL is
when LVL_PAGE => transdata := PTE(P32K_PTE_PPN32PAG_U downto P32K_PTE_PPN32PAG_D) & data(P32K_VA_OFFPAG_U downto P32K_VA_OFFPAG_D);
when LVL_SEGMENT => transdata := PTE(P32K_PTE_PPN32SEG_U downto P32K_PTE_PPN32SEG_D) & data(P32K_VA_OFFSEG_U downto P32K_VA_OFFSEG_D);
when LVL_REGION => transdata := PTE(P32K_PTE_PPN32REG_U downto P32K_PTE_PPN32REG_D) & data(P32K_VA_OFFREG_U downto P32K_VA_OFFREG_D);
when LVL_CTX => transdata := data(P32K_VA_OFFCTX_U downto P32K_VA_OFFCTX_D);
when others => transdata := (others => 'X');
end case;
when others =>
-- 4k
case LVL is
when LVL_PAGE => transdata := PTE(PTE_PPN32PAG_U downto PTE_PPN32PAG_D) & data(VA_OFFPAG_U downto VA_OFFPAG_D);
when LVL_SEGMENT => transdata := PTE(PTE_PPN32SEG_U downto PTE_PPN32SEG_D) & data(VA_OFFSEG_U downto VA_OFFSEG_D);
when LVL_REGION => transdata := PTE(PTE_PPN32REG_U downto PTE_PPN32REG_D) & data(VA_OFFREG_U downto VA_OFFREG_D);
when LVL_CTX => transdata := data(VA_OFFCTX_U downto VA_OFFCTX_D);
when others => transdata := (others => 'X');
end case;
end case;
end;
function TLB_CreateCamWrite( two_data : std_logic_vector(31 downto 0);
read : std_logic;
lvl : std_logic_vector(1 downto 0);
ctx : std_logic_vector(M_CTX_SZ-1 downto 0);
vaddr : std_logic_vector(31 downto 0)
) return tlbcam_reg is
variable tlbcam_tagwrite : tlbcam_reg;
begin
tlbcam_tagwrite.ET := two_data(PT_ET_U downto PT_ET_D);
tlbcam_tagwrite.ACC := two_data(PTE_ACC_U downto PTE_ACC_D);
tlbcam_tagwrite.M := two_data(PTE_M) or (not read); -- tw : p-update modified
tlbcam_tagwrite.R := '1';
case tlbcam_tagwrite.ACC is -- tw : p-su ACC >= 6
when "110" | "111" => tlbcam_tagwrite.SU := '1';
when others => tlbcam_tagwrite.SU := '0';
end case;
tlbcam_tagwrite.VALID := '1';
tlbcam_tagwrite.LVL := lvl;
tlbcam_tagwrite.I1 := vaddr(VA_I1_U downto VA_I1_D);
tlbcam_tagwrite.I2 := vaddr(VA_I2_U downto VA_I2_D);
tlbcam_tagwrite.I3 := vaddr(VA_I3_U downto VA_I3_D);
tlbcam_tagwrite.CTX := ctx;
tlbcam_tagwrite.PPN := two_data(PTE_PPN_U downto PTE_PPN_D);
tlbcam_tagwrite.C := two_data(PTE_C);
return tlbcam_tagwrite;
end;
function MMU_getpagesize( mmupgsz : in integer range 0 to 4;
mmctrl : in mmctrl_type1
) return mmu_gpsz_typ is
variable pagesize : mmu_gpsz_typ;
begin
if mmupgsz = 4 then pagesize := conv_integer(mmctrl.pagesize); -- variable
else pagesize := mmupgsz; end if;
return pagesize;
end;
function TLB_CreateCamTrans( vaddr : std_logic_vector(31 downto 0);
read : std_logic;
ctx : std_logic_vector(M_CTX_SZ-1 downto 0)
) return tlbcam_tfp is
variable mtag : tlbcam_tfp;
begin
mtag.TYP := (others => '0');
mtag.I1 := vaddr(VA_I1_U downto VA_I1_D);
mtag.I2 := vaddr(VA_I2_U downto VA_I2_D);
mtag.I3 := vaddr(VA_I3_U downto VA_I3_D);
mtag.CTX := ctx;
mtag.M := not (read);
return mtag;
end;
function TLB_CreateCamFlush( data : std_logic_vector(31 downto 0);
ctx : std_logic_vector(M_CTX_SZ-1 downto 0)
) return tlbcam_tfp is
variable ftag : tlbcam_tfp;
begin
ftag.TYP := data(FPTY_U downto FPTY_D);
ftag.I1 := data(FPA_I1_U downto FPA_I1_D);
ftag.I2 := data(FPA_I2_U downto FPA_I2_D);
ftag.I3 := data(FPA_I3_U downto FPA_I3_D);
ftag.CTX := ctx;
ftag.M := '0';
return ftag;
end;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/stratixiii/alt/actrlout.vhd | 3 | 2539 | library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library stratixiii;
use stratixiii.all;
entity actrlout is
generic(
power_up : string := "high"
);
port(
clk : in std_logic;
i : in std_logic;
o : out std_logic
);
end;
architecture rtl of actrlout is
component stratixiii_ddio_out
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
half_rate_mode : string := "false";
use_new_clocking_model : string := "false";
lpm_type : string := "stratixiii_ddio_out"
);
port (
datainlo : in std_logic := '0';
datainhi : in std_logic := '0';
clk : in std_logic := '0';
clkhi : in std_logic := '0';
clklo : in std_logic := '0';
muxsel : in std_logic := '0';
ena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
dataout : out std_logic
-- dfflo : out std_logic;
-- dffhi : out std_logic-- ;
--devclrn : in std_logic := '1';
--devpor : in std_logic := '1'
);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal clk_reg : std_logic;
signal clk_buf, clk_bufn : std_logic;
begin
vcc <= '1'; gnd <= (others => '0');
out_reg0 : stratixiii_ddio_out
generic map(
power_up => power_up,--"high",
async_mode => "none",
sync_mode => "none",
half_rate_mode => "false",
use_new_clocking_model => "false",
lpm_type => "stratixiii_ddio_out"
)
port map(
datainlo => i,
datainhi => i,
clk => clk,
clkhi => clk,
clklo => clk,
muxsel => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => o
-- dfflo => open,
-- dffhi => open--,
--devclrn => vcc,
--devpor => vcc
);
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/maps/iopad_ds.vhd | 1 | 4961 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iopad_ds
-- File: iopad_ds.vhd
-- Author: Nils Johan Wessman - Gaisler Research
-- Description: differential io pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity iopad_ds is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0; term : integer := 0);
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end;
architecture rtl of iopad_ds is
signal oen : std_ulogic;
begin
oen <= not en when oepol /= padoen_polarity(tech) else en;
gen0 : if has_ds_pads(tech) = 0 or
tech = axcel or tech = axdsp or tech = rhlib18t or
tech = ut25 or tech = ut130 generate
padp <= transport i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0' and slew = 0 else i when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(oen)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
padn <= transport not i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0' and slew = 0 else not i when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(oen)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
o <= to_X01(padp)
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
end generate;
xcv : if is_unisim(tech) = 1 generate
x0 : unisim_iopad_ds generic map (level, slew, voltage, strength)
port map (padp, padn, i, oen, o);
end generate;
pa3 : if (tech = apa3) generate
x0 : apa3_iopad_ds generic map (level)
port map (padp, padn, i, oen, o);
end generate;
pa3e : if (tech = apa3e) generate
x0 : apa3e_iopad_ds generic map (level)
port map (padp, padn, i, oen, o);
end generate;
pa3l : if (tech = apa3l) generate
x0 : apa3l_iopad_ds generic map (level)
port map (padp, padn, i, oen, o);
end generate;
fus : if (tech = actfus) generate
x0 : fusion_iopad_ds generic map (level)
port map (padp, padn, i, oen, o);
end generate;
n2x : if (tech = easic45) generate
x0 : n2x_iopad_ds generic map (level, slew, voltage, strength)
port map (padp, padn, i, oen, o);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopad_dsv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp, padn : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of iopad_dsv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad_ds generic map (tech, level, slew, voltage, strength, oepol)
port map (padp(j), padn(j), i(j), en, o(j));
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity iopad_dsvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp, padn : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end;
architecture rtl of iopad_dsvv is
begin
v : for j in width-1 downto 0 generate
x0 : iopad_ds generic map (tech, level, slew, voltage, strength, oepol)
port map (padp(j), padn(j), i(j), en(j), o(j));
end generate;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-nuhorizons-3s1500/leon3mp.vhd | 1 | 24422 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.can.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
pb_sw : in std_logic_vector (4 downto 1); -- push buttons
pll_clk : in std_ulogic; -- PLL clock
led : out std_logic_vector(8 downto 1);
flash_a : out std_logic_vector(20 downto 0);
flash_d : inout std_logic_vector(15 downto 0);
sdram_a : out std_logic_vector(11 downto 0);
sdram_d : inout std_logic_vector(31 downto 0);
sdram_ba : out std_logic_vector(3 downto 0);
sdram_dqm : out std_logic_vector(3 downto 0);
sdram_clk : inout std_ulogic;
sdram_cke : out std_ulogic; -- sdram clock enable
sdram_csn : out std_ulogic; -- sdram chip select
sdram_wen : out std_ulogic; -- sdram write enable
sdram_rasn : out std_ulogic; -- sdram ras
sdram_casn : out std_ulogic; -- sdram cas
uart1_txd : out std_ulogic;
uart1_rxd : in std_ulogic;
uart1_rts : out std_ulogic;
uart1_cts : in std_ulogic;
uart2_txd : out std_ulogic;
uart2_rxd : in std_ulogic;
uart2_rts : out std_ulogic;
uart2_cts : in std_ulogic;
flash_oen : out std_ulogic;
flash_wen : out std_ulogic;
flash_cen : out std_ulogic;
flash_byte : out std_ulogic;
flash_ready : in std_ulogic;
flash_rpn : out std_ulogic;
flash_wpn : out std_ulogic;
phy_mii_data: inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(3 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_tx_data : out std_logic_vector(3 downto 0);
phy_tx_en : out std_ulogic;
phy_mii_clk : out std_ulogic;
phy_100 : in std_ulogic; -- 100 Mbit indicator
phy_rst_n : out std_ulogic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
-- lcd_data : inout std_logic_vector(7 downto 0);
-- lcd_rs : out std_ulogic;
-- lcd_rw : out std_ulogic;
-- lcd_en : out std_ulogic;
-- lcd_backl : out std_ulogic;
can_txd : out std_ulogic;
can_rxd : in std_ulogic;
smsc_addr : out std_logic_vector(14 downto 0);
smsc_data : inout std_logic_vector(31 downto 0);
smsc_nbe : out std_logic_vector(3 downto 0);
smsc_resetn : out std_ulogic;
smsc_ardy : in std_ulogic;
-- smsc_intr : in std_ulogic;
smsc_nldev : in std_ulogic;
smsc_nrd : out std_ulogic;
smsc_nwr : out std_ulogic;
smsc_ncs : out std_ulogic;
smsc_aen : out std_ulogic;
smsc_lclk : out std_ulogic;
smsc_wnr : out std_ulogic;
smsc_rdyrtn : out std_ulogic;
smsc_cycle : out std_ulogic;
smsc_nads : out std_ulogic
);
end;
architecture rtl of leon3mp is
signal vcc, gnd : std_logic_vector(7 downto 0);
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, sdclkl : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal can_lrx, can_ltx : std_ulogic;
signal lclk, pci_lclk, sdfb : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal resetn : std_ulogic;
signal pbsw : std_logic_vector(4 downto 1);
signal ledo : std_logic_vector(8 downto 1);
signal memi : memory_in_type;
signal memo : memory_out_type;
--for smc lan chip
signal s_eth_aen : std_logic;
signal s_eth_readn : std_logic;
signal s_eth_writen: std_logic;
signal s_eth_nbe : std_logic_vector(3 downto 0);
signal s_eth_din : std_logic_vector(31 downto 0);
constant ahbmmax : integer := CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+ CFG_GRETH;
constant BOARD_FREQ : integer := 50000; -- board frequency in KHz
constant CPU_FREQ : integer := (BOARD_FREQ*CFG_CLKMUL)/CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
sdram_clk_pad : skew_outpad
generic map (tech => padtech, slew => 1, strength => 24, skew => -60)
port map (sdram_clk, sdclkl, rstn);
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
resetn <= pbsw(4);
ledo(2) <= not cgo.clklock;
ledo(3) <= pbsw(3);
clk_pad : clkpad generic map (tech => padtech) port map (pll_clk, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, pci_lclk, clkm, open, open, sdclkl, pciclk, cgi, cgo);
rst0 : rstgen -- reset generator
port map (resetn, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
nahbm => ahbmmax, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
ledo(8) <= dbgo(0).error;
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1'; dsui.break <= pbsw(1); ledo(1) <= not dsuo.active;
end generate;
end generate;
nodcom : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dui.rxd <= u2i.rxd; u2o.txd <= duo.txd; u2o.rtsn <= gnd(0);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- PROM/SDRAM Memory controller ------------------------------------
----------------------------------------------------------------------
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111";
memi.bwidth <= "00" when CFG_MCTRL_RAM16BIT = 0 else "01";
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : entity work.smc_mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4+CFG_MCTRL_5CS, sden => CFG_MCTRL_SDEN,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS,
sdbits => 32 + 32*CFG_MCTRL_SD64)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0),
wpo, sdo, s_eth_aen, s_eth_readn, s_eth_writen, s_eth_nbe, s_eth_din);
addr_pad : outpadv generic map (width => 21, tech => padtech)
port map (flash_a(20 downto 0), memo.address(21 downto 1));
roms_pad : outpad generic map (tech => padtech)
port map (flash_cen, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (flash_oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (flash_wen, memo.writen);
rom8 : if CFG_MCTRL_RAM16BIT = 0 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (flash_d(7 downto 0), memo.data(31 downto 24),
memo.bdrive(0), memi.data(31 downto 24));
data15_pad : iopad generic map (tech => padtech)
port map (flash_d(15), memo.address(0), gnd(0), open);
end generate;
rom16 : if CFG_MCTRL_RAM16BIT = 1 generate
data_pad : iopadv generic map (tech => padtech, width => 16)
port map (flash_d(15 downto 0), memo.data(31 downto 16),
memo.bdrive(0), memi.data(31 downto 16));
end generate;
sa_pad : outpadv generic map (width => 12, tech => padtech)
port map (sdram_a, memo.sa(11 downto 0));
sba1_pad : outpadv generic map (width => 2, tech => padtech)
port map (sdram_ba(1 downto 0), memo.sa(14 downto 13));
sba2_pad : outpadv generic map (width => 2, tech => padtech)
port map (sdram_ba(3 downto 2), memo.sa(14 downto 13));
bdr : for i in 0 to 3 generate
sd_pad : iopadv generic map (tech => padtech, width => 8)
port map (sdram_d(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.sd(31-i*8 downto 24-i*8));
end generate;
sdcke_pad : outpad generic map (tech => padtech)
port map (sdram_cke, sdo.sdcke(0));
sdwen_pad : outpad generic map (tech => padtech)
port map (sdram_wen, sdo.sdwen);
sdcsn_pad : outpad generic map (tech => padtech)
port map (sdram_csn, sdo.sdcsn(0));
sdras_pad : outpad generic map (tech => padtech)
port map (sdram_rasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdram_casn, sdo.casn);
sddqm_pad : outpadv generic map (width => 4, tech => padtech)
port map (sdram_dqm, sdo.dqm(3 downto 0));
end generate;
nosd0 : if (CFG_MCTRL_SDEN = 0) generate -- no SDRAM controller
sdcke_pad : outpad generic map (tech => padtech)
port map (sdram_cke, gnd(0));
sdcsn_pad : outpad generic map (tech => padtech)
port map (sdram_csn, vcc(0));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 4, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(4));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(4) <= ahbs_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua1rx_pad : inpad generic map (tech => padtech) port map (uart1_rxd, u1i.rxd);
ua1tx_pad : outpad generic map (tech => padtech) port map (uart1_txd, u1o.txd);
ua1cts_pad : inpad generic map (tech => padtech) port map (uart1_cts, u1i.ctsn);
ua1rts_pad : outpad generic map (tech => padtech) port map (uart1_rts, u1o.rtsn);
ua2 : if (CFG_UART2_ENABLE /= 0) and (CFG_AHB_UART = 0) generate
uart2 : apbuart -- UART 2
generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
u2i.extclk <= '0';
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
ua2rx_pad : inpad generic map (tech => padtech) port map (uart2_rxd, u2i.rxd);
ua2tx_pad : outpad generic map (tech => padtech) port map (uart2_txd, u2o.txd);
ua2cts_pad : inpad generic map (tech => padtech) port map (uart2_cts, u2i.ctsn);
ua2rts_pad : outpad generic map (tech => padtech) port map (uart2_rts, u2o.rtsn);
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(15), ethi => ethi, etho => etho);
end generate;
ethpads : if CFG_GRETH = 0 generate -- no eth
etho <= eth_out_none;
end generate;
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 0)
port map (phy_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 0)
port map (phy_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (phy_rx_data, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (phy_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (phy_tx_data, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( phy_tx_en, etho.tx_en);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, etho.mdc);
ereset_pad : outpad generic map (tech => padtech)
port map (phy_rst_n, rstn);
-----------------------------------------------------------------------
--- CAN --------------------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_oc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech)
port map (rstn, clkm, ahbsi, ahbso(6), can_lrx, can_ltx );
end generate;
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
can_loopback : if CFG_CANLOOP = 1 generate
can_lrx <= can_ltx;
end generate;
can_pads : if CFG_CANLOOP = 0 generate
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd, can_ltx);
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd, can_lrx);
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- I/O interface ---------------------------------------------------
-----------------------------------------------------------------------
pb_sw_pad : inpadv generic map (width => 4, tech => padtech)
port map (pb_sw, pbsw);
led_pad : outpadv generic map (width => 8, tech => padtech)
port map (led, ledo);
rom8 : if CFG_MCTRL_RAM16BIT = 0 generate
byte_pad : outpad generic map (tech => padtech) port map (flash_byte, gnd(0));
end generate;
rom16 : if CFG_MCTRL_RAM16BIT = 1 generate
byte_pad : outpad generic map (tech => padtech) port map (flash_byte, vcc(0));
end generate;
rpn_pad : outpad generic map (tech => padtech) port map (flash_rpn, rstn);
wpn_pad : outpad generic map (tech => padtech) port map (flash_wpn, vcc(0));
ready_pad : inpad generic map (tech => padtech) port map (flash_ready, open);
smsc_data_pads : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (smsc_data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), s_eth_din(31-i*8 downto 24-i*8));
end generate;
smsc_addr_pad : outpadv generic map (tech => padtech, width => 15)
port map (smsc_addr, memo.address(15 downto 1));
smsc_nbe_pad : outpadv generic map (tech => padtech, width => 4)
port map (smsc_nbe, s_eth_nbe);
smsc_reset_pad : outpad generic map (tech => padtech)
port map (smsc_resetn, rstn);
smsc_nrd_pad : outpad generic map (tech => padtech)
port map (smsc_nrd, s_eth_readn);
smsc_nwr_pad : outpad generic map (tech => padtech)
port map (smsc_nwr, s_eth_writen);
smsc_ncs_pad : outpad generic map (tech => padtech)
port map (smsc_ncs, memo.iosn);
smsc_aen_pad : outpad generic map (tech => padtech)
port map (smsc_aen, s_eth_aen);
smsc_lclk_pad : outpad generic map (tech => padtech)
port map (smsc_lclk, vcc(0));
smsc_wnr_pad : outpad generic map (tech => padtech)
port map (smsc_wnr, vcc(0));
smsc_rdyrtn_pad : outpad generic map (tech => padtech)
port map (smsc_rdyrtn, vcc(0));
smsc_cycle_pad : outpad generic map (tech => padtech)
port map (smsc_cycle, vcc(0));
smsc_nads_pad : outpad generic map (tech => padtech)
port map (smsc_nads, gnd(0));
-- lcd_data_pad : iopadv generic map (width => 8, tech => padtech)
-- port map (lcd_data, nuo.lcd_data, nuo.lcd_ben, nui.lcd_data);
-- lcd_rs_pad : outpad generic map (tech => padtech)
-- port map (lcd_rs, nuo.lcd_rs);
-- lcd_rw_pad : outpad generic map (tech => padtech)
-- port map (lcd_rw, nuo.lcd_rw );
-- lcd_en_pad : outpad generic map (tech => padtech)
-- port map (lcd_en, nuo.lcd_en);
-- lcd_backl_pad : outpad generic map (tech => padtech)
-- port map (lcd_backl, nuo.lcd_backl);
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1-CFG_GRETH generate apbo(i) <= apb_none; end generate;
apbo(6) <= apb_none;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Nuhorizon SP3 board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/pci/pcitrace/pcitrace.in.vhd | 6 | 131 | -- PCI trace buffer
constant CFG_PCITBUFEN: integer := CONFIG_PCI_TRACE;
constant CFG_PCITBUF : integer := CFG_PCI_TRACEBUF;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-digilent-xc7z020/config.vhd | 1 | 5090 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := zynq7000;
constant CFG_MEMTECH : integer := zynq7000;
constant CFG_PADTECH : integer := zynq7000;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := zynq7000;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (32);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (2);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 4;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 1 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 1;
constant CFG_ATBSZ : integer := 1;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 0;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- AHB status register
constant CFG_AHBSTAT : integer := 0;
constant CFG_AHBSTATN : integer := 1;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 1;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 0;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (16);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-altera-ep2sgx90-av/sram32.vhd | 1 | 2686 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sram32
-- File: sram32.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Simulation model of generic 32-bit async SRAM
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library gaisler;
use gaisler.sim.all;
library grlib;
use grlib.stdlib.all;
entity sram32 is
generic (
index : integer := 0; -- Byte lane (0 - 3)
abits: Positive := 10; -- Default 10 address bits (1Kx32)
echk : integer := 0; -- Generate EDAC checksum
tacc : integer := 10; -- access time (ns)
fname : string := "ram.dat"); -- File to read from
port (
a : in std_logic_vector(abits-1 downto 0);
d : inout std_logic_vector(31 downto 0);
lb : in std_logic;
ub : in std_logic;
ce : in std_logic;
we : in std_ulogic;
oe : in std_ulogic);
end;
architecture sim of sram32 is
signal cex : std_logic_vector(0 to 1);
begin
cex(0) <= ce or lb; cex(1) <= ce or ub;
sr0 : sram generic map (index+3, abits, tacc, fname)
port map (a, d(7 downto 0), cex(0), we, oe);
sr1 : sram generic map (index+2, abits, tacc, fname)
port map (a, d(15 downto 8), cex(1), we, oe);
sr2 : sram generic map (index+1, abits, tacc, fname)
port map (a, d(23 downto 16), cex(1), we, oe);
sr3 : sram generic map (index, abits, tacc, fname)
port map (a, d(31 downto 24), cex(1), we, oe);
end sim;
-- pragma translate_on
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-gr-xc6s/leon3mp.vhd | 1 | 47744 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2011 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.i2c.all;
use gaisler.can.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
-- pragma translate_off
use gaisler.sim.all;
library unisim;
use unisim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic; -- 50 MHz main clock
clk2 : in std_ulogic; -- User clock
clk125 : in std_ulogic; -- 125 MHz clock from PHY
wdogn : out std_ulogic;
address : out std_logic_vector(24 downto 0);
data : inout std_logic_vector(31 downto 24);
oen : out std_ulogic;
writen : out std_ulogic;
romsn : out std_logic;
ddr_clk : out std_logic;
ddr_clkb : out std_logic;
ddr_cke : out std_logic;
ddr_odt : out std_logic;
ddr_we : out std_ulogic; -- ddr write enable
ddr_ras : out std_ulogic; -- ddr ras
ddr_csn : out std_ulogic; -- ddr csn
ddr_cas : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (1 downto 0); -- ddr dqs n
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (2 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (15 downto 0); -- ddr data
ddr_rzq : inout std_ulogic;
ddr_zio : inout std_ulogic;
-- dsuen : in std_ulogic; -- dip swtich 7
-- dsubre : in std_ulogic; -- switch 9
-- dsuact : out std_ulogic; -- led (0)
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
ctsn1 : in std_ulogic; -- UART1 ctsn
rtsn1 : out std_ulogic; -- UART1 trsn
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
ctsn2 : in std_ulogic; -- UART2 ctsn
rtsn2 : out std_ulogic; -- UART2 rtsn
pio : inout std_logic_vector(17 downto 0); -- I/O port
genio : inout std_logic_vector(59 downto 0); -- I/O port
switch : in std_logic_vector(9 downto 0); -- I/O port
led : out std_logic_vector(3 downto 0); -- I/O port
erx_clk : in std_ulogic;
emdio : inout std_logic; -- ethernet PHY interface
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
emdint : in std_ulogic;
etx_clk : out std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
emdc : out std_ulogic;
ps2clk : inout std_logic_vector(1 downto 0);
ps2data : inout std_logic_vector(1 downto 0);
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
ddc_scl : inout std_ulogic;
ddc_sda : inout std_ulogic;
dvi_iic_scl : inout std_logic;
dvi_iic_sda : inout std_logic;
tft_lcd_data : out std_logic_vector(11 downto 0);
tft_lcd_clk_p : out std_ulogic;
tft_lcd_clk_n : out std_ulogic;
tft_lcd_hsync : out std_ulogic;
tft_lcd_vsync : out std_ulogic;
tft_lcd_de : out std_ulogic;
tft_lcd_reset_b : out std_ulogic;
spw_clk : in std_ulogic;
spw_rxdp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxdn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsp : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxsn : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txdn : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsp : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txsn : out std_logic_vector(0 to CFG_SPW_NUM-1);
-- SPI flash
spi_sel_n : inout std_ulogic;
spi_clk : out std_ulogic;
spi_mosi : out std_ulogic
-- SD Card interface (SD SPI interface)
-- sdata : inout std_ulogic_vector(3 downto 0);
-- sd_clk : out std_ulogic;
-- spi_cmd : out std_ulogic;
-- sd_prot : in std_logic;
-- sd_detect : in std_logic
);
end;
architecture rtl of leon3mp is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component IODELAY2
generic (
COUNTER_WRAPAROUND : string := "WRAPAROUND";
DATA_RATE : string := "SDR";
DELAY_SRC : string := "IO";
IDELAY2_VALUE : integer := 0;
IDELAY_MODE : string := "NORMAL";
IDELAY_TYPE : string := "DEFAULT";
IDELAY_VALUE : integer := 0;
ODELAY_VALUE : integer := 0;
SERDES_MODE : string := "NONE";
SIM_TAPDELAY_VALUE : integer := 75
);
port (
BUSY : out std_ulogic;
DATAOUT : out std_ulogic;
DATAOUT2 : out std_ulogic;
DOUT : out std_ulogic;
TOUT : out std_ulogic;
CAL : in std_ulogic;
CE : in std_ulogic;
CLK : in std_ulogic;
IDATAIN : in std_ulogic;
INC : in std_ulogic;
IOCLK0 : in std_ulogic;
IOCLK1 : in std_ulogic;
ODATAIN : in std_ulogic;
RST : in std_ulogic;
T : in std_ulogic
);
end component;
attribute syn_netlist_hierarchy : boolean;
attribute syn_netlist_hierarchy of rtl : architecture is false;
constant use_eth_input_delay : integer := 1;
constant use_eth_output_delay : integer := 1;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_GRETH+
CFG_AHB_JTAG+CFG_SPW_NUM*CFG_SPW_EN;
signal vcc, gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal leds : std_logic_vector(3 downto 0); -- I/O port
signal apbi, apbi2 : apb_slv_in_type;
signal apbo, apbo2 : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal vahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal vahbmo : ahb_mst_out_type;
signal clkm, rstn, rstraw, sdclkl : std_ulogic;
signal clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2, cgi3 : clkgen_in_type;
signal cgo, cgo2, cgo3 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gmiii, rgmiii, rgmiii_buf : eth_in_type;
signal gmiio, rgmiio : eth_out_type;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal gpioi2 : gpio_in_type;
signal gpioo2 : gpio_out_type;
signal gpioi3 : gpio_in_type;
signal gpioo3 : gpio_out_type;
signal can_lrx, can_ltx : std_logic_vector(0 to 7);
signal lock, calib_done, clkml, lclk, rst, ndsuact, wdogl : std_ulogic := '0';
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ethclk, ddr2clk : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal spmi2 : spimctrl_in_type;
signal spmo2 : spimctrl_out_type;
constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant IOAEN : integer := CFG_CAN;
constant DDR2_FREQ : integer := 200000; -- DDR2 input frequency in KHz
signal spwi : grspw_in_type_vector(0 to CFG_SPW_NUM-1);
signal spwo : grspw_out_type_vector(0 to CFG_SPW_NUM-1);
signal dtmp : std_logic_vector(CFG_SPW_NUM*CFG_SPW_PORTS-1 downto 0);
signal stmp : std_logic_vector(CFG_SPW_NUM*CFG_SPW_PORTS-1 downto 0);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM*CFG_SPW_PORTS);
signal spw_rstn : std_ulogic;
signal spw_rstn_sync : std_ulogic;
signal stati : ahbstat_in_type;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
signal rstgtxn : std_logic;
signal idelay_reset_cnt : std_logic_vector(3 downto 0);
signal idelay_cal_cnt : std_logic_vector(3 downto 0);
signal idelayctrl_reset : std_logic;
signal idelayctrl_cal : std_logic;
signal rgmiii_rx_clk_n : std_logic;
signal rgmiii_rx_clk_n_buf : std_logic;
signal rgmiio_tx_clk,rgmiio_tx_en : std_logic;
signal rgmiio_txd : std_logic_vector(3 downto 0);
-- Used for connecting input/output signals to the DDR2 controller
signal core_ddr_clk : std_logic_vector(2 downto 0);
signal core_ddr_clkb : std_logic_vector(2 downto 0);
signal core_ddr_cke : std_logic_vector(1 downto 0);
signal core_ddr_csb : std_logic_vector(1 downto 0);
signal core_ddr_ad : std_logic_vector(13 downto 0);
signal core_ddr_odt : std_logic_vector(1 downto 0);
constant SPW_LOOP_BACK : integer := 0;
signal video_clk, clk50, clk100, spw100 : std_logic; -- signals to vga_clkgen.
signal clk_sel : std_logic_vector(1 downto 0);
signal clkvga, clkvga_p, clkvga_n : std_ulogic;
signal clk_125 : std_ulogic;
signal nerror : std_ulogic;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clk50 : signal is true;
attribute syn_preserve of clk50 : signal is true;
attribute keep of clk50 : signal is true;
attribute syn_keep of video_clk : signal is true;
attribute syn_preserve of video_clk : signal is true;
attribute keep of video_clk : signal is true;
attribute syn_preserve of ddr2clk : signal is true;
attribute keep of ddr2clk : signal is true;
attribute syn_keep of ddr2clk : signal is true;
attribute syn_preserve of spw100 : signal is true;
attribute keep of spw100 : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of clkm : signal is true;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1'; gnd <= '0';
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
ddr2clk <= lclk;
ethclk <= lclk;
no_clk_mig : if CFG_MIG_DDR2 = 0 generate
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo, open, clk50, clk100);
rst0 : rstgen -- reset generator
generic map(syncin => 1)
port map (rst, clkm, lock, rstn, rstraw);
end generate;
clk_mig : if CFG_MIG_DDR2 = 1 generate
clk50 <= clkm;
rstraw <= rst;
cgo.clklock <= '1';
end generate;
resetn_pad : inpad generic map (tech => padtech) port map (resetn, rst);
lock <= cgo.clklock and calib_done;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 16)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
nosh : if CFG_GRFPUSH = 0 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ft -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm);
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ftsh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm, fpi(i), fpo(i));
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
nerror <= dbgo(0).error;
led1_pad : odpad generic map (tech => padtech) port map (led(1), nerror);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (switch(7), dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (switch(8), dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (led(0), ndsuact);
ndsuact <= not dsuo.active;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; ahbso(2) <= ahbs_none;
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (rxd2, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (txd2, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
memi.brdyn <= '0'; memi.bexcn <= '1';
mctrl0 : if CFG_MCTRL_LEON2 /= 0 generate
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS,
pageburst => CFG_MCTRL_PAGE, rammask => 0, iomask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 25, tech => padtech)
port map (address, memo.address(24 downto 0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
bdr : for i in 0 to 0 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
nomctrl : if CFG_MCTRL_LEON2 = 0 generate
romsn <= '1'; ahbso(0) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 6, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(6));
-- pragma translate_on
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
ddr_csn <= '0';
mig_gen : if (CFG_MIG_DDR2 = 1) generate
ddrc : entity work.ahb2mig_grxc6s_2p
generic map(
hindex => 4, haddr => 16#400#, hmask => 16#F80#,
pindex => 0, paddr => 0, vgamst => CFG_SVGA_ENABLE, vgaburst => 64,
clkdiv => 10)
port map(
mcb3_dram_dq => ddr_dq,
mcb3_dram_a => ddr_ad,
mcb3_dram_ba => ddr_ba,
mcb3_dram_ras_n => ddr_ras,
mcb3_dram_cas_n => ddr_cas,
mcb3_dram_we_n => ddr_we,
mcb3_dram_odt => ddr_odt,
mcb3_dram_cke => ddr_cke,
mcb3_dram_dm => ddr_dm(0),
mcb3_dram_udqs => ddr_dqs(1),
mcb3_dram_udqs_n => ddr_dqsn(1),
mcb3_rzq => ddr_rzq,
mcb3_zio => ddr_zio,
mcb3_dram_udm => ddr_dm(1),
mcb3_dram_dqs => ddr_dqs(0),
mcb3_dram_dqs_n => ddr_dqsn(0),
mcb3_dram_ck => ddr_clk,
mcb3_dram_ck_n => ddr_clkb,
ahbsi => ahbsi,
ahbso => ahbso(4),
ahbmi => vahbmi,
ahbmo => vahbmo,
apbi => apbi2,
apbo => apbo2(0),
calib_done => calib_done,
rst_n_syn => rstn,
rst_n_async => rstraw,
clk_amba => clkm,
clk_mem_n => ddr2clk,
clk_mem_p => ddr2clk,
test_error => open,
clk_125 => clk_125,
clk_100 => clk100
);
end generate;
noddr : if (CFG_DDR2SP+CFG_MIG_DDR2) = 0 generate calib_done <= '1'; end generate;
----------------------------------------------------------------------
--- SPI Memory Controller--------------------------------------------
----------------------------------------------------------------------
spimc: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 1 generate
spimctrl0 : spimctrl -- SPI Memory Controller
generic map (hindex => 3, hirq => 7, faddr => 16#e00#, fmask => 16#ff8#,
ioaddr => 16#002#, iomask => 16#fff#,
spliten => CFG_SPLIT, oepol => 0,
sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER,
pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
port map (rstn, clkm, ahbsi, ahbso(3), spmi, spmo);
-- MISO is shared with Flash data 0
spmi.miso <= memi.data(24);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, spmo.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, spmo.sck);
slvsel0_pad : odpad generic map (tech => padtech)
port map (spi_sel_n, spmo.csn);
end generate;
nospimc: if ((CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 0) or
(CFG_SPICTRL_ENABLE = 1 and CFG_SPIMCTRL = 1) or
(CFG_SPICTRL_ENABLE = 1 and CFG_SPIMCTRL = 0))generate
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, '0');
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, '0');
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
apb1 : apbctrl -- AHB/APB bridge
generic map (hindex => 13, haddr => CFG_APBADDR+1, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(13), apbi2, apbo2 );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
cts1_pad : inpad generic map (tech => padtech) port map (ctsn1, u1i.ctsn);
rts1_pad : outpad generic map (tech => padtech) port map (rtsn1, u1o.rtsn);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
rts1_pad : outpad generic map (tech => padtech) port map (rtsn2, '0');
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
wden : if CFG_GPT_WDOGEN /= 0 generate
wdogl <= gpto.wdogn or not rstn;
wdogn_pad : odpad generic map (tech => padtech) port map (wdogn, wdogl);
end generate;
wddis : if CFG_GPT_WDOGEN = 0 generate
wdogn_pad : odpad generic map (tech => padtech) port map (wdogn, vcc);
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate
apbo(4) <= apb_none; mouo <= ps2o_none;
apbo(5) <= apb_none; kbdo <= ps2o_none;
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(1),kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2data(1), kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2clk(0),mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2data(0), mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
video_clk <= not ethclk;
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 20000, clk1 => 0, --1000000000/((BOARD_FREQ * CFG_CLKMUL)/CFG_CLKDIV),
clk2 => 0, clk3 => 0, burstlen => 6)
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao, vahbmi,
vahbmo, clk_sel);
end generate;
--b0 : techbuf generic map (2, fabtech) port map (clk50, video_clk);
video_clk <= clk50;
vgadvi : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
dvi0 : entity work.svga2ch7301c generic map (tech => fabtech, dynamic => 1)
port map (clkm, vgao, video_clk, clkvga_p, clkvga_n,
lcd_datal, lcd_hsyncl, lcd_vsyncl, lcd_del);
i2cdvi : i2cmst
generic map (pindex => 9, paddr => 9, pmask => 16#FFF#, pirq => 3)
port map (rstn, clkm, apbi, apbo(9), dvi_i2ci, dvi_i2co);
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
tft_lcd_data_pad : outpadv generic map (width => 12, tech => padtech)
port map (tft_lcd_data, lcd_datal);
tft_lcd_clkp_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_p, clkvga_p);
tft_lcd_clkn_pad : outpad generic map (tech => padtech)
port map (tft_lcd_clk_n, clkvga_n);
tft_lcd_hsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_hsync, lcd_hsyncl);
tft_lcd_vsync_pad : outpad generic map (tech => padtech)
port map (tft_lcd_vsync, lcd_vsyncl);
tft_lcd_de_pad : outpad generic map (tech => padtech)
port map (tft_lcd_de, lcd_del);
tft_lcd_reset_pad : outpad generic map (tech => padtech)
port map (tft_lcd_reset_b, rstn);
dvi_i2c_scl_pad : iopad generic map (tech => padtech)
port map (dvi_iic_scl, dvi_i2co.scl, dvi_i2co.scloen, dvi_i2ci.scl);
dvi_i2c_sda_pad : iopad generic map (tech => padtech)
port map (dvi_iic_sda, dvi_i2co.sda, dvi_i2co.sdaoen, dvi_i2ci.sda);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 10, paddr => 10, imask => CFG_GRGPIO_IMASK, nbits => 16)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(10),
gpioi => gpioi, gpioo => gpioo);
p0 : if (CFG_CAN = 0) or (CFG_CAN_NUM = 1) generate
pio_pads : for i in 1 to 2 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
p1 : if (CFG_CAN = 0) generate
pio_pads : for i in 4 to 5 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
pio_pad0 : iopad generic map (tech => padtech)
port map (pio(0), gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
pio_pad1 : iopad generic map (tech => padtech)
port map (pio(3), gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
pio_pads : for i in 6 to 15 generate
pio_pad : iopad generic map (tech => padtech)
port map (pio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-- make an additonal 32 bit GPIO port for genio(31..0)
gpio1 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio1: grgpio
generic map(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 32)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(11),
gpioi => gpioi2, gpioo => gpioo2);
pio_pads : for i in 0 to 31 generate
pio_pad : iopad generic map (tech => padtech)
port map (genio(i), gpioo2.dout(i), gpioo2.oen(i), gpioi2.din(i));
end generate;
end generate;
gpio2 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio2: grgpio
generic map(pindex => 12, paddr => 12, imask => CFG_GRGPIO_IMASK, nbits => 28)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(12),
gpioi => gpioi3, gpioo => gpioo3);
pio_pads : for i in 0 to 27 generate
pio_pad : iopad generic map (tech => padtech)
port map (genio(i+32), gpioo3.dout(i), gpioo3.oen(i), gpioi3.din(i));
end generate;
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 13, paddr => 13, pirq => 1,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(13));
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 14, paddr => 14, pirq => 6, memtech => memtech,
mdcscaler => CPU_FREQ/1000, rmii => 0, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, phyrstadr => 1,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(14), ethi => gmiii, etho => gmiio);
end generate;
led(3 downto 2) <= not (gmiio.gbit & gmiio.speed);
noethindelay0 : if (use_eth_input_delay = 0) generate
rgmiii.rx_dv <= rgmiii_buf.rx_dv;
rgmiii.rxd <= rgmiii_buf.rxd;
end generate;
noethoutdelay0 : if (use_eth_output_delay = 0) generate
rgmiio_tx_clk <= rgmiio.tx_clk;
rgmiio_tx_en <= rgmiio.tx_en;
rgmiio_txd <= rgmiio.txd(3 downto 0);
end generate;
ethindelay0 : if (use_eth_input_delay /= 0) generate
delay_rgmii_rx_ctl0 : IODELAY2 generic map(
DELAY_SRC => "IDATAIN",
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 16 -- Delay (256/8)*424ps*30% + n/8*424ps + Ttap(See table 39 in Xilinx ds162.pdf)
)
port map(
IDATAIN => rgmiii_buf.rx_dv,
T => '1',
ODATAIN => '0',
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => rgmiii.rx_dv,
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => OPEN
);
rgmii_rxd : for i in 0 to 3 generate
delay_rgmii_rxd0 : IODELAY2 generic map(
DELAY_SRC => "IDATAIN",
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 16 -- Delay (256/8)*424ps*30% + n/8*424ps + Ttap(See table 39 in Xilinx ds162.pdf)
)
port map(
IDATAIN => rgmiii_buf.rxd(i),
T => '1',
ODATAIN => '0',
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => rgmiii.rxd(i),
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => OPEN
);
end generate;
end generate;
ethoutdelay0 : if (use_eth_output_delay /= 0) generate
delay_rgmii_tx_clk0 : IODELAY2 generic map(
DELAY_SRC => "ODATAIN",
IDELAY_TYPE => "FIXED",
ODELAY_VALUE => 16 -- Delay (256/8)*424ps*30% + n/8*424ps + Ttap(See table 39 in Xilinx ds162.pdf)
)
port map(
IDATAIN => '0',
T => '1',
ODATAIN => rgmiio.tx_clk,
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => OPEN,
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => rgmiio_tx_clk
);
delay_rgmii_tx_en0 : IODELAY2 generic map(
DELAY_SRC => "ODATAIN",
IDELAY_TYPE => "FIXED",
ODELAY_VALUE => 0
)
port map(
IDATAIN => '0',
T => '1',
ODATAIN => rgmiio.tx_en,
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => OPEN,
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => rgmiio_tx_en
);
rgmii_txd : for i in 0 to 3 generate
delay_rgmii_txd0 : IODELAY2 generic map(
DELAY_SRC => "ODATAIN",
IDELAY_TYPE => "FIXED",
ODELAY_VALUE => 0
)
port map(
IDATAIN => '0',
T => '1',
ODATAIN => rgmiio.txd(i),
CAL => '0',
IOCLK0 => '0',
IOCLK1 => '0',
CLK => '0',
INC => '0',
CE => '0',
RST => '0',
BUSY => OPEN,
DATAOUT => OPEN,
DATAOUT2 => OPEN,
TOUT => OPEN,
DOUT => rgmiio_txd(i)
);
end generate;
end generate;
rgmii0 : rgmii generic map (15, 16#010# , 16#ff0#, fabtech, CFG_GRETH1G, 1, 0, 1)
port map (rstn, rgmiii.gtx_clk, gmiii, gmiio, rgmiii, rgmiio, clkm, rstn, apbi, apbo(15));
ethpads : if (CFG_GRETH = 1) generate -- eth pads
etxc_pad : outpad generic map (tech => padtech)
port map (etx_clk, rgmiio_tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, rgmiii.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, rgmiii_buf.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, rgmiii_buf.rx_dv);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, rgmiio_txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, rgmiio_tx_en);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, rgmiio.mdio_o, rgmiio.mdio_oe, rgmiii.mdio_i);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, rgmiio.mdc);
emdint_pad : inpad generic map (tech => padtech)
port map (emdint, rgmiii.mdint);
-- Incoming 125Mhz ref clock
clk125_pad : clkpad generic map (tech => padtech, arch => 2)
port map (clk125, rgmiii.gtx_clk);
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- Multi-core CAN ---------------------------------------------------
-----------------------------------------------------------------------
can0 : if CFG_CAN = 1 generate
can0 : can_mc generic map (slvndx => 4, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech,
ncores => CFG_CAN_NUM, sepirq => CFG_CANSEPIRQ)
port map (rstn, clkm, ahbsi, ahbso(4), can_lrx, can_ltx );
can_tx_pad1 : iopad generic map (tech => padtech)
port map (pio(5), can_ltx(0), gnd, gpioi.din(5));
can_rx_pad1 : iopad generic map (tech => padtech)
port map (pio(4), gnd, vcc, can_lrx(0));
canpas : if CFG_CAN_NUM = 2 generate
can_tx_pad2 : iopad generic map (tech => padtech)
port map (pio(2), can_ltx(1), gnd, gpioi.din(2));
can_rx_pad2 : iopad generic map (tech => padtech)
port map (pio(1), gnd, vcc, can_lrx(1));
end generate;
end generate;
-- standby controlled by pio(3) and pio(0)
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
-- temporary, just to make sure the SPW pins are instantiated correctly
no_spw : if CFG_SPW_EN = 0 generate
pad_gen: for i in 0 to CFG_SPW_NUM-1 generate
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x33v)
port map (spw_rxdp(i), spw_rxdn(i), dtmp(i));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x33v)
port map (spw_rxsp(i), spw_rxsn(i), stmp(i));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x33v)
port map (spw_txdp(i), spw_txdn(i), dtmp(i), gnd);
spw_txs_pad : outpad_ds generic map (padtech, lvds, x33v)
port map (spw_txsp(i), spw_txsn(i), stmp(i), gnd);
end generate;
end generate;
spw : if CFG_SPW_EN > 0 generate
core0: if CFG_SPW_GRSPW = 1 generate
spw_rxtxclk <= clkm;
spw_rstn <= rstn;
end generate;
core1 : if CFG_SPW_GRSPW = 2 generate
spw_rxtxclk <= clk100;
spw_rstn_sync_proc : process(rstn,spw_rxtxclk)
begin
if rstn = '0' then
spw_rstn_sync <= '0';
spw_rstn <= '0';
elsif rising_edge(spw_rxtxclk) then
spw_rstn_sync <= '1';
spw_rstn <= spw_rstn_sync;
end if;
end process spw_rstn_sync_proc;
end generate;
spw_rxclkn <= not spw_rxtxclk;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_inputloop: for j in 0 to CFG_SPW_PORTS-1 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT)
port map(
rstn => spw_rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i*CFG_SPW_PORTS+j),
si => stmp(i*CFG_SPW_PORTS+j),
do => spwi(i).d(j*2+1 downto j*2),
dov => spwi(i).dv(j*2+1 downto j*2),
dconnect => spwi(i).dconnect(j*2+1 downto j*2),
rxclko => spw_rxclk(i*CFG_SPW_PORTS+j));
end generate;
oneport : if CFG_SPW_PORTS = 1 generate
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dv(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
end generate;
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
end generate;
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_inputloop: for j in 0 to CFG_SPW_PORTS-1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 2,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i*CFG_SPW_PORTS+j),
si => stmp(i*CFG_SPW_PORTS+j),
rxclko => spw_rxclk(i*CFG_SPW_PORTS+j),
do => spwi(i).d(j),
ndo => spwi(i).nd(j*5+4 downto j*5),
dconnect => spwi(i).dconnect(j*2+1 downto j*2));
end generate spw_inputloop;
oneport : if CFG_SPW_PORTS = 1 generate
spwi(i).d(1) <= '0'; -- For second port
spwi(i).d(3 downto 2) <= "00"; -- For GRSPW2 second port
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
end generate;
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
end generate spw1_input;
sw0 : grspwm generic map(tech => memtech,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+i,
sysfreq => CPU_FREQ, usegen => 1,
pindex => 10+i, paddr => 10+i, pirq => 10+i,
nsync => 1, rmap => CFG_SPW_RMAP, rxunaligned => CFG_SPW_RXUNAL,
rmapcrc => CFG_SPW_RMAPCRC, fifosize1 => CFG_SPW_AHBFIFO,
fifosize2 => CFG_SPW_RXFIFO, rxclkbuftype => 2, dmachan => CFG_SPW_DMACHAN,
rmapbufs => CFG_SPW_RMAPBUF, ft => CFG_SPW_FT, ports => CFG_SPW_PORTS,
spwcore => CFG_SPW_GRSPW, netlist => CFG_SPW_NETLIST,
rxtx_sameclk => CFG_SPW_RTSAME, input_type => CFG_SPW_INPUT,
output_type => CFG_SPW_OUTPUT)
port map(rstn, clkm, spw_rxclk(i*CFG_SPW_PORTS), spw_rxclk(i*CFG_SPW_PORTS+1),
spw_rxtxclk, spw_rxtxclk, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+i),
apbi2, apbo2(10+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '1';
spwi(i).clkdiv10 <= conv_std_logic_vector(CPU_FREQ/10000-1, 8) when CFG_SPW_GRSPW = 1
else conv_std_logic_vector(10-1, 8);
spwi(i).tickinraw <= '0';
spwi(i).timein <= (others => '0');
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
swportloop1: for j in 0 to CFG_SPW_PORTS-1 generate
spwlb0 : if SPW_LOOP_BACK = 1 generate
dtmp(i*CFG_SPW_PORTS+j) <= spwo(i).d(j); stmp(i*CFG_SPW_PORTS+j) <= spwo(i).s(j);
end generate;
nospwlb0 : if SPW_LOOP_BACK = 0 generate
spw_rxd_pad : inpad_ds generic map (padtech, lvds, x33v, 1)
port map (spw_rxdp(i*CFG_SPW_PORTS+j), spw_rxdn(i*CFG_SPW_PORTS+j), dtmp(i*CFG_SPW_PORTS+j));
spw_rxs_pad : inpad_ds generic map (padtech, lvds, x33v, 1)
port map (spw_rxsp(i*CFG_SPW_PORTS+j), spw_rxsn(i*CFG_SPW_PORTS+j), stmp(i*CFG_SPW_PORTS+j));
spw_txd_pad : outpad_ds generic map (padtech, lvds, x33v)
port map (spw_txdp(i*CFG_SPW_PORTS+j), spw_txdn(i*CFG_SPW_PORTS+j), spwo(i).d(j), gnd);
spw_txs_pad : outpad_ds generic map (padtech, lvds, x33v)
port map (spw_txsp(i*CFG_SPW_PORTS+j), spw_txsn(i*CFG_SPW_PORTS+j), spwo(i).s(j), gnd);
end generate;
end generate;
end generate;
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 GR-XC6S-LX75 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-altera-ep2sgx90-av/leon3mp.vhd | 2 | 22087 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.ft245.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
-- RESET, CLK, ERROR
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : out std_ulogic;
-- combined flash/SSRAM/IO bus (fs_...)
fs_addr : out std_logic_vector(24 downto 0);
fs_data : inout std_logic_vector(31 downto 0);
-- IO chip enable
io_cen : out std_logic;
io_wen : out std_logic;
-- separate flash signals (flash_...)
flash_cen : out std_ulogic;
flash_oen : out std_logic;
flash_wen : out std_logic;
-- separate SSRAM signals (ssram_...)
ssram_cen : out std_logic;
ssram_wen : out std_logic;
ssram_bw : out std_logic_vector (3 downto 0);
ssram_oen : out std_ulogic;
ssram_clk : out std_ulogic;
ssram_adscn : out std_ulogic;
ssram_adspn : out std_ulogic;
ssram_advn : out std_ulogic;
-- DDR2
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_odt : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (7 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (63 downto 0); -- ddr data
-- ETHERNET PHY
phy_gtx_clk : out std_logic;
phy_mii_data: inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(7 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_tx_data : out std_logic_vector(7 downto 0);
phy_tx_en : out std_ulogic;
phy_tx_er : out std_ulogic;
phy_mii_clk : out std_ulogic;
-- debug support unit
dsuact : out std_ulogic;
-- console/debug UART
rxd1 : in std_logic;
txd1 : out std_logic;
-- FT245 UART
ft245_data : inout std_logic_vector (7 downto 0);
ft245_rdn : out std_logic;
ft245_wr : out std_logic;
ft245_rxfn : in std_logic;
ft245_txen : in std_logic;
ft245_pwrenn : in std_logic;
-- GPIO
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0)
);
end;
architecture rtl of leon3mp is
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal memi, smemi : memory_in_type;
signal memo, smemo : memory_out_type;
signal wpo : wprot_out_type;
signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector (13 downto 0);
signal clklock, lock, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
-- attribute syn_keep : boolean;
-- attribute syn_preserve : boolean;
-- attribute syn_keep of clkml : signal is true;
-- attribute syn_preserve of clkml : signal is true;
signal extd : std_logic_vector(31 downto 0);
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector;
signal clkm, rstn, ssram_clkl : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal ft245i : ft245_in_type;
signal ft245o : ft245_out_type;
signal ft245_vbdrive : std_logic_vector(7 downto 0);
constant IOAEN : integer := 1;
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; cgi.pllref <= '0';
clklock <= cgo.clklock and lock;
clkgen0 : clkgen -- clock generator for main clock
generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL, clk_div => CFG_CLKDIV,
sdramen => CFG_MCTRL_SDEN, pcien => 0, pcidll => 0,
freq => BOARD_FREQ, clk2xen => 0, clksel => 0, clk_odiv => 0)
port map (clkin => clk, pciclkin => gnd(0), clk => clkm, clkn => ssram_clkl,
clk2x => open, sdclk => open, pciclk => open,
cgi => cgi, cgo => cgo);
-- ssram_clkl <= not clkm;
ssrclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (ssram_clk, ssram_clkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, clklock, rstn);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsui.break <= '0';
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
romaddr => 16#000#, rommask => 16#E00#,
ioaddr => 16#200#, iomask => 16#E00#,
ramaddr => 16#C00#, rammask => 16#F00#,
paddr => 0, pmask => 16#FFF#,
srbanks => 1, wprot => 0,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT,
sden => CFG_MCTRL_SDEN,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, open);
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
mg0 : if CFG_MCTRL_LEON2 = 0 generate -- no prom/sram pads
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
rom_sel_pad : outpad generic map (tech => padtech)
port map (flash_cen, vcc(0));
ssram_sel_pad : outpad generic map (tech => padtech)
port map (ssram_cen, vcc(0));
io_sel_pad : outpad generic map (tech => padtech)
port map (io_cen, vcc(0));
end generate;
mgpads : if CFG_MCTRL_LEON2 = 1 generate
-- flash/ssram data/address pads
fsaddr_pad : outpadv generic map (width => 25, tech => padtech)
port map (fs_addr, memo.address(25 downto 1));
fsdata_pad : iopadvv generic map (width => 32, tech => padtech)
port map (fs_data, memo.data, memo.vbdrive, memi.data);
-- flash only pads
rom_sel_pad : outpad generic map (tech => padtech)
port map (flash_cen, memo.romsn(0));
rom_oen_pad : outpad generic map (tech => padtech)
port map (flash_oen, memo.oen);
rom_wri_pad : outpad generic map (tech => padtech)
port map (flash_wen, memo.writen);
-- ssram only pads
ssram_adv_n_pad : outpad generic map (tech => padtech)
port map (ssram_advn, vcc(0));
ssram_adsp_n_pad : outpad generic map (tech => padtech)
port map (ssram_adspn, vcc(0));
ssram_adscn_pad : outpad generic map (tech => padtech)
port map (ssram_adscn, gnd(0));
ssram_sel_pad : outpad generic map ( tech => padtech)
port map (ssram_cen, memo.ramsn(0));
ssram_oen_pad : outpad generic map (tech => padtech)
port map (ssram_oen, memo.ramoen(0));
ssram_wen_pad : outpad generic map (tech => padtech)
port map (ssram_wen, memo.wrn(0));
ssram_bw_pad : outpadv generic map (width => 4, tech => padtech)
port map (ssram_bw, memo.mben);
-- io data
io_sel_pad : outpad generic map (tech => padtech)
port map (io_cen, memo.iosn);
io_wri_pad : outpad generic map (tech => padtech)
port map (io_wen, memo.writen);
end generate;
ddrsp0 : if (CFG_DDR2SP /= 0) generate
ddrc0 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 3, haddr => 16#400#, hmask => 16#C00#, ioaddr => 1,
pwron => CFG_DDR2SP_INIT, MHz => BOARD_FREQ/1000,
clkmul => CFG_DDR2SP_FREQ/10, clkdiv => BOARD_FREQ/10000,
ahbfreq => CPU_FREQ/1000, col => CFG_DDR2SP_COL,
Mbyte => CFG_DDR2SP_SIZE, ddrbits => 64, readdly => 1,
ddelayb0 => CFG_DDR2SP_DELAY0, ddelayb1 => CFG_DDR2SP_DELAY1,
ddelayb2 => CFG_DDR2SP_DELAY2, ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4, ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6, ddelayb7 => CFG_DDR2SP_DELAY7,
numidelctrl => 3, norefclk => 1, odten => 1, dqsse => 1)
port map ( rst_ddr => resetn, rst_ahb => rstn, clk_ddr => clk, clk_ahb => clkm, clkref200 => gnd(0),
lock => lock, clkddro => clkml, clkddri => clkml, ahbsi => ahbsi, ahbso => ahbso(3),
ddr_clk => ddr_clkv, ddr_clkb => ddr_clkbv, ddr_clk_fb => gnd(0), ddr_cke => ddr_ckev,
ddr_csb => ddr_csbv, ddr_web => ddr_web, ddr_rasb => ddr_rasb, ddr_casb => ddr_casb,
ddr_dm => ddr_dm, ddr_dqs => ddr_dqs, ddr_dqsn => open, ddr_ad => ddr_ad, ddr_ba => ddr_ba,
ddr_dq => ddr_dq, ddr_odt => ddr_odt);
ddr_clk <= ddr_clkv(2 downto 0); ddr_clkb <= ddr_clkbv(2 downto 0);
ddr_cke <= ddr_ckev(1 downto 0); ddr_csb <= ddr_csbv(1 downto 0);
end generate;
noddr : if (CFG_DDR2SP = 0) generate
ddr_cke <= (others => '0'); ddr_csb <= (others => '1'); lock <= '1';
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 18,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(11), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : inpad generic map (tech => padtech)
port map (phy_tx_clk, ethi.tx_clk);
erxc_pad : inpad generic map (tech => padtech)
port map (phy_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (phy_rx_data, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (phy_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (phy_tx_data, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( phy_tx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy_tx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, etho.mdc);
end generate;
----------------------------------------------------------------------
--- APB Bridge and various peripherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE = 1 generate
uart1 : ft245uart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart)
port map (rstn, clkm, apbi, apbo(1), ft245i, ft245o);
ft245_vbdrive <= (others => ft245o.oen);
ft245_data_pad : iopadvv generic map (width => 8, tech => padtech)
port map (ft245_data, ft245o.wrdata, ft245_vbdrive, ft245i.rddata);
ft245_rdn_pad : outpad generic map (tech => padtech)
port map (ft245_rdn, ft245o.rdn);
ft245_wr_pad : outpad generic map (tech => padtech)
port map (ft245_wr, ft245o.wr);
ft245_rxfn_pad : inpad generic map (tech => padtech)
port map (ft245_rxfn, ft245i.rxfn);
ft245_txen_pad : inpad generic map (tech => padtech)
port map (ft245_txen, ft245i.txen);
ft245_pwrenn_pad : inpad generic map (tech => padtech)
port map (ft245_pwrenn, ft245i.pwrenn);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ,
pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-- nap0 : for i in 6 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 7 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera EP2SGX90 SSRAM/DDR Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-gr-xc3s-1500/config.vhd | 1 | 8833 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan3;
constant CFG_MEMTECH : integer := spartan3;
constant CFG_PADTECH : integer := spartan3;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan3;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (4);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 4;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- USB DSU
constant CFG_GRUSB_DCL : integer := 0;
constant CFG_GRUSB_DCL_UIFACE : integer := 1;
constant CFG_GRUSB_DCL_DW : integer := 8;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000008#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 1 + 0;
-- AHB status register
constant CFG_AHBSTAT : integer := 0;
constant CFG_AHBSTATN : integer := 1;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 16;
-- CAN 2.0 interface
constant CFG_CAN : integer := 0;
constant CFG_CAN_NUM : integer := 1;
constant CFG_CANIO : integer := 16#0#;
constant CFG_CANIRQ : integer := 0;
constant CFG_CANSEPIRQ: integer := 0;
constant CFG_CAN_SYNCRST : integer := 0;
constant CFG_CANFT : integer := 0;
-- GR USB 2.0 Device Controller
constant CFG_GRUSBDC : integer := 0;
constant CFG_GRUSBDC_AIFACE : integer := 0;
constant CFG_GRUSBDC_UIFACE : integer := 1;
constant CFG_GRUSBDC_DW : integer := 8;
constant CFG_GRUSBDC_NEPI : integer := 1;
constant CFG_GRUSBDC_NEPO : integer := 1;
constant CFG_GRUSBDC_I0 : integer := 1024;
constant CFG_GRUSBDC_I1 : integer := 1024;
constant CFG_GRUSBDC_I2 : integer := 1024;
constant CFG_GRUSBDC_I3 : integer := 1024;
constant CFG_GRUSBDC_I4 : integer := 1024;
constant CFG_GRUSBDC_I5 : integer := 1024;
constant CFG_GRUSBDC_I6 : integer := 1024;
constant CFG_GRUSBDC_I7 : integer := 1024;
constant CFG_GRUSBDC_I8 : integer := 1024;
constant CFG_GRUSBDC_I9 : integer := 1024;
constant CFG_GRUSBDC_I10 : integer := 1024;
constant CFG_GRUSBDC_I11 : integer := 1024;
constant CFG_GRUSBDC_I12 : integer := 1024;
constant CFG_GRUSBDC_I13 : integer := 1024;
constant CFG_GRUSBDC_I14 : integer := 1024;
constant CFG_GRUSBDC_I15 : integer := 1024;
constant CFG_GRUSBDC_O0 : integer := 1024;
constant CFG_GRUSBDC_O1 : integer := 1024;
constant CFG_GRUSBDC_O2 : integer := 1024;
constant CFG_GRUSBDC_O3 : integer := 1024;
constant CFG_GRUSBDC_O4 : integer := 1024;
constant CFG_GRUSBDC_O5 : integer := 1024;
constant CFG_GRUSBDC_O6 : integer := 1024;
constant CFG_GRUSBDC_O7 : integer := 1024;
constant CFG_GRUSBDC_O8 : integer := 1024;
constant CFG_GRUSBDC_O9 : integer := 1024;
constant CFG_GRUSBDC_O10 : integer := 1024;
constant CFG_GRUSBDC_O11 : integer := 1024;
constant CFG_GRUSBDC_O12 : integer := 1024;
constant CFG_GRUSBDC_O13 : integer := 1024;
constant CFG_GRUSBDC_O14 : integer := 1024;
constant CFG_GRUSBDC_O15 : integer := 1024;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 0;
constant CFG_UART2_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-xilinx-vc707/testbench.vhd | 1 | 21601 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library micron;
use micron.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
testahb : boolean := true;
USE_MIG_INTERFACE_MODEL : boolean := false
);
end;
architecture behav of testbench is
-- DDR3 Simulation parameters
constant SIM_BYPASS_INIT_CAL : string := "FAST";
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
constant SIMULATION : string := "TRUE";
-- Should be TRUE during design simulations and
-- FALSE during implementations
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0';
signal address : std_logic_vector(25 downto 0);
signal data : std_logic_vector(15 downto 0);
signal button : std_logic_vector(3 downto 0) := "0000";
signal genio : std_logic_vector(59 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal adv : std_logic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal txd1 , rxd1 , dsurx : std_logic;
signal txd2 , rxd2 , dsutx : std_logic;
signal ctsn1 , rtsn1 , dsuctsn : std_ulogic;
signal ctsn2 , rtsn2 , dsurtsn : std_ulogic;
signal phy_mii_data : std_logic;
signal phy_tx_clk : std_ulogic;
signal phy_rx_clk : std_ulogic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_dv : std_ulogic;
signal phy_rx_er : std_ulogic;
signal phy_col : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_en : std_ulogic;
signal phy_tx_er : std_ulogic;
signal phy_mii_clk : std_ulogic;
signal phy_rst_n : std_ulogic;
signal phy_gtx_clk : std_ulogic;
signal phy_mii_int_n : std_ulogic;
signal clk27 : std_ulogic := '0';
signal clk200p : std_ulogic := '0';
signal clk200n : std_ulogic := '1';
signal clk33 : std_ulogic := '0';
signal clkethp : std_ulogic := '0';
signal clkethn : std_ulogic := '1';
signal txp1 : std_logic;
signal txn : std_logic;
signal rxp : std_logic := '1';
signal rxn : std_logic := '0';
signal iic_scl : std_ulogic;
signal iic_sda : std_ulogic;
signal ddc_scl : std_ulogic;
signal ddc_sda : std_ulogic;
signal dvi_iic_scl : std_logic;
signal dvi_iic_sda : std_logic;
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_ulogic;
signal tft_lcd_clk_n : std_ulogic;
signal tft_lcd_hsync : std_ulogic;
signal tft_lcd_vsync : std_ulogic;
signal tft_lcd_de : std_ulogic;
signal tft_lcd_reset_b : std_ulogic;
-- DDR3 memory
signal ddr3_dq : std_logic_vector(63 downto 0);
signal ddr3_dqs_p : std_logic_vector(7 downto 0);
signal ddr3_dqs_n : std_logic_vector(7 downto 0);
signal ddr3_addr : std_logic_vector(13 downto 0);
signal ddr3_ba : std_logic_vector(2 downto 0);
signal ddr3_ras_n : std_logic;
signal ddr3_cas_n : std_logic;
signal ddr3_we_n : std_logic;
signal ddr3_reset_n : std_logic;
signal ddr3_ck_p : std_logic_vector(0 downto 0);
signal ddr3_ck_n : std_logic_vector(0 downto 0);
signal ddr3_cke : std_logic_vector(0 downto 0);
signal ddr3_cs_n : std_logic_vector(0 downto 0);
signal ddr3_dm : std_logic_vector(7 downto 0);
signal ddr3_odt : std_logic_vector(0 downto 0);
-- SPI flash
signal spi_sel_n : std_ulogic;
signal spi_clk : std_ulogic;
signal spi_mosi : std_ulogic;
signal dsurst : std_ulogic;
signal errorn : std_logic;
signal switch : std_logic_vector(4 downto 0); -- I/O port
signal led : std_logic_vector(6 downto 0); -- I/O port
constant lresp : boolean := false;
signal tdqs_n : std_logic;
signal gmii_tx_clk : std_logic;
signal gmii_rx_clk : std_logic;
signal gmii_txd : std_logic_vector(7 downto 0);
signal gmii_tx_en : std_logic;
signal gmii_tx_er : std_logic;
signal gmii_rxd : std_logic_vector(7 downto 0);
signal gmii_rx_dv : std_logic;
signal gmii_rx_er : std_logic;
signal configuration_finished : boolean;
signal speed_is_10_100 : std_logic;
signal speed_is_100 : std_logic;
signal usb_clkout : std_logic := '0';
signal usb_d : std_logic_vector(7 downto 0);
signal usb_resetn : std_ulogic;
signal usb_nxt : std_ulogic;
signal usb_stp : std_ulogic;
signal usb_dir : std_ulogic;
-- GRUSB_DCL test signals
signal ddelay : std_ulogic := '0';
signal dstart : std_ulogic := '0';
signal drw : std_ulogic;
signal daddr : std_logic_vector(31 downto 0);
signal dlen : std_logic_vector(14 downto 0);
signal ddi : grusb_dcl_debug_data;
signal ddone : std_ulogic;
signal ddo : grusb_dcl_debug_data;
signal phy_mdio : std_logic;
signal phy_mdc : std_ulogic;
component leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
testahb : boolean := false;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false;
autonegotiation : integer := 1
);
port (
reset : in std_ulogic;
clk200p : in std_ulogic; -- 200 MHz clock
clk200n : in std_ulogic; -- 200 MHz clock
address : out std_logic_vector(25 downto 0);
data : inout std_logic_vector(15 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
romsn : out std_logic;
adv : out std_logic;
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
dsurx : in std_ulogic;
dsutx : out std_ulogic;
dsuctsn : in std_ulogic;
dsurtsn : out std_ulogic;
button : in std_logic_vector(3 downto 0);
switch : inout std_logic_vector(4 downto 0);
led : out std_logic_vector(6 downto 0);
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
usb_refclk_opt : in std_logic;
usb_clkout : in std_logic;
usb_d : inout std_logic_vector(7 downto 0);
usb_nxt : in std_logic;
usb_stp : out std_logic;
usb_dir : in std_logic;
usb_resetn : out std_ulogic;
gtrefclk_p : in std_logic;
gtrefclk_n : in std_logic;
txp : out std_logic;
txn : out std_logic;
rxp : in std_logic;
rxn : in std_logic;
emdio : inout std_logic;
emdc : out std_ulogic;
eint : in std_ulogic;
erst : out std_ulogic;
can_txd : out std_logic_vector(0 to CFG_CAN_NUM-1);
can_rxd : in std_logic_vector(0 to CFG_CAN_NUM-1);
spi_data_out : in std_logic;
spi_data_in : out std_ulogic;
spi_data_cs_b : out std_ulogic;
spi_clk : out std_ulogic
);
end component;
component ddr3_model
generic(
ADDR_BITS : integer := 14;
BA_BITS : integer := 3;
DM_BITS : integer := 1;
DQ_BITS : integer := 8;
DQS_BITS : integer := 1
);
port(
rst_n : in std_logic;
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ras_n : in std_logic;
cas_n : in std_logic;
we_n : in std_logic;
dm_tdqs : inout std_logic;
ba : in std_logic_vector(2 downto 0);
addr : in std_logic_vector(13 downto 0);
dq : inout std_logic_vector(7 downto 0);
dqs : inout std_logic;
dqs_n : inout std_logic;
tdqs_n : out std_logic_vector(0 to 0);
odt : in std_logic
);
end component;
begin
-- clock and reset
clk200p <= not clk200p after 2.5 ns;
clk200n <= not clk200n after 2.5 ns;
clkethp <= not clkethp after 4 ns;
clkethn <= not clkethp after 4 ns;
rst <= not dsurst;
rxd1 <= 'H'; ctsn1 <= '0';
rxd2 <= 'H'; ctsn2 <= '0';
button <= "0000";
switch(3 downto 0) <= "0000";
cpu : leon3mp
generic map (
fabtech => fabtech,
memtech => memtech,
padtech => padtech,
clktech => clktech,
disas => disas,
dbguart => dbguart,
pclow => pclow,
testahb => testahb,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
SIMULATION => SIMULATION,
USE_MIG_INTERFACE_MODEL => USE_MIG_INTERFACE_MODEL,
autonegotiation => 0
)
port map (
reset => rst,
clk200p => clk200p,
clk200n => clk200n,
address => address,
data => data,
oen => oen,
writen => writen,
romsn => romsn,
adv => adv,
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
dsurx => dsurx,
dsutx => dsutx,
dsuctsn => dsuctsn,
dsurtsn => dsurtsn,
button => button,
switch => switch,
led => led,
iic_scl => iic_scl,
iic_sda => iic_sda,
usb_refclk_opt => '0',
usb_clkout => usb_clkout,
usb_d => usb_d,
usb_nxt => usb_nxt,
usb_stp => usb_stp,
usb_dir => usb_dir,
usb_resetn => usb_resetn,
gtrefclk_p => clkethp,
gtrefclk_n => clkethn,
txp => OPEN,
txn => OPEN,
rxp => '1',
rxn => '1',
emdio => phy_mdio,
emdc => phy_mdc,
eint => '0',
erst => OPEN,
can_txd => OPEN,
can_rxd => "0",
spi_data_out => '0',
spi_data_in => OPEN,
spi_data_cs_b => OPEN,
spi_clk => OPEN
);
phy0 : if (CFG_GRETH = 1) generate
phy_mdio <= 'H';
p0: phy
generic map (address => 7)
port map(dsurst, phy_mdio, OPEN , OPEN , OPEN ,
OPEN , OPEN , OPEN , OPEN , "00000000",
'0', '0', phy_mdc, clkethp);
end generate;
prom0 : for i in 0 to 1 generate
sr0 : sram generic map (index => i+4, abits => 26, fname => promfile)
port map (address(25 downto 0), data(15-i*8 downto 8-i*8), romsn,
writen, oen);
end generate;
-- Memory Models instantiations
gen_mem_model : if (USE_MIG_INTERFACE_MODEL /= true) generate
ddr3mem : if (CFG_MIG_SERIES7 = 1) generate
gen_mem: for i in 0 to 7 generate
u1: ddr3_model
generic map(
ADDR_BITS => 14,
BA_BITS => 3,
DM_BITS => 1,
DQ_BITS => 8,
DQS_BITS => 1
)
port map (
rst_n => ddr3_reset_n,
ck => ddr3_ck_p(0),
ck_n => ddr3_ck_n(0),
cke => ddr3_cke(0),
cs_n => ddr3_cs_n(0),
ras_n => ddr3_ras_n,
cas_n => ddr3_cas_n,
we_n => ddr3_we_n,
dm_tdqs => ddr3_dm(i),
ba => ddr3_ba,
addr => ddr3_addr,
dq => ddr3_dq((8*i+7) downto (8*i)),
dqs => ddr3_dqs_p(i),
dqs_n => ddr3_dqs_n(i),
tdqs_n => open,
odt => ddr3_odt(0)
);
end generate gen_mem;
end generate ddr3mem;
end generate gen_mem_model;
mig_mem_model : if (USE_MIG_INTERFACE_MODEL = true) generate
ddr3_dq <= (others => 'Z');
ddr3_dqs_p <= (others => 'Z');
ddr3_dqs_n <= (others => 'Z');
end generate mig_mem_model;
errorn <= led(1);
errorn <= 'H'; -- ERROR pull-up
usbtr: if (CFG_GRUSBHC = 1) generate
u0: ulpi
port map (usb_clkout, usb_d, usb_nxt, usb_stp, usb_dir, usb_resetn);
end generate usbtr;
usbdevsim: if (CFG_GRUSBDC = 1) generate
u0: grusbdcsim
generic map (functm => 0, keepclk => 1)
port map (usb_resetn, usb_clkout, usb_d, usb_nxt, usb_stp, usb_dir);
end generate usbdevsim;
usb_dclsim: if (CFG_GRUSB_DCL = 1) generate
u0: grusb_dclsim
generic map (functm => 0, keepclk => 1)
port map (usb_resetn, usb_clkout, usb_d, usb_nxt, usb_stp, usb_dir,
ddelay, dstart, drw, daddr, dlen, ddi, ddone, ddo);
usb_dcl_proc : process
begin
wait for 10 ns;
Print("GRUSB_DCL test started");
wait until rising_edge(ddone);
-- Write 128 bytes to memory
daddr <= X"40000000";
dlen <= conv_std_logic_vector(32,15);
for i in 0 to 127 loop
ddi(i) <= conv_std_logic_vector(i+8,8);
end loop; -- i
grusb_dcl_write(usb_clkout, drw, dstart, ddone);
-- Read back written data
grusb_dcl_read(usb_clkout, drw, dstart, ddone);
-- Compare data
for i in 0 to 127 loop
if ddo(i) /= ddi(i) then
Print("ERROR: Data mismatch using GRUSB_DCL");
end if;
end loop;
Print("GRUSB_DCL test finished");
wait;
end process;
end generate usb_dclsim;
iuerr : process
begin
wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation
wait on led(3); -- DDR3 Memory Init ready
wait for 5000 ns;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ; -- this should be a failure
end process;
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
switch(4) <= '0';
wait for 2500 ns;
wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation
dsurst <= '1';
switch(4) <= '1';
if (USE_MIG_INTERFACE_MODEL /= true) then
wait on led(3); -- Wait for DDR3 Memory Init ready
end if;
report "Start DSU transfer";
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- Reads from memory and DSU register to mimic GRMON during simulation
l1 : loop
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
rxi(dsurx, w32, txp, lresp);
--report "DSU read memory " & tost(w32);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
rxi(dsurx, w32, txp, lresp);
--report "DSU Break and Single Step register" & tost(w32);
end loop l1;
wait;
-- ** This is only kept for reference --
-- do test read and writes to DDR3 to check status
-- Write
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#01#, 16#23#, 16#45#, 16#67#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
txa(dsutx, 16#89#, 16#AB#, 16#CD#, 16#EF#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#08#, txp);
txa(dsutx, 16#08#, 16#19#, 16#2A#, 16#3B#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#0C#, txp);
txa(dsutx, 16#4C#, 16#5D#, 16#6E#, 16#7F#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
rxi(dsurx, w32, txp, lresp);
report "* Read " & tost(w32);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#08#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#0C#, txp);
rxi(dsurx, w32, txp, lresp);
wait;
-- Register 0x90000000 (DSU Control Register)
-- Data 0x0000202e (b0010 0000 0010 1110)
-- [0] - Trace Enable
-- [1] - Break On Error
-- [2] - Break on IU watchpoint
-- [3] - Break on s/w break points
--
-- [4] - (Break on trap)
-- [5] - Break on error traps
-- [6] - Debug mode (Read mode only)
-- [7] - DSUEN (read mode)
--
-- [8] - DSUBRE (read mode)
-- [9] - Processor mode error (clears error)
-- [10] - processor halt (returns 1 if processor halted)
-- [11] - power down mode (return 1 if processor in power down mode)
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#80#, 16#02#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
end;
begin
dsuctsn <= '0';
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/grlib/modgen/multlib.vhd | 6 | 1614 | -----------------------------------------------------------------------------
-- Package: multlib
-- File: multlib.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: A set of multipliers generated from the Arithmetic Module
-- Generator at Norwegian University of Science and Technology.
------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.std_logic_1164.all;
package multlib is
component mul_17_17
generic (mulpipe : integer := 0);
port (
clk : in std_ulogic;
holdn: in std_ulogic;
x : in std_logic_vector(16 downto 0);
y : in std_logic_vector(16 downto 0);
p : out std_logic_vector(33 downto 0)
);
end component;
component mul_33_9
port (
x : in std_logic_vector(32 downto 0);
y : in std_logic_vector(8 downto 0);
p : out std_logic_vector(41 downto 0)
);
end component;
component mul_33_17
port (
x : in std_logic_vector(32 downto 0);
y : in std_logic_vector(16 downto 0);
p : out std_logic_vector(49 downto 0)
);
end component;
component mul_33_33
generic (mulpipe : integer := 0);
port (
clk : in std_ulogic;
holdn: in std_ulogic;
x : in std_logic_vector(32 downto 0);
y : in std_logic_vector(32 downto 0);
p : out std_logic_vector(65 downto 0)
);
end component;
component add32
port(
x : in std_logic_vector(31 downto 0);
y : in std_logic_vector(31 downto 0);
ci : in std_ulogic;
s : out std_logic_vector(31 downto 0);
co : out std_ulogic
);
end component;
end multlib;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/misc/ahbram.vhd | 1 | 9173 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbram
-- File: ahbram.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Jan Andersson - Aeroflex Gaisler
-- Description: AHB ram. 0-waitstate read, 0/1-waitstate write.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
entity ahbram is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pipe : integer := 0;
maccsz : integer := AHBDW;
scantest: integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbram is
constant abits : integer := log2ext(kbytes) + 8 - maccsz/64;
constant dw : integer := maccsz;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBRAM, 0, abits+2+maccsz/64, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
type reg_type is record
hwrite : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
addr : std_logic_vector(abits-1+log2(dw/8) downto 0);
size : std_logic_vector(2 downto 0);
prdata : std_logic_vector((dw-1)*pipe downto 0);
pwrite : std_ulogic;
pready : std_ulogic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : reg_type :=
(hwrite => '0', hready => '1', hsel => '0', addr => (others => '0'),
size => (others => '0'), prdata => (others => '0'), pwrite => '0',
pready => '1');
signal r, c : reg_type;
signal ramsel : std_logic_vector(dw/8-1 downto 0);
signal write : std_logic_vector(dw/8-1 downto 0);
signal ramaddr : std_logic_vector(abits-1 downto 0);
signal ramdata : std_logic_vector(dw-1 downto 0);
signal hwdata : std_logic_vector(dw-1 downto 0);
begin
comb : process (ahbsi, r, rst, ramdata)
variable bs : std_logic_vector(dw/8-1 downto 0);
variable v : reg_type;
variable haddr : std_logic_vector(abits-1 downto 0);
variable hrdata : std_logic_vector(dw-1 downto 0);
variable seldata : std_logic_vector(dw-1 downto 0);
variable raddr : std_logic_vector(3 downto 2);
variable adsel : std_logic;
begin
v := r; v.hready := '1'; bs := (others => '0');
v.pready := r.hready;
if pipe=0 then
adsel := r.hwrite or not r.hready;
else
adsel := r.hwrite or r.pwrite;
v.hready := r.hready or not r.pwrite;
end if;
if adsel = '1' then
haddr := r.addr(abits-1+log2(dw/8) downto log2(dw/8));
else
haddr := ahbsi.haddr(abits-1+log2(dw/8) downto log2(dw/8));
bs := (others => '0');
end if;
raddr := (others => '0');
v.pwrite := '0';
if pipe/=0 and (r.hready='1' or r.pwrite='0') then
v.addr := ahbsi.haddr(abits-1+log2(dw/8) downto 0);
end if;
if ahbsi.hready = '1' then
if pipe=0 then
v.addr := ahbsi.haddr(abits-1+log2(dw/8) downto 0);
end if;
v.hsel := ahbsi.hsel(hindex) and ahbsi.htrans(1);
v.size := ahbsi.hsize(2 downto 0);
v.hwrite := ahbsi.hwrite and v.hsel;
if pipe = 1 and v.hsel = '1' and ahbsi.hwrite = '0' and (r.pready='1' or ahbsi.htrans(0)='0') then
v.hready := '0';
v.pwrite := r.hwrite;
end if;
end if;
if r.hwrite = '1' then
case r.size is
when HSIZE_BYTE =>
bs(bs'left-conv_integer(r.addr(log2(dw/16) downto 0))) := '1';
when HSIZE_HWORD =>
for i in 0 to dw/16-1 loop
if i = conv_integer(r.addr(log2(dw/16) downto 1)) then
bs(bs'left-i*2 downto bs'left-i*2-1) := (others => '1');
end if;
end loop; -- i
when HSIZE_WORD =>
if dw = 32 then bs := (others => '1');
else
for i in 0 to dw/32-1 loop
if i = conv_integer(r.addr(log2(dw/8)-1 downto 2)) then
bs(bs'left-i*4 downto bs'left-i*4-3) := (others => '1');
end if;
end loop; -- i
end if;
when HSIZE_DWORD =>
if dw = 32 then null;
elsif dw = 64 then bs := (others => '1');
else
for i in 0 to dw/64-1 loop
if i = conv_integer(r.addr(3)) then
bs(bs'left-i*8 downto bs'left-i*8-7) := (others => '1');
end if;
end loop; -- i
end if;
when HSIZE_4WORD =>
if dw < 128 then null;
elsif dw = 128 then bs := (others => '1');
else
for i in 0 to dw/64-1 loop
if i = conv_integer(r.addr(3)) then
bs(bs'left-i*8 downto bs'left-i*8-7) := (others => '1');
end if;
end loop; -- i
end if;
when others => --HSIZE_8WORD
if dw < 256 then null;
else bs := (others => '1'); end if;
end case;
v.hready := not (v.hsel and not ahbsi.hwrite);
v.hwrite := v.hwrite and v.hready;
end if;
-- Duplicate read data on word basis, unless CORE_ACDM is enabled
if CORE_ACDM = 0 then
if dw = 32 then
seldata := ramdata;
elsif dw = 64 then
if r.size = HSIZE_DWORD then seldata := ramdata; else
if r.addr(2) = '0' then
seldata(dw/2-1 downto 0) := ramdata(dw-1 downto dw/2);
else
seldata(dw/2-1 downto 0) := ramdata(dw/2-1 downto 0);
end if;
seldata(dw-1 downto dw/2) := seldata(dw/2-1 downto 0);
end if;
elsif dw = 128 then
if r.size = HSIZE_4WORD then
seldata := ramdata;
elsif r.size = HSIZE_DWORD then
if r.addr(3) = '0' then seldata(dw/2-1 downto 0) := ramdata(dw-1 downto dw/2);
else seldata(dw/2-1 downto 0) := ramdata(dw/2-1 downto 0); end if;
seldata(dw-1 downto dw/2) := seldata(dw/2-1 downto 0);
else
raddr := r.addr(3 downto 2);
case raddr is
when "00" => seldata(dw/4-1 downto 0) := ramdata(4*dw/4-1 downto 3*dw/4);
when "01" => seldata(dw/4-1 downto 0) := ramdata(3*dw/4-1 downto 2*dw/4);
when "10" => seldata(dw/4-1 downto 0) := ramdata(2*dw/4-1 downto 1*dw/4);
when others => seldata(dw/4-1 downto 0) := ramdata(dw/4-1 downto 0);
end case;
seldata(dw-1 downto dw/4) := seldata(dw/4-1 downto 0) &
seldata(dw/4-1 downto 0) &
seldata(dw/4-1 downto 0);
end if;
else
seldata := ahbselectdata(ramdata, r.addr(4 downto 2), r.size);
end if;
else
seldata := ramdata;
end if;
if pipe = 0 then
v.prdata := (others => '0');
hrdata := seldata;
else
v.prdata := seldata;
hrdata := r.prdata;
end if;
if (not RESET_ALL) and (rst = '0') then
v.hwrite := RES.hwrite; v.hready := RES.hready;
end if;
write <= bs; for i in 0 to dw/8-1 loop ramsel(i) <= v.hsel or r.hwrite; end loop;
ramaddr <= haddr; c <= v;
ahbso.hrdata <= ahbdrivedata(hrdata);
ahbso.hready <= r.hready;
end process;
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
-- Select correct write data
hwdata <= ahbreaddata(ahbsi.hwdata, r.addr(4 downto 2),
conv_std_logic_vector(log2(dw/8), 3));
aram : syncrambw generic map (tech, abits, dw, scantest) port map (
clk, ramaddr, hwdata, ramdata, ramsel, write, ahbsi.testin);
reg : process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and rst = '0' then
r <= RES;
end if;
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbram" & tost(hindex) &
": AHB SRAM Module rev 1, " & tost(kbytes) & " kbytes");
-- pragma translate_on
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/stratixiii/ddr_phy_stratixiii.vhd | 4 | 22934 | library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
------------------------------------------------------------------
-- STRATIXIII DDR2 PHY ----------------------------------------------
------------------------------------------------------------------
entity stratixiii_ddr2_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0;
tech : integer := stratix3; odten : integer := 0; rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0); -- ddr address
ba : in std_logic_vector ( 2 downto 0); -- ddr bank address
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_pll : in std_logic_vector(1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(1 downto 0);
oct : in std_logic
);
end;
architecture rtl of stratixiii_ddr2_phy is
component apll is
generic (
freq : integer := 200;
mult : integer := 8;
div : integer := 5;
rskew : integer := 0
);
port(
areset : in std_logic := '0';
inclk0 : in std_logic := '0';
phasestep : in std_logic := '0';
phaseupdown : in std_logic := '0';
scanclk : in std_logic := '1';
c0 : out std_logic ;
c1 : out std_logic ;
c2 : out std_logic ;
c3 : out std_logic ;
c4 : out std_logic ;
locked : out std_logic;
phasedone : out std_logic
);
end component;
component aclkout is
port(
clk : in std_logic;
ddr_clk : out std_logic;
ddr_clkn: out std_logic
);
end component;
component actrlout is
generic(
power_up : string := "high"
);
port(
clk : in std_logic;
i : in std_logic;
o : out std_logic
);
end component;
--component adqsout is
--port(
-- clk : in std_logic; -- clk90
-- dqs : in std_logic;
-- dqs_oe : in std_logic;
-- dqs_oct : in std_logic; -- gnd = disable
-- dqs_pad : out std_logic; -- DQS pad
-- dqsn_pad : out std_logic -- DQSN pad
--);
--end component;
--component adqsin is
--port(
-- dqs_pad : in std_logic; -- DQS pad
-- dqsn_pad : in std_logic; -- DQSN pad
-- dqs : out std_logic
--);
--end component;
component admout is
port(
clk : in std_logic; -- clk0
dm_h : in std_logic;
dm_l : in std_logic;
dm_pad : out std_logic -- DQ pad
);
end component;
--component adqin is
--port(
-- clk : in std_logic;
-- dq_pad : in std_logic; -- DQ pad
-- dq_h : out std_logic;
-- dq_l : out std_logic;
-- config_clk : in std_logic;
-- config_clken : in std_logic;
-- config_datain : in std_logic;
-- config_update : in std_logic
--);
--end component;
--component adqout is
--port(
-- clk : in std_logic; -- clk0
-- clk_oct : in std_logic; -- clk90
-- dq_h : in std_logic;
-- dq_l : in std_logic;
-- dq_oe : in std_logic;
-- dq_oct : in std_logic; -- gnd = disable
-- dq_pad : out std_logic -- DQ pad
--);
--end component;
component dq_dqs_inst is
port(
bidir_dq_input_data_in : in std_logic_vector (7 downto 0);
bidir_dq_input_data_out_high : out std_logic_vector (7 downto 0);
bidir_dq_input_data_out_low : out std_logic_vector (7 downto 0);
bidir_dq_io_config_ena : in std_logic_vector (7 downto 0);
bidir_dq_oct_in : in std_logic_vector (7 downto 0);
bidir_dq_oct_out : out std_logic_vector (7 downto 0);
bidir_dq_oe_in : in std_logic_vector (7 downto 0);
bidir_dq_oe_out : out std_logic_vector (7 downto 0);
bidir_dq_output_data_in_high : in std_logic_vector (7 downto 0);
bidir_dq_output_data_in_low : in std_logic_vector (7 downto 0);
bidir_dq_output_data_out : out std_logic_vector (7 downto 0);
bidir_dq_sreset : in std_logic_vector (7 downto 0);
config_clk : in std_logic;
config_datain : in std_logic;
config_update : in std_logic;
dq_input_reg_clk : in std_logic;
dq_output_reg_clk : in std_logic;
dqs_areset : in std_logic;
dqs_oct_in : in std_logic;
dqs_oct_out : out std_logic;
dqs_oe_in : in std_logic;
dqs_oe_out : out std_logic;
dqs_output_data_in_high : in std_logic;
dqs_output_data_in_low : in std_logic;
dqs_output_data_out : out std_logic;
dqs_output_reg_clk : in std_logic;
dqsn_oct_in : in std_logic;
dqsn_oct_out : out std_logic;
dqsn_oe_in : in std_logic;
dqsn_oe_out : out std_logic;
oct_reg_clk : in std_logic
);
end component;
component bidir_dq_iobuf_inst is
port(
datain : in std_logic_vector (7 downto 0);
dyn_term_ctrl : in std_logic_vector (7 downto 0);
oe : in std_logic_vector (7 downto 0);
dataio : inout std_logic_vector (7 downto 0);
dataout : out std_logic_vector (7 downto 0)
);
end component;
component bidir_dqs_iobuf_inst is
port(
datain : in std_logic_vector (0 downto 0);
dyn_term_ctrl : in std_logic_vector (0 downto 0);
dyn_term_ctrl_b : in std_logic_vector (0 downto 0);
oe : in std_logic_vector (0 downto 0);
oe_b : in std_logic_vector (0 downto 0);
dataio : inout std_logic_vector (0 downto 0);
dataio_b : inout std_logic_vector (0 downto 0);
dataout : out std_logic_vector (0 downto 0)
);
end component;
signal reset : std_logic;
signal vcc, gnd, oe : std_ulogic;
signal locked, vlockl, lockl : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r, rclk : std_ulogic;
signal ckel, ckel2 : std_logic_vector(1 downto 0);
signal odtl : std_logic_vector(1 downto 0);
signal dqsin, dqsin_reg : std_logic_vector (7 downto 0); -- ddr dqs
signal dqsn : std_logic_vector(dbits/8-1 downto 0);
signal dqsoenr : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal delayrst : std_logic_vector(3 downto 0);
signal phasedone : std_logic;
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
-- altdq_dqs
signal bidir_dq_input_data_in : std_logic_vector (dbits-1 downto 0) := (others => '0');
signal bidir_dq_io_config_ena : std_logic_vector (dbits-1 downto 0) := (others => '1');
signal bidir_dq_oct_in : std_logic_vector (dbits-1 downto 0) := (others => '0');
signal bidir_dq_oct_out : std_logic_vector (dbits-1 downto 0);
signal bidir_dq_oe_in : std_logic_vector (dbits-1 downto 0) := (others => '0');
signal bidir_dq_oe_out : std_logic_vector (dbits-1 downto 0);
signal bidir_dq_output_data_out : std_logic_vector (dbits-1 downto 0);
signal bidir_dq_sreset : std_logic_vector (dbits-1 downto 0) := (others => '0');
signal dqs_areset : std_logic_vector (dbits/8-1 downto 0);
signal dqs_oct_out : std_logic_vector (dbits/8-1 downto 0);
signal dqs_oe_out : std_logic_vector (dbits/8-1 downto 0);
signal dqs_output_data_out : std_logic_vector (dbits/8-1 downto 0);
signal dqsn_oct_out : std_logic_vector (dbits/8-1 downto 0);
signal dqsn_oe_out : std_logic_vector (dbits/8-1 downto 0);
type phy_r_type is record
delay : std_logic_vector(3 downto 0);
count : std_logic_vector(3 downto 0);
update : std_logic;
sdata : std_logic;
enable : std_logic;
update_delay : std_logic;
end record;
type phy_r_type_arr is array (7 downto 0) of phy_r_type;
signal r,rin : phy_r_type_arr;
signal rp : std_logic_vector(8 downto 0);
signal rlockl : std_logic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of dqsn : signal is true;
attribute syn_preserve of dqsn : signal is true;
attribute syn_keep of dqsoenr : signal is true;
attribute syn_preserve of dqsoenr : signal is true;
attribute syn_keep of dqsin_reg : signal is true;
attribute syn_preserve of dqsin_reg : signal is true;
begin
-----------------------------------------------------------------------------------
-- Clock generation
-----------------------------------------------------------------------------------
oe <= not oen;
vcc <= '1'; gnd <= '0';
reset <= not rst;
-- Optional DDR clock multiplication
pll0 : apll
generic map(
freq => MHz,
mult => clk_mul,
div => clk_div,
rskew => rskew
)
port map(
areset => reset,
inclk0 => clk,
phasestep => rp(3),--rp(1),
phaseupdown => rp(8),--rp(3),
scanclk => clk0r,
c0 => clk0r,
c1 => clk90r,
c2 => open, --clk180r,
c3 => open, --clk270r,
c4 => rclk,
locked => lockl,
phasedone => phasedone
);
clk180r <= not clk0r;
clk270r <= not clk90r;
clkout <= clk0r;
-----------------------------------------------------------------------------------
-- Lock delay
-----------------------------------------------------------------------------------
rdel : if rstdelay /= 0 generate
rcnt : process (clk0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk0r) then
co := cnt(15);
vlockl <= vlock;
if rlockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
cnt(0) := dqsin_reg(7) or dqsin_reg(6) or dqsin_reg(5) or dqsin_reg(4) or -- dummy use of dqsin
dqsin_reg(3) or dqsin_reg(2) or dqsin_reg(1) or dqsin_reg(0);
-- pragma translate_off
cnt(0) := '0';
-- pragma translate_on
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if rlockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-----------------------------------------------------------------------------------
-- Generate external DDR clock
-----------------------------------------------------------------------------------
ddrclocks : for i in 0 to 2 generate
ddrclk_pad : aclkout port map(clk => clk90r, ddr_clk => ddr_clk(i), ddr_clkn => ddr_clkb(i));
end generate;
-----------------------------------------------------------------------------------
-- DDR single-edge control signals
-----------------------------------------------------------------------------------
-- ODT pads
odtgen : for i in 0 to 1 generate
odtl(i) <= locked and odt(i);
ddr_odt_pad : actrlout generic map(power_up => "low")
port map(clk =>clk180r , i => odtl(i), o => ddr_odt(i));
end generate;
-- CSN and CKE
ddrbanks : for i in 0 to 1 generate
ddr_csn_pad : actrlout port map(clk =>clk180r , i => csn(i), o => ddr_csb(i));
ckel(i) <= cke(i) and locked;
ddr_cke_pad : actrlout generic map(power_up => "low")
port map(clk =>clk0r , i => ckel(i), o => ddr_cke(i));
end generate;
-- RAS
ddr_rasn_pad : actrlout port map(clk =>clk180r , i => rasn, o => ddr_rasb);
-- CAS
ddr_casn_pad : actrlout port map(clk =>clk180r , i => casn, o => ddr_casb);
-- WEN
ddr_wen_pad : actrlout port map(clk =>clk180r , i => wen, o => ddr_web);
-- BA
bagen : for i in 0 to 1+eightbanks generate
ddr_ba_pad : actrlout port map(clk =>clk180r , i => ba(i), o => ddr_ba(i));
end generate;
-- ADDRESS
dagen : for i in 0 to 13 generate
ddr_ad_pad : actrlout port map(clk =>clk180r , i => addr(i), o => ddr_ad(i));
end generate;
-----------------------------------------------------------------------------------
-- DQM generation
-----------------------------------------------------------------------------------
dmgen : for i in 0 to dbits/8-1 generate
ddr_dm_pad : admout port map(
clk => clk0r, -- clk0
dm_h => dm(i+dbits/8),
dm_l => dm(i),
dm_pad => ddr_dm(i) -- DQ pad
);
end generate;
-----------------------------------------------------------------------------------
-- DQS generation (and DQ)
-----------------------------------------------------------------------------------
dqsgen : for i in 0 to dbits/8-1 generate
doen : process(clk180r)
begin
if reset = '1' then dqsoenr(i) <= '1';
elsif rising_edge(clk180r) then dqsoenr(i) <= dqsoen; end if;
end process;
dsqreg : process(clk180r)
begin if rising_edge(clk180r) then dqsn(i) <= oe; end if; end process;
-- dqs_out_pad : adqsout port map(
-- clk => clk90r, -- clk90
-- dqs => dqsn(i),
-- dqs_oe => dqsoenr(i),
-- dqs_oct => odt(0), --oct_reg(i),--gnd, -- gnd = disable
-- dqs_pad => ddr_dqs(i), -- DQS pad
-- dqsn_pad => ddr_dqsn(i) -- DQSN pad
-- );
--
-- dqs_in_pad : adqsin port map(
-- dqs_pad => ddr_dqs(i),
-- dqsn_pad => ddr_dqsn(i),
-- dqs => dqsin(i)
-- );
-- -- Dummy procces to sample dqsin
-- process(clk0r)
-- begin
-- if rising_edge(clk0r) then
-- dqsin_reg(i) <= dqsin(i);
-- end if;
-- end process;
-- altdq_dqs
bidir_dq_io_config_ena((i)*8+7 downto 0+(i)*8) <= (others => r(i).enable);
bidir_dq_oct_in((i)*8+7 downto 0+(i)*8) <= (others => oct);
bidir_dq_oe_in((i)*8+7 downto 0+(i)*8) <= (others => oen);
bidir_dq_sreset((i)*8+7 downto 0+(i)*8) <= (others => reset);
dqs_areset(i) <= reset;
dq_dqs : dq_dqs_inst port map(
bidir_dq_input_data_in => bidir_dq_input_data_in((i)*8+7 downto 0+(i)*8),
bidir_dq_input_data_out_high => dqin((i)*8+7 downto 0+(i)*8),
bidir_dq_input_data_out_low => dqin((i)*8+7+dbits downto 0+(i)*8+dbits),
bidir_dq_io_config_ena => bidir_dq_io_config_ena((i)*8+7 downto 0+(i)*8),
bidir_dq_oct_in => bidir_dq_oct_in((i)*8+7 downto 0+(i)*8),
bidir_dq_oct_out => bidir_dq_oct_out((i)*8+7 downto 0+(i)*8),
bidir_dq_oe_in => bidir_dq_oe_in((i)*8+7 downto 0+(i)*8),
bidir_dq_oe_out => bidir_dq_oe_out((i)*8+7 downto 0+(i)*8),
bidir_dq_output_data_in_high => dqout((i)*8+7+dbits downto 0+(i)*8+dbits),
bidir_dq_output_data_in_low => dqout((i)*8+7 downto 0+(i)*8),
bidir_dq_output_data_out => bidir_dq_output_data_out((i)*8+7 downto 0+(i)*8),
bidir_dq_sreset => bidir_dq_sreset((i)*8+7 downto 0+(i)*8),
config_clk => clk0r,
config_datain => r(i).sdata,
config_update => r(i).update_delay,
dq_input_reg_clk => rclk,
dq_output_reg_clk => clk0r,
dqs_areset => dqs_areset(i),
dqs_oct_in => oct,
dqs_oct_out => dqs_oct_out(i),
dqs_oe_in => dqsoenr(i),
dqs_oe_out => dqs_oe_out(i),
dqs_output_data_in_high => dqsn(i),
dqs_output_data_in_low => gnd,
dqs_output_data_out => dqs_output_data_out(i),
dqs_output_reg_clk => clk90r,
dqsn_oct_in => oct,
dqsn_oct_out => dqsn_oct_out(i),
dqsn_oe_in => dqsoenr(i),
dqsn_oe_out => dqsn_oe_out(i),
oct_reg_clk => clk90r
);
dq_pad : bidir_dq_iobuf_inst PORT map(
datain => bidir_dq_output_data_out((i)*8+7 downto 0+(i)*8),
dyn_term_ctrl => bidir_dq_oct_out((i)*8+7 downto 0+(i)*8),
oe => bidir_dq_oe_out((i)*8+7 downto 0+(i)*8),
dataio => ddr_dq((i)*8+7 downto (i)*8+0),
dataout => bidir_dq_input_data_in((i)*8+7 downto 0+(i)*8)
);
dqs_pad : bidir_dqs_iobuf_inst PORT map(
datain(0) => dqs_output_data_out(i),
dyn_term_ctrl(0) => dqs_oct_out(i),
dyn_term_ctrl_b(0) => dqsn_oct_out(i),
oe(0) => dqs_oe_out(i),
oe_b(0) => dqsn_oe_out(i),
dataio(0) => ddr_dqs(i),
dataio_b(0) => ddr_dqsn(i),
dataout(0) => dqsin(i)
);
-- Dummy procces to sample dqsin
process(clk0r)
begin
if rising_edge(clk0r) then
dqsin_reg(i) <= dqsin(i);
end if;
end process;
end generate;
-----------------------------------------------------------------------------------
-- Data bus
-----------------------------------------------------------------------------------
-- ddgen : for i in 0 to dbits-1 generate
-- -- DQ Input
-- dq_in_pad : adqin port map(
-- clk => rclk,--clk0r,
-- dq_pad => ddr_dq(i), -- DQ pad
-- dq_h => dqin(i), --dqinl(i),
-- dq_l => dqin(i+dbits),--dqin(i),
-- config_clk => clk0r,
-- config_clken => r(i/8).enable,--io_config_clkena,
-- config_datain => r(i/8).sdata,--io_config_datain,
-- config_update => r(i/8).update_delay--io_config_update
-- );
-- --dinq1 : process (clk0r)
-- --begin if rising_edge(clk0r) then dqin(i+dbits) <= dqinl(i); end if; end process;
--
-- -- DQ Output
-- dq_out_pad : adqout port map(
-- clk => clk0r, -- clk0
-- clk_oct => clk90r, -- clk90
-- dq_h => dqout(i+dbits),
-- dq_l => dqout(i),
-- dq_oe => oen,
-- dq_oct => odt(0),--gnd, -- gnd = disable
-- dq_pad => ddr_dq(i) -- DQ pad
-- );
-- end generate;
-----------------------------------------------------------------------------------
-- Delay control
-----------------------------------------------------------------------------------
delay_control : for i in 0 to dbits/8-1 generate
process(r(i),cal_en(i), cal_inc(i), delayrst(3))
variable v : phy_r_type;
variable data : std_logic_vector(0 to 3);
begin
v := r(i);
data := r(i).delay;
v.update_delay := '0';
if cal_en(i) = '1' then
if cal_inc(i) = '1' then
v.delay := r(i).delay + 1;
else
v.delay := r(i).delay - 1;
end if;
v.update := '1';
v.count := (others => '0');
end if;
if r(i).update = '1' then
v.enable := '1';
v.sdata := '0';
if r(i).count <= "1011" then
v.count := r(i).count + 1;
end if;
if r(i).count <= "0011" then
v.sdata := data(conv_integer(r(i).count));
end if;
if r(i).count = "1011" then
v.update_delay := '1';
v.enable := '0';
v.update := '0';
end if;
end if;
if delayrst(3) = '0' then
v.delay := (others => '0');
v.count := (others => '0');
v.update := '0';
v.enable := '0';
end if;
rin(i) <= v;
end process;
end generate;
process(clk0r)
begin
if locked = '0' then
delayrst <= (others => '0');
elsif rising_edge(clk0r) then
delayrst <= delayrst(2 downto 0) & '1';
r <= rin;
-- PLL phase config
-- Active puls is extended to be sampled vith scanclk = (ddr clock / 2)
--rp(0) <= cal_pll(0); rp(1) <= cal_pll(0) or rp(0);
rp(0) <= cal_pll(0); rp(1) <= rp(0); rp(2) <= rp(1); rp(3) <= cal_pll(0) or rp(0) or rp(1) or rp(2);
--rp(2) <= cal_pll(1); rp(3) <= cal_pll(1) or rp(2);
--rp(2) <= cal_pll(1); rp(4) <= cal_pll(1) or rp(2); rp(3) <= rp(4);
rp(4) <= cal_pll(1); rp(5) <= rp(4); rp(6) <= rp(5); rp(7) <= rp(6); rp(8) <= cal_pll(1) or rp(4) or rp(5) or rp(6) or rp(7);
end if;
end process;
process(lockl,clk0r)
begin
if lockl = '0' then
rlockl <= '0';
elsif rising_edge(clk0r) then
rlockl <= lockl;
end if;
end process;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/grlib/stdlib/config_types.vhd | 1 | 2411 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: config_types
-- File: config_types.vhd
-- Description: GRLIB Global configuration types package.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package config_types is
-----------------------------------------------------------------------------
-- Configuration constants part of GRLIB configuration array
-----------------------------------------------------------------------------
-- debug level and debug mask controls debug output from tech map
constant grlib_debug_level : integer := 0;
constant grlib_debug_mask : integer := 1;
-- Defines if strict RAM techmap should be used. Otherwise small (shallow)
-- RAMs may be mapped to inferred technology.
constant grlib_techmap_strict_ram : integer := 2;
-- Expand testin vector to syncrams with additional bits
constant grlib_techmap_testin_extra : integer := 3;
-- Add synchronous resets to all registers (requires support in IP cores)
constant grlib_sync_reset_enable_all : integer := 4;
-- Use asynchronous reset, with this option enabled all registers will be
-- reset using asynchronous reset (within IP cores that support this).
constant grlib_async_reset_enable : integer := 5;
type grlib_config_array_type is array (0 to 6) of integer;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gsi/ssram/functions.vhd | 6 | 97832 | -----------------------------------------------------------
-- VHDL file for FUNCTIONs used in verilog2vhdl files
-- DO NOT MODIFY THIS FILE
-- Author : S.O
-- Date : March 14, 1995
-- Modification History --
-- 3/31/95 Added shift operations (S.O)
-- 4/6/95 Added arithmetic operations for std_logic_vectors (S.O)
-- 4/11/95 Added conversion functions
-- 10/5/95 added to_boolean conversions
-- 1/31/96 added funcs. for std_logic and std_logic
-- 2/28/96 added funcs. for TERNARY combinations
-- 4/18/96 added logical operations bet. std_logic_vector and integer/boolean
-- 7/9/96 modified all TERNARY functions with *ulogic* conditional
-----------------------------------------------------------
library ieee;
library GSI;
use ieee.std_logic_1164.all;
--use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
package FUNCTIONS is
-- TYPE used in conversion function
TYPE direction is (LITTLE_ENDIAN, BIG_ENDIAN);
TYPE hex_digit IS ('0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A',
'B', 'C', 'D', 'E', 'F', 'a', 'b', 'c', 'd', 'e', 'f');
TYPE hex_number IS array (POSITIVE range <>) OF hex_digit;
TYPE hexstdlogic IS ARRAY (hex_digit'LOW TO hex_digit'HIGH) of std_logic_vector(3 DOWNTO 0);
-- This conversion table would not accept X or Z.
-- To convert a hex number with X or Z use to_stdlogicvector(hex : STRING).
--CONSTANT hex_to_stdlogic : hexstdlogic := (x"0", x"1", x"2", x"3", x"4", x"5",
-- x"6", x"7", x"8", x"9", x"A", x"B", x"C", x"D", x"E", x"F", x"A", x"B",
-- x"C", x"D", x"E", x"F");
-- Signals used for v2v
--SIGNAL v2v_std_logic : std_logic;
--SIGNAL v2v_sig_integer : integer;
--SIGNAL v2v_boolean : boolean;
--SIGNAL v2v_real : real;
-- FUNCTIONs for unary operations
FUNCTION U_AND(a : std_ulogic_vector) return std_ulogic;
FUNCTION U_AND(a : std_logic_vector) return std_logic;
FUNCTION U_NAND(a : std_ulogic_vector) return std_ulogic;
FUNCTION U_NAND(a : std_logic_vector) return std_logic;
FUNCTION U_OR(a : std_ulogic_vector) return std_ulogic;
FUNCTION U_OR(a : std_logic_vector) return std_logic;
FUNCTION U_NOR(a : std_ulogic_vector) return std_ulogic;
FUNCTION U_NOR(a : std_logic_vector) return std_logic;
FUNCTION U_XOR(a : std_ulogic_vector) return std_ulogic;
FUNCTION U_XOR(a : std_logic_vector) return std_logic;
FUNCTION U_XNOR(a : std_ulogic_vector) return std_ulogic;
FUNCTION U_XNOR(a : std_logic_vector) return std_logic;
-- FUNCTIONs for ternary operations
FUNCTION TERNARY(a,b,c : boolean) return boolean;
FUNCTION TERNARY(a : boolean; b,c : std_ulogic) return std_ulogic;
FUNCTION TERNARY(a : boolean; b,c : std_ulogic_vector) return std_ulogic_vector;
FUNCTION TERNARY(a : boolean; b,c : std_logic_vector) return std_logic_vector;
--pragma synthesis_off
FUNCTION TERNARY(a : boolean; b,c : real) return real;
FUNCTION TERNARY(a : boolean; b,c : time) return time;
--pragma synthesis_on
FUNCTION TERNARY(a,b,c : integer) return integer;
FUNCTION TERNARY(a : integer; b,c : std_ulogic) return std_ulogic;
FUNCTION TERNARY(a : integer; b,c : std_ulogic_vector) return std_ulogic_vector;
FUNCTION TERNARY(a : integer; b,c : std_logic_vector) return std_logic_vector;
--pragma synthesis_off
FUNCTION TERNARY(a : integer; b,c : real) return real;
FUNCTION TERNARY(a : integer; b,c : time) return time;
--pragma synthesis_on
FUNCTION TERNARY(a,b,c : std_ulogic) return std_ulogic;
FUNCTION TERNARY(a : std_ulogic; b,c : integer) return integer;
FUNCTION TERNARY(a : std_ulogic; b,c : std_ulogic_vector) return std_ulogic_vector;
FUNCTION TERNARY(a : std_ulogic; b,c : std_logic_vector) return std_logic_vector;
--pragma synthesis_off
FUNCTION TERNARY(a : std_ulogic; b,c : real) return real;
FUNCTION TERNARY(a : std_ulogic; b,c : time) return time;
--pragma synthesis_on
FUNCTION TERNARY(a,b,c : std_ulogic_vector) return std_ulogic_vector;
FUNCTION TERNARY(a : std_ulogic_vector; b,c : integer) return integer;
FUNCTION TERNARY(a : std_ulogic_vector; b,c : std_ulogic) return std_ulogic;
FUNCTION TERNARY(a : std_ulogic_vector; b,c : std_logic_vector) return std_logic_vector;
--pragma synthesis_off
FUNCTION TERNARY(a : std_ulogic_vector; b,c : real) return real;
FUNCTION TERNARY(a : std_ulogic_vector; b,c : time) return time;
--pragma synthesis_on
FUNCTION TERNARY(a,b,c : std_logic_vector) return std_logic_vector;
FUNCTION TERNARY(a : std_logic_vector; b,c : integer) return integer;
FUNCTION TERNARY(a : std_logic_vector; b,c : std_ulogic) return std_ulogic;
FUNCTION TERNARY(a : std_logic_vector; b,c : std_ulogic_vector) return std_ulogic_vector;
--pragma synthesis_off
FUNCTION TERNARY(a : std_logic_vector; b,c : real) return real;
FUNCTION TERNARY(a : std_logic_vector; b,c : time) return time;
FUNCTION TERNARY(a,b,c : real) return real;
FUNCTION TERNARY(a : real; b,c : std_ulogic) return std_ulogic;
FUNCTION TERNARY(a : real; b,c : std_ulogic_vector) return std_ulogic_vector;
FUNCTION TERNARY(a : real; b,c : std_logic_vector) return std_logic_vector;
FUNCTION TERNARY(a : real; b,c : integer) return integer;
FUNCTION TERNARY(a : real; b,c : time) return time;
--pragma synthesis_on
-- functions for TERNARY combination
FUNCTION TERNARY(a : std_ulogic; b : std_logic_vector; c: std_ulogic) return
std_logic_vector;
FUNCTION TERNARY(a : std_ulogic; b : std_ulogic; c: std_logic_vector) return
std_logic_vector;
FUNCTION TERNARY(a : std_ulogic; b : integer; c: std_ulogic) return
integer;
FUNCTION TERNARY(a : std_ulogic; b : std_ulogic; c: integer) return
integer;
FUNCTION TERNARY(a : integer; b : integer; c: std_ulogic) return
integer;
FUNCTION TERNARY(a : integer; b : std_ulogic; c: integer) return
integer;
FUNCTION TERNARY(a : integer; b : std_logic_vector; c: std_ulogic) return
std_logic_vector;
FUNCTION TERNARY(a : integer; b : std_ulogic; c: std_logic_vector) return
std_logic_vector;
--end functions for TERNARY combination
-- FUNCTIONS for shift operations
FUNCTION "sll" ( l : std_logic_vector; r : integer) RETURN std_logic_vector;
FUNCTION "sll" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector;
FUNCTION "srl" ( l : std_logic_vector; r : integer) RETURN std_logic_vector;
FUNCTION "srl" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector;
FUNCTION "sla" ( l : std_logic_vector; r : integer) RETURN std_logic_vector;
FUNCTION "sla" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector;
FUNCTION "sra" ( l : std_logic_vector; r : integer) RETURN std_logic_vector;
FUNCTION "sra" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector;
FUNCTION "rol" ( l : std_logic_vector; r : integer) RETURN std_logic_vector;
FUNCTION "rol" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector;
FUNCTION "ror" ( l : std_logic_vector; r : integer) RETURN std_logic_vector;
FUNCTION "ror" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector;
-- FUNCTIONs for integer operations
FUNCTION "not" (l: integer) return integer;
FUNCTION "and" (l,r: integer) return integer;
FUNCTION "nand" (l,r: integer) return integer;
FUNCTION "or" (l,r: integer) return integer;
FUNCTION "nor" (l,r: integer) return integer;
FUNCTION "xor" (l,r: integer) return integer;
FUNCTION "xnor" (l,r: integer) return integer;
FUNCTION "sll" (l,r: integer) return integer;
FUNCTION "srl" (l,r: integer) return integer;
-- FUNCTIONs for std_logic/std_ulogic_vector/std_logic_vector operations
-- FUNCTIONs for combination of Boolean and ints
FUNCTION "=" ( l : Boolean; r : natural ) RETURN boolean;
FUNCTION "/=" ( l : Boolean; r : natural ) RETURN boolean;
FUNCTION "=" ( l : integer; r : std_logic_vector ) RETURN boolean;
FUNCTION "/=" ( l : integer; r : std_logic_vector ) RETURN boolean;
FUNCTION "<" ( l : integer; r : std_logic_vector ) RETURN boolean;
FUNCTION ">" ( l : integer; r : std_logic_vector ) RETURN boolean;
FUNCTION "<=" ( l : integer; r : std_logic_vector ) RETURN boolean;
FUNCTION ">=" ( l : integer; r : std_logic_vector ) RETURN boolean;
FUNCTION "=" ( l : std_logic_vector; r : integer ) RETURN boolean;
FUNCTION "/=" ( l : std_logic_vector; r : integer ) RETURN boolean;
FUNCTION "<" ( l : std_logic_vector; r : integer ) RETURN boolean;
FUNCTION ">" ( l : std_logic_vector; r : integer ) RETURN boolean;
FUNCTION "<=" ( l : std_logic_vector; r : integer ) RETURN boolean;
FUNCTION ">=" ( l : std_logic_vector; r : integer ) RETURN boolean;
--logical functions between std_logic_vector and integer, std_logic_vector and boolean
FUNCTION "and" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector;
FUNCTION "nand" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector;
FUNCTION "or" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector;
FUNCTION "nor" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector;
FUNCTION "xor" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector;
FUNCTION "and" ( l : integer; r : std_logic_vector ) RETURN integer;
FUNCTION "nand" ( l : integer; r : std_logic_vector ) RETURN integer;
FUNCTION "or" ( l : integer; r : std_logic_vector ) RETURN integer;
FUNCTION "nor" ( l : integer; r : std_logic_vector ) RETURN integer;
FUNCTION "xor" ( l : integer; r : std_logic_vector ) RETURN integer;
FUNCTION "and" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector;
FUNCTION "nand" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector;
FUNCTION "or" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector;
FUNCTION "nor" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector;
FUNCTION "xor" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector;
FUNCTION "and" ( l : boolean; r : std_logic_vector ) RETURN boolean;
FUNCTION "nand" ( l : boolean; r : std_logic_vector ) RETURN boolean;
FUNCTION "or" ( l : boolean; r : std_logic_vector ) RETURN boolean;
FUNCTION "nor" ( l : boolean; r : std_logic_vector ) RETURN boolean;
FUNCTION "xor" ( l : boolean; r : std_logic_vector ) RETURN boolean;
--logical functions between std_logic_vector and integer, std_logic_vector and boolean
-- Added functions for std_logic, integer
FUNCTION "=" ( l : std_logic; r : integer ) RETURN boolean;
FUNCTION "/=" ( l : std_logic; r : integer ) RETURN boolean;
FUNCTION "<" ( l : std_logic; r : integer ) RETURN boolean;
FUNCTION ">" ( l : std_logic; r : integer ) RETURN boolean;
FUNCTION "<=" ( l : std_logic; r : integer ) RETURN boolean;
FUNCTION ">=" ( l : std_logic; r : integer ) RETURN boolean;
-- Functions for std_logic, integer
--pragma synthesis_off
-- arithmetic operations for real and int and int and real
FUNCTION "+" ( l : real; r : integer ) RETURN real;
FUNCTION "-" ( l : real; r : integer ) RETURN real;
FUNCTION "/" ( l : real; r : integer ) RETURN real;
FUNCTION "*" ( l : real; r : integer ) RETURN real;
FUNCTION "+" ( l : integer; r : real ) RETURN real;
FUNCTION "-" ( l : integer; r : real ) RETURN real;
FUNCTION "/" ( l : integer; r : real ) RETURN real;
FUNCTION "*" ( l : integer; r : real ) RETURN real;
-- end arithmetic operations for real and int and int and real
FUNCTION "=" ( l : real; r : integer ) RETURN boolean;
FUNCTION "/=" ( l : real; r : integer ) RETURN boolean;
FUNCTION "<" ( l : real; r : integer ) RETURN boolean;
FUNCTION ">" ( l : real; r : integer ) RETURN boolean;
FUNCTION "<=" ( l : real; r : integer ) RETURN boolean;
FUNCTION ">=" ( l : real; r : integer ) RETURN boolean;
FUNCTION "=" ( l : integer; r : real ) RETURN boolean;
FUNCTION "/=" ( l : integer; r : real ) RETURN boolean;
FUNCTION "<" ( l : integer; r : real ) RETURN boolean;
FUNCTION ">" ( l : integer; r : real ) RETURN boolean;
FUNCTION "<=" ( l : integer; r : real ) RETURN boolean;
FUNCTION ">=" ( l : integer; r : real ) RETURN boolean;
--pragma synthesis_on
FUNCTION "+" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "-" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "*" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "/" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "REM" ( l, r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "+" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector;
FUNCTION "-" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector;
FUNCTION "*" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector;
FUNCTION "/" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector;
FUNCTION "REM" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector;
FUNCTION "&" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector;
FUNCTION "&" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector;
-- need logical functions bet. std_logic_vector and std_logic
FUNCTION "and" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector;
FUNCTION "nand" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector;
FUNCTION "or" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector;
FUNCTION "nor" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector;
FUNCTION "xor" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector;
--FUNCTION "xnor" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector;
FUNCTION "and" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "nand" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "or" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "nor" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "xor" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector;
--FUNCTION "xnor" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector;
-- end logical functions for std_logic_vector and std_logic
-- need arith functions bet std_logic and std_logic
-- used only when the int can be 0 or 1
-- need arithmetic functions bet. std_logic_vector and std_logic
FUNCTION "+" ( l : std_logic; r : std_logic ) RETURN std_logic;
FUNCTION "-" ( l : std_logic; r : std_logic ) RETURN std_logic;
FUNCTION "*" ( l : std_logic; r : std_logic ) RETURN std_logic;
FUNCTION "/" ( l : std_logic; r : std_logic ) RETURN std_logic;
FUNCTION "REM" ( l : std_logic; r : std_logic ) RETURN std_logic;
-- need arithmetic functions bet. std_logic_vector and std_logic
FUNCTION "+" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector;
FUNCTION "-" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector;
FUNCTION "*" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector;
FUNCTION "/" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector;
FUNCTION "REM" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector;
-- need arithmetic func. between std_logic and std_logic_vector, caveat, returns type of 'r'
FUNCTION "+" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "-" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "*" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "/" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "REM" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector;
FUNCTION "+" ( l : integer; r : std_logic_vector ) RETURN integer;
FUNCTION "-" ( l : integer; r : std_logic_vector ) RETURN integer;
FUNCTION "*" ( l : integer; r : std_logic_vector ) RETURN integer;
FUNCTION "/" ( l : integer; r : std_logic_vector ) RETURN integer;
FUNCTION "REM" ( l : integer; r : std_logic_vector ) RETURN integer;
-- need arith. functions bet std_logic and integer
FUNCTION "+" ( l : std_logic; r : integer ) RETURN integer;
FUNCTION "-" ( l : std_logic; r : integer ) RETURN integer;
FUNCTION "*" ( l : std_logic; r : integer ) RETURN integer;
FUNCTION "/" ( l : std_logic; r : integer ) RETURN integer;
FUNCTION "REM" ( l : std_logic; r : integer ) RETURN integer;
FUNCTION "and" ( l : std_logic; r : integer ) RETURN std_logic;
FUNCTION "nand" ( l : std_logic; r : integer ) RETURN std_logic;
FUNCTION "or" ( l : std_logic; r : integer ) RETURN std_logic;
FUNCTION "nor" ( l : std_logic; r : integer ) RETURN std_logic;
FUNCTION "xor" ( l : std_logic; r : integer ) RETURN std_logic;
FUNCTION "&" ( l : std_logic; r : integer ) RETURN std_logic_vector;
FUNCTION "xnor" ( l : std_logic; r : integer ) RETURN std_logic;
FUNCTION "and" ( l : integer; r : std_logic ) RETURN integer;
FUNCTION "nand" ( l : integer; r : std_logic ) RETURN integer;
FUNCTION "or" ( l : integer; r : std_logic ) RETURN integer;
FUNCTION "nor" ( l : integer; r : std_logic ) RETURN integer;
FUNCTION "xor" ( l : integer; r : std_logic ) RETURN integer;
FUNCTION "&" ( l : integer; r : std_logic ) RETURN std_logic_vector;
FUNCTION "xnor" ( l : integer; r : std_logic ) RETURN integer;
-- need functions for operations between std_logic and integer
FUNCTION "+" ( l : integer; r : std_logic ) RETURN integer;
FUNCTION "-" ( l : integer; r : std_logic ) RETURN integer;
FUNCTION "*" ( l : integer; r : std_logic ) RETURN integer;
FUNCTION "/" ( l : integer; r : std_logic ) RETURN integer;
FUNCTION "REM" ( l : integer; r : std_logic ) RETURN integer;
FUNCTION "and" ( l : std_logic; r : boolean ) RETURN std_logic;
FUNCTION "nand" ( l : std_logic; r : boolean ) RETURN std_logic;
FUNCTION "or" ( l : std_logic; r : boolean ) RETURN std_logic;
FUNCTION "nor" ( l : std_logic; r : boolean ) RETURN std_logic;
FUNCTION "xor" ( l : std_logic; r : boolean ) RETURN std_logic;
FUNCTION "&" ( l : std_logic; r : boolean ) RETURN std_logic_vector;
FUNCTION "xnor" ( l : std_logic; r : boolean ) RETURN std_logic;
FUNCTION "and" ( l : boolean; r : std_logic ) RETURN boolean;
FUNCTION "nand" ( l : boolean; r : std_logic ) RETURN boolean;
FUNCTION "or" ( l : boolean; r : std_logic ) RETURN boolean;
FUNCTION "nor" ( l : boolean; r : std_logic ) RETURN boolean;
FUNCTION "xor" ( l : boolean; r : std_logic ) RETURN boolean;
FUNCTION "&" ( l : boolean; r : std_logic ) RETURN std_logic_vector;
FUNCTION "xnor" ( l : boolean; r : std_logic ) RETURN boolean;
FUNCTION "and" ( l : integer; r : boolean ) RETURN integer;
FUNCTION "nand" ( l : integer; r : boolean ) RETURN integer;
FUNCTION "or" ( l : integer; r : boolean ) RETURN integer;
FUNCTION "nor" ( l : integer; r : boolean ) RETURN integer;
FUNCTION "xor" ( l : integer; r : boolean ) RETURN integer;
FUNCTION "&" ( l : integer; r : boolean ) RETURN std_logic_vector;
FUNCTION "xnor" ( l : integer; r : boolean ) RETURN integer;
FUNCTION "and" ( l : boolean; r : integer ) RETURN boolean;
FUNCTION "nand" ( l : boolean; r : integer ) RETURN boolean;
FUNCTION "or" ( l : boolean; r : integer ) RETURN boolean;
FUNCTION "nor" ( l : boolean; r : integer ) RETURN boolean;
FUNCTION "xor" ( l : boolean; r : integer ) RETURN boolean;
FUNCTION "&" ( l : boolean; r : integer ) RETURN std_logic_vector;
FUNCTION "xnor" ( l : boolean; r : integer ) RETURN boolean;
-- Overloaded function for text output
FUNCTION to_bitvector ( a : bit ) RETURN bit_vector;
FUNCTION to_bitvector ( a : std_ulogic ) RETURN bit_vector;
FUNCTION to_bitvector ( a : integer ) RETURN bit_vector;
--Conversion functions
FUNCTION to_stdlogicvector(l : integer; size : natural; dir : direction := LITTLE_ENDIAN) RETURN std_logic_vector;
FUNCTION to_stdlogicvector(l : std_logic_vector) RETURN std_logic_vector;
FUNCTION to_stdlogicvector(l : std_logic_vector; size : natural;dir : direction := little_endian ) RETURN std_logic_vector;
FUNCTION to_stdlogicvector ( hex : STRING ) RETURN std_logic_vector;
FUNCTION to_stdlogicvector(l : std_logic; size : natural) RETURN std_logic_vector;
FUNCTION to_stdlogicvector(l : boolean; size : natural) RETURN std_logic_vector;
FUNCTION to_integer(l : std_logic_vector; dir : direction := little_endian) RETURN integer;
FUNCTION to_integer(l : integer) RETURN integer;
FUNCTION to_integer(l : std_logic) RETURN integer;
FUNCTION to_integer(l : boolean) RETURN integer;
-- functions for resolving ambiguity
FUNCTION v2v_to_integer(l : std_logic_vector; dir : direction := little_endian) RETURN integer;
FUNCTION v2v_to_integer(l : integer) RETURN integer;
FUNCTION v2v_to_integer(l : std_logic) RETURN integer;
FUNCTION v2v_to_integer(l : boolean) RETURN integer;
FUNCTION to_stdlogic(l : integer) RETURN std_logic;
FUNCTION to_stdlogic(l : Boolean) RETURN std_logic;
FUNCTION to_stdlogic(l : std_logic) RETURN std_logic;
FUNCTION to_stdlogic(l : std_logic_vector) RETURN std_logic;
--pragma synthesis_off
FUNCTION to_real(l : integer) RETURN real;
FUNCTION to_real (l : real) RETURN real;
--pragma synthesis_on
FUNCTION to_boolean(l : std_logic) RETURN boolean;
FUNCTION to_boolean(l : integer) RETURN boolean;
FUNCTION to_boolean(l : std_logic_vector) RETURN boolean;
FUNCTION to_boolean(l : boolean) RETURN boolean;
end FUNCTIONS;
library ieee;
library GSI;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library grlib;
--use grlib.stdlib.all;
Package body FUNCTIONS is
--============= Local Subprograms (from numeric_std.vhd)=====================
function MAX (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end MAX;
function MIN (LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT < RIGHT then return LEFT;
else return RIGHT;
end if;
end MIN;
-- unary operations
TYPE stdlogic_boolean_table is array(std_ulogic, std_ulogic) of boolean;
TYPE stdlogic_1d IS ARRAY (std_ulogic) OF std_ulogic;
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
FUNCTION U_AND(a : std_ulogic_vector) return std_ulogic is
VARIABLE result : std_ulogic := '1';
begin
FOR i in a'RANGE LOOP
result := result and a(i);
END LOOP;
return result;
end U_AND;
FUNCTION U_AND(a : std_logic_vector) return std_logic is
VARIABLE result : std_logic := '1';
begin
FOR i in a'RANGE LOOP
result := result and a(i);
END LOOP;
return result;
end U_AND;
FUNCTION U_NAND(a : std_ulogic_vector) return std_ulogic is
VARIABLE result : std_ulogic := '1';
begin
FOR i in a'RANGE LOOP
result := result and a(i);
END LOOP;
return not(result);
end U_NAND;
FUNCTION U_NAND(a : std_logic_vector) return std_logic is
VARIABLE result : std_logic := '1';
begin
FOR i in a'RANGE LOOP
result := result and a(i);
END LOOP;
return not(result);
end U_NAND;
FUNCTION U_OR(a : std_ulogic_vector) return std_ulogic is
VARIABLE result : std_ulogic := '0';
begin
FOR i in a'RANGE LOOP
result := result or a(i);
END LOOP;
return result;
end U_OR;
FUNCTION U_OR(a : std_logic_vector) return std_logic is
VARIABLE result : std_logic := '0';
begin
FOR i in a'RANGE LOOP
result := result or a(i);
END LOOP;
return result;
end U_OR;
FUNCTION U_NOR(a : std_ulogic_vector) return std_ulogic is
VARIABLE result : std_ulogic := '0';
begin
FOR i in a'RANGE LOOP
result := result or a(i);
END LOOP;
return not(result);
end U_NOR;
FUNCTION U_NOR(a : std_logic_vector) return std_logic is
VARIABLE result : std_logic := '0';
begin
FOR i in a'RANGE LOOP
result := result or a(i);
END LOOP;
return not(result);
end U_NOR;
FUNCTION U_XOR(a : std_ulogic_vector) return std_ulogic is
VARIABLE result : std_ulogic := '0';
begin
FOR i in a'RANGE LOOP
result := result xor a(i);
END LOOP;
return result;
end U_XOR;
FUNCTION U_XOR(a : std_logic_vector) return std_logic is
VARIABLE result : std_logic := '0';
begin
FOR i in a'RANGE LOOP
result := result xor a(i);
END LOOP;
return result;
end U_XOR;
FUNCTION U_XNOR(a : std_ulogic_vector) return std_ulogic is
VARIABLE result : std_ulogic := '0';
begin
FOR i in a'RANGE LOOP
result := result xor a(i);
END LOOP;
return not(result);
end U_XNOR;
FUNCTION U_XNOR(a : std_logic_vector) return std_logic is
VARIABLE result : std_logic := '0';
begin
FOR i in a'RANGE LOOP
result := result xor a(i);
END LOOP;
return not(result);
end U_XNOR;
-- ternary operations
FUNCTION TERNARY(a,b,c : boolean) return boolean IS
begin
IF a = TRUE THEN
RETURN b;
ELSE
RETURN c;
END IF;
end TERNARY;
---------------------------------------------------
FUNCTION TERNARY(a : boolean; b,c : std_ulogic) return std_ulogic IS
begin
IF a = TRUE THEN
RETURN b;
ELSE
RETURN c;
END IF;
end TERNARY;
---------------------------------------------------
FUNCTION TERNARY(a : boolean; b,c : std_ulogic_vector) return std_ulogic_vector IS
begin
IF a = TRUE THEN
RETURN b;
ELSE
RETURN c;
END IF;
end TERNARY;
---------------------------------------------------
FUNCTION TERNARY(a : boolean; b,c : std_logic_vector) return std_logic_vector IS
begin
IF a = TRUE THEN
RETURN b;
ELSE
RETURN c;
END IF;
end TERNARY;
--pragma synthesis_off
---------------------------------------------------
FUNCTION TERNARY(a : boolean; b,c : real) return real IS
begin
IF a = TRUE THEN
RETURN b;
ELSE
RETURN c;
END IF;
end TERNARY;
---------------------------------------------------
FUNCTION TERNARY(a : boolean; b,c : time) return time IS
begin
IF a = TRUE THEN
RETURN b;
ELSE
RETURN c;
END IF;
end TERNARY;
--pragma synthesis_on
---------------------------------------------------
FUNCTION TERNARY(a,b,c : integer) return integer is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : integer; b,c : std_ulogic) return std_ulogic is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : integer; b,c : std_ulogic_vector) return std_ulogic_vector is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : integer; b,c : std_logic_vector) return std_logic_vector is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
--pragma synthesis_off
FUNCTION TERNARY(a : integer; b,c : real) return real is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : integer; b,c : time) return time is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
--pragma synthesis_on
FUNCTION TERNARY(a,b,c : std_ulogic) return std_ulogic is
begin
IF (a = '1') THEN
return b;
ELSIF (a = '0') THEN
return c;
--pragma synthesis_off
ELSIF (b = c AND NOT Is_X(b)) THEN
return b;
ELSE
return 'X';
--pragma synthesis_on
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_ulogic; b,c : integer) return integer is
begin
IF (a = '1') THEN
return b;
ELSIF (a = '0') THEN
return c;
--pragma synthesis_off
ELSIF (b = c) THEN
return b;
ELSE
return 0;
--pragma synthesis_on
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_ulogic; b,c : std_ulogic_vector) return std_ulogic_vector is
--pragma synthesis_off
constant SIZE: NATURAL := MAX(b'LENGTH, c'LENGTH);
variable b01 : std_ulogic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable c01 : std_ulogic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable result : std_ulogic_vector(SIZE-1 downto 0);
--pragma synthesis_on
begin
IF (a = '1') THEN
return b;
ELSIF (a = '0') THEN
return c;
--pragma synthesis_off
ELSIF (b = c AND NOT Is_X(b)) THEN
return b;
ELSE
b01(b'LENGTH-1 downto 0) := b;
c01(c'LENGTH-1 downto 0) := c;
FOR I IN SIZE-1 DOWNTO 0 LOOP
IF (b01(I) = c01(I) AND NOT Is_X(b01(I))) THEN
result(I) := b01(I);
ELSE
result(I) := 'X';
END IF;
END LOOP;
return result;
--pragma synthesis_on
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_ulogic; b,c : std_logic_vector) return std_logic_vector is
--pragma synthesis_off
constant SIZE: NATURAL := MAX(b'LENGTH, c'LENGTH);
variable b01 : std_logic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable c01 : std_logic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable result : std_logic_vector(SIZE-1 downto 0);
--pragma synthesis_on
begin
IF (a = '1') THEN
return b;
ELSIF (a = '0') THEN
return c;
--pragma synthesis_off
ELSIF (b = c AND NOT Is_X(b)) THEN
return b;
ELSE
b01(b'LENGTH-1 downto 0) := b;
c01(c'LENGTH-1 downto 0) := c;
FOR I IN SIZE-1 DOWNTO 0 LOOP
IF (b01(I) = c01(I) AND NOT Is_X(b01(I))) THEN
result(I) := b01(I);
ELSE
result(I) := 'X';
END IF;
END LOOP;
return result;
--pragma synthesis_on
END IF;
end TERNARY;
--pragma synthesis_off
FUNCTION TERNARY(a : std_ulogic; b,c : real) return real is
begin
IF (a = '1') THEN
return b;
ELSIF (a = '0') THEN
return c;
ELSIF (b = c) THEN
return b;
ELSE
return 0.0;
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_ulogic; b,c : time) return time is
begin
IF (a = '1') THEN
return b;
ELSIF (a = '0') THEN
return c;
ELSIF (b = c) THEN
return b;
ELSE
return 0 ns;
END IF;
end TERNARY;
--pragma synthesis_on
FUNCTION TERNARY(a,b,c : std_ulogic_vector) return std_ulogic_vector is
--pragma synthesis_off
constant SIZE: NATURAL := MAX(b'LENGTH, c'LENGTH);
variable b01 : std_ulogic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable c01 : std_ulogic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable result : std_ulogic_vector(SIZE-1 downto 0);
--pragma synthesis_on
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
--pragma synthesis_off
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE
b01(b'LENGTH-1 downto 0) := b;
c01(c'LENGTH-1 downto 0) := c;
FOR I IN SIZE-1 DOWNTO 0 LOOP
IF (b01(I) = c01(I) AND NOT Is_X(b01(I))) THEN
result(I) := b01(I);
ELSE
result(I) := 'X';
END IF;
END LOOP;
return result;
END IF;
--pragma synthesis_on
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_ulogic_vector; b,c : integer) return integer is
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
--pragma synthesis_off
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE return 0;
END IF;
--pragma synthesis_on
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_ulogic_vector; b,c : std_ulogic) return std_ulogic is
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
--pragma synthesis_off
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE return 'X';
END IF;
--pragma synthesis_on
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_ulogic_vector; b,c : std_logic_vector) return std_logic_vector is
--pragma synthesis_off
constant SIZE: NATURAL := MAX(b'LENGTH, c'LENGTH);
variable b01 : std_logic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable c01 : std_logic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable result : std_logic_vector(SIZE-1 downto 0);
--pragma synthesis_on
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
--pragma synthesis_off
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE
b01(b'LENGTH-1 downto 0) := b;
c01(c'LENGTH-1 downto 0) := c;
FOR I IN SIZE-1 DOWNTO 0 LOOP
IF (b01(I) = c01(I) AND NOT Is_X(b01(I))) THEN
result(I) := b01(I);
ELSE
result(I) := 'X';
END IF;
END LOOP;
return result;
END IF;
--pragma synthesis_on
ELSE
return c;
END IF;
end TERNARY;
--pragma synthesis_off
FUNCTION TERNARY(a : std_ulogic_vector; b,c : real) return real is
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE return 0.0;
END IF;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_ulogic_vector; b,c : time) return time is
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE return 0 ns;
END IF;
ELSE
return c;
END IF;
end TERNARY;
--pragma synthesis_on
FUNCTION TERNARY(a,b,c : std_logic_vector) return std_logic_vector is
--pragma synthesis_off
constant SIZE: NATURAL := MAX(b'LENGTH, c'LENGTH);
variable b01 : std_logic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable c01 : std_logic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable result : std_logic_vector(SIZE-1 downto 0);
--pragma synthesis_on
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
--pragma synthesis_off
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE
b01(b'LENGTH-1 downto 0) := b;
c01(c'LENGTH-1 downto 0) := c;
FOR I IN SIZE-1 DOWNTO 0 LOOP
IF (b01(I) = c01(I) AND NOT Is_X(b01(I))) THEN
result(I) := b01(I);
ELSE
result(I) := 'X';
END IF;
END LOOP;
return result;
END IF;
--pragma synthesis_on
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_logic_vector; b,c : integer) return integer is
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
--pragma synthesis_off
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE return 0;
END IF;
--pragma synthesis_on
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_logic_vector; b,c : std_ulogic) return std_ulogic is
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
--pragma synthesis_off
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE return 'X';
END IF;
--pragma synthesis_on
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_logic_vector; b,c : std_ulogic_vector) return std_ulogic_vector is
--pragma synthesis_off
constant SIZE: NATURAL := MAX(b'LENGTH, c'LENGTH);
variable b01 : std_ulogic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable c01 : std_ulogic_vector(SIZE-1 downto 0) := (OTHERS => '0');
variable result : std_ulogic_vector(SIZE-1 downto 0);
--pragma synthesis_on
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
--pragma synthesis_off
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE
b01(b'LENGTH-1 downto 0) := b;
c01(c'LENGTH-1 downto 0) := c;
FOR I IN SIZE-1 DOWNTO 0 LOOP
IF (b01(I) = c01(I) AND NOT Is_X(b01(I))) THEN
result(I) := b01(I);
ELSE
result(I) := 'X';
END IF;
END LOOP;
return result;
END IF;
--pragma synthesis_on
ELSE
return c;
END IF;
end TERNARY;
--pragma synthesis_off
FUNCTION TERNARY(a : std_logic_vector; b,c : real) return real is
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE return 0.0;
END IF;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : std_logic_vector; b,c : time) return time is
begin
IF to_boolean(to_stdlogicvector(to_bitvector(a))) THEN
return b;
ELSIF (Is_X(a)) THEN
IF (b = c) THEN return b;
ELSE return 0 ns;
END IF;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a,b,c : real) return real is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : real; b,c : std_ulogic) return std_ulogic is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : real; b,c : std_ulogic_vector) return std_ulogic_vector is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : real; b,c : std_logic_vector) return std_logic_vector is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : real; b,c : integer) return integer is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
FUNCTION TERNARY(a : real; b,c : time) return time is
begin
IF (a /= 0) THEN
return b;
ELSE
return c;
END IF;
end TERNARY;
--pragma synthesis_on
-- functions for TERNARY combination
FUNCTION TERNARY(a : std_ulogic; b : std_logic_vector; c: std_ulogic) return
std_logic_vector IS
variable c01 : std_logic_vector(b'LENGTH-1 downto 0) := (OTHERS => '0');
--pragma synthesis_off
variable b01 : std_logic_vector(b'LENGTH-1 downto 0) := b;
variable result : std_logic_vector(b'LENGTH-1 downto 0);
--pragma synthesis_on
BEGIN
c01(0) := c;
IF (a = '1') THEN
return b;
ELSIF (a = '0') THEN
return c01;
--pragma synthesis_off
ELSIF (b01 = c01 AND NOT Is_X(b)) THEN
return b;
ELSE
FOR I IN b'LENGTH-1 DOWNTO 0 LOOP
IF (b01(I) = c01(I) AND NOT Is_X(b01(I))) THEN
result(I) := b01(I);
ELSE
result(I) := 'X';
END IF;
END LOOP;
return result;
--pragma synthesis_on
END IF;
END TERNARY;
FUNCTION TERNARY(a : std_ulogic; b : std_ulogic; c: std_logic_vector) return
std_logic_vector IS
variable b01 : std_logic_vector(c'LENGTH-1 downto 0) := (OTHERS => '0');
--pragma synthesis_off
variable c01 : std_logic_vector(c'LENGTH-1 downto 0) := c;
variable result : std_logic_vector(c'LENGTH-1 downto 0);
--pragma synthesis_on
BEGIN
b01(0) := b;
IF (a = '1') THEN
return b01;
ELSIF (a = '0') THEN
return c;
--pragma synthesis_off
ELSIF (b01 = c01 AND NOT Is_X(b01)) THEN
return b01;
ELSE
FOR I IN c'LENGTH-1 DOWNTO 0 LOOP
IF (b01(I) = c01(I) AND NOT Is_X(b01(I))) THEN
result(I) := b01(I);
ELSE
result(I) := 'X';
END IF;
END LOOP;
return result;
--pragma synthesis_on
END IF;
END TERNARY;
FUNCTION TERNARY(a : std_ulogic; b : integer; c: std_ulogic) return
integer IS
BEGIN
IF (a = '0') THEN
return to_integer(c);
ELSIF (a = '1') THEN
return b;
--pragma synthesis_off
ELSIF (b = to_integer(c) AND NOT Is_X(c)) THEN
return b;
ELSE
return 0;
--pragma synthesis_on
END IF;
END TERNARY;
FUNCTION TERNARY(a : std_ulogic; b : std_ulogic; c: integer) return
integer IS
BEGIN
IF (a = '0') THEN
return c;
ELSIF (a = '1') THEN
return to_integer(b);
--pragma synthesis_off
ELSIF (to_integer(b) = c AND NOT Is_X(b)) THEN
return c;
ELSE
return 0;
--pragma synthesis_on
END IF;
END TERNARY;
FUNCTION TERNARY(a : integer; b : integer; c: std_ulogic) return
integer IS
BEGIN
IF (a /= 0) THEN
return b;
ELSE
return to_integer(c);
END IF;
END TERNARY;
FUNCTION TERNARY(a : integer; b : std_ulogic; c: integer) return
integer IS
BEGIN
IF (a /= 0) THEN
return to_integer(b);
ELSE
return c;
END IF;
END TERNARY;
FUNCTION TERNARY(a : integer; b : std_logic_vector; c: std_ulogic) return
std_logic_vector IS
VARIABLE temp : std_logic_vector(0 downto 0);
BEGIN
IF (a /= 0) THEN
return b;
ELSE
temp(0) := c;
return temp;
END IF;
END TERNARY;
FUNCTION TERNARY(a : integer; b : std_ulogic; c: std_logic_vector) return
std_logic_vector IS
VARIABLE temp : std_logic_vector(0 downto 0);
BEGIN
IF (a /= 0) THEN
temp(0) := b;
return temp;
ELSE
return c;
END IF;
END TERNARY;
--end functions for TERNARY combination
-- FUNCTIONS for integer operations
FUNCTION "not" (l: integer) return integer is
VARIABLE temp : SIGNED(31 downto 0) := TO_SIGNED(l,32);
begin
return TO_INTEGER(NOT(temp));
end "not";
FUNCTION "and" (l,r: integer) return integer is
VARIABLE temp1 : SIGNED(31 downto 0) := TO_SIGNED(l,32);
VARIABLE temp2 : SIGNED(31 downto 0) := TO_SIGNED(r,32);
begin
return TO_INTEGER(temp1 AND temp2);
end "and";
FUNCTION "nand" (l,r: integer) return integer is
VARIABLE temp1 : SIGNED(31 downto 0) := TO_SIGNED(l,32);
VARIABLE temp2 : SIGNED(31 downto 0) := TO_SIGNED(r,32);
begin
return TO_INTEGER(temp1 NAND temp2);
end "nand";
FUNCTION "or" (l,r: integer) return integer is
VARIABLE temp1 : SIGNED(31 downto 0) := TO_SIGNED(l,32);
VARIABLE temp2 : SIGNED(31 downto 0) := TO_SIGNED(r,32);
begin
return TO_INTEGER(temp1 OR temp2);
end "or";
FUNCTION "nor" (l,r: integer) return integer is
VARIABLE temp1 : SIGNED(31 downto 0) := TO_SIGNED(l,32);
VARIABLE temp2 : SIGNED(31 downto 0) := TO_SIGNED(r,32);
begin
return TO_INTEGER(temp1 NOR temp2);
end "nor";
FUNCTION "xor" (l,r: integer) return integer is
VARIABLE temp1 : SIGNED(31 downto 0) := TO_SIGNED(l,32);
VARIABLE temp2 : SIGNED(31 downto 0) := TO_SIGNED(r,32);
begin
return TO_INTEGER(temp1 XOR temp2);
end "xor";
FUNCTION "xnor" (l,r: integer) return integer is
VARIABLE temp1 : SIGNED(31 downto 0) := TO_SIGNED(l,32);
VARIABLE temp2 : SIGNED(31 downto 0) := TO_SIGNED(r,32);
begin
return TO_INTEGER(temp1 XNOR temp2);
end "xnor";
FUNCTION "sll" (l,r: integer) return integer is
VARIABLE temp1 : SIGNED(31 downto 0) := TO_SIGNED(l,32);
begin
return TO_INTEGER(temp1 SLL r);
end "sll";
FUNCTION "srl" (l,r: integer) return integer is
VARIABLE temp1 : SIGNED(31 downto 0) := TO_SIGNED(l,32);
begin
return TO_INTEGER(temp1 SRL r);
end "srl";
-- functions for std_ulogic operations
-- first add all the tables needed
-- truth table for "=" function
CONSTANT eq_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 0 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | L |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
-- truth table for "/=" function
CONSTANT neq_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 0 |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | L |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
-- truth table for "<" function
CONSTANT ltb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 0 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | L |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
-- truth table for ">" function
CONSTANT gtb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | 0 |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ), -- | L |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE ) -- | D |
);
-- truth table for "<=" function
CONSTANT leb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | U |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | X |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | 0 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | 1 |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | Z |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | W |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | L |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ), -- | H |
( FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE ) -- | D |
);
-- truth table for ">=" function
CONSTANT geb_table : stdlogic_boolean_table := (
-- ----------------------------------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------------------------------
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | U |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | X |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | 0 |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | 1 |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | Z |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | W |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ), -- | L |
( TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE ), -- | H |
( FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE ) -- | D |
);
CONSTANT lt_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | D |
);
-- truth table for ">" function
CONSTANT gt_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '0', 'X', 'X', '0', '0', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | D |
);
-- truth table for "<=" function
CONSTANT le_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U' ), -- | U |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 0 |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | Z |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | L |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ) -- | D |
);
-- truth table for ">=" function
CONSTANT ge_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H D | |
-- ----------------------------------------------------
( 'U', 'U', '1', 'U', 'U', 'U', '1', 'U', 'U' ), -- | U |
( 'U', 'X', '1', 'X', 'X', 'X', '1', 'X', 'X' ), -- | X |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 0 |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1 |
( 'U', 'X', '1', 'X', 'X', 'X', '1', 'X', 'X' ), -- | Z |
( 'U', 'X', '1', 'X', 'X', 'X', '1', 'X', 'X' ), -- | W |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | L |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H |
( 'U', 'X', '1', 'X', 'X', 'X', '1', 'X', 'X' ) -- | D |
);
FUNCTION "=" ( l : Boolean; r : natural ) RETURN Boolean is
begin
IF l = TRUE AND r = 1 THEN
return TRUE;
ELSIF l = FALSE AND r = 0 THEN
return TRUE;
ELSE
return FALSE;
END IF;
end "=";
FUNCTION "/=" ( l : Boolean; r : natural ) RETURN Boolean is
begin
return NOT (l = r);
end "/=";
-----------------------------------------------------------------
FUNCTION "=" ( l : integer; r : std_logic_vector ) RETURN boolean IS
BEGIN
RETURN l = SIGNED(r);
END "=";
-----------------------------------------------------------------
FUNCTION "/=" ( l : integer; r : std_logic_vector ) RETURN boolean IS
BEGIN
RETURN l /= SIGNED(r);
END "/=";
-----------------------------------------------------------------
FUNCTION "<" ( l : integer; r : std_logic_vector ) RETURN boolean IS
BEGIN
RETURN l < SIGNED(r);
END "<";
-----------------------------------------------------------------
FUNCTION ">" ( l : integer; r : std_logic_vector ) RETURN boolean IS
BEGIN
RETURN l > SIGNED(r);
END ">";
-----------------------------------------------------------------
FUNCTION "<=" ( l : integer; r : std_logic_vector ) RETURN boolean IS
BEGIN
RETURN l <= SIGNED(r);
END "<=";
-----------------------------------------------------------------
FUNCTION ">=" ( l : integer; r : std_logic_vector ) RETURN boolean IS
BEGIN
RETURN l >= SIGNED(r);
END ">=";
-----------------------------------------------------------------
FUNCTION "=" ( l : std_logic_vector; r : integer ) RETURN boolean IS
BEGIN
RETURN SIGNED(l) = r;
END "=";
-----------------------------------------------------------------
FUNCTION "/=" ( l : std_logic_vector; r : integer ) RETURN boolean IS
BEGIN
RETURN SIGNED(l) /= r;
END "/=";
-----------------------------------------------------------------
FUNCTION "<" ( l : std_logic_vector; r : integer ) RETURN boolean IS
BEGIN
RETURN SIGNED(l) < r;
END "<";
-----------------------------------------------------------------
FUNCTION ">" ( l : std_logic_vector; r : integer ) RETURN boolean IS
BEGIN
RETURN SIGNED(l) > r;
END ">";
-----------------------------------------------------------------
FUNCTION "<=" ( l : std_logic_vector; r : integer ) RETURN boolean IS
BEGIN
RETURN SIGNED(l) <= r;
END "<=";
-----------------------------------------------------------------
FUNCTION ">=" ( l : std_logic_vector; r : integer ) RETURN boolean IS
BEGIN
RETURN SIGNED(l) >= r;
END ">=";
-----------------------------------------------------------------
--logical functions between std_logic_vector and integer, std_logic_vector and boolean
FUNCTION "and" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector is
BEGIN
RETURN l and to_stdlogicvector(l, 32);
END;
-----------------------------------------------------------------
FUNCTION "nand" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector IS
BEGIN
RETURN l nand to_stdlogicvector(l, 32);
END;
-----------------------------------------------------------------
FUNCTION "or" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector IS
BEGIN
RETURN l or to_stdlogicvector(l, 32);
END;
-----------------------------------------------------------------
FUNCTION "nor" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector IS
BEGIN
RETURN l nor to_stdlogicvector(l, 32);
END;
-----------------------------------------------------------------
FUNCTION "xor" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector IS
BEGIN
RETURN l xor to_stdlogicvector(l, 32);
END;
-----------------------------------------------------------------
FUNCTION "and" ( l : integer; r : std_logic_vector ) RETURN integer IS
BEGIN
RETURN l and v2v_to_integer(r);
END;
-----------------------------------------------------------------
FUNCTION "nand" ( l : integer; r : std_logic_vector ) RETURN integer IS
BEGIN
RETURN l nand v2v_to_integer(r);
END;
-----------------------------------------------------------------
FUNCTION "or" ( l : integer; r : std_logic_vector ) RETURN integer IS
BEGIN
RETURN l or v2v_to_integer(r);
END;
-----------------------------------------------------------------
FUNCTION "nor" ( l : integer; r : std_logic_vector ) RETURN integer IS
BEGIN
RETURN l nor v2v_to_integer(r);
END;
-----------------------------------------------------------------
FUNCTION "xor" ( l : integer; r : std_logic_vector ) RETURN integer IS
BEGIN
RETURN l xor v2v_to_integer(r);
END;
-----------------------------------------------------------------
FUNCTION "and" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector IS
BEGIN
RETURN l and to_stdlogicvector(r,32);
END;
-----------------------------------------------------------------
FUNCTION "nand" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector IS
BEGIN
RETURN l nand to_stdlogicvector(r,32);
END;
-----------------------------------------------------------------
FUNCTION "or" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector IS
BEGIN
RETURN l or to_stdlogicvector(r,32);
END;
-----------------------------------------------------------------
FUNCTION "nor" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector IS
BEGIN
RETURN l nor to_stdlogicvector(r,32);
END;
-----------------------------------------------------------------
FUNCTION "xor" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector IS
BEGIN
RETURN l xor to_stdlogicvector(r,32);
END;
-----------------------------------------------------------------
FUNCTION "and" ( l : boolean; r : std_logic_vector ) RETURN boolean IS
BEGIN
RETURN l and to_boolean(r);
END;
-----------------------------------------------------------------
FUNCTION "nand" ( l : boolean; r : std_logic_vector ) RETURN boolean IS
BEGIN
RETURN l nand to_boolean(r);
END;
-----------------------------------------------------------------
FUNCTION "or" ( l : boolean; r : std_logic_vector ) RETURN boolean IS
BEGIN
RETURN l or to_boolean(r);
END;
-----------------------------------------------------------------
FUNCTION "nor" ( l : boolean; r : std_logic_vector ) RETURN boolean IS
BEGIN
RETURN l nor to_boolean(r);
END;
-----------------------------------------------------------------
FUNCTION "xor" ( l : boolean; r : std_logic_vector ) RETURN boolean IS
BEGIN
RETURN l xor to_boolean(r);
END;
--logical functions between std_logic_vector and integer, std_logic_vector and boolean
-----------------------------------------------------------------
-- Added functions for std_logic, integer
FUNCTION "=" ( l : std_logic; r : integer ) RETURN boolean IS
BEGIN
RETURN to_integer(l) = r;
END "=";
-----------------------------------------------------------------
FUNCTION "/=" ( l : std_logic; r : integer ) RETURN boolean IS
BEGIN
RETURN to_integer(l) /= r;
END "/=";
-----------------------------------------------------------------
FUNCTION "<" ( l : std_logic; r : integer ) RETURN boolean IS
BEGIN
RETURN to_integer(l) < r;
END "<";
-----------------------------------------------------------------
FUNCTION ">" ( l : std_logic; r : integer ) RETURN boolean IS
BEGIN
RETURN to_integer(l) > r;
END ">";
-----------------------------------------------------------------
FUNCTION "<=" ( l : std_logic; r : integer ) RETURN boolean IS
BEGIN
RETURN to_integer(l) <= r;
END "<=";
-----------------------------------------------------------------
FUNCTION ">=" ( l : std_logic; r : integer ) RETURN boolean IS
BEGIN
RETURN to_integer(l) >= r;
END ">=";
-----------------------------------------------------------------
-- Functions for std_logic, integer
-----------------------------------------------------------------
--pragma synthesis_off
-- arithmetic operations for real and int and int and real
FUNCTION "+" ( l : real; r : integer ) RETURN real IS
BEGIN
RETURN l + to_real(r);
END;
FUNCTION "-" ( l : real; r : integer ) RETURN real IS
BEGIN
RETURN l - to_real(r);
END;
FUNCTION "/" ( l : real; r : integer ) RETURN real IS
BEGIN
RETURN l / to_real(r);
END;
FUNCTION "*" ( l : real; r : integer ) RETURN real IS
BEGIN
RETURN l * to_real(r);
END ;
FUNCTION "+" ( l : integer; r : real ) RETURN real IS
BEGIN
RETURN to_real(l) + r;
END;
FUNCTION "-" ( l : integer; r : real ) RETURN real IS
BEGIN
RETURN to_real(l) - r;
END;
FUNCTION "/" ( l : integer; r : real ) RETURN real IS
BEGIN
RETURN to_real(l) / l;
END;
FUNCTION "*" ( l : integer; r : real ) RETURN real IS
BEGIN
RETURN to_real(l) * r;
END;
-- end arithmetic operations for real and int and int and real
-----------------------------------------------------------------
FUNCTION "=" ( l : real; r : integer ) RETURN boolean IS
BEGIN
RETURN INTEGER(l) = r;
END "=";
-----------------------------------------------------------------
FUNCTION "/=" ( l : real; r : integer ) RETURN boolean IS
BEGIN
RETURN INTEGER(l) /= r;
END "/=";
-----------------------------------------------------------------
FUNCTION "<" ( l : real; r : integer ) RETURN boolean IS
BEGIN
RETURN INTEGER(l) < r;
END "<";
-----------------------------------------------------------------
FUNCTION ">" ( l : real; r : integer ) RETURN boolean IS
BEGIN
RETURN INTEGER(l) > r;
END ">";
-----------------------------------------------------------------
FUNCTION "<=" ( l : real; r : integer ) RETURN boolean IS
BEGIN
RETURN INTEGER(l) <= r;
END "<=";
-----------------------------------------------------------------
FUNCTION ">=" ( l : real; r : integer ) RETURN boolean IS
BEGIN
RETURN INTEGER(l) >= r;
END ">=";
-----------------------------------------------------------------
FUNCTION "=" ( l : integer; r : real ) RETURN boolean IS
BEGIN
RETURN l = INTEGER(r);
END "=";
-----------------------------------------------------------------
FUNCTION "/=" ( l : integer; r : real ) RETURN boolean IS
BEGIN
RETURN l /= INTEGER(r);
END "/=";
-----------------------------------------------------------------
FUNCTION "<" ( l : integer; r : real ) RETURN boolean IS
BEGIN
RETURN l < INTEGER(r);
END "<";
-----------------------------------------------------------------
FUNCTION ">" ( l : integer; r : real ) RETURN boolean IS
BEGIN
RETURN l > INTEGER(r);
END ">";
-----------------------------------------------------------------
FUNCTION "<=" ( l : integer; r : real ) RETURN boolean IS
BEGIN
RETURN l <= INTEGER(r);
END "<=";
-----------------------------------------------------------------
FUNCTION ">=" ( l : integer; r : real ) RETURN boolean IS
BEGIN
RETURN l >= INTEGER(r);
END ">=";
--pragma synthesis_on
-----------------------------------------------------------------
FUNCTION "+" ( l, r : std_logic_vector ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(UNSIGNED(l) + UNSIGNED(r));
end "+";
------------------------------------------------------------------
FUNCTION "-" ( l, r : std_logic_vector ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(UNSIGNED(l) - UNSIGNED(r));
end "-";
------------------------------------------------------------------
FUNCTION "*" ( l, r : std_logic_vector ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(UNSIGNED(l) * UNSIGNED(r));
end "*";
------------------------------------------------------------------
FUNCTION "/" ( l, r : std_logic_vector ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(UNSIGNED(l) / UNSIGNED(r));
end "/";
------------------------------------------------------------------
FUNCTION "REM" ( l, r : std_logic_vector ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(UNSIGNED(l) rem UNSIGNED(r));
end "REM";
------------------------------------------------------------------
FUNCTION "+" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(SIGNED(l) + r);
end "+";
------------------------------------------------------------------
FUNCTION "-" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(SIGNED(l) - r);
end "-";
------------------------------------------------------------------
FUNCTION "*" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(SIGNED(l) * r);
end "*";
------------------------------------------------------------------
FUNCTION "/" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(SIGNED(l) / r);
end "/";
------------------------------------------------------------------
FUNCTION "REM" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(SIGNED(l) rem r);
end "REM";
------------------------------------------------------------------
FUNCTION "&" ( l : std_logic_vector; r : integer ) RETURN std_logic_vector is
begin
return l & to_stdlogic(r);
end "&";
------------------------------------------------------------------
FUNCTION "&" ( l : std_logic_vector; r : boolean ) RETURN std_logic_vector is
begin
return l & to_stdlogic(r);
end "&";
------------------------------------------------------------------
FUNCTION "+" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(SIGNED(l) + to_integer(r));
end "+";
------------------------------------------------------------------
FUNCTION "-" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(SIGNED(l) - to_integer(r));
end "-";
------------------------------------------------------------------
FUNCTION "*" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(SIGNED(l) * to_integer(r));
end "*";
------------------------------------------------------------------
FUNCTION "/" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(SIGNED(l) / to_integer(r));
end "/";
------------------------------------------------------------------
FUNCTION "REM" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(SIGNED(l) rem to_integer(r));
end "REM";
------------------------------------------------------------------
FUNCTION "+" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(to_integer(l) + SIGNED(r));
END "+";
------------------------------------------------------------------
FUNCTION "-" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(to_integer(l) - SIGNED(r));
END "-";
------------------------------------------------------------------
FUNCTION "*" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(to_integer(l) * SIGNED(r));
END "*";
------------------------------------------------------------------
FUNCTION "/" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(to_integer(l) / SIGNED(r));
END "/";
------------------------------------------------------------------
FUNCTION "REM" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector is
begin
return STD_LOGIC_VECTOR(to_integer(l) REM SIGNED(r));
END "REM";
-------------------------------------------------------------
-- need logical functions bet. std_logic_vector and std_logic
FUNCTION "and" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector IS
BEGIN
RETURN l and to_stdlogicvector(r, l'length);
END "and";
--------------------------------------------------------------
FUNCTION "nand" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector IS
BEGIN
RETURN l nand to_stdlogicvector(r, l'length);
END "nand";
--------------------------------------------------------------
FUNCTION "or" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector IS
BEGIN
RETURN l or to_stdlogicvector(r, l'length);
END "or";
--------------------------------------------------------------
FUNCTION "nor" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector IS
BEGIN
RETURN l nor to_stdlogicvector(r, l'length);
END "nor";
--------------------------------------------------------------
FUNCTION "xor" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector IS
BEGIN
RETURN l xor to_stdlogicvector(r, l'length);
END "xor";
--------------------------------------------------------------
FUNCTION "xnor" ( l : std_logic_vector; r : std_logic ) RETURN std_logic_vector IS
BEGIN
RETURN NOT(l xor to_stdlogicvector(r, l'length));
END "xnor";
--------------------------------------------------------------
FUNCTION "and" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector IS
BEGIN
RETURN to_stdlogicvector(l, r'length) and r;
END "and";
--------------------------------------------------------------
FUNCTION "nand" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector IS
BEGIN
RETURN to_stdlogicvector(l, r'length) nand r;
END "nand";
--------------------------------------------------------------
FUNCTION "or" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector IS
BEGIN
RETURN to_stdlogicvector(l, r'length) or r;
END "or";
--------------------------------------------------------------
FUNCTION "nor" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector IS
BEGIN
RETURN to_stdlogicvector(l, r'length) nor r;
END "nor";
--------------------------------------------------------------
FUNCTION "xor" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector IS
BEGIN
RETURN to_stdlogicvector(l, r'length) xor r;
END "xor";
--------------------------------------------------------------
FUNCTION "xnor" ( l : std_logic; r : std_logic_vector ) RETURN std_logic_vector IS
BEGIN
RETURN NOT(to_stdlogicvector(l, r'length) xor r);
END "xnor";
--------------------------------------------------------------
-- end logical functions for std_logic_vector and std_logic
------------------------------------------------------------------
-- need arith functions bet std_logic and std_logic
-- used only when the int can be 0 or 1
-- need arithmetic functions bet. std_logic_vector and std_logic
FUNCTION "+" ( l : std_logic; r : std_logic ) RETURN std_logic IS
BEGIN
return to_stdlogic(to_integer(l) + to_integer(r));
END "+";
FUNCTION "-" ( l : std_logic; r : std_logic ) RETURN std_logic IS
BEGIN
return to_stdlogic(to_integer(l) - to_integer(r));
END "-";
FUNCTION "*" ( l : std_logic; r : std_logic ) RETURN std_logic IS
BEGIN
return to_stdlogic(to_integer(l) * to_integer(r));
END "*";
FUNCTION "/" ( l : std_logic; r : std_logic ) RETURN std_logic IS
BEGIN
return to_stdlogic(to_integer(l) / to_integer(r));
END "/";
FUNCTION "REM" ( l : std_logic; r : std_logic ) RETURN std_logic IS
BEGIN
return to_stdlogic(to_integer(l) REM to_integer(r));
END "REM";
------- Arithmatic operations between std_logic and integer
-- caveat, functions below return integer
FUNCTION "+" ( l : std_logic; r : integer ) RETURN integer IS
BEGIN
return to_integer(l) + r;
END "+";
-------------------------------------------------------
FUNCTION "-" ( l : std_logic; r : integer ) RETURN integer IS
BEGIN
return to_integer(l) - r;
END "-";
-------------------------------------------------------
FUNCTION "*" ( l : std_logic; r : integer ) RETURN integer IS
BEGIN
return to_integer(l) * r;
END "*";
-------------------------------------------------------
FUNCTION "/" ( l : std_logic; r : integer ) RETURN integer IS
BEGIN
return to_integer(l) / r;
END "/";
-------------------------------------------------------
FUNCTION "REM" ( l : std_logic; r : integer ) RETURN integer IS
BEGIN
return to_integer(l) REM r;
END "REM";
-------------------------------------------------------
-------------------------------------------------------
FUNCTION "+" ( l : integer; r : std_logic ) RETURN integer IS
begin
return l + to_integer(r);
END "+";
-------------------------------------------------------
FUNCTION "-" ( l : integer; r : std_logic ) RETURN integer IS
begin
return l - to_integer(r);
END "-";
-------------------------------------------------------
FUNCTION "*" ( l : integer; r : std_logic ) RETURN integer IS
begin
return l * to_integer(r);
END "*";
-------------------------------------------------------
FUNCTION "/" ( l : integer; r : std_logic ) RETURN integer IS
begin
return l / to_integer(r);
END "/";
-------------------------------------------------------
FUNCTION "REM" ( l : integer; r : std_logic ) RETURN integer IS
begin
return l REM to_integer(r);
END "REM";
-------------------------------------------------------
FUNCTION "+" ( l : integer; r : std_logic_vector ) RETURN integer IS
BEGIN
RETURN to_integer(l + SIGNED(r));
END "+";
------------------------------------------------------------------
FUNCTION "-" ( l : integer; r : std_logic_vector ) RETURN integer IS
BEGIN
RETURN to_integer(l - SIGNED(r));
END "-";
------------------------------------------------------------------
FUNCTION "*" ( l : integer; r : std_logic_vector ) RETURN integer IS
BEGIN
RETURN to_integer(l * SIGNED(r));
END "*";
------------------------------------------------------------------
FUNCTION "/" ( l : integer; r : std_logic_vector ) RETURN integer IS
BEGIN
RETURN to_integer(l / SIGNED(r));
END "/";
------------------------------------------------------------------
FUNCTION "REM" ( l : integer; r : std_logic_vector ) RETURN integer IS
BEGIN
RETURN to_integer(l REM SIGNED(r));
END "REM";
------------------------------------------------------------------
FUNCTION "and" ( l : std_logic; r : integer ) RETURN std_logic IS
BEGIN
RETURN l and to_stdlogic(r);
END "and";
------------------------------------------------------------------
FUNCTION "nand" ( l : std_logic; r : integer ) RETURN std_logic IS
BEGIN
RETURN l nand to_stdlogic(r);
END "nand";
------------------------------------------------------------------
FUNCTION "or" ( l : std_logic; r : integer ) RETURN std_logic IS
BEGIN
RETURN l or to_stdlogic(r);
END "or";
------------------------------------------------------------------
FUNCTION "nor" ( l : std_logic; r : integer ) RETURN std_logic IS
BEGIN
RETURN l nor to_stdlogic(r);
END "nor";
------------------------------------------------------------------
FUNCTION "xor" ( l : std_logic; r : integer ) RETURN std_logic IS
BEGIN
RETURN l xor to_stdlogic(r);
END "xor";
------------------------------------------------------------------
FUNCTION "&" ( l : std_logic; r : integer ) RETURN std_logic_vector IS
BEGIN
RETURN l & to_stdlogic(r);
END "&";
------------------------------------------------------------------
FUNCTION "xnor" ( l : std_logic; r : integer ) RETURN std_logic IS
BEGIN
RETURN not(l xor to_stdlogic(r));
END "xnor";
------------------------------------------------------------------
FUNCTION "and" ( l : integer; r : std_logic ) RETURN integer IS
VARIABLE tmp : integer := 0;
BEGIN
RETURN l and to_integer(r);
END "and";
------------------------------------------------------------------
FUNCTION "nand" ( l : integer; r : std_logic ) RETURN integer IS
VARIABLE tmp : integer := 0;
BEGIN
RETURN l nand to_integer(r);
END "nand";
------------------------------------------------------------------
FUNCTION "or" ( l : integer; r : std_logic ) RETURN integer IS
VARIABLE tmp : integer := 0;
BEGIN
RETURN l or to_integer(r);
END "or";
------------------------------------------------------------------
FUNCTION "nor" ( l : integer; r : std_logic ) RETURN integer IS
VARIABLE tmp : integer := 0;
BEGIN
RETURN l nor to_integer(r);
END "nor";
------------------------------------------------------------------
FUNCTION "xor" ( l : integer; r : std_logic ) RETURN integer IS
VARIABLE tmp : integer := 0;
BEGIN
RETURN l xor to_integer(r);
END "xor";
------------------------------------------------------------------
FUNCTION "&" ( l : integer; r : std_logic ) RETURN std_logic_vector IS
BEGIN
RETURN to_stdlogic(l) & r;
END "&";
------------------------------------------------------------------
FUNCTION "xnor" ( l : integer; r : std_logic ) RETURN integer IS
VARIABLE tmp : integer := 0;
BEGIN
RETURN l xnor to_integer(r);
END "xnor";
------------------------------------------------------------------
FUNCTION "and" ( l : std_logic ; r : boolean ) RETURN std_logic IS
BEGIN
RETURN l AND to_stdlogic(r);
END "and";
------------------------------------------------------------------
FUNCTION "nand" ( l : std_logic ; r : boolean ) RETURN std_logic IS
BEGIN
RETURN l NAND to_stdlogic(r);
END "nand";
------------------------------------------------------------------
FUNCTION "or" ( l : std_logic ; r : boolean ) RETURN std_logic IS
BEGIN
RETURN l OR to_stdlogic(r);
END "or";
------------------------------------------------------------------
FUNCTION "nor" ( l : std_logic ; r : boolean ) RETURN std_logic IS
BEGIN
RETURN l NOR to_stdlogic(r);
END "nor";
------------------------------------------------------------------
FUNCTION "xor" ( l : std_logic ; r : boolean ) RETURN std_logic IS
BEGIN
RETURN l XOR to_stdlogic(r);
END "xor";
------------------------------------------------------------------
FUNCTION "&" ( l : std_logic; r : boolean ) RETURN std_logic_vector IS
BEGIN
RETURN l & to_stdlogic(r);
END "&";
------------------------------------------------------------------
FUNCTION "xnor" ( l : std_logic ; r : boolean ) RETURN std_logic IS
BEGIN
RETURN NOT(l XOR to_stdlogic(r));
END "xnor";
------------------------------------------------------------------
FUNCTION "and" ( l : boolean ; r : std_logic ) RETURN boolean IS
VARIABLE tmp : std_logic := 'U';
BEGIN
tmp := to_stdlogic(l) AND r;
RETURN to_boolean(tmp);
END "and";
------------------------------------------------------------------
FUNCTION "nand" ( l : boolean ; r : std_logic ) RETURN boolean IS
VARIABLE tmp : std_logic := 'U';
BEGIN
tmp := to_stdlogic(l) NAND r;
RETURN to_boolean(tmp);
END "nand";
------------------------------------------------------------------
FUNCTION "or" ( l : boolean ; r : std_logic ) RETURN boolean IS
VARIABLE tmp : std_logic := 'U';
BEGIN
tmp := to_stdlogic(l) OR r;
RETURN to_boolean(tmp);
END "or";
------------------------------------------------------------------
FUNCTION "nor" ( l : boolean ; r : std_logic ) RETURN boolean IS
VARIABLE tmp : std_logic := 'U';
BEGIN
tmp := to_stdlogic(l) NOR r;
RETURN to_boolean(tmp);
END "nor";
------------------------------------------------------------------
FUNCTION "xor" ( l : boolean ; r : std_logic ) RETURN boolean IS
VARIABLE tmp : std_logic := 'U';
BEGIN
tmp := to_stdlogic(l) XOR r;
RETURN to_boolean(tmp);
END "xor";
------------------------------------------------------------------
FUNCTION "&" ( l : boolean ; r : std_logic ) RETURN std_logic_vector IS
BEGIN
RETURN to_stdlogic(l) & r;
END "&";
------------------------------------------------------------------
FUNCTION "xnor" ( l : boolean ; r : std_logic ) RETURN boolean IS
VARIABLE tmp : std_logic := 'U';
BEGIN
tmp := NOT(to_stdlogic(l) XOR r);
RETURN to_boolean(tmp);
END "xnor";
------------------------------------------------------------------
FUNCTION "and" ( l : integer; r : boolean ) RETURN integer IS
BEGIN
RETURN l and to_integer(r);
END "and";
------------------------------------------------------------------
FUNCTION "nand" ( l : integer; r : boolean ) RETURN integer IS
BEGIN
RETURN l nand to_integer(r);
END "nand";
------------------------------------------------------------------
FUNCTION "or" ( l : integer; r : boolean ) RETURN integer IS
BEGIN
RETURN l or to_integer(r);
END "or";
------------------------------------------------------------------
FUNCTION "nor" ( l : integer; r : boolean ) RETURN integer IS
BEGIN
RETURN l nor to_integer(r);
END "nor";
------------------------------------------------------------------
FUNCTION "xor" ( l : integer; r : boolean ) RETURN integer IS
BEGIN
RETURN l xor to_integer(r);
END "xor";
------------------------------------------------------------------
FUNCTION "&" ( l : integer; r : boolean ) RETURN std_logic_vector IS
BEGIN
RETURN to_stdlogic(l) & to_stdlogic(r);
END "&";
------------------------------------------------------------------
FUNCTION "xnor" ( l : integer; r : boolean ) RETURN integer IS
BEGIN
RETURN l xnor to_integer(r);
END "xnor";
------------------------------------------------------------------
FUNCTION "and" ( l : boolean; r : integer ) RETURN boolean IS
BEGIN
RETURN l AND to_boolean(r);
END "and";
------------------------------------------------------------------
FUNCTION "nand" ( l : boolean; r : integer ) RETURN boolean IS
BEGIN
RETURN l NAND to_boolean(r);
END "nand";
------------------------------------------------------------------
FUNCTION "or" ( l : boolean; r : integer ) RETURN boolean IS
BEGIN
RETURN l or to_boolean(r);
END "or";
------------------------------------------------------------------
FUNCTION "nor" ( l : boolean; r : integer ) RETURN boolean IS
BEGIN
RETURN l nor to_boolean(r);
END "nor";
------------------------------------------------------------------
FUNCTION "xor" ( l : boolean; r : integer ) RETURN boolean IS
BEGIN
RETURN l xor to_boolean(r);
END "xor";
------------------------------------------------------------------
FUNCTION "&" ( l : boolean; r : integer ) RETURN std_logic_vector IS
BEGIN
RETURN to_stdlogic(l) & to_stdlogic(r);
END "&";
------------------------------------------------------------------
FUNCTION "xnor" ( l : boolean; r : integer ) RETURN boolean IS
BEGIN
RETURN l xnor to_boolean(r);
END "xnor";
------------------------------------------------------------------
-- Overloaded function for text output
FUNCTION to_bitvector ( a : bit ) RETURN bit_vector IS
VARIABLE s : bit_vector ( 1 TO 1 );
BEGIN
s(1) := a;
RETURN s;
END to_bitvector;
------------------------------------------------------------------
FUNCTION to_bitvector ( a : std_ulogic ) RETURN bit_vector IS
VARIABLE s : bit_vector ( 1 TO 1 );
BEGIN
s(1) := to_bit(a);
RETURN s;
END to_bitvector;
------------------------------------------------------------------
FUNCTION to_bitvector ( a : integer ) RETURN bit_vector IS
VARIABLE s : bit_vector ( 31 DOWNTO 0 );
BEGIN
s := to_bitvector(STD_LOGIC_VECTOR(to_signed(a, 32)));
RETURN s;
END to_bitvector;
------------------------------------------------------------------
FUNCTION to_stdlogicvector(l : integer; size : natural; dir : direction := little_endian) RETURN std_logic_vector IS
BEGIN
IF dir = little_endian THEN
RETURN STD_LOGIC_VECTOR(to_signed(l,size));
ELSE
RETURN STD_LOGIC_VECTOR(to_signed(l,size) ROL size); -- rotate left by size times
END IF;
END to_stdlogicvector;
------------------------------------------------------------------
FUNCTION to_stdlogicvector(l : std_logic_vector ) RETURN std_logic_vector IS
BEGIN
RETURN l;
END to_stdlogicvector;
------------------------------------------------------------------
FUNCTION to_stdlogicvector(l : std_logic_vector; size : natural; dir : direction := little_endian )
RETURN std_logic_vector IS
VARIABLE tmp1 : UNSIGNED(l'length-1 downto 0);
VARIABLE tmp2 : UNSIGNED(size-1 downto 0);
BEGIN
IF dir = little_endian THEN
RETURN STD_LOGIC_VECTOR(resize(UNSIGNED(l),size));
ELSE
-- using function ROTATE_LEFT to make it both 87 and 93 compliant
-- first get eqiv. in descending range
-- second resize
-- finally, rotate and return
tmp1 := ROTATE_LEFT(UNSIGNED(l),l'length);
tmp2 := resize(UNSIGNED(tmp1),size);
RETURN STD_LOGIC_VECTOR(ROTATE_LEFT(UNSIGNED(tmp2),size));
END IF;
END to_stdlogicvector;
------------------------------------------------------------------
FUNCTION to_stdlogicvector(l : std_logic; size : natural) RETURN std_logic_vector IS
VARIABLE tmp : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
tmp(0) := l;
RETURN tmp;
END to_stdlogicvector;
------------------------------------------------------------------
FUNCTION to_stdlogicvector(l : boolean; size : natural) RETURN std_logic_vector IS
VARIABLE tmp : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
tmp(0) := to_stdlogic(l);
RETURN tmp;
END to_stdlogicvector;
------------------------------------------------------------------
FUNCTION to_integer(l : integer) RETURN integer IS
BEGIN
RETURN l;
END to_integer;
------------------------------------------------------------------
FUNCTION to_integer(l : std_logic) RETURN integer IS
BEGIN
IF ( l = '0') THEN
RETURN 0;
ELSIF (l = '1') THEN
RETURN 1;
ELSE
ASSERT FALSE REPORT("Std_logic values other than '0' and '1' cannot be converted to integer type")
SEVERITY WARNING;
RETURN 0;
END IF;
END to_integer;
------------------------------------------------------------------
FUNCTION to_integer(l : boolean) RETURN integer IS
BEGIN
IF ( l = TRUE) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END to_integer;
------------------------------------------------------------------
FUNCTION to_stdlogic(l : integer) RETURN std_logic IS
VARIABLE ret_val : std_logic := '0';
BEGIN
IF l = 0 THEN
ret_val := '0';
ELSIF l = 1 THEN
ret_val := '1';
ELSE
ASSERT FALSE REPORT("Integers other than 0 and 1 cannot be converted to std_logic type")
SEVERITY WARNING;
END IF;
RETURN ret_val;
END to_stdlogic;
------------------------------------------------------------------
FUNCTION to_stdlogic(l : Boolean) RETURN std_logic IS
VARIABLE ret_val : std_logic := '0';
BEGIN
IF l = FALSE THEN
ret_val := '0';
ELSE
ret_val := '1';
END IF;
RETURN ret_val;
END to_stdlogic;
------------------------------------------------------------------
FUNCTION to_stdlogic(l : std_logic) RETURN std_logic IS
BEGIN
RETURN l;
END to_stdlogic;
------------------------------------------------------------------
FUNCTION to_stdlogic(l : std_logic_vector) RETURN std_logic IS
BEGIN
RETURN l(l'LOW);
END to_stdlogic;
------------------------------------------------------------------
FUNCTION to_integer(l : std_logic_vector; dir : direction := little_endian) RETURN integer IS
BEGIN
IF dir = little_endian THEN
-- RETURN to_integer(SIGNED(l));
RETURN to_integer(UNSIGNED(l));
ELSE
-- RETURN to_integer(SIGNED(l) ROR l'LENGTH);
RETURN to_integer(UNSIGNED(l) ROR l'LENGTH);
END IF;
END to_integer;
------------------------------------------------------------------
FUNCTION v2v_to_integer(l : std_logic_vector; dir : direction := little_endian) RETURN integer IS
BEGIN
IF dir = little_endian THEN
-- RETURN to_integer(SIGNED(l));
RETURN to_integer(UNSIGNED(l));
ELSE
--NOTE, since ROR is not available in 87, we will use ROTATE_RIGHT
RETURN to_integer(ROTATE_RIGHT(UNSIGNED(l) , l'LENGTH));
-- RETURN to_integer(UNSIGNED(l) ROR l'LENGTH);
END IF;
END v2v_to_integer;
------------------------------------------------------------------
FUNCTION v2v_to_integer(l : integer) RETURN integer IS
BEGIN
RETURN l;
END v2v_to_integer;
------------------------------------------------------------------
FUNCTION v2v_to_integer(l : std_logic) RETURN integer IS
BEGIN
IF ( l = '0') THEN
RETURN 0;
ELSIF (l = '1') THEN
RETURN 1;
ELSE
ASSERT FALSE REPORT("Std_logic values other than '0' and '1' cannot be converted to integer type")
SEVERITY WARNING;
RETURN 0;
END IF;
END v2v_to_integer;
------------------------------------------------------------------
FUNCTION v2v_to_integer(l : boolean) RETURN integer IS
BEGIN
IF ( l = TRUE) THEN
RETURN 0;
ELSE
RETURN 1;
END IF;
END v2v_to_integer;
------------------------------------------------------------------
--pragma synthesis_off
------------------------------------------------------------------
FUNCTION to_real(l : integer) RETURN real IS
BEGIN
RETURN REAL(l);
END to_real;
------------------------------------------------------------------
FUNCTION to_real(l : real) RETURN real IS
BEGIN
RETURN l;
END to_real;
--pragma synthesis_on
------------------------------------------------------------------
FUNCTION to_boolean(l : std_logic) RETURN boolean IS
BEGIN
IF ( l = '0' ) THEN
RETURN FALSE;
ELSIF (l = '1') THEN
RETURN TRUE;
ELSE
ASSERT FALSE REPORT("Std_logic values other than '0' and '1' cannot be converted to boolean type")
SEVERITY WARNING;
RETURN FALSE;
END IF;
END to_boolean;
------------------------------------------------------------------
FUNCTION to_boolean(l : std_logic_vector) RETURN boolean IS
VARIABLE tmp : std_logic_vector(l'RANGE);
BEGIN
tmp := (OTHERS=>'1');
if to_integer(l AND tmp) /= 0 THEN
RETURN TRUE;
END IF;
RETURN FALSE;
END to_boolean;
------------------------------------------------------------------
FUNCTION to_boolean(l : boolean) RETURN boolean IS
BEGIN
IF ( l) THEN
RETURN TRUE;
END IF;
RETURN FALSE;
END to_boolean;
------------------------------------------------------------------
FUNCTION to_boolean(l : integer) RETURN boolean IS
BEGIN
IF ( l = 0 ) THEN
RETURN FALSE;
ELSE
RETURN TRUE;
END IF;
END to_boolean;
------------------------------------------------------------------
FUNCTION "sll" ( l : std_logic_vector; r : integer) RETURN std_logic_vector IS
VARIABLE v : std_logic_vector(l'RANGE) := (others=>'0');
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "srl"(l,-r);
ELSIF r<l'LENGTH THEN
IF l'LEFT<l'RIGHT THEN
FOR i IN l'LEFT TO (l'RIGHT-r) LOOP
v(i) := l(i+r);
END LOOP;
ELSE
FOR i IN l'LEFT DOWNTO (l'RIGHT+r) LOOP
v(i) := l(i-r);
END LOOP;
END IF;
END IF;
RETURN v;
END;
FUNCTION "sll" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector IS
VARIABLE v : std_ulogic_vector(l'RANGE) := (others=>'0');
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "srl"(l,-r);
ELSIF r<l'LENGTH THEN
IF l'LEFT<l'RIGHT THEN
FOR i IN l'LEFT TO (l'RIGHT-r) LOOP
v(i) := l(i+r);
END LOOP;
ELSE
FOR i IN l'LEFT DOWNTO (l'RIGHT+r) LOOP
v(i) := l(i-r);
END LOOP;
END IF;
END IF;
RETURN v;
END;
FUNCTION "srl" ( l : std_logic_vector; r : integer) RETURN std_logic_vector IS
VARIABLE v : std_logic_vector(l'RANGE) := (others=>'0');
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "sll"(l,-r);
ELSIF r<l'LENGTH THEN
IF l'LEFT<l'RIGHT THEN
FOR i IN l'LEFT TO (l'RIGHT-r) LOOP
v(i+r) := l(i);
END LOOP;
ELSE
FOR i IN l'LEFT DOWNTO (l'RIGHT+r) LOOP
v(i-r) := l(i);
END LOOP;
END IF;
END IF;
RETURN v;
END;
FUNCTION "srl" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector IS
VARIABLE v : std_ulogic_vector(l'RANGE) := (others=>'0');
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "sll"(l,-r);
ELSIF r<l'LENGTH THEN
IF l'LEFT<l'RIGHT THEN
FOR i IN l'LEFT TO (l'RIGHT-r) LOOP
v(i+r) := l(i);
END LOOP;
ELSE
FOR i IN l'LEFT DOWNTO (l'RIGHT+r) LOOP
v(i-r) := l(i);
END LOOP;
END IF;
END IF;
RETURN v;
END;
FUNCTION "sla" ( l : std_logic_vector; r : integer) RETURN std_logic_vector IS
VARIABLE v : std_logic_vector(l'RANGE) := (others=>l(l'RIGHT));
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "sra"(l,-r);
ELSIF r<l'LENGTH THEN
IF l'LEFT<l'RIGHT THEN
FOR i IN l'LEFT TO (l'RIGHT-r) LOOP
v(i) := l(i+r);
END LOOP;
ELSE
FOR i IN l'LEFT DOWNTO (l'RIGHT+r) LOOP
v(i) := l(i-r);
END LOOP;
END IF;
END IF;
RETURN v;
END;
FUNCTION "sla" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector IS
VARIABLE v : std_ulogic_vector(l'RANGE) := (others=>l(l'RIGHT));
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "sra"(l,-r);
ELSIF r<l'LENGTH THEN
IF l'LEFT<l'RIGHT THEN
FOR i IN l'LEFT TO (l'RIGHT-r) LOOP
v(i) := l(i+r);
END LOOP;
ELSE
FOR i IN l'LEFT DOWNTO (l'RIGHT+r) LOOP
v(i) := l(i-r);
END LOOP;
END IF;
END IF;
RETURN v;
END;
FUNCTION "sra" ( l : std_logic_vector; r : integer) RETURN std_logic_vector IS
VARIABLE v : std_logic_vector(l'RANGE) := (others=>l(l'RIGHT));
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "sla"(l,-r);
ELSIF r<l'LENGTH THEN
IF l'LEFT<l'RIGHT THEN
FOR i IN l'LEFT TO (l'RIGHT-r) LOOP
v(i+r) := l(i);
END LOOP;
ELSE
FOR i IN l'LEFT DOWNTO (l'RIGHT+r) LOOP
v(i-r) := l(i);
END LOOP;
END IF;
END IF;
RETURN v;
END;
FUNCTION "sra" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector IS
VARIABLE v : std_ulogic_vector(l'RANGE) := (others=>l(l'RIGHT));
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "sla"(l,-r);
ELSIF r<l'LENGTH THEN
IF l'LEFT<l'RIGHT THEN
FOR i IN l'LEFT TO (l'RIGHT-r) LOOP
v(i+r) := l(i);
END LOOP;
ELSE
FOR i IN l'LEFT DOWNTO (l'RIGHT+r) LOOP
v(i-r) := l(i);
END LOOP;
END IF;
END IF;
RETURN v;
END;
FUNCTION "rol" ( l : std_logic_vector; r : integer) RETURN std_logic_vector IS
VARIABLE v : std_logic_vector(0 TO l'LENGTH*2-1);
VARIABLE v1 : std_logic_vector(l'RANGE);
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "ror"(l,-r);
ELSE
v(0 TO l'LENGTH-1) := l;
v(l'LENGTH TO v'LENGTH-1) := l;
v1 := v(r TO r+l'LENGTH-1);
RETURN v1;
END IF;
END;
FUNCTION "rol" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector IS
VARIABLE v : std_ulogic_vector(0 TO l'LENGTH*2-1);
VARIABLE v1 : std_ulogic_vector(l'RANGE);
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "ror"(l,-r);
ELSE
v(0 TO l'LENGTH-1) := l;
v(l'LENGTH TO v'LENGTH-1) := l;
v1 := v(r TO r+l'LENGTH-1);
RETURN v1;
END IF;
END;
FUNCTION "ror" ( l : std_logic_vector; r : integer) RETURN std_logic_vector IS
VARIABLE v : std_logic_vector(0 TO l'LENGTH*2-1);
VARIABLE v1 : std_logic_vector(l'RANGE);
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "rol"(l,-r);
ELSE
v(0 TO l'LENGTH-1) := l;
v(l'LENGTH TO v'LENGTH-1) := l;
v1 := v(l'LENGTH-r TO v'LENGTH-r-1);
RETURN v1;
END IF;
END;
FUNCTION "ror" ( l : std_ulogic_vector; r : integer) RETURN std_ulogic_vector IS
VARIABLE v : std_ulogic_vector(0 TO l'LENGTH*2-1);
VARIABLE v1 : std_ulogic_vector(l'RANGE);
BEGIN
IF r=0 THEN
RETURN l;
ELSIF r<0 THEN
RETURN "rol"(l,-r);
ELSE
v(0 TO l'LENGTH-1) := l;
v(l'LENGTH TO v'LENGTH-1) := l;
v1 := v(l'LENGTH-r TO v'LENGTH-r-1);
RETURN v1;
END IF;
END;
FUNCTION to_stdlogicvector(hex : STRING) RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(4 * hex'LENGTH DOWNTO 1);
BEGIN
-- Note: The hex parameter can have a range with hex'LOW > 1.
-- For these cases, variable index i in assignments in the FOR loop is normalized
-- to 1 by subtracting hex'LOW ** sas 2/13/96 **
FOR i in hex'RANGE LOOP
CASE hex(i) IS
WHEN '0' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"0";
WHEN '1' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"1";
WHEN '2' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"2";
WHEN '3' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"3";
WHEN '4' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"4";
WHEN '5' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"5";
WHEN '6' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"6";
WHEN '7' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"7";
WHEN '8' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"8";
WHEN '9' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"9";
WHEN 'A' | 'a' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"A";
WHEN 'B' | 'b' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"B";
WHEN 'C' | 'c' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"C";
WHEN 'D' | 'd' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"D";
WHEN 'E' | 'e' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"E";
WHEN 'F' | 'f' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := x"F";
WHEN 'X' | 'x' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := "XXXX";
WHEN 'Z' | 'z' =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := "ZZZZ";
WHEN OTHERS =>
result(4*(hex'LENGTH - (i-hex'LOW)) DOWNTO 4*(hex'LENGTH - (i-hex'LOW)) -3) := "XXXX";
END CASE;
END LOOP;
RETURN result;
END to_stdlogicvector;
end FUNCTIONS;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/grdware/mul_dware.vhd | 1 | 4078 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: misc
-- File: mul_dware.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Dware multipliers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library Dware;
use DWARE.DWpackages.all;
use DWARE.DW_Foundation_comp_arith.all;
entity mul_dw is
generic (
a_width : positive := 2; -- multiplier word width
b_width : positive := 2; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1 -- '0': non-stallable; '1': stallable
);
port(a : in std_logic_vector(a_width-1 downto 0);
b : in std_logic_vector(b_width-1 downto 0);
clk : in std_logic;
en : in std_logic;
sign : in std_logic;
product : out std_logic_vector(a_width+b_width-1 downto 0));
end;
architecture rtl of mul_dw is
component DW02_mult
generic( A_width: NATURAL; -- multiplier wordlength
B_width: NATURAL); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic; -- signed -> '1', unsigned -> '0'
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end component;
signal gnd : std_ulogic;
begin
gnd <= '0';
np : if num_stages = 1 generate
u0 : DW02_mult
generic map ( a_width => a_width, b_width => b_width)
port map (a => a, b => b, TC => sign, product => product);
end generate;
pipe : if num_stages > 1 generate
u0 : DW_mult_pipe
generic map ( a_width => a_width, b_width => b_width,
num_stages => num_stages, stall_mode => stall_mode, rst_mode => 0)
port map (a => a, b => b, TC => sign, clk => clk, product => product,
rst_n => gnd, en => en);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library Dware;
use DWARE.DWpackages.all;
use DWARE.DW_Foundation_comp_arith.all;
entity dw_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end;
architecture rtl of dw_mul_61x61 is
signal gnd : std_ulogic;
signal pin, p : std_logic_vector(121 downto 0);
begin
gnd <= '0';
-- u0 : DW02_mult_2_stage
-- generic map ( A_width => A'length, B_width => B'length )
-- port map ( A => A, B => B, TC => gnd, CLK => CLK, PRODUCT => pin );
u0 : DW_mult_pipe
generic map ( a_width => 61, b_width => 61,
num_stages => 2, stall_mode => 0, rst_mode => 0)
port map (a => a, b => b, TC => gnd, clk => clk, product => pin,
rst_n => gnd, en => gnd);
reg0 : process(CLK)
begin
if rising_edge(CLK) then
p <= pin;
end if;
end process;
PRODUCT <= p;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/techmap/inferred/ddrphy_datapath.vhd | 1 | 9238 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddrphy_datapath
-- File: ddrphy_datapath.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Generic DDR/DDR2 PHY data path (digital part of phy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity ddrphy_datapath is
generic (
regtech: integer := 0;
dbits: integer;
abits: integer;
bankbits: integer range 2 to 3 := 2;
ncs: integer;
nclk: integer;
-- Enable extra resync stage clocked by clkresync
resync: integer range 0 to 2 := 0
);
port (
clk0: in std_ulogic;
clk90: in std_ulogic;
clk180: in std_ulogic;
clk270: in std_ulogic;
clkresync: in std_ulogic;
ddr_clk: out std_logic_vector(nclk-1 downto 0);
ddr_clkb: out std_logic_vector(nclk-1 downto 0);
ddr_dq_in: in std_logic_vector(dbits-1 downto 0);
ddr_dq_out: out std_logic_vector(dbits-1 downto 0);
ddr_dq_oen: out std_logic_vector(dbits-1 downto 0);
ddr_dqs_in90: in std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_in90n: in std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_out: out std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_oen: out std_logic_vector(dbits/8-1 downto 0);
ddr_cke: out std_logic_vector(ncs-1 downto 0);
ddr_csb: out std_logic_vector(ncs-1 downto 0);
ddr_web: out std_ulogic;
ddr_rasb: out std_ulogic;
ddr_casb: out std_ulogic;
ddr_ad: out std_logic_vector(abits-1 downto 0);
ddr_ba: out std_logic_vector(bankbits-1 downto 0);
ddr_dm: out std_logic_vector(dbits/8-1 downto 0);
ddr_odt: out std_logic_vector(ncs-1 downto 0);
-- Control signals synchronous to clk0
dqin: out std_logic_vector(dbits*2-1 downto 0);
dqout: in std_logic_vector(dbits*2-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector (bankbits-1 downto 0);
dm : in std_logic_vector (dbits/4-1 downto 0);
oen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0); -- Clk enable control signal to memory
odt : in std_logic_vector(ncs-1 downto 0);
dqs_en : in std_ulogic; -- Run dqs strobe (active low)
dqs_oen : in std_ulogic; -- DQS output enable (active low)
ddrclk_en : in std_logic_vector(nclk-1 downto 0) -- Enable/stop ddr_clk
);
end;
architecture rtl of ddrphy_datapath is
signal vcc,gnd: std_ulogic;
signal dqs_en_inv,dqs_en_inv180: std_ulogic;
signal dqcaptr,dqcaptf: std_logic_vector(dbits-1 downto 0);
signal dqsyncr,dqsyncf: std_logic_vector(dbits-1 downto 0);
begin
vcc <= '1';
gnd <= '0';
-----------------------------------------------------------------------------
-- DDR interface clock signal
-----------------------------------------------------------------------------
-- 90 degree shifted relative to master clock, gated by ddrclk_en
genclk: for x in 0 to nclk-1 generate
clkreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => ddrclk_en(x), d2 => gnd, ce => vcc,
c1 => clk90, c2 => clk270, r => gnd, s => gnd,
q => ddr_clk(x));
clkbreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => gnd, d2 => ddrclk_en(x), ce => vcc,
c1 => clk90, c2 => clk270, r => gnd, s => gnd,
q => ddr_clkb(x));
end generate;
-----------------------------------------------------------------------------
-- Control signals RAS,CAS,WE,BA,ADDR,CS,ODT,CKE
-----------------------------------------------------------------------------
rasreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => rasn, q => ddr_rasb);
casreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => casn, q => ddr_casb);
wereg: grdff generic map (tech => regtech)
port map (clk => clk0, d => wen, q => ddr_web);
genba: for x in 0 to bankbits-1 generate
bareg: grdff generic map (tech => regtech)
port map (clk => clk0, d => ba(x), q => ddr_ba(x));
end generate;
gencs: for x in 0 to ncs-1 generate
csreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => csn(x), q => ddr_csb(x));
ckereg: grdff generic map (tech => regtech)
port map (clk => clk0, d => cke(x), q => ddr_cke(x));
odtreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => odt(x), q => ddr_odt(x));
end generate;
genaddr: for x in 0 to abits-1 generate
addrreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => addr(x), q => ddr_ad(x));
end generate;
-----------------------------------------------------------------------------
-- Outgoing data, output enable, DQS, DQSOEN, DM
-----------------------------------------------------------------------------
gendqout: for x in 0 to dbits-1 generate
dqoutreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => dqout(x+dbits), d2 => dqout(x), ce => vcc,
c1 => clk0, c2 => clk180, r => gnd, s => gnd,
q => ddr_dq_out(x));
dqoenreg: grdff
generic map (tech => regtech)
port map (clk => clk0, d => oen, q => ddr_dq_oen(x));
end generate;
-- dqs_en -> invert -> delay -> +90-deg DDR-regs -> dqs_out
-- In total oen is delayed 5/4 cycles. We use 1/2 cycle delay
-- instead of 1 cycle delay to get better timing margin to DDR regs.
-- DQSOEN is delayed one cycle just like ctrl sigs
dqs_en_inv <= not dqs_en;
dqseninv180reg: grdff
generic map (tech => regtech)
port map (clk => clk180, d => dqs_en_inv, q => dqs_en_inv180);
gendqsout: for x in 0 to dbits/8-1 generate
dqsreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => dqs_en_inv180, d2 => gnd, ce => vcc,
c1 => clk90, c2 => clk270, r => gnd, s => gnd,
q => ddr_dqs_out(x));
dqsoenreg: grdff generic map (tech => regtech)
port map (clk => clk0, d => dqs_oen, q => ddr_dqs_oen(x));
end generate;
gendm: for x in 0 to dbits/8-1 generate
dmreg: ddr_oreg
generic map (tech => regtech)
port map (d1 => dm(x+dbits/8), d2 => dm(x), ce => vcc,
c1 => clk0, c2 => clk180, r => gnd, s => gnd,
q => ddr_dm(x));
end generate;
-----------------------------------------------------------------------------
-- Incoming data
-----------------------------------------------------------------------------
gendqin: for x in 0 to dbits-1 generate
-- capture using dqs+90
-- Note: The ddr_ireg delivers both edges on c1 rising edge, therefore c1
-- is connected to inverted clock (c1 rising edge == dqs falling edge)
dqcaptreg: ddr_ireg generic map (tech => regtech)
port map (d => ddr_dq_in(x),
c1 => ddr_dqs_in90n(x/8), c2 => ddr_dqs_in90(x/8), ce => vcc, r => gnd, s => gnd,
q1 => dqcaptf(x), q2 => dqcaptr(x));
-- optional extra resync stage
ifresync: if resync=1 generate
genresync: for x in 0 to dbits-1 generate
dqsyncrreg: grdff generic map (tech => regtech)
port map (clk => clkresync, d => dqcaptr(x), q => dqsyncr(x));
dqsyncfreg: grdff generic map (tech => regtech)
port map (clk => clkresync, d => dqcaptf(x), q => dqsyncf(x));
end generate;
end generate;
noresync: if resync/=1 generate
dqsyncr <= dqcaptr;
dqsyncf <= dqcaptf;
end generate;
-- sample in clk0 domain
gensamp: if resync/=2 generate
dqinregr: grdff generic map (tech => regtech)
port map (clk => clk0, d => dqsyncr(x), q => dqin(x+dbits));
dqinregf: grdff generic map (tech => regtech)
port map (clk => clk0, d => dqsyncf(x), q => dqin(x));
end generate;
nosamp: if resync=2 generate
dqin(x+dbits) <= dqsyncr(x);
dqin(x) <= dqsyncf(x);
end generate;
end generate;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/greth/greth.in.vhd | 3 | 360 | -- Gaisler Ethernet core
constant CFG_GRETH : integer := CONFIG_GRETH_ENABLE;
constant CFG_GRETH1G : integer := CONFIG_GRETH_GIGA;
constant CFG_ETH_FIFO : integer := CFG_GRETH_FIFO;
#ifdef CONFIG_LEON3FT_PRESENT
constant CFG_GRETH_FT : integer := CONFIG_GRETH_FT;
constant CFG_GRETH_EDCLFT : integer := CONFIG_GRETH_EDCLFT;
#endif
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/memctrl/sdmctrl.vhd | 1 | 25493 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sdmctrl
-- File: sdmctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: SDRAM memory controller to fit with LEON2 memory controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.memctrl.all;
entity sdmctrl is
generic (
pindex : integer := 0;
invclk : integer := 0;
fast : integer := 0;
wprot : integer := 0;
sdbits : integer := 32;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
sdi : in sdram_in_type;
sdo : out sdram_out_type;
apbi : in apb_slv_in_type;
wpo : in wprot_out_type;
sdmo : out sdram_mctrl_out_type
);
end;
architecture rtl of sdmctrl is
constant WPROTEN : boolean := (wprot /= 0);
constant SDINVCLK : boolean := (invclk /= 0);
constant BUS64 : boolean := (sdbits = 64);
constant PM_PD : std_logic_vector(2 downto 0) := "001";
constant PM_SR : std_logic_vector(2 downto 0) := "010";
constant PM_DPD : std_logic_vector(2 downto 0) := "101";
type mcycletype is (midle, active, leadout);
type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
wr1, wr2, wr3, wr4, wr5, sidle, sref, pd, dpd);
type icycletype is (iidle, pre, ref, lmode, emode, finish);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
casdel : std_ulogic; -- CAS to data delay: 2/3 clock cycles
trfc : std_logic_vector(2 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(14 downto 0);
renable : std_ulogic;
pageburst : std_ulogic;
mobileen : std_logic_vector(1 downto 0); -- Mobile SD support, Mobile SD enabled
ds : std_logic_vector(3 downto 0); -- ds(1:0) (ds(3:2) used to detect update)
tcsr : std_logic_vector(3 downto 0); -- tcrs(1:0) (tcrs(3:2) used to detect update)
pasr : std_logic_vector(5 downto 0); -- pasr(2:0) (pasr(5:3) used to detect update)
pmode : std_logic_vector(2 downto 0); -- Power-Saving mode
txsr : std_logic_vector(3 downto 0); -- Exit Self Refresh timing
cke : std_ulogic; -- Clock enable
end record;
-- local registers
type reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
bdrive : std_ulogic;
burst : std_ulogic;
busy : std_ulogic;
bdelay : std_ulogic;
wprothit : std_ulogic;
startsd : std_ulogic;
aload : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
icnt : std_logic_vector(2 downto 0);
cfg : sdram_cfg_type;
trfc : std_logic_vector(3 downto 0);
refresh : std_logic_vector(14 downto 0);
sdcsn : std_logic_vector(1 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(7 downto 0);
bsel : std_ulogic;
haddr : std_logic_vector(31 downto 10);
-- only needed to keep address lines from switch too much
address : std_logic_vector(16 downto 2); -- memory address
idlecnt : std_logic_vector(3 downto 0); -- Counter, 16 idle clock sycles before entering Power-Saving mode
sref_tmpcom : std_logic_vector(2 downto 0); -- Save SD command when exit sref
end record;
signal r, ri : reg_type;
begin
ctrl : process(rst, apbi, sdi, wpo, r)
variable v : reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable haddr : std_logic_vector(31 downto 0);
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable dqm : std_logic_vector(7 downto 0);
variable raddr : std_logic_vector(12 downto 0);
variable adec : std_ulogic;
variable busy : std_ulogic;
variable aload : std_ulogic;
variable rams : std_logic_vector(1 downto 0);
variable hresp : std_logic_vector(1 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable lline : std_logic_vector(2 downto 0);
variable rline : std_logic_vector(2 downto 0);
variable lineburst : boolean;
variable arefresh : std_logic;
begin
-- Variable default settings to avoid latches
v := r; startsd := '0'; v.busy := '0'; hresp := HRESP_OKAY;
lline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel;
rline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel;
arefresh := '0';
if sdi.hready = '1' then v.hsel := sdi.hsel; end if;
if (sdi.hready and sdi.hsel ) = '1' then
if sdi.htrans(1) = '1' then v.hready := '0'; end if;
end if;
if fast = 1 then haddr := sdi.rhaddr; else haddr := sdi.haddr; end if;
if (pageburst = 0) or ((pageburst = 2) and r.cfg.pageburst = '0') then
lineburst := true;
else lineburst := false; end if;
-- main state
case sdi.hsize is
when "00" =>
case sdi.rhaddr(1 downto 0) is
when "00" => dqm := "11110111";
when "01" => dqm := "11111011";
when "10" => dqm := "11111101";
when others => dqm := "11111110";
end case;
when "01" =>
if sdi.rhaddr(1) = '0' then dqm := "11110011"; else dqm := "11111100"; end if;
when others => dqm := "11110000";
end case;
if BUS64 and (r.bsel = '1') then
dqm := dqm(3 downto 0) & "1111";
end if;
-- main FSM
case r.mstate is
when midle =>
if (v.hsel and sdi.nhtrans(1)) = '1' then
if (r.sdstate = sidle) and (r.cfg.command = "000") and
(r.cmstate = midle) and (sdi.idle = '1')
then
if fast = 1 then v.startsd := '1'; else startsd := '1'; end if;
v.mstate := active;
elsif ((r.sdstate = sref) or (r.sdstate = pd) or (r.sdstate = dpd))
and (r.cfg.command = "000") and (r.cmstate = midle) --and (v.hio = '0')
then
v.startsd := '1';
if r.sdstate = dpd then -- Error response when on Deep Power-Down mode
hresp := HRESP_ERROR;
else
v.mstate := active;
end if;
end if;
end if;
when others => null;
end case;
startsd := r.startsd or startsd;
-- generate row and column address size
case r.cfg.csize is
when "00" => raddr := haddr(22 downto 10);
when "01" => raddr := haddr(23 downto 11);
when "10" => raddr := haddr(24 downto 12);
when others =>
if r.cfg.bsize = "111" then raddr := haddr(26 downto 14);
else raddr := haddr(25 downto 13); end if;
end case;
-- generate bank address
ba := genmux(r.cfg.bsize, haddr(28 downto 21)) &
genmux(r.cfg.bsize, haddr(27 downto 20));
-- generate chip select
if BUS64 then
adec := genmux(r.cfg.bsize, haddr(30 downto 23));
v.bsel := genmux(r.cfg.bsize, sdi.rhaddr(29 downto 22));
else
adec := genmux(r.cfg.bsize, haddr(29 downto 22)); v.bsel := '0';
end if;
if (sdi.srdis = '0') and (r.cfg.bsize = "111") then adec := not adec; end if;
rams := adec & not adec;
if r.trfc /= "0000" then v.trfc := r.trfc - 1; end if;
if r.idlecnt /= "0000" then v.idlecnt := r.idlecnt - 1; end if;
-- sdram access FSM
case r.sdstate is
when sidle =>
v.bdelay := '0';
if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle) then
v.address(16 downto 2) := ba & raddr;
v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
v.startsd := '0';
elsif (r.idlecnt = "0000") and (r.cfg.command = "000")
and (r.cmstate = midle) and (r.cfg.mobileen(1) = '1') then
case r.cfg.pmode is
when PM_SR =>
v.cfg.cke := '0'; v.sdstate := sref;
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; -- Control minimum duration of Self Refresh mode (= tRAS)
when PM_PD => v.cfg.cke := '0'; v.sdstate := pd;
when PM_DPD =>
v.cfg.cke := '0'; v.sdstate := dpd;
v.sdcsn := (others => '0'); v.sdwen := '0'; v.rasn := '1'; v.casn := '1';
when others =>
end case;
end if;
when act1 =>
v.rasn := '1'; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; v.haddr := sdi.rhaddr(31 downto 10);
if r.cfg.casdel = '1' then v.sdstate := act2; else
v.sdstate := act3;
v.hready := sdi.hwrite and sdi.htrans(0) and sdi.htrans(1);
end if;
if WPROTEN then
v.wprothit := wpo.wprothit;
if wpo.wprothit = '1' then hresp := HRESP_ERROR; end if;
end if;
when act2 =>
v.sdstate := act3;
v.hready := sdi.hwrite and sdi.htrans(0) and sdi.htrans(1);
if WPROTEN and (r.wprothit = '1') then
hresp := HRESP_ERROR; v.hready := '0';
end if;
when act3 =>
v.casn := '0';
v.address(14 downto 2) := sdi.rhaddr(13 downto 12) & '0' & sdi.rhaddr(11 downto 2);
v.dqm := dqm; v.burst := r.hready;
if sdi.hwrite = '1' then
v.sdstate := wr1; v.sdwen := '0'; v.bdrive := '1';
if sdi.htrans = "11" or (r.hready = '0') then v.hready := '1'; end if;
if WPROTEN and (r.wprothit = '1') then
hresp := HRESP_ERROR; v.hready := '1';
v.sdstate := wr1; v.sdwen := '1'; v.bdrive := '0'; v.casn := '1';
end if;
else v.sdstate := rd1; end if;
when wr1 =>
v.address(14 downto 2) := sdi.rhaddr(13 downto 12) & '0' & sdi.rhaddr(11 downto 2);
if (((r.burst and r.hready) = '1') and (sdi.rhtrans = "11"))
and not (WPROTEN and (r.wprothit = '1'))
then
v.hready := sdi.htrans(0) and sdi.htrans(1) and r.hready;
if ((sdi.rhaddr(5 downto 2) = "1111") and (r.cfg.command = "100")) then -- exit on refresh
v.hready := '0';
end if;
else
v.sdstate := wr2; v.bdrive := '0'; v.casn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
end if;
when wr2 =>
if (sdi.rhtrans = "10") and (sdi.rhaddr(31 downto 10) = r.haddr) and (r.hsel = '1') then
if sdi.hwrite = '1' then v.hready := '1'; end if; v.sdstate := act3;
elsif (r.trfc(2 downto 1) = "00") then
if (r.cfg.trp = '0') then v.rasn := '0'; v.sdwen := '0'; end if;
v.sdstate := wr3;
end if;
when wr3 =>
if (sdi.rhtrans = "10") and (sdi.rhaddr(31 downto 10) = r.haddr) and (r.sdwen = '1') and (r.hsel = '1') then
if sdi.hwrite = '1' then v.hready := '1'; end if; v.sdstate := act3;
elsif (r.cfg.trp = '1') then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4;
else
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1';
if r.trfc = "0000" then v.sdstate := sidle; end if;
end if;
when wr4 =>
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1';
if (r.cfg.trp = '1') then v.sdstate := wr5;
else
if r.trfc = "0000" then v.sdstate := sidle; end if;
end if;
when wr5 =>
if r.trfc = "0000" then v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
when rd1 =>
v.casn := '1'; v.sdstate := rd7;
if lineburst and (sdi.htrans = "11") then
if sdi.rhaddr(4 downto 2) = "111" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd7 =>
v.casn := '1';
if r.cfg.casdel = '1' then
v.sdstate := rd2;
if lineburst and (sdi.htrans = "11") then
if sdi.rhaddr(4 downto 2) = "110" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
else
v.sdstate := rd3;
if sdi.htrans /= "11" then
if (r.trfc(2 downto 1) = "00") then v.rasn := '0'; v.sdwen := '0'; end if;
elsif lineburst then
if sdi.rhaddr(4 downto 2) = "110" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
if sdi.htrans /= "11" then -- v.rasn := '0'; v.sdwen := '0';
if (r.trfc(2 downto 1) = "00") then v.rasn := '0'; v.sdwen := '0'; end if;
elsif lineburst then
if sdi.rhaddr(4 downto 2) = "101" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
if v.sdwen = '0' then v.dqm := (others => '1'); end if;
when rd3 =>
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
if r.sdwen = '0' then
v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1');
elsif lineburst and (sdi.htrans = "11") and (r.casn = '1') then
if sdi.rhaddr(4 downto 2) = ("10" & not r.cfg.casdel) then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
if (sdi.htrans /= "11") or (r.sdcsn = "11") or
((sdi.rhaddr(5 downto 2) = "1111") and (r.cfg.command = "100")) -- exit on refresh
then
v.hready := '0'; v.dqm := (others => '1');
if (r.sdcsn /= "11") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
end if;
elsif lineburst then
if (sdi.rhaddr(4 downto 2) = lline) and (r.casn = '1') then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6; else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1'; v.dqm := (others => '1');
v.casn := '1';
when rd6 =>
v.sdstate := sidle; v.idlecnt := (others => '1'); v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when sref =>
if (startsd = '1') -- and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_SR then
if r.trfc = "0000" then -- Minimum duration (= tRAS)
v.cfg.cke := '1';
v.sdcsn := (others => '0'); v.rasn := '1'; v.casn := '1';
end if;
if r.cfg.cke = '1' then
if (r.idlecnt = "0000") then -- tXSR ns with NOP
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.sref_tmpcom := r.cfg.command;
v.cfg.command := "100";
end if;
else
v.idlecnt := r.cfg.txsr;
end if;
end if;
when pd =>
if (startsd = '1') -- and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_PD then
v.cfg.cke := '1';
v.sdstate := sidle;
v.idlecnt := (others => '1');
end if;
when dpd =>
v.sdcsn := (others => '1'); v.sdwen := '1'; v.rasn := '1'; v.casn := '1';
v.cfg.renable := '0';
if (startsd = '1') then -- and r.hio = '0') then
v.hready := '1'; -- ack all accesses with Error response
v.startsd := '0';
hresp := HRESP_ERROR;
elsif r.cfg.pmode /= PM_DPD then
v.cfg.cke := '1';
if r.cfg.cke = '1' then
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.cfg.renable := '1';
end if;
end if;
when others =>
v.sdstate := sidle; v.idlecnt := (others => '1');
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when "010" => -- precharge
if (sdi.idle = '1') then
v.busy := '1';
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
end if;
when "100" => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when "110" =>
if (sdi.idle = '1') then
v.busy := '1';
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
if lineburst then
v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0011";
else
v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0111";
end if;
end if;
when "111" => -- Load Ext-Mode Reg
if (sdi.idle = '1') then
v.busy := '1';
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
v.address(16 downto 2) := "10000000" & r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0)
& r.cfg.pasr(2 downto 0);
end if;
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; --v.cfg.command := "000";
v.cfg.command := r.sref_tmpcom; v.sref_tmpcom := "000";
v.cmstate := leadout; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
when leadout =>
if r.trfc = "0000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
v.cfg.cke := '1';
if (sdi.idle and sdi.enable) = '1' and r.cfg.cke = '1' then
v.cfg.command := "010"; v.istate := pre;
end if;
when pre =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.istate := ref; v.icnt := "111";
end if;
when ref =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.icnt := r.icnt - 1;
if r.icnt = "000" then v.istate := lmode; v.cfg.command := "110"; end if;
end if;
when lmode =>
if r.cfg.command = "000" then
if r.cfg.mobileen = "11" then
v.cfg.command := "111"; v.istate := emode;
else
v.istate := finish;
end if;
end if;
when emode =>
if r.cfg.command = "000" then
v.istate := finish;
end if;
when others =>
if sdi.enable = '0' and r.sdstate /= dpd then
v.istate := iidle;
end if;
end case;
if (sdi.hready and sdi.hsel ) = '1' then
if sdi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
-- second part of main fsm
case r.mstate is
when active =>
if v.hready = '1' then
v.mstate := midle;
end if;
when others => null;
end case;
-- sdram refresh counter
if (r.cfg.renable = '1') and (r.istate = finish) and r.sdstate /= sref then
v.refresh := r.refresh - 1;
if (v.refresh(14) and not r.refresh(14)) = '1' then
v.refresh := r.cfg.refresh;
v.cfg.command := "100";
arefresh := '1';
end if;
end if;
-- APB register access
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "01" =>
if pageburst = 2 then v.cfg.pageburst := apbi.pwdata(17); end if;
if sdi.enable = '1' then
v.cfg.command(2 downto 1) := apbi.pwdata(20 downto 19);
end if;
v.cfg.csize := apbi.pwdata(22 downto 21);
v.cfg.bsize := apbi.pwdata(25 downto 23);
v.cfg.casdel := apbi.pwdata(26);
v.cfg.trfc := apbi.pwdata(29 downto 27);
v.cfg.trp := apbi.pwdata(30);
v.cfg.renable := apbi.pwdata(31);
when "10" =>
v.cfg.refresh := apbi.pwdata(26 downto 12);
v.refresh := (others => '0');
when "11" =>
if r.cfg.mobileen(1) = '1' and mobile /= 3 then v.cfg.mobileen(0) := apbi.pwdata(31); end if;
if r.cfg.pmode = "000" then
v.cfg.cke := apbi.pwdata(30);
end if;
if r.cfg.mobileen(1) = '1' then
if sdi.enable = '1' then
v.cfg.command(0) := apbi.pwdata(29);
end if;
v.cfg.txsr := apbi.pwdata(23 downto 20);
v.cfg.pmode := apbi.pwdata(18 downto 16);
v.cfg.ds(3 downto 2) := apbi.pwdata( 6 downto 5);
v.cfg.tcsr(3 downto 2) := apbi.pwdata( 4 downto 3);
v.cfg.pasr(5 downto 3) := apbi.pwdata( 2 downto 0);
end if;
when others =>
end case;
end if;
-- Disable CS and DPD when Mobile SDR is Disabled
if r.cfg.mobileen(0) = '0' then v.cfg.pmode(2) := '0'; end if;
-- Update EMR when ds, tcsr or pasr change
if r.cfg.command = "000" and arefresh = '0' and r.cfg.mobileen(0) = '1' then
if r.cfg.ds(1 downto 0) /= r.cfg.ds(3 downto 2) then
v.cfg.command := "111"; v.cfg.ds(1 downto 0) := r.cfg.ds(3 downto 2);
end if;
if r.cfg.tcsr(1 downto 0) /= r.cfg.tcsr(3 downto 2) then
v.cfg.command := "111"; v.cfg.tcsr(1 downto 0) := r.cfg.tcsr(3 downto 2);
end if;
if r.cfg.pasr(2 downto 0) /= r.cfg.pasr(5 downto 3) then
v.cfg.command := "111"; v.cfg.pasr(2 downto 0) := r.cfg.pasr(5 downto 3);
end if;
end if;
regsd := (others => '0');
case apbi.paddr(3 downto 2) is
when "01" =>
regsd(31 downto 19) := r.cfg.renable & r.cfg.trp & r.cfg.trfc &
r.cfg.casdel & r.cfg.bsize & r.cfg.csize & r.cfg.command(2 downto 1);
if not lineburst then regsd(17) := '1'; end if;
regsd(16) := r.cfg.mobileen(1);
when "11" =>
regsd(31) := r.cfg.mobileen(0);
regsd(30) := r.cfg.cke;
regsd(30) := r.cfg.command(0);
regsd(23 downto 0) := r.cfg.txsr & '0' & r.cfg.pmode & "000000000" &
r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0) & r.cfg.pasr(2 downto 0);
when others =>
regsd(26 downto 12) := r.cfg.refresh;
end case;
sdmo.prdata <= regsd;
-- synchronise with sram/prom controller
if fast = 0 then
if (r.sdstate < wr4) or (v.hsel = '1') then v.busy := '1';end if;
else
if (r.sdstate < wr4) or (r.startsd = '1') then v.busy := '1';end if;
end if;
v.busy := v.busy or r.bdelay;
busy := v.busy or r.busy;
v.aload := r.busy and not v.busy;
aload := v.aload;
-- generate memory address
sdmo.address <= v.address;
-- reset
if rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := iidle;
v.cmstate := midle;
v.hsel := '0';
v.cfg.command := "000";
v.cfg.csize := "10";
v.cfg.bsize := "000";
v.cfg.casdel := '1';
v.cfg.trfc := "111";
v.cfg.renable := '0';
v.cfg.trp := '1';
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '1';
v.startsd := '0';
if (pageburst = 2) then
v.cfg.pageburst := '0';
end if;
if mobile >= 2 then v.cfg.mobileen := "11";
elsif mobile = 1 then v.cfg.mobileen := "10";
else v.cfg.mobileen := "00"; end if;
v.cfg.txsr := (others => '1');
v.cfg.pmode := (others => '0');
v.cfg.ds := (others => '0');
v.cfg.tcsr := (others => '0');
v.cfg.pasr := (others => '0');
if mobile >= 2 then v.cfg.cke := '0';
else v.cfg.cke := '1'; end if;
v.sref_tmpcom := "000";
v.idlecnt := (others => '1');
end if;
ri <= v;
sdmo.bdrive <= v.bdrive;
--sdo.sdcke <= (others => '1');
sdo.sdcke <= (others => r.cfg.cke);
sdo.sdcsn <= r.sdcsn;
sdo.sdwen <= r.sdwen;
sdo.dqm <= r.dqm;
sdo.rasn <= r.rasn;
sdo.casn <= r.casn;
sdmo.busy <= busy;
sdmo.aload <= aload;
sdmo.hready <= r.hready;
sdmo.vhready <= v.hready;
sdmo.hresp <= hresp;
sdmo.hsel <= r.hsel;
sdmo.bsel <= r.bsel;
end process;
regs : process(clk,rst)
begin
if rising_edge(clk) then
r <= ri;
if rst = '0' then
r.icnt <= (others => '0');
end if;
end if;
if rst = '0' then
r.bdrive <= '0';
r.sdcsn <= (others => '1');
end if;
end process;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/misc/ahbdma.vhd | 3 | 5554 | -- GAISLER_LICENSE
-----------------------------------------------------------------------------
-- Entity: dma
-- File: dma.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Simple DMA (needs the AHB master interface)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
entity ahbdma is
generic (
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
dbuf : integer := 4);
port (
rst : in std_logic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end;
architecture struct of ahbdma is
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBDMA, 0, 0, pirq),
1 => apb_iobar(paddr, pmask));
type dma_state_type is (readc, writec);
subtype word32 is std_logic_vector(31 downto 0);
type datavec is array (0 to dbuf-1) of word32;
type reg_type is record
srcaddr : std_logic_vector(31 downto 0);
srcinc : std_logic_vector(1 downto 0);
dstaddr : std_logic_vector(31 downto 0);
dstinc : std_logic_vector(1 downto 0);
len : std_logic_vector(15 downto 0);
enable : std_logic;
write : std_logic;
inhibit : std_logic;
status : std_logic_vector(1 downto 0);
dstate : dma_state_type;
data : datavec;
cnt : integer range 0 to dbuf-1;
end record;
signal r, rin : reg_type;
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
begin
comb : process(apbi, dmao, rst, r)
variable v : reg_type;
variable regd : std_logic_vector(31 downto 0); -- data from registers
variable start : std_logic;
variable burst : std_logic;
variable write : std_logic;
variable ready : std_logic;
variable retry : std_logic;
variable mexc : std_logic;
variable irq : std_logic;
variable address : std_logic_vector(31 downto 0); -- DMA address
variable size : std_logic_vector( 1 downto 0); -- DMA transfer size
variable newlen : std_logic_vector(15 downto 0);
variable oldaddr : std_logic_vector(9 downto 0);
variable newaddr : std_logic_vector(9 downto 0);
variable oldsize : std_logic_vector( 1 downto 0);
variable ainc : std_logic_vector( 3 downto 0);
begin
v := r; regd := (others => '0'); burst := '0'; start := '0';
write := '0'; ready := '0'; mexc := '0';
size := r.srcinc; irq := '0'; v.inhibit := '0';
if r.write = '0' then address := r.srcaddr;
else address := r.dstaddr; end if;
newlen := r.len - 1;
if (r.cnt < dbuf-1) or (r.len(9 downto 2) = "11111111") then burst := '1';
else burst := '0'; end if;
start := r.enable;
if dmao.active = '1' then
if r.write = '0' then
if dmao.ready = '1' then
v.data(r.cnt) := ahbreadword(dmao.rdata);
if r.cnt = dbuf-1 then
v.write := '1'; v.cnt := 0; v.inhibit := '1';
address := r.dstaddr; size := r.dstinc;
else v.cnt := r.cnt + 1; end if;
end if;
else
if r.cnt = dbuf-1 then start := '0'; end if;
if dmao.ready = '1' then
if r.cnt = dbuf-1 then v.cnt := 0;
v.write := '0'; v.len := newlen; v.enable := start; irq := start;
else v.cnt := r.cnt + 1; end if;
end if;
end if;
end if;
if r.write = '0' then oldaddr := r.srcaddr(9 downto 0); oldsize := r.srcinc;
else oldaddr := r.dstaddr(9 downto 0); oldsize := r.dstinc; end if;
ainc := decode(oldsize);
newaddr := oldaddr + ainc(3 downto 0);
if (dmao.active and dmao.ready) = '1' then
if r.write = '0' then v.srcaddr(9 downto 0) := newaddr;
else v.dstaddr(9 downto 0) := newaddr; end if;
end if;
-- read DMA registers
case apbi.paddr(3 downto 2) is
when "00" => regd := r.srcaddr;
when "01" => regd := r.dstaddr;
when "10" => regd(20 downto 0) := r.enable & r.srcinc & r.dstinc & r.len;
when others => null;
end case;
-- write DMA registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "00" =>
v.srcaddr := apbi.pwdata;
when "01" =>
v.dstaddr := apbi.pwdata;
when "10" =>
v.len := apbi.pwdata(15 downto 0);
v.srcinc := apbi.pwdata(17 downto 16);
v.dstinc := apbi.pwdata(19 downto 18);
v.enable := apbi.pwdata(20);
when others => null;
end case;
end if;
if rst = '0' then
v.dstate := readc; v.enable := '0'; v.write := '0';
v.cnt := 0;
end if;
rin <= v;
apbo.prdata <= regd;
dmai.address <= address;
dmai.wdata <= ahbdrivedata(r.data(r.cnt));
dmai.start <= start and not v.inhibit;
dmai.burst <= burst;
dmai.write <= v.write;
dmai.size <= '0' & size;
apbo.pirq <= (others =>'0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
end process;
ahbif : ahbmst generic map (hindex => hindex, devid => 16#26#, incaddr => 1)
port map (rst, clk, dmai, dmao, ahbi, ahbo);
regs : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbdma" & tost(pindex) &
": AHB DMA Unit rev " & tost(0) & ", irq " & tost(pirq));
-- pragma translate_on
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/tech/unisim/ise/unisim_VPKG.vhd | 4 | 13609 | ----------------------------------------------------------------------------
-- Simple simulation models for some Xilinx blocks
----------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
library STD;
use STD.TEXTIO.all;
package vpkg is
signal GTS : std_logic := '0';
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN STRING := "";
Constant Unit : IN STRING := "";
Constant ExpectedValueMsg : IN STRING := "";
Constant ExpectedGenericValue : IN STRING := "";
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN INTEGER;
Constant Unit : IN STRING := "";
Constant ExpectedValueMsg : IN STRING := "";
Constant ExpectedGenericValue : IN INTEGER;
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN BOOLEAN;
Constant Unit : IN STRING := "";
Constant ExpectedValueMsg : IN STRING := "";
Constant ExpectedGenericValue : IN STRING := "";
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN INTEGER;
CONSTANT Unit : IN STRING := "";
CONSTANT ExpectedValueMsg : IN STRING := "";
CONSTANT ExpectedGenericValue : IN STRING := "";
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN REAL;
CONSTANT Unit : IN STRING := "";
CONSTANT ExpectedValueMsg : IN STRING := "";
CONSTANT ExpectedGenericValue : IN STRING := "";
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
);
procedure detect_resolution ( constant model_name : in string);
function slv_to_int (slv : in std_logic_vector) return integer;
function addr_is_valid (slv : in std_logic_vector) return boolean ;
function DECODE_ADDR4 (
ADDRESS : in std_logic_vector(3 downto 0)
) return integer;
function DECODE_ADDR5 (
ADDRESS : in std_logic_vector(4 downto 0)
) return integer;
function SLV_TO_STR (
SLV : in std_logic_vector
) return string;
end;
package body vpkg is
function SLV_TO_STR (
SLV : in std_logic_vector
) return string is
variable j : integer := SLV'length;
variable STR : string (SLV'length downto 1);
begin
for I in SLV'high downto SLV'low loop
case SLV(I) is
when '0' => STR(J) := '0';
when '1' => STR(J) := '1';
when 'X' => STR(J) := 'X';
when 'U' => STR(J) := 'U';
when others => STR(J) := 'X';
end case;
J := J - 1;
end loop;
return STR;
end SLV_TO_STR;
function DECODE_ADDR4 (
ADDRESS : in std_logic_vector(3 downto 0)
) return integer is
variable I : integer;
begin
case ADDRESS is
when "0000" => I := 0;
when "0001" => I := 1;
when "0010" => I := 2;
when "0011" => I := 3;
when "0100" => I := 4;
when "0101" => I := 5;
when "0110" => I := 6;
when "0111" => I := 7;
when "1000" => I := 8;
when "1001" => I := 9;
when "1010" => I := 10;
when "1011" => I := 11;
when "1100" => I := 12;
when "1101" => I := 13;
when "1110" => I := 14;
when "1111" => I := 15;
when others => I := 16;
end case;
return I;
end DECODE_ADDR4;
function ADDR_IS_VALID (
SLV : in std_logic_vector
) return boolean is
variable IS_VALID : boolean := TRUE;
begin
for I in SLV'high downto SLV'low loop
if (SLV(I) /= '0' AND SLV(I) /= '1') then
IS_VALID := FALSE;
end if;
end loop;
return IS_VALID;
end ADDR_IS_VALID;
function SLV_TO_INT(SLV: in std_logic_vector
) return integer is
variable int : integer;
begin
int := 0;
for i in SLV'high downto SLV'low loop
int := int * 2;
if SLV(i) = '1' then
int := int + 1;
end if;
end loop;
return int;
end;
procedure detect_resolution (
constant model_name : in string
) IS
variable test_value : time;
variable Message : LINE;
BEGIN
test_value := 1 ps;
if (test_value = 0 ps) then
Write (Message, STRING'(" Simulator Resolution Error : "));
Write (Message, STRING'(" Simulator resolution is set to a value greater than 1 ps. "));
Write (Message, STRING'(" In order to simulate the "));
Write (Message, model_name);
Write (Message, STRING'(", the simulator resolution must be set to 1ps or smaller "));
ASSERT FALSE REPORT Message.ALL SEVERITY ERROR;
DEALLOCATE (Message);
end if;
END detect_resolution;
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN STRING := "";
Constant Unit : IN STRING := "";
Constant ExpectedValueMsg : IN STRING := "";
Constant ExpectedGenericValue : IN STRING := "";
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE Message : LINE;
BEGIN
Write ( Message, HeaderMsg );
Write ( Message, STRING'(" The attribute ") );
Write ( Message, GenericName );
Write ( Message, STRING'(" on ") );
Write ( Message, EntityName );
Write ( Message, STRING'(" instance ") );
Write ( Message, InstanceName );
Write ( Message, STRING'(" is set to ") );
Write ( Message, GenericValue );
Write ( Message, Unit );
Write ( Message, '.' & LF );
Write ( Message, ExpectedValueMsg );
Write ( Message, ExpectedGenericValue );
Write ( Message, Unit );
Write ( Message, TailMsg );
ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity;
DEALLOCATE (Message);
END GenericValueCheckMessage;
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN INTEGER;
CONSTANT Unit : IN STRING := "";
CONSTANT ExpectedValueMsg : IN STRING := "";
CONSTANT ExpectedGenericValue : IN INTEGER;
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE Message : LINE;
BEGIN
Write ( Message, HeaderMsg );
Write ( Message, STRING'(" The attribute ") );
Write ( Message, GenericName );
Write ( Message, STRING'(" on ") );
Write ( Message, EntityName );
Write ( Message, STRING'(" instance ") );
Write ( Message, InstanceName );
Write ( Message, STRING'(" is set to ") );
Write ( Message, GenericValue );
Write ( Message, Unit );
Write ( Message, '.' & LF );
Write ( Message, ExpectedValueMsg );
Write ( Message, ExpectedGenericValue );
Write ( Message, Unit );
Write ( Message, TailMsg );
ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity;
DEALLOCATE (Message);
END GenericValueCheckMessage;
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN BOOLEAN;
Constant Unit : IN STRING := "";
CONSTANT ExpectedValueMsg : IN STRING := "";
CONSTANT ExpectedGenericValue : IN STRING := "";
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE Message : LINE;
BEGIN
Write ( Message, HeaderMsg );
Write ( Message, STRING'(" The attribute ") );
Write ( Message, GenericName );
Write ( Message, STRING'(" on ") );
Write ( Message, EntityName );
Write ( Message, STRING'(" instance ") );
Write ( Message, InstanceName );
Write ( Message, STRING'(" is set to ") );
Write ( Message, GenericValue );
Write ( Message, Unit );
Write ( Message, '.' & LF );
Write ( Message, ExpectedValueMsg );
Write ( Message, ExpectedGenericValue );
Write ( Message, Unit );
Write ( Message, TailMsg );
ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity;
DEALLOCATE (Message);
END GenericValueCheckMessage;
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN INTEGER;
CONSTANT Unit : IN STRING := "";
CONSTANT ExpectedValueMsg : IN STRING := "";
CONSTANT ExpectedGenericValue : IN STRING := "";
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE Message : LINE;
BEGIN
Write ( Message, HeaderMsg );
Write ( Message, STRING'(" The attribute ") );
Write ( Message, GenericName );
Write ( Message, STRING'(" on ") );
Write ( Message, EntityName );
Write ( Message, STRING'(" instance ") );
Write ( Message, InstanceName );
Write ( Message, STRING'(" is set to ") );
Write ( Message, GenericValue );
Write ( Message, Unit );
Write ( Message, '.' & LF );
Write ( Message, ExpectedValueMsg );
Write ( Message, ExpectedGenericValue );
Write ( Message, Unit );
Write ( Message, TailMsg );
ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity;
DEALLOCATE (Message);
END GenericValueCheckMessage;
PROCEDURE GenericValueCheckMessage (
CONSTANT HeaderMsg : IN STRING := " Attribute Syntax Error ";
CONSTANT GenericName : IN STRING := "";
CONSTANT EntityName : IN STRING := "";
CONSTANT InstanceName : IN STRING := "";
CONSTANT GenericValue : IN REAL;
CONSTANT Unit : IN STRING := "";
CONSTANT ExpectedValueMsg : IN STRING := "";
CONSTANT ExpectedGenericValue : IN STRING := "";
CONSTANT TailMsg : IN STRING;
CONSTANT MsgSeverity : IN SEVERITY_LEVEL := WARNING
) IS
VARIABLE Message : LINE;
BEGIN
Write ( Message, HeaderMsg );
Write ( Message, STRING'(" The attribute ") );
Write ( Message, GenericName );
Write ( Message, STRING'(" on ") );
Write ( Message, EntityName );
Write ( Message, STRING'(" instance ") );
Write ( Message, InstanceName );
Write ( Message, STRING'(" is set to ") );
Write ( Message, GenericValue );
Write ( Message, Unit );
Write ( Message, '.' & LF );
Write ( Message, ExpectedValueMsg );
Write ( Message, ExpectedGenericValue );
Write ( Message, Unit );
Write ( Message, TailMsg );
ASSERT FALSE REPORT Message.ALL SEVERITY MsgSeverity;
DEALLOCATE (Message);
END GenericValueCheckMessage;
function DECODE_ADDR5 (
ADDRESS : in std_logic_vector(4 downto 0)
) return integer is
variable I : integer;
begin
case ADDRESS is
when "00000" => I := 0;
when "00001" => I := 1;
when "00010" => I := 2;
when "00011" => I := 3;
when "00100" => I := 4;
when "00101" => I := 5;
when "00110" => I := 6;
when "00111" => I := 7;
when "01000" => I := 8;
when "01001" => I := 9;
when "01010" => I := 10;
when "01011" => I := 11;
when "01100" => I := 12;
when "01101" => I := 13;
when "01110" => I := 14;
when "01111" => I := 15;
when "10000" => I := 16;
when "10001" => I := 17;
when "10010" => I := 18;
when "10011" => I := 19;
when "10100" => I := 20;
when "10101" => I := 21;
when "10110" => I := 22;
when "10111" => I := 23;
when "11000" => I := 24;
when "11001" => I := 25;
when "11010" => I := 26;
when "11011" => I := 27;
when "11100" => I := 28;
when "11101" => I := 29;
when "11110" => I := 30;
when "11111" => I := 31;
when others => I := 32;
end case;
return I;
end DECODE_ADDR5;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/gaisler/leon3v3/libleon3.vhd | 1 | 7842 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: libleon3
-- File: libleon3.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: LEON3 internal components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.libfpu.all;
use gaisler.mmuiface.all;
package libleon3 is
component proc3
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := 0;
memtech : integer range 0 to NTECH := 0;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0; -- support SMP systems
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : out std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
crami : out cram_in_type;
cramo : in cram_out_type;
tbi : out tracebuf_in_type;
tbo : in tracebuf_out_type;
fpi : out fpc_in_type;
fpo : in fpc_out_type;
cpi : out fpc_in_type;
cpo : in fpc_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
hclk, sclk : in std_ulogic;
hclken : in std_ulogic
);
end component;
component grfpwx
generic (
fabtech : integer := 0;
memtech : integer := 0;
mul : integer range 0 to 3 := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
netlist : integer := 0;
index : integer := 0);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type
);
end component;
component mfpwx
generic (
tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
rfft : integer range 0 to 2 := 0); -- 0 - no protection, 1 - parity
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type
);
end component;
component grlfpwx
generic (
tech : integer := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
pipe : integer := 0;
netlist : integer := 0;
index : integer := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type
);
end component;
component regfile_3p_l3
generic (
tech : integer := 0;
abits : integer := 6;
dbits : integer := 8;
wrfst : integer := 0;
numregs : integer := 64;
testen : integer := 0);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
rclk : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0);
testin : in std_logic_vector(3 downto 0) := "0000");
end component;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/eth/wrapper/greth_gbit_gen.vhd | 1 | 13434 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_gbit_gen
-- File: greth_gbit_gen.vhd
-- Author: Marko Isomaki
-- Description: Generic Gigabit Ethernet MAC
------------------------------------------------------------------------------
library ieee;
library grlib;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library eth;
use eth.ethcomp.all;
entity greth_gbit_gen is
generic(
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 1;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
sim : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahbg : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--edcl ahb mst in
ehgrant : in std_ulogic;
ehready : in std_ulogic;
ehresp : in std_logic_vector(1 downto 0);
ehrdata : in std_logic_vector(31 downto 0);
--edcl ahb mst out
ehbusreq : out std_ulogic;
ehlock : out std_ulogic;
ehtrans : out std_logic_vector(1 downto 0);
ehaddr : out std_logic_vector(31 downto 0);
ehwrite : out std_ulogic;
ehsize : out std_logic_vector(2 downto 0);
ehburst : out std_logic_vector(2 downto 0);
ehprot : out std_logic_vector(3 downto 0);
ehwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--ethernet input signals
gtx_clk : in std_ulogic;
tx_clk : in std_ulogic;
rx_clk : in std_ulogic;
rxd : in std_logic_vector(7 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_crs : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
mdint : in std_ulogic;
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(7 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic;
testoen : in std_ulogic;
edcladdr : in std_logic_vector(3 downto 0);
edclsepahb : in std_ulogic;
edcldisable : in std_ulogic;
speed : out std_ulogic;
gbit : out std_ulogic
);
end entity;
architecture rtl of greth_gbit_gen is
--host constants
constant fifosize : integer := 512;
constant fabits : integer := log2(fifosize);
constant fsize : std_logic_vector(fabits downto 0) :=
conv_std_logic_vector(fifosize, fabits+1);
--edcl constants
type szvct is array (0 to 6) of integer;
constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256);
constant eabits: integer := log2(edclbufsz) + 8;
constant ebufsize : integer := ebuf(log2(edclbufsz));
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(8 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(8 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(8 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(8 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--edcl buf
signal erenable : std_ulogic;
signal eraddress : std_logic_vector(15 downto 0);
signal ewritem : std_ulogic;
signal ewritel : std_ulogic;
signal ewaddressm : std_logic_vector(15 downto 0);
signal ewaddressl : std_logic_vector(15 downto 0);
signal ewdata : std_logic_vector(31 downto 0);
signal erdata : std_logic_vector(31 downto 0);
begin
gtxc0: greth_gbitc
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
slot_time => slot_time,
mdcscaler => mdcscaler,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
burstlength => burstlength,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
sim => sim,
oepol => oepol,
scanen => scanen,
mdint_pol => mdint_pol,
enable_mdint => enable_mdint,
multicast => multicast,
edclsepahbg => edclsepahbg,
ramdebug => ramdebug)
port map(
rst => rst,
clk => clk,
--ahb mst in
hgrant => hgrant,
hready => hready,
hresp => hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => hbusreq,
hlock => hlock,
htrans => htrans,
haddr => haddr,
hwrite => hwrite,
hsize => hsize,
hburst => hburst,
hprot => hprot,
hwdata => hwdata,
--edcl ahb mst in
ehgrant => ehgrant,
ehready => ehready,
ehresp => ehresp,
ehrdata => ehrdata,
--edcl ahb mst out
ehbusreq => ehbusreq,
ehlock => ehlock,
ehtrans => ehtrans,
ehaddr => ehaddr,
ehwrite => ehwrite,
ehsize => ehsize,
ehburst => ehburst,
ehprot => ehprot,
ehwdata => ehwdata,
--apb slv in
psel => psel,
penable => penable,
paddr => paddr,
pwrite => pwrite,
pwdata => pwdata,
--apb slv out
prdata => prdata,
--irq
irq => irq,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--edcl buf
erenable => erenable,
eraddress => eraddress,
ewritem => ewritem,
ewritel => ewritel,
ewaddressm => ewaddressm,
ewaddressl => ewaddressl,
ewdata => ewdata,
erdata => erdata,
--ethernet input signals
gtx_clk => gtx_clk,
tx_clk => tx_clk,
rx_clk => rx_clk,
rxd => rxd,
rx_dv => rx_dv,
rx_er => rx_er,
rx_col => rx_col,
rx_crs => rx_crs,
mdio_i => mdio_i,
phyrstaddr => phyrstaddr,
mdint => mdint,
--ethernet output signals
reset => reset,
txd => txd,
tx_en => tx_en,
tx_er => tx_er,
mdc => mdc,
mdio_o => mdio_o,
mdio_oe => mdio_oe,
--scantest
testrst => testrst,
testen => testen,
testoen => testoen,
edcladdr => edcladdr,
edclsepahb => edclsepahb,
edcldisable => edcldisable,
speed => speed,
gbit => gbit);
-------------------------------------------------------------------------------
-- FIFOS ----------------------------------------------------------------------
-------------------------------------------------------------------------------
nft : if ft = 0 generate
tx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0)
port map(clk, txrenable, txraddress(fabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(fabits-1 downto 0), txwdata);
rx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata);
end generate;
ft1 : if ft /= 0 generate
tx_fifo0 : syncram_2pft generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0, ft => ft)
port map(clk, txrenable, txraddress(fabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(fabits-1 downto 0), txwdata);
rx_fifo0 : syncram_2pft generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0, ft => ft)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata);
end generate;
-------------------------------------------------------------------------------
-- EDCL buffer ram ------------------------------------------------------------
-------------------------------------------------------------------------------
edclramnft : if (edcl /= 0) and (edclft = 0) generate
r0 : syncram_2p generic map (memtech, eabits, 16) port map (
clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16));
r1 : syncram_2p generic map (memtech, eabits, 16) port map (
clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0));
end generate;
edclramft1 : if (edcl /= 0) and (edclft /= 0) generate
r0 : syncram_2pft generic map (memtech, eabits, 16, 0, 0, edclft) port map (
clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16));
r1 : syncram_2pft generic map (memtech, eabits, 16, 0, 0, edclft) port map (
clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0));
end generate;
end architecture;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-altera-ep3c25-eek/altera_eek_clkgen.vhd | 1 | 4171 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altpll;
library grlib;
use grlib.stdlib.all;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity altera_eek_clkgen is
generic (
clk0_mul : integer := 1;
clk0_div : integer := 1;
clk1_mul : integer := 1;
clk1_div : integer := 1;
clk_freq : integer := 25000);
port (
inclk0 : in std_ulogic;
clk0 : out std_ulogic;
clk0x3 : out std_ulogic;
clksel : in std_logic_vector(1 downto 0);
locked : out std_ulogic);
end;
architecture rtl of altera_eek_clkgen is
component altpll
generic (
intended_device_family : string := "CycloneIII" ;
operation_mode : string := "NORMAL" ;
compensate_clock : string := "clock0";
inclk0_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1;
clk3_multiply_by : positive := 1;
clk3_divide_by : positive := 1
);
port (
inclk : in std_logic_vector(1 downto 0);
clkena : in std_logic_vector(5 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
signal clkena : std_logic_vector (5 downto 0);
signal clkout : std_logic_vector (4 downto 0);
signal inclk : std_logic_vector (1 downto 0);
constant clk_period : integer := 1000000000/clk_freq;
constant CLK0_MUL3X : integer := clk0_mul * 3;
constant CLK1_MUL3X : integer := clk1_mul * 3;
constant VERSION : integer := 1;
attribute syn_keep : boolean;
attribute syn_keep of clkout : signal is true;
begin
clkena(5 downto 4) <= (others => '0');
clkena(0) <= '1';
clkena(1) <= '1';
clkena(2) <= '1';
clkena(3) <= '1';
inclk <= '0' & inclk0;
clk_select: process (clkout, clksel)
begin -- process clk_select
case clksel is
when "00" => clk0 <= clkout(0); clk0x3 <= clkout(1);
when "01" => clk0 <= clkout(2); clk0x3 <= clkout(3);
when others => clk0 <= '0'; clk0x3 <= '0';
end case;
end process clk_select;
altpll0 : altpll
generic map (
intended_device_family => "Cyclone III",
operation_mode => "NO_COMPENSATION", inclk0_input_frequency => clk_period,
width_clock => 5, compensate_clock => "CLK1",
clk0_multiply_by => clk0_mul, clk0_divide_by => clk0_div,
clk1_multiply_by => CLK0_MUL3X, clk1_divide_by => clk0_div,
clk2_multiply_by => clk1_mul, clk2_divide_by => clk1_div,
clk3_multiply_by => CLK1_MUL3X, clk3_divide_by => clk1_div)
port map (clkena => clkena, inclk => inclk,
clk => clkout, locked => locked);
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_cycloneiii" & ": altpll lcd/vga clock generator, version " & tost(VERSION)
);
-- pragma translate_on
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-altera-ep2s60-ddr/config.vhd | 1 | 5448 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := stratix2;
constant CFG_MEMTECH : integer := stratix2;
constant CFG_PADTECH : integer := stratix2;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := stratix2;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 4;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 4;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (100);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (32);
constant CFG_DDRSP_RSKEW : integer := 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#FFFF#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/designs/leon3-terasic-de0-nano/mt48lc16m16a2.vhd | 6 | 69329 |
--*****************************************************************************
--
-- Micron Semiconductor Products, Inc.
--
-- Copyright 1997, Micron Semiconductor Products, Inc.
-- All rights reserved.
--
--*****************************************************************************
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.ALL;
use std.textio.all;
PACKAGE mti_pkg IS
FUNCTION To_StdLogic (s : BIT) RETURN STD_LOGIC;
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER;
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER;
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER;
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR);
END mti_pkg;
PACKAGE BODY mti_pkg IS
-- Convert BIT to STD_LOGIC
FUNCTION To_StdLogic (s : BIT) RETURN STD_LOGIC IS
BEGIN
CASE s IS
WHEN '0' => RETURN ('0');
WHEN '1' => RETURN ('1');
WHEN OTHERS => RETURN ('0');
END CASE;
END;
-- Convert STD_LOGIC to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
IF input = '1' THEN
result := weight;
ELSE
result := 0; -- if unknowns, default to logic 0
END IF;
RETURN result;
END TO_INTEGER;
-- Convert BIT_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Convert STD_LOGIC_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Conver INTEGER to BIT_VECTOR
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR) IS
VARIABLE work,offset,outputlen,j : INTEGER := 0;
BEGIN
--length of vector
IF output'LENGTH > 32 THEN --'
outputlen := 32;
offset := output'LENGTH - 32; --'
IF input >= 0 THEN
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '0'; --'
END LOOP;
ELSE
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '1'; --'
END LOOP;
END IF;
ELSE
outputlen := output'LENGTH; --'
END IF;
--positive value
IF (input >= 0) THEN
work := input;
j := outputlen - 1;
FOR i IN 1 to 32 LOOP
IF j >= 0 then
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '0'; --'
ELSE
output(output'HIGH-j-offset) := '1'; --'
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '0'; --'
END IF;
--negative value
ELSE
work := (-input) - 1;
j := outputlen - 1;
FOR i IN 1 TO 32 LOOP
IF j>= 0 THEN
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '1'; --'
ELSE
output(output'HIGH-j-offset) := '0'; --'
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '1'; --'
END IF;
END IF;
END TO_BITVECTOR;
END mti_pkg;
-----------------------------------------------------------------------------------------
--
-- File Name: MT48LC16M16A2.VHD
-- Version: 0.0g
-- Date: June 29th, 2000
-- Model: Behavioral
-- Simulator: Model Technology (PC version 5.3 PE)
--
-- Dependencies: None
--
-- Author: Son P. Huynh
-- Email: [email protected]
-- Phone: (208) 368-3825
-- Company: Micron Technology, Inc.
-- Part Number: MT48LC16M16A2 (4Mb x 16 x 4 Banks)
--
-- Description: Micron 256Mb SDRAM
--
-- Limitation: - Doesn't check for 4096-cycle refresh --'
--
-- Note: - Set simulator resolution to "ps" accuracy
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Copyright (c) 1998 Micron Semiconductor Products, Inc.
-- All rights researved
--
-- Rev Author Phone Date Changes
-- ---- ---------------------------- ---------- -------------------------------------
-- 0.0g Son Huynh 208-368-3825 06/29/2000 Add Load/Dump memory array
-- Micron Technology Inc. Modify tWR + tRAS timing check
--
-- 0.0f Son Huynh 208-368-3825 07/08/1999 Fix tWR = 1 Clk + 7.5 ns (Auto)
-- Micron Technology Inc. Fix tWR = 15 ns (Manual)
-- Fix tRP (Autoprecharge to AutoRefresh)
--
-- 0.0c Son P. Huynh 208-368-3825 04/08/1999 Fix tWR + tRP in Write with AP
-- Micron Technology Inc. Fix tRC check in Load Mode Register
--
-- 0.0b Son P. Huynh 208-368-3825 01/06/1998 Derive from 64Mb SDRAM model
-- Micron Technology Inc.
--
-----------------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY WORK;
USE WORK.MTI_PKG.ALL;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
ENTITY mt48lc16m16a2 IS
GENERIC (
-- Timing Parameters for -75 (PC133) and CAS Latency = 2
tAC : TIME := 6.0 ns;
tHZ : TIME := 7.0 ns;
tOH : TIME := 2.7 ns;
tMRD : INTEGER := 2; -- 2 Clk Cycles
tRAS : TIME := 44.0 ns;
tRC : TIME := 66.0 ns;
tRCD : TIME := 20.0 ns;
tRP : TIME := 20.0 ns;
tRRD : TIME := 15.0 ns;
tWRa : TIME := 7.5 ns; -- A2 Version - Auto precharge mode only (1 Clk + 7.5 ns)
tWRp : TIME := 15.0 ns; -- A2 Version - Precharge mode only (15 ns)
tAH : TIME := 0.8 ns;
tAS : TIME := 1.5 ns;
tCH : TIME := 2.5 ns;
tCL : TIME := 2.5 ns;
tCK : TIME := 10.0 ns;
tDH : TIME := 0.8 ns;
tDS : TIME := 1.5 ns;
tCKH : TIME := 0.8 ns;
tCKS : TIME := 1.5 ns;
tCMH : TIME := 0.8 ns;
tCMS : TIME := 1.5 ns;
addr_bits : INTEGER := 13;
data_bits : INTEGER := 16;
col_bits : INTEGER := 9;
index : INTEGER := 0;
fname : string := "ram.srec" -- File to read from
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '1';
Cs_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '1';
We_n : IN STD_LOGIC := '1';
Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
);
END mt48lc16m16a2;
ARCHITECTURE behave OF mt48lc16m16a2 IS
TYPE State IS (ACT, A_REF, BST, LMR, NOP, PRECH, READ, READ_A, WRITE, WRITE_A, LOAD_FILE, DUMP_FILE);
TYPE Array4xI IS ARRAY (3 DOWNTO 0) OF INTEGER;
TYPE Array4xT IS ARRAY (3 DOWNTO 0) OF TIME;
TYPE Array4xB IS ARRAY (3 DOWNTO 0) OF BIT;
TYPE Array4x2BV IS ARRAY (3 DOWNTO 0) OF BIT_VECTOR (1 DOWNTO 0);
TYPE Array4xCBV IS ARRAY (4 DOWNTO 0) OF BIT_VECTOR (Col_bits - 1 DOWNTO 0);
TYPE Array_state IS ARRAY (4 DOWNTO 0) OF State;
SIGNAL Operation : State := NOP;
SIGNAL Mode_reg : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL Active_enable, Aref_enable, Burst_term : BIT := '0';
SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : BIT := '0';
SIGNAL Burst_length_1, Burst_length_2, Burst_length_4, Burst_length_8 : BIT := '0';
SIGNAL Cas_latency_2, Cas_latency_3 : BIT := '0';
SIGNAL Ras_in, Cas_in, We_in : BIT := '0';
SIGNAL Write_burst_mode : BIT := '0';
SIGNAL RAS_clk, Sys_clk, CkeZ : BIT := '0';
-- Checking internal wires
SIGNAL Pre_chk : BIT_VECTOR (3 DOWNTO 0) := "0000";
SIGNAL Act_chk : BIT_VECTOR (3 DOWNTO 0) := "0000";
SIGNAL Dq_in_chk, Dq_out_chk : BIT := '0';
SIGNAL Bank_chk : BIT_VECTOR (1 DOWNTO 0) := "00";
SIGNAL Row_chk : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL Col_chk : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- CS# Decode
WITH Cs_n SELECT
Cas_in <= TO_BIT (Cas_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
WITH Cs_n SELECT
Ras_in <= TO_BIT (Ras_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
WITH Cs_n SELECT
We_in <= TO_BIT (We_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
-- Commands Decode
Active_enable <= NOT(Ras_in) AND Cas_in AND We_in;
Aref_enable <= NOT(Ras_in) AND NOT(Cas_in) AND We_in;
Burst_term <= Ras_in AND Cas_in AND NOT(We_in);
Mode_reg_enable <= NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in);
Prech_enable <= NOT(Ras_in) AND Cas_in AND NOT(We_in);
Read_enable <= Ras_in AND NOT(Cas_in) AND We_in;
Write_enable <= Ras_in AND NOT(Cas_in) AND NOT(We_in);
-- Burst Length Decode
Burst_length_1 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND NOT(Mode_reg(0));
Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0);
Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0));
Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0);
-- CAS Latency Decode
Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4));
Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4);
-- Write Burst Mode
Write_burst_mode <= Mode_reg(9);
-- RAS Clock for checking tWR and tRP
PROCESS
variable Clk0, Clk1 : integer := 0;
begin
RAS_clk <= '1';
wait for 0.5 ns;
RAS_clk <= '0';
wait for 0.5 ns;
if Clk0 > 100 or Clk1 > 100 then
wait;
else
if Clk = '1' and Cke = '1' then
Clk0 := 0;
Clk1 := Clk1 + 1;
elsif Clk = '0' and Cke = '1' then
Clk0 := Clk0 + 1;
Clk1 := 0;
end if;
end if;
END PROCESS;
-- System Clock
int_clk : PROCESS (Clk)
begin
IF Clk'LAST_VALUE = '0' AND Clk = '1' THEN --'
CkeZ <= TO_BIT(Cke, '1');
END IF;
Sys_clk <= CkeZ AND TO_BIT(Clk, '0');
END PROCESS;
state_register : PROCESS
-- NOTE: The extra bits in RAM_TYPE is for checking memory access. A logic 1 means
-- the location is in use. This will be checked when doing memory DUMP.
TYPE ram_type IS ARRAY (2**col_bits - 1 DOWNTO 0) OF BIT_VECTOR (data_bits DOWNTO 0);
TYPE ram_pntr IS ACCESS ram_type;
TYPE ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF ram_pntr;
VARIABLE Bank0 : ram_stor;
VARIABLE Bank1 : ram_stor;
VARIABLE Bank2 : ram_stor;
VARIABLE Bank3 : ram_stor;
VARIABLE Row_index, Col_index : INTEGER := 0;
VARIABLE Dq_temp : BIT_VECTOR (data_bits DOWNTO 0) := (OTHERS => '0');
VARIABLE Col_addr : Array4xCBV;
VARIABLE Bank_addr : Array4x2BV;
VARIABLE Dqm_reg0, Dqm_reg1 : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE Bank, Previous_bank : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Col_brst : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Row : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Col : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Burst_counter : INTEGER := 0;
VARIABLE Command : Array_state;
VARIABLE Bank_precharge : Array4x2BV;
VARIABLE A10_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Auto_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Read_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Write_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_read : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_write : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_bank : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE Count_time : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE Count_precharge : Array4xI := (0 & 0 & 0 & 0);
VARIABLE Data_in_enable, Data_out_enable : BIT := '0';
VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : BIT := '0';
VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : BIT := '0';
-- Timing Check
VARIABLE MRD_chk : INTEGER := 0;
VARIABLE WR_counter : Array4xI := (0 & 0 & 0 & 0);
VARIABLE WR_time : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE WR_chkp : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE RC_chk, RRD_chk : TIME := 0 ns;
VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns;
VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns;
VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns;
-- Load and Dumb variables
FILE file_load : TEXT open read_mode is fname; -- Data load
FILE file_dump : TEXT open write_mode is "dumpdata.txt"; -- Data dump
VARIABLE bank_load : bit_vector ( 1 DOWNTO 0);
VARIABLE rows_load : BIT_VECTOR (12 DOWNTO 0);
VARIABLE cols_load : BIT_VECTOR ( 8 DOWNTO 0);
VARIABLE data_load : BIT_VECTOR (15 DOWNTO 0);
VARIABLE i, j : INTEGER;
VARIABLE good_load : BOOLEAN;
VARIABLE l : LINE;
variable load : std_logic := '1';
variable dump : std_logic := '0';
variable ch : character;
variable rectype : bit_vector(3 downto 0);
variable recaddr : bit_vector(31 downto 0);
variable reclen : bit_vector(7 downto 0);
variable recdata : bit_vector(0 to 16*8-1);
-- Initialize empty rows
PROCEDURE Init_mem (Bank : bit_vector (1 DOWNTO 0); Row_index : INTEGER) IS
VARIABLE i, j : INTEGER := 0;
BEGIN
IF Bank = "00" THEN
IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty
Bank0 (Row_index) := NEW ram_type; -- Open new row for access
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank0 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "01" THEN
IF Bank1 (Row_index) = NULL THEN
Bank1 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank1 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "10" THEN
IF Bank2 (Row_index) = NULL THEN
Bank2 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank2 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "11" THEN
IF Bank3 (Row_index) = NULL THEN
Bank3 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank3 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
END IF;
END;
-- Burst Counter
PROCEDURE Burst_decode IS
VARIABLE Col_int : INTEGER := 0;
VARIABLE Col_vec, Col_temp : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- Advance Burst Counter
Burst_counter := Burst_counter + 1;
-- Burst Type
IF Mode_reg (3) = '0' THEN
Col_int := TO_INTEGER(Col);
Col_int := Col_int + 1;
TO_BITVECTOR (Col_int, Col_temp);
ELSIF Mode_reg (3) = '1' THEN
TO_BITVECTOR (Burst_counter, Col_vec);
Col_temp (2) := Col_vec (2) XOR Col_brst (2);
Col_temp (1) := Col_vec (1) XOR Col_brst (1);
Col_temp (0) := Col_vec (0) XOR Col_brst (0);
END IF;
-- Burst Length
IF Burst_length_2 = '1' THEN
Col (0) := Col_temp (0);
ELSIF Burst_length_4 = '1' THEN
Col (1 DOWNTO 0) := Col_temp (1 DOWNTO 0);
ELSIF Burst_length_8 = '1' THEN
Col (2 DOWNTO 0) := Col_temp (2 DOWNTO 0);
ELSE
Col := Col_temp;
END IF;
-- Burst Read Single Write
IF Write_burst_mode = '1' AND Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Data counter
IF Burst_length_1 = '1' THEN
IF Burst_counter >= 1 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_2 = '1' THEN
IF Burst_counter >= 2 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_4 = '1' THEN
IF Burst_counter >= 4 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_8 = '1' THEN
IF Burst_counter >= 8 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
END IF;
END;
BEGIN
WAIT ON Sys_clk, RAS_clk;
IF Sys_clk'event AND Sys_clk = '1' AND Load = '0' AND Dump = '0' THEN --'
-- Internal Command Pipeline
Command(0) := Command(1);
Command(1) := Command(2);
Command(2) := Command(3);
Command(3) := NOP;
Col_addr(0) := Col_addr(1);
Col_addr(1) := Col_addr(2);
Col_addr(2) := Col_addr(3);
Col_addr(3) := (OTHERS => '0');
Bank_addr(0) := Bank_addr(1);
Bank_addr(1) := Bank_addr(2);
Bank_addr(2) := Bank_addr(3);
Bank_addr(3) := "00";
Bank_precharge(0) := Bank_precharge(1);
Bank_precharge(1) := Bank_precharge(2);
Bank_precharge(2) := Bank_precharge(3);
Bank_precharge(3) := "00";
A10_precharge(0) := A10_precharge(1);
A10_precharge(1) := A10_precharge(2);
A10_precharge(2) := A10_precharge(3);
A10_precharge(3) := '0';
-- Operation Decode (Optional for showing current command on posedge clock / debug feature)
IF Active_enable = '1' THEN
Operation <= ACT;
ELSIF Aref_enable = '1' THEN
Operation <= A_REF;
ELSIF Burst_term = '1' THEN
Operation <= BST;
ELSIF Mode_reg_enable = '1' THEN
Operation <= LMR;
ELSIF Prech_enable = '1' THEN
Operation <= PRECH;
ELSIF Read_enable = '1' THEN
IF Addr(10) = '0' THEN
Operation <= READ;
ELSE
Operation <= READ_A;
END IF;
ELSIF Write_enable = '1' THEN
IF Addr(10) = '0' THEN
Operation <= WRITE;
ELSE
Operation <= WRITE_A;
END IF;
ELSE
Operation <= NOP;
END IF;
-- Dqm pipeline for Read
Dqm_reg0 := Dqm_reg1;
Dqm_reg1 := TO_BITVECTOR(Dqm);
-- Read or Write with Auto Precharge Counter
IF Auto_precharge (0) = '1' THEN
Count_precharge (0) := Count_precharge (0) + 1;
END IF;
IF Auto_precharge (1) = '1' THEN
Count_precharge (1) := Count_precharge (1) + 1;
END IF;
IF Auto_precharge (2) = '1' THEN
Count_precharge (2) := Count_precharge (2) + 1;
END IF;
IF Auto_precharge (3) = '1' THEN
Count_precharge (3) := Count_precharge (3) + 1;
END IF;
-- Auto Precharge Timer for tWR
if (Burst_length_1 = '1' OR Write_burst_mode = '1') then
if (Count_precharge(0) = 1) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 1) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 1) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 1) then
Count_time(3) := NOW;
end if;
elsif (Burst_length_2 = '1') then
if (Count_precharge(0) = 2) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 2) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 2) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 2) then
Count_time(3) := NOW;
end if;
elsif (Burst_length_4 = '1') then
if (Count_precharge(0) = 4) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 4) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 4) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 4) then
Count_time(3) := NOW;
end if;
elsif (Burst_length_8 = '1') then
if (Count_precharge(0) = 8) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 8) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 8) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 8) then
Count_time(3) := NOW;
end if;
end if;
-- tMRD Counter
MRD_chk := MRD_chk + 1;
-- tWR Counter
WR_counter(0) := WR_counter(0) + 1;
WR_counter(1) := WR_counter(1) + 1;
WR_counter(2) := WR_counter(2) + 1;
WR_counter(3) := WR_counter(3) + 1;
-- Auto Refresh
IF Aref_enable = '1' THEN
-- Auto Refresh to Auto Refresh
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Auto Refresh"
SEVERITY WARNING;
-- Precharge to Auto Refresh
ASSERT (NOW - RP_chk0 >= tRP OR NOW - RP_chk1 >= tRP OR NOW - RP_chk2 >= tRP OR NOW - RP_chk3 >= tRP)
REPORT "tRP violation during Auto Refresh"
SEVERITY WARNING;
-- All banks must be idle before refresh
IF (Pc_b3 ='0' OR Pc_b2 = '0' OR Pc_b1 ='0' OR Pc_b0 = '0') THEN
ASSERT (FALSE)
REPORT "All banks must be Precharge before Auto Refresh"
SEVERITY WARNING;
END IF;
-- Record current tRC time
RC_chk := NOW;
END IF;
-- Load Mode Register
IF Mode_reg_enable = '1' THEN
Mode_reg <= TO_BITVECTOR (Addr);
IF (Pc_b3 ='0' OR Pc_b2 = '0' OR Pc_b1 ='0' OR Pc_b0 = '0') THEN
ASSERT (FALSE)
REPORT "All bank must be Precharge before Load Mode Register"
SEVERITY WARNING;
END IF;
-- REF to LMR
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Load Mode Register"
SEVERITY WARNING;
-- LMR to LMR
ASSERT (MRD_chk >= tMRD)
REPORT "tMRD violation during Load Mode Register"
SEVERITY WARNING;
-- Record current tMRD time
MRD_chk := 0;
END IF;
-- Active Block (latch Bank and Row Address)
IF Active_enable = '1' THEN
IF Ba = "00" AND Pc_b0 = '1' THEN
Act_b0 := '1';
Pc_b0 := '0';
B0_row_addr := TO_BITVECTOR (Addr);
RCD_chk0 := NOW;
RAS_chk0 := NOW;
-- Precharge to Active Bank 0
ASSERT (NOW - RP_chk0 >= tRP)
REPORT "tRP violation during Activate Bank 0"
SEVERITY WARNING;
ELSIF Ba = "01" AND Pc_b1 = '1' THEN
Act_b1 := '1';
Pc_b1 := '0';
B1_row_addr := TO_BITVECTOR (Addr);
RCD_chk1 := NOW;
RAS_chk1 := NOW;
-- Precharge to Active Bank 1
ASSERT (NOW - RP_chk1 >= tRP)
REPORT "tRP violation during Activate Bank 1"
SEVERITY WARNING;
ELSIF Ba = "10" AND Pc_b2 = '1' THEN
Act_b2 := '1';
Pc_b2 := '0';
B2_row_addr := TO_BITVECTOR (Addr);
RCD_chk2 := NOW;
RAS_chk2 := NOW;
-- Precharge to Active Bank 2
ASSERT (NOW - RP_chk2 >= tRP)
REPORT "tRP violation during Activate Bank 2"
SEVERITY WARNING;
ELSIF Ba = "11" AND Pc_b3 = '1' THEN
Act_b3 := '1';
Pc_b3 := '0';
B3_row_addr := TO_BITVECTOR (Addr);
RCD_chk3 := NOW;
RAS_chk3 := NOW;
-- Precharge to Active Bank 3
ASSERT (NOW - RP_chk3 >= tRP)
REPORT "tRP violation during Activate Bank 3"
SEVERITY WARNING;
ELSIF Ba = "00" AND Pc_b0 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 0 is not Precharged"
SEVERITY WARNING;
ELSIF Ba = "01" AND Pc_b1 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 1 is not Precharged"
SEVERITY WARNING;
ELSIF Ba = "10" AND Pc_b2 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 2 is not Precharged"
SEVERITY WARNING;
ELSIF Ba = "11" AND Pc_b3 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 3 is not Precharged"
SEVERITY WARNING;
END IF;
-- Active Bank A to Active Bank B
IF ((Previous_bank /= TO_BITVECTOR (Ba)) AND (NOW - RRD_chk < tRRD)) THEN
ASSERT (FALSE)
REPORT "tRRD violation during Activate"
SEVERITY WARNING;
END IF;
-- LMR to ACT
ASSERT (MRD_chk >= tMRD)
REPORT "tMRD violation during Activate"
SEVERITY WARNING;
-- AutoRefresh to Activate
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Activate"
SEVERITY WARNING;
-- Record variable for checking violation
RRD_chk := NOW;
Previous_bank := TO_BITVECTOR (Ba);
END IF;
-- Precharge Block
IF Prech_enable = '1' THEN
IF Addr(10) = '1' THEN
Pc_b0 := '1';
Pc_b1 := '1';
Pc_b2 := '1';
Pc_b3 := '1';
Act_b0 := '0';
Act_b1 := '0';
Act_b2 := '0';
Act_b3 := '0';
RP_chk0 := NOW;
RP_chk1 := NOW;
RP_chk2 := NOW;
RP_chk3 := NOW;
-- Activate to Precharge all banks
ASSERT ((NOW - RAS_chk0 >= tRAS) OR (NOW - RAS_chk1 >= tRAS))
REPORT "tRAS violation during Precharge all banks"
SEVERITY WARNING;
-- tWR violation check for Write
IF ((NOW - WR_chkp(0) < tWRp) OR (NOW - WR_chkp(1) < tWRp) OR
(NOW - WR_chkp(2) < tWRp) OR (NOW - WR_chkp(3) < tWRp)) THEN
ASSERT (FALSE)
REPORT "tWR violation during Precharge ALL banks"
SEVERITY WARNING;
END IF;
ELSIF Addr(10) = '0' THEN
IF Ba = "00" THEN
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
-- Activate to Precharge bank 0
ASSERT (NOW - RAS_chk0 >= tRAS)
REPORT "tRAS violation during Precharge bank 0"
SEVERITY WARNING;
ELSIF Ba = "01" THEN
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
-- Activate to Precharge bank 1
ASSERT (NOW - RAS_chk1 >= tRAS)
REPORT "tRAS violation during Precharge bank 1"
SEVERITY WARNING;
ELSIF Ba = "10" THEN
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
-- Activate to Precharge bank 2
ASSERT (NOW - RAS_chk2 >= tRAS)
REPORT "tRAS violation during Precharge bank 2"
SEVERITY WARNING;
ELSIF Ba = "11" THEN
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
-- Activate to Precharge bank 3
ASSERT (NOW - RAS_chk3 >= tRAS)
REPORT "tRAS violation during Precharge bank 3"
SEVERITY WARNING;
END IF;
-- tWR violation check for Write
ASSERT (NOW - WR_chkp(TO_INTEGER(Ba)) >= tWRp)
REPORT "tWR violation during Precharge"
SEVERITY WARNING;
END IF;
-- Terminate a Write Immediately (if same bank or all banks)
IF (Data_in_enable = '1' AND (Bank = TO_BITVECTOR(Ba) OR Addr(10) = '1')) THEN
Data_in_enable := '0';
END IF;
-- Precharge Command Pipeline for READ
IF CAS_latency_3 = '1' THEN
Command(2) := PRECH;
Bank_precharge(2) := TO_BITVECTOR (Ba);
A10_precharge(2) := TO_BIT(Addr(10));
ELSIF CAS_latency_2 = '1' THEN
Command(1) := PRECH;
Bank_precharge(1) := TO_BITVECTOR (Ba);
A10_precharge(1) := TO_BIT(Addr(10));
END IF;
END IF;
-- Burst Terminate
IF Burst_term = '1' THEN
-- Terminate a Write immediately
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Terminate a Read depend on CAS Latency
IF CAS_latency_3 = '1' THEN
Command(2) := BST;
ELSIF CAS_latency_2 = '1' THEN
Command(1) := BST;
END IF;
END IF;
-- Read, Write, Column Latch
IF Read_enable = '1' OR Write_enable = '1' THEN
-- Check to see if bank is open (ACT) for Read or Write
IF ((Ba="00" AND Pc_b0='1') OR (Ba="01" AND Pc_b1='1') OR (Ba="10" AND Pc_b2='1') OR (Ba="11" AND Pc_b3='1')) THEN
ASSERT (FALSE)
REPORT "Cannot Read or Write - Bank is not Activated"
SEVERITY WARNING;
END IF;
-- Activate to Read or Write
IF Ba = "00" THEN
ASSERT (NOW - RCD_chk0 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 0"
SEVERITY WARNING;
ELSIF Ba = "01" THEN
ASSERT (NOW - RCD_chk1 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 1"
SEVERITY WARNING;
ELSIF Ba = "10" THEN
ASSERT (NOW - RCD_chk2 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 2"
SEVERITY WARNING;
ELSIF Ba = "11" THEN
ASSERT (NOW - RCD_chk3 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 3"
SEVERITY WARNING;
END IF;
-- Read Command
IF Read_enable = '1' THEN
-- CAS Latency Pipeline
IF Cas_latency_3 = '1' THEN
IF Addr(10) = '1' THEN
Command(2) := READ_A;
ELSE
Command(2) := READ;
END IF;
Col_addr (2) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (2) := TO_BITVECTOR (Ba);
ELSIF Cas_latency_2 = '1' THEN
IF Addr(10) = '1' THEN
Command(1) := READ_A;
ELSE
Command(1) := READ;
END IF;
Col_addr (1) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (1) := TO_BITVECTOR (Ba);
END IF;
-- Read intterupt a Write (terminate Write immediately)
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Write Command
ELSIF Write_enable = '1' THEN
IF Addr(10) = '1' THEN
Command(0) := WRITE_A;
ELSE
Command(0) := WRITE;
END IF;
Col_addr (0) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (0) := TO_BITVECTOR (Ba);
-- Write intterupt a Write (terminate Write immediately)
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Write interrupt a Read (terminate Read immediately)
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
-- Interrupt a Write with Auto Precharge
IF Auto_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' AND Write_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' THEN
RW_interrupt_write(TO_INTEGER(RW_Interrupt_Bank)) := '1';
END IF;
-- Interrupt a Read with Auto Precharge
IF Auto_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' AND Read_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' THEN
RW_interrupt_read(TO_INTEGER(RW_Interrupt_Bank)) := '1';
END IF;
-- Read or Write with Auto Precharge
IF Addr(10) = '1' THEN
Auto_precharge (TO_INTEGER(Ba)) := '1';
Count_precharge (TO_INTEGER(Ba)) := 0;
RW_Interrupt_Bank := TO_BitVector(Ba);
IF Read_enable = '1' THEN
Read_precharge (TO_INTEGER(Ba)) := '1';
ELSIF Write_enable = '1' THEN
Write_precharge (TO_INTEGER(Ba)) := '1';
END IF;
END IF;
END IF;
-- Read with AutoPrecharge Calculation
-- The device start internal precharge when:
-- 1. BL/2 cycles after command
-- and 2. Meet tRAS requirement
-- or 3. Interrupt by a Read or Write (with or without Auto Precharge)
IF ((Auto_precharge(0) = '1') AND (Read_precharge(0) = '1')) THEN
IF (((NOW - RAS_chk0 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(0) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(0) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(0) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(0) >= 8))) OR
(RW_interrupt_read(0) = '1')) THEN
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
Auto_precharge(0) := '0';
Read_precharge(0) := '0';
RW_interrupt_read(0) := '0';
END IF;
END IF;
IF ((Auto_precharge(1) = '1') AND (Read_precharge(1) = '1')) THEN
IF (((NOW - RAS_chk1 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(1) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(1) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(1) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(1) >= 8))) OR
(RW_interrupt_read(1) = '1')) THEN
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
Auto_precharge(1) := '0';
Read_precharge(1) := '0';
RW_interrupt_read(1) := '0';
END IF;
END IF;
IF ((Auto_precharge(2) = '1') AND (Read_precharge(2) = '1')) THEN
IF (((NOW - RAS_chk2 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(2) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(2) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(2) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(2) >= 8))) OR
(RW_interrupt_read(2) = '1')) THEN
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
Auto_precharge(2) := '0';
Read_precharge(2) := '0';
RW_interrupt_read(2) := '0';
END IF;
END IF;
IF ((Auto_precharge(3) = '1') AND (Read_precharge(3) = '1')) THEN
IF (((NOW - RAS_chk3 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(3) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(3) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(3) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(3) >= 8))) OR
(RW_interrupt_read(3) = '1')) THEN
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
Auto_precharge(3) := '0';
Read_precharge(3) := '0';
RW_interrupt_read(3) := '0';
END IF;
END IF;
-- Internal Precharge or Bst
IF Command(0) = PRECH THEN -- PRECH terminate a read if same bank or all banks
IF Bank_precharge(0) = Bank OR A10_precharge(0) = '1' THEN
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Command(0) = BST THEN -- BST terminate a read regardless of bank
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
IF Data_out_enable = '0' THEN
Dq <= TRANSPORT (OTHERS => 'Z') AFTER tOH;
END IF;
-- Detect Read or Write Command
IF Command(0) = READ OR Command(0) = READ_A THEN
Bank := Bank_addr (0);
Col := Col_addr (0);
Col_brst := Col_addr (0);
IF Bank_addr (0) = "00" THEN
Row := B0_row_addr;
ELSIF Bank_addr (0) = "01" THEN
Row := B1_row_addr;
ELSIF Bank_addr (0) = "10" THEN
Row := B2_row_addr;
ELSE
Row := B3_row_addr;
END IF;
Burst_counter := 0;
Data_in_enable := '0';
Data_out_enable := '1';
ELSIF Command(0) = WRITE OR Command(0) = WRITE_A THEN
Bank := Bank_addr(0);
Col := Col_addr(0);
Col_brst := Col_addr(0);
IF Bank_addr (0) = "00" THEN
Row := B0_row_addr;
ELSIF Bank_addr (0) = "01" THEN
Row := B1_row_addr;
ELSIF Bank_addr (0) = "10" THEN
Row := B2_row_addr;
ELSE
Row := B3_row_addr;
END IF;
Burst_counter := 0;
Data_in_enable := '1';
Data_out_enable := '0';
END IF;
-- DQ (Driver / Receiver)
Row_index := TO_INTEGER (Row);
Col_index := TO_INTEGER (Col);
IF Data_in_enable = '1' THEN
IF Dqm /= "11" THEN
Init_mem (Bank, Row_index);
IF Bank = "00" THEN
Dq_temp := Bank0 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank0 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
ELSIF Bank = "01" THEN
Dq_temp := Bank1 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank1 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
ELSIF Bank = "10" THEN
Dq_temp := Bank2 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank2 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
ELSIF Bank = "11" THEN
Dq_temp := Bank3 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank3 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
END IF;
WR_chkp(TO_INTEGER(Bank)) := NOW;
WR_counter(TO_INTEGER(Bank)) := 0;
END IF;
Burst_decode;
ELSIF Data_out_enable = '1' THEN
IF Dqm_reg0 /= "11" THEN
Init_mem (Bank, Row_index);
IF Bank = "00" THEN
Dq_temp := Bank0 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
ELSIF Bank = "01" THEN
Dq_temp := Bank1 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
ELSIF Bank = "10" THEN
Dq_temp := Bank2 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
ELSIF Bank = "11" THEN
Dq_temp := Bank3 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
END IF;
ELSE
Dq <= TRANSPORT (OTHERS => 'Z') AFTER tHZ;
END IF;
Burst_decode;
END IF;
ELSIF Sys_clk'event AND Sys_clk = '1' AND Load = '1' AND Dump = '0' THEN --'
Operation <= LOAD_FILE;
load := '0';
-- ASSERT (FALSE) REPORT "Reading memory array from file. This operation may take several minutes. Please wait..."
-- SEVERITY NOTE;
WHILE NOT endfile(file_load) LOOP
readline(file_load, l);
read(l, ch);
if (ch /= 'S') or (ch /= 's') then
hread(l, rectype);
hread(l, reclen);
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(l, recaddr(15 downto 0));
when "0010" =>
hread(l, recaddr(23 downto 0));
when "0011" =>
hread(l, recaddr);
recaddr(31 downto 24) := (others => '0');
when others => next;
end case;
hread(l, recdata);
if index < 32 then
Bank_Load := recaddr(25 downto 24);
Rows_Load := recaddr(23 downto 11);
Cols_Load := recaddr(10 downto 2);
Init_Mem (Bank_Load, To_Integer(Rows_Load));
IF Bank_Load = "00" THEN
for i in 0 to 3 loop
Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
ELSIF Bank_Load = "01" THEN
for i in 0 to 3 loop
Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
ELSIF Bank_Load = "10" THEN
for i in 0 to 3 loop
Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
ELSIF Bank_Load = "11" THEN
for i in 0 to 3 loop
Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
END IF;
elsif(index < 1024) then
Bank_Load := recaddr(26 downto 25);
Rows_Load := recaddr(24 downto 12);
Cols_Load := recaddr(11 downto 3);
Init_Mem (Bank_Load, To_Integer(Rows_Load));
IF Bank_Load = "00" THEN
for i in 0 to 1 loop
Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
end loop;
ELSIF Bank_Load = "01" THEN
for i in 0 to 1 loop
Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
end loop;
ELSIF Bank_Load = "10" THEN
for i in 0 to 1 loop
Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
end loop;
ELSIF Bank_Load = "11" THEN
for i in 0 to 1 loop
Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
end loop;
END IF;
else
Bank_Load := recaddr(22 downto 21);
Rows_Load := '0' & recaddr(20 downto 9);
Cols_Load := '0' & recaddr(8 downto 1);
Init_Mem (Bank_Load, To_Integer(Rows_Load));
IF Bank_Load = "00" THEN
for i in 0 to 7 loop
Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*16 to i*16+15));
end loop;
ELSIF Bank_Load = "01" THEN
for i in 0 to 7 loop
Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*16 to i*16+15));
end loop;
ELSIF Bank_Load = "10" THEN
for i in 0 to 7 loop
Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*16 to i*16+15));
end loop;
ELSIF Bank_Load = "11" THEN
for i in 0 to 7 loop
Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*16 to i*16+15));
end loop;
END IF;
END IF;
END IF;
END LOOP;
ELSIF Sys_clk'event AND Sys_clk = '1' AND Load = '0' AND Dump = '1' THEN --'
Operation <= DUMP_FILE;
ASSERT (FALSE) REPORT "Writing memory array to file. This operation may take several minutes. Please wait..."
SEVERITY NOTE;
WRITE (l, string'("# Micron Technology, Inc. (FILE DUMP / MEMORY DUMP)")); --'
WRITELINE (file_dump, l);
WRITE (l, string'("# BA ROWS COLS DQ")); --'
WRITELINE (file_dump, l);
WRITE (l, string'("# -- ------------- --------- ----------------")); --'
WRITELINE (file_dump, l);
-- Dumping Bank 0
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank0 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank0 (i) (j) (data_bits) = '0';
WRITE (l, string'("00"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank0 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
-- Dumping Bank 1
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank1 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank1 (i) (j) (data_bits) = '0';
WRITE (l, string'("01"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank1 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
-- Dumping Bank 2
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank2 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank2 (i) (j) (data_bits) = '0';
WRITE (l, string'("10"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank2 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
-- Dumping Bank 3
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank3 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank3 (i) (j) (data_bits) = '0';
WRITE (l, string'("11"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank3 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
END IF;
-- Write with AutoPrecharge Calculation
-- The device start internal precharge when:
-- 1. tWR cycles after command
-- and 2. Meet tRAS requirement
-- or 3. Interrupt by a Read or Write (with or without Auto Precharge)
IF ((Auto_precharge(0) = '1') AND (Write_precharge(0) = '1')) THEN
IF (((NOW - RAS_chk0 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(0) >= 1 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(0) >= 2 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(0) >= 4 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(0) >= 8 AND NOW - Count_time(0) >= tWRa))) OR
(RW_interrupt_write(0) = '1' AND WR_counter(0) >= 1 AND NOW - WR_time(0) >= tWRa)) THEN
Auto_precharge(0) := '0';
Write_precharge(0) := '0';
RW_interrupt_write(0) := '0';
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
ASSERT FALSE REPORT "Start Internal Precharge Bank 0" SEVERITY NOTE;
END IF;
END IF;
IF ((Auto_precharge(1) = '1') AND (Write_precharge(1) = '1')) THEN
IF (((NOW - RAS_chk1 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(1) >= 1 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(1) >= 2 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(1) >= 4 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(1) >= 8 AND NOW - Count_time(1) >= tWRa))) OR
(RW_interrupt_write(1) = '1' AND WR_counter(1) >= 1 AND NOW - WR_time(1) >= tWRa)) THEN
Auto_precharge(1) := '0';
Write_precharge(1) := '0';
RW_interrupt_write(1) := '0';
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
END IF;
END IF;
IF ((Auto_precharge(2) = '1') AND (Write_precharge(2) = '1')) THEN
IF (((NOW - RAS_chk2 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(2) >= 1 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(2) >= 2 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(2) >= 4 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(2) >= 8 AND NOW - Count_time(2) >= tWRa))) OR
(RW_interrupt_write(2) = '1' AND WR_counter(2) >= 1 AND NOW - WR_time(2) >= tWRa)) THEN
Auto_precharge(2) := '0';
Write_precharge(2) := '0';
RW_interrupt_write(2) := '0';
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
END IF;
END IF;
IF ((Auto_precharge(3) = '1') AND (Write_precharge(3) = '1')) THEN
IF (((NOW - RAS_chk3 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(3) >= 1 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(3) >= 2 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(3) >= 4 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(3) >= 8 AND NOW - Count_time(3) >= tWRa))) OR
(RW_interrupt_write(0) = '1' AND WR_counter(0) >= 1 AND NOW - WR_time(3) >= tWRa)) THEN
Auto_precharge(3) := '0';
Write_precharge(3) := '0';
RW_interrupt_write(3) := '0';
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
END IF;
END IF;
-- Checking internal wires (Optional for debug purpose)
Pre_chk (0) <= Pc_b0;
Pre_chk (1) <= Pc_b1;
Pre_chk (2) <= Pc_b2;
Pre_chk (3) <= Pc_b3;
Act_chk (0) <= Act_b0;
Act_chk (1) <= Act_b1;
Act_chk (2) <= Act_b2;
Act_chk (3) <= Act_b3;
Dq_in_chk <= Data_in_enable;
Dq_out_chk <= Data_out_enable;
Bank_chk <= Bank;
Row_chk <= Row;
Col_chk <= Col;
END PROCESS;
-- Clock timing checks
-- Clock_check : PROCESS
-- VARIABLE Clk_low, Clk_high : TIME := 0 ns;
-- BEGIN
-- WAIT ON Clk;
-- IF (Clk = '1' AND NOW >= 10 ns) THEN
-- ASSERT (NOW - Clk_low >= tCL)
-- REPORT "tCL violation"
-- SEVERITY WARNING;
-- ASSERT (NOW - Clk_high >= tCK)
-- REPORT "tCK violation"
-- SEVERITY WARNING;
-- Clk_high := NOW;
-- ELSIF (Clk = '0' AND NOW /= 0 ns) THEN
-- ASSERT (NOW - Clk_high >= tCH)
-- REPORT "tCH violation"
-- SEVERITY WARNING;
-- Clk_low := NOW;
-- END IF;
-- END PROCESS;
-- Setup timing checks
Setup_check : PROCESS
BEGIN
wait;
WAIT ON Clk;
IF Clk = '1' THEN
ASSERT(Cke'LAST_EVENT >= tCKS) --'
REPORT "CKE Setup time violation -- tCKS"
SEVERITY WARNING;
ASSERT(Cs_n'LAST_EVENT >= tCMS) --'
REPORT "CS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Cas_n'LAST_EVENT >= tCMS) --'
REPORT "CAS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Ras_n'LAST_EVENT >= tCMS) --'
REPORT "RAS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(We_n'LAST_EVENT >= tCMS) --'
REPORT "WE# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Dqm'LAST_EVENT >= tCMS) --'
REPORT "Dqm Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Addr'LAST_EVENT >= tAS) --'
REPORT "ADDR Setup time violation -- tAS"
SEVERITY WARNING;
ASSERT(Ba'LAST_EVENT >= tAS) --'
REPORT "BA Setup time violation -- tAS"
SEVERITY WARNING;
ASSERT(Dq'LAST_EVENT >= tDS) --'
REPORT "Dq Setup time violation -- tDS"
SEVERITY WARNING;
END IF;
END PROCESS;
-- Hold timing checks
Hold_check : PROCESS
BEGIN
wait;
WAIT ON Clk'DELAYED (tCKH), Clk'DELAYED (tCMH), Clk'DELAYED (tAH), Clk'DELAYED (tDH);
IF Clk'DELAYED (tCKH) = '1' THEN --'
ASSERT(Cke'LAST_EVENT > tCKH) --'
REPORT "CKE Hold time violation -- tCKH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tCMH) = '1' THEN --'
ASSERT(Cs_n'LAST_EVENT > tCMH) --'
REPORT "CS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Cas_n'LAST_EVENT > tCMH) --'
REPORT "CAS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Ras_n'LAST_EVENT > tCMH) --'
REPORT "RAS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(We_n'LAST_EVENT > tCMH) --'
REPORT "WE# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Dqm'LAST_EVENT > tCMH) --'
REPORT "Dqm Hold time violation -- tCMH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tAH) = '1' THEN --'
ASSERT(Addr'LAST_EVENT > tAH) --'
REPORT "ADDR Hold time violation -- tAH"
SEVERITY WARNING;
ASSERT(Ba'LAST_EVENT > tAH) --'
REPORT "BA Hold time violation -- tAH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tDH) = '1' THEN --'
ASSERT(Dq'LAST_EVENT > tDH) --'
REPORT "Dq Hold time violation -- tDH"
SEVERITY WARNING;
END IF;
END PROCESS;
END behave;
-- pragma translate_on
| gpl-2.0 |
marco-c/leon-nexys2 | grlib-gpl-1.3.4-b4140/lib/openchip/gpio/gpio.vhd | 3 | 1454 | ----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- package: gpio
-- File: gpio.vhd
-- Author: Antti Lukats, OpenChip
-- Description: GPIO types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package gpio is
type gpio_in_type is record
d_in : std_logic_vector(31 downto 0);
end record;
type gpio_out_type is record
d_out : std_logic_vector(31 downto 0);
t_out : std_logic_vector(31 downto 0);
end record;
component apbgpio
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gpioi : in gpio_in_type;
gpioo : out gpio_out_type);
end component;
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-terasic-de0-nano/leon3mp.vhd | 1 | 20867 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2012 Aeroflex Gaisler
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
use gaisler.i2c.all;
use gaisler.spi.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS;
dbguart : integer := CFG_DUART;
pclow : integer := CFG_PCLOW
);
port (
clock_50 : in std_logic;
led : inout std_logic_vector(7 downto 0);
key : in std_logic_vector(1 downto 0);
sw : in std_logic_vector(3 downto 0);
dram_ba : out std_logic_vector(1 downto 0);
dram_dqm : out std_logic_vector(1 downto 0);
dram_ras_n : out std_ulogic;
dram_cas_n : out std_ulogic;
dram_cke : out std_ulogic;
dram_clk : out std_ulogic;
dram_we_n : out std_ulogic;
dram_cs_n : out std_ulogic;
dram_dq : inout std_logic_vector(15 downto 0);
dram_addr : out std_logic_vector(12 downto 0);
epcs_data0 : in std_ulogic;
epcs_dclk : out std_ulogic;
epcs_ncso : out std_ulogic;
epcs_asdo : out std_ulogic;
i2c_sclk : inout std_logic;
i2c_sdat : inout std_logic;
g_sensor_cs_n : out std_ulogic;
g_sensor_int : in std_ulogic;
adc_cs_n : out std_ulogic;
adc_saddr : out std_ulogic;
adc_sclk : out std_ulogic;
adc_sdat : in std_ulogic;
gpio_2 : inout std_logic_vector(12 downto 0);
gpio_2_in : in std_logic_vector(2 downto 0);
gpio_1_in : in std_logic_vector(1 downto 0);
gpio_1 : inout std_logic_vector(33 downto 0);
gpio_0_in : in std_logic_vector(1 downto 0);
gpio_0 : inout std_logic_vector(33 downto 0)
);
end;
architecture rtl of leon3mp is
signal vcc, gnd : std_logic_vector(4 downto 0);
signal clkm, rstn, rstraw, sdclkl, lclk, rst, clklck : std_ulogic;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
signal stati : ahbstat_in_type;
signal gpti : gptimer_in_type;
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal gpio0i, gpio1i, gpio2i : gpio_in_type;
signal gpio0o, gpio1o, gpio2o : gpio_out_type;
signal dsubren : std_ulogic;
signal tck, tms, tdi, tdo : std_logic;
constant BOARD_FREQ : integer := 50000; -- Board frequency in KHz, used in clkgen
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV;
constant IOAEN : integer := 1;
constant OEPOL : integer := padoen_polarity(padtech);
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
clk_pad : clkpad generic map (tech => padtech) port map (clock_50, lclk);
clkgen0 : entity work.clkgen_de0
generic map (clk_mul => CFG_CLKMUL, clk_div => CFG_CLKDIV,
clk_freq => BOARD_FREQ, sdramen => CFG_SDCTRL)
port map (inclk0 => lclk, c0 => clkm, c0_2x => open, e0 => sdclkl,
locked => clklck);
sdclk_pad : outpad generic map (tech => padtech, slew => 1)
port map (dram_clk, sdclkl);
resetn_pad : inpad generic map (tech => padtech) port map (key(0), rst);
rst0 : rstgen -- reset generator (reset is active LOW)
port map (rst, clkm, clklck, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN,
nahbm => CFG_NCPU+CFG_AHB_JTAG,
nahbs => 6)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
----- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
cpu : for i in 0 to CFG_NCPU-1 generate
nosh : if CFG_GRFPUSH = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
errorn_pad : outpad generic map (tech => padtech) port map (led(6), dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0,
kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (sw(0), dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (key(1), dsubren);
dsui.break <= not dsubren;
dsuact_pad : outpad generic map (tech => padtech) port map (led(7), dsuo.active);
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
sdctrl0 : if CFG_SDCTRL = 1 generate -- 16-bit SDRAM controller
sdc : entity work.sdctrl16
generic map (hindex => 3, haddr => 16#400#, hmask => 16#FE0#,
ioaddr => 1, fast => 0, pwron => 0, invclk => 0,
sdbits => 16, pageburst => 2)
port map (rstn, clkm, ahbsi, ahbso(3), sdi, sdo);
sa_pad : outpadv generic map (width => 13, tech => padtech)
port map (dram_addr, sdo.address(14 downto 2));
ba0_pad : outpadv generic map (tech => padtech, width => 2)
port map (dram_ba, sdo.address(16 downto 15));
sd_pad : iopadvv generic map (width => 16, tech => padtech, oepol => OEPOL)
port map (dram_dq(15 downto 0), sdo.data(15 downto 0), sdo.vbdrive(15 downto 0), sdi.data(15 downto 0));
sdcke_pad : outpad generic map (tech => padtech)
port map (dram_cke, sdo.sdcke(0));
sdwen_pad : outpad generic map (tech => padtech)
port map (dram_we_n, sdo.sdwen);
sdcsn_pad : outpad generic map (tech => padtech)
port map (dram_cs_n, sdo.sdcsn(0));
sdras_pad : outpad generic map (tech => padtech)
port map (dram_ras_n, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (dram_cas_n, sdo.casn);
sddqm_pad : outpadv generic map (tech => padtech, width => 2)
port map (dram_dqm, sdo.dqm(1 downto 0));
end generate;
spimctrl0: if CFG_SPIMCTRL /= 0 generate -- SPI Memory Controller
spimc : spimctrl
generic map (hindex => 0, hirq => 10, faddr => 16#000#, fmask => 16#f00#,
ioaddr => 16#002#, iomask => 16#fff#,
spliten => CFG_SPLIT, oepol => OEPOL,sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD, dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT, scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER, pwrupcnt => CFG_SPIMCTRL_PWRUPCNT,
offset => CFG_SPIMCTRL_OFFSET)
port map (rstn, clkm, ahbsi, ahbso(0), spmi, spmo);
end generate;
nospimctrl0 : if CFG_SPIMCTRL = 0 generate spmo <= spimctrl_out_none; end generate;
miso_pad : inpad generic map (tech => padtech)
port map (epcs_data0, spmi.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (epcs_asdo, spmo.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (epcs_dclk, spmo.sck);
slvsel0_pad : outpad generic map (tech => padtech)
port map (epcs_ncso, spmo.csn);
----------------------------------------------------------------------
--- AHB ROM ---------------------------------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 and CFG_SPIMCTRL = 0 generate
brom : entity work.ahbrom
generic map (hindex => 0, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map (rstn, clkm, ahbsi, ahbso(0));
end generate;
noprom : if CFG_AHBROMEN = 0 and CFG_SPIMCTRL = 0 generate
ahbso(0) <= ahbs_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various peripherals ------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
apbo(0) <= apb_none; -- Typically occupied by memory controller
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, flow => 0,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
u1i.rxd <= '1';
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 4, paddr => 4, pmask => 16#FFF#,
pirq => 3, filter => 3, dynfilt => 1)
port map (rstn, clkm, apbi, apbo(4), i2ci, i2co);
end generate;
noi2cm: if CFG_I2C_ENABLE = 0 generate
i2co.scloen <= '1'; i2co.sdaoen <= '1';
i2co.scl <= '0'; i2co.sda <= '0';
end generate;
i2c_scl_pad : iopad generic map (tech => padtech)
port map (i2c_sclk, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech)
port map (i2c_sdat, i2co.sda, i2co.sdaoen, i2ci.sda);
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 5, paddr => 5, pmask => 16#fff#, pirq => 5,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => 0, netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(5), spii, spio, slvsel);
spii.spisel <= '1'; -- Master only
spii.astart <= '0';
miso_pad : inpad generic map (tech => padtech)
port map (adc_sdat, spii.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (adc_saddr, spio.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (adc_sclk, spio.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (adc_cs_n, slvsel(0));
end generate spic;
nospi: if CFG_SPICTRL_ENABLE = 0 generate
miso_pad : inpad generic map (tech => padtech)
port map (adc_sdat, spii.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (adc_saddr, vcc(0));
sck_pad : outpad generic map (tech => padtech)
port map (adc_sclk, gnd(0));
slvsel_pad : outpad generic map (tech => padtech)
port map (adc_cs_n, vcc(0));
end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GRGPIO0 port
grgpio0: grgpio
generic map( pindex => 9, paddr => 9, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map( rstn, clkm, apbi, apbo(9), gpio0i, gpio0o);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio_0(i), gpio0o.dout(i), gpio0o.oen(i), gpio0i.din(i));
end generate;
end generate;
nogpio0: if CFG_GRGPIO_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
gpio1 : if CFG_GRGPIO2_ENABLE /= 0 generate -- GRGPIO1 port
grgpio1: grgpio
generic map( pindex => 10, paddr => 10, imask => CFG_GRGPIO2_IMASK, nbits => CFG_GRGPIO2_WIDTH)
port map( rstn, clkm, apbi, apbo(10), gpio1i, gpio1o);
pio_pads : for i in 0 to CFG_GRGPIO2_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio_1(i), gpio1o.dout(i), gpio1o.oen(i), gpio1i.din(i));
end generate;
end generate;
nogpio1: if CFG_GRGPIO2_ENABLE = 0 generate apbo(10) <= apb_none; end generate;
grgpio2: grgpio -- GRGPIO2 port
generic map( pindex => 11, paddr => 11, imask => 2**30, nbits => 31)
port map( rstn, clkm, apbi, apbo(11), gpio2i, gpio2o);
gpio_2_pads : iopadvv generic map (tech => padtech, width => 13)
port map (gpio_2(12 downto 0), gpio2o.dout(12 downto 0), gpio2o.oen(12 downto 0),
gpio2i.din(12 downto 0));
gpio_2_inpads : inpadv generic map (tech => padtech, width => 3)
port map (gpio_2_in, gpio2i.din(15 downto 13));
gpio_0_pads : iopadvv generic map (tech => padtech, width => 2)
port map (gpio_0(33 downto 32), gpio2o.dout(17 downto 16), gpio2o.oen(17 downto 16),
gpio2i.din(17 downto 16));
gpio_0_inpads : inpadv generic map (tech => padtech, width => 2)
port map (gpio_0_in, gpio2i.din(19 downto 18));
gpio_1_pads : iopadvv generic map (tech => padtech, width => 2)
port map (gpio_1(33 downto 32), gpio2o.dout(21 downto 20), gpio2o.oen(21 downto 20),
gpio2i.din(21 downto 20));
gpio_1_inpads : inpadv generic map (tech => padtech, width => 2)
port map (gpio_1_in, gpio2i.din(23 downto 22));
led_pads : iopadvv generic map (tech => padtech, width => 6)
port map (led(5 downto 0), gpio2o.dout(29 downto 24), gpio2o.oen(29 downto 24),
gpio2i.din(29 downto 24));
g_sensor_int_pad : inpad generic map (tech => padtech)
port map (g_sensor_int, gpio2i.din(30));
-- g_sensor_cs_n_pad : outpad generic map (tech => padtech)
-- port map (g_sensor_cs_n, gpio2o.dout(31));
g_sensor_cs_n <= '1';
-- gpio2i.din(31) <= gpio2o.dout(31);
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 1, nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
nop2 : if CFG_AHBSTAT = 0 generate apbo(15) <= apb_none; end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map (rstn, clkm, ahbsi, ahbso(4));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(4) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 5, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(5));
-- pragma translate_on
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera DE0-EP4CE22 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-altera-ep2s60-sdr/config.vhd | 1 | 5584 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := stratix2;
constant CFG_MEMTECH : integer := stratix2;
constant CFG_PADTECH : integer := stratix2;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := stratix2;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- PROM/SRAM controller
constant CFG_SRCTRL : integer := 0;
constant CFG_SRCTRL_PROMWS : integer := 0;
constant CFG_SRCTRL_RAMWS : integer := 0;
constant CFG_SRCTRL_IOWS : integer := 0;
constant CFG_SRCTRL_RMW : integer := 0;
constant CFG_SRCTRL_8BIT : integer := 0;
constant CFG_SRCTRL_SRBANKS : integer := 1;
constant CFG_SRCTRL_BANKSZ : integer := 0;
constant CFG_SRCTRL_ROMASEL : integer := 0;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 1;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 1 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#FFFF#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/gr1553b/gr1553b_2.in.vhd | 3 | 299 | -- Secondary GR1553B
constant CFG_GR1553B_ENABLE2 : integer := CONFIG_GR1553B_ENABLE2;
constant CFG_GR1553B_RTEN2 : integer := CONFIG_GR1553B_RTEN2;
constant CFG_GR1553B_BCEN2 : integer := CONFIG_GR1553B_BCEN2;
constant CFG_GR1553B_BMEN2 : integer := CONFIG_GR1553B_BMEN2;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-kc705/leon3mp.vhd | 1 | 37655 | -----------------------------------------------------------------------------
-- LEON3 Xilinx KC705 Demonstration design
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
library unisim;
use unisim.all;
-- pragma translate_on
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
testahb : boolean := false;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port (
reset : in std_ulogic;
clk200p : in std_ulogic; -- 200 MHz clock
clk200n : in std_ulogic; -- 200 MHz clock
address : out std_logic_vector(25 downto 0);
data : inout std_logic_vector(15 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
romsn : out std_logic;
adv : out std_logic;
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
dsurx : in std_ulogic;
dsutx : out std_ulogic;
dsuctsn : in std_ulogic;
dsurtsn : out std_ulogic;
button : in std_logic_vector(3 downto 0);
switch : inout std_logic_vector(3 downto 0);
led : out std_logic_vector(6 downto 0);
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
gtrefclk_p : in std_logic;
gtrefclk_n : in std_logic;
phy_gtxclk : out std_logic;
phy_txd : out std_logic_vector(3 downto 0);
phy_txctl_txen : out std_ulogic;
phy_rxd : in std_logic_vector(3 downto 0);
phy_rxctl_rxdv : in std_ulogic;
phy_rxclk : in std_ulogic;
phy_reset : out std_ulogic;
phy_mdio : inout std_logic;
phy_mdc : out std_ulogic;
phy_int : in std_ulogic
);
end;
architecture rtl of leon3mp is
component ahb2mig_series7
generic(
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port(
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
ahbso : out ahb_slv_out_type;
ahbsi : in ahb_slv_in_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
calib_done : out std_logic;
rst_n_syn : in std_logic;
rst_n_async : in std_logic;
clk_amba : in std_logic;
sys_clk_p : in std_logic;
sys_clk_n : in std_logic;
clk_ref_i : in std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic
);
end component ;
component ddr_dummy
port (
ddr_dq : inout std_logic_vector(63 downto 0);
ddr_dqs : inout std_logic_vector(7 downto 0);
ddr_dqs_n : inout std_logic_vector(7 downto 0);
ddr_addr : out std_logic_vector(13 downto 0);
ddr_ba : out std_logic_vector(2 downto 0);
ddr_ras_n : out std_logic;
ddr_cas_n : out std_logic;
ddr_we_n : out std_logic;
ddr_reset_n : out std_logic;
ddr_ck_p : out std_logic_vector(0 downto 0);
ddr_ck_n : out std_logic_vector(0 downto 0);
ddr_cke : out std_logic_vector(0 downto 0);
ddr_cs_n : out std_logic_vector(0 downto 0);
ddr_dm : out std_logic_vector(7 downto 0);
ddr_odt : out std_logic_vector(0 downto 0)
);
end component ;
-- pragma translate_off
component ahbram_sim
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pipe : integer := 0;
maccsz : integer := AHBDW;
fname : string := "ram.dat"
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component ;
-- pragma translate_on
component IBUFDS_GTE2
port (
O : out std_ulogic;
ODIV2 : out std_ulogic;
CEB : in std_ulogic;
I : in std_ulogic;
IB : in std_ulogic
);
end component;
component IDELAYCTRL
port (
RDY : out std_ulogic;
REFCLK : in std_ulogic;
RST : in std_ulogic
);
end component;
component IODELAYE1
generic (
DELAY_SRC : string := "I";
IDELAY_TYPE : string := "DEFAULT";
IDELAY_VALUE : integer := 0
);
port (
CNTVALUEOUT : out std_logic_vector(4 downto 0);
DATAOUT : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
CINVCTRL : in std_ulogic;
CLKIN : in std_ulogic;
CNTVALUEIN : in std_logic_vector(4 downto 0);
DATAIN : in std_ulogic;
IDATAIN : in std_ulogic;
INC : in std_ulogic;
ODATAIN : in std_ulogic;
RST : in std_ulogic;
T : in std_ulogic
);
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
--constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH;
constant maxahbm : integer := 16;
--constant maxahbs : integer := 1+CFG_DSU+CFG_MCTRL_LEON2+CFG_AHBROMEN+CFG_AHBRAMEN+2;
constant maxahbs : integer := 16;
constant maxapbs : integer := CFG_IRQ3_ENABLE+CFG_GPT_ENABLE+CFG_GRGPIO_ENABLE+CFG_AHBSTAT+CFG_AHBSTAT;
signal vcc, gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2, sdo3 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal vahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal vahbmo : ahb_mst_out_type;
signal ui_clk : std_ulogic;
signal clkm : std_ulogic := '0';
signal rstn, rstraw, sdclkl : std_ulogic;
signal clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gmiii : eth_in_type;
signal gmiio : eth_out_type;
signal rgmiii,rgmiii_buf : eth_in_type;
signal rgmiio : eth_out_type;
signal sgmiii : eth_sgmii_in_type;
signal sgmiio : eth_sgmii_out_type;
signal sgmiirst : std_logic;
signal ethernet_phy_int : std_logic;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gtx_clk,gtx_clk_nobuf,gtx_clk90 : std_ulogic;
signal rstgtxn : std_logic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, elock, ulock : std_ulogic;
signal lock, calib_done, clkml, lclk, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
constant BOARD_FREQ : integer := 200000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
signal stati : ahbstat_in_type;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
signal dsurx_int : std_logic;
signal dsutx_int : std_logic;
signal dsuctsn_int : std_logic;
signal dsurtsn_int : std_logic;
signal dsu_sel : std_logic;
signal idelay_reset_cnt : std_logic_vector(3 downto 0);
signal idelayctrl_reset : std_logic;
signal io_ref : std_logic;
signal clkref : std_logic;
signal migrstn : std_logic;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1'; gnd <= '0';
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
clk_gen0 : if (CFG_MIG_SERIES7 = 0) generate
clk_pad_ds : clkpad_ds generic map (tech => padtech, level => sstl, voltage => x15v) port map (clk200p, clk200n, lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
port map (lclk, lclk, clkm, open, open, open, open, cgi, cgo, open, open, open);
end generate;
reset_pad : inpad generic map (tech => padtech, level => cmos, voltage => x15v) port map (reset, rst);
rst0 : rstgen -- reset generator
generic map (acthigh => 1, syncin => 1)
port map (rst, clkm, lock, rstn, rstraw);
lock <= calib_done when CFG_MIG_SERIES7 = 1 else cgo.clklock;
rst1 : rstgen -- reset generator
generic map (acthigh => 1)
port map (rst, clkm, '1', migrstn, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, fpnpen => CFG_FPNPEN,
nahbm => maxahbm, nahbs => maxahbs)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
nosh : if CFG_GRFPUSH = 0 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ft -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm);
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
l3ft : if CFG_LEON3FT_EN /= 0 generate
leon3ft0 : leon3ftsh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_IUFT_EN, CFG_FPUFT_EN, CFG_CACHE_FT_EN, CFG_RF_ERRINJ,
CFG_CACHE_ERRINJ, CFG_DFIXED, CFG_LEON3_NETLIST, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clkm, fpi(i), fpo(i));
end generate;
l3s : if CFG_LEON3FT_EN = 0 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
led1_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v) port map (led(1), dbgo(0).error);
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsui_break_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (button(0), dsui.break);
dsuact_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v) port map (led(0), ndsuact);
ndsuact <= not dsuo.active;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; ahbso(2) <= ahbs_none;
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dui.extclk <= '0';
end generate;
nouah : if CFG_AHB_UART = 0 generate
apbo(7) <= apb_none;
duo.txd <= '0';
duo.rtsn <= '0';
dui.extclk <= '0';
end generate;
sw4_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (switch(3), '0', '1', dsu_sel);
dsutx_int <= duo.txd when dsu_sel = '1' else u1o.txd;
dui.rxd <= dsurx_int when dsu_sel = '1' else '1';
u1i.rxd <= dsurx_int when dsu_sel = '0' else '1';
dsurtsn_int <= duo.rtsn when dsu_sel = '1' else u1o.rtsn;
dui.ctsn <= dsuctsn_int when dsu_sel = '1' else '1';
u1i.ctsn <= dsuctsn_int when dsu_sel = '0' else '1';
dsurx_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsurx, dsurx_int);
dsutx_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsutx, dsutx_int);
dsuctsn_pad : inpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsuctsn, dsuctsn_int);
dsurtsn_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech) port map (dsurtsn, dsurtsn_int);
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+1)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+1),
open, open, open, open, open, open, open, gnd);
end generate;
nojtag : if CFG_AHB_JTAG = 0 generate apbo(CFG_NCPU+1) <= apb_none; end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
memi.brdyn <= '0'; memi.bexcn <= '1';
mctrl_gen : if CFG_MCTRL_LEON2 /= 0 generate
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
paddr => 0, srbanks => 2, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS,
pageburst => CFG_MCTRL_PAGE, rammask => 0, iomask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
addr_pad : outpadv generic map (width => 26, tech => padtech, level => cmos, voltage => x25v)
port map (address(25 downto 0), memo.address(26 downto 1));
roms_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (oen, memo.oen);
adv_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (adv, '0');
wri_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (writen, memo.writen);
data_pad : iopadvv generic map (tech => padtech, width => 16, level => cmos, voltage => x25v)
port map (data(15 downto 0), memo.data(31 downto 16),
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
end generate;
nomctrl : if CFG_MCTRL_LEON2 = 0 generate
roms_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (romsn, vcc); --ahbso(0) <= ahbso_none;
end generate;
----------------------------------------------------------------------
--- DDR3 memory controller ------------------------------------------
----------------------------------------------------------------------
mig_gen : if (CFG_MIG_SERIES7 = 1) generate
gen_mig : if (USE_MIG_INTERFACE_MODEL /= true) generate
ddrc : ahb2mig_series7 generic map(
hindex => 4, haddr => 16#400#, hmask => 16#C00#,
pindex => 4, paddr => 4,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
SIMULATION => SIMULATION, USE_MIG_INTERFACE_MODEL => USE_MIG_INTERFACE_MODEL)
port map(
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
ahbsi => ahbsi,
ahbso => ahbso(4),
apbi => apbi,
apbo => apbo(4),
calib_done => calib_done,
rst_n_syn => migrstn,
rst_n_async => rstraw,
clk_amba => clkm,
sys_clk_p => clk200p,
sys_clk_n => clk200n,
clk_ref_i => clkref,
ui_clk => clkm,
ui_clk_sync_rst => open
);
clkgenmigref0 : clkgen
generic map (clktech, 16, 8, 0,CFG_CLK_NOFB, 0, 0, 0, 100000)
port map (clkm, clkm, clkref, open, open, open, open, cgi, cgo, open, open, open);
end generate gen_mig;
gen_mig_model : if (USE_MIG_INTERFACE_MODEL = true) generate
-- pragma translate_off
mig_ahbram : ahbram_sim
generic map (
hindex => 4,
haddr => 16#400#,
hmask => 16#C00#,
tech => 0,
kbytes => 1000,
pipe => 0,
maccsz => AHBDW,
fname => "ram.srec"
)
port map(
rst => rstn,
clk => clkm,
ahbsi => ahbsi,
ahbso => ahbso(4)
);
ddr3_dq <= (others => 'Z');
ddr3_dqs_p <= (others => 'Z');
ddr3_dqs_n <= (others => 'Z');
ddr3_addr <= (others => '0');
ddr3_ba <= (others => '0');
ddr3_ras_n <= '0';
ddr3_cas_n <= '0';
ddr3_we_n <= '0';
ddr3_reset_n <= '1';
ddr3_ck_p <= (others => '0');
ddr3_ck_n <= (others => '0');
ddr3_cke <= (others => '0');
ddr3_cs_n <= (others => '0');
ddr3_dm <= (others => '0');
ddr3_odt <= (others => '0');
--calib_done : out std_logic;
calib_done <= '1';
--ui_clk : out std_logic;
clkm <= not clkm after 5.0 ns;
--ui_clk_sync_rst : out std_logic
-- n/a
-- pragma translate_on
end generate gen_mig_model;
end generate;
no_mig_gen : if (CFG_MIG_SERIES7 = 0) generate
ahbram0 : ahbram
generic map (hindex => 4, haddr => 16#400#, tech => CFG_MEMTECH, kbytes => 32)
port map ( rstn, clkm, ahbsi, ahbso(4));
ddrdummy0 : ddr_dummy
port map (
ddr_dq => ddr3_dq,
ddr_dqs => ddr3_dqs_p,
ddr_dqs_n => ddr3_dqs_n,
ddr_addr => ddr3_addr,
ddr_ba => ddr3_ba,
ddr_ras_n => ddr3_ras_n,
ddr_cas_n => ddr3_cas_n,
ddr_we_n => ddr3_we_n,
ddr_reset_n => ddr3_reset_n,
ddr_ck_p => ddr3_ck_p,
ddr_ck_n => ddr3_ck_n,
ddr_cke => ddr3_cke,
ddr_cs_n => ddr3_cs_n,
ddr_dm => ddr3_dm,
ddr_odt => ddr3_odt
);
calib_done <= '1';
end generate;
led2_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v)
port map (led(2), calib_done);
led3_pad : outpad generic map (tech => padtech, level => cmos, voltage => x15v)
port map (led(3), lock);
led4_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (led(4), ahbso(4).hready);
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 14, paddr => 16#C00#, pmask => 16#C00#, pirq => 14, memtech => memtech,
mdcscaler => CPU_FREQ/1000, rmii => 0, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 2, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF, phyrstadr => 7,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL,
giga => CFG_GRETH1G, ramdebug => 2)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(14), ethi => ethi, etho => etho);
-----------------------------------------------------------------------------
-- An IDELAYCTRL primitive needs to be instantiated for the Fixed Tap Delay
-- mode of the IDELAY.
-- All IDELAYs in Fixed Tap Delay mode and the IDELAYCTRL primitives have
-- to be LOC'ed in the UCF file.
-----------------------------------------------------------------------------
dlyctrl0 : IDELAYCTRL port map (
RDY => OPEN,
REFCLK => io_ref,
RST => idelayctrl_reset
);
delay_rgmii_rx_ctl0 : IODELAYE1 generic map(
DELAY_SRC => "I",
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 20
)
port map(
IDATAIN => rgmiii_buf.rx_dv,
ODATAIN => '0',
DATAOUT => rgmiii.rx_dv,
DATAIN => '0',
C => '0',
T => '1',
CE => '0',
INC => '0',
CINVCTRL => '0',
CLKIN => '0',
CNTVALUEIN => "00000",
CNTVALUEOUT => OPEN,
RST => '0'
);
rgmii_rxd : for i in 0 to 3 generate
delay_rgmii_rxd0 : IODELAYE1 generic map(
DELAY_SRC => "I",
IDELAY_TYPE => "FIXED",
IDELAY_VALUE => 20
)
port map(
IDATAIN => rgmiii_buf.rxd(i),
ODATAIN => '0',
DATAOUT => rgmiii.rxd(i),
DATAIN => '0',
C => '0',
T => '1',
CE => '0',
INC => '0',
CINVCTRL => '0',
CLKIN => '0',
CNTVALUEIN => "00000",
CNTVALUEOUT => OPEN,
RST => '0'
);
end generate;
-- Generate a synchron delayed reset for Xilinx IO delay
rst1 : rstgen
generic map (acthigh => 1)
port map (rst, io_ref, lock, rstgtxn, OPEN);
process (io_ref,rstgtxn)
begin
if (rstgtxn = '0') then
idelay_reset_cnt <= (others => '0');
idelayctrl_reset <= '1';
elsif rising_edge(io_ref) then
if (idelay_reset_cnt > "1110") then
idelay_reset_cnt <= (others => '1');
idelayctrl_reset <= '0';
else
idelay_reset_cnt <= idelay_reset_cnt + 1;
idelayctrl_reset <= '1';
end if;
end if;
end process;
-- RGMII Interface
rgmii0 : rgmii generic map (pindex => 11, paddr => 16#010#, pmask => 16#ff0#, tech => fabtech,
gmii => CFG_GRETH1G, debugmem => 1, abits => 8, no_clk_mux => 1,
pirq => 11, use90degtxclk => 1)
port map (rstn, ethi, etho, rgmiii, rgmiio, clkm, rstn, apbi, apbo(11));
egtxc_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v, slew => 1)
port map (phy_gtxclk, rgmiio.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, level => cmos, voltage => x25v, arch => 4)
port map (phy_rxclk, rgmiii.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, level => cmos, voltage => x25v, width => 4)
port map (phy_rxd, rgmiii_buf.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_rxctl_rxdv, rgmiii_buf.rx_dv);
etxd_pad : outpadv generic map (tech => padtech, level => cmos, voltage => x25v, slew => 1, width => 4)
port map (phy_txd, rgmiio.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v, slew => 1)
port map (phy_txctl_txen, rgmiio.tx_en);
emdio_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_mdio, rgmiio.mdio_o, rgmiio.mdio_oe, rgmiii.mdio_i);
emdc_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_mdc, rgmiio.mdc);
eint_pad : inpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_int, rgmiii.mdint);
erst_pad : outpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (phy_reset, rgmiio.reset);
-- GTX Clock
rgmiii.gtx_clk <= gtx_clk;
-- 125MHz input clock
ibufds_gtrefclk : IBUFDS_GTE2
port map (
I => gtrefclk_p,
IB => gtrefclk_n,
CEB => '0',
O => gtx_clk_nobuf,
ODIV2 => open
);
cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw;
clkgen_gtrefclk : clkgen
generic map (clktech, 8, 8, 0, 0, 0, 0, 0, 125000)
port map (gtx_clk_nobuf, gtx_clk_nobuf, gtx_clk, rgmiii.tx_clk_90, io_ref, open, open, cgi2, cgo2, open, open, open);
end generate;
noeth0 : if CFG_GRETH = 0 generate
-- TODO:
end generate;
----------------------------------------------------------------------
--- I2C Controller --------------------------------------------------
----------------------------------------------------------------------
--i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst generic map (pindex => 9, paddr => 9, pmask => 16#FFF#, pirq => 9, filter => 9)
port map (rstn, clkm, apbi, apbo(9), i2ci, i2co);
i2c_scl_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (iic_scl, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (iic_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
--end generate i2cm;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16, debug => 2)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 10, paddr => 10, imask => CFG_GRGPIO_IMASK, nbits => 7)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(10),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to 2 generate
pio_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (switch(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
pio_pads2 : for i in 3 to 5 generate
pio_pad : inpad generic map (tech => padtech, level => cmos, voltage => x15v)
port map (button(i-2), gpioi.din(i));
end generate;
end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
serrx_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (led(5), rxd1);
sertx_pad : outpad generic map (level => cmos, voltage => x25v, tech => padtech)
port map (led(6), txd1);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 7, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 5, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map ( rstn, clkm, ahbsi, ahbso(5));
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0_gen : if (testahb = true) generate
test0 : ahbrep generic map (hindex => 3, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
-- pragma translate_on
test1_gen : if (testahb = false) generate
ahbram0 : ahbram generic map (hindex => 3, haddr => 16#200#,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map ( rstn, clkm, ahbsi, ahbso(3));
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Xilinx KC705 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/tech/dware/simprims/DW_Foundation_comp_arith.vhd | 4 | 2072 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.all;
package DW_Foundation_comp_arith is
component DW_mult_pipe
generic (
a_width : positive; -- multiplier word width
b_width : positive; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1; -- '0': non-stallable; '1': stallable
rst_mode : natural range 0 to 2 := 1; -- '0': none; '1': async; '2': sync
op_iso_mode : natural range 0 to 4 := 0); -- '0': apply Power Compiler user setting; '1': noop; '2': and; '3': or; '4' preferred style...'and'
port (
clk : in std_logic; -- register clock
rst_n : in std_logic; -- register reset
en : in std_logic; -- register enable
tc : in std_logic; -- '0' : unsigned, '1' : signed
a : in std_logic_vector(a_width-1 downto 0); -- multiplier
b : in std_logic_vector(b_width-1 downto 0); -- multiplicand
product : out std_logic_vector(a_width+b_width-1 downto 0)); -- product
end component;
component DW02_mult
generic( A_width: NATURAL; -- multiplier wordlength
B_width: NATURAL); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic; -- signed -> '1', unsigned -> '0'
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end component;
component DW02_mult_2_stage
generic( A_width: POSITIVE; -- multiplier wordlength
B_width: POSITIVE); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic; -- signed -> '1', unsigned -> '0'
CLK : in std_logic; -- clock for the stage registers.
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end component;
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-altera-ep2s60-sdr/testbench.vhd | 1 | 9465 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 8; -- rom data width (8/32)
romdepth : integer := 23; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 1 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal clkout, pllref : std_ulogic;
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(23 downto 0);
signal data : std_logic_vector(31 downto 0);
signal ramsn : std_ulogic;
signal ramoen : std_ulogic;
signal rwen : std_ulogic;
signal mben : std_logic_vector(3 downto 0);
--signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_ulogic;
signal iosn : std_ulogic;
signal oen : std_ulogic;
--signal read : std_ulogic;
signal writen : std_ulogic;
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal sdcke : std_ulogic; -- clk en
signal sdcsn : std_ulogic; -- chip sel
signal sdwen : std_ulogic; -- write en
signal sdrasn : std_ulogic; -- row addr stb
signal sdcasn : std_ulogic; -- col addr stb
signal sddqm : std_logic_vector (3 downto 0); -- data i/o mask
signal sdclk : std_ulogic;
signal sdba : std_logic_vector(1 downto 0);
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
--signal txd2, rxd2 : std_ulogic;
-- for smc lan chip
signal eth_aen : std_ulogic; -- for smsc eth
signal eth_readn : std_ulogic; -- for smsc eth
signal eth_writen : std_ulogic; -- for smsc eth
signal eth_nbe : std_logic_vector(3 downto 0); -- for smsc eth
signal eth_datacsn : std_ulogic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(31 downto 0);
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsubren <= '1'; rxd1 <= '1';
d3 : entity work.leon3mp generic map (fabtech, memtech, padtech, clktech,
ncpu, disas, dbguart, pclow )
port map (rst, clk, error, address, data, ramsn, ramoen, rwen, mben, iosn,
romsn, oen, writen, open, open, sa(11 downto 0), sd, sdclk, sdcke,
sdcsn, sdwen, sdrasn, sdcasn, sddqm, sdba, dsutx, dsurx, dsubren,
dsuact, rxd1, txd1, eth_aen, eth_readn,
eth_writen, eth_nbe);
sd1 : if (CFG_MCTRL_SDEN = 1) and (CFG_MCTRL_SEPBUS = 1) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sdba, Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sdba, Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
-- 8 bit prom
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24),
romsn, rwen, oen);
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn,
rwen, ramoen);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
sd <= buskeep(sd), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/pci/grpci1/pci_mtf.vhd | 1 | 99259 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: pci_mtf
-- File: pci_mtf.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Alf Vaerneus - Gaisler Research
-- Description: PCI master and target interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.pci.all;
use gaisler.pcilib.all;
entity pci_mtf is
generic (
memtech : integer := DEFMEMTECH;
hmstndx : integer := 0;
dmamst : integer := NAHBMST;
readpref : integer := 0;
abits : integer := 21;
dmaabits : integer := 26;
fifodepth : integer := 3; -- FIFO depth
device_id : integer := 0; -- PCI device ID
vendor_id : integer := 0; -- PCI vendor ID
master : integer := 1; -- Enable PCI Master
hslvndx : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
haddr : integer := 16#F00#;
hmask : integer := 16#F00#;
ioaddr : integer := 16#000#;
irq : integer := 0;
irqmask : integer := 0;
nsync : integer range 1 to 2 := 2; -- 1 or 2 sync regs between clocks
oepol : integer := 0;
endian : integer := 0; -- 0 little, 1 big
class_code: integer := 16#0B4000#;
rev : integer := 0;
scanen : integer := 0;
syncrst : integer := 0;
hostrst : integer := 0);
port(
rst : in std_logic;
clk : in std_logic;
pciclk : in std_logic;
pcii : in pci_in_type;
pcio : out pci_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
attribute sync_set_reset of rst : signal is "true";
end;
architecture rtl of pci_mtf is
function byte_twist(di : in std_logic_vector(31 downto 0); enable : in std_logic) return std_logic_vector is
variable do : std_logic_vector(31 downto 0);
begin
if enable = '1' then
for i in 0 to 3 loop
do(31-i*8 downto 24-i*8) := di(31-(3-i)*8 downto 24-(3-i)*8);
end loop;
else
do := di;
end if;
return do;
end function;
function nr_of_1(di : in integer) return integer is
variable vec : unsigned(31 downto 0);
variable ones : integer;
begin
ones := 0;
vec := to_unsigned(di,32);
for i in 0 to 31 loop
if vec(i) = '1' then
ones := ones + 1;
end if;
end loop;
return ones;
end function;
constant REVISION : amba_version_type := rev;
constant CSYNC : integer := nsync-1;
constant HADDR_WIDTH : integer := 28;
constant MADDR_WIDTH : integer := abits;
constant DMAMADDR_WIDTH : integer := dmaabits;
constant FIFO_DEPTH : integer := fifodepth;
constant FIFO_FULL : std_logic_vector(FIFO_DEPTH - 2 downto 0) := (others => '1');
constant FIFO_DATA_BITS : integer := 32; -- One valid bit
constant NO_CPU_REGS : integer := 6; -- Number of CPU sync registers (pci->ahb)
constant NO_PCI_REGS : integer := 6; -- Number of PCI sync registers (ahb->pci)
constant HMASK_WIDTH : integer := nr_of_1(hmask);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_PCIFBRG, 0, REVISION, irq),
1 => apb_iobar(paddr, pmask));
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_PCIFBRG, 0, REVISION, 0),
4 => ahb_membar(haddr, '0', '0', hmask),
5 => ahb_iobar (ioaddr, 16#E00#),
others => zero32);
type pci_input_type is record
ad : std_logic_vector(31 downto 0);
cbe : std_logic_vector(3 downto 0);
frame : std_logic;
devsel : std_logic;
idsel : std_logic;
trdy : std_logic;
irdy : std_logic;
par : std_logic;
stop : std_logic;
gnt : std_logic;
host : std_logic;
end record;
type pci_fifo_in_type is record
ren : std_logic;
raddr : std_logic_vector(FIFO_DEPTH - 1 downto 0);
wen : std_logic;
waddr : std_logic_vector(FIFO_DEPTH - 1 downto 0);
wdata : std_logic_vector(FIFO_DATA_BITS - 1 downto 0);
end record;
type pci_fifo_out_type is record
rdata : std_logic_vector(FIFO_DATA_BITS - 1 downto 0);
end record;
type fifo_type is record
side : std_logic; -- Owner access side. Receiver accesses the other side
raddr : std_logic_vector(FIFO_DEPTH - 2 downto 0);
waddr : std_logic_vector(FIFO_DEPTH - 2 downto 0);
end record;
type pci_target_state_type is (idle, b_busy, s_data, backoff, turn_ar);
type pci_master_state_type is (idle, addr, m_data, turn_ar, s_tar, dr_bus);
type pci_master_fifo_state_type is (idle, addr, incr, last1, sync, t_retry, ttermwd, ttermnd, abort, done, wdone);
type pci_target_type is record
state : pci_target_state_type;
cnt : std_logic_vector(2 downto 0);
csel : std_logic; -- Configuration chip select
msel : std_logic; -- Memory hit
barsel : std_logic; -- Memory hit
psel : std_logic; -- Page hit
addr : std_logic_vector(31 downto 0);
laddr : std_logic_vector(31 downto 0);
lsize : std_logic_vector(1 downto 0);
lcbe : std_logic_vector(3 downto 0);
lwrite : std_logic;
lburst : std_logic;
lmult : std_logic;
mult : std_logic;
read : std_logic; -- PCI target read
burst : std_logic;
pending : std_logic;
wdel : std_logic;
last : std_logic;
fifo : fifo_type;
trdy_del : std_logic; -- (delay trdy to send last word in fifo) bug fix ***
thold : std_logic; -- hold target while last word is transfered
thold2 : std_logic; -- hold target while last word is transfered
ready_del: std_logic; -- delayed ready
detectperr : std_logic_vector(1 downto 0);
end record;
type pci_master_type is record
state : pci_master_state_type;
fstate : pci_master_fifo_state_type;
cnt : std_logic_vector(2 downto 0);
ltim : std_logic_vector(7 downto 0); -- Latency timer
request : std_logic;
hwrite : std_logic;
stop_req : std_logic;
last : std_logic;
valid : std_logic;
split : std_logic;
first : std_logic;
firstw : std_logic;
fifo : fifo_type;
rmdone : std_logic; -- bug fix ***
stopframe: std_logic;
lto : std_logic; -- bug fix latency timer timeout
detectperr : std_logic_vector(1 downto 0);
end record;
type pci_sync_regs is array (0 to NO_PCI_REGS - 1) of std_logic_vector(csync downto 0);
type pci_reg_type is record
pci : pci_sigs_type;
noe_par : std_logic;
noe_ad : std_logic;
noe_ctrl : std_logic;
noe_cbe : std_logic;
noe_frame : std_logic;
noe_irdy : std_logic;
noe_req : std_logic;
noe_perr : std_logic;
noe_serr : std_logic;
m : pci_master_type;
t : pci_target_type;
comm : pci_config_command_type; -- Command register
stat : pci_config_status_type; -- Status register
bar0 : std_logic_vector(31 downto MADDR_WIDTH); -- Base Address register 0
bar1 : std_logic_vector(31 downto DMAMADDR_WIDTH); -- Base Address register 1
bar0_conf : std_logic;
bar1_conf : std_logic;
page : std_logic_vector(31 downto MADDR_WIDTH-1); -- AHB page
bt_enable : std_logic; -- Byte twist enable, page0 bit 0
ltim : std_logic_vector(7 downto 0); -- Latency timer
cline : std_logic_vector(7 downto 0); -- Cache Line Size
intline : std_logic_vector(7 downto 0); -- Interrupt Line
syncs : pci_sync_regs;
trans : std_logic_vector(NO_CPU_REGS - 1 downto 0);
end record;
type cpu_master_state_type is (idle, cbe_prepare, write, read_w, read, stop);
type cpu_slave_state_type is (idle, w_wait, t_data, r_hold, r_wait, w_done, t_done);
type cpu_master_type is record
state : cpu_master_state_type; -- AMBA master state machine
dmaddr : std_logic_vector(31 downto 0);
fifo : fifo_type;
cbe_fifo : fifo_type;
cur_cbe : std_logic_vector(3 downto 0);
cbe_prep_cnt : std_ulogic;
read_half : std_logic;
last_side_wr : std_ulogic;
end record;
type cpu_slave_type is record
state : cpu_slave_state_type; -- AMBA slave state machine
maddr : std_logic_vector(31 downto 0);
mdata : std_logic_vector(31 downto 0);
be : std_logic_vector(3 downto 0);
perror : std_logic;
hresp : std_logic_vector(1 downto 0);
hready : std_logic;
htrans : std_logic_vector(1 downto 0);
hmaster : std_logic_vector(3 downto 0);
pcicomm : std_logic_vector(3 downto 0);
hold : std_logic;
fifos_write : std_logic;
fifo : fifo_type;
last_side : std_logic;
hold_retry : std_logic_vector(1 downto 0); -- Used to detect non-burst accesses in r_hold state -- ***
end record;
type cpu_sync_regs is array (0 to NO_CPU_REGS - 1) of std_logic_vector(csync downto 0);
type cpu_reg_type is record
m : cpu_master_type;
s : cpu_slave_type;
syncs : cpu_sync_regs;
trans : std_logic_vector(NO_PCI_REGS - 1 downto 0);
pciba : std_logic_vector(HMASK_WIDTH-1 downto 0);
cfto : std_logic;
wcomm : std_logic;
rcomm : std_logic;
werr : std_logic;
clscnt : std_logic_vector(8 downto 0);
dmapage : std_logic_vector(31 downto DMAMADDR_WIDTH); -- DMA page
ioba : std_logic_vector(15 downto 0);
bus_nr : std_logic_vector(3 downto 0);
irq : std_logic_vector(9 downto 0);
irq_en : std_logic_vector(9 downto 0);
pirq : std_logic_vector(0 to 1);
end record;
signal clk_int : std_logic;
signal pr : pci_input_type;
signal r, rin : pci_reg_type;
signal r2, r2in : cpu_reg_type;
signal dmai : pci_ahb_dma_in_type;
signal dmao : pci_ahb_dma_out_type;
signal fifo1i, fifo2i, fifo3i, fifo4i, cbe_fifoi : pci_fifo_in_type;
signal fifo1o, fifo2o, fifo3o, fifo4o, cbe_fifoo : pci_fifo_out_type;
signal roe_ad, rioe_ad, ad, adin : std_logic_vector(31 downto 0);
signal pcirst : std_logic;
signal prrst : std_logic;
signal pcirstin : std_logic;
--attribute sync_set_reset : string;
attribute sync_set_reset of prrst : signal is "true";
attribute async_set_reset : string;
attribute async_set_reset of pcirst : signal is "true";
attribute sync_set_reset of pcirst : signal is "true";
attribute syn_preserve : boolean;
attribute syn_preserve of roe_ad : signal is true;
attribute syn_ramstyle : string;
attribute syn_ramstyle of ad : signal is "registers";
attribute syn_preserve of ad : signal is true;
begin
-----------------------------------------------
-- Back-end state machine (AHB clock domain) --
-----------------------------------------------
comb : process (rst, r2, r, dmao, ahbsi, fifo2o, fifo4o, apbi, pr,
cbe_fifoo, dmai, pcii)
variable vdmai : pci_ahb_dma_in_type;
variable v : cpu_reg_type;
variable hready : std_logic;
variable hresp, hsize : std_logic_vector(1 downto 0);
variable p_done, wsdone, wmdone, rtdone, rmdone : std_logic;
variable pstart, habort, hstart_ack : std_logic;
variable hstart, pabort, pstart_ack, pcidc : std_logic;
variable i : integer range 0 to NO_CPU_REGS;
variable fifom_write, fifos_write : std_logic;
variable prdata : std_logic_vector(31 downto 0);
variable wmvalid, wsvalid, rmvalid, rsvalid, burst_read, hold : std_logic;
variable fifors_limit, fifows_limit,fiform_limit, fifowm_limit, fifows_stop : std_logic;
variable comp, request, s_read_side, m_read_side : std_logic;
variable ahb_access : std_logic; -- *** access control fix
variable start, single_access : std_logic;
variable next_cbe : std_logic_vector(3 downto 0);
variable byteaddr : std_logic_vector(1 downto 0);
begin
v := r2;
vdmai.start := '0';
vdmai.irq := '0'; vdmai.busy := '0'; vdmai.burst := '1';
vdmai.wdata := fifo2o.rdata(31 downto 0); vdmai.write := r.t.lwrite;
rmvalid := '1'; wmvalid := '1'; request := '0'; hold := '0';
rsvalid := '1'; wsvalid := '1'; burst_read := '0';
hready := '1'; hresp := HRESP_OKAY; hsize := "10";
fifom_write := '0'; v.s.fifos_write := '0';
comp := '0'; prdata := (others => '0'); v.s.hold := '0';
s_read_side := not r.m.fifo.side; m_read_side := not r.t.fifo.side;
ahb_access := '0'; -- *** access control fix
-- Synch registers
pstart := r2.trans(0);
habort := r2.trans(1);
hstart_ack := r2.trans(2);
-- fifows_limit := r2.trans(3);
wsdone := r2.trans(4);
wmdone := r2.trans(5);
for i in 0 to NO_CPU_REGS - 1 loop
v.syncs(i)(csync) := r.trans(i);
if csync /= 0 then v.syncs(i)(0) := r2.syncs(i)(csync); end if;
end loop;
hstart := r2.syncs(0)(0);
pabort := r2.syncs(1)(0);
pstart_ack := r2.syncs(2)(0);
pcidc := r2.syncs(3)(0);
rtdone := r2.syncs(4)(0);
rmdone := r2.syncs(5)(0);
p_done := pstart_ack or pabort;
-- Interrupts
if irq /= 0 then
if to_x01(pcii.host) = '0' then
v.irq(3 downto 0) := (not pcii.int);
end if;
end if;
v.irq(9 downto 4) := r.stat.dpe & r.stat.sse & r.stat.rma & r.stat.rta & r.stat.sta & r.stat.dped;
apbo.pirq <= (others => '0');
apbo.pirq(irq) <= orv(r2.irq and r2.irq_en);
if r2.m.fifo.raddr = FIFO_FULL then fiform_limit := '1'; else fiform_limit := '0'; end if;
if r2.m.fifo.waddr = FIFO_FULL then fifowm_limit := '1'; else fifowm_limit := '0'; end if;
if r2.s.fifo.raddr = FIFO_FULL then fifors_limit := '1'; else fifors_limit := '0'; end if;
if r2.s.fifo.waddr = FIFO_FULL then fifows_limit := '1'; else fifows_limit := '0'; end if;
if r2.s.fifo.waddr(FIFO_DEPTH - 2 downto 1) = FIFO_FULL(FIFO_DEPTH - 2 downto 1) then fifows_stop := '1'; else fifows_stop := '0'; end if;
-----------------------------------
---- APB Control & Status regs ----
-----------------------------------
if (apbi.psel(pindex) and apbi.penable) = '1' then
case apbi.paddr(4 downto 2) is
when "000" =>
if apbi.pwrite = '1' then
v.pciba := apbi.pwdata(31 downto 31-HMASK_WIDTH+1);
v.bus_nr := apbi.pwdata(26 downto 23);
v.werr := r2.werr and not apbi.pwdata(14);
v.wcomm := apbi.pwdata(10) and r.comm.mwie;
v.rcomm := apbi.pwdata(9);
end if;
prdata(31 downto 31-HMASK_WIDTH+1) := r2.pciba;
prdata(26 downto 23) := r2.bus_nr;
prdata(22 downto 0) := r.ltim & r2.werr & not pr.host & r.comm.msen & r.comm.men & r2.wcomm & r2.rcomm & r2.cfto & r.cline;
when "001" =>
prdata := r.bar0(31 downto MADDR_WIDTH) & addzero(MADDR_WIDTH-1 downto 0);
when "010" =>
prdata := r.page(31 downto MADDR_WIDTH-1) & addzero(MADDR_WIDTH-2 downto 1) & r.bt_enable;
when "011" =>
prdata := r.bar1(31 downto DMAMADDR_WIDTH) & addzero(DMAMADDR_WIDTH-1 downto 0);
when "100" =>
if apbi.pwrite = '1' then
v.dmapage(31 downto DMAMADDR_WIDTH) := apbi.pwdata(31 downto DMAMADDR_WIDTH);
end if;
prdata := r2.dmapage(31 downto DMAMADDR_WIDTH) & addzero(DMAMADDR_WIDTH-1 downto 0);
when "101" =>
if apbi.pwrite = '1' then
v.ioba := apbi.pwdata(31 downto 16);
end if;
prdata := r2.ioba & addzero(15 downto 4) & hstart & hstart_ack & pstart & pstart_ack;
when "110" =>
prdata(1) := r.comm.men;
prdata(2) := r.comm.msen;
prdata(4) := r.comm.mwie;
prdata(6) := r.comm.per;
prdata(8) := r.comm.ser;
prdata(24) := r.stat.dped;
prdata(26) := '1';
prdata(27) := r.stat.sta;
prdata(28) := r.stat.rta;
prdata(29) := r.stat.rma;
prdata(30) := r.stat.sse;
prdata(31) := r.stat.dpe;
when "111" =>
if apbi.pwrite = '1' then
v.irq_en := apbi.pwdata(25 downto 16);
end if;
prdata(31 downto 26) := (others => '0');
prdata(25 downto 16) := r2.irq_en;
prdata(15 downto 10) := (others => '0');
prdata(9 downto 0) := r2.irq;
when others =>
end case;
end if;
---------------------
---- AHB MASTER ----
---------------------
-- Burst control
if (r2.m.state = read or r2.m.state = read_w) then
if r.t.lmult = '1' then
comp := fifowm_limit and r2.m.fifo.side;
elsif r.t.lburst = '1' then
if r2.clscnt(8) = '1' then comp := '1';
else v.clscnt := r2.clscnt - (dmao.active and dmao.ready); end if;
else comp := '1'; end if;
else
v.clscnt := '0' & (r.cline - '1'); -- set burst counter to cache line size
end if;
if (rtdone = '1' and (r2.m.fifo.raddr + '1') = r.t.fifo.waddr) then rmvalid := '0'; end if;
-- step DMA address
if dmao.ready = '1' then
v.m.dmaddr(31 downto 2) := r2.m.dmaddr(31 downto 2) + '1';
end if;
-- Translate current CBE to hsize and address
byteaddr := "00";
if endian = 0 then -- pci is little endian
case r2.m.cur_cbe is
when "0000" => -- 32 bit access
vdmai.size := "10"; byteaddr := "00";
when "1100" => -- 16 bit
vdmai.size := "01"; byteaddr := "00";
when "0011" =>
vdmai.size := "01"; byteaddr := "10";
when "1110" => -- 8 bit
vdmai.size := "00"; byteaddr := "00";
when "1101" =>
vdmai.size := "00"; byteaddr := "01";
when "1011" =>
vdmai.size := "00"; byteaddr := "10";
when "0111" =>
vdmai.size := "00"; byteaddr := "11";
when others => vdmai.size := "10";
end case;
else -- big endian
case r2.m.cur_cbe is
when "0000" => -- 32 bit access
vdmai.size := "10"; byteaddr := "00";
when "0011" => -- 16 bit
vdmai.size := "01"; byteaddr := "00";
when "1100" =>
vdmai.size := "01"; byteaddr := "10";
when "0111" => -- 8 bit
vdmai.size := "00"; byteaddr := "00";
when "1011" =>
vdmai.size := "00"; byteaddr := "01";
when "1101" =>
vdmai.size := "00"; byteaddr := "10";
when "1110" =>
vdmai.size := "00"; byteaddr := "11";
when others => vdmai.size := "10";
end case;
end if;
vdmai.address := r2.m.dmaddr(31 downto 2) & byteaddr;
next_cbe := cbe_fifoo.rdata(3 downto 0);
-- AHB master state machine
case r2.m.state is
when idle =>
v.m.read_half := '0';
v.m.last_side_wr := '0';
v.m.cur_cbe := (others => '0');
v.m.fifo.waddr := (others => '0');
if hstart = '1' then
wmdone := '0';
fifowm_limit := '0';
-- v.m.fifo.waddr := (others => '0');
if r.t.lwrite = '1' then
v.m.dmaddr := r.t.laddr;
v.m.state := write;
v.m.cur_cbe := cbe_fifoo.rdata(3 downto 0);
-- burst access
if rtdone = '0' or conv_integer(r.t.fifo.waddr) /= 1 then
v.m.cbe_fifo.raddr := r2.m.cbe_fifo.raddr + 1;
v.m.state := cbe_prepare;
v.m.cbe_prep_cnt := '1';
end if;
-- vdmai.busy := '1';
-- if rmvalid = '1' then v.m.state := write;
-- else vdmai.start := '0'; v.m.state := stop; end if;
else
--vdmai.start := '1';
v.m.state := read_w;
v.m.dmaddr := r.t.laddr;
end if;
-- Latching dmaddr is now only done when hstart = 1 [nisse]
else --v.m.dmaddr := r.t.laddr;
end if;
when cbe_prepare =>
v.m.cur_cbe := next_cbe;
-- Need to wait for correct cycle to sample next
-- cbe if we have switched FIFO side.
if r2.m.cbe_prep_cnt = '1' then
v.m.state := write;
else
v.m.cbe_prep_cnt := '1';
end if;
when write =>
start := '0';
--if fiform_limit = '1' then
--if fiform_limit = '1' and dmao.start = '1' then -- 1k bug fix (store last word in first
-- v.m.read_half := '1'; -- fifo half if addr = 0x400 ...)
--end if;
--if fiform_limit = '1' and dmao.start = '1' and dmao.ready = '1' then -- 1k bug fix (store last word in first
-- Need to check dmao active and ready to handle retry/split on last word (check dmao start instead of active result in lockup if waitstates on AHB)
if fiform_limit = '1' and dmao.active = '1' and dmao.ready = '1' then -- 1k bug fix (store last word in first
v.m.read_half := '1'; -- fifo half if addr = 0x400 ...)
end if;
-- Don't start again until PCI side is done filling second half of fifo (bug fix kc)
if r2.m.read_half = '1' then
if rtdone = '1' then
start := ((rmvalid and not fiform_limit) or (not dmao.active and not rmvalid));
end if;
else
-- vdmai.start := ((rmvalid and not fiform_limit) or (not dmao.active and not rmvalid));
-- 1k bug fix (store last word in first fifo half if addr = 0x400 ...)
start := ((rmvalid and not v.m.read_half) or (not dmao.active and not rmvalid));
end if;
if (fiform_limit and dmao.active) = '1' then start := '0'; end if; -- [nisse]
-- Burst CBE handling
if rtdone = '0' or conv_integer(r.t.fifo.waddr) /= 1 then
-- Current or access is subword. Must be forced to single access
if r2.m.cur_cbe /= "0000" then
vdmai.burst := '0';
if dmao.active = '1' then
start := '0';
end if;
end if;
-- Next access is subword. Make current access last in burst
if rmvalid = '1' and next_cbe /= "0000" then
if dmao.active = '1' then
start := '0';
end if;
end if;
end if;
vdmai.start := start;
-- End of data phase for access with cur_cbe
if (dmao.active and dmao.ready) = '1' then
v.m.fifo.raddr := r2.m.fifo.raddr + (rmvalid and not fiform_limit and not dmao.mexc);
v.m.cbe_fifo.raddr := r2.m.cbe_fifo.raddr + (rmvalid and not fiform_limit and not dmao.mexc);
v.m.last_side_wr := m_read_side;
-- First half of FIFO
if v.m.read_half = '0' then
v.m.cur_cbe := next_cbe;
-- FIFO side switch
elsif r2.m.read_half = '0' then
v.m.cbe_prep_cnt := '0';
v.m.state := cbe_prepare;
elsif v.m.last_side_wr = '0' then
v.m.cbe_prep_cnt := '0';
v.m.state := cbe_prepare;
-- Second side of FIFO
else
v.m.cur_cbe := next_cbe;
end if;
if (dmao.mexc = '1' or rmvalid = '0') then
habort := dmao.mexc and not r.t.lwrite;
v.werr := r2.werr or (dmao.mexc and r.t.lwrite);
v.m.state := stop;
end if;
end if;
when read_w =>
vdmai.start := not (comp and dmao.active);
if dmao.mexc = '1' then
habort := not r.t.lwrite;
v.werr := '1';
v.m.state := stop;
elsif dmao.ready = '1' then
fifom_write := '1';
wmvalid := not (comp or dmao.mexc);
if comp = '1' then
v.m.state := stop;
v.m.fifo.waddr := r2.m.fifo.waddr + '1';
else
v.m.fifo.waddr := r2.m.fifo.waddr + (not fifowm_limit);
v.m.state := read; end if;
end if;
when read =>
vdmai.start := not (comp and dmao.active);
fifom_write := dmao.ready; wmvalid := not (comp or dmao.mexc);
-- if ((comp and dmao.ready) or dmao.retry) = '1' then
if (comp and dmao.ready) = '1' then
v.m.state := stop; v.m.fifo.waddr := r2.m.fifo.waddr + '1';
elsif (dmao.active and dmao.ready) = '1' then
v.m.fifo.waddr := r2.m.fifo.waddr + (not dmao.mexc and not fifowm_limit);
if dmao.mexc = '1' then habort := not r.t.lwrite; v.werr := r2.werr or r.t.lwrite; v.m.state := stop; end if;
end if;
when stop =>
if hstart = '0' and ((r.t.lwrite and not fiform_limit) = '1' or wmdone = '1') then
v.m.state := idle; hstart_ack := '0';
v.m.fifo.side := '0'; habort := '0';
v.m.fifo.raddr := (others => '0');
v.m.cbe_fifo.raddr := (others => '0');
else
comp := '1';
fiform_limit := r.t.lwrite;
fifowm_limit := not r.t.lwrite;
end if;
end case;
-- FIFO control
if fifowm_limit = '1' then
-- if (((r2.m.fifo.side or hstart_ack or (not hstart)) = '0' and not (dmao.active and not dmao.ready) = '1')
if (((r2.m.fifo.side or hstart_ack or (not hstart)) = '0' and (dmao.ready or comp) = '1')
or ((hstart_ack and not hstart) = '1' and v.m.state = stop)) then
if v.m.state = stop then wmdone := '1';
else v.m.fifo.waddr := (others => '0'); end if;
hstart_ack := '1';
v.m.fifo.side := not r2.m.fifo.side;
end if;
elsif fiform_limit = '1' then
-- if dmao.active = '0' then
if dmao.active = '0' and dmai.start = '0' then -- 1k bug fix ***
m_read_side := '1';
hstart_ack := '1';
-- v.m.fifo.raddr := (others => hstart);
v.m.fifo.raddr := (others => '0'); -- 1k bug fix ***
v.m.cbe_fifo.raddr := conv_std_logic_vector(1, FIFO_DEPTH-1);
end if;
end if;
-----------------------
--- AHB MASTER END ----
-----------------------
-------------------
---- AHB SLAVE ----
-------------------
-- if MASTER = 1 then
-- Access decode
if (ahbsi.hready and ahbsi.hsel(hslvndx)) = '1' then
if (ahbsi.hmbsel(0) or ahbsi.hmbsel(1)) = '1' then
hsize := ahbsi.hsize(1 downto 0); v.s.htrans := ahbsi.htrans;
--if (v.s.htrans(1) and r.comm.msen) = '1' then request := '1'; end if;
if (v.s.htrans(1) and r.comm.msen) = '1' then -- fix access control ***
ahb_access := '1';
--if (r2.s.state /= r_wait and r2.s.state /= r_hold) or r2.s.hmaster = ahbsi.hmaster then
--if (r2.s.state = idle or r2.s.state = t_done) or r2.s.hmaster = ahbsi.hmaster then
if (r2.s.state = idle) or r2.s.hmaster = ahbsi.hmaster then
request := '1';
end if;
end if;
end if;
end if;
-- Access latches
if (request = '1' and r2.s.state = idle) then
if ahbsi.hmbsel(1) = '1' then
if ahbsi.haddr(16) = '1' then -- Configuration cycles
v.s.maddr := (others => '0');
if r2.bus_nr = "0000" then -- Type 0
v.s.maddr(conv_integer(ahbsi.haddr(15 downto 11)) + 10) := '1';
v.s.maddr(10 downto 0) := ahbsi.haddr(10 downto 2) & "00";
else -- Type 1
v.s.maddr(19 downto 0) := r2.bus_nr & ahbsi.haddr(15 downto 2) & "01";
end if;
v.s.pcicomm := "101" & ahbsi.hwrite;
else -- I/O space access
v.s.maddr(31 downto 16) := r2.ioba;
v.s.maddr(15 downto 0) := ahbsi.haddr(15 downto 0);
v.s.pcicomm := "001" & ahbsi.hwrite;
end if;
else -- Memory space access
if conv_integer(ahbsi.hmaster) = dmamst then
v.s.maddr := ahbsi.haddr;
else
v.s.maddr := r2.pciba & ahbsi.haddr(31-HMASK_WIDTH downto 2) & "00";
end if;
if ahbsi.hwrite = '1' then
v.s.pcicomm := r2.wcomm & "111";
else
v.s.pcicomm := ahbsi.hburst(0) & '1' & (r2.rcomm or not ahbsi.hburst(0)) & '0';
end if;
end if;
-- Decode HSIZE and HADDR
if endian = 0 then -- pci is little endian
case hsize is
when "00" => -- Decode byte enable
case ahbsi.haddr(1 downto 0) is
when "00" => v.s.be := "1110";
when "01" => v.s.be := "1101";
when "10" => v.s.be := "1011";
when "11" => v.s.be := "0111";
when others => v.s.be := "1111";
end case;
when "01" =>
case ahbsi.haddr(1 downto 0) is
when "00" => v.s.be := "1100";
when "10" => v.s.be := "0011";
when others => v.s.be := "1111";
end case;
when "10" => v.s.be := "0000";
when others => v.s.be := "1111";
end case;
else -- pci is big endian
case hsize is
when "00" => -- Decode byte enable
case ahbsi.haddr(1 downto 0) is
when "00" => v.s.be := "0111";
when "01" => v.s.be := "1011";
when "10" => v.s.be := "1101";
when "11" => v.s.be := "1110";
when others => v.s.be := "1111";
end case;
when "01" =>
case ahbsi.haddr(1 downto 0) is
when "00" => v.s.be := "0011";
when "10" => v.s.be := "1100";
when others => v.s.be := "1111";
end case;
when "10" => v.s.be := "0000";
when others => v.s.be := "1111";
end case;
end if;
end if;
if ((rmdone and not r2.s.pcicomm(0)) = '1' and (r2.s.fifo.raddr + '1' + pcidc) = r.m.fifo.waddr) then rsvalid := '0'; end if;
-- FIFO address counters
-- if (r2.s.state = t_data or r2.s.state = w_wait) then
if (r2.s.state = t_data or r2.s.state = w_wait or -- bug fix ***
--(r2.s.state = r_hold and fifors_limit = '0' and ((pstart_ack or pstart) = '0') and request = '1')) then -- (r_hold -> t_data) bug fix ***
(r2.s.state = r_hold and fifors_limit = '0' and ((pstart_ack or pstart) = '0') and request = '1' and rmdone = '1')) then -- (r_hold -> t_data) bug fix ***
v.s.fifos_write := r2.s.pcicomm(0) and r2.s.htrans(1);
v.s.fifo.waddr := r2.s.fifo.waddr + r2.s.fifos_write;
v.s.fifo.raddr := r2.s.fifo.raddr + ((ahbsi.htrans(1) and not r2.s.pcicomm(0) and not fifors_limit and rsvalid) or not ahbsi.hready);
end if;
if pstart_ack = '1' then
if pabort = '1' then
if (r2.s.pcicomm = CONF_WRITE or r2.s.pcicomm = CONF_READ) then v.cfto := '1';
else v.s.perror := '1'; end if;
else v.s.perror := '0'; v.cfto := '0'; end if;
end if;
--
-- AHB slave state machine
case r2.s.state is
when idle =>
v.s.hold_retry := "00";
if request = '1' and p_done = '0' then
if ahbsi.hwrite = '1' then
v.s.state := w_wait;
v.s.fifo.side := '0';
else
pstart := '1'; v.s.state := r_wait;
end if;
v.s.hmaster := ahbsi.hmaster;
end if;
when w_wait =>
if ((ahbsi.hready and not ahbsi.htrans(0)) = '1') then
v.s.state := w_done; fifows_limit := not wsvalid;
else
v.s.state := t_data;
end if;
when t_data =>
if ahbsi.htrans(1) = '1' then v.s.hold_retry := "00"; end if;
burst_read := ahbsi.htrans(1) and not fifors_limit;
if (fifows_stop and r2.s.fifos_write) = '1' then
if r2.s.fifo.side = '1' then
v.s.state := w_done;
end if;
elsif ((fifors_limit or not rsvalid) = '1' and v.s.htrans(1) = '1') then
if (r.m.fifo.side = '0') or (rsvalid = '0') then
v.s.state := t_done;
--else v.s.state := r_hold; end if;
else v.s.state := r_hold; v.s.hold_retry := "00"; end if; -- reset hold_retry ***
end if;
if ((ahbsi.hready and not ahbsi.htrans(0)) = '1') then
if r2.s.pcicomm(0) = '1' then
--v.s.state := w_done; wsvalid := '0';
v.s.state := w_done;
if ahbsi.htrans /= "00" then wsvalid := '0'; end if; -- fix dont set wsvalid if amba idle
else -- (if wsvalid = 0 side is changed before last write
v.s.state := t_done; -- to fifo if hrans = 00)
wsvalid := '0'; -- Bug fix, must give RETRY here! /KC
end if;
end if;
when r_hold =>
s_read_side := '1';
if r2.s.hold_retry(1) = '0' then -- only check this once (first access)
if ahbsi.htrans = "11" then
v.s.hold_retry := "11"; -- Seq Burst access
elsif ahbsi.htrans /= "01" then -- if busy, wait to decide
v.s.hold_retry := "10"; -- New nonseq or idle
end if;
end if;
if v.s.hold_retry = "10" then
v.s.state := t_done;
--elsif fifors_limit = '0' and ((pstart_ack or pstart) = '0') and request = '1' and v.s.hold_retry = "11" then
elsif rmdone = '1' and fifors_limit = '0' and ((pstart_ack or pstart) = '0') and request = '1' and v.s.hold_retry = "11" then
v.s.state := t_data;
burst_read := ahbsi.htrans(1) and not fifors_limit; -- bug fix ***
else
v.s.hold := '1';
end if;
--if fifors_limit = '0' and ((pstart_ack or pstart) = '0') and request = '1' then
-- --if rmdone = '0' then -- bug fix ***
-- v.s.state := t_data;
-- burst_read := ahbsi.htrans(1) and not fifors_limit; -- bug fix ***
-- --else
-- -- v.s.state := t_done;
-- --end if;
--elsif (ahbsi.hready = '1' and ahbsi.htrans = "00" and r2.s.hresp = HRESP_OKAY) then -- (idle -> t_done) bug fix ***
-- v.s.state := t_done;
--else v.s.hold := '1'; end if;
when r_wait =>
s_read_side := '0';
if (pstart_ack and request) = '1' then
v.s.state := t_data; hready := '0';
end if;
if r2.s.hmaster /= ahbsi.hmaster and conv_integer(ahbsi.hmaster) = dmamst and pstart_ack = '1' then -- if pcidma cancel read
v.s.state := t_done;
end if;
when w_done =>
v.s.state := t_done; wsvalid := '0';
-- if (r2.s.htrans(1) or not fifows_limit) = '1' then
-- if (r2.s.htrans(1) and fifows_limit) = '1' then
v.s.fifo.waddr := r2.s.fifo.waddr + r2.s.fifos_write;
-- end if;
fifows_limit := '1';
when t_done =>
wsvalid := '0';
fifors_limit := not r2.s.pcicomm(0);
if (pstart or pstart_ack) = '0' then
v.s.state := idle; v.s.perror := '0';
v.s.fifo.waddr := (others => '0'); wsdone := '0'; fifows_limit := '0';
v.s.pcicomm := (0 => '1', others => '0'); -- default write
else fifows_limit := r2.s.pcicomm(0); end if;
end case;
-- Respond encoder
if v.s.state = t_data
or (v.s.state = r_hold and v.s.hold = '0') -- bug fix ***
or (v.s.state = t_done and r2.s.state = t_data) -- (end of trans) bug fix ***
or (v.s.state = w_wait and ahbsi.hwrite = '1') then
if r2.s.perror = '1' then hresp := HRESP_ERROR;
elsif wsvalid = '1' then hresp := HRESP_OKAY;
else hresp := HRESP_RETRY; end if;
v.s.perror := '0';
else hresp := HRESP_RETRY; end if;
-- added to provent read from unvalid fifo address
if r2.s.state = t_data and rsvalid = '0' and r2.s.hold_retry /= "00" then hresp := HRESP_RETRY; end if;
if r.comm.msen = '0' then hresp := HRESP_ERROR; end if; -- Master disabled
--if (v.s.htrans(1) and request) = '0' then hresp := HRESP_OKAY; end if; -- Response OK for BUSY and IDLE
if (v.s.htrans(1) and ahb_access) = '0' then hresp := HRESP_OKAY; end if; -- Response OK for BUSY and IDLE -- *** access control fix
if (hresp /= HRESP_OKAY or hready = '0') then v.s.hready := '0'; else v.s.hready := '1'; end if;
-- Dont change hresp during wait states
if ahbsi.hready = '0' then hresp := r2.s.hresp; end if;
v.s.hresp := hresp;
-- FIFO controller
if fifows_limit = '1' then
if (r2.s.fifos_write or not wsvalid) = '1' and (r2.s.fifo.side = '0' or pstart_ack = '1') then
--if wsvalid = '0' then wsdone := '1';
if wsvalid = '0' or v.s.state = w_done then wsdone := '1'; -- fix set wsdone and pstart at the same time
else v.s.fifo.waddr := (others => '0'); end if;
pstart := not pstart_ack;
v.s.fifo.side := pstart;
end if;
elsif ((r2.s.state = t_done or r2.s.state = r_hold) and fifors_limit = '1') then
if pstart_ack = '1' then pstart := '0'; v.s.fifo.raddr := (others => '0');
else v.s.fifo.raddr := (others => '0'); end if;
end if;
-- Set last fifo side written so that PCI master knows when to stop
if (r2.s.fifos_write = '1') then
v.s.last_side := r2.s.fifo.side;
end if;
-- end if;
-----------------------
---- AHB SLAVE END ----
-----------------------
-- Sync registers
v.trans(0) := pstart;
v.trans(1) := habort;
v.trans(2) := hstart_ack;
v.trans(3) := fifows_limit;
v.trans(4) := wsdone;
v.trans(5) := wmdone;
-- input data for write accesses
if r2.s.pcicomm(0) = '1' then v.s.mdata := ahbreadword(ahbsi.hwdata); end if;
-- output data for read accesses
-- if (ahbsi.htrans(1) and not r2.s.hold and not r2.s.pcicomm(0)) = '1' then v.s.mdata := fifo4o.rdata(31 downto 0); end if;
if (ahbsi.htrans(1) and not r2.s.pcicomm(0)) = '1' then v.s.mdata := fifo4o.rdata(31 downto 0); end if; -- bug fix ***
if rst = '0' then
v.s.state := idle;
v.m.state := idle;
v.s.perror := '0';
v.pciba := (others => '0');
v.trans := (others => '0');
v.m.cbe_fifo.waddr := (others => '0');
v.m.cbe_fifo.raddr := (others => '0');
v.m.fifo.waddr := (others => '0');
v.m.fifo.raddr := (others => '0');
v.s.fifo.waddr := (others => '0');
v.s.fifo.raddr := (others => '0');
v.m.fifo.side := '0';
v.s.fifo.side := '0';
v.wcomm := '0';
v.rcomm := '0';
v.werr := '0';
v.cfto := '0';
v.dmapage := (others => '0');
v.ioba := (others => '0');
v.bus_nr := (others => '0');
v.irq := (others => '0');
v.irq_en := (others => '0');
v.m.cbe_prep_cnt := '0';
end if;
apbo.prdata <= prdata;
ahbso.hready <= r2.s.hready;
ahbso.hresp <= r2.s.hresp;
ahbso.hrdata <= ahbdrivedata(byte_twist(r2.s.mdata, r.bt_enable));
ahbso.hindex <= hslvndx;
fifo1i.wen <= fifom_write;
fifo1i.waddr <= r2.m.fifo.side & r2.m.fifo.waddr;
fifo1i.wdata <= dmao.rdata;
fifo2i.ren <= '1';
fifo2i.raddr <= m_read_side & (r2.m.fifo.raddr + dmao.ready);
fifo3i.wen <= r2.s.fifos_write;
fifo3i.waddr <= r2.s.fifo.side & r2.s.fifo.waddr;
fifo3i.wdata <= byte_twist(r2.s.mdata, r.bt_enable);
fifo4i.ren <= '1';
fifo4i.raddr <= s_read_side & (r2.s.fifo.raddr + burst_read);
cbe_fifoi.ren <= '1';
cbe_fifoi.raddr <= m_read_side & (r2.m.cbe_fifo.raddr + dmao.ready); -- read one cycle before data fifo
r2in <= v; dmai <= vdmai;
end process;
ahbso.hconfig <= hconfig when MASTER = 1 else (others => zero32);
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
---------------------------------
-- PCI core (PCI clock domain) --
---------------------------------
pcicomb : process(pr, pcii, r, r2, fifo1o, fifo3o, roe_ad, prrst, ahbmi,
pcirstin, ad)
variable v : pci_reg_type;
variable chit, mhit0, mhit1, phit, hit, hosthit, ready, cwrite, retry : std_logic;
variable cdata, cwdata : std_logic_vector(31 downto 0);
variable comp : std_logic; -- Last transaction cycle on PCI bus
variable mto, tto, term, ben_err, lto : std_logic;
variable i : integer range 0 to NO_PCI_REGS;
variable tad, mad : std_logic_vector(31 downto 0);
variable pstart, habort, hstart_ack, wsdone, wmdone : std_logic;
variable hstart, pabort, pstart_ack, pcidc, rtdone, rmdone : std_logic;
variable fifort_limit, fifowt_limit, fiform_limit, fifowm_limit, fifowm_stop, t_valid : std_logic;
variable d_ready, tabort, backendnr : std_logic;
variable m_fifo_write, t_fifo_write, grant : std_logic;
variable write_access, memwrite, memread, read_match, m_read_side, t_read_side : std_logic;
variable readt_dly : std_logic; -- 1 turnaround cycle
variable bus_idle, data_transfer, data_transfer_r, data_phase, targ_d_w_data, targ_abort, m_request : std_logic;
variable voe_ad : std_logic_vector(31 downto 0);
variable oe_par : std_logic;
variable oe_ad : std_logic;
variable oe_ctrl : std_logic;
variable oe_cbe : std_logic;
variable oe_frame : std_logic;
variable oe_irdy : std_logic;
variable oe_req : std_logic;
variable oe_perr : std_logic;
variable oe_serr : std_logic;
begin
-- Process defaults
v := r; v.pci.trdy := '1'; v.pci.stop := '1'; v.pci.frame := '1';
v.pci.oe_ad := '1'; v.pci.devsel := '1'; v.pci.oe_frame := '1';
v.pci.irdy := '1'; v.pci.req := '1'; hosthit := '0'; m_request := '0';
v.pci.oe_req := '0'; v.pci.oe_cbe := '1'; v.pci.oe_irdy := '1';
mto := '0'; tto := '0'; v.m.stop_req := '0'; lto := '0';
cdata := (others => '0'); retry := '0'; t_fifo_write := '0';
chit := '0'; phit := '0'; mhit0 := '0'; mhit1 := '0'; tabort := '0';
readt_dly := '0'; m_fifo_write := '0'; voe_ad := roe_ad;
tad := r.pci.ad; mad := r.pci.ad; grant := pcii.gnt; d_ready := '0';
m_read_side := not r2.s.fifo.side; t_read_side := not r2.m.fifo.side;
v.m.rmdone := '0';
write_access := not r.t.read and not pr.irdy and not pr.trdy;
memwrite := r.t.msel and r.t.lwrite and not r.t.read;
memread := r.t.msel and not r.t.lwrite and r.t.read;
-- Synch registers
hstart := r.trans(0);
pabort := r.trans(1);
pstart_ack := r.trans(2);
pcidc := r.trans(3);
rtdone := r.trans(4);
rmdone := r.trans(5);
for i in 0 to NO_PCI_REGS - 1 loop
v.syncs(i)(csync) := r2.trans(i);
if csync /= 0 then v.syncs(i)(0) := r.syncs(i)(csync); end if;
end loop;
pstart := r.syncs(0)(0);
habort := r.syncs(1)(0);
hstart_ack := r.syncs(2)(0);
backendnr := r.syncs(3)(0);
wsdone := r.syncs(4)(0);
wmdone := r.syncs(5)(0);
-- FIFO limit detector
if r.t.fifo.raddr = FIFO_FULL then fifort_limit := '1'; else fifort_limit := '0'; end if;
if r.t.fifo.waddr = FIFO_FULL then fifowt_limit := '1'; else fifowt_limit := '0'; end if;
if r.m.fifo.raddr = FIFO_FULL then fiform_limit := '1'; else fiform_limit := '0'; end if;
if r.m.fifo.waddr = FIFO_FULL then fifowm_limit := '1'; else fifowm_limit := '0'; end if;
if r.m.fifo.waddr(FIFO_DEPTH - 2 downto 1) = FIFO_FULL(FIFO_DEPTH - 2 downto 1) then fifowm_stop := '1'; else fifowm_stop := '0'; end if;
-- useful control variables
--if (r.t.laddr = r.page & r.t.addr(MADDR_WIDTH-2 downto 0) or r.t.laddr = r2.dmapage & r.t.addr(DMAMADDR_WIDTH-1 downto 0))
if (r.t.laddr(31 downto 2) = r.page & r.t.addr(MADDR_WIDTH-2 downto 2) -- bug fix match if byte access
or r.t.laddr(31 downto 2) = r2.dmapage & r.t.addr(DMAMADDR_WIDTH-1 downto 2))
and (r.t.lcbe = pr.cbe) -- bug fix match byte access
and (r.t.lburst = r.t.burst) then read_match := r.t.pending; else read_match := r.t.csel or r.t.psel; end if;
-- if (pr.cbe = "0000" and r.t.lsize = "10") or (pr.cbe = "1100" and r.t.lsize = "01") or (pr.cbe = "1110" and r.t.lsize = "00")
-- pragma translate_off
-- or (pr.cbe = "XXXX") -- For simulation purposes
-- pragma translate_on
-- then ben_err := '0'; else ben_err := '1'; end if;
ben_err := '0';
--if r.stat.dpe = '0' then v.stat.dpe := not (r.pci.perr and r.pci.serr); end if;
if r.stat.dpe = '0' and (r.m.detectperr(1) = '1' or r.t.detectperr(1) = '1' or r.pci.serr = '0') then v.stat.dpe := not (r.pci.perr and r.pci.serr); end if;
-------------------------
----- PCI TARGET --------
-------------------------
-- Data valid?
if ((wmdone and not r.t.lwrite) = '1' and (r.t.fifo.raddr + '1') = r2.m.fifo.waddr) then t_valid := '0';
else t_valid := not fifowt_limit or not r.t.fifo.side; end if;
-- Step addresses
if (r.t.state = s_data or r.t.state = turn_ar or r.t.state = backoff) then
--if (pcii.irdy or r.pci.trdy) = '0' then
if (pcii.irdy or r.t.trdy_del) = '0' then
v.t.addr := r.t.addr + ((r.t.csel and r.t.read) & "00");
readt_dly := '1';
if r.t.msel = '1' then
-- **** ???? **** Is r2.m.fifo.side really synced here ??? *** may need to be changed *** [nisse]
v.t.wdel := (fifort_limit and r2.m.fifo.side) or r.t.lwrite;
v.t.fifo.raddr := r.t.fifo.raddr + (r.t.read and not fifort_limit and t_valid);
end if;
end if;
if write_access = '1' then
v.t.fifo.waddr := r.t.fifo.waddr + (r.t.msel and not r.t.read and not ben_err);
t_fifo_write := r.t.msel;
v.t.addr := r.t.addr + ((r.t.csel and not r.t.read) & "00");
end if;
tabort := habort;
else v.t.wdel := '0'; end if;
-- signal to hold target while last word is transfered
if (fifort_limit and not (pcii.irdy or r.t.trdy_del) and not r.t.thold) = '1' then -- should be r.pci.trdy
v.t.thold := '1';
elsif (r.t.thold and not (pcii.irdy or r.t.trdy_del)) = '1' then -- should be r.pci.trdy
v.t.thold := '0';
end if;
-- Config space read access
case r.t.addr(7 downto 2) is
when "000000" => -- 0x00, device & vendor id
cdata := conv_std_logic_vector(DEVICE_ID, 16) &
conv_std_logic_vector(VENDOR_ID, 16);
when "000001" => -- 0x04, status & command
cdata(1) := r.comm.men;
cdata(2) := r.comm.msen;
cdata(4) := r.comm.mwie;
cdata(6) := r.comm.per;
cdata(8) := r.comm.ser;
cdata(24) := r.stat.dped;
cdata(26) := '1';
cdata(27) := r.stat.sta;
cdata(28) := r.stat.rta;
cdata(29) := r.stat.rma;
cdata(30) := r.stat.sse;
cdata(31) := r.stat.dpe;
when "000010" => -- 0x08, class code & revision
cdata(31 downto 0) := conv_std_logic_vector(CLASS_CODE,24) & conv_std_logic_vector(REV,8) ;
when "000011" => -- 0x0C, latency & cacheline size
cdata(7 downto 0) := r.cline;
cdata(15 downto 8) := r.ltim;
when "000100" => -- 0x10, BAR0
cdata(31 downto MADDR_WIDTH) := r.bar0;
when "000101" => -- 0x14, BAR1
cdata(31 downto DMAMADDR_WIDTH) := r.bar1;
when "001111" => -- 0x3C, Interrupts & Latency timer settings
cdata(7 downto 0) := r.intline; -- Interrupt line
cdata(8) := '1'; -- Use interrupt pin INTA#
if fifodepth < 11 then cdata(fifodepth+13) := '1'; end if; --Define wanted burst period
when others =>
end case;
-- Config space write access
cwdata := pr.ad;
if pr.cbe(3) = '1' then cwdata(31 downto 24) := cdata(31 downto 24); end if;
if pr.cbe(2) = '1' then cwdata(23 downto 16) := cdata(23 downto 16); end if;
if pr.cbe(1) = '1' then cwdata(15 downto 8) := cdata(15 downto 8); end if;
if pr.cbe(0) = '1' then cwdata( 7 downto 0) := cdata( 7 downto 0); end if;
if (r.t.csel and write_access) = '1' then
case r.t.addr(7 downto 2) is
when "000001" => -- 0x04, status & command
-- Command register
v.comm.men := cwdata(1);
if MASTER = 1 then v.comm.msen := cwdata(2); end if;
v.comm.mwie := cwdata(4);
v.comm.per := cwdata(6);
v.comm.ser := cwdata(8);
-- Status register, sticky bits
v.stat.dped := r.stat.dped and not cwdata(24);
v.stat.sta := r.stat.sta and not cwdata(27);
v.stat.rta := r.stat.rta and not cwdata(28);
v.stat.rma := r.stat.rma and not cwdata(29);
v.stat.sse := r.stat.sse and not cwdata(30);
v.stat.dpe := r.stat.dpe and not cwdata(31);
when "000011" => -- 0x0c, latency & cacheline size
if FIFO_DEPTH <= 7 then v.cline(FIFO_DEPTH - 1 downto 0) := cwdata(FIFO_DEPTH - 1 downto 0);
else v.cline := cwdata(7 downto 0); end if;
v.ltim := cwdata(15 downto 8);
when "000100" => -- 0x10, BAR0
v.bar0 := cwdata(31 downto MADDR_WIDTH);
if v.bar0 = zero(31 downto MADDR_WIDTH) then v.bar0_conf := '0'; else v.bar0_conf := '1'; end if;
when "000101" => -- 0x14, BAR1
v.bar1 := cwdata(31 downto DMAMADDR_WIDTH);
if v.bar1 = zero(31 downto DMAMADDR_WIDTH) then v.bar1_conf := '0'; else v.bar1_conf := '1'; end if;
when "001111" => -- 0x3C, Interrupts & Latency timer settings
v.intline := cwdata(7 downto 0); -- Interrupt line
when others =>
end case;
end if;
-- Page bar write
if (r.t.psel and write_access) = '1' then
v.page := pr.ad(31 downto MADDR_WIDTH - 1);
v.bt_enable := pr.ad(0);
end if;
-- Command and address decode
case pr.cbe is
when CONF_READ | CONF_WRITE =>
if pr.ad(1 downto 0) = "00" then chit := '1'; end if;
if pr.host = '0' then --Active low
if pr.ad(31 downto 11) = "000000000000000000000" then hosthit := '1'; end if;
end if;
when MEM_READ | MEM_WRITE =>
if pr.ad(31 downto MADDR_WIDTH) = r.bar0 then
phit := r.bar0_conf and pr.ad(MADDR_WIDTH - 1);
mhit0 := r.bar0_conf and not pr.ad(MADDR_WIDTH - 1);
elsif pr.ad(31 downto DMAMADDR_WIDTH) = r.bar1 then
mhit1 := r.bar1_conf;
end if;
when MEM_R_MULT | MEM_R_LINE | MEM_W_INV =>
if pr.ad(31 downto MADDR_WIDTH - 1) = r.bar0 & '0' then mhit0 := r.bar0_conf;
elsif pr.ad(31 downto DMAMADDR_WIDTH) = r.bar1 then mhit1 := r.bar1_conf; end if;
when others => phit := '0'; mhit0 := '0'; chit := '0'; mhit1 := '0';
end case;
-- SERR, address phase parity error. Treat as non hit.
v.pci.serr := '1';
v.pci.oe_serr := '1';
--if pr.frame = '0' then
if pr.frame = '0' and (r.t.state = idle or r.t.state = turn_ar) then -- Only signal address parity error on SERR#
if ( (pcii.par xor xorv(pr.ad & pr.cbe)) = '1') then
v.pci.serr := '0';
chit := '0'; phit := '0'; mhit0 := '0'; mhit1 := '0';
--if r.comm.ser = '1' then
if r.comm.ser = '1' and r.comm.per = '1' then -- Address parity error only if "Parity Error Response" and "SERR# enable" is enabled.
v.pci.oe_serr := '0';
v.stat.sse := '1';
end if;
end if;
end if;
-- Hit detect
hit := r.t.csel or r.t.msel or r.t.psel;
if (hstart and r.pci.devsel) = '1' then
if (r.t.pending or r.t.lwrite) = '0' then
hstart := not hstart_ack;
v.t.fifo.raddr := (others => '0');
end if;
end if;
-- Ready to transfer data
if ((r.t.csel and not readt_dly) or r.t.psel) = '1'
or ((((memwrite and not r.pci.devsel) = '1')
-- Changed to transfer last word (instead of delaying trdy) [nisse]
--or (memread = '1' and not (hstart_ack and v.t.wdel) = '1')) and ben_err = '0')
or (memread = '1' and not (hstart_ack and r.t.wdel) = '1')) and ben_err = '0')
then ready := '1'; else ready := '0'; t_read_side := r.t.read and not hstart; end if;
v.t.ready_del := ready;
-- Target timeout counter
--if (hit and pr.trdy and not (pr.frame and pr.irdy)) = '1' then
--if (hit and pr.trdy and not (pr.frame and pr.irdy) and v.t.wdel) = '1' then
if (hit and pr.trdy and not (pr.frame and pr.irdy) and not ready) = '1' then
if r.t.cnt /= "000" then v.t.cnt := r.t.cnt - 1;
else tto := '1'; end if;
else v.t.cnt := (0 => '0', others => '1'); end if;
-- -- Ready to transfer data
-- if ((r.t.csel and not readt_dly) or r.t.psel) = '1'
-- or ((((memwrite and not r.pci.devsel) = '1')
-- or (memread = '1' and not (hstart_ack and v.t.wdel) = '1')) and ben_err = '0')
-- then ready := '1'; else ready := '0'; t_read_side := r.t.read and not hstart; end if;
-- Terminate current transaction
if (((r.t.fifo.waddr >= (FIFO_FULL - "10") and r.t.fifo.side = '1')
or (t_valid = '0') or r.pci.stop = '0') and pcii.frame = '0')
or ((r.t.read xor r.t.lwrite) = '0' and r.pci.devsel = '0')
or (tto = '1') or (ben_err = '1')
then
term := '1';
else term := '0'; end if;
-- Retry transfer
if r.t.state = b_busy then
if not ((r.t.read and not r.t.lwrite and hstart_ack and read_match) = '1'
or (r.t.read or hstart or hstart_ack) = '0'
or ((r.t.csel or r.t.psel) and not hstart and not hstart_ack) = '1')
then
retry := '1';
end if;
end if;
-- Target state machine
case r.t.state is
when idle =>
v.t.detectperr(0) := '0';
v.t.thold := '0';
v.t.thold2 := '0';
if pr.frame = '0' then v.t.state := b_busy; end if; -- !HIT ?
v.t.addr := pr.ad;
if readpref = 1 then v.t.burst := '1';
else v.t.burst := pr.cbe(3); end if;
v.t.read := not pr.cbe(0); v.t.mult := not pr.cbe(1);
v.t.csel := (pr.idsel or hosthit) and chit; v.t.psel := phit;
v.t.msel := r.comm.men and (mhit0 or mhit1); v.t.barsel := mhit1;
when turn_ar =>
v.t.detectperr(0) := '0';
if pr.frame = '1' then
v.t.state := idle;
v.t.fifo.raddr := (others => '0'); -- fix reset fifo read address
else v.t.state := b_busy; end if; -- !HIT ?
v.t.addr := pr.ad; v.t.wdel := '1';
if readpref = 1 then v.t.burst := '1';
else v.t.burst := pr.cbe(3); end if;
v.t.read := not pr.cbe(0); v.t.mult := not pr.cbe(1);
v.t.csel := (pr.idsel or hosthit) and chit; v.t.psel := phit;
v.t.msel := r.comm.men and (mhit0 or mhit1); v.t.barsel := mhit1;
when b_busy =>
v.t.thold := '0';
v.t.thold2 := '0';
if (pr.frame and pr.irdy) = '1' then
v.t.state := idle;
elsif hit = '1' then
v.t.detectperr(0) := '1';
v.t.state := s_data;
v.t.fifo.raddr := r.t.fifo.raddr + (r.t.read and r.t.msel);
readt_dly := '1';
if r.t.pending = '0' then
v.t.pending := retry and not hstart_ack;
end if;
end if;
-- else v.t.state := backoff; end if;
-- We should not go to back off if the access wasn't to us
when s_data =>
if r.t.pending = '1' then v.t.pending := not ((habort or not r.pci.trdy) and read_match); end if;
if (pcii.frame = '0' and r.pci.stop ='0' and (r.pci.trdy or not pcii.irdy) = '1') then
v.t.state := backoff;
if r.t.last = '0' then v.t.last := r.t.msel and r.t.lwrite and v.t.wdel; end if;
v.t.fifo.raddr := r.t.fifo.raddr - (r.t.read and r.t.msel and not fifort_limit);
-- elsif (pcii.frame = '1' and (r.pci.trdy = '0' or r.pci.stop = '0')) then
elsif (pcii.frame = '1' and (r.t.trdy_del = '0' or r.pci.stop = '0')) then -- (send last word in fifo) bug fix ***
v.t.state := turn_ar;
if r.t.last = '0' then v.t.last := r.t.msel and r.t.lwrite and v.t.wdel; end if;
v.t.fifo.raddr := r.t.fifo.raddr - (r.t.read and r.t.msel and not fifort_limit);
end if;
when backoff =>
v.t.detectperr(0) := '0';
if pcii.frame = '1' then v.t.state := turn_ar; end if;
end case;
-- #TRDY assert
--if (v.t.state = s_data and habort = '0' and ready = '1' and retry = '0') then v.pci.trdy := '0'; end if;
-- Changed to only deassert trdy when irdy is asserted [nisse]
if (v.t.state = s_data and habort = '0' and (ready or (pcii.irdy and not r.pci.trdy)) = '1' and retry = '0') then v.pci.trdy := '0'; end if;
-- #STOP assert
--if (v.t.state = backoff or (v.t.state = s_data and ((tabort or ((term or retry) and not habort)) = '1'))) then
-- Changed to only deassert stop when irdy is asserted [nisse]
if (v.t.state = backoff or (v.t.state = s_data and ((tabort or (((term and (not pcii.irdy or not r.pci.stop)) or retry) and not habort)) = '1'))) then
v.pci.stop := '0'; end if;
-- #DEVSEL assert
if (((v.t.state = backoff and r.pci.devsel = '0') or v.t.state = s_data) and (read_match and tabort) = '0') then v.pci.devsel := '0'; end if;
-- Enable #TRDY, #STOP and #DEVSEL
if (v.t.state = s_data) or (v.t.state = backoff) or (v.t.state = turn_ar) then
v.pci.oe_ctrl := not hit;
else v.pci.oe_ctrl := '1'; end if;
-- Signaled target abort
if (r.pci.devsel and not (r.pci.stop or r.pci.oe_ctrl)) = '1' then v.stat.sta := '1'; end if;
if (fifort_limit and v.t.thold) = '1' then --v.pci.trdy := '0';
elsif (r.t.thold and not v.t.thold) = '1' then --v.pci.trdy := '1';
end if;
-- Removed, (ready is delayed instead) [nisse]
--if r.t.state = s_data and v.t.state = s_data and r.pci.trdy = '0'
-- and v.pci.trdy = '1' and v.t.wdel = '1' and pcii.frame = '0' then -- (send last word in fifo) bug fix ***
-- v.t.trdy_del := '0';
--v.pci.trdy := '0';
--v.t.trdy_del := v.pci.trdy;
--else
v.t.trdy_del := v.pci.trdy;
--end if;
if r.t.state = s_data and r.pci.trdy = '1' and v.pci.trdy = '0' and pcii.frame = '0' then -- bug fix ***
readt_dly := '1';
v.t.fifo.raddr := r.t.fifo.raddr + (r.t.read and not fifort_limit and t_valid);
end if;
-- Latched signals to AHB backend
if (r.t.state = b_busy) then
if (hstart or hstart_ack) = '0' then -- must be idle
v.t.lwrite := not r.t.read;
if r.t.msel = '1' then
v.t.lburst := r.t.burst;
v.t.lcbe := pr.cbe;
if r.t.barsel = '0' then v.t.laddr := r.page & r.t.addr(MADDR_WIDTH-2 downto 2) & "00";
else v.t.laddr := r2.dmapage & r.t.addr(DMAMADDR_WIDTH-1 downto 2) & "00"; end if;
v.t.lmult := r.t.mult;
rtdone := '0'; v.t.fifo.waddr := (others => '0');
hstart := r.t.read and r.t.msel;
end if;
end if;
end if;
-- Read data mux
if r.t.csel = '1' then tad := cdata;
elsif r.t.psel = '1' then
tad(31 downto MADDR_WIDTH-1) := r.page;
tad(MADDR_WIDTH-2 downto 0) := zero32(MADDR_WIDTH-2 downto 1) & r.bt_enable;
-- elsif (r.t.state = b_busy or (r.pci.trdy or pcii.irdy) = '0') then tad := fifo1o.rdata(31 downto 0);
elsif (r.t.state = b_busy or (r.pci.trdy or pcii.irdy) = '0' or r.t.wdel = '1') then tad := byte_twist(fifo1o.rdata(31 downto 0), r.bt_enable); -- bug fix ***
end if;
-- FIFO controller
if ((fifowt_limit and write_access) = '1' or (r.t.last or rtdone) = '1') then
if hstart = hstart_ack then
if rtdone = '0' then hstart := not hstart_ack; v.t.fifo.side := hstart; end if;
if r.t.last = '1' then rtdone := '1'; v.t.last := '0';
else v.t.fifo.waddr := (others => '0');
if rtdone = '1' then
rtdone := '0'; hstart := '0'; v.t.fifo.side := '0';
end if;
end if;
end if;
end if;
-- Changed to only reset address counter when last word is transfered [nisse]
--if (fifort_limit and v.t.wdel) = '1' then
-- if hstart_ack = '1' then hstart := '0'; v.t.fifo.raddr := (others => '0');
-- else v.t.fifo.raddr := (others => '0'); end if;
--end if;
if hstart_ack = '1' and (fifort_limit and r.t.thold and not v.t.thold) = '1' then
hstart := '0'; v.t.fifo.raddr := (others => '0');
end if;
-- Hold AD if irdy waitstates after fifo switch [nisse]
if r.t.state = s_data and pcii.irdy = '1' and r.pci.trdy = '1' and v.pci.trdy = '0' and r.t.thold2 = '0' then v.t.thold2 := '1';
elsif r.t.thold2 = '1' and pcii.irdy = '0' then v.t.thold2 := '0'; end if;
----------------------
--- PCI TARGET END ---
----------------------
------------------
--- PCI MASTER ---
------------------
if MASTER = 1 then
bus_idle := pcii.frame and pcii.irdy;
data_transfer := not (pcii.trdy or r.pci.irdy);
data_transfer_r := not (pr.trdy or pr.irdy);
data_phase := not ((pcii.trdy and pcii.stop) or r.pci.irdy);
targ_d_w_data := not (pr.stop or pr.trdy);
targ_abort := pr.devsel and not pr.stop;
-- Request from AHB backend to start PCI transaction
if (pstart and not pstart_ack) = '1' then
if (r.m.fstate = idle and r.m.request = '0') then
v.m.request := '1';
rmdone := '0'; v.m.valid := '1';
v.m.fifo.waddr := (others => '0');
v.m.hwrite := r2.s.pcicomm(0);
end if;
end if;
-- Master timeout and DEVSEL timeout
if ((pr.irdy and not pr.frame) or (pr.devsel and not r.pci.oe_frame)) = '1' then
if r.m.cnt /= "000" then v.m.cnt := r.m.cnt - 1;
else mto := '1'; end if;
else v.m.cnt := (others => '1'); end if;
-- Latency counter
if r.pci.frame = '0' then
if r.m.ltim > "00000000" then v.m.ltim := r.m.ltim - '1';
else lto := '1'; end if;
else
v.m.ltim := r.ltim;
end if;
-- Last data
case r2.s.pcicomm is
when MEM_R_MULT | MEM_R_LINE =>
if (r.m.fifo.waddr >= (FIFO_FULL - "10") and r.m.fifo.side = '1') then
comp := '1';
else comp := '0'; end if;
when MEM_WRITE | MEM_W_INV => comp := not r.m.valid;
when others => comp := '1';
end case;
-- Minimun latency
--if lto = '0' then grant := '0'; end if;
if lto = '0' then grant := '0'; -- latency timer bug fix
elsif pcii.gnt = '1' then v.m.lto := '1'; end if;
-- Data parity error detected
if (r.m.fstate /= idle and r.stat.dped = '0') then v.stat.dped := r.comm.per and not pcii.perr; end if;
-- FIFO control state machine
case r.m.fstate is
when idle =>
v.m.lto := '0';
if (r.m.request and bus_idle and not pcii.gnt) = '1' and (r.m.state = idle or r.m.state = dr_bus) then
v.m.fstate := addr; v.m.fifo.waddr := (others => '0'); v.m.fifo.side := '0'; m_request := '1';
end if;
when addr =>
-- if (wsdone = '1' and (r.m.fifo.raddr + '1') = r2.s.fifo.waddr) then v.m.valid := '0'; end if;
if (wsdone = '1' and ((r.m.fifo.raddr + '1') = r2.s.fifo.waddr) and (m_read_side = r2.s.last_side)) then v.m.valid := '0'; end if; --bug fix kc
if fiform_limit = '1' then v.m.fstate := last1;
else v.m.fstate := incr; end if;
v.m.fifo.raddr := r.m.fifo.raddr + r.m.hwrite;
v.m.first := '1'; v.m.firstw := '1';
when incr =>
d_ready := '1';
if r.m.valid = '0' then v.m.lto := '0'; end if; -- dont look at latency timer if done
if data_transfer = '1' then
--if fiform_limit = '1' then v.m.fstate := last1; v.m.split := not backendnr; end if;
if fiform_limit = '1' and r.m.lto = '0' then v.m.fstate := last1; v.m.split := not backendnr; end if; -- bug fix latency timer
-- if (wsdone = '1' and (r.m.fifo.raddr + pcii.stop) = r2.s.fifo.waddr) then v.m.valid := '0'; end if;
if (wsdone = '1' and ((r.m.fifo.raddr + pcii.stop) = r2.s.fifo.waddr) and (m_read_side = r2.s.last_side)) then v.m.valid := '0'; end if; --bug fix kc
v.m.fifo.raddr := r.m.fifo.raddr + r.m.hwrite;
v.m.first := '0';
end if;
if data_transfer_r = '1' then
if fifowm_stop = '1' then
if r.m.firstw = '1' then
if (fifowm_limit and pr.stop) = '1' then v.m.fifo.side := not r.m.fifo.side; v.m.firstw := '0'; pstart_ack := pstart; end if;
end if;
end if;
v.m.fifo.waddr := r.m.fifo.waddr + (not r.m.hwrite);
end if;
if pr.stop = '0' then
if targ_abort = '1' then v.m.fstate := abort;
elsif targ_d_w_data = '1' then v.m.fstate := ttermwd;
elsif r.m.first = '1' then v.m.fstate := t_retry;
-- else v.m.fstate := ttermnd; end if;
else -- bug fix ***
-- if r.m.fifo.waddr = "0000000" then v.m.rmdone := '1'; end if;
if r.m.fifo.waddr = zero32(FIFO_DEPTH - 2 downto 0) then v.m.rmdone := '1'; end if;
v.m.fstate := ttermnd;
end if;
elsif mto = '1' then v.m.fstate := abort;
--elsif grant = '1' then -- pci_gnt bug fix
-- if r.m.hwrite = '0' then rmdone := not r.m.fifo.side; v.m.fifo.side := '1'; v.m.fstate := done; pstart_ack := pstart;
-- else v.m.fstate := idle; end if;
--elsif (pr.frame and not r.m.first) = '1' then
elsif (pr.frame and not pr.trdy and not r.m.first) = '1' then -- not done if target not ready *** bug fix
if r.m.hwrite = '0' then rmdone := not r.m.fifo.side; v.m.fifo.side := '1'; v.m.fstate := done; pstart_ack := pstart;
--else v.m.fstate := done; pstart_ack := pstart; end if;
else
if r.m.lto = '1' then -- latency timer bug fix
v.m.fifo.raddr := r.m.fifo.raddr - r.m.hwrite;
v.m.fstate := idle;
else
v.m.fstate := done; pstart_ack := pstart;
end if;
end if;
elsif (pr.devsel and not r.m.first) = '1' then
if r.m.hwrite = '0' then rmdone := not r.m.fifo.side; v.m.fifo.side := '1'; v.m.fstate := done; pstart_ack := pstart;
else v.m.fstate := idle; end if;
end if;
when last1 =>
if (pr.trdy and not pr.stop) = '1' then
if targ_abort = '1' then v.m.fstate := abort;
elsif targ_d_w_data = '1' then v.m.fstate := ttermwd;
else v.m.fstate := ttermnd; v.m.valid := '1'; end if;
--elsif (pr.frame and not r.m.first and not r.m.split) = '1' then v.m.fstate := done; rmdone := not r.m.fifo.side; pstart_ack := pstart;
-- not done if target not ready *** bug fix
elsif (pr.frame and not pr.trdy and not r.m.first and not r.m.split) = '1' then v.m.fstate := done; rmdone := not r.m.fifo.side; pstart_ack := pstart;
elsif data_transfer = '1' then
if r.m.valid = '1' then v.m.fstate := sync; pstart_ack := pstart;
else v.m.fstate := done; rmdone := not r.m.fifo.side; pstart_ack := pstart; end if;
else d_ready := '1';
end if;
when sync =>
if pstart = not pstart_ack then
v.m.split := '0';
if ((r.m.split or (pr.trdy and not pr.stop and not r.m.split)) = '1' or r.m.state /= m_data) then v.m.fstate := idle; d_ready := '1';
else
--if (wsdone = '1' and (r.m.fifo.raddr + '1') = r2.s.fifo.waddr) then v.m.valid := '0'; end if;
if (r2.trans(4) = '1' and (r.m.fifo.raddr + '1') = r2.s.fifo.waddr) then v.m.valid := '0'; end if; -- not synced wsdone
v.m.fstate := incr; data_transfer := '1'; v.m.fifo.raddr := r.m.fifo.raddr + r.m.hwrite; d_ready := '1';
end if;
else m_read_side := '1';
end if;
when t_retry =>
v.m.fifo.raddr := r.m.fifo.raddr - r.m.hwrite; v.m.fstate := idle;
when ttermwd =>
if data_transfer = '1' then v.m.fifo.raddr := r.m.fifo.raddr + r.m.hwrite;
elsif pr.trdy = '1' then v.m.fifo.raddr := r.m.fifo.raddr - r.m.hwrite;
if (r.m.hwrite and r.m.valid) = '1' then v.m.fstate := idle;
else v.m.fstate := done; rmdone := not r.m.fifo.side; v.m.fifo.side := '1'; pstart_ack := pstart; end if;
end if;
when ttermnd =>
if r.m.hwrite = '1' then
v.m.fifo.raddr := r.m.fifo.raddr - '1';
-- if (r.m.fifo.raddr /= (r2.s.fifo.waddr + '1') or wsdone = '0') then v.m.valid := '1'; v.m.fstate := idle; -- bug fix ***
if (r.m.fifo.raddr /= (r2.s.fifo.waddr + '1') or wsdone = '0' or r.m.valid = '1') then v.m.valid := '1'; v.m.fstate := idle;
else v.m.fstate := done; rmdone := not r.m.fifo.side; v.m.fifo.side := '1'; pstart_ack := pstart; end if;
-- else v.m.fstate := done; rmdone := not r.m.fifo.side; v.m.fifo.side := '1'; pstart_ack := pstart; end if;
else v.m.fstate := done; rmdone := (not r.m.fifo.side or r.m.rmdone); v.m.fifo.side := '1'; pstart_ack := pstart; end if; -- bug fix ***
when abort =>
v.m.fifo.raddr := (others => '0'); v.m.fifo.waddr := (others => '0');
v.m.fstate := done; pstart_ack := pstart; pabort := '1';
when done =>
d_ready := '1'; comp := '1'; v.m.request := '0';
if (pstart or pstart_ack) = '0' then
v.m.fstate := wdone; v.m.fifo.raddr := (others => '0'); v.m.fifo.side := '0'; rmdone := '1';
else pstart_ack := pstart; end if;
when wdone =>
d_ready := '1'; comp := '1';
if (r.m.state = idle or r.m.state = dr_bus) then v.m.fstate := idle; pabort := '0'; end if;
end case;
-- PCI master state machine
case r.m.state is
when idle => -- Master idle
v.m.stopframe := '0';
if (pcii.gnt = '0' and bus_idle = '1') then
if m_request = '1' then v.m.state := addr;
else v.m.state := dr_bus; end if;
end if;
when addr => -- Always one address cycle at the beginning of an transaction
v.m.stopframe := '0';
v.m.state := m_data;
when m_data => -- Master transfers data
if r.m.hwrite = '0' then v.m.detectperr(0) := '1'; end if; -- Only detect perr on read
if r.pci.frame = '1' then v.m.stopframe := '1'; end if; -- ***
if (r.pci.frame = '0') or ((r.pci.frame and pcii.trdy and pcii.stop and not mto) = '1') then
v.m.state := m_data;
if (r.pci.frame and not d_ready) = '1' then d_ready := '1'; end if;
elsif ((r.pci.frame and (mto or not pcii.stop)) = '1') then
v.m.state := s_tar;
v.m.stop_req := '1';
else v.m.state := turn_ar; end if;
when turn_ar => -- Transaction complete
v.m.detectperr(0) := '0';
if pcii.gnt = '0' then
if m_request = '1' then v.m.state := addr;
else v.m.state := dr_bus; end if;
else v.m.state := idle; end if;
when s_tar => -- Stop was asserted
v.m.detectperr(0) := '0';
if pcii.gnt = '0' then v.m.state := dr_bus;
else v.m.state := idle; end if;
when dr_bus => -- Drive bus when parked on this agent
if pcii.gnt = '1' then v.m.state := idle;
elsif m_request = '1' then v.m.state := addr; end if;
end case;
-- FIFO write strobe
m_fifo_write := not r.m.hwrite and not pr.irdy and not (pr.trdy and (pr.stop or not r.trans(3))) and not r.pci.oe_irdy;
-- PCI data mux
if v.m.state = addr then
if r.m.hwrite = '1' then mad := (r2.s.maddr + ((((not r2.s.fifo.side) & r.m.fifo.raddr)) & "00"));
else mad := r2.s.maddr; end if;
elsif (r.m.state = addr or data_transfer = '1') then mad := fifo3o.rdata(31 downto 0);
end if;
-- Target abort
if ((pr.devsel and pr.trdy and not pr.gnt and not pr.stop) = '1') then v.stat.rta := '1'; end if;
-- Master abort
if mto = '1' then v.stat.rma := '1'; end if;
-- Drive FRAME# and IRDY#
if (v.m.state = addr or v.m.state = m_data) then v.pci.oe_frame := '0'; end if;
-- Drive CBE#
if (v.m.state = addr or v.m.state = m_data or v.m.state = dr_bus) then v.pci.oe_cbe := '0'; end if;
-- Drive IRDY# (FRAME# delayed one pciclk)
v.pci.oe_irdy := r.pci.oe_frame;
-- FRAME# assert
if (v.m.state = addr or (v.m.state = m_data and mto = '0' and v.m.stopframe = '0' -- stopframe fix frame when pci_gnt is deasserted
--and ((((pcii.stop or not d_ready) and not (comp or v.m.split or not v.m.valid)) and not grant)) = '1')) -- dont change frame when gnt = 1 if not irdy and trdy or stop
and ((((pcii.stop or not d_ready) and not (comp or v.m.split or not v.m.valid)) and not (grant and not pr.irdy and (not pcii.trdy or not pcii.stop) ) )) = '1'))
then
v.pci.frame := '0';
end if;
-- IRDY# assert
if (v.m.state = m_data and ((d_ready or mto or (not r.m.valid) or (v.pci.frame and not r.pci.frame)) = '1')) then v.pci.irdy := '0'; end if;
-- REQ# assert
if ((v.m.request = '1' and (r.m.fstate = idle or comp = '0')) and (v.m.stop_req or r.m.stop_req) = '0') then v.pci.req := '0'; end if;
-- C/BE# assert
if v.m.state = addr then v.pci.cbe := r2.s.pcicomm; else v.pci.cbe := r2.s.be; end if;
end if;
---------------------
---PCI MASTER END ---
---------------------
----------------------
--- SHARED SIGNALS ---
----------------------
v.m.detectperr(1) := r.m.detectperr(0);
v.t.detectperr(1) := r.t.detectperr(0);
-- Drive PAR one clock after AD
v.pci.oe_par := r.pci.oe_ad;
v.pci.par := xorv(r.pci.ad & r.pci.cbe); -- Default asserted by master
-- PERR error
if (r.m.detectperr(0) = '1' or (r.m.detectperr(1) and not r.pci.perr) = '1') -- Drive perr for master:read
or (r.t.detectperr(0) = '1' or (r.t.detectperr(1) and not r.pci.perr) = '1') then -- Drive perr for target:write
v.pci.oe_perr := not(r.comm.per and r.pci.oe_par and not (pr.irdy and pr.trdy)) and (r.pci.oe_perr or r.pci.perr);
else
v.pci.oe_perr := (r.pci.oe_perr or r.pci.perr);
end if;
v.pci.perr := not (pcii.par xor xorv(pr.ad & pr.cbe)) or pr.irdy or pr.trdy; -- Detect parity error
v.pci.ad := mad; -- Default asserted by master
-- Master drives AD
if (v.m.state = addr or (v.m.state = m_data and r.m.hwrite = '1') or v.m.state = dr_bus) then
v.pci.oe_ad := '0';
end if;
-- Target drives AD
if r.t.read = '1' then
if v.t.state = s_data then
v.pci.oe_ad := '0';
--v.pci.ad := tad; end if;
-- Hold AD when master adds waitstates [nisse]
if (v.t.thold = '0' or (v.t.trdy_del = '0' and r.t.trdy_del = '0')) and v.t.thold2 = '0' and (pcii.irdy and not r.pci.trdy) = '0' then v.pci.ad := tad; end if;
end if;
if r.t.state = s_data then
v.pci.par := xorv(r.pci.ad & pcii.cbe);
end if;
end if;
adin <= v.pci.ad;
v.noe_ad := not v.pci.oe_ad;
v.noe_ctrl := not v.pci.oe_ctrl;
v.noe_par := not v.pci.oe_par;
v.noe_req := not v.pci.oe_req;
v.noe_frame := not v.pci.oe_frame;
v.noe_cbe := not v.pci.oe_cbe;
v.noe_irdy := not v.pci.oe_irdy;
v.noe_perr := not v.pci.oe_perr;
v.noe_serr := not v.pci.oe_serr;
if (scanen = 1) and (syncrst = 1) and (ahbmi.testen = '1') then
voe_ad := (others => ahbmi.testoen);
oe_ad := '1';
oe_ctrl := '1';
oe_par := '1';
oe_req := '1';
oe_frame := '1';
oe_cbe := '1';
oe_irdy := '1';
oe_perr := '1';
oe_serr := '1';
elsif oepol = 0 then
if (syncrst = 1) and (pcirstin = '0') then
voe_ad := (others => '1');
oe_ad := '1';
oe_ctrl := '1';
oe_par := '1';
oe_req := '1';
oe_frame := '1';
oe_cbe := '1';
oe_irdy := '1';
oe_perr := '1';
else
voe_ad := (others => v.pci.oe_ad);
oe_ad := r.pci.oe_ad;
oe_ctrl := r.pci.oe_ctrl;
oe_par := r.pci.oe_par;
oe_req := r.pci.oe_req;
oe_frame := r.pci.oe_frame;
oe_cbe := r.pci.oe_cbe;
oe_irdy := r.pci.oe_irdy;
oe_perr := r.pci.oe_perr;
oe_serr := r.pci.oe_serr;
end if;
else -- oepol = 1
if (syncrst = 1) and (pcirstin = '0') then
voe_ad := (others => '0');
oe_ad := '0';
oe_ctrl := '0';
oe_par := '0';
oe_req := '0';
oe_frame := '0';
oe_cbe := '0';
oe_irdy := '0';
oe_perr := '0';
else
voe_ad := (others => v.noe_ad);
oe_ad := r.noe_ad;
oe_ctrl := r.noe_ctrl;
oe_par := r.noe_par;
oe_req := r.noe_req;
oe_frame := r.noe_frame;
oe_cbe := r.noe_cbe;
oe_irdy := r.noe_irdy;
oe_perr := r.noe_perr;
oe_serr := r.noe_serr;
end if;
end if;
--------------------------
--- SHARED SIGNALS END ---
--------------------------
v.trans(0) := hstart;
v.trans(1) := pabort;
v.trans(2) := pstart_ack;
v.trans(3) := pcidc;
v.trans(4) := rtdone;
v.trans(5) := rmdone;
if prrst = '0' then
v.t.state := idle; v.m.state := idle; v.m.fstate := idle;
v.bar0 := (others => '0'); v.bar0_conf := '0';
v.bar1 := (others => '0'); v.bar1_conf := '0';
v.t.msel := '0'; v.t.csel := '0';
v.t.pending := '0'; v.t.lwrite := '0';
v.bt_enable := '1'; -- twisting enabled by default, changed through page0
v.page(31 downto 30) := "01";
v.page(29 downto MADDR_WIDTH-1) := zero32(29 downto MADDR_WIDTH-1);
v.pci.par := '0';
v.comm.msen := not pr.host;
v.comm.men := '0';
v.comm.mwie := '0';
v.comm.per := '0';
v.comm.ser := '0';
v.stat.rta := '0';
v.stat.rma := '0';
v.stat.sta := '0';
v.stat.dped := '0';
v.stat.dpe := '0';
v.stat.sse := '0';
v.cline := (others => '0');
v.ltim := (others => '0');
v.intline := (others => '0');
v.trans := (others => '0');
v.t.fifo.waddr := (others => '0');
v.t.fifo.raddr := (others => '0');
v.m.fifo.waddr := (others => '0');
v.m.fifo.raddr := (others => '0');
v.t.fifo.side := '0';
v.m.fifo.side := '0';
v.m.request := '0';
v.m.hwrite := '0';
v.m.valid := '1';
v.m.split := '0';
v.m.last := '0'; v.t.last := '0';
v.t.laddr := (others => '0'); -- to remove x problem in gate-simulation
v.m.detectperr(0) := '0'; v.t.detectperr(0) := '0';
end if;
cbe_fifoi.wen <= t_fifo_write;
cbe_fifoi.waddr <= r.t.fifo.side & r.t.fifo.waddr;
cbe_fifoi.wdata(3 downto 0) <= pr.cbe;
fifo2i.wen <= t_fifo_write;
fifo2i.waddr <= r.t.fifo.side & r.t.fifo.waddr;
fifo2i.wdata <= byte_twist(pr.ad, r.bt_enable);
fifo1i.ren <= '1';
fifo1i.raddr <= t_read_side & (r.t.fifo.raddr + readt_dly);
fifo4i.wen <= m_fifo_write;
fifo4i.waddr <= r.m.fifo.side & r.m.fifo.waddr;
fifo4i.wdata <= pr.ad;
fifo3i.ren <= '1';
fifo3i.raddr <= m_read_side & (r.m.fifo.raddr + data_transfer);
rin <= v;
rioe_ad <= voe_ad;
pcio.cbeen <= (others => oe_cbe);
pcio.cbe <= r.pci.cbe;
pcio.vaden <= roe_ad;
pcio.aden <= oe_ad;
pcio.ad <= ad;
-- pcio.trdy <= r.pci.trdy;
pcio.trdy <= r.t.trdy_del; -- (send last word in fifo) bug fix ***
pcio.ctrlen <= oe_ctrl;
pcio.trdyen <= oe_ctrl;
pcio.devselen <= oe_ctrl;
pcio.stopen <= oe_ctrl;
pcio.stop <= r.pci.stop;
pcio.devsel <= r.pci.devsel;
pcio.par <= r.pci.par;
pcio.paren <= oe_par;
pcio.perren <= oe_perr;
pcio.perr <= r.pci.perr;
pcio.serr <= r.pci.serr;
pcio.serren <= oe_serr;
pcio.reqen <= oe_req;
pcio.req <= r.pci.req;
pcio.frameen <= oe_frame;
pcio.frame <= r.pci.frame;
pcio.irdyen <= oe_irdy;
pcio.irdy <= r.pci.irdy;
end process;
rstinputgen : if hostrst = 0 generate
pcirstin <= pcii.rst;
pcio.rst <= '1';
end generate;
hostrstgen : if hostrst = 1 generate
--pcirstin <= rst when pcii.host = '0' else pcii.rst;
pcirstin <= pcii.rst;
pcio.rst <= rst when pcii.host = '0' else '1';
end generate;
pcirst <= ahbmi.testrst when (scanen = 1) and (ahbmi.testen = '1')
else pcirstin;
pr_regs : process (pciclk)
begin
if rising_edge (pciclk) then
pr.ad <= to_x01(pcii.ad);
pr.cbe <= to_x01(pcii.cbe);
pr.devsel <= to_x01(pcii.devsel);
pr.frame <= to_x01(pcii.frame);
pr.idsel <= to_x01(pcii.idsel);
pr.irdy <= to_x01(pcii.irdy);
pr.trdy <= to_x01(pcii.trdy);
pr.par <= to_x01(pcii.par);
pr.stop <= to_x01(pcii.stop);
prrst <= to_x01(pcirstin);
pr.gnt <= to_x01(pcii.gnt);
pr.host <= to_x01(pcii.host);
end if;
end process;
regs : process (pciclk, pcirst)
begin
if rising_edge (pciclk) then
r <= rin; ad <= adin;
end if;
if (syncrst = 0) and (pcirst = '0') then -- asynch reset required
r.pci.oe_ad <= '1'; r.pci.oe_ctrl <= '1'; r.pci.oe_par <= '1';
r.pci.oe_req <= '1'; r.pci.oe_frame <= '1'; r.pci.oe_cbe <= '1';
r.pci.oe_irdy <= '1'; r.pci.oe_perr <= '1';
r.noe_ad <= '0'; r.noe_ctrl <= '0'; r.noe_par <= '0';
r.noe_req <= '0'; r.noe_frame <= '0'; r.noe_cbe <= '0';
r.noe_irdy <= '0'; r.noe_perr <= '0';
end if;
end process;
oeregs_pol0 : if oepol = 0 generate
oeregs : process (pciclk, pcirst)
begin
if rising_edge (pciclk) then
roe_ad <= rioe_ad;
end if;
if (syncrst = 0) and (pcirst = '0') then -- asynch reset required
roe_ad <= (others => '1');
end if;
end process;
end generate;
oeregs_pol1 : if oepol = 1 generate
oeregs : process (pciclk, pcirst)
begin
if rising_edge (pciclk) then
roe_ad <= rioe_ad;
end if;
if (syncrst = 0) and (pcirst = '0') then -- asynch reset required
roe_ad <= (others => '0');
end if;
end process;
end generate;
cpur : process (clk)
begin
if rising_edge (clk) then
r2 <= r2in;
end if;
end process;
oe0 : if oepol = 0 generate
pcio.inten <= '1';
pcio.vinten <= (others => '1');
pcio.locken <= '1';
end generate;
oe1 : if oepol = 1 generate
pcio.inten <= '0';
pcio.vinten <= (others => '0');
pcio.locken <= '0';
end generate;
pcio.int <= '1';
pcio.lock <= '1';
pcio.power_state <= (others => '0');
pcio.pme_enable <= '0';
pcio.pme_clear <= '0';
msttgt : if MASTER = 1 generate
ahbmst0 : pciahbmst generic map (hindex => hmstndx, devid => GAISLER_PCIFBRG, incaddr => 1)
port map (rst, clk, dmai, dmao, ahbmi, ahbmo);
fifo1 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH, dbits => FIFO_DATA_BITS, sepclk => 1)
port map (pciclk, fifo1i.ren, fifo1i.raddr, fifo1o.rdata, clk, fifo1i.wen, fifo1i.waddr, fifo1i.wdata);
fifo2 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH, dbits => FIFO_DATA_BITS, sepclk => 1)
port map (clk, fifo2i.ren, fifo2i.raddr, fifo2o.rdata, pciclk, fifo2i.wen, fifo2i.waddr, fifo2i.wdata);
fifo3 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH, dbits => FIFO_DATA_BITS, sepclk => 1)
port map (pciclk, fifo3i.ren, fifo3i.raddr, fifo3o.rdata, clk, fifo3i.wen, fifo3i.waddr, fifo3i.wdata);
fifo4 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH, dbits => FIFO_DATA_BITS, sepclk => 1)
port map (clk, fifo4i.ren, fifo4i.raddr, fifo4o.rdata, pciclk, fifo4i.wen, fifo4i.waddr, fifo4i.wdata);
cbe_fifo : syncram_2p generic map (tech => 0, abits => FIFO_DEPTH, dbits => 4, sepclk => 1)
port map (clk, cbe_fifoi.ren, cbe_fifoi.raddr, cbe_fifoo.rdata(3 downto 0), pciclk, cbe_fifoi.wen, cbe_fifoi.waddr, cbe_fifoi.wdata(3 downto 0));
-- pragma translate_off
bootmsg : report_version
generic map ("pci_mtf" & tost(hslvndx) &
": 32-bit PCI/AHB bridge rev " & tost(REVISION) &
", " & tost(2**abits/2**20) & " Mbyte PCI memory BAR, " &
tost(2**FIFO_DEPTH) & "-word FIFOs" );
-- pragma translate_on
end generate;
tgtonly : if MASTER = 0 generate
ahbmst0 : pciahbmst generic map (hindex => hmstndx, devid => GAISLER_PCIFBRG, incaddr => 1)
port map (rst, clk, dmai, dmao, ahbmi, ahbmo);
fifo1 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH, dbits => FIFO_DATA_BITS, sepclk => 1)
port map (pciclk, fifo1i.ren, fifo1i.raddr, fifo1o.rdata, clk, fifo1i.wen, fifo1i.waddr, fifo1i.wdata);
fifo2 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH, dbits => FIFO_DATA_BITS, sepclk => 1)
port map (clk, fifo2i.ren, fifo2i.raddr, fifo2o.rdata, pciclk, fifo2i.wen, fifo2i.waddr, fifo2i.wdata);
cbe_fifo : syncram_2p generic map (tech => 0, abits => FIFO_DEPTH, dbits => 4, sepclk => 1)
port map (clk, cbe_fifoi.ren, cbe_fifoi.raddr, cbe_fifoo.rdata(3 downto 0), pciclk, cbe_fifoi.wen, cbe_fifoi.waddr, cbe_fifoi.wdata(3 downto 0));
-- pragma translate_off
bootmsg : report_version
generic map ("pci_mtf" & tost(hmstndx) &
": 32-bit PCI/AHB bridge rev, target-only, " & tost(REVISION) &
", " & tost(2**abits/2**20) & " Mbyte PCI memory BAR, " &
tost(2**FIFO_DEPTH) & "-word FIFOs" );
-- pragma translate_on
end generate;
end;
| gpl-2.0 |
a4a881d4/ringbus4xilinx | src/dma/AAI.vhd | 2 | 1825 | ---------------------------------------------------------------------------------------------------
--
-- Title : auto add cpu interface
-- Design : Ring Bus
-- Author : Zhao Ming
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
--
-- File : AAI.vhd
-- Generated : 2013/9/5
-- From :
-- By :
--
---------------------------------------------------------------------------------------------------
--
-- Description : auto add cpu interface
--
-- Rev: 3.1
--
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.dma_config.all;
entity AAI is
generic(
width : natural := 32;
CPUDBwidth : natural := 8;
Baddr : std_logic_vector( 3 downto 0 ) := "0000"
);
port(
-- system signal
rst : in STD_LOGIC;
-- CPU bus
CS : in std_logic;
addr : in std_logic_vector( 3 downto 0 );
Din : in std_logic_vector( CPUDBwidth-1 downto 0 );
cpuClk : in std_logic;
Q : out std_logic_vector( width-1 downto 0 )
);
end AAI;
architecture behave of AAI is
signal start : natural range 0 to width+CPUDBwidth-1;
signal D : std_logic_vector( CPUDBwidth*32 downto 0 );
begin
writeP:process( cpuClk, rst )
begin
if rst='1' then
D<=( others=>'0' );
start<=0;
elsif rising_edge(cpuClk) then
if CS='1' then
if addr=reg_RESET and Din(0)='1' then
start<=0;
elsif addr=Baddr then
D( start+CPUDBwidth-1 downto start )<=Din;
start<=start+CPUDBwidth;
end if;
end if;
end if;
end process;
Q<=D(width-1 downto 0 );
end behave;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/gencomp/gencomp.vhd | 1 | 85952 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: gencomp
-- File: gencomp.vhd
-- Author: Jiri Gaisler et al. - Aeroflex Gaisler
-- Description: Declaration of portable memory modules, pads, e.t.c.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config.grlib_config_array;
use grlib.config_types.grlib_techmap_testin_extra;
package gencomp is
---------------------------------------------------------------------------
-- BASIC DECLARATIONS
---------------------------------------------------------------------------
-- technologies and libraries
constant NTECH : integer := 54;
type tech_ability_type is array (0 to NTECH) of integer;
constant inferred : integer := 0;
constant virtex : integer := 1;
constant virtex2 : integer := 2;
constant memvirage : integer := 3;
constant axcel : integer := 4;
constant proasic : integer := 5;
constant atc18s : integer := 6;
constant altera : integer := 7;
constant umc : integer := 8;
constant rhumc : integer := 9;
constant apa3 : integer := 10;
constant spartan3 : integer := 11;
constant ihp25 : integer := 12;
constant rhlib18t : integer := 13;
constant virtex4 : integer := 14;
constant lattice : integer := 15;
constant ut25 : integer := 16;
constant spartan3e : integer := 17;
constant peregrine : integer := 18;
constant memartisan : integer := 19;
constant virtex5 : integer := 20;
constant custom1 : integer := 21;
constant ihp25rh : integer := 22;
constant stratix1 : integer := 23;
constant stratix2 : integer := 24;
constant eclipse : integer := 25;
constant stratix3 : integer := 26;
constant cyclone3 : integer := 27;
constant memvirage90 : integer := 28;
constant tsmc90 : integer := 29;
constant easic90 : integer := 30;
constant atc18rha : integer := 31;
constant smic013 : integer := 32;
constant tm65gplus : integer := 33;
constant axdsp : integer := 34;
constant spartan6 : integer := 35;
constant virtex6 : integer := 36;
constant actfus : integer := 37;
constant stratix4 : integer := 38;
constant st65lp : integer := 39;
constant st65gp : integer := 40;
constant easic45 : integer := 41;
constant cmos9sf : integer := 42;
constant apa3e : integer := 43;
constant apa3l : integer := 44;
constant ut130 : integer := 45;
constant ut90 : integer := 46;
constant gf65 : integer := 47;
constant virtex7 : integer := 48;
constant kintex7 : integer := 49;
constant artix7 : integer := 50;
constant zynq7000 : integer := 51;
constant rhlib13t : integer := 52;
constant saed32 : integer := 53;
constant dare : integer := 54;
constant DEFMEMTECH : integer := inferred;
constant DEFPADTECH : integer := inferred;
constant DEFFABTECH : integer := inferred;
constant is_fpga : tech_ability_type :=
(inferred => 1, virtex => 1, virtex2 => 1, axcel => 1,
proasic => 1, altera => 1, apa3 => 1, spartan3 => 1,
virtex4 => 1, lattice => 1, spartan3e => 1, virtex5 => 1,
stratix1 => 1, stratix2 => 1, eclipse => 1,
stratix3 => 1, cyclone3 => 1, axdsp => 1,
spartan6 => 1, virtex6 => 1, actfus => 1,
stratix4 => 1, apa3e => 1, apa3l => 1, virtex7 => 1, kintex7 => 1,
artix7 => 1, zynq7000 => 1,
others => 0);
constant infer_mul : tech_ability_type := is_fpga;
constant syncram_2p_write_through : tech_ability_type :=
(rhumc => 1, eclipse => 1, others => 0);
constant regfile_3p_write_through : tech_ability_type :=
(rhumc => 1, ihp25 => 1, ihp25rh => 1, eclipse => 1, others => 0);
constant regfile_3p_infer : tech_ability_type :=
(inferred => 1, rhumc => 1, ihp25 => 1, rhlib18t => 0, ut90 => 1,
peregrine => 1, ihp25rh => 1, umc => 1, custom1 => 0, others => 0);
constant syncram_2p_dest_rw_collision : tech_ability_type :=
(memartisan => 1, smic013 => 1, easic45 => 1, ut130 => 1, others => 0);
constant syncram_dp_dest_rw_collision : tech_ability_type :=
(memartisan => 1, smic013 => 1, easic45 => 1, others => 0);
constant syncram_has_customif : tech_ability_type := (others => 0);
constant syncram_customif_maxwidth: integer := 64; -- Expand as needed
constant has_sram : tech_ability_type :=
(atc18s => 0, others => 1);
constant has_2pram : tech_ability_type :=
( atc18s => 0, umc => 0, rhumc => 0, ihp25 => 0, others => 1);
constant has_dpram : tech_ability_type :=
(virtex => 1, virtex2 => 1, memvirage => 1, axcel => 0,
altera => 1, apa3 => 1, spartan3 => 1, virtex4 => 1,
lattice => 1, spartan3e => 1, memartisan => 1, virtex5 => 1,
custom1 => 1, stratix1 => 1, stratix2 => 1, stratix3 => 1,
cyclone3 => 1, memvirage90 => 1, atc18rha => 1, smic013 => 1,
tm65gplus => 1, axdsp => 0, spartan6 => 1, virtex6 => 1,
actfus => 1, stratix4 => 1, easic45 => 1, apa3e => 1,
apa3l => 1, ut90 => 1, virtex7 => 1, kintex7 => 1, artix7 => 1, zynq7000 => 1, dare => 1, others => 0);
constant has_sram64 : tech_ability_type :=
(inferred => 0, virtex2 => 1, spartan3 => 1, virtex4 => 1,
spartan3e => 1, memartisan => 1, virtex5 => 1, smic013 => 1,
spartan6 => 1, virtex6 => 1, easic45 => 1, virtex7 => 1, kintex7 => 1,
artix7 => 1, zynq7000 => 1, others => 0);
constant has_sram128bw : tech_ability_type := (
virtex2 => 1, virtex4 => 1, virtex5 => 1, spartan3 => 1,
spartan3e => 1, spartan6 => 1, virtex6 => 1, virtex7 => 1, kintex7 => 1,
altera => 1, cyclone3 => 1, stratix2 => 1, stratix3 => 1, stratix4 => 1,
ut90 => 1, others => 0);
constant has_sram128 : tech_ability_type := (
virtex2 => 1, virtex4 => 1, virtex5 => 1, spartan3 => 1,
spartan3e => 1, spartan6 => 1, virtex6 => 1, virtex7 => 1, kintex7 => 1,
tm65gplus => 0, easic45 => 1, others => 0);
constant has_sram156bw : tech_ability_type := (
virtex2 => 0, virtex4 => 0, virtex5 => 0, spartan3 => 0,
spartan3e => 0, spartan6 => 0, virtex6 => 0, virtex7 => 0, kintex7 => 0,
altera => 0, cyclone3 => 0, stratix2 => 0, stratix3 => 0, stratix4 => 0,
tm65gplus => 0, custom1 => 1, ut90 => 1, others => 0);
constant has_sram256bw : tech_ability_type := (
virtex2 => 1, virtex4 => 1, virtex5 => 1, spartan3 => 1,
spartan3e => 1, spartan6 => 1, virtex6 => 1, virtex7 => 1, kintex7 => 1,
altera => 1, cyclone3 => 1, stratix2 => 1, stratix3 => 1, stratix4 => 1,
tm65gplus => 0, cmos9sf => 1, others => 0);
constant has_sram_2pbw : tech_ability_type := (
easic45 => 1, others => 0);
constant has_srambw : tech_ability_type := (easic45 => 1, others => 0);
constant has_2pfifo : tech_ability_type := (
altera => 1, stratix1 => 1, stratix2 => 1, stratix3 => 1,
stratix4 => 1, others => 0);
-- ram_raw_latency - describes how many edges on the write-port clock that
-- must pass before data is commited to memory. for example, if the write data
-- is commited to memory on the falling edge after a write cycle, and is
-- available to the read port after a short T_{raw} then ram_raw_latency
-- should be set to 1. If the data is available to the read port immediately
-- after the write-port clock rising edge that latches the write operation then
-- ram_raw_latency(tech) should return 0. If T_{raw} cannot be assumed to be
-- negligible (for instance, it is longer than a clock cycle on the read port)
-- then the ram_raw_latency value should be increased to cover also T_{raw}.
-- this value is important for cores that use DP or 2P memories in CDC.
constant ram_raw_latency : tech_ability_type := (easic45 => 1, others => 0);
constant padoen_polarity : tech_ability_type :=
(axcel => 1, proasic => 1, umc => 1, rhumc => 1, saed32 => 1, dare => 1, apa3 => 1,
ihp25 => 1, ut25 => 1, peregrine => 1, easic90 => 1, axdsp => 1,
actfus => 1, apa3e => 1, apa3l => 1, ut130 => 1, easic45 => 1,
ut90 => 1, others => 0);
constant has_pads : tech_ability_type :=
(inferred => 0, virtex => 1, virtex2 => 1, memvirage => 0,
axcel => 1, proasic => 1, atc18s => 1, altera => 0,
umc => 1, rhumc => 1, saed32 => 1, dare => 1, apa3 => 1, spartan3 => 1,
ihp25 => 1, rhlib18t => 1, virtex4 => 1, lattice => 0,
ut25 => 1, spartan3e => 1, peregrine => 1, virtex5 => 1, axdsp => 1,
easic90 => 1, atc18rha => 1, spartan6 => 1, virtex6 => 1,
actfus => 1, apa3e => 1, apa3l => 1, ut130 => 1, easic45 => 1,
ut90 => 1, virtex7 => 1, kintex7 => 1,
artix7 => 1, zynq7000 => 1, others => 0);
constant has_ds_pads : tech_ability_type :=
(inferred => 0, virtex => 1, virtex2 => 1, memvirage => 0,
axcel => 1, proasic => 0, atc18s => 0, altera => 0,
umc => 0, rhumc => 0, saed32 => 0, dare => 0, apa3 => 1, spartan3 => 1,
ihp25 => 0, rhlib18t => 1, virtex4 => 1, lattice => 0,
ut25 => 1, spartan3e => 1, virtex5 => 1, axdsp => 1,
spartan6 => 1, virtex6 => 1, actfus => 1,
apa3e => 1, apa3l => 1, ut130 => 0, easic45 => 1, virtex7 => 1, kintex7 => 1,
artix7 => 1, zynq7000 => 1, others => 0);
constant has_ds_combo : tech_ability_type :=
( rhumc => 1, ut25 => 1, ut130 => 1, others => 0);
constant has_clkand : tech_ability_type :=
( virtex => 1, virtex2 => 1, spartan3 => 1, spartan3e => 1, virtex4 => 1,
virtex5 => 1, ut25 => 1, rhlib18t => 1,
spartan6 => 1, virtex6 => 1, ut130 => 1, easic45 => 1,
ut90 => 1, virtex7 => 1, kintex7 => 1, artix7 => 1, zynq7000 => 1, saed32 => 1, dare => 1, others => 0);
constant has_clkmux : tech_ability_type :=
( virtex => 1, virtex2 => 1, spartan3 => 1, spartan3e => 1,
virtex4 => 1, virtex5 => 1, rhlib18t => 1,
spartan6 => 1, virtex6 => 1, ut130 => 1, easic45 => 1,
ut90 => 1, virtex7 => 1, kintex7 => 1, artix7 => 1, zynq7000 => 1, saed32 => 1, dare => 1, rhumc => 1, others => 0);
constant has_clkinv : tech_ability_type :=
( saed32 => 1, dare => 1, others => 0);
constant has_techbuf : tech_ability_type :=
( virtex => 1, virtex2 => 1, virtex4 => 1, virtex5 => 1,
spartan3 => 1, spartan3e => 1, axcel => 1, ut25 => 1,
apa3 => 1, easic90 => 1, axdsp => 1, actfus => 1,
apa3e => 1, apa3l => 1, ut130 => 1, easic45 => 1,
ut90 => 1, spartan6 => 1, virtex6 => 1, virtex7 => 1, kintex7 => 1,
artix7 => 1, zynq7000 => 1, others => 0);
constant has_tapsel : tech_ability_type :=
( virtex => 1, virtex2 => 1, virtex4 => 1, virtex5 => 1,
spartan3 => 1, spartan3e => 1,
spartan6 => 1, virtex6 => 1, virtex7 => 1, kintex7 => 1,
artix7 => 1, zynq7000 => 1, others => 0);
constant tap_tck_gated : tech_ability_type :=
( virtex => 1, virtex2 => 1, virtex4 => 1, virtex5 => 1, spartan3 => 1, spartan3e => 1,
spartan6 => 0, others => 0);
constant need_extra_sync_reset : tech_ability_type :=
(axcel => 1, atc18s => 1, ut25 => 1, rhumc => 1, saed32 => 1, dare => 1, tsmc90 => 1,
rhlib18t => 1, atc18rha => 1, easic90 => 1, tm65gplus => 1,
axdsp => 1, cmos9sf => 1, apa3 => 1, apa3e => 1, apa3l => 1,
ut130 => 1, easic45 => 1, ut90 => 1, others => 0);
constant is_unisim : tech_ability_type :=
( virtex => 1, virtex2 => 1, virtex4 => 1, virtex5 => 1,
spartan3 => 1, spartan3e => 1,
spartan6 => 1, virtex6 => 1, virtex7 => 1, kintex7 => 1, artix7 => 1, zynq7000 => 1, others => 0);
constant has_tap : tech_ability_type :=
(inferred => 0, virtex => 1, virtex2 => 1, axcel => 0,
proasic => 0, altera => 1, apa3 => 1, spartan3 => 1,
virtex4 => 1, lattice => 0, spartan3e => 1, virtex5 => 1,
stratix1 => 1, stratix2 => 1, eclipse => 0,
stratix3 => 1, cyclone3 => 1, axdsp => 0,
spartan6 => 1, virtex6 => 1, actfus => 1,
stratix4 => 1, easic45 => 0, apa3e => 1, apa3l => 1, virtex7 => 1, kintex7 => 1,
artix7 => 1, zynq7000 => 1,
others => 0);
constant has_clkgen : tech_ability_type :=
(inferred => 0, virtex => 1, virtex2 => 1, axcel => 1,
proasic => 1, altera => 1, apa3 => 1, spartan3 => 1,
virtex4 => 1, lattice => 0, spartan3e => 1, virtex5 => 1,
stratix1 => 1, stratix2 => 1, eclipse => 0, rhumc => 1, saed32 => 1, dare => 1,
stratix3 => 1, cyclone3 => 1, axdsp => 1,
spartan6 => 1, virtex6 => 1, actfus => 1, easic90 => 1,
stratix4 => 1, easic45 => 1, apa3e => 1, apa3l => 1,
rhlib18t => 1, ut130 => 1, ut90 => 1, virtex7 => 1, kintex7 => 1, artix7 => 1, zynq7000 => 1, others => 0);
constant has_ddr2phy: tech_ability_type :=
(inferred => 0, stratix2 => 1, stratix3 => 1, spartan3 => 1,
easic90 => 1, spartan6 => 1, easic45 => 1,
virtex4 => 1, virtex5 => 1, virtex6 => 1, others => 0);
constant ddr2phy_builtin_pads: tech_ability_type := (
-- Wrapped DDR2 IP cores with builtin pads
easic45 => 1,
-- Below techs have builtin pads for legacy reasons, can be converted if needed
easic90 => 1, spartan3 => 1, stratix3 => 1, stratix2 => 1,
others => 0);
constant ddr2phy_has_fbclk: tech_ability_type :=
(inferred => 1, others => 0);
constant ddrphy_has_fbclk: tech_ability_type :=
(others => 0);
constant ddr2phy_has_reg: tech_ability_type :=
(easic45 => 1, others => 0);
constant ddr2phy_has_custom: tech_ability_type :=
(easic45 => 1, others => 0);
constant ddr2phy_refclk_type: tech_ability_type :=
(virtex4 => 1, virtex5 => 1, virtex6 => 1, -- 1: 200 MHz reference
easic45 => 2, -- 2: 270 degree shifted clock
others => 0); -- 0: None
constant ddr2phy_has_datavalid: tech_ability_type :=
(easic45 => 1,
others => 0);
constant ddrphy_has_datavalid: tech_ability_type :=
(ut90 => 1, others => 0);
constant ddrphy_builtin_pads: tech_ability_type := (
inferred => 0,
-- Most techs have builtin pads for legacy reasons, can be converted if needed
others => 1);
constant ddrphy_latency: tech_ability_type := (
-- extra read latency, only used when not datavalid signal is available
inferred => 1,
others => 0
);
-- If the PHY passes through the control signals directly to the pads
-- and therefore needs them to be set asynchronously at reset
constant ddr2phy_ptctrl: tech_ability_type := (
inferred => 1, others => 0
);
constant ddrphy_ptctrl: tech_ability_type := (
inferred => 1, others => 0
);
constant has_syncreg: tech_ability_type := (
inferred => 0, others => 0);
-- pragma translate_off
subtype tech_description is string(1 to 10);
type tech_table_type is array (0 to NTECH) of tech_description;
-------------------------------------------------------------------------------
constant tech_table : tech_table_type := (
inferred => "inferred ", virtex => "virtex ",
virtex2 => "virtex2 ", memvirage => "virage ",
axcel => "axcel ", proasic => "proasic ",
atc18s => "atc18s ", altera => "altera ",
umc => "umc18 ", rhumc => "rhumc ",
apa3 => "proasic3 ", spartan3 => "spartan3 ",
ihp25 => "ihp25 ", rhlib18t => "rhlib18t ",
virtex4 => "virtex4 ", lattice => "lattice ",
ut25 => "ut025crh ", spartan3e => "spartan3e ",
peregrine => "peregrine ", memartisan => "artisan ",
virtex5 => "virtex5 ", custom1 => "custom1 ",
ihp25rh => "ihp25rh ", stratix1 => "stratix ",
stratix2 => "stratixii ", eclipse => "eclipse ",
stratix3 => "stratixiii", cyclone3 => "cycloneiii",
memvirage90 => "virage90 ", tsmc90 => "tsmc90 ",
easic90 => "nextreme ", atc18rha => "atc18rha ",
smic013 => "smic13 ", tm65gplus => "tm65gplus ",
axdsp => "axdsp ", spartan6 => "spartan6 ",
virtex6 => "virtex6 ", actfus => "fusion ",
stratix4 => "stratix4 ", st65lp => "st65lp ",
st65gp => "st65gp ", easic45 => "nextreme2 ",
cmos9sf => "cmos9sf ", apa3e => "proasic3e ",
apa3l => "proasic3l ", ut130 => "ut130hbd ",
ut90 => "ut90nhbd ", gf65 => "gf65g ",
virtex7 => "virtex7 ", kintex7 => "kintex7 ",
artix7 => "artix7 ", zynq7000 => "zynq7000 ",
rhlib13t => "rhlib13t ", saed32 => "saed32 ",
dare => "dare ");
-- pragma translate_on
-- input/output voltage
constant x12v : integer := 12;
constant x15v : integer := 15;
constant x18v : integer := 1;
constant x25v : integer := 2;
constant x33v : integer := 3;
constant x50v : integer := 5;
-- input/output levels
constant ttl : integer := 0;
constant cmos : integer := 1;
constant pci33 : integer := 2;
constant pci66 : integer := 3;
constant lvds : integer := 4;
constant sstl2_i : integer := 5;
constant sstl2_ii : integer := 6;
constant sstl3_i : integer := 7;
constant sstl3_ii : integer := 8;
constant sstl18_i : integer := 9;
constant sstl18_ii: integer := 10;
constant lvpecl : integer := 11;
constant sstl : integer := 12;
-- pad types
constant normal : integer := 0;
constant pullup : integer := 1;
constant pulldown : integer := 2;
constant opendrain: integer := 3;
constant schmitt : integer := 4;
constant dci : integer := 5;
---------------------------------------------------------------------------
-- MEMORY
---------------------------------------------------------------------------
-- testin vector is testen & scanen & (tech-dependent...)
constant TESTIN_WIDTH : integer := 4 + GRLIB_CONFIG_ARRAY(grlib_techmap_testin_extra);
constant testin_none : std_logic_vector(TESTIN_WIDTH-1 downto 0) := (others => '0');
-- synchronous single-port ram
component syncram
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
testen : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(custombits-1 downto 0));
end component;
-- synchronous two-port ram (1 read, 1 write port)
component syncram_2p
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0; testen : integer := 0;
words : integer := 0; custombits : integer := 1);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(custombits-1 downto 0));
end component;
-- synchronous dual-port ram (2 read/write ports)
component syncram_dp
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
testen : integer := 0; custombits : integer := 1);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(custombits-1 downto 0));
end component;
-- synchronous 3-port regfile (2 read, 1 write port)
component regfile_3p
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
wrfst : integer := 0; numregs : integer := 64; testen : integer := 0;
custombits : integer := 1);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
rclk : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(2*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(2*custombits-1 downto 0));
end component;
-- 64-bit synchronous single-port ram with 32-bit write strobe
component syncram64
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0;
paren : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63+8*paren downto 0);
dataout : out std_logic_vector (63+8*paren downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(2*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(2*custombits-1 downto 0));
end component;
-- 128-bit synchronous single-port ram with 32-bit write strobe
component syncram128
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0;
paren : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127+16*paren downto 0);
dataout : out std_logic_vector (127+16*paren downto 0);
enable : in std_logic_vector (3 downto 0);
write : in std_logic_vector (3 downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(4*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(4*custombits-1 downto 0));
end component;
component syncramft
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
ft : integer range 0 to 3 := 0; testen : integer := 0; custombits : integer := 1 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic;
enable : in std_ulogic;
error : out std_logic_vector(((dbits + 7) / 8)-1 downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none;
errinj : in std_logic_vector(((dbits + 7)/8)*2-1 downto 0) := (others => '0');
customclk: in std_ulogic := '0';
customin : in std_logic_vector(3*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(3*custombits-1 downto 0));
end component;
component syncram_2pft
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0; ft : integer := 0;
testen : integer := 0; words : integer := 0; custombits : integer := 1);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
error : out std_logic_vector(((dbits + 7) / 8)-1 downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(3*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(3*custombits-1 downto 0));
end component;
component syncram128bw
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(16*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(16*custombits-1 downto 0));
end component;
component syncram156bw
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (155 downto 0);
dataout : out std_logic_vector (155 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(20*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(20*custombits-1 downto 0));
end component;
component syncram256bw is
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (255 downto 0);
dataout : out std_logic_vector (255 downto 0);
enable : in std_logic_vector (31 downto 0);
write : in std_logic_vector (31 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(32*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(32*custombits-1 downto 0));
end component;
component syncrambw
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
testen : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits-1 downto 0);
datain : in std_logic_vector (dbits-1 downto 0);
dataout : out std_logic_vector (dbits-1 downto 0);
enable : in std_logic_vector (dbits/8-1 downto 0);
write : in std_logic_vector (dbits/8-1 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector((dbits/8)*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector((dbits/8)*custombits-1 downto 0));
end component;
component syncram_2pbw
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0; testen : integer := 0;
words : integer := 0; custombits : integer := 1);
port (
rclk : in std_ulogic;
renable : in std_logic_vector((dbits/8-1) downto 0);
raddress : in std_logic_vector((abits-1) downto 0);
dataout : out std_logic_vector((dbits-1) downto 0);
wclk : in std_ulogic;
write : in std_logic_vector((dbits/8-1) downto 0);
waddress : in std_logic_vector((abits-1) downto 0);
datain : in std_logic_vector((dbits-1) downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector((dbits/8)*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector((dbits/8)*custombits-1 downto 0));
end component;
component syncrambwft is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
ft : integer range 0 to 3 := 0; testen : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits-1 downto 0);
datain : in std_logic_vector (dbits-1 downto 0);
dataout : out std_logic_vector (dbits-1 downto 0);
enable : in std_logic_vector (dbits/8-1 downto 0);
write : in std_logic_vector (dbits/8-1 downto 0);
error : out std_logic_vector (dbits/8-1 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none;
errinj : in std_logic_vector((dbits/8)*2-1 downto 0) := (others => '0');
customclk : in std_ulogic := '0';
customin : in std_logic_vector(3*(dbits/8)*custombits-1 downto 0) := (others => '0');
customout : out std_logic_vector(3*(dbits/8)*custombits-1 downto 0));
end component;
component from is
generic (
timingcheckson: boolean := True;
instancepath: string := "*";
xon: boolean := False;
msgon: boolean := True;
data_x: integer := 1;
memoryfile: string := "";
progfile: string := "");
port (
clk: in std_ulogic;
addr: in std_logic_vector(6 downto 0);
data: out std_logic_vector(7 downto 0));
end component;
component syncfifo_2p is
generic (
tech : integer := 0;
abits : integer := 6;
dbits : integer := 8
);
port (
rclk : in std_logic;
renable : in std_logic;
rfull : out std_logic;
rempty : out std_logic;
rusedw : out std_logic_vector(abits-1 downto 0);
datain : in std_logic_vector(dbits-1 downto 0);
wclk : in std_logic;
write : in std_logic;
wfull : out std_logic;
wempty : out std_logic;
wusedw : out std_logic_vector(abits-1 downto 0);
dataout : out std_logic_vector(dbits-1 downto 0)
);
end component;
---------------------------------------------------------------------------
-- PADS
---------------------------------------------------------------------------
component inpad
generic (tech : integer := 0; level : integer := 0;
voltage : integer := x33v; filter : integer := 0;
strength : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component inpadv
generic (tech : integer := 0; level : integer := 0;
voltage : integer := x33v; width : integer := 1;
filter : integer := 0; strength : integer := 0);
port (
pad : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end component;
component iopad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0; filter : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component iopadv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0; filter : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
o : out std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component iopadvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0; filter : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000"
);
end component;
component iodpad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : inout std_ulogic; i : in std_ulogic; o : out std_ulogic);
end component;
component iodpadv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end component;
component outpad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : out std_ulogic; i : in std_ulogic;
cfgi : in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component outpadv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component odpad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component odpadv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component toutpad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component toutpadv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component toutpadvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component toutpad_ds
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
end component;
component toutpad_dsv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp : out std_logic_vector(width-1 downto 0);
padn : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic);
end component;
component toutpad_dsvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp : out std_logic_vector(width-1 downto 0);
padn : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0));
end component;
component skew_outpad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; skew : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic; rst : in std_ulogic;
o : out std_ulogic);
end component;
component clkpad
generic (tech : integer := 0; level : integer := 0;
voltage : integer := x33v; arch : integer := 0;
hf : integer := 0; filter : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic; rstn : std_ulogic := '1'; lock : out std_ulogic);
end component;
component inpad_ds
generic (tech : integer := 0; level : integer := lvds; voltage : integer := x33v; term : integer := 0);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component clkpad_ds
generic (tech : integer := 0; level : integer := lvds; voltage : integer := x33v; term : integer := 0);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component inpad_dsv
generic (tech : integer := 0; level : integer := lvds;
voltage : integer := x33v; width : integer := 1; term : integer := 0);
port (
padp : in std_logic_vector(width-1 downto 0);
padn : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end component;
component iopad_ds
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0; term : integer := 0);
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component iopad_dsv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp, padn : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
o : out std_logic_vector(width-1 downto 0));
end component;
component iopad_dsvv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp, padn : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end component;
component outpad_ds
generic (tech : integer := 0; level : integer := lvds;
voltage : integer := x33v; oepol : integer := 0; slew : integer := 0);
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
end component;
component outpad_dsv
generic (tech : integer := 0; level : integer := lvds;
voltage : integer := x33v; width : integer := 1; slew : integer := 0);
port (
padp : out std_logic_vector(width-1 downto 0);
padn : out std_logic_vector(width-1 downto 0);
i, en: in std_logic_vector(width-1 downto 0));
end component;
component lvds_combo is
generic (tech : integer := 0; voltage : integer := 0; width : integer := 1;
oepol : integer := 0; term : integer := 0);
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
odval, osval, en : in std_logic_vector(0 to width-1);
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
idval, isval : out std_logic_vector(0 to width-1);
powerdown : in std_logic_vector(0 to width-1) := (others => '0');
powerdownrx : in std_logic_vector(0 to width-1) := (others => '0');
lvdsref : in std_logic := '1'; lvdsrefo : out std_logic
);
end component;
-------------------------------------------------------------------------------
-- DDR PADS (bundles PAD and DDR register(s))
-------------------------------------------------------------------------------
component inpad_ddr
generic (tech : integer := 0; level : integer := 0; voltage : integer := x33v;
filter : integer := 0; strength : integer := 0 );
port (pad : in std_ulogic; o1, o2 : out std_ulogic; c1, c2 : in std_ulogic;
ce : in std_ulogic; r : in std_ulogic; s : in std_ulogic);
end component;
component inpad_ddrv
generic (tech : integer := 0; level : integer := 0; voltage : integer := 0;
filter : integer := 0; strength : integer := 0; width : integer := 1);
port (pad : in std_logic_vector(width-1 downto 0);
o1, o2 : out std_logic_vector(width-1 downto 0); c1, c2 : in std_ulogic;
ce : in std_ulogic; r: in std_ulogic; s : in std_ulogic);
end component;
component outpad_ddr
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : out std_ulogic; i1, i2 : in std_ulogic; c1, c2 : in std_ulogic;
ce : in std_ulogic; r : in std_ulogic; s : in std_ulogic);
end component;
component outpad_ddrv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 12;
width : integer := 1);
port (pad : out std_logic_vector(width-1 downto 0);
i1, i2 : in std_logic_vector(width-1 downto 0);
c1, c2 : in std_ulogic; ce : in std_ulogic;
r : in std_ulogic; s : in std_ulogic);
end component;
component iopad_ddr
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : inout std_ulogic; i1, i2 : in std_ulogic; en : in std_ulogic;
o1, o2 : out std_ulogic; c1, c2 : in std_ulogic; ce : in std_ulogic;
r : in std_ulogic; s : in std_ulogic);
end component;
component iopad_ddrv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (pad : inout std_logic_vector(width-1 downto 0);
i1, i2 : in std_logic_vector(width-1 downto 0); en : in std_ulogic;
o1, o2 : out std_logic_vector(width-1 downto 0); c1, c2 : in std_ulogic;
ce : in std_ulogic; r : in std_ulogic; s : in std_ulogic);
end component;
component iopad_ddrvv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (pad : inout std_logic_vector(width-1 downto 0);
i1, i2 : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o1, o2 : out std_logic_vector(width-1 downto 0); c1, c2 : in std_ulogic;
ce : in std_ulogic; r : in std_ulogic; s : in std_ulogic);
end component;
---------------------------------------------------------------------------
-- BUFFERS
---------------------------------------------------------------------------
component techbuf is
generic(
buftype : integer range 0 to 6 := 0;
tech : integer range 0 to NTECH := inferred);
port(
i : in std_ulogic;
o : out std_ulogic
);
end component;
---------------------------------------------------------------------------
-- CLOCK GENERATION
---------------------------------------------------------------------------
type clkgen_in_type is record
pllref : std_logic; -- optional reference for PLL
pllrst : std_logic; -- optional reset for PLL
pllctrl : std_logic_vector(1 downto 0); -- optional control for PLL
clksel : std_logic_vector(1 downto 0); -- optional clock select
end record;
type clkgen_out_type is record
clklock : std_logic;
pcilock : std_logic;
end record;
component clkgen
generic (
tech : integer := DEFFABTECH;
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 1;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
clksel : integer := 0; -- enable clock select
clk_odiv : integer := 1; -- Proasic3/Fusion output divider clkA
clkb_odiv: integer := 0; -- Proasic3/Fusion output divider clkB
clkc_odiv: integer := 0); -- Proasic3/Fusion output divider clkC
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- 2x clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk4x : out std_logic; -- 4x clock
clk1xu : out std_logic; -- unscaled 1X clock
clk2xu : out std_logic; -- unscaled 2X clock
clkb : out std_logic; -- Proasic3/Fusion clkB
clkc : out std_logic; -- Proasic3/Fusion clkC
clk8x : out std_logic); -- 8x clock
end component;
component clkand
generic( tech : integer := 0;
ren : integer range 0 to 1 := 0); -- registered enable
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic := '0'
);
end component;
component clkmux
generic( tech : integer := 0;
rsel : integer range 0 to 1 := 0); -- registered sel
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic;
rst : in std_ulogic := '1'
);
end component;
component clkinv
generic( tech : integer := 0);
port(
i : in std_ulogic;
o : out std_ulogic
);
end component;
component clkrand is
generic( tech : integer := 0);
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic := '0'
);
end component;
---------------------------------------------------------------------------
-- TAP controller and boundary scan
---------------------------------------------------------------------------
component tap
generic (
tech : integer := 0;
irlen : integer range 2 to 8 := 4;
idcode : integer range 0 to 255 := 9;
manf : integer range 0 to 2047 := 804;
part : integer range 0 to 65535 := 0;
ver : integer range 0 to 15 := 0;
trsten : integer range 0 to 1 := 1;
scantest : integer := 0;
oepol : integer := 1;
tcknen : integer := 0);
port (
trst : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic;
tapi_en1 : in std_ulogic;
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_ninst : out std_logic_vector(7 downto 0);
tapo_iupd : out std_ulogic;
tapo_tckn : out std_ulogic;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1';
testoen : in std_ulogic := '0';
tdoen : out std_ulogic;
tckn : in std_ulogic := '0'
);
end component;
component scanregi
generic (
tech : integer := 0;
intesten: integer := 1
);
port (
pad : in std_ulogic;
core : out std_ulogic;
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic; -- capture signal to scan reg on next tck edge
bsupd : in std_ulogic; -- update data reg from scan reg on next tck edge
bsdrive : in std_ulogic; -- drive data reg to core
bshighz : in std_ulogic
);
end component;
component scanrego
generic (
tech : integer := 0
);
port (
pad : out std_ulogic;
core : in std_ulogic;
samp : in std_ulogic; -- normally same as core unless outpad has feedback
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic; -- capture signal to scan reg on next tck edge
bsupd : in std_ulogic; -- update data reg from scan reg on next tck edge
bsdrive : in std_ulogic -- drive data reg to pad
);
end component;
component scanregto -- 2 scan registers: tdo<---output<--outputen<--tdi
generic (
tech : integer := 0;
hzsup: integer range 0 to 1 := 1;
oepol: integer range 0 to 1 := 1
);
port (
pado : out std_ulogic;
padoen : out std_ulogic;
samp : in std_ulogic; -- normally same as core unless outpad has feedback
coreo : in std_ulogic;
coreoen : in std_ulogic;
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic; -- capture signal to scan reg on next tck edge
bsupdo : in std_ulogic; -- update data reg from scan reg on next tck edge
bsdrive : in std_ulogic; -- drive data reg to pad
bshighz : in std_ulogic -- tri-state output
);
end component;
component scanregio -- 3 scan registers: tdo<--input<--output<--outputen<--tdi
generic (
tech : integer := 0;
hzsup: integer range 0 to 1 := 1;
oepol: integer range 0 to 1 := 1;
intesten: integer range 0 to 1 := 1
);
port (
pado : out std_ulogic;
padoen : out std_ulogic;
padi : in std_ulogic;
coreo : in std_ulogic;
coreoen : in std_ulogic;
corei : out std_ulogic;
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic; -- capture signals to scan regs on next tck edge
bsupdi : in std_ulogic; -- update indata reg from scan reg on next tck edge
bsupdo : in std_ulogic; -- update outdata reg from scan reg on next tck edge
bsdrive : in std_ulogic; -- drive outdata regs to pad,
-- drive datareg(coreoen=0) or coreo(coreoen=1) to corei
bshighz : in std_ulogic -- tri-state output
);
end component;
---------------------------------------------------------------------------
-- DDR registers and PHY
---------------------------------------------------------------------------
component ddr_ireg is
generic ( tech : integer; arch : integer := 0);
port ( Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component ddr_oreg is generic (tech : integer; arch : integer := 0);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component ddrphy
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2 ; clk_div : integer := 2;
rskew : integer :=0; mobile : integer := 0;
abits: integer := 14; nclk: integer := 3; ncs: integer := 2;
scantest : integer := 0; phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkread : out std_ulogic; -- read clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
ck : in std_logic_vector(2 downto 0);
moben : in std_logic;
dqvalid : out std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
component ddrphy_wo_pads
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2; clk_div : integer := 2;
rskew : integer := 0; mobile: integer := 0;
abits : integer := 14; nclk: integer := 3; ncs: integer := 2;
scantest : integer := 0; phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock returned
clkread : out std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector (1 downto 0);
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
ck : in std_logic_vector(2 downto 0);
moben : in std_logic;
dqvalid : out std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
component ddr2phy
generic (
tech : integer := virtex5; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
ddelayb8 : integer := 0;
ddelayb9 : integer := 0; ddelayb10: integer := 0; ddelayb11: integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0; rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0; dqsse : integer range 0 to 1 := 0;
abits : integer := 14; nclk: integer := 3; ncs: integer := 2;
ctrl2en: integer := 0; resync: integer := 0; custombits: integer := 8; extraio: integer := 0;
scantest : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref : in std_logic; -- input reference clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkresync : in std_ulogic; -- resync clock (if resync/=0)
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (extraio+dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector ( 2 downto 0);
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
noen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_pll : in std_logic_vector(1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(ncs-1 downto 0);
oct : in std_logic;
read_pend : in std_logic_vector(7 downto 0);
regwdata : in std_logic_vector(63 downto 0);
regwrite : in std_logic_vector(1 downto 0);
regrdata : out std_logic_vector(63 downto 0);
dqin_valid : out std_ulogic;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
-- Copy of control signals for 2nd DIMM
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
component ddr2phy_wo_pads
generic (tech : integer := virtex5; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
ddelayb8: integer := 0;
ddelayb9: integer := 0; ddelayb10: integer := 0; ddelayb11: integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0; rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0; dqsse : integer range 0 to 1 := 0;
abits : integer := 14; nclk: integer := 3; ncs: integer := 2;
resync : integer := 0; custombits: integer := 8; scantest: integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock returned
clkresync : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector ( 2 downto 0);
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
noen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_pll : in std_logic_vector(1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(ncs-1 downto 0);
oct : in std_logic;
read_pend : in std_logic_vector(7 downto 0);
regwdata : in std_logic_vector(63 downto 0);
regwrite : in std_logic_vector(1 downto 0);
regrdata : out std_logic_vector(63 downto 0);
dqin_valid : out std_ulogic;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
component lpddr2phy_wo_pads
generic (
tech : integer := virtex5;
dbits : integer := 16;
nclk: integer := 3;
ncs: integer := 2;
clkratio: integer := 1;
scantest: integer := 0);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
clkin2 : in std_ulogic;
clkout : out std_ulogic;
clkoutret : in std_ulogic; -- ckkout returned
clkout2 : out std_ulogic;
lock : out std_ulogic;
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_ca : out std_logic_vector(9 downto 0);
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ca : in std_logic_vector (10*2*clkratio-1 downto 0);
cke : in std_logic_vector (ncs*clkratio-1 downto 0);
csn : in std_logic_vector (ncs*clkratio-1 downto 0);
dqin : out std_logic_vector (dbits*2*clkratio-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2*clkratio-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4*clkratio-1 downto 0); -- data mask
ckstop : in std_ulogic;
boot : in std_ulogic;
wrpend : in std_logic_vector(7 downto 0);
rdpend : in std_logic_vector(7 downto 0);
wrreq : out std_logic_vector(clkratio-1 downto 0);
rdvalid : out std_logic_vector(clkratio-1 downto 0);
refcal : in std_ulogic;
refcalwu : in std_ulogic;
refcaldone : out std_ulogic;
phycmd : in std_logic_vector(7 downto 0);
phycmden : in std_ulogic;
phycmdin : in std_logic_vector(31 downto 0);
phycmdout : out std_logic_vector(31 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
component ddr2pads is
generic (tech: integer := virtex5;
dbits: integer := 16;
eightbanks: integer := 0;
dqsse: integer range 0 to 1 := 0;
abits: integer := 14;
nclk: integer := 3;
ncs: integer := 2;
ctrl2en: integer := 0);
port (
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
-- Copy of control signals for 2nd DIMM (if ctrl2en /= 0)
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
lddr_clk : in std_logic_vector(nclk-1 downto 0);
lddr_clkb : in std_logic_vector(nclk-1 downto 0);
lddr_clk_fb_out : in std_logic;
lddr_clk_fb : out std_logic;
lddr_cke : in std_logic_vector(ncs-1 downto 0);
lddr_csb : in std_logic_vector(ncs-1 downto 0);
lddr_web : in std_ulogic; -- ddr write enable
lddr_rasb : in std_ulogic; -- ddr ras
lddr_casb : in std_ulogic; -- ddr cas
lddr_dm : in std_logic_vector (dbits/8-1 downto 0); -- ddr dm
lddr_dqs_in : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_dqs_out : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_dqs_oen : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_ad : in std_logic_vector (abits-1 downto 0); -- ddr address
lddr_ba : in std_logic_vector (1+eightbanks downto 0); -- ddr bank address
lddr_dq_in : out std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_dq_out : in std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_dq_oen : in std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_odt : in std_logic_vector(ncs-1 downto 0)
);
end component;
component ddrpads is
generic (tech: integer := virtex5;
dbits: integer := 16;
abits: integer := 14;
nclk: integer := 3;
ncs: integer := 2;
ctrl2en: integer := 0);
port (
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
-- Copy of control signals for 2nd DIMM (if ctrl2en /= 0)
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1 downto 0); -- ddr bank address
lddr_clk : in std_logic_vector(nclk-1 downto 0);
lddr_clkb : in std_logic_vector(nclk-1 downto 0);
lddr_clk_fb_out : in std_logic;
lddr_clk_fb : out std_logic;
lddr_cke : in std_logic_vector(ncs-1 downto 0);
lddr_csb : in std_logic_vector(ncs-1 downto 0);
lddr_web : in std_ulogic; -- ddr write enable
lddr_rasb : in std_ulogic; -- ddr ras
lddr_casb : in std_ulogic; -- ddr cas
lddr_dm : in std_logic_vector (dbits/8-1 downto 0); -- ddr dm
lddr_dqs_in : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_dqs_out : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_dqs_oen : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_ad : in std_logic_vector (abits-1 downto 0); -- ddr address
lddr_ba : in std_logic_vector (1 downto 0); -- ddr bank address
lddr_dq_in : out std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_dq_out : in std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_dq_oen : in std_logic_vector (dbits-1 downto 0) -- ddr data
);
end component;
component ddrphy_datapath is
generic (
regtech: integer := 0;
dbits: integer;
abits: integer;
bankbits: integer range 2 to 3 := 2;
ncs: integer;
nclk: integer;
resync: integer range 0 to 2 := 0
);
port (
clk0: in std_ulogic;
clk90: in std_ulogic;
clk180: in std_ulogic;
clk270: in std_ulogic;
clkresync: in std_ulogic;
ddr_clk: out std_logic_vector(nclk-1 downto 0);
ddr_clkb: out std_logic_vector(nclk-1 downto 0);
ddr_dq_in: in std_logic_vector(dbits-1 downto 0);
ddr_dq_out: out std_logic_vector(dbits-1 downto 0);
ddr_dq_oen: out std_logic_vector(dbits-1 downto 0);
ddr_dqs_in90: in std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_in90n: in std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_out: out std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_oen: out std_logic_vector(dbits/8-1 downto 0);
ddr_cke: out std_logic_vector(ncs-1 downto 0);
ddr_csb: out std_logic_vector(ncs-1 downto 0);
ddr_web: out std_ulogic;
ddr_rasb: out std_ulogic;
ddr_casb: out std_ulogic;
ddr_ad: out std_logic_vector(abits-1 downto 0);
ddr_ba: out std_logic_vector(bankbits-1 downto 0);
ddr_dm: out std_logic_vector(dbits/8-1 downto 0);
ddr_odt: out std_logic_vector(ncs-1 downto 0);
dqin: out std_logic_vector(dbits*2-1 downto 0);
dqout: in std_logic_vector(dbits*2-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector (bankbits-1 downto 0);
dm : in std_logic_vector (dbits/4-1 downto 0);
oen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
odt : in std_logic_vector(ncs-1 downto 0);
dqs_en : in std_ulogic;
dqs_oen : in std_ulogic;
ddrclk_en : in std_logic_vector(nclk-1 downto 0)
);
end component;
---------------------------------------------------------------------------
-- 61x61 Multiplier
---------------------------------------------------------------------------
component mul_61x61
generic (multech : integer := 0;
fabtech : integer := 0);
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
---------------------------------------------------------------------------
-- Ring oscillator
---------------------------------------------------------------------------
component ringosc
generic (tech : integer := 0);
port (
roen : in Std_ULogic;
roout : out Std_ULogic);
end component;
---------------------------------------------------------------------------
-- System monitor
---------------------------------------------------------------------------
component system_monitor
generic (
-- GRLIB generics
tech : integer := DEFFABTECH;
-- Virtex 5 SYSMON generics
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "design.txt");
port (
alm : out std_logic_vector(2 downto 0);
busy : out std_ulogic;
channel : out std_logic_vector(4 downto 0);
do : out std_logic_vector(15 downto 0);
drdy : out std_ulogic;
eoc : out std_ulogic;
eos : out std_ulogic;
jtagbusy : out std_ulogic;
jtaglocked : out std_ulogic;
jtagmodified : out std_ulogic;
ot : out std_ulogic;
convst : in std_ulogic;
convstclk : in std_ulogic;
daddr : in std_logic_vector(6 downto 0);
dclk : in std_ulogic;
den : in std_ulogic;
di : in std_logic_vector(15 downto 0);
dwe : in std_ulogic;
reset : in std_ulogic;
vauxn : in std_logic_vector(15 downto 0);
vauxp : in std_logic_vector(15 downto 0);
vn : in std_ulogic;
vp : in std_ulogic);
end component;
component nandtree
generic(
tech : integer := inferred;
width : integer := 2;
imp : integer := 0 );
port( i : in std_logic_vector(width-1 downto 0);
o : out std_ulogic;
en : in std_ulogic
);
end component;
component grmux2 is generic( tech : integer := inferred; imp : integer := 0);
port( ip0, ip1, sel : in std_logic; op : out std_ulogic); end component;
component grmux2v is generic( tech : integer := inferred; bits : integer := 2; imp : integer := 0);
port( ip0, ip1 : in std_logic_vector(bits-1 downto 0);
sel : in std_logic; op : out std_logic_vector(bits-1 downto 0));
end component;
component grdff is generic( tech : integer := inferred; imp : integer := 0);
port( clk, d : in std_ulogic; q : out std_ulogic); end component;
component gror2 is generic( tech : integer := inferred; imp : integer := 0);
port( i0, i1 : in std_ulogic; q : out std_ulogic); end component;
component grand12 is generic( tech : integer := inferred; imp : integer := 0);
port( i0, i1 : in std_ulogic; q : out std_ulogic); end component;
component grnand2 is generic (tech: integer := inferred; imp: integer := 0);
port( i0, i1 : in std_ulogic; q : out std_ulogic); end component;
component techmult
generic (
tech : integer := 0;
arch : integer := 0;
a_width : positive := 2; -- multiplier word width
b_width : positive := 2; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1 -- '0': non-stallable; '1': stallable
);
port(a : in std_logic_vector(a_width-1 downto 0);
b : in std_logic_vector(b_width-1 downto 0);
clk : in std_logic;
en : in std_logic;
sign : in std_logic;
product : out std_logic_vector(a_width+b_width-1 downto 0));
end component;
component syncreg
generic (
tech : integer := 0;
stages : integer range 1 to 5 := 2
);
port (
clk : in std_ulogic;
d : in std_ulogic;
q : out std_ulogic
);
end component;
-------------------------------------------------------------------------------
-- SDRAM PHY
-------------------------------------------------------------------------------
component sdram_phy
generic (
tech : integer := spartan3;
oepol : integer := 0;
level : integer := 0;
voltage : integer := x33v;
strength : integer := 12;
aw : integer := 15; -- # address bits
dw : integer := 32; -- # data bits
ncs : integer := 2;
reg : integer := 0); -- 1: include registers on all signals
port (
-- SDRAM interface
addr : out std_logic_vector(aw-1 downto 0);
dq : inout std_logic_vector(dw-1 downto 0);
cke : out std_logic_vector(ncs-1 downto 0);
sn : out std_logic_vector(ncs-1 downto 0);
wen : out std_ulogic;
rasn : out std_ulogic;
casn : out std_ulogic;
dqm : out std_logic_vector(dw/8-1 downto 0);
-- Interface toward memory controller
laddr : in std_logic_vector(aw-1 downto 0);
ldq_din : out std_logic_vector(dw-1 downto 0);
ldq_dout : in std_logic_vector(dw-1 downto 0);
ldq_oen : in std_logic_vector(dw-1 downto 0);
lcke : in std_logic_vector(ncs-1 downto 0);
lsn : in std_logic_vector(ncs-1 downto 0);
lwen : in std_ulogic;
lrasn : in std_ulogic;
lcasn : in std_ulogic;
ldqm : in std_logic_vector(dw/8-1 downto 0);
-- Only used when reg generic is non-zero
rstn : in std_ulogic; -- Registered pads reset
clk : in std_ulogic; -- SDRAM clock for registered pads
-- Optional pad configuration inputs
cfgi_cmd : in std_logic_vector(19 downto 0) := "00000000000000000000"; -- CMD pads
cfgi_dq : in std_logic_vector(19 downto 0) := "00000000000000000000" -- DQ pads
);
end component;
-------------------------------------------------------------------------------
-- GIGABIT ETHERNET SERDES
-------------------------------------------------------------------------------
component serdes is
generic (
tech : integer
);
port (
clk_125 : in std_logic;
rst_125 : in std_logic;
rx_in : in std_logic; -- SER IN
rx_out : out std_logic_vector(9 downto 0); -- PAR OUT
rx_clk : out std_logic;
rx_rstn : out std_logic;
rx_pll_clk : out std_logic;
rx_pll_rstn : out std_logic;
tx_pll_clk : out std_logic;
tx_pll_rstn : out std_logic;
tx_in : in std_logic_vector(9 downto 0) ; -- PAR IN
tx_out : out std_logic; -- SER OUT
bitslip : in std_logic
);
end component;
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/l2cache/l2c.in.vhd | 3 | 638 | -- L2 Cache
constant CFG_L2_EN : integer := CONFIG_L2_ENABLE;
constant CFG_L2_SIZE : integer := CFG_L2_SZ;
constant CFG_L2_WAYS : integer := CFG_L2_ASSO;
constant CFG_L2_HPROT : integer := CONFIG_L2_HPROT;
constant CFG_L2_PEN : integer := CONFIG_L2_PEN;
constant CFG_L2_WT : integer := CONFIG_L2_WT;
constant CFG_L2_RAN : integer := CONFIG_L2_RAN;
constant CFG_L2_SHARE : integer := CONFIG_L2_SHARE;
constant CFG_L2_LSZ : integer := CFG_L2_LINE;
constant CFG_L2_MAP : integer := 16#CONFIG_L2_MAP#;
constant CFG_L2_MTRR : integer := CONFIG_L2_MTRR;
constant CFG_L2_EDAC : integer := CONFIG_L2_EDAC;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-asic/bschain.vhd | 1 | 11906 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013, Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.jtag.all;
use work.config.all;
entity bschain is
generic (tech: integer := CFG_FABTECH;
enable: integer range 0 to 1 := CFG_BOUNDSCAN_EN;
hzsup: integer range 0 to 1 := 1);
port (
-- Chain control signals
chain_tck : in std_ulogic;
chain_tckn : in std_ulogic;
chain_tdi : in std_ulogic;
chain_tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic;
bsupdi : in std_ulogic;
bsupdo : in std_ulogic;
bsdrive : in std_ulogic;
bshighz : in std_ulogic;
-- Pad-side signals
Presetn : in std_ulogic;
Pclksel : in std_logic_vector (1 downto 0);
Pclk : in std_ulogic;
Perrorn : out std_ulogic;
Paddress : out std_logic_vector(27 downto 0);
Pdatain : in std_logic_vector(31 downto 0);
Pdataout : out std_logic_vector(31 downto 0);
Pdataen : out std_logic_vector(31 downto 0);
Pcbin : in std_logic_vector(7 downto 0);
Pcbout : out std_logic_vector(7 downto 0);
Pcben : out std_logic_vector(7 downto 0);
Psdclk : out std_ulogic;
Psdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
Psdwen : out std_ulogic; -- sdram write enable
Psdrasn : out std_ulogic; -- sdram ras
Psdcasn : out std_ulogic; -- sdram cas
Psddqm : out std_logic_vector (3 downto 0); -- sdram dqm
Pdsutx : out std_ulogic; -- DSU tx data
Pdsurx : in std_ulogic; -- DSU rx data
Pdsuen : in std_ulogic;
Pdsubre : in std_ulogic;
Pdsuact : out std_ulogic;
Ptxd1 : out std_ulogic; -- UART1 tx data
Prxd1 : in std_ulogic; -- UART1 rx data
Ptxd2 : out std_ulogic; -- UART2 tx data
Prxd2 : in std_ulogic; -- UART2 rx data
Pramsn : out std_logic_vector (4 downto 0);
Pramoen : out std_logic_vector (4 downto 0);
Prwen : out std_logic_vector (3 downto 0);
Poen : out std_ulogic;
Pwriten : out std_ulogic;
Pread : out std_ulogic;
Piosn : out std_ulogic;
Promsn : out std_logic_vector (1 downto 0);
Pbrdyn : in std_ulogic;
Pbexcn : in std_ulogic;
Pwdogn : out std_ulogic;
Pgpioin : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
Pgpioout : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
Pgpioen : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
Pprom32 : in std_ulogic;
Ppromedac : in std_ulogic;
Pspw_clksel : in std_logic_vector (1 downto 0);
Pspw_clk : in std_ulogic;
Pspw_rxd : in std_logic_vector(0 to CFG_SPW_NUM-1);
Pspw_rxs : in std_logic_vector(0 to CFG_SPW_NUM-1);
Pspw_txd : out std_logic_vector(0 to CFG_SPW_NUM-1);
Pspw_txs : out std_logic_vector(0 to CFG_SPW_NUM-1);
Pspw_ten : out std_logic_vector(0 to CFG_SPW_NUM-1);
Plclk2x : in std_ulogic;
Plclk4x : in std_ulogic;
Plclkdis : out std_ulogic;
Plclklock : in std_ulogic;
Plock : out std_ulogic;
Proen : in std_ulogic;
Proout : out std_ulogic;
-- Core-side signals
Cresetn : out std_ulogic;
Cclksel : out std_logic_vector (1 downto 0);
Cclk : out std_ulogic;
Cerrorn : in std_ulogic;
Caddress : in std_logic_vector(27 downto 0);
Cdatain : out std_logic_vector(31 downto 0);
Cdataout : in std_logic_vector(31 downto 0);
Cdataen : in std_logic_vector(31 downto 0);
Ccbin : out std_logic_vector(7 downto 0);
Ccbout : in std_logic_vector(7 downto 0);
Ccben : in std_logic_vector(7 downto 0);
Csdclk : in std_ulogic;
Csdcsn : in std_logic_vector (1 downto 0); -- sdram chip select
Csdwen : in std_ulogic; -- sdram write enable
Csdrasn : in std_ulogic; -- sdram ras
Csdcasn : in std_ulogic; -- sdram cas
Csddqm : in std_logic_vector (3 downto 0); -- sdram dqm
Cdsutx : in std_ulogic; -- DSU tx data
Cdsurx : out std_ulogic; -- DSU rx data
Cdsuen : out std_ulogic;
Cdsubre : out std_ulogic;
Cdsuact : in std_ulogic;
Ctxd1 : in std_ulogic; -- UART1 tx data
Crxd1 : out std_ulogic; -- UART1 rx data
Ctxd2 : in std_ulogic; -- UART2 tx data
Crxd2 : out std_ulogic; -- UART2 rx data
Cramsn : in std_logic_vector (4 downto 0);
Cramoen : in std_logic_vector (4 downto 0);
Crwen : in std_logic_vector (3 downto 0);
Coen : in std_ulogic;
Cwriten : in std_ulogic;
Cread : in std_ulogic;
Ciosn : in std_ulogic;
Cromsn : in std_logic_vector (1 downto 0);
Cbrdyn : out std_ulogic;
Cbexcn : out std_ulogic;
Cwdogn : in std_ulogic;
Cgpioin : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
Cgpioout : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
Cgpioen : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
Cprom32 : out std_ulogic;
Cpromedac : out std_ulogic;
Cspw_clksel : out std_logic_vector (1 downto 0);
Cspw_clk : out std_ulogic;
Cspw_rxd : out std_logic_vector(0 to CFG_SPW_NUM-1);
Cspw_rxs : out std_logic_vector(0 to CFG_SPW_NUM-1);
Cspw_txd : in std_logic_vector(0 to CFG_SPW_NUM-1);
Cspw_txs : in std_logic_vector(0 to CFG_SPW_NUM-1);
Cspw_ten : in std_logic_vector(0 to CFG_SPW_NUM-1);
Clclk2x : out std_ulogic;
Clclk4x : out std_ulogic;
Clclkdis : in std_ulogic;
Clclklock : out std_ulogic;
Clock : in std_ulogic;
Croen : out std_ulogic;
Croout : in std_ulogic
);
end;
architecture rtl of bschain is
signal sr1_tdi, sr1a_tdi, sr2a_tdi, sr2_tdi, sr3a_tdi, sr3_tdi, sr4_tdi: std_ulogic;
signal sr1i, sr1o: std_logic_vector(4 downto 0);
signal sr3i, sr3o: std_logic_vector(41 downto 0);
signal sr5i, sr5o: std_logic_vector(11+5*CFG_SPW_NUM downto 0);
begin
-----------------------------------------------------------------------------
-- Scan chain registers (note: adjust order to match pad ring)
sr1a: bscanregs
generic map (tech => tech, nsigs => sr1i'length, dirmask => 2#00001#, enable => enable)
port map (sr1i, sr1o, chain_tck, chain_tckn, sr1a_tdi, chain_tdo,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr1i <= Presetn & Pclksel & Pclk & Cerrorn;
Cresetn <= sr1o(4); Cclksel <= sr1o(3 downto 2);
Cclk <= sr1o(1); Perrorn <= sr1o(0);
sr1b: bscanregs
generic map (tech => tech, nsigs => Paddress'length, dirmask => 16#3FFFFFFF#, enable => enable)
port map (Caddress, Paddress, chain_tck, chain_tckn, sr1_tdi, sr1a_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr2a: bscanregsbd
generic map (tech => tech, nsigs => Pdataout'length, enable => enable, hzsup => hzsup)
port map (Pdataout, Pdataen, Pdatain, Cdataout, Cdataen, Cdatain,
chain_tck, chain_tckn, sr2a_tdi, sr1_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr2b: bscanregsbd
generic map (tech => tech, nsigs => Pcbout'length, enable => enable, hzsup => hzsup)
port map (Pcbout, Pcben, Pcbin, Ccbout, Ccben, Ccbin,
chain_tck, chain_tckn, sr2_tdi, sr2a_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr3a: bscanregs
generic map (tech => tech, nsigs => sr3i'length-30, dirmask => 2#11_11111111_10#, enable => enable)
port map (sr3i(sr3i'high downto 30), sr3o(sr3i'high downto 30), chain_tck, chain_tckn, sr3a_tdi, sr2_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr3b: bscanregs
generic map (tech => tech, nsigs => 30, dirmask => 2#001101_01111111_11111111_11111001#, enable => enable)
port map (sr3i(29 downto 0), sr3o(29 downto 0), chain_tck, chain_tckn, sr3_tdi, sr3a_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr3i(41 downto 30) <= Csdclk & Csdcsn & Csdwen & Csdrasn & Csdcasn &
Csddqm & Cdsutx & Pdsurx;
sr3i(29 downto 23) <= Pdsuen & Pdsubre & Cdsuact & Ctxd1 & Prxd1 & Ctxd2 & Prxd2;
sr3i(22 downto 9) <= Cramsn & Cramoen & Crwen;
sr3i(8 downto 0) <= Coen & Cwriten & Cread & Ciosn & Cromsn(1 downto 0) & Pbrdyn & Pbexcn & Cwdogn;
Psdclk <= sr3o(41); Psdcsn <= sr3o(40 downto 39); Psdwen <= sr3o(38);
Psdrasn <= sr3o(37); Psdcasn <= sr3o(36); Psddqm <= sr3o(35 downto 32);
Pdsutx <= sr3o(31); Cdsurx <= sr3o(30); Cdsuen <= sr3o(29);
Cdsubre <= sr3o(28); Pdsuact <= sr3o(27); Ptxd1 <= sr3o(26);
Crxd1 <= sr3o(25); Ptxd2 <= sr3o(24); Crxd2 <= sr3o(23);
Pramsn <= sr3o(22 downto 18); Pramoen <= sr3o(17 downto 13); Prwen <= sr3o(12 downto 9);
Poen <= sr3o(8); Pwriten <= sr3o(7); Pread <= sr3o(6);
Piosn <= sr3o(5); Promsn <= sr3o(4 downto 3); Cbrdyn <= sr3o(2);
Cbexcn <= sr3o(1); Pwdogn <= sr3o(0);
sr4: bscanregsbd
generic map (tech => tech, nsigs => Pgpioin'length, enable => enable, hzsup => hzsup)
port map (Pgpioout, Pgpioen, Pgpioin, Cgpioout, Cgpioen, Cgpioin,
chain_tck, chain_tckn, sr4_tdi, sr3_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr5: bscanregs
generic map (tech => tech, nsigs => sr5i'length, dirmask => 2#00000011_10010101#, enable => enable)
port map (sr5i, sr5o, chain_tck, chain_tckn, chain_tdi, sr4_tdi,
bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz);
sr5i <= Pprom32 & Ppromedac & Pspw_clksel & Pspw_clk & Pspw_rxd & Pspw_rxs &
Cspw_txd & Cspw_txs & Cspw_ten & Plclk2x & Plclk4x &
Clclkdis & Plclklock & Clock & Proen & Croout;
Cprom32 <= sr5o(11+5*CFG_SPW_NUM);
Cpromedac <= sr5o(10+5*CFG_SPW_NUM);
Cspw_clksel <= sr5o(9+5*CFG_SPW_NUM downto 8+5*CFG_SPW_NUM);
Cspw_clk <= sr5o(7+5*CFG_SPW_NUM);
Cspw_rxd <= sr5o(6+5*CFG_SPW_NUM downto 7+4*CFG_SPW_NUM);
Cspw_rxs <= sr5o(6+4*CFG_SPW_NUM downto 7+3*CFG_SPW_NUM);
Pspw_txd <= sr5o(6+3*CFG_SPW_NUM downto 7+2*CFG_SPW_NUM);
Pspw_txs <= sr5o(6+2*CFG_SPW_NUM downto 7+CFG_SPW_NUM);
Pspw_ten <= sr5o(6+CFG_SPW_NUM downto 7);
Clclk2x <= sr5o(6);
Clclk4x <= sr5o(5);
Plclkdis <= sr5o(4);
Clclklock <= sr5o(3);
Plock <= sr5o(2);
Croen <= sr5o(1);
Proout <= sr5o(0);
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-terasic-de4/ddr2sim.vhd | 1 | 10025 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
entity ddr2ctrl is
port (
pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk
global_reset_n : in std_logic := '0'; -- global_reset.reset_n
soft_reset_n : in std_logic := '0'; -- soft_reset.reset_n
afi_clk : out std_logic; -- afi_clk.clk
afi_half_clk : out std_logic; -- afi_half_clk.clk
afi_reset_n : out std_logic; -- afi_reset.reset_n
afi_reset_export_n : out std_logic; -- afi_reset_export.reset_n
mem_a : out std_logic_vector(13 downto 0); -- memory.mem_a
mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
mem_ck : out std_logic_vector(1 downto 0); -- .mem_ck
mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
mem_dm : out std_logic_vector(7 downto 0); -- .mem_dm
mem_ras_n : out std_logic_vector(0 downto 0); -- .mem_ras_n
mem_cas_n : out std_logic_vector(0 downto 0); -- .mem_cas_n
mem_we_n : out std_logic_vector(0 downto 0); -- .mem_we_n
mem_dq : inout std_logic_vector(63 downto 0) := (others => '0'); -- .mem_dq
mem_dqs : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dqs
mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dqs_n
mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
avl_ready : out std_logic; -- avl.waitrequest_n
avl_burstbegin : in std_logic := '0'; -- .beginbursttransfer
avl_addr : in std_logic_vector(24 downto 0) := (others => '0'); -- .address
avl_rdata_valid : out std_logic; -- .readdatavalid
avl_rdata : out std_logic_vector(255 downto 0); -- .readdata
avl_wdata : in std_logic_vector(255 downto 0) := (others => '0'); -- .writedata
avl_be : in std_logic_vector(31 downto 0) := (others => '0'); -- .byteenable
avl_read_req : in std_logic := '0'; -- .read
avl_write_req : in std_logic := '0'; -- .write
avl_size : in std_logic_vector(3 downto 0) := (others => '0'); -- .burstcount
local_init_done : out std_logic; -- status.local_init_done
local_cal_success : out std_logic; -- .local_cal_success
local_cal_fail : out std_logic; -- .local_cal_fail
oct_rdn : in std_logic := '0'; -- oct.rdn
oct_rup : in std_logic := '0' -- .rup
);
end ddr2ctrl;
architecture sim of ddr2ctrl is
signal lafi_clk, lafi_rst_n: std_ulogic;
signal lafi_half_clk: std_ulogic;
begin
afi_clk <= lafi_clk;
afi_half_clk <= lafi_half_clk;
afi_reset_n <= lafi_rst_n;
mem_a <= (others => '0');
mem_ba <= (others => '0');
mem_ck <= (others => '0');
mem_ck_n <= (others => '1');
mem_cke <= (others => '0');
mem_cs_n <= (others => '1');
mem_dm <= (others => '0');
mem_ras_n <= (others => '1');
mem_cas_n <= (others => '1');
mem_we_n <= (others => '1');
mem_dq <= (others => 'Z');
mem_dqs <= (others => 'Z');
mem_dqs_n <= (others => 'Z');
mem_odt <= (others => '0');
avl_ready <= '1';
local_init_done <= '1';
local_cal_success <= '1';
local_cal_fail <= '0';
-- 200 MHz clock
clkproc: process
begin
lafi_clk <= '0';
lafi_half_clk <= '0';
loop
wait for 2.5 ns;
lafi_clk <= not lafi_clk;
if lafi_clk='0' then
lafi_half_clk <= not lafi_half_clk;
end if;
end loop;
end process;
rstproc: process
begin
lafi_rst_n <= '0';
wait for 10 ns;
loop
if global_reset_n='0' then
lafi_rst_n <= '0';
wait until global_reset_n/='0';
wait until rising_edge(lafi_clk);
end if;
lafi_rst_n <= '1';
wait until global_reset_n='0';
end loop;
end process;
avlproc: process
subtype BYTE is std_logic_vector(7 downto 0);
type MEM is array(0 to ((2**20)-1)) of BYTE;
variable MEMA: MEM;
procedure load_srec is
file TCF : text open read_mode is "ram.srec";
variable L1: line;
variable CH: character;
variable ai: integer;
variable rectype: std_logic_vector(3 downto 0);
variable recaddr: std_logic_vector(31 downto 0);
variable reclen: std_logic_vector(7 downto 0);
variable recdata: std_logic_vector(0 to 16*8-1);
variable len: integer;
begin
L1:= new string'(""); --'
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then --'
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then --'
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := conv_integer(reclen)-1;
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
len := len-2;
when "0010" =>
hread(L1, recaddr(23 downto 0));
len := len-3;
when "0011" =>
hread(L1, recaddr);
len := len-4;
when others => next;
end case;
hread(L1, recdata(0 to 8*len-1));
recaddr(31 downto 20) := (others => '0');
ai := conv_integer(recaddr);
-- print("Setting " & tost(len) & "bytes at " & tost(recaddr));
for i in 0 to len-1 loop
MEMA(ai+i) := recdata((i*8) to (i*8+7));
end loop;
end if;
end if;
end if;
end loop;
end load_srec;
constant avldbits: integer := 256;
variable outqueue: std_logic_vector(0 to 4*avldbits-1) := (others => 'X');
variable outqueue_valid: std_logic_vector(0 to 3) := (others => '0');
variable ai,p: integer;
variable wbleft: integer := 0;
begin
load_srec;
loop
wait until rising_edge(lafi_clk);
avl_rdata_valid <= outqueue_valid(0);
avl_rdata <= outqueue(0 to avldbits-1);
outqueue(0 to 3*avldbits-1) := outqueue(avldbits to 4*avldbits-1);
outqueue(3*avldbits to 4*avldbits-1) := (others => 'X');
outqueue_valid := outqueue_valid(1 to 3) & '0';
if avl_burstbegin='1' then wbleft:=0; end if;
if lafi_rst_n='0' then
outqueue_valid := (others => '0');
elsif avl_read_req='1' then
ai := conv_integer(avl_addr(16 downto 0));
p := 0;
while outqueue_valid(p)='1' loop p:=p+1; end loop;
for x in 0 to conv_integer(avl_size)-1 loop
for y in 0 to avldbits/8-1 loop
outqueue((p+x)*avldbits+y*8 to (p+x)*avldbits+y*8+7) := MEMA((ai+x)*avldbits/8+y);
end loop;
outqueue_valid(p+x) := '1';
end loop;
elsif avl_write_req='1' then
if wbleft=0 then
wbleft := conv_integer(avl_size);
ai := conv_integer(avl_addr(16 downto 0));
end if;
for y in 0 to avldbits/8-1 loop
if avl_be(avldbits/8-1-y)='1' then
MEMA(ai*avldbits/8+y) := avl_wdata(avldbits-8*y-1 downto avldbits-8*y-8);
end if;
end loop;
wbleft := wbleft-1;
ai := ai+1;
end if;
end loop;
end process;
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/spacewire/router.in.vhd | 4 | 1703 | -- Spacewire interface
constant CFG_SPWRTR_ENABLE : integer := CONFIG_SPWRTR_ENABLE;
constant CFG_SPWRTR_INPUT : integer := CONFIG_SPWRTR_INPUT;
constant CFG_SPWRTR_OUTPUT : integer := CONFIG_SPWRTR_OUTPUT;
constant CFG_SPWRTR_RTSAME : integer := CONFIG_SPWRTR_RTSAME;
constant CFG_SPWRTR_FIFO : integer := CONFIG_SPWRTR_FIFO;
constant CFG_SPWRTR_TECHFIFO : integer := CONFIG_SPWRTR_TECHFIFO;
constant CFG_SPWRTR_FT : integer := CONFIG_SPWRTR_FT;
constant CFG_SPWRTR_SPWEN : integer := CONFIG_SPWRTR_SPWEN;
constant CFG_SPWRTR_AMBAEN : integer := CONFIG_SPWRTR_AMBAEN;
constant CFG_SPWRTR_FIFOEN : integer := CONFIG_SPWRTR_FIFOEN;
constant CFG_SPWRTR_SPWPORTS : integer := CONFIG_SPWRTR_SPWPORTS;
constant CFG_SPWRTR_AMBAPORTS : integer := CONFIG_SPWRTR_AMBAPORTS;
constant CFG_SPWRTR_FIFOPORTS : integer := CONFIG_SPWRTR_FIFOPORTS;
constant CFG_SPWRTR_ARB : integer := CONFIG_SPWRTR_ARB;
constant CFG_SPWRTR_RMAP : integer := CONFIG_SPWRTR_RMAP;
constant CFG_SPWRTR_RMAPCRC : integer := CONFIG_SPWRTR_RMAPCRC;
constant CFG_SPWRTR_FIFO2 : integer := CONFIG_SPWRTR_FIFO2;
constant CFG_SPWRTR_ALMOST : integer := CONFIG_SPWRTR_ALMOST;
constant CFG_SPWRTR_RXUNAL : integer := CONFIG_SPWRTR_RXUNAL;
constant CFG_SPWRTR_RMAPBUF : integer := CONFIG_SPWRTR_RMAPBUF;
constant CFG_SPWRTR_DMACHAN : integer := CONFIG_SPWRTR_DMACHAN;
constant CFG_SPWRTR_AHBSLVEN : integer := CONFIG_SPWRTR_AHBSLVEN;
constant CFG_SPWRTR_TIMERBITS : integer := CONFIG_SPWRTR_TIMERBITS;
constant CFG_SPWRTR_PNP : integer := CONFIG_SPWRTR_PNP;
constant CFG_SPWRTR_AUTOSCRUB : integer := CONFIG_SPWRTR_AUTOSCRUB;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-altera-ep2s60-ddr/testbench.vhd | 1 | 10576 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 8; -- rom data width (8/32)
romdepth : integer := 23; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 1 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal clkout, pllref : std_ulogic;
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(23 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_ulogic;
signal iosn : std_ulogic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal ssram_ce1n : std_logic;
signal ssram_ce2 : std_logic;
signal ssram_ce3n : std_logic;
signal ssram_wen : std_logic;
signal ssram_bw : std_logic_vector (0 to 3);
signal ssram_oen : std_ulogic;
signal ssaddr : std_logic_vector(20 downto 2);
signal ssdata : std_logic_vector(31 downto 0);
signal ssram_clk : std_ulogic;
signal ssram_adscn : std_ulogic;
signal ssram_adsp_n : std_ulogic;
signal ssram_adv_n : std_ulogic;
signal datazz : std_logic_vector(3 downto 0);
-- ddr memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clkin : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (1 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (1 downto 0); -- ddr dqs
signal ddr_dqs2 : std_logic_vector (1 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq, ddr_dq2 : std_logic_vector (15 downto 0); -- ddr data
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
--signal txd2, rxd2 : std_ulogic;
-- for smc lan chip
signal eth_aen : std_ulogic; -- for smsc eth
signal eth_readn : std_ulogic; -- for smsc eth
signal eth_writen : std_ulogic; -- for smsc eth
signal eth_nbe : std_logic_vector(3 downto 0); -- for smsc eth
signal eth_datacsn : std_ulogic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(31 downto 0);
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
ddr_clkin <= not clk after ct * 1 ns;
rst <= dsurst;
dsubren <= '1'; rxd1 <= '1';
dqs2delay : delay_wire
generic map(data_width => ddr_dqs'length, delay_atob => 3.0, delay_btoa => 1.0)
port map(a => ddr_dqs, b => ddr_dqs2);
ddr2delay : delay_wire
generic map(data_width => ddr_dq'length, delay_atob => 3.0, delay_btoa => 1.0)
port map(a => ddr_dq, b => ddr_dq2);
-- ddr_dqs <= (others => 'L');
d3 : entity work.leon3mp generic map (fabtech, memtech, padtech, clktech,
ncpu, disas, dbguart, pclow )
port map (rst, clk, error,
address, data, romsn, oen, writen, open, open,
ssram_ce1n, ssram_ce2, ssram_ce3n, ssram_wen, ssram_bw, ssram_oen, ssaddr, ssdata,
ssram_clk, ssram_adscn, ssram_adsp_n, ssram_adv_n, iosn,
ddr_clkin, ddr_clk, ddr_clkb, ddr_cke, ddr_csb, ddr_web, ddr_rasb,
ddr_casb, ddr_dm, ddr_dqs2, ddr_ad, ddr_ba, ddr_dq2,
dsubren, dsuact, rxd1, txd1,
eth_aen, eth_readn, eth_writen, eth_nbe);
ddr2: ddrram
generic map (width => 16, abits => 13,
colbits => 9, rowbits => 12, implbanks => 1,
fname => sdramfile, igndqs => 1)
port map (
ck => ddr_clk, cke => ddr_cke, csn => ddr_csb,
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq, dqs => ddr_dqs);
datazz <= "HHHH";
ssram0 : cy7c1380d generic map (fname => sramfile)
port map(
ioDq(35 downto 32) => datazz, ioDq(31 downto 0) => ssdata,
iAddr => ssaddr(20 downto 2), iMode => gnd,
inGW => vcc, inBWE => ssram_wen, inADV => ssram_adv_n,
inADSP => ssram_adsp_n, inADSC => ssram_adscn,
iClk => ssram_clk,
inBwa => ssram_bw(3), inBwb => ssram_bw(2),
inBwc => ssram_bw(1), inBwd => ssram_bw(0),
inOE => ssram_oen, inCE1 => ssram_ce1n,
iCE2 => ssram_ce2, inCE3 => ssram_ce3n, iZz => gnd);
-- 8 bit prom
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24),
romsn, writen, oen);
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
sd <= buskeep(sd), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, open);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-altera-ep2sgx90-av/sram32.vhd | 1 | 2686 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sram32
-- File: sram32.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Simulation model of generic 32-bit async SRAM
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library gaisler;
use gaisler.sim.all;
library grlib;
use grlib.stdlib.all;
entity sram32 is
generic (
index : integer := 0; -- Byte lane (0 - 3)
abits: Positive := 10; -- Default 10 address bits (1Kx32)
echk : integer := 0; -- Generate EDAC checksum
tacc : integer := 10; -- access time (ns)
fname : string := "ram.dat"); -- File to read from
port (
a : in std_logic_vector(abits-1 downto 0);
d : inout std_logic_vector(31 downto 0);
lb : in std_logic;
ub : in std_logic;
ce : in std_logic;
we : in std_ulogic;
oe : in std_ulogic);
end;
architecture sim of sram32 is
signal cex : std_logic_vector(0 to 1);
begin
cex(0) <= ce or lb; cex(1) <= ce or ub;
sr0 : sram generic map (index+3, abits, tacc, fname)
port map (a, d(7 downto 0), cex(0), we, oe);
sr1 : sram generic map (index+2, abits, tacc, fname)
port map (a, d(15 downto 8), cex(1), we, oe);
sr2 : sram generic map (index+1, abits, tacc, fname)
port map (a, d(23 downto 16), cex(1), we, oe);
sr3 : sram generic map (index, abits, tacc, fname)
port map (a, d(31 downto 24), cex(1), we, oe);
end sim;
-- pragma translate_on
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/can/can_rd.vhd | 1 | 6705 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: can_oc
-- File: can_oc.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB interface for the OpenCores CAN MAC
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.can.all;
entity can_rd is
generic (
slvndx : integer := 0;
ioaddr : integer := 16#000#;
iomask : integer := 16#FF0#;
irq : integer := 0;
memtech : integer := DEFMEMTECH;
syncrst : integer := 0;
dmap : integer := 0);
port (
resetn : in std_logic;
clk : in std_logic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
can_rxi : in std_logic_vector(1 downto 0);
can_txo : out std_logic_vector(1 downto 0)
);
end;
architecture rtl of can_rd is
constant ncores : integer := 1;
constant sepirq : integer := 0;
constant REVISION : amba_version_type := ncores-1;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_CANAHB, 0, REVISION, irq),
4 => ahb_iobar(ioaddr, iomask), others => zero32);
type ahbregs is record
hsel : std_ulogic;
hwrite : std_ulogic;
hwrite2 : std_ulogic;
htrans : std_logic_vector(1 downto 0);
haddr : std_logic_vector(10 downto 0);
hwdata : std_logic_vector(7 downto 0);
herr : std_ulogic;
hready : std_ulogic;
ws : std_logic_vector(1 downto 0);
irqi : std_logic_vector(ncores-1 downto 0);
irqo : std_logic_vector(ncores-1 downto 0);
muxsel : std_logic;
writemux : std_logic;
end record;
subtype cdata is std_logic_vector(7 downto 0);
type cdataarr is array (0 to 7) of cdata;
signal data_out : cdataarr;
signal reset : std_logic;
signal irqo : std_logic_vector(ncores-1 downto 0);
signal addr : std_logic_vector(7 downto 0);
signal vcc, gnd : std_ulogic;
signal r, rin : ahbregs;
signal can_lrxi, can_ltxo : std_logic;
begin
gnd <= '0'; vcc <= '1'; reset <= not resetn;
comb : process(ahbsi, r, resetn, data_out, irqo)
variable v : ahbregs;
variable hresp : std_logic_vector(1 downto 0);
variable dataout : std_logic_vector(7 downto 0);
variable irqvec : std_logic_vector(NAHBIRQ-1 downto 0);
variable vmuxreg : std_logic;
variable hwdata : std_logic_vector(31 downto 0);
begin
v := r;
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2));
if (r.hsel = '1' ) and (r.ws /= "11") then v.ws := r.ws + 1; end if;
if ahbsi.hready = '1' then
v.hsel := ahbsi.hsel(slvndx);
v.haddr := ahbsi.haddr(10 downto 0);
v.htrans := ahbsi.htrans;
v.hwrite := ahbsi.hwrite;
v.herr := orv(ahbsi.hsize) and ahbsi.hwrite;
v.ws := "00";
end if;
v.hready := (r.hsel and r.ws(1) and not r.ws(0)) or not resetn
or (ahbsi.hready and not ahbsi.htrans(1));
vmuxreg := not r.haddr(7) and r.haddr(6);
--v.hwrite2 := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
-- and not r.ws(0) and not r.herr;
v.hwrite2 := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
and not r.ws(0) and not r.herr and not vmuxreg;
v.writemux := r.hwrite and r.hsel and r.htrans(1) and r.ws(1)
and not r.ws(0) and vmuxreg;
if (r.herr and r.ws(1)) = '1' then hresp := HRESP_ERROR;
else hresp := HRESP_OKAY; end if;
case r.haddr(1 downto 0) is
when "00" => v.hwdata := hwdata(31 downto 24);
when "01" => v.hwdata := hwdata(23 downto 16);
when "10" => v.hwdata := hwdata(15 downto 8);
when others => v.hwdata := hwdata(7 downto 0);
end case;
--dataout := data_out(0);
if r.haddr(7 downto 6) = "01" then
dataout := (others => r.muxsel);
if r.writemux = '1' then
v.muxsel := r.hwdata(0);
end if;
else
dataout := data_out(0);
end if;
-- Interrupt goes to low when appeard and is normal high
-- but the irq controller from leon is active high and the interrupt should appear only
-- for 1 Clk cycle,
v.irqi := irqo; v.irqo:= (r.irqi and not irqo);
irqvec := (others => '0');
if sepirq = 1 then irqvec(ncores-1+irq downto irq) := r.irqo;
else irqvec(irq) := orv(r.irqo); end if;
ahbso.hirq <= irqvec;
ahbso.hrdata <= ahbdrivedata(dataout);
ahbso.hresp <= hresp; rin <= v;
end process;
-- Double mapping of registers [byte (offset 0), word (offset 0x80)]
dmap0 : if dmap = 0 generate
addr <= r.haddr(7 downto 0);
end generate;
dmap1 : if dmap = 1 generate
addr <= "000"&r.haddr(6 downto 2) when r.haddr(7) = '1' else
r.haddr(7 downto 0);
end generate;
reg : process(clk)
begin if clk'event and clk = '1' then r <= rin; end if; end process;
cmod : can_mod generic map (memtech, syncrst)
--port map (reset, clk, r.hsel, r.hwrite2, r.haddr(7 downto 0), r.hwdata,
port map (reset, clk, r.hsel, r.hwrite2, addr, r.hwdata,
data_out(0), irqo(0), can_lrxi, can_ltxo, ahbsi.testen);
cmux : canmux port map (r.muxsel, can_lrxi, can_ltxo, can_rxi, can_txo);
ahbso.hconfig <= hconfig;
ahbso.hindex <= slvndx;
ahbso.hsplit <= (others => '0');
ahbso.hready <= r.hready;
-- pragma translate_off
bootmsg : report_version
generic map (
"can_oc" & tost(slvndx) &
": SJA1000 Compatible CAN MAC, revision " & tost(REVISION) &
", irq " & tost(irq));
-- pragma translate_on
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/memctrl/memctrl.vhd | 1 | 20444 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: memctrl
-- File: memctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory controller package
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.log2;
library techmap;
use techmap.gencomp.all;
package memctrl is
type memory_in_type is record
data : std_logic_vector(31 downto 0); -- Data bus address
brdyn : std_logic;
bexcn : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
bwidth : std_logic_vector(1 downto 0);
sd : std_logic_vector(63 downto 0);
cb : std_logic_vector(15 downto 0);
scb : std_logic_vector(15 downto 0);
edac : std_logic;
end record;
constant memory_in_none : memory_in_type :=
((others => '0'), '0', '0', '0', (others => '0'), (others => '0'),
(others => '0'), (others => '0'), (others => '0'), '0');
type memory_out_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
sddata : std_logic_vector(63 downto 0);
ramsn : std_logic_vector(7 downto 0);
ramoen : std_logic_vector(7 downto 0);
ramn : std_ulogic;
romn : std_ulogic;
mben : std_logic_vector(3 downto 0);
iosn : std_logic;
romsn : std_logic_vector(7 downto 0);
oen : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
bdrive : std_logic_vector(3 downto 0);
vbdrive : std_logic_vector(31 downto 0); --vector bus drive
svbdrive : std_logic_vector(63 downto 0); --vector bus drive sdram
read : std_logic;
sa : std_logic_vector(14 downto 0);
cb : std_logic_vector(15 downto 0);
scb : std_logic_vector(15 downto 0);
vcdrive : std_logic_vector(15 downto 0); --vector bus drive cb
svcdrive : std_logic_vector(15 downto 0); --vector bus drive cb sdram
ce : std_ulogic;
sdram_en : std_ulogic; -- SDRAM enabled
rs_edac_en : std_ulogic; -- Reed-Solomon enabled
end record;
constant memory_out_none : memory_out_type :=
((others => '0'), (others => '0'), (others => '0'), (others => '1'),
(others => '1'), '1', '1', (others => '1'), '1', (others => '1'),
'1', '1', (others => '1'), (others => '1'), (others => '1'),
(others => '1'), '0', (others => '0'), (others => '1'), (others => '1'),
(others => '1'), (others => '1'), '0', '0', '0');
type sdctrl_in_type is record
wprot : std_ulogic;
data : std_logic_vector (127 downto 0); -- data in
cb : std_logic_vector(63 downto 0);
regrdata : std_logic_vector(63 downto 0); -- PHY-specific reg in
datavalid : std_logic; -- Data-valid signal
end record;
constant sdctrl_in_none : sdctrl_in_type :=
('0', (others => '0'), (others => '0'), (others => '0'), '0');
type sdctrl_out_type is record
sdcke : std_logic_vector ( 1 downto 0); -- clk en
sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
xsdcsn : std_logic_vector ( 7 downto 0); -- ext. chip sel
sdwen : std_ulogic; -- write en
rasn : std_ulogic; -- row addr stb
casn : std_ulogic; -- col addr stb
dqm : std_logic_vector ( 15 downto 0); -- data i/o mask
bdrive : std_ulogic; -- bus drive
qdrive : std_ulogic; -- bus drive
nbdrive : std_ulogic; -- bdrive 1 cycle early
vbdrive : std_logic_vector(63 downto 0); -- vector bus drive
address : std_logic_vector (16 downto 2); -- address out
data : std_logic_vector (127 downto 0); -- data out
cb : std_logic_vector(63 downto 0);
ce : std_ulogic;
ba : std_logic_vector (2 downto 0); -- bank address
sdck : std_logic_vector(2 downto 0);
moben : std_logic; -- Mobile support
cal_en : std_logic_vector(7 downto 0); -- enable delay calibration
cal_inc : std_logic_vector(7 downto 0); -- inc/dec delay
cal_pll : std_logic_vector(1 downto 0); -- (enable,inc/dec) pll phase
cal_rst : std_logic; -- calibration reset
odt : std_logic_vector(1 downto 0); -- In Die Termination
conf : std_logic_vector(63 downto 0);
oct : std_logic; -- On Chip Termination
vcbdrive : std_logic_vector(31 downto 0); -- cb vector bus drive
dqs_gate : std_logic;
cbdqm : std_logic_vector(7 downto 0);
cbcal_en : std_logic_vector(3 downto 0);
cbcal_inc : std_logic_vector(3 downto 0);
read_pend : std_logic_vector(7 downto 0); -- Read pending within 7...0
-- cycles (not including phy delays)
-- PHY-specific register interface
regwdata : std_logic_vector(63 downto 0);
regwrite : std_logic_vector(1 downto 0);
end record;
constant sdctrl_out_none : sdctrl_out_type :=
((others => '0'), (others => '0'), (others => '0'), '0', '0', '0', (others => '0'),
'0', '0', '0', (others => '0'), (others => '0'), (others => '0'),
(others => '0'), '0', (others => '0'), (others => '0'), '0',
(others => '0'), (others => '0'), (others => '0'), '0',
(others => '0'), (others => '0'), '0', (others => '0'), '0',
(others => '0'), (others => '0'), (others => '0'), "00000000",
(others => '0'), "00");
type sdram_out_type is record
sdcke : std_logic_vector ( 1 downto 0); -- clk en
sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
sdwen : std_ulogic; -- write en
rasn : std_ulogic; -- row addr stb
casn : std_ulogic; -- col addr stb
dqm : std_logic_vector ( 7 downto 0); -- data i/o mask
end record;
type zbtssram_out_type is record
cen : std_ulogic;
oen : std_ulogic;
wen : std_ulogic;
advld : std_ulogic;
addr : std_logic_vector(22 downto 0);
bwn : std_logic_vector(15 downto 0);
data : std_logic_vector(127 downto 0);
dqoen : std_logic_vector(127 downto 0);
zz : std_ulogic;
shutdown : std_ulogic;
end record;
constant zbtssram_out_none : zbtssram_out_type := (
'1','1','1','1',(others => '0'),(others => '1'),(others => '0'),(others => '1'),'0','0');
type zbtssram_in_type is record
data : std_logic_vector(127 downto 0);
mbe : std_logic_vector(7 downto 0);
end record;
constant zbtssram_in_none : zbtssram_in_type := ( data => (others => '0'), mbe => (others => '0') );
component sdctrl
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
sdbits : integer := 32;
oepol : integer := 0;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component sdctrl64
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ftsdctrl is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
sdbits : integer := 32;
edacen : integer := 1;
errcnt : integer := 0;
cntbits : integer range 1 to 8 := 1;
oepol : integer := 0;
pageburst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ftsdctrl64
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
pageburst : integer := 0;
mobile : integer := 0;
edac : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component srctrl
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
romws : integer := 2;
iows : integer := 2;
rmw : integer := 0;
prom8en : integer := 0;
oepol : integer := 0;
srbanks : integer range 1 to 5 := 1;
banksz : integer range 0 to 13 := 13;
romasel : integer range 0 to 28 := 19
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
component ftsrctrl is
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
romws : integer := 2;
iows : integer := 2;
rmw : integer := 0;
srbanks : integer range 1 to 8 := 1;
banksz : integer range 0 to 15 := 15;
rombanks : integer range 1 to 8 := 1;
rombanksz : integer range 0 to 15 := 15;
rombankszdef : integer range 0 to 15 := 15;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer range 0 to 1 := 1;
errcnt : integer range 0 to 1 := 0;
cntbits : integer range 1 to 8 := 1;
wsreg : integer := 0;
oepol : integer := 0;
prom8en : integer := 0;
netlist : integer := 0;
tech : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
type sdram_in_type is record
haddr : std_logic_vector(31 downto 0); -- memory address
rhaddr : std_logic_vector(31 downto 0); -- latched memory address
hready : std_ulogic;
hsize : std_logic_vector(1 downto 0);
hsel : std_ulogic;
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
rhtrans : std_logic_vector(1 downto 0);
nhtrans : std_logic_vector(1 downto 0);
idle : std_ulogic;
enable : std_ulogic;
error : std_ulogic;
merror : std_ulogic;
brmw : std_ulogic;
edac : std_ulogic;
srdis : std_logic;
end record;
type sdram_mctrl_out_type is record
address : std_logic_vector(16 downto 2);
busy : std_ulogic;
aload : std_ulogic;
bdrive : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
bsel : std_ulogic;
hresp : std_logic_vector (1 downto 0);
vhready : std_ulogic;
prdata : std_logic_vector (31 downto 0);
end record;
type wprot_out_type is record
wprothit : std_ulogic;
end record;
component sdmctrl
generic (
pindex : integer := 0;
invclk : integer := 0;
fast : integer := 0;
wprot : integer := 0;
sdbits : integer := 32;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
sdi : in sdram_in_type;
sdo : out sdram_out_type;
apbi : in apb_slv_in_type;
wpo : in wprot_out_type;
sdmo : out sdram_mctrl_out_type
);
end component;
component ftsdmctrl
generic (
pindex : integer := 0;
invclk : integer := 0;
fast : integer := 0;
wprot : integer := 0;
sdbits : integer := 32;
syncrst : integer := 0;
pageburst : integer := 0;
edac : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
sdi : in sdram_in_type;
sdo : out sdram_out_type;
apbi : in apb_slv_in_type;
wpo : in wprot_out_type;
sdmo : out sdram_mctrl_out_type
);
end component;
component ftmctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2; -- set to 12 for the GE-HPE board
oepol : integer := 0;
edac : integer := 0;
syncrst : integer := 0;
pageburst : integer := 0;
scantest : integer := 0;
writefb : integer := 0;
netlist : integer := 0;
tech : integer := 0;
rahold : integer := 0;
wsshift : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type
);
end component;
component ssrctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
paddr : integer := 0;
pmask : integer := 16#fff#;
oepol : integer := 0;
bus16 : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type
);
end component;
component ftsrctrl_v1
generic (
hindex: Integer := 1;
romaddr: Integer := 16#000#;
rommask: Integer := 16#ff0#;
ramaddr: Integer := 16#400#;
rammask: Integer := 16#ff0#;
ioaddr: Integer := 16#200#;
iomask: Integer := 16#ff0#;
ramws: Integer := 0;
romws: Integer := 0;
iows: Integer := 0;
rmw: Integer := 1;
srbanks: Integer range 1 to 8 := 8;
banksz: Integer range 0 to 13 := 0;
rombanks: Integer range 1 to 8 := 8;
rombanksz: Integer range 0 to 13 := 0;
rombankszdef: Integer range 0 to 13 := 6;
romasel: Integer range 0 to 28 := 0;
pindex: Integer := 0;
paddr: Integer := 16#000#;
pmask: Integer := 16#fff#;
edacen: Integer range 0 to 1 := 1;
errcnt: Integer range 0 to 1 := 0;
cntbits: Integer range 1 to 8 := 1;
wsreg: Integer := 1;
oepol: Integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
component ftsrctrl8 is
generic (
hindex : integer := 0;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
iows : integer := 2;
srbanks : integer range 1 to 8 := 1;
banksz : integer range 0 to 15 := 15;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer range 0 to 1 := 1;
errcnt : integer range 0 to 1 := 1;
cntbits : integer range 1 to 8 := 1;
wsreg : integer := 0;
oepol : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type
);
end component;
component p8ctrl
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 0;
iomask : integer := 16#ff0#;
ioaddr : integer := 0;
rammask : integer := 16#ff0#;
romws : integer := 15;
ramws : integer := 15;
prom8en : integer := 0;
rmw : integer := 0;
oepol : integer := 0;
romasel : integer range 0 to 28 := 23
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/misc/rstgen.vhd | 1 | 3595 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: rstgen
-- File: rstgen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Reset generation with glitch filter
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity rstgen is
generic (
acthigh : integer := 0;
syncrst : integer := 0;
scanen : integer := 0;
syncin : integer := 0);
port (
rstin : in std_ulogic;
clk : in std_ulogic;
clklock : in std_ulogic;
rstout : out std_ulogic;
rstoutraw : out std_ulogic;
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end;
architecture rtl of rstgen is
signal r : std_logic_vector(4 downto 0);
signal rst, rstoutl, clklockl, arst : std_ulogic;
signal rstsyncin : std_ulogic;
signal inrst_syncreg : std_ulogic;
signal genrst : std_ulogic;
signal genrst_syncreg : std_logic_vector(1 downto 0);
begin
nosyncinrst : if syncin = 0 generate
rst <= not rstin when acthigh = 1 else rstin;
clklockl <= clklock;
end generate;
syncinrst : if syncin = 1 generate
rstsyncin <= not rstin when acthigh = 1 else rstin;
syncreg0 : syncreg port map (clk, rstsyncin, inrst_syncreg);
genrst <= testrst when (scanen = 1) and (testen = '1') else inrst_syncreg;
gensyncrest : process (clk, genrst) begin
if rising_edge(clk) then
genrst_syncreg(0) <= '1';
genrst_syncreg(1) <= genrst_syncreg(0);
end if;
if ( genrst = '0') then genrst_syncreg <= (others => '0'); end if;
end process;
rst <= genrst_syncreg(1);
syncreg1 : syncreg port map (clk, clklock, clklockl);
end generate;
rstoutraw <= not rstin when acthigh = 1 else rstin;
arst <= testrst when (scanen = 1) and (testen = '1') else rst;
async : if (syncrst = 0 and syncin = 0) generate
reg1 : process (clk, arst) begin
if rising_edge(clk) then
r <= r(3 downto 0) & clklockl;
rstoutl <= r(4) and r(3) and r(2);
end if;
if (arst = '0') then r <= "00000"; rstoutl <= '0'; end if;
end process;
rstout <= (rstoutl and rst) when scanen = 1 else rstoutl;
end generate;
sync : if (syncrst = 1 or syncin = 1) generate
reg1 : process (clk) begin
if rising_edge(clk) then
r <= (r(3 downto 0) & clklockl) and (rst & rst & rst & rst & rst);
rstoutl <= r(4) and r(3) and r(2);
end if;
end process;
rstout <= rstoutl and rst;
end generate;
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/ddr/mig_series7.in.vhd | 2 | 162 | -- Xilinx MIG Series 7
constant CFG_MIG_SERIES7 : integer := CONFIG_MIG_SERIES7;
constant CFG_MIG_SERIES7_MODEL : integer := CONFIG_MIG_SERIES7_MODEL;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/maps/outpad_ds.vhd | 1 | 3628 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: outpad_ds
-- File: outpad_ds.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Differential output pad with technology wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allpads.all;
entity outpad_ds is
generic (tech : integer := 0; level : integer := lvds;
voltage : integer := x33v; oepol : integer := 0; slew : integer := 0);
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
end;
architecture rtl of outpad_ds is
signal gnd, oen : std_ulogic;
begin
gnd <= '0';
oen <= not en when oepol /= padoen_polarity(tech) else en;
gen0 : if has_ds_pads(tech) = 0 generate
padp <= i
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
padn <= not i
-- pragma translate_off
after 1 ns
-- pragma translate_on
;
end generate;
xcv : if (is_unisim(tech) = 1) generate
u0 : unisim_outpad_ds generic map (level, slew, voltage) port map (padp, padn, i);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
u0 : axcel_outpad_ds generic map (level, voltage) port map (padp, padn, i);
end generate;
pa3 : if (tech = apa3) generate
u0 : apa3_outpad_ds generic map (level) port map (padp, padn, i);
end generate;
pa3e : if (tech = apa3e) generate
u0 : apa3e_outpad_ds generic map (level) port map (padp, padn, i);
end generate;
pa3l : if (tech = apa3l) generate
u0 : apa3l_outpad_ds generic map (level) port map (padp, padn, i);
end generate;
fus : if (tech = actfus) generate
u0 : fusion_outpad_ds generic map (level) port map (padp, padn, i);
end generate;
rht : if (tech = rhlib18t) generate
u0 : rh_lib18t_outpad_ds port map (padp, padn, i, oen);
end generate;
n2x : if (tech = easic45) generate
u0 : n2x_outpad_ds generic map (level, voltage) port map (padp, padn, i);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity outpad_dsv is
generic (tech : integer := 0; level : integer := x33v;
voltage : integer := lvds; width : integer := 1;
oepol : integer := 0; slew : integer := 0);
port (
padp : out std_logic_vector(width-1 downto 0);
padn : out std_logic_vector(width-1 downto 0);
i, en: in std_logic_vector(width-1 downto 0));
end;
architecture rtl of outpad_dsv is
begin
v : for j in width-1 downto 0 generate
u0 : outpad_ds generic map (tech, level, voltage, oepol, slew)
port map (padp(j), padn(j), i(j), en(j));
end generate;
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-vc707/sgmii_vc707.vhd | 1 | 40242 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sgmii
-- File: sgmii.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler
-- Description: GMII to SGMII interface
------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Description: This is the top level vhdl example design for the
-- Ethernet 1000BASE-X PCS/PMA core.
--
-- This design example instantiates IOB flip-flops
-- and input/output buffers on the GMII.
--
-- A Transmitter Elastic Buffer is instantiated on the Tx
-- GMII path to perform clock compenstation between the
-- core and the external MAC driving the Tx GMII.
--
-- This design example can be synthesised.
--
--
--
-- ----------------------------------------------------------------
-- | Example Design |
-- | |
-- | ---------------------------------------------- |
-- | | Core Block (wrapper) | |
-- | | | |
-- | | -------------- -------------- | |
-- | | | Core | | tranceiver | | |
-- | | | | | | | |
-- | --------- | | | | | | |
-- | | | | | | | | | |
-- | | Tx | | | | | | | |
-- ---->|Elastic|----->| GMII |--------->| TXP |--------->
-- | |Buffer | | | Tx | | TXN | | |
-- | | | | | | | | | |
-- | --------- | | | | | | |
-- | GMII | | | | | | |
-- | IOBs | | | | | | |
-- | | | | | | | |
-- | | | GMII | | RXP | | |
-- <-------------------| Rx |<---------| RXN |<---------
-- | | | | | | | |
-- | | -------------- -------------- | |
-- | | | |
-- | ---------------------------------------------- |
-- | |
-- ----------------------------------------------------------------
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library gaisler;
use gaisler.net.all;
use gaisler.misc.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library eth;
use eth.grethpkg.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- The entity declaration for the example design
--------------------------------------------------------------------------------
entity sgmii_vc707 is
generic(
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
abits : integer := 8;
autonegotiation : integer := 1;
pirq : integer := 0;
debugmem : integer := 0;
tech : integer := 0;
simulation : integer := 0
);
port(
-- Tranceiver Interface
sgmiii : in eth_sgmii_in_type;
sgmiio : out eth_sgmii_out_type;
-- GMII Interface (client MAC <=> PCS)
gmiii : out eth_in_type;
gmiio : in eth_out_type;
-- Asynchronous reset for entire core.
reset : in std_logic;
-- APB Status bus
apb_clk : in std_logic;
apb_rstn : in std_logic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type
);
end sgmii_vc707;
architecture top_level of sgmii_vc707 is
------------------------------------------------------------------------------
-- Component Declaration for the Core Block (core wrapper).
------------------------------------------------------------------------------
component sgmii
port(
-- Transceiver Interface
------------------------
gtrefclk : in std_logic; -- Very high quality 125MHz clock for GT transceiver
txp : out std_logic; -- Differential +ve of serial transmission from PMA to PMD.
txn : out std_logic; -- Differential -ve of serial transmission from PMA to PMD.
rxp : in std_logic; -- Differential +ve for serial reception from PMD to PMA.
rxn : in std_logic; -- Differential -ve for serial reception from PMD to PMA.
resetdone : out std_logic; -- The GT transceiver has completed its reset cycle
cplllock : out std_logic;
txoutclk : out std_logic; -- txoutclk from GT transceiver (62.5MHz)
rxoutclk : out std_logic; -- txoutclk from GT transceiver (62.5MHz)
userclk : in std_logic; -- 62.5MHz clock.
userclk2 : in std_logic; -- 125MHz clock.
rxuserclk : in std_logic; -- 125MHz clock.
rxuserclk2 : in std_logic; -- 125MHz clock.
independent_clock_bufg : in std_logic;
pma_reset : in std_logic; -- transceiver PMA reset signal
mmcm_locked : in std_logic; -- Locked signal from MMCM
-- GMII Interface
-----------------
sgmii_clk_r : out std_logic; -- Clock for client MAC (125Mhz, 12.5MHz or 1.25MHz).
sgmii_clk_f : out std_logic; -- Clock for client MAC (125Mhz, 12.5MHz or 1.25MHz).
sgmii_clk_en : out std_logic; -- Clock enable for client MAC
gmii_txd : in std_logic_vector(7 downto 0); -- Transmit data from client MAC.
gmii_tx_en : in std_logic; -- Transmit control signal from client MAC.
gmii_tx_er : in std_logic; -- Transmit control signal from client MAC.
gmii_rxd : out std_logic_vector(7 downto 0); -- Received Data to client MAC.
gmii_rx_dv : out std_logic; -- Received control signal to client MAC.
gmii_rx_er : out std_logic; -- Received control signal to client MAC.
gmii_isolate : out std_logic; -- Tristate control to electrically isolate GMII.
-- Management: MDIO Interface
-----------------------------
configuration_vector : in std_logic_vector(4 downto 0); -- Alternative to MDIO interface.
an_interrupt : out std_logic; -- Interrupt to processor to signal that Auto-Negotiation has completed
an_adv_config_vector : in std_logic_vector(15 downto 0); -- Alternate interface to program REG4 (AN ADV)
an_restart_config : in std_logic; -- Alternate signal to modify AN restart bit in REG0
-- Speed Control
----------------
speed_is_10_100 : in std_logic; -- Core should operate at either 10Mbps or 100Mbps speeds
speed_is_100 : in std_logic; -- Core should operate at 100Mbps speed
-- General IO's
---------------
status_vector : out std_logic_vector(15 downto 0); -- Core status.
reset : in std_logic; -- Asynchronous reset for entire core.
signal_detect : in std_logic; -- Input from PMD to indicate presence of optical input.
gt0_qplloutclk_in : in std_logic; -- Input from PMD to indicate presence of optical input.
gt0_qplloutrefclk_in : in std_logic -- Input from PMD to indicate presence of optical input.
);
end component;
component MMCME2_ADV
generic (
BANDWIDTH : string := "OPTIMIZED";
CLKFBOUT_MULT_F : real := 5.000;
CLKFBOUT_PHASE : real := 0.000;
--CLKFBOUT_USE_FINE_PS : boolean := FALSE;
CLKIN1_PERIOD : real := 0.000;
CLKIN2_PERIOD : real := 0.000;
CLKOUT0_DIVIDE_F : real := 1.000;
CLKOUT0_DUTY_CYCLE : real := 0.500;
CLKOUT0_PHASE : real := 0.000;
--CLKOUT0_USE_FINE_PS : boolean := FALSE;
CLKOUT1_DIVIDE : integer := 1;
CLKOUT1_DUTY_CYCLE : real := 0.500;
CLKOUT1_PHASE : real := 0.000;
--CLKOUT1_USE_FINE_PS : boolean := FALSE;
CLKOUT2_DIVIDE : integer := 1;
CLKOUT2_DUTY_CYCLE : real := 0.500;
CLKOUT2_PHASE : real := 0.000;
--CLKOUT2_USE_FINE_PS : boolean := FALSE;
CLKOUT3_DIVIDE : integer := 1;
CLKOUT3_DUTY_CYCLE : real := 0.500;
CLKOUT3_PHASE : real := 0.000;
--CLKOUT3_USE_FINE_PS : boolean := FALSE;
--CLKOUT4_CASCADE : boolean := FALSE;
CLKOUT4_DIVIDE : integer := 1;
CLKOUT4_DUTY_CYCLE : real := 0.500;
CLKOUT4_PHASE : real := 0.000;
--CLKOUT4_USE_FINE_PS : boolean := FALSE;
CLKOUT5_DIVIDE : integer := 1;
CLKOUT5_DUTY_CYCLE : real := 0.500;
CLKOUT5_PHASE : real := 0.000;
--CLKOUT5_USE_FINE_PS : boolean := FALSE;
CLKOUT6_DIVIDE : integer := 1;
CLKOUT6_DUTY_CYCLE : real := 0.500;
CLKOUT6_PHASE : real := 0.000;
--CLKOUT6_USE_FINE_PS : boolean := FALSE;
COMPENSATION : string := "ZHOLD";
DIVCLK_DIVIDE : integer := 1;
REF_JITTER1 : real := 0.0;
REF_JITTER2 : real := 0.0;
--SS_EN : string := "FALSE";
SS_MODE : string := "CENTER_HIGH";
SS_MOD_PERIOD : integer := 10000
);
port (
CLKFBOUT : out std_ulogic := '0';
CLKFBOUTB : out std_ulogic := '0';
CLKFBSTOPPED : out std_ulogic := '0';
CLKINSTOPPED : out std_ulogic := '0';
CLKOUT0 : out std_ulogic := '0';
CLKOUT0B : out std_ulogic := '0';
CLKOUT1 : out std_ulogic := '0';
CLKOUT1B : out std_ulogic := '0';
CLKOUT2 : out std_ulogic := '0';
CLKOUT2B : out std_ulogic := '0';
CLKOUT3 : out std_ulogic := '0';
CLKOUT3B : out std_ulogic := '0';
CLKOUT4 : out std_ulogic := '0';
CLKOUT5 : out std_ulogic := '0';
CLKOUT6 : out std_ulogic := '0';
DO : out std_logic_vector (15 downto 0);
DRDY : out std_ulogic := '0';
LOCKED : out std_ulogic := '0';
PSDONE : out std_ulogic := '0';
CLKFBIN : in std_ulogic;
CLKIN1 : in std_ulogic;
CLKIN2 : in std_ulogic;
CLKINSEL : in std_ulogic;
DADDR : in std_logic_vector(6 downto 0);
DCLK : in std_ulogic;
DEN : in std_ulogic;
DI : in std_logic_vector(15 downto 0);
DWE : in std_ulogic;
PSCLK : in std_ulogic;
PSEN : in std_ulogic;
PSINCDEC : in std_ulogic;
PWRDWN : in std_ulogic;
RST : in std_ulogic
);
end component;
----- component IBUFDS_GTE2 -----
component IBUFDS_GTE2
port (
O : out std_ulogic;
ODIV2 : out std_ulogic;
CEB : in std_ulogic;
I : in std_ulogic;
IB : in std_ulogic
);
end component;
----- component BUFHCE -----
component BUFHCE
generic (
CE_TYPE : string := "SYNC";
INIT_OUT : integer := 0
);
port (
O : out std_ulogic;
CE : in std_ulogic;
I : in std_ulogic
);
end component;
----- component BUFGMUX -----
component BUFGMUX
generic (
CLK_SEL_TYPE : string := "ASYNC"
);
port (
O : out std_ulogic := '0';
I0 : in std_ulogic := '0';
I1 : in std_ulogic := '0';
S : in std_ulogic := '0'
);
end component;
----- component ODDR -----
component ODDR
generic (
DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
INIT : bit := '0';
SRTYPE : string := "SYNC"
);
port (
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic := 'L';
S : in std_ulogic := 'L'
);
end component;
constant REVISION : integer := 1;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_SGMII, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
type sgmiiregs is record
irq : std_logic_vector(31 downto 0); -- interrupt
mask : std_logic_vector(31 downto 0); -- interrupt enable
configuration_vector : std_logic_vector( 4 downto 0);
an_adv_config_vector : std_logic_vector(15 downto 0);
end record;
-- APB and RGMII control register
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES_configuration_vector : std_logic_vector(4 downto 0) := std_logic_vector(to_unsigned(autonegotiation,1)) & "0000";
constant RES : sgmiiregs :=
( irq => (others => '0'), mask => (others => '0'),
configuration_vector => RES_configuration_vector, an_adv_config_vector => "0001100000000001");
type rxregs is record
gmii_rxd : std_logic_vector(7 downto 0);
gmii_rxd_int : std_logic_vector(7 downto 0);
gmii_rx_dv : std_logic;
gmii_rx_er : std_logic;
count : integer;
gmii_dv : std_logic;
keepalive : integer;
end record;
constant RESRX : rxregs :=
( gmii_rxd => (others => '0'), gmii_rxd_int => (others => '0'),
gmii_rx_dv => '0', gmii_rx_er => '0',
count => 0, gmii_dv => '0', keepalive => 0
);
type txregs is record
gmii_txd : std_logic_vector(7 downto 0);
gmii_txd_int : std_logic_vector(7 downto 0);
gmii_tx_en : std_logic;
gmii_tx_en_int : std_logic;
gmii_tx_er : std_logic;
count : integer;
cnt_en : std_logic;
keepalive : integer;
end record;
constant RESTX : txregs :=
( gmii_txd => (others => '0'), gmii_txd_int => (others => '0'),
gmii_tx_en => '0', gmii_tx_en_int => '0', gmii_tx_er => '0',
count => 0, cnt_en => '0', keepalive => 0
);
------------------------------------------------------------------------------
-- internal signals used in this top level example design.
------------------------------------------------------------------------------
-- clock generation signals for tranceiver
signal gtrefclk : std_logic;
signal txoutclk : std_logic;
signal rxoutclk : std_logic;
signal resetdone : std_logic;
signal mmcm_locked : std_logic;
signal mmcm_reset : std_logic;
signal clkfbout : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal userclk : std_logic;
signal userclk2 : std_logic;
signal rxuserclk : std_logic;
signal rxuserclk2 : std_logic;
-- PMA reset generation signals for tranceiver
signal pma_reset_pipe : std_logic_vector(3 downto 0);
signal pma_reset : std_logic;
-- clock generation signals for SGMII clock
signal sgmii_clk_r : std_logic;
signal sgmii_clk_f : std_logic;
signal sgmii_clk_en : std_logic;
signal sgmii_clk : std_logic;
signal sgmii_clk_int : std_logic;
-- GMII signals
signal gmii_txd : std_logic_vector(7 downto 0);
signal gmii_tx_en : std_logic;
signal gmii_tx_er : std_logic;
signal gmii_rxd : std_logic_vector(7 downto 0);
signal gmii_rx_dv : std_logic;
signal gmii_rx_er : std_logic;
signal gmii_isolate : std_logic;
-- Internal GMII signals from Xilinx SGMII block
signal gmii_rxd_int : std_logic_vector(7 downto 0);
signal gmii_rx_dv_int : std_logic;
signal gmii_rx_er_int : std_logic;
-- Extra registers to ease IOB placement
signal status_vector_int : std_logic_vector(15 downto 0);
signal status_vector_apb : std_logic_vector(15 downto 0);
signal status_vector_apb1 : std_logic_vector(31 downto 0);
signal status_vector_apb2 : std_logic_vector(31 downto 0);
-- These attributes will stop timing errors being reported in back annotated
-- SDF simulation.
attribute ASYNC_REG : string;
attribute ASYNC_REG of pma_reset_pipe : signal is "TRUE";
-- Configuration register
signal speed_is_10_100 : std_logic;
signal speed_is_100 : std_logic;
signal configuration_vector : std_logic_vector(4 downto 0);
signal an_interrupt : std_logic;
signal an_adv_config_vector : std_logic_vector(15 downto 0);
signal an_restart_config : std_logic;
signal link_timer_value : std_logic_vector(8 downto 0);
signal synchronization_done : std_logic;
signal linkup : std_logic;
signal signal_detect : std_logic;
-- Route gtrefclk through an IBUFG.
signal gtrefclk_buf_i : std_logic;
attribute clock_signal : string;
attribute clock_signal of sgmii_clk : signal is "yes";
attribute clock_signal of sgmii_clk_int : signal is "yes";
signal r, rin : sgmiiregs;
signal rrx,rinrx : rxregs;
signal rtx, rintx : txregs;
signal cnt_en : std_logic;
signal usr2rstn : std_logic;
-- debug signal
signal WMemRgmiioData : std_logic_vector(15 downto 0);
signal RMemRgmiioData : std_logic_vector(15 downto 0);
signal RMemRgmiioAddr : std_logic_vector(9 downto 0);
signal WMemRgmiioAddr : std_logic_vector(9 downto 0);
signal WMemRgmiioWrEn : std_logic;
signal WMemRgmiiiData : std_logic_vector(15 downto 0);
signal RMemRgmiiiData : std_logic_vector(15 downto 0);
signal RMemRgmiiiAddr : std_logic_vector(9 downto 0);
signal WMemRgmiiiAddr : std_logic_vector(9 downto 0);
signal WMemRgmiiiWrEn : std_logic;
signal RMemRgmiiiRead : std_logic;
signal RMemRgmiioRead : std_logic;
begin
-----------------------------------------------------------------------------
-- Default for VC707
-----------------------------------------------------------------------------
-- Remove AN during simulation i.e. "00000"
configuration_vector <= "10000" when (autonegotiation = 1) else "00000";
-- Configuration for Xilinx SGMII IP. See doc for SGMII IP for more information
an_adv_config_vector <= "0001100000000001";
an_restart_config <= '0';
link_timer_value <= "000110010";
-- Core Status vector outputs
synchronization_done <= status_vector_int(1);
linkup <= status_vector_int(0);
signal_detect <= '1';
gmiii.gtx_clk <= userclk2;
gmiii.tx_clk <= userclk2;
gmiii.rx_clk <= userclk2;
gmiii.rmii_clk <= userclk2;
gmiii.rxd <= gmii_rxd;
gmiii.rx_dv <= gmii_rx_dv;
gmiii.rx_er <= gmii_rx_er;
gmiii.rx_en <= gmii_rx_dv or sgmii_clk_en;
--gmiii.tx_dv <= '1';
gmiii.tx_dv <= cnt_en when gmiio.tx_en = '1' else '1';
-- GMII output controlled via generics
gmiii.edclsepahb <= '0';
gmiii.edcldisable <= '0';
gmiii.phyrstaddr <= (others => '0');
gmiii.edcladdr <= (others => '0');
-- Not used
gmiii.rx_col <= '0';
gmiii.rx_crs <= '0';
gmiii.tx_clk_90 <= '0';
sgmiio.mdio_o <= gmiio.mdio_o;
sgmiio.mdio_oe <= gmiio.mdio_oe;
gmiii.mdio_i <= sgmiii.mdio_i;
sgmiio.mdc <= gmiio.mdc;
gmiii.mdint <= sgmiii.mdint;
sgmiio.reset <= apb_rstn;
-----------------------------------------------------------------------------
-- Transceiver Clock Management
-----------------------------------------------------------------------------
sgmii1 : if simulation = 1 generate
end generate;
sgmii0 : if simulation = 0 generate
-- Clock circuitry for the GT Transceiver uses a differential input clock.
-- gtrefclk is routed to the tranceiver.
ibufds_gtrefclk : IBUFDS_GTE2
port map (
I => sgmiii.clkp,
IB => sgmiii.clkn,
CEB => '0',
O => gtrefclk_buf_i,
ODIV2 => open
);
bufhce_gtrefclk : BUFHCE
port map (
I => gtrefclk_buf_i,
CE => '1',
O => gtrefclk
);
-- The GT transceiver provides a 62.5MHz clock to the FPGA fabrix. This is
-- routed to an MMCM module where it is used to create phase and frequency
-- related 62.5MHz and 125MHz clock sources
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
--CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
-- STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 16.000,
CLKFBOUT_PHASE => 0.000,
--CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 8.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.5,
--CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => 16,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.5,
--CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 16.0,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => open,
CLKOUT0 => clkout0,
CLKOUT0B => open,
CLKOUT1 => clkout1,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => clkfbout,
CLKIN1 => txoutclk,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => mmcm_locked,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => mmcm_reset);
mmcm_reset <= reset or (not resetdone);
-- This 62.5MHz clock is placed onto global clock routing and is then used
-- for tranceiver TXUSRCLK/RXUSRCLK.
bufg_userclk: BUFG
port map (
I => clkout1,
O => userclk
);
-- This 125MHz clock is placed onto global clock routing and is then used
-- to clock all Ethernet core logic.
bufg_userclk2: BUFG
port map (
I => clkout0,
O => userclk2
);
-- This 62.5MHz clock is placed onto global clock routing and is then used
-- for tranceiver TXUSRCLK/RXUSRCLK.
bufg_rxuserclk: BUFG
port map (
I => rxoutclk,
O => rxuserclk
);
end generate;
-----------------------------------------------------------------------------
-- Sync Reset for user clock
-----------------------------------------------------------------------------
userclk2_rst : rstgen
generic map(syncin => 1, syncrst => 1)
port map(apb_rstn, userclk2, '1', usr2rstn, open);
-----------------------------------------------------------------------------
-- Transceiver PMA reset circuitry
-----------------------------------------------------------------------------
-- Create a reset pulse of a decent length
process(reset, apb_clk)
begin
if (reset = '1') then
pma_reset_pipe <= "1111";
elsif apb_clk'event and apb_clk = '1' then
pma_reset_pipe <= pma_reset_pipe(2 downto 0) & reset;
end if;
end process;
pma_reset <= pma_reset_pipe(3);
------------------------------------------------------------------------------
-- GMII (Aeroflex Gaisler) to GMII (Xilinx) style
------------------------------------------------------------------------------
-- 10/100Mbit TX Loic
process (usr2rstn,rtx,gmiio)
variable v : txregs;
begin
v := rtx;
v.cnt_en := '0';
v.gmii_tx_en_int := gmiio.tx_en;
if (gmiio.tx_en = '1' and rtx.gmii_tx_en_int = '0') then
v.count := 0;
elsif (v.count >= 9) and gmiio.speed = '1' then
v.count := 0;
elsif (v.count >= 99) and gmiio.speed = '0' then
v.count := 0;
else
v.count := rtx.count + 1;
end if;
case v.count is
when 0 =>
v.gmii_txd_int(3 downto 0) := gmiio.txd(3 downto 0);
v.cnt_en := '1';
when 5 =>
if gmiio.speed = '1' then
v.gmii_txd_int(7 downto 4) := gmiio.txd(3 downto 0);
v.cnt_en := '1';
end if;
when 50=>
if gmiio.speed = '0' then
v.gmii_txd_int(7 downto 4) := gmiio.txd(3 downto 0);
v.cnt_en := '1';
end if;
when 9 =>
if gmiio.speed = '1' then
v.gmii_txd := v.gmii_txd_int;
v.gmii_tx_en := '1';
v.gmii_tx_er := gmiio.tx_er;
if (gmiio.tx_en = '0' and rtx.keepalive <= 1) then v.gmii_tx_en := '0'; end if;
if (rtx.keepalive > 0) then v.keepalive := rtx.keepalive - 1; end if;
end if;
when 99 =>
if gmiio.speed = '0' then
v.gmii_txd := v.gmii_txd_int;
v.gmii_tx_en := '1';
v.gmii_tx_er := gmiio.tx_er;
if (gmiio.tx_en = '0' and rtx.keepalive <= 1) then v.gmii_tx_en := '0'; end if;
if (rtx.keepalive > 0) then v.keepalive := rtx.keepalive - 1; end if;
end if;
when others =>
null;
end case;
if (gmiio.tx_en = '0' and rtx.gmii_tx_en_int = '1') then
v.keepalive := 2;
end if;
if (gmiio.tx_en = '0' and rtx.gmii_tx_en_int = '0' and rtx.keepalive = 0) then
v := RESTX;
end if;
-- reset operation
if (not RESET_ALL) and (usr2rstn = '0') then
v := RESTX;
end if;
-- update registers
rintx <= v;
end process;
txegs : process(userclk2)
begin
if rising_edge(userclk2) then
rtx <= rintx;
if RESET_ALL and usr2rstn = '0' then
rtx <= RESTX;
end if;
end if;
end process;
-- 1000Mbit TX Logic (Bypass)
-- n/a
-- TX Mux Select
cnt_en <= '1' when (gmiio.gbit = '1') else rtx.cnt_en;
gmii_txd <= gmiio.txd when (gmiio.gbit = '1') else rtx.gmii_txd;
gmii_tx_en <= gmiio.tx_en when (gmiio.gbit = '1') else rtx.gmii_tx_en;
gmii_tx_er <= gmiio.tx_er when (gmiio.gbit = '1') else rtx.gmii_tx_er;
------------------------------------------------------------------------------
-- Instantiate the Core Block (core wrapper).
------------------------------------------------------------------------------
speed_is_10_100 <= not gmiio.gbit;
speed_is_100 <= gmiio.speed;
core_wrapper : sgmii
port map (
gtrefclk => gtrefclk,
txp => sgmiio.txp,
txn => sgmiio.txn,
rxp => sgmiii.rxp,
rxn => sgmiii.rxn,
resetdone => resetdone,
cplllock => OPEN ,
txoutclk => txoutclk,
rxoutclk => rxoutclk ,
userclk => userclk,
userclk2 => userclk2,
rxuserclk => rxuserclk ,
rxuserclk2 => rxuserclk ,
independent_clock_bufg => apb_clk,
pma_reset => pma_reset,
mmcm_locked => mmcm_locked,
sgmii_clk_r => sgmii_clk_r,
sgmii_clk_f => sgmii_clk_f,
sgmii_clk_en => sgmii_clk_en,
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_rxd => gmii_rxd_int,
gmii_rx_dv => gmii_rx_dv_int,
gmii_rx_er => gmii_rx_er_int,
gmii_isolate => gmii_isolate,
configuration_vector => configuration_vector,
an_interrupt => an_interrupt,
an_adv_config_vector => an_adv_config_vector,
an_restart_config => an_restart_config,
speed_is_10_100 => speed_is_10_100,
speed_is_100 => speed_is_100,
status_vector => status_vector_int,
reset => reset,
signal_detect => signal_detect,
gt0_qplloutclk_in => '0',
gt0_qplloutrefclk_in => '0'
);
------------------------------------------------------------------------------
-- GMII (Xilinx) to GMII (Aeroflex Gailers) style
------------------------------------------------------------------------------
---- 10/100Mbit RX Loic
process (usr2rstn,rrx,gmii_rx_dv_int,gmii_rxd_int,gmii_rx_er_int,sgmii_clk_en)
variable v : rxregs;
begin
v := rrx;
if (gmii_rx_dv_int = '1' and sgmii_clk_en = '1') then
v.count := 0;
v.gmii_rxd_int := gmii_rxd_int;
v.gmii_dv := '1';
v.keepalive := 1;
elsif (v.count >= 9) and gmiio.speed = '1' then
v.count := 0;
v.keepalive := rrx.keepalive - 1;
elsif (v.count >= 99) and gmiio.speed = '0' then
v.count := 0;
v.keepalive := rrx.keepalive - 1;
else
v.count := rrx.count + 1;
end if;
case v.count is
when 0 =>
v.gmii_rxd := v.gmii_rxd_int(3 downto 0) & v.gmii_rxd_int(3 downto 0);
v.gmii_rx_dv := v.gmii_dv;
when 5 =>
if gmiio.speed = '1' then
v.gmii_rxd := v.gmii_rxd_int(7 downto 4) & v.gmii_rxd_int(7 downto 4);
v.gmii_rx_dv := v.gmii_dv;
v.gmii_dv := '0';
end if;
when 50 =>
if gmiio.speed = '0' then
v.gmii_rxd := v.gmii_rxd_int(7 downto 4) & v.gmii_rxd_int(7 downto 4);
v.gmii_rx_dv := v.gmii_dv;
v.gmii_dv := '0';
end if;
when others =>
v.gmii_rxd := v.gmii_rxd;
v.gmii_rx_dv := '0';
end case;
v.gmii_rx_er := gmii_rx_er_int;
if (rrx.keepalive = 0 and gmii_rx_dv_int = '0') then
v := RESRX;
end if;
-- reset operation
if (not RESET_ALL) and (usr2rstn = '0') then
v := RESRX;
end if;
-- update registers
rinrx <= v;
end process;
rx100regs : process(userclk2)
begin
if rising_edge(userclk2) then
rrx <= rinrx;
if RESET_ALL and usr2rstn = '0' then
rrx <= RESRX;
end if;
end if;
end process;
---- 1000Mbit RX Logic (Bypass)
-- n/a
---- RX Mux Select
gmii_rxd <= gmii_rxd_int when (gmiio.gbit = '1') else rinrx.gmii_rxd;
gmii_rx_dv <= gmii_rx_dv_int when (gmiio.gbit = '1') else rinrx.gmii_rx_dv;
gmii_rx_er <= gmii_rx_er_int when (gmiio.gbit = '1') else rinrx.gmii_rx_er;
-----------------------------------------------------------------------------
-- Extra registers to ease CDC placement
-----------------------------------------------------------------------------
process (apb_clk)
begin
if apb_clk'event and apb_clk = '1' then
status_vector_apb <= status_vector_int;
end if;
end process;
---------------------------------------------------------------------------------------
-- APB Section
---------------------------------------------------------------------------------------
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
-- Extra registers to ease CDC placement
process (apb_clk)
begin
if apb_clk'event and apb_clk = '1' then
status_vector_apb1 <= (others => '0');
status_vector_apb2 <= (others => '0');
if autonegotiation = 1 then status_vector_apb2(17) <= '1'; else status_vector_apb2(17) <= '0'; end if;
if debugmem = 1 then status_vector_apb2(16) <= '1'; else status_vector_apb2(16) <= '0'; end if;
-- Register to detect a speed change
status_vector_apb1(15 downto 0) <= status_vector_apb;
status_vector_apb2 <= status_vector_apb1;
end if;
end process;
rgmiiapb : process(apb_rstn, r, apbi, status_vector_apb1, status_vector_apb2, RMemRgmiiiData, RMemRgmiiiRead, RMemRgmiioRead )
variable rdata : std_logic_vector(31 downto 0);
variable paddress : std_logic_vector(7 downto 2);
variable v : sgmiiregs;
begin
v := r;
paddress := (others => '0');
paddress(abits-1 downto 2) := apbi.paddr(abits-1 downto 2);
rdata := (others => '0');
-- read/write registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case paddress(7 downto 2) is
when "000000" =>
rdata(31 downto 0) := status_vector_apb2;
when "000001" =>
rdata(31 downto 0) := r.irq;
v.irq := (others => '0'); -- Interrupt is clear on read
when "000010" =>
rdata(31 downto 0) := r.mask;
when "000011" =>
rdata(4 downto 0) := r.configuration_vector;
when "000100" =>
rdata(15 downto 0) := r.an_adv_config_vector;
when others =>
null;
end case;
end if;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case paddress(7 downto 2) is
when "000000" =>
null;
when "000001" =>
null;
when "000010" =>
v.mask := apbi.pwdata(31 downto 0);
when "000011" =>
v.configuration_vector := apbi.pwdata(4 downto 0);
when "000100" =>
v.an_adv_config_vector := apbi.pwdata(15 downto 0);
when others =>
null;
end case;
end if;
-- Check interrupts
for i in 0 to status_vector_apb2'length-1 loop
if ((status_vector_apb1(i) xor status_vector_apb2(i)) and v.mask(i)) = '1' then
v.irq(i) := '1';
end if;
end loop;
-- reset operation
if (not RESET_ALL) and (apb_rstn = '0') then
v := RES;
end if;
-- update registers
rin <= v;
-- drive outputs
if apbi.psel(pindex) = '0' then
apbo.prdata <= (others => '0');
elsif RMemRgmiiiRead = '1' then
apbo.prdata(31 downto 16) <= (others => '0');
apbo.prdata(15 downto 0) <= RMemRgmiiiData;
elsif RMemRgmiioRead = '1' then
apbo.prdata(31 downto 16) <= (others => '0');
apbo.prdata(15 downto 0) <= RMemRgmiioData;
else
apbo.prdata <= rdata;
end if;
apbo.pirq <= (others => '0');
apbo.pirq(pirq) <= orv(v.irq);
end process;
regs : process(apb_clk)
begin
if rising_edge(apb_clk) then
r <= rin;
if RESET_ALL and apb_rstn = '0' then
r <= RES;
end if;
end if;
end process;
---------------------------------------------------------------------------------------
-- Debug Mem
---------------------------------------------------------------------------------------
debugmem1 : if (debugmem /= 0) generate
-- Write GMII IN data
process (userclk2)
begin -- process
if rising_edge(userclk2) then
WMemRgmiioData(15 downto 0) <= '0' & '0' & '0' & '0' & "00" & gmii_tx_er & gmii_tx_en & gmii_txd;
if (gmii_tx_en = '1') and ((WMemRgmiioAddr < "0111111110") or (WMemRgmiioAddr = "1111111111")) then
WMemRgmiioAddr <= WMemRgmiioAddr + 1;
WMemRgmiioWrEn <= '1';
else
if (gmii_tx_en = '0') then
WMemRgmiioAddr <= (others => '1');
else
WMemRgmiioAddr <= WMemRgmiioAddr;
end if;
WMemRgmiioWrEn <= '0';
end if;
if usr2rstn = '0' then
WMemRgmiioAddr <= (others => '0');
WMemRgmiioWrEn <= '0';
end if;
end if;
end process;
-- Read
RMemRgmiioRead <= apbi.paddr(10) and apbi.psel(pindex);
RMemRgmiioAddr <= "00" & apbi.paddr(10-1 downto 2);
gmiii0 : syncram_2p generic map (tech, 10, 16, 1, 0, 0) port map(
apb_clk, RMemRgmiioRead, RMemRgmiioAddr, RMemRgmiioData,
userclk2, WMemRgmiioWrEn, WMemRgmiioAddr(10-1 downto 0), WMemRgmiioData);
-- Write GMII IN data
process (userclk2)
begin -- process
if rising_edge(userclk2) then
if (gmii_rx_dv = '1') then
WMemRgmiiiData(15 downto 0) <= '0' & sgmii_clk_en & '0' & '0' & "00" & gmii_rx_er & gmii_rx_dv & gmii_rxd;
elsif (gmii_rx_dv_int = '0') then
WMemRgmiiiData(15 downto 0) <= (others => '0');
else
WMemRgmiiiData <= WMemRgmiiiData;
end if;
if (gmii_rx_dv = '1') and ((WMemRgmiiiAddr < "0111111110") or (WMemRgmiiiAddr = "1111111111")) then
WMemRgmiiiAddr <= WMemRgmiiiAddr + 1;
WMemRgmiiiWrEn <= '1';
else
if (gmii_rx_dv_int = '0') then
WMemRgmiiiAddr <= (others => '1');
WMemRgmiiiWrEn <= '0';
else
WMemRgmiiiAddr <= WMemRgmiiiAddr;
WMemRgmiiiWrEn <= '0';
end if;
end if;
if usr2rstn = '0' then
WMemRgmiiiAddr <= (others => '0');
WMemRgmiiiWrEn <= '0';
end if;
end if;
end process;
-- Read
RMemRgmiiiRead <= apbi.paddr(11) and apbi.psel(pindex);
RMemRgmiiiAddr <= "00" & apbi.paddr(10-1 downto 2);
rgmiii0 : syncram_2p generic map (tech, 10, 16, 1, 0, 0) port map(
apb_clk, RMemRgmiiiRead, RMemRgmiiiAddr, RMemRgmiiiData,
userclk2, WMemRgmiiiWrEn, WMemRgmiiiAddr(10-1 downto 0), WMemRgmiiiData);
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("sgmii" & tost(pindex) &
": SGMII rev " & tost(REVISION) & ", irq " & tost(pirq));
-- pragma translate_on
end top_level;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/atc18/pads_atc18.vhd | 1 | 10099 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: atcpads_gen
-- File: atcpads_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Atmel ATC18 pad wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package atcpads is
-- input pad
component pc33d00z port (pad : in std_logic; cin : out std_logic); end component;
-- input pad with pull-up
component pc33d00uz port (pad : in std_logic; cin : out std_logic); end component;
-- schmitt input pad
component pc33d20z port (pad : in std_logic; cin : out std_logic); end component;
-- schmitt input pad with pull-up
component pt33d20uz port (pad : inout std_logic; cin : out std_logic); end component;
-- output pads
component pt33o01z port (i : in std_logic; pad : out std_logic); end component;
component pt33o02z port (i : in std_logic; pad : out std_logic); end component;
component pt33o04z port (i : in std_logic; pad : out std_logic); end component;
component pt33o08z port (i : in std_logic; pad : out std_logic); end component;
-- tri-state output pads
component pt33t01z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t02z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t04z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t08z port (i, oen : in std_logic; pad : out std_logic); end component;
-- tri-state output pads with pull-up
component pt33t01uz port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t02uz port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t04uz port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t08uz port (i, oen : in std_logic; pad : out std_logic); end component;
-- bidirectional pads
component pt33b01z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b02z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b08z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b04z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
-- bidirectional pads with pull-up
component pt33b01uz
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b02uz
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b08uz
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b04uz
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
--PCI pads
component pp33o01z
port (i : in std_logic; pad : out std_logic);
end component;
component pp33b01z
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pp33t01z
port (i, oen : in std_logic; pad : out std_logic);
end component;
end;
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
-- pragma translate_off
library atc18;
use atc18.pc33d00z;
-- pragma translate_on
entity atc18_inpad is
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end;
architecture rtl of atc18_inpad is
component pc33d00z port (pad : in std_logic; cin : out std_logic); end component;
begin
pci0 : if level = pci33 generate
ip : pc33d00z port map (pad => pad, cin => o);
end generate;
gen0 : if level /= pci33 generate
ip : pc33d00z port map (pad => pad, cin => o);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library atc18;
use atc18.pp33b01z;
use atc18.pt33b01z;
use atc18.pt33b02z;
use atc18.pt33b08z;
use atc18.pt33b04z;
-- pragma translate_on
entity atc18_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end ;
architecture rtl of atc18_iopad is
component pp33b01z
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b01z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b02z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b08z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b04z
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
begin
pci0 : if level = pci33 generate
op : pp33b01z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
gen0 : if level /= pci33 generate
f1 : if (strength <= 4) generate
op : pt33b01z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
f2 : if (strength > 4) and (strength <= 8) generate
op : pt33b02z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
f3 : if (strength > 8) and (strength <= 16) generate
op : pt33b04z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
f4 : if (strength > 16) generate
op : pt33b08z port map (i => i, oen => en, pad => pad, cin => o);
end generate;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library atc18;
use atc18.pp33t01z;
use atc18.pt33o01z;
use atc18.pt33o02z;
use atc18.pt33o04z;
use atc18.pt33o08z;
-- pragma translate_on
entity atc18_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end ;
architecture rtl of atc18_outpad is
component pp33t01z
port (i, oen : in std_logic; pad : out std_logic);
end component;
component pt33o01z port (i : in std_logic; pad : out std_logic); end component;
component pt33o02z port (i : in std_logic; pad : out std_logic); end component;
component pt33o04z port (i : in std_logic; pad : out std_logic); end component;
component pt33o08z port (i : in std_logic; pad : out std_logic); end component;
signal gnd : std_logic;
begin
gnd <= '0';
pci0 : if level = pci33 generate
op : pp33t01z port map (i => i, oen => gnd, pad => pad);
end generate;
gen0 : if level /= pci33 generate
f4 : if (strength <= 4) generate
op : pt33o01z port map (i => i, pad => pad);
end generate;
f8 : if (strength > 4) and (strength <= 8) generate
op : pt33o02z port map (i => i, pad => pad);
end generate;
f16 : if (strength > 8) and (strength <= 16) generate
op : pt33o04z port map (i => i, pad => pad);
end generate;
f32 : if (strength > 16) generate
op : pt33o08z port map (i => i, pad => pad);
end generate;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library atc18;
use atc18.pp33t01z;
use atc18.pt33t01z;
use atc18.pt33t02z;
use atc18.pt33t04z;
use atc18.pt33t08z;
-- pragma translate_on
entity atc18_toutpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end ;
architecture rtl of atc18_toutpad is
component pp33t01z
port (i, oen : in std_logic; pad : out std_logic);
end component;
component pt33t01z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t02z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t04z port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t08z port (i, oen : in std_logic; pad : out std_logic); end component;
begin
pci0 : if level = pci33 generate
op : pp33t01z port map (i => i, oen => en, pad => pad);
end generate;
gen0 : if level /= pci33 generate
f4 : if (strength <= 4) generate
op : pt33t01z port map (i => i, oen => en, pad => pad);
end generate;
f8 : if (strength > 4) and (strength <= 8) generate
op : pt33t02z port map (i => i, oen => en, pad => pad);
end generate;
f16 : if (strength > 8) and (strength <= 16) generate
op : pt33t04z port map (i => i, oen => en, pad => pad);
end generate;
f32 : if (strength > 16) generate
op : pt33t08z port map (i => i, oen => en, pad => pad);
end generate;
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
entity atc18_clkpad is
generic (level : integer := 0; voltage : integer := 0);
port (pad : in std_logic; o : out std_logic);
end;
architecture rtl of atc18_clkpad is
begin
o <= pad;
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/maps/clkinv.vhd | 1 | 1889 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: clkinv
-- File: clkinv.vhd
-- Author: Fredrik Ringhage - Aeroflex Gaisler Research
-- Description: SET protected inverters for clock tree
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.gencomp.all;
use work.allclkgen.all;
entity clkinv is
generic(tech : integer := 0);
port(
i : in std_ulogic;
o : out std_ulogic
);
end entity;
architecture rtl of clkinv is
begin
tec : if has_clkinv(tech) = 1 generate
saed : if (tech = saed32) generate
x0 : clkinv_saed32 port map (i => i, o => o);
end generate;
dar : if (tech = dare) generate
x0 : clkinv_dare port map (i => i, o => o);
end generate;
end generate;
gen : if has_clkinv(tech) = 0 generate
o <= not i;
end generate;
end architecture;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-altera-ep2sgx90-av/prgmem.vhd | 3 | 5738 | ------------------------------------------------------
-- Program-Memory
------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use std.textio.all;
-- Important NOTE:
-- ---------------
--
-- The ROM_BITS generic controls the size of the internal
-- ROM. The ROM is located in upper part of program memory
-- and is initialized by the given (intel-).hex-file.
-- If there's no such file, everything is filled up with
-- 'null'. Everything before the ROM is always nulled.
-- If you don't want a System-ROM, just set ROM_BITS to 0.
entity prgmem is
generic (
INIT_FILE_NAME : string; -- => init file for rom
PRGM_MEM : positive := 12; -- => 4k word
MEM_WIDTH : positive := 32
);
port (
-- common signals
clk : in std_logic; -- normal system clock
reset : in std_logic;
-- access (r)
addr : in std_logic_vector(PRGM_MEM-1 downto 0);
data : out std_logic_vector(MEM_WIDTH-1 downto 0)
);
end entity;
architecture Behavioral of prgmem is
-- some constants
constant MEM_DEPTH : positive := 2**PRGM_MEM;
-- constant MEM_WIDTH : positive := ;
-- constant ROM_DEPTH : positive := 2**ROM_BITS ;
-- constant ROM_POS : integer := rom_start(PRGM_MEM, ROM_BITS);
-- declare memory type
type MEM_TYPE is array(0 to MEM_DEPTH - 1) of std_logic_vector(MEM_WIDTH-1 downto 0);
type BYTE_STRING is array(1 downto 0) of character;
type WORD_STRING is array(3 downto 0) of character;
function CHAR_TO_INT ( char : in character) return integer is
variable r : integer := 0;
begin
case char is
when 'A' => r := 10;
when 'B' => r := 11;
when 'C' => r := 12;
when 'D' => r := 13;
when 'E' => r := 14;
when 'F' => r := 15;
when 'a' => r := 10;
when 'b' => r := 11;
when 'c' => r := 12;
when 'd' => r := 13;
when 'e' => r := 14;
when 'f' => r := 15;
when '1' => r := 1;
when '2' => r := 2;
when '3' => r := 3;
when '4' => r := 4;
when '5' => r := 5;
when '6' => r := 6;
when '7' => r := 7;
when '8' => r := 8;
when '9' => r := 9;
when others => null;
end case;
return r;
end function;
function BYTE_TO_INT ( bytechars : in string(1 to 2)) return integer is
begin
return CHAR_TO_INT(bytechars(1))*16+CHAR_TO_INT(bytechars(2));
end function;
function WORD_TO_INT ( wordchars : in string(1 to 4)) return integer is
begin
return BYTE_TO_INT(wordchars(1) & wordchars(2))*256+BYTE_TO_INT(wordchars(3) & wordchars(4));
end function;
-- function for loading the init values
impure function InitRamFromFile (file_name : in string) return MEM_TYPE is
FILE init_file : text;-- is in file_name;
variable rline : line;
variable memory : MEM_TYPE;
-- variable offs : integer := 0;
variable count : integer;
variable linemode : integer;
variable addr : integer;
variable tmp_chr : character;
variable tmp_byte : string(1 to 2);--BYTE_STRING;
variable tmp_word : string(1 to 4);--WORD_STRING;
variable tmp_addr : integer;
variable tmp_v : std_logic_vector(MEM_WIDTH-1 downto 0);
begin
-- first just null everything
for i in 0 to MEM_DEPTH-1 loop
memory(i) := (others => '0');
end loop;
file_open(init_file, file_name, READ_MODE);
-- read rom file
while (not endfile(init_file)) loop
readline (init_file, rline);
exit when endfile (init_file);
read (rline, tmp_chr);
if tmp_chr = ':' then --beginning of line is correct
--how much to read
read (rline, tmp_byte);
count := BYTE_TO_INT(tmp_byte);
--addr
read (rline, tmp_word);
addr := WORD_TO_INT(tmp_word);
--line mode
read (rline, tmp_byte);
linemode := BYTE_TO_INT(tmp_byte);
if linemode = 0 then
-- loop every PROGRAM-WORD
for i in 0 to (count/(MEM_WIDTH/8) - 1) loop
tmp_v := (others=>'0');
-- loop for every BYTE IN PROGRAM-WORD
for j in 0 to MEM_WIDTH/8-1 loop
read (rline, tmp_byte);
tmp_v((j+1)*8-1 downto j*8) := std_logic_vector(to_unsigned(BYTE_TO_INT(tmp_byte),8));
end loop;
-- store in memory
memory(addr/(MEM_WIDTH/8) + i) := tmp_v;
end loop;
end if;
end if;
end loop;
file_close(init_file);
return memory;
end function;
-- define memory and initialize it
signal memory : MEM_TYPE := InitRamFromFile(INIT_FILE_NAME);
signal mem_addr : std_logic_vector(PRGM_MEM-1 downto 0);
signal mem_doa : std_logic_vector(15 downto 0);
signal mem_we : std_logic;
-- output register
signal reg_cmd_out : std_logic_vector(MEM_WIDTH-1 downto 0);
signal reg_const_out : std_logic_vector(MEM_WIDTH-1 downto 0);
signal reg_lpmspm : std_logic_vector(MEM_WIDTH-1 downto 0);
begin
mem_addr <= addr;
---------------------------------------------------
-- infering the block ram
process(clk)
begin
if clk'event and clk = '1' then
data <= memory(to_integer(unsigned(addr)));
end if;
end process;
end architecture;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/sim/phy.vhd | 1 | 24601 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
----------------------------------------------------------------------------
-- Entity: phy
-- File: phy.vhd
-- Description: Simulation model of an Ethernet PHY
-- Author: Marko Isomaki
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
library grlib;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
entity phy is
generic(
address : integer range 0 to 31 := 0;
extended_regs : integer range 0 to 1 := 1;
aneg : integer range 0 to 1 := 1;
base100_t4 : integer range 0 to 1 := 0;
base100_x_fd : integer range 0 to 1 := 1;
base100_x_hd : integer range 0 to 1 := 1;
fd_10 : integer range 0 to 1 := 1;
hd_10 : integer range 0 to 1 := 1;
base100_t2_fd : integer range 0 to 1 := 1;
base100_t2_hd : integer range 0 to 1 := 1;
base1000_x_fd : integer range 0 to 1 := 0;
base1000_x_hd : integer range 0 to 1 := 0;
base1000_t_fd : integer range 0 to 1 := 1;
base1000_t_hd : integer range 0 to 1 := 1;
rmii : integer range 0 to 1 := 0;
rgmii : integer range 0 to 1 := 0
);
port(
rstn : in std_logic;
mdio : inout std_logic;
tx_clk : out std_logic;
rx_clk : out std_logic;
rxd : out std_logic_vector(7 downto 0);
rx_dv : out std_logic;
rx_er : out std_logic;
rx_col : out std_logic;
rx_crs : out std_logic;
txd : in std_logic_vector(7 downto 0);
tx_en : in std_logic;
tx_er : in std_logic;
mdc : in std_logic;
gtx_clk : in std_logic
);
end;
architecture behavioral of phy is
type mdio_state_type is (idle, start_of_frame, start_of_frame2, op, phyad, regad,
ta, rdata, wdata);
type ctrl_reg_type is record
reset : std_ulogic;
loopback : std_ulogic;
speedsel : std_logic_vector(1 downto 0);
anegen : std_ulogic;
powerdown : std_ulogic;
isolate : std_ulogic;
restartaneg : std_ulogic;
duplexmode : std_ulogic;
coltest : std_ulogic;
end record;
type status_reg_type is record
base100_t4 : std_ulogic;
base100_x_fd : std_ulogic;
base100_x_hd : std_ulogic;
fd_10 : std_ulogic;
hd_10 : std_ulogic;
base100_t2_fd : std_ulogic;
base100_t2_hd : std_ulogic;
extstat : std_ulogic;
mfpreamblesup : std_ulogic;
anegcmpt : std_ulogic;
remfault : std_ulogic;
anegability : std_ulogic;
linkstat : std_ulogic;
jabdetect : std_ulogic;
extcap : std_ulogic;
end record;
type aneg_ab_type is record
next_page : std_ulogic;
remote_fault : std_ulogic;
tech_ability : std_logic_vector(7 downto 0);
selector : std_logic_vector(4 downto 0);
end record;
type aneg_exp_type is record
par_detct_flt : std_ulogic;
lp_np_able : std_ulogic;
np_able : std_ulogic;
page_rx : std_ulogic;
lp_aneg_able : std_ulogic;
end record;
type aneg_nextpage_type is record
next_page : std_ulogic;
message_page : std_ulogic;
ack2 : std_ulogic;
toggle : std_ulogic;
message : std_logic_vector(10 downto 0);
end record;
type mst_slv_ctrl_type is record
tmode : std_logic_vector(2 downto 0);
manualcfgen : std_ulogic;
cfgval : std_ulogic;
porttype : std_ulogic;
base1000_t_fd : std_ulogic;
base1000_t_hd : std_ulogic;
end record;
type mst_slv_status_type is record
cfgfault : std_ulogic;
cfgres : std_ulogic;
locrxstate : std_ulogic;
remrxstate : std_ulogic;
lpbase1000_t_fd : std_ulogic;
lpbase1000_t_hd : std_ulogic;
idlerrcnt : std_logic_vector(7 downto 0);
end record;
type extended_status_reg_type is record
base1000_x_fd : std_ulogic;
base1000_x_hd : std_ulogic;
base1000_t_fd : std_ulogic;
base1000_t_hd : std_ulogic;
end record;
type reg_type is record
state : mdio_state_type;
cnt : integer;
op : std_logic_vector(1 downto 0);
phyad : std_logic_vector(4 downto 0);
regad : std_logic_vector(4 downto 0);
wr : std_ulogic;
regtmp : std_logic_vector(15 downto 0);
-- MII management registers
ctrl : ctrl_reg_type;
status : status_reg_type;
anegadv : aneg_ab_type;
aneglp : aneg_ab_type;
anegexp : aneg_exp_type;
anegnptx : aneg_nextpage_type;
anegnplp : aneg_nextpage_type;
mstslvctrl : mst_slv_ctrl_type;
mstslvstat : mst_slv_status_type;
extstatus : extended_status_reg_type;
rstcnt : integer;
anegcnt : integer;
end record;
signal r, rin : reg_type;
signal int_clk : std_ulogic := '0';
signal clkslow : std_ulogic := '0';
signal rcnt : integer;
signal anegact : std_ulogic;
begin
--mdio signal pull-up
int_clk <= not int_clk after 10 ns when rmii = 1 else
not int_clk after 4 ns when r.ctrl.speedsel = "01" else
not int_clk after 20 ns when r.ctrl.speedsel = "10" else
not int_clk after 200 ns when r.ctrl.speedsel = "00";
clkslow <= not clkslow after 20 ns when r.ctrl.speedsel = "10" else
not clkslow after 200 ns;
-- rstdelay : process
-- begin
-- loop
-- rstd <= '0';
-- while r.ctrl.reset /= '1' loop
-- wait on r.ctrl.reset;
-- end loop;
-- rstd <= '1';
-- while rstn = '0' loop
-- wait on rstn;
-- end loop;
-- wait on rstn for 3 us;
-- rstd <= '0';
-- wait on rstn until r.ctrl.reset = '0' for 5 us;
-- end loop;
-- end process;
anegproc : process is
begin
loop
anegact <= '0';
while rstn /= '1' loop
wait on rstn;
end loop;
while rstn = '1' loop
if r.ctrl.anegen = '0' then
anegact <= '0';
wait on rstn, r.ctrl.anegen, r.ctrl.restartaneg;
else
if r.ctrl.restartaneg = '1' then
anegact <= '1';
wait on rstn, r.ctrl.restartaneg, r.ctrl.anegen for 2 us;
anegact <= '0';
wait on rstn, r.ctrl.anegen until r.ctrl.restartaneg = '0';
if (rstn and r.ctrl.anegen) = '1' then
wait on rstn, r.ctrl.anegen, r.ctrl.restartaneg;
end if;
else
anegact <= '0';
wait on rstn, r.ctrl.restartaneg, r.ctrl.anegen;
end if;
end if;
end loop;
end loop;
end process;
mdiocomb : process(rstn, r, anegact, mdio) is
variable v : reg_type;
begin
v := r;
if anegact = '0' then
v.ctrl.restartaneg := '0';
end if;
case r.state is
when idle =>
mdio <= 'Z';
if to_X01(mdio) = '1' then
v.cnt := v.cnt + 1;
if v.cnt = 31 then
v.state := start_of_frame; v.cnt := 0;
end if;
else
v.cnt := 0;
end if;
when start_of_frame =>
if to_X01(mdio) = '0' then
v.state := start_of_frame2;
elsif to_X01(mdio) /= '1' then
v.state := idle;
end if;
when start_of_frame2 =>
if to_X01(mdio) = '1' then
v.state := op;
else
v.state := idle;
end if;
when op =>
v.cnt := v.cnt + 1;
v.op := r.op(0) & to_X01(mdio);
if r.cnt = 1 then
if (v.op = "01") or (v.op = "10") then
v.state := phyad; v.cnt := 0;
else
v.state := idle; v.cnt := 0;
end if;
end if;
when phyad =>
v.phyad := r.phyad(3 downto 0) & to_X01(mdio);
v.cnt := v.cnt + 1;
if r.cnt = 4 then
v.state := regad; v.cnt := 0;
end if;
when regad =>
v.regad := r.regad(3 downto 0) & to_X01(mdio);
v.cnt := v.cnt + 1;
if r.cnt = 4 then
v.cnt := 0;
if conv_integer(r.phyad) = address then
v.state := ta;
else
v.state := idle;
end if;
end if;
when ta =>
v.cnt := r.cnt + 1;
if r.cnt = 0 then
if (r.op = "01") and to_X01(mdio) /= '1' then
v.cnt := 0; v.state := idle;
end if;
else
if r.op = "10" then
mdio <= '0'; v.cnt := 0; v.state := rdata;
case r.regad is
when "00000" => --ctrl (basic)
v.regtmp := r.ctrl.reset & r.ctrl.loopback &
r.ctrl.speedsel(1) & r.ctrl.anegen & r.ctrl.powerdown &
r.ctrl.isolate & r.ctrl.restartaneg & r.ctrl.duplexmode &
r.ctrl.coltest & r.ctrl.speedsel(0) & "000000";
when "00001" => --statuc (basic)
v.regtmp := r.status.base100_t4 & r.status.base100_x_fd &
r.status.base100_x_hd & r.status.fd_10 & r.status.hd_10 &
r.status.base100_t2_fd & r.status.base100_t2_hd &
r.status.extstat & '0' & r.status.mfpreamblesup &
r.status.anegcmpt & r.status.remfault & r.status.anegability &
r.status.linkstat & r.status.jabdetect & r.status.extcap;
when "00010" => --PHY ID (extended)
if extended_regs = 1 then
v.regtmp := X"BBCD";
else
v.cnt := 0; v.state := idle;
end if;
when "00011" => --PHY ID (extended)
if extended_regs = 1 then
v.regtmp := X"9C83";
else
v.cnt := 0; v.state := idle;
end if;
when "00100" => --Auto-neg adv. (extended)
if extended_regs = 1 then
v.regtmp := r.anegadv.next_page & '0' & r.anegadv.remote_fault &
r.anegadv.tech_ability & r.anegadv.selector;
else
v.cnt := 0; v.state := idle;
end if;
when "00101" => --Auto-neg link partner ability (extended)
if extended_regs = 1 then
v.regtmp := r.aneglp.next_page & '0' & r.aneglp.remote_fault &
r.aneglp.tech_ability & r.aneglp.selector;
else
v.cnt := 0; v.state := idle;
end if;
when "00110" => --Auto-neg expansion (extended)
if extended_regs = 1 then
v.regtmp := "00000000000" & r.anegexp.par_detct_flt &
r.anegexp.lp_np_able & r.anegexp.np_able & r.anegexp.page_rx &
r.anegexp.lp_aneg_able;
else
v.cnt := 0; v.state := idle;
end if;
when "00111" => --Auto-neg next page (extended)
if extended_regs = 1 then
v.regtmp := r.anegnptx.next_page & '0' & r.anegnptx.message_page &
r.anegnptx.ack2 & r.anegnptx.toggle & r.anegnptx.message;
else
v.cnt := 0; v.state := idle;
end if;
when "01000" => --Auto-neg link partner received next page (extended)
if extended_regs = 1 then
v.regtmp := r.anegnplp.next_page & '0' & r.anegnplp.message_page &
r.anegnplp.ack2 & r.anegnplp.toggle & r.anegnplp.message;
else
v.cnt := 0; v.state := idle;
end if;
when "01001" => --Master-slave control (extended)
if extended_regs = 1 then
v.regtmp := r.mstslvctrl.tmode & r.mstslvctrl.manualcfgen &
r.mstslvctrl.cfgval & r.mstslvctrl.porttype &
r.mstslvctrl.base1000_t_fd & r.mstslvctrl.base1000_t_hd &
"00000000";
else
v.cnt := 0; v.state := idle;
end if;
when "01010" => --Master-slave status (extended)
if extended_regs = 1 then
v.regtmp := r.mstslvstat.cfgfault & r.mstslvstat.cfgres &
r.mstslvstat.locrxstate & r.mstslvstat.remrxstate &
r.mstslvstat.lpbase1000_t_fd & r.mstslvstat.lpbase1000_t_hd &
"00" & r.mstslvstat.idlerrcnt;
else
v.cnt := 0; v.state := idle;
end if;
when "01111" =>
if (base1000_x_fd = 1) or (base1000_x_hd = 1) or
(base1000_t_fd = 1) or (base1000_t_hd = 1) then
v.regtmp := r.extstatus.base1000_x_fd &
r.extstatus.base1000_x_hd &
r.extstatus.base1000_t_fd &
r.extstatus.base1000_t_hd & X"000";
else
v.regtmp := (others => '0');
end if;
when others =>
--PHY shall not drive MDIO when unimplemented registers
--are accessed
v.cnt := 0; v.state := idle;
v.regtmp := (others => '0');
end case;
if r.ctrl.reset = '1' then
if r.regad = "00000" then
v.regtmp := X"8000";
else
v.regtmp := X"0000";
end if;
end if;
else
if to_X01(mdio) /= '0'then
v.cnt := 0; v.state := idle;
else
v.cnt := 0; v.state := wdata;
end if;
end if;
end if;
when rdata =>
v.cnt := r.cnt + 1;
mdio <= r.regtmp(15-r.cnt);
if r.cnt = 15 then
v.state := idle; v.cnt := 0;
end if;
when wdata =>
v.cnt := r.cnt + 1;
v.regtmp := r.regtmp(14 downto 0) & to_X01(mdio);
if r.cnt = 15 then
v.state := idle; v.cnt := 0;
if r.ctrl.reset = '0' then
case r.regad is
when "00000" =>
v.ctrl.reset := v.regtmp(15);
v.ctrl.loopback := v.regtmp(14);
v.ctrl.speedsel(1) := v.regtmp(13);
v.ctrl.anegen := v.regtmp(12);
v.ctrl.powerdown := v.regtmp(11);
v.ctrl.isolate := v.regtmp(10);
v.ctrl.restartaneg := v.regtmp(9);
v.ctrl.duplexmode := v.regtmp(8);
v.ctrl.coltest := v.regtmp(7);
v.ctrl.speedsel(0) := v.regtmp(6);
when "00100" =>
if extended_regs = 1 then
v.anegadv.remote_fault := r.regtmp(13);
v.anegadv.tech_ability := r.regtmp(12 downto 5);
v.anegadv.selector := r.regtmp(4 downto 0);
end if;
when "00111" =>
if extended_regs = 1 then
v.anegnptx.next_page := r.regtmp(15);
v.anegnptx.message_page := r.regtmp(13);
v.anegnptx.ack2 := r.regtmp(12);
v.anegnptx.message := r.regtmp(10 downto 0);
end if;
when "01001" =>
if extended_regs = 1 then
v.mstslvctrl.tmode := r.regtmp(15 downto 13);
v.mstslvctrl.manualcfgen := r.regtmp(12);
v.mstslvctrl.cfgval := r.regtmp(11);
v.mstslvctrl.porttype := r.regtmp(10);
v.mstslvctrl.base1000_t_fd := r.regtmp(9);
v.mstslvctrl.base1000_t_hd := r.regtmp(8);
end if;
when others => --no writable bits for other regs
null;
end case;
end if;
end if;
when others =>
null;
end case;
if r.rstcnt > 19 then
v.ctrl.reset := '0'; v.rstcnt := 0;
else
v.rstcnt := r.rstcnt + 1;
end if;
if (v.ctrl.reset and not r.ctrl.reset) = '1' then
v.rstcnt := 0;
end if;
if r.ctrl.anegen = '1' then
if r.anegcnt < 10 then
v.anegcnt := r.anegcnt + 1;
else
v.status.anegcmpt := '1';
if (base1000_x_fd = 1) or (base1000_x_hd = 1) or
(r.mstslvctrl.base1000_t_fd = '1') or
(r.mstslvctrl.base1000_t_hd = '1') then
v.ctrl.speedsel(1 downto 0) := "01";
elsif (r.anegadv.tech_ability(4) = '1') or
(r.anegadv.tech_ability(3) = '1') or
(r.anegadv.tech_ability(2) = '1') or
(base100_t2_fd = 1) or (base100_t2_hd = 1) then
v.ctrl.speedsel(1 downto 0) := "10";
else
v.ctrl.speedsel(1 downto 0) := "00";
end if;
if ((base1000_x_fd = 1) or (r.mstslvctrl.base1000_t_fd = '1')) or
(((base100_t2_fd = 1) or (r.anegadv.tech_ability(3) = '1')) and
(r.mstslvctrl.base1000_t_hd = '0') and (base1000_x_hd = 0)) or
((r.anegadv.tech_ability(1) = '1') and (base100_t2_hd = 0) and
(r.anegadv.tech_ability(4) = '0') and
(r.anegadv.tech_ability(2) = '0')) then
v.ctrl.duplexmode := '1';
else
v.ctrl.duplexmode := '0';
end if;
end if;
end if;
if r.ctrl.restartaneg = '1' then
v.anegcnt := 0;
v.status.anegcmpt := '0';
v.ctrl.restartaneg := '0';
end if;
rin <= v;
end process;
reg : process(rstn, mdc) is
begin
if rising_edge(mdc) then
r <= rin;
end if;
-- -- RESET DELAY
-- if rstd = '1' then
-- r.ctrl.reset <= '1';
-- else
-- r.ctrl.reset <= '0';
-- end if;
-- RESET
if (r.ctrl.reset or not rstn) = '1' then
r.ctrl.loopback <= '1'; r.anegcnt <= 0;
if (base1000_x_hd = 1) or (base1000_x_fd = 1) or (base1000_t_hd = 1) or
(base1000_t_fd = 1) then
r.ctrl.speedsel <= "01";
elsif (base100_x_hd = 1) or (base100_t2_hd = 1) or (base100_x_fd = 1) or
(base100_t2_fd = 1) or (base100_t4 = 1) then
r.ctrl.speedsel <= "10";
else
r.ctrl.speedsel <= "00";
end if;
r.ctrl.anegen <= conv_std_logic(aneg = 1);
r.ctrl.powerdown <= '0';
r.ctrl.isolate <= '0';
r.ctrl.restartaneg <= '0';
if (base100_x_hd = 0) and (hd_10 = 0) and (base100_t2_hd = 0) and
(base1000_x_hd = 0) and (base1000_t_hd = 0) then
r.ctrl.duplexmode <= '1';
else
r.ctrl.duplexmode <= '0';
end if;
r.ctrl.coltest <= '0';
r.status.base100_t4 <= conv_std_logic(base100_t4 = 1);
r.status.base100_x_fd <= conv_std_logic(base100_x_fd = 1);
r.status.base100_x_hd <= conv_std_logic(base100_x_hd = 1);
r.status.fd_10 <= conv_std_logic(fd_10 = 1);
r.status.hd_10 <= conv_std_logic(hd_10 = 1);
r.status.base100_t2_fd <= conv_std_logic(base100_t2_fd = 1);
r.status.base100_t2_hd <= conv_std_logic(base100_t2_hd = 1);
r.status.extstat <= conv_std_logic((base1000_x_fd = 1) or
(base1000_x_hd = 1) or
(base1000_t_fd = 1) or
(base1000_t_hd = 1));
r.status.mfpreamblesup <= '0';
r.status.anegcmpt <= '0';
r.status.remfault <= '0';
r.status.anegability <= conv_std_logic(aneg = 1);
r.status.linkstat <= '0';
r.status.jabdetect <= '0';
r.status.extcap <= conv_std_logic(extended_regs = 1);
r.anegadv.next_page <= '0';
r.anegadv.remote_fault <= '0';
r.anegadv.tech_ability <= "000" & conv_std_logic(base100_t4 = 1) &
conv_std_logic(base100_x_fd = 1) & conv_std_logic(base100_x_hd = 1) &
conv_std_logic(fd_10 = 1) & conv_std_logic(hd_10 = 1);
r.anegadv.selector <= "00001";
r.aneglp.next_page <= '0';
r.aneglp.remote_fault <= '0';
r.aneglp.tech_ability <= "000" & conv_std_logic(base100_t4 = 1) &
conv_std_logic(base100_x_fd = 1) & conv_std_logic(base100_x_hd = 1) &
conv_std_logic(fd_10 = 1) & conv_std_logic(hd_10 = 1);
r.aneglp.selector <= "00001";
r.anegexp.par_detct_flt <= '0';
r.anegexp.lp_np_able <= '0';
r.anegexp.np_able <= '0';
r.anegexp.page_rx <= '0';
r.anegexp.lp_aneg_able <= '0';
r.anegnptx.next_page <= '0';
r.anegnptx.message_page <= '1';
r.anegnptx.ack2 <= '0';
r.anegnptx.toggle <= '0';
r.anegnptx.message <= "00000000001";
r.anegnplp.next_page <= '0';
r.anegnplp.message_page <= '1';
r.anegnplp.ack2 <= '0';
r.anegnplp.toggle <= '0';
r.anegnplp.message <= "00000000001";
r.mstslvctrl.tmode <= (others => '0');
r.mstslvctrl.manualcfgen <= '0';
r.mstslvctrl.cfgval <= '0';
r.mstslvctrl.porttype <= '0';
r.mstslvctrl.base1000_t_fd <= conv_std_logic(base1000_t_fd = 1);
r.mstslvctrl.base1000_t_hd <= conv_std_logic(base1000_t_fd = 1);
r.mstslvstat.cfgfault <= '0';
r.mstslvstat.cfgres <= '1';
r.mstslvstat.locrxstate <= '1';
r.mstslvstat.remrxstate <= '1';
r.mstslvstat.lpbase1000_t_fd <= conv_std_logic(base1000_t_fd = 1);
r.mstslvstat.lpbase1000_t_hd <= conv_std_logic(base1000_t_fd = 1);
r.mstslvstat.idlerrcnt <= (others => '0');
r.extstatus.base1000_x_fd <= conv_std_logic(base1000_x_fd = 1);
r.extstatus.base1000_x_hd <= conv_std_logic(base1000_x_hd = 1);
r.extstatus.base1000_t_fd <= conv_std_logic(base1000_t_fd = 1);
r.extstatus.base1000_t_hd <= conv_std_logic(base1000_t_hd = 1);
end if;
if rstn = '0' then
r.cnt <= 0; r.state <= idle; r.rstcnt <= 0;
r.ctrl.reset <= '1';
end if;
end process;
loopback_sel : process(r.ctrl.loopback, int_clk, gtx_clk, r.ctrl.speedsel, txd, tx_en) is
begin
if r.ctrl.loopback = '1' then
if rmii = 0 then
rx_col <= '0'; rx_crs <= tx_en; rx_dv <= tx_en; rx_er <= tx_er;
rxd <= txd;
if r.ctrl.speedsel /= "01" then
rx_clk <= int_clk; tx_clk <= int_clk;
else
rx_clk <= gtx_clk; tx_clk <= clkslow;
end if;
else
rx_dv <= '1'; rx_er <= '1'; --unused should not affect anything
rx_col <= '0'; rx_crs <= tx_en;
if tx_en = '0' then
rxd(1 downto 0) <= "00";
else
rxd(1 downto 0) <= txd(1 downto 0);
end if;
if rgmii = 1 then
if (gtx_clk = '1' and tx_en = '0') then
rxd(3 downto 0) <= r.ctrl.duplexmode & r.ctrl.speedsel & r.status.linkstat;
end if;
end if;
rx_clk <= '0'; tx_clk <= '0';
end if;
else
rx_col <= '0'; rx_crs <= '0'; rx_dv <= '0'; rx_er <= '0';
rxd <= (others => '0');
if rgmii = 1 then
if (gtx_clk = '1') then
rxd(3 downto 0) <= r.ctrl.duplexmode & r.ctrl.speedsel & r.status.linkstat;
end if;
end if;
if rmii = 0 then
if r.ctrl.speedsel /= "01" then
rx_clk <= int_clk; tx_clk <= int_clk after 3 ns;
else
rx_clk <= gtx_clk; tx_clk <= clkslow;
end if;
else
rx_clk <= int_clk; tx_clk <= int_clk after 3 ns;
end if;
end if;
end process;
end;
-- pragma translate_on
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/sim/sram16.vhd | 1 | 2363 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sram16
-- File: sram16.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Simulation model of generic 16-bit async SRAM
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library gaisler;
use gaisler.sim.all;
library grlib;
use grlib.stdlib.all;
entity sram16 is
generic (
index : integer := 0; -- Byte lane (0 - 3)
abits: Positive := 10; -- Default 10 address bits (1 Kbyte)
echk : integer := 0; -- Generate EDAC checksum
tacc : integer := 10; -- access time (ns)
fname : string := "ram.dat"; -- File to read from
clear : integer := 0); -- clear memory
port (
a : in std_logic_vector(abits-1 downto 0);
d : inout std_logic_vector(15 downto 0);
lb : in std_logic;
ub : in std_logic;
ce : in std_logic;
we : in std_ulogic;
oe : in std_ulogic);
end;
architecture sim of sram16 is
signal cex : std_logic_vector(0 to 1);
begin
cex(0) <= ce or lb; cex(1) <= ce or ub;
sr0 : sram generic map (index+1, abits, tacc, fname, clear)
port map (a, d(7 downto 0), cex(0), we, oe);
sr1 : sram generic map (index, abits, tacc, fname, clear)
port map (a, d(15 downto 8), cex(1), we, oe);
end sim;
-- pragma translate_on
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/spw/wrapper/grspw_gen.vhd | 1 | 11111 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grspw_gen
-- File: grspw_gen.vhd
-- Author: Marko Isomaki - Gaisler Research
-- Description: Generic GRSPW core
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library spw;
use spw.spwcomp.all;
entity grspw_gen is
generic(
tech : integer := 0;
sysfreq : integer := 10000;
usegen : integer range 0 to 1 := 1;
nsync : integer range 1 to 2 := 1;
rmap : integer range 0 to 2 := 0;
rmapcrc : integer range 0 to 1 := 0;
fifosize1 : integer range 4 to 32 := 32;
fifosize2 : integer range 16 to 64 := 64;
rxclkbuftype : integer range 0 to 2 := 0;
rxunaligned : integer range 0 to 1 := 0;
rmapbufs : integer range 2 to 8 := 4;
ft : integer range 0 to 2 := 0;
scantest : integer range 0 to 1 := 0;
techfifo : integer range 0 to 1 := 1;
ports : integer range 1 to 2 := 1;
memtech : integer := 0;
nodeaddr : integer range 0 to 255 := 254;
destkey : integer range 0 to 255 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txclk : in std_ulogic;
rxclk : in std_logic_vector(1 downto 0);
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--spw in
d : in std_logic_vector(1 downto 0);
nd : in std_logic_vector(9 downto 0);
dconnect : in std_logic_vector(3 downto 0);
--spw out
do : out std_logic_vector(1 downto 0);
so : out std_logic_vector(1 downto 0);
rxrsto : out std_ulogic;
--time iface
tickin : in std_ulogic;
tickout : out std_ulogic;
--irq
irq : out std_logic;
--misc
clkdiv10 : in std_logic_vector(7 downto 0);
dcrstval : in std_logic_vector(9 downto 0);
timerrstval : in std_logic_vector(11 downto 0);
--rmapen
rmapen : in std_ulogic;
rmapnodeaddr : in std_logic_vector(7 downto 0);
linkdis : out std_ulogic;
testclk : in std_ulogic := '0';
testrst : in std_ulogic := '0';
testen : in std_ulogic := '0'
);
end entity;
architecture rtl of grspw_gen is
constant fabits1 : integer := log2(fifosize1);
constant fabits2 : integer := log2(fifosize2);
constant rfifo : integer := 5 + log2(rmapbufs);
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(4 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(4 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(4 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(4 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--nchar fifo
signal ncrenable : std_ulogic;
signal ncraddress : std_logic_vector(5 downto 0);
signal ncwrite : std_ulogic;
signal ncwdata : std_logic_vector(8 downto 0);
signal ncwaddress : std_logic_vector(5 downto 0);
signal ncrdata : std_logic_vector(8 downto 0);
--rmap buf
signal rmrenable : std_ulogic;
signal rmrenablex : std_ulogic;
signal rmraddress : std_logic_vector(7 downto 0);
signal rmwrite : std_ulogic;
signal rmwdata : std_logic_vector(7 downto 0);
signal rmwaddress : std_logic_vector(7 downto 0);
signal rmrdata : std_logic_vector(7 downto 0);
attribute syn_netlist_hierarchy : boolean;
attribute syn_netlist_hierarchy of rtl : architecture is false;
begin
grspwc0 : grspwc
generic map(
sysfreq => sysfreq,
usegen => usegen,
nsync => nsync,
rmap => rmap,
rmapcrc => rmapcrc,
fifosize1 => fifosize1,
fifosize2 => fifosize2,
rxunaligned => rxunaligned,
rmapbufs => rmapbufs,
scantest => scantest,
ports => ports,
tech => tech,
nodeaddr => nodeaddr,
destkey => destkey)
port map(
rst => rst,
clk => clk,
txclk => txclk,
--ahb mst in
hgrant => hgrant,
hready => hready,
hresp => hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => hbusreq,
hlock => hlock,
htrans => htrans,
haddr => haddr,
hwrite => hwrite,
hsize => hsize,
hburst => hburst,
hprot => hprot,
hwdata => hwdata,
--apb slv in
psel => psel,
penable => penable,
paddr => paddr,
pwrite => pwrite,
pwdata => pwdata,
--apb slv out
prdata => prdata,
--spw in
d => d,
nd => nd,
dconnect => dconnect,
--spw out
do => do,
so => so,
rxrsto => rxrsto,
--time iface
tickin => tickin,
tickout => tickout,
--clk bufs
rxclki => rxclk,
--irq
irq => irq,
--misc
clkdiv10 => clkdiv10,
dcrstval => dcrstval,
timerrstval => timerrstval,
--rmapen
rmapen => rmapen,
rmapnodeaddr => rmapnodeaddr,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--nchar fifo
ncrenable => ncrenable,
ncraddress => ncraddress,
ncwrite => ncwrite,
ncwdata => ncwdata,
ncwaddress => ncwaddress,
ncrdata => ncrdata,
--rmap buf
rmrenable => rmrenable,
rmraddress => rmraddress,
rmwrite => rmwrite,
rmwdata => rmwdata,
rmwaddress => rmwaddress,
rmrdata => rmrdata,
linkdis => linkdis,
testclk => clk,
testrst => testrst,
testen => testen
);
ntst: if scantest = 0 generate
rmrenablex <= rmrenable;
end generate;
tst: if scantest = 1 generate
rmrenablex <= rmrenable and not testen;
end generate;
------------------------------------------------------------------------------
-- FIFOS ---------------------------------------------------------------------
------------------------------------------------------------------------------
nft : if ft = 0 generate
--receiver AHB FIFO
rx_ram0 : syncram_2p generic map(memtech*techfifo, fabits1, 32)
port map(clk, rxrenable, rxraddress(fabits1-1 downto 0),
rxrdata, clk, rxwrite,
rxwaddress(fabits1-1 downto 0), rxwdata);
--receiver nchar FIFO
rx_ram1 : syncram_2p generic map(memtech*techfifo, fabits2, 9)
port map(clk, ncrenable, ncraddress(fabits2-1 downto 0),
ncrdata, clk, ncwrite,
ncwaddress(fabits2-1 downto 0), ncwdata);
--transmitter FIFO
tx_ram0 : syncram_2p generic map(memtech*techfifo, fabits1, 32)
port map(clk, txrenable, txraddress(fabits1-1 downto 0),
txrdata, clk, txwrite, txwaddress(fabits1-1 downto 0), txwdata);
--RMAP Buffer
rmap_ram : if (rmap /= 0) generate
ram0 : syncram_2p generic map(memtech, rfifo, 8)
port map(clk, rmrenablex, rmraddress(rfifo-1 downto 0),
rmrdata, clk, rmwrite, rmwaddress(rfifo-1 downto 0),
rmwdata);
end generate;
end generate;
ft1 : if ft /= 0 generate
--receiver AHB FIFO
rx_ram0 : syncram_2pft generic map(memtech*techfifo, fabits1, 32, 0, 0, ft*techfifo)
port map(clk, rxrenable, rxraddress(fabits1-1 downto 0),
rxrdata, clk, rxwrite,
rxwaddress(fabits1-1 downto 0), rxwdata);
--receiver nchar FIFO
rx_ram1 : syncram_2pft generic map(memtech*techfifo, fabits2, 9, 0, 0, 2*techfifo)
port map(clk, ncrenable, ncraddress(fabits2-1 downto 0),
ncrdata, clk, ncwrite,
ncwaddress(fabits2-1 downto 0), ncwdata);
--transmitter FIFO
tx_ram0 : syncram_2pft generic map(memtech*techfifo, fabits1, 32, 0, 0, ft*techfifo)
port map(clk, txrenable, txraddress(fabits1-1 downto 0),
txrdata, clk, txwrite, txwaddress(fabits1-1 downto 0), txwdata);
--RMAP Buffer
rmap_ram : if (rmap /= 0) generate
ram0 : syncram_2pft generic map(memtech, rfifo, 8, 0, 0, 2)
port map(clk, rmrenablex, rmraddress(rfifo-1 downto 0),
rmrdata, clk, rmwrite, rmwaddress(rfifo-1 downto 0),
rmwdata);
end generate;
end generate;
end architecture;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-terasic-de4/grlib_config.vhd | 2 | 2861 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: config
-- File: config.vhd
-- Description: GRLIB Global configuration package. Can be overriden
-- by local config packages in template designs.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
package config is
-- AHBDW - AHB data with
--
-- Valid values are 32, 64, 128 and 256
--
-- The value here sets the width of the AMBA AHB data vectors for all
-- cores in the library.
--
constant CFG_AHBDW : integer := 32;
-- CFG_AHB_ACDM - Enable AMBA Compliant Data Muxing in cores
--
-- Valid values are 0 and 1
--
-- 0: All GRLIB cores that use the ahbread* programs defined in the AMBA package
-- will read their data from the low part of the AHB data vector.
--
-- 1: All GRLIB cores that use the ahbread* programs defined in the AMBA package
-- will select valid data, as defined in the AMBA AHB standard, from the
-- AHB data vectors based on the address input. If a core uses a function
-- that does not have the address input, a failure will be asserted.
--
-- The value of CFG_AHB_ACDM is assigned to the constant CORE_ACDM in the
-- grlib.amba package. Note that this setting is separate from the ACDM setting
-- of the AHBCTRL core (which is set directly via a AHBCTRL VHDL generic).
--
constant CFG_AHB_ACDM : integer := 0;
-- GRLIB_CONFIG_ARRAY - Array of configuration values
--
-- The length of this array and the meaning of different positions is defined
-- in the grlib.config_types package.
constant GRLIB_CONFIG_ARRAY : grlib_config_array_type := (
grlib_debug_level => 0,
grlib_debug_mask => 0,
grlib_techmap_strict_ram => 0,
grlib_techmap_testin_extra => 0,
grlib_sync_reset_enable_all => 0,
grlib_async_reset_enable => 0,
others => 0);
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/jtag/ahbjtag.vhd | 1 | 6275 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbjtag
-- File: ahbjtag.vhd
-- Author: Edvin Catovic, Jiri Gaisler - Gaisler Research
-- Description: JTAG communication link with AHB master interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.misc.all;
use gaisler.libjtagcom.all;
use gaisler.jtag.all;
entity ahbjtag is
generic (
tech : integer range 0 to NTECH := 0;
hindex : integer := 0;
nsync : integer range 1 to 2 := 1;
idcode : integer range 0 to 255 := 9;
manf : integer range 0 to 2047 := 804;
part : integer range 0 to 65535 := 0;
ver : integer range 0 to 15 := 0;
ainst : integer range 0 to 255 := 2;
dinst : integer range 0 to 255 := 3;
scantest : integer := 0;
oepol : integer := 1;
tcknen : integer := 0;
versel : integer range 0 to 1 := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapi_tdo : in std_ulogic;
trst : in std_ulogic := '1';
tdoen : out std_ulogic;
tckn : in std_ulogic := '0';
tapo_tckn : out std_ulogic;
tapo_ninst : out std_logic_vector(7 downto 0);
tapo_iupd : out std_ulogic
);
end;
architecture struct of ahbjtag is
-- Use old jtagcom that only supports AHB clock up to 1/3 of JTAG clock
-- Must be used for certain techs where we don't have full access to TCK
-- Can also be forced by setting versel generic to 0
constant USEOLDCOM : integer := 1 - (1-tap_tck_gated(tech))*(versel);
-- Set REREAD to 1 to include support for re-read operation when host reads
-- out data register before jtagcom has completed the current AMBA access and
-- returned to state 'shft'.
constant REREAD : integer := 1;
constant REVISION : integer := 2 - (2-REREAD)*USEOLDCOM;
constant TAPSEL : integer := has_tapsel(tech);
signal dmai : ahb_dma_in_type;
signal dmao : ahb_dma_out_type;
signal ltapi : tap_in_type;
signal ltapo : tap_out_type;
signal lltck, lltckn, ltck, ltckn: std_ulogic;
signal lupd: std_ulogic;
signal ctrst: std_ulogic;
begin
ahbmst0 : ahbmst
generic map (hindex => hindex, venid => VENDOR_GAISLER,
devid => GAISLER_AHBJTAG, version => REVISION)
port map (rst, clk, dmai, dmao, ahbi, ahbo);
tap0 : tap generic map (tech => tech, irlen => 6, idcode => idcode,
manf => manf, part => part, ver => ver, scantest => scantest, oepol => oepol,
tcknen => tcknen)
port map (trst, tck, tms, tdi, tdo, lltck, ltapo.tdi, ltapo.inst, ltapo.reset, ltapo.capt,
ltapo.shift, lupd, ltapo.asel, ltapo.dsel, ltapi.en, ltapi.tdo, tapi_tdo,
tapo_ninst, tapo_iupd, lltckn,
ahbi.testen, ahbi.testrst, ahbi.testoen, tdoen, tckn);
ltapo.tck <= ltck;
tapo_tckn <= ltckn;
gtckbuf : if (USEOLDCOM=0 and is_fpga(tech)/=0) generate
tckbuf: techbuf
generic map (buftype => 2, tech => tech)
port map (lltck, ltck);
ltckn <= not ltck;
end generate;
notckbuf: if not (USEOLDCOM=0 and is_fpga(tech)/=0) generate
ltck <= lltck;
ltckn <= lltckn;
end generate;
-- Quirk for Xilinx TAP - upd changes on falling TCK edge and
-- the flow doesn't maintain synchrony with user falling TCK edge logic.
gupdff : if (USEOLDCOM=0 and is_unisim(tech)/=0) generate
updff: grdff port map (ltck, lupd, ltapo.upd);
end generate;
noupdff: if not (USEOLDCOM=0 and is_unisim(tech)/=0) generate
ltapo.upd <= lupd;
end generate;
oldcom: if USEOLDCOM /= 0 generate
jtagcom0 : jtagcom generic map (isel => TAPSEL, nsync => nsync, ainst => ainst, dinst => dinst, reread => REREAD)
port map (rst, clk, ltapo, ltapi, dmao, dmai, ltck, ctrst);
end generate;
newcom: if USEOLDCOM=0 generate
jtagcom0 : jtagcom2 generic map (gatetech => tech, isel => TAPSEL, ainst => ainst, dinst => dinst)
port map (rst, clk, ltapo, ltapi, dmao, dmai, ltck, ltckn, ctrst);
end generate;
tapo_tck <= ltck; tapo_tdi <= ltapo.tdi; tapo_inst <= ltapo.inst;
tapo_rst <= ltapo.reset; tapo_capt <= ltapo.capt; tapo_shft <= ltapo.shift;
tapo_upd <= ltapo.upd;
-- Async reset for tck-domain FFs in jtagcom.
-- In FPGA configs use AMBA reset as real TRST may not be available.
-- For ASIC:s we want to use the real TRST to simplify constraining.
ctrst <= ahbi.testrst when scantest/=0 and ahbi.testen='1' else
rst when is_fpga(tech)/=0 else
trst;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbjtag AHB Debug JTAG rev " & tost(REVISION));
-- pragma translate_on
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-sp605/svga2ch7301c.vhd | 2 | 6789 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: svga2ch7301c
-- File: svga2ch7301c.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- [email protected]
--
-- Description: Converter inteneded to connect a SVGACTRL core to a Chrontel
-- CH7301C DVI transmitter. Multiplexes data and generates clocks.
-- Tailored for use on the Xilinx ML50x boards with Leon3/GRLIB
-- template designs.
--
-- This multiplexer has been developed for use with the Chrontel CH7301C DVI
-- transmitter. Supported multiplexed formats are, as in the CH7301 datasheet:
--
-- IDF Description
-- 0 12-bit multiplexed RGB input (24-bit color), (scheme 1)
-- 1 12-bit multiplexed RGB2 input (24-bit color), (scheme 2)
-- 2 8-bit multiplexed RGB input (16-bit color, 565)
-- 3 8-bit multiplexed RGB input (15-bit color, 555)
--
-- This core assumes a 100 MHz input clock on the 'clk' input.
--
-- If the generic 'dynamic' is non-zero the core uses the value vgao.bitdepth
-- to decide if multiplexing should be done according to IDF 0 or IDF 2.
-- vago.bitdepth = "11" gives IDF 0, others give IDF2.
-- The 'idf' generic is not used when the 'dynamic' generic is non-zero.
-- Note that if dynamic selection is enabled you will need to reconfigure
-- the DVI transmitter when the VGA core changes bit depth.
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.misc.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity svga2ch7301c is
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
vgao : in apbvga_out_type;
vgaclk : in std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end svga2ch7301c;
architecture rtl of svga2ch7301c is
component BUFG port (O : out std_logic; I : in std_logic); end component;
component BUFGMUX port ( O : out std_ulogic; I0 : in std_ulogic;
I1 : in std_ulogic; S : in std_ulogic);
end component;
signal nvgaclk : std_ulogic;
signal vcc, gnd : std_logic;
signal d0, d1 : std_logic_vector(11 downto 0);
signal red, green, blue : std_logic_vector(7 downto 0);
signal lvgaclk, lclk40, lclk65, lclk40_65 : std_ulogic;
signal clkval : std_logic_vector(1 downto 0);
begin -- rtl
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------
-- RGB data multiplexer
-----------------------------------------------------------------------------
red <= vgao.video_out_r;
green <= vgao.video_out_g;
blue <= vgao.video_out_b;
static: if dynamic = 0 generate
idf0: if (idf = 0) generate
d0 <= green(3 downto 0) & blue(7 downto 0);
d1 <= red(7 downto 0) & green(7 downto 4);
end generate;
idf1: if (idf = 1) generate
d0 <= green(4 downto 2) & blue(7 downto 3) & green(0) & blue(2 downto 0);
d1 <= red(7 downto 3) & green(7 downto 5) & red(2 downto 0) & green(1);
end generate;
idf2: if (idf = 2) generate
d0(11 downto 4) <= green(4 downto 2) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= red(7 downto 3) & green(7 downto 5);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate;
idf3: if (idf = 3) generate
d0(11 downto 4) <= green(5 downto 3) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= '0' & red(7 downto 3) & green(7 downto 6);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate idf3;
-- DDR regs
dataregs: for i in 11 downto (4*(idf/2)) generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk, c2 => nvgaclk, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
nvgaclk <= not vgaclk;
nostatic: if dynamic /= 0 generate
d0 <= green(3 downto 0) & blue(7 downto 0) when vgao.bitdepth = "11" else
green(4 downto 2) & blue(7 downto 3) & "0000";
d1 <= red(7 downto 0) & green(7 downto 4) when vgao.bitdepth = "11" else
red(7 downto 3) & green(7 downto 5) & "0000";
dataregs: for i in 11 downto 0 generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk, c2 => nvgaclk, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
-----------------------------------------------------------------------------
-- Sync signals
-----------------------------------------------------------------------------
process (vgaclk)
begin -- process
if rising_edge(vgaclk) then
hsync <= vgao.hsync;
vsync <= vgao.vsync;
de <= vgao.blank;
end if;
end process;
-----------------------------------------------------------------------------
-- Clock generation
-----------------------------------------------------------------------------
ddroreg_p : ddr_oreg generic map (tech)
port map (q => dclk_p, c1 => vgaclk, c2 => nvgaclk, ce => vcc,
d1 => vcc, d2 => gnd, r => gnd, s => gnd);
ddroreg_n : ddr_oreg generic map (tech)
port map (q => dclk_n, c1 => vgaclk, c2 => nvgaclk, ce => vcc,
d1 => gnd, d2 => vcc, r => gnd, s => gnd);
end rtl;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/i2c/i2c2ahb_apb.vhd | 1 | 7346 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2c2ahb_apb
-- File: i2c2ahb_apb.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple I2C-slave providing a bridge to AMBA AHB
-- This entity provides an APB interface for setting defining the
-- AHB address window that can be accessed from I2C.
-- See i2c2ahbx.vhd and GRIP for documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.i2c.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.conv_std_logic;
use grlib.stdlib.conv_std_logic_vector;
entity i2c2ahb_apb is
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
resen : integer := 0;
-- APB configuration
pindex : integer := 0; -- slave bus index
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
-- I2C configuration
i2cslvaddr : integer range 0 to 127 := 0;
i2ccfgaddr : integer range 0 to 127 := 0;
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
--
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end entity i2c2ahb_apb;
architecture rtl of i2c2ahb_apb is
-- Register offsets
constant CTRL_OFF : std_logic_vector(4 downto 2) := "000";
constant STS_OFF : std_logic_vector(4 downto 2) := "001";
constant ADDR_OFF : std_logic_vector(4 downto 2) := "010";
constant MASK_OFF : std_logic_vector(4 downto 2) := "011";
constant SLVA_OFF : std_logic_vector(4 downto 2) := "100";
constant SLVC_OFF : std_logic_vector(4 downto 2) := "101";
-- AMBA PnP
constant PCONFIG : apb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_I2C2AHB, 0, 0, pirq),
1 => apb_iobar(paddr, pmask));
type apb_reg_type is record
i2c2ahbi : i2c2ahb_in_type;
irq : std_ulogic;
irqen : std_ulogic;
prot : std_ulogic;
protx : std_ulogic;
wr : std_ulogic;
dma : std_ulogic;
dmax : std_ulogic;
end record;
signal r, rin : apb_reg_type;
signal i2c2ahbo : i2c2ahb_out_type;
begin
bridge : i2c2ahbx
generic map (hindex => hindex, oepol => oepol, filter => filter)
port map (rstn => rstn, clk => clk, ahbi => ahbi, ahbo => ahbo,
i2ci => i2ci, i2co => i2co, i2c2ahbi => r.i2c2ahbi,
i2c2ahbo => i2c2ahbo);
comb: process (r, rstn, apbi, i2c2ahbo)
variable v : apb_reg_type;
variable apbaddr : std_logic_vector(4 downto 2);
variable apbout : std_logic_vector(31 downto 0);
variable irqout : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r; apbaddr := apbi.paddr(apbaddr'range); apbout := (others => '0');
v.irq := '0'; irqout := (others => '0'); irqout(pirq) := r.irq;
v.protx := i2c2ahbo.prot; v.dmax := i2c2ahbo.dma;
---------------------------------------------------------------------------
-- APB register interface
---------------------------------------------------------------------------
-- read registers
if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
case apbaddr is
when CTRL_OFF => apbout(1 downto 0) := r.irqen & r.i2c2ahbi.en;
when STS_OFF => apbout(2 downto 0) := r.prot & r.wr & r.dma;
when ADDR_OFF => apbout := r.i2c2ahbi.haddr;
when MASK_OFF => apbout := r.i2c2ahbi.hmask;
when SLVA_OFF => apbout(6 downto 0) := r.i2c2ahbi.slvaddr;
when SLVC_OFF => apbout(6 downto 0) := r.i2c2ahbi.cfgaddr;
when others => null;
end case;
end if;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbaddr is
when CTRL_OFF => v.irqen := apbi.pwdata(1); v.i2c2ahbi.en := apbi.pwdata(0);
when STS_OFF => v.dma := r.dma and not apbi.pwdata(0);
v.prot := r.prot and not apbi.pwdata(2);
when ADDR_OFF => v.i2c2ahbi.haddr := apbi.pwdata;
when MASK_OFF => v.i2c2ahbi.hmask := apbi.pwdata;
when SLVA_OFF => v.i2c2ahbi.slvaddr := apbi.pwdata(6 downto 0);
when SLVC_OFF => v.i2c2ahbi.cfgaddr := apbi.pwdata(6 downto 0);
when others => null;
end case;
end if;
-- interrupt and status register handling
if ((i2c2ahbo.dma and not r.dmax) or
(i2c2ahbo.prot and not r.protx)) = '1' then
v.dma := '1'; v.prot := r.prot or i2c2ahbo.prot; v.wr := i2c2ahbo.wr;
if (r.irqen and not r.dma) = '1' then v.irq := '1'; end if;
end if;
---------------------------------------------------------------------------
-- reset
---------------------------------------------------------------------------
if rstn = '0' then
v.i2c2ahbi.en := conv_std_logic(resen = 1);
v.i2c2ahbi.haddr := conv_std_logic_vector(ahbaddrh, 16) &
conv_std_logic_vector(ahbaddrl, 16);
v.i2c2ahbi.hmask := conv_std_logic_vector(ahbmaskh, 16) &
conv_std_logic_vector(ahbmaskl, 16);
v.i2c2ahbi.slvaddr := conv_std_logic_vector(i2cslvaddr, 7);
v.i2c2ahbi.cfgaddr := conv_std_logic_vector(i2ccfgaddr, 7);
v.irqen := '0'; v.prot := '0'; v.wr := '0'; v.dma := '0';
end if;
---------------------------------------------------------------------------
-- signal assignments
---------------------------------------------------------------------------
-- update registers
rin <= v;
-- update outputs
apbo.prdata <= apbout;
apbo.pirq <= irqout;
apbo.pconfig <= PCONFIG;
apbo.pindex <= pindex;
end process comb;
reg: process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process reg;
-- Boot message provided in i2c2ahbx...
end architecture rtl;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/ddr/ahb2avl_async.vhd | 1 | 5697 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahb2avl_async
-- File: ahb2avl_async.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Asynchronous AHB to Avalon-MM interface based on ddr2spa
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
use gaisler.ddrintpkg.all;
entity ahb2avl_async is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
burstlen : integer := 8;
nosync : integer := 0;
ahbbits : integer := ahbdw;
avldbits : integer := 32;
avlabits : integer := 20
);
port (
rst_ahb : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
rst_avl : in std_ulogic;
clk_avl : in std_ulogic;
avlsi : out ddravl_slv_in_type;
avlso : in ddravl_slv_out_type
);
end;
architecture struct of ahb2avl_async is
constant l2blen: integer := log2(burstlen)+log2(32);
constant l2ddrw: integer := log2(avldbits);
constant l2ahbw: integer := log2(ahbbits);
-- Write buffer dimensions
constant wbuf_rabits_s: integer := 1+l2blen-l2ddrw;
constant wbuf_rabits_r: integer := wbuf_rabits_s;
constant wbuf_rdbits: integer := avldbits;
constant wbuf_wabits: integer := 1+l2blen-5;
constant wbuf_wdbits: integer := ahbbits;
-- Read buffer dimensions
constant rbuf_rabits: integer := l2blen-l2ahbw;
constant rbuf_rdbits: integer := wbuf_wdbits;
constant rbuf_wabits: integer := l2blen-l2ddrw; -- log2((burstlen*32)/(2*ddrbits));
constant rbuf_wdbits: integer := avldbits;
signal request : ddr_request_type;
signal start_tog : std_ulogic;
signal response : ddr_response_type;
signal wbwaddr: std_logic_vector(wbuf_wabits-1 downto 0);
signal wbwdata: std_logic_vector(wbuf_wdbits-1 downto 0);
signal wbraddr: std_logic_vector(wbuf_rabits_s-1 downto 0);
signal wbrdata: std_logic_vector(wbuf_rdbits-1 downto 0);
signal rbwaddr: std_logic_vector(rbuf_wabits-1 downto 0);
signal rbwdata: std_logic_vector(rbuf_wdbits-1 downto 0);
signal rbraddr: std_logic_vector(rbuf_rabits-1 downto 0);
signal rbrdata: std_logic_vector(rbuf_rdbits-1 downto 0);
signal wbwrite,wbwritebig,rbwrite: std_ulogic;
signal gnd: std_logic_vector(3 downto 0);
signal vcc: std_ulogic;
begin
gnd <= (others => '0');
vcc <= '1';
fe0: ddr2spax_ahb
generic map (
hindex => hindex,
haddr => haddr,
hmask => hmask,
ioaddr => 0,
iomask => 0,
burstlen => burstlen,
nosync => nosync,
ahbbits => ahbbits,
devid => GAISLER_AHB2AVLA,
ddrbits => avldbits/2
)
port map (
rst => rst_ahb,
clk_ahb => clk_ahb,
ahbsi => ahbsi,
ahbso => ahbso,
request => request,
start_tog => start_tog,
response => response,
wbwaddr => wbwaddr,
wbwdata => wbwdata,
wbwrite => wbwrite,
wbwritebig => wbwritebig,
rbraddr => rbraddr,
rbrdata => rbrdata,
hwidth => gnd(0),
beid => gnd(3 downto 0)
);
be0: ahb2avl_async_be
generic map (
avldbits => avldbits,
avlabits => avlabits,
ahbbits => ahbbits,
burstlen => burstlen,
nosync => nosync
)
port map (
rst => rst_avl,
clk => clk_avl,
avlsi => avlsi,
avlso => avlso,
request => request,
start_tog => start_tog,
response => response,
wbraddr => wbraddr,
wbrdata => wbrdata,
rbwaddr => rbwaddr,
rbwdata => rbwdata,
rbwrite => rbwrite
);
wbuf: ddr2buf
generic map (tech => 0, wabits => wbuf_wabits, wdbits => wbuf_wdbits,
rabits => wbuf_rabits_r, rdbits => wbuf_rdbits,
sepclk => 1, wrfst => 0)
port map ( rclk => clk_avl, renable => vcc, raddress => wbraddr(wbuf_rabits_r-1 downto 0),
dataout => wbrdata, wclk => clk_ahb, write => wbwrite,
writebig => wbwritebig, waddress => wbwaddr, datain => wbwdata);
rbuf: ddr2buf
generic map (tech => 0, wabits => rbuf_wabits, wdbits => rbuf_wdbits,
rabits => rbuf_rabits, rdbits => rbuf_rdbits,
sepclk => 1, wrfst => 0)
port map ( rclk => clk_ahb, renable => vcc, raddress => rbraddr,
dataout => rbrdata,
wclk => clk_avl, write => rbwrite,
writebig => '0', waddress => rbwaddr, datain => rbwdata);
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/unisim/ddr_phy_unisim.vhd | 1 | 103327 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: ddr_phy_unisim.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: DDR PHY for Virtex-2 and Virtex-4
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.ODDR;
use unisim.FD;
use unisim.IDDR;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
------------------------------------------------------------------
-- Virtex4 DDR PHY -----------------------------------------------
------------------------------------------------------------------
entity virtex4_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0;
phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
ck : in std_logic_vector(2 downto 0)
);
end;
architecture rtl of virtex4_ddr_phy is
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component ODDR
generic
( DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
-- INIT : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component IDDR
generic ( DDR_CLK_EDGE : string := "SAME_EDGE";
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
SRTYPE : string := "ASYNC");
port
( Q1 : out std_ulogic;
Q2 : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
signal vcc, gnd, dqsn, oe, lockl : std_ulogic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl, dllfb : std_ulogic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst, dll2rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal rclk270b, rclk90b, rclk0b : std_ulogic;
signal rclk270, rclk90, rclk0 : std_ulogic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
attribute keep : boolean;
attribute keep of rclk90b : signal is true;
attribute syn_keep : boolean;
attribute syn_keep of rclk90b : signal is true;
attribute syn_preserve : boolean;
attribute syn_preserve of rclk90b : signal is true;
-- To prevent synplify 9.4 to remove any of these registers.
attribute syn_noprune : boolean;
attribute syn_noprune of FD : component is true;
attribute syn_noprune of IDDR : component is true;
attribute syn_noprune of ODDR : component is true;
begin
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
mclk <= clk;
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
port map ( CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
-- DDR clock generation
ddrref_pad : clkpad generic map (tech => virtex4)
port map (ddr_clk_fb, ddrclkfbl);
bufg1 : BUFG port map (I => clk_0ro, O => clk_0r);
-- bufg2 : BUFG port map (I => clk_90ro, O => clk_90r);
clk_90r <= not clk_270r;
-- bufg3 : BUFG port map (I => clk_180ro, O => clk_180r);
clk_180r <= not clk_0r;
bufg4 : BUFG port map (I => clk_270ro, O => clk_270r);
clkout <= clk_270r; clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dllfb <= clk_0r;
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_0ro,
CLK90 => clk_90ro, CLK180 => clk_180ro, CLK270 => clk_270ro,
LOCKED => lockl);
rstdel : process (mclk, rst)
begin
if rst = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
fbdclk0r : ODDR port map ( Q => ddr_clk_fb_outr, C => clk90r, CE => vcc,
D1 => vcc, D2 => gnd, R => gnd, S => gnd);
fbclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk_fb_out, ddr_clk_fb_outr);
ddrclkdiffio : if phyiconf = 0 generate
ddrclocks0 : for i in 0 to 2 generate
dclk0r : ODDR port map ( Q => ddr_clkl(i), C => clk90r, CE => vcc,
D1 => vcc, D2 => gnd, R => gnd, S => gnd);
ddrclk_pad : outpad_ds generic map (tech => virtex4, level => sstl2_ii)
port map (ddr_clk(i), ddr_clkb(i), ddr_clkl(i), '1');
end generate;
end generate;
ddrclknodiffio : if phyiconf = 1 generate
ddrclocks1 : for i in 0 to 2 generate
dclk0r : ODDR port map ( Q => ddr_clkl(i), C => clk90r, CE => vcc,
D1 => vcc, D2 => gnd, R => gnd, S => gnd);
ddrclk1_pad : outpad generic map (tech => virtex4, level => sstl2_ii)
port map (ddr_clk(i), ddr_clkl(i));
dclk0rb : ODDR port map ( Q => ddr_clkbl(i), C => clk90r, CE => vcc,
D1 => gnd, D2 => vcc, R => gnd, S => gnd);
ddrclk1b_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clkb(i), ddr_clkbl(i));
end generate;
end generate;
ddrbanks : for i in 0 to 1 generate
csn0gen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_csnr(i), C => clk0r, CE => vcc,
D1 => csn(i), D2 => csn(i), R => gnd, S => gnd);
csn0_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_csb(i), ddr_csnr(i));
ckel(i) <= cke(i) and locked;
ckegen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_ckenr(i), C => clk0r, CE => vcc,
D1 => ckel(i), D2 => ckel(i), R => gnd, S => gnd);
cke_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_cke(i), ddr_ckenr(i));
end generate;
rasgen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_rasnr, C => clk0r, CE => vcc,
D1 => rasn, D2 => rasn, R => gnd, S => gnd);
rasn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_rasb, ddr_rasnr);
casgen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_casnr, C => clk0r, CE => vcc,
D1 => casn, D2 => casn, R => gnd, S => gnd);
casn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_casb, ddr_casnr);
wengen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_wenr, C => clk0r, CE => vcc,
D1 => wen, D2 => wen, R => gnd, S => gnd);
wen_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_web, ddr_wenr);
dmgen : for i in 0 to dbits/8-1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dmr(i), C => clk0r, CE => vcc,
D1 => dm(i+dbits/8), D2 => dm(i), R => gnd, S => gnd);
ddr_bm_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_dm(i), ddr_dmr(i));
end generate;
bagen : for i in 0 to 1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_bar(i), C => clk0r, CE => vcc,
D1 => ba(i), D2 => ba(i), R => gnd, S => gnd);
ddr_ba_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ba(i), ddr_bar(i));
end generate;
dagen : for i in 0 to 13 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_adr(i), C => clk0r, CE => vcc,
D1 => addr(i), D2 => addr(i), R => gnd, S => gnd);
ddr_ad_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ad(i), ddr_adr(i));
end generate;
-- DQS generation
dsqreg : FD port map ( Q => dqsn, C => clk180r, D => oe);
dqsgen : for i in 0 to dbits/8-1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dqsin(i), C => clk90r, CE => vcc,
D1 => dqsn, D2 => gnd, R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqsoen(i), C => clk0r, D => dqsoen);
dqs_pad : iopad generic map (tech => virtex4, level => sstl2_ii)
port map (pad => ddr_dqs(i), i => ddr_dqsin(i), en => ddr_dqsoen(i),
o => ddr_dqsoutl(i));
end generate;
-- Data bus
read_rstdel : process (clk_0r, lockl)
begin
if lockl = '0' then dll2rst <= (others => '1');
elsif rising_edge(clk_0r) then
dll2rst <= dll2rst(1 to 3) & '0';
end if;
end process;
bufg7 : BUFG port map (I => rclk0, O => rclk0b);
bufg8 : BUFG port map (I => rclk90, O => rclk90b);
-- bufg9 : BUFG port map (I => rclk270, O => rclk270b);
rclk270b <= not rclk90b;
nops : if rskew = 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ps : if rskew /= 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => rskew)
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ddgen : for i in 0 to dbits-1 generate
qi : IDDR generic map (DDR_CLK_EDGE => "OPPOSITE_EDGE")
port map ( Q1 => dqinl(i), --(i+dbits), -- 1-bit output for positive edge of clock
Q2 => dqin(i), -- 1-bit output for negative edge of clock
C => rclk90b, --clk270r, --dqsclk((2*i)/dbits), -- 1-bit clock input
CE => vcc, -- 1-bit clock enable input
D => ddr_dqin(i), -- 1-bit DDR data input
R => gnd, -- 1-bit reset
S => gnd -- 1-bit set
);
dinq1 : FD port map ( Q => dqin(i+dbits), C => rclk270b, D => dqinl(i));
dout : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dqout(i), C => clk0r, CE => vcc,
D1 => dqout(i+dbits), D2 => dqout(i), R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqoen(i), C => clk0r, D => oen);
dq_pad : iopad generic map (tech => virtex4, level => sstl2_ii)
port map (pad => ddr_dq(i), i => ddr_dqout(i), en => ddr_dqoen(i), o => ddr_dqin(i));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.FDDRRSE;
use unisim.IFDDRRSE;
use unisim.FD;
-- pragma translate_on
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.oddrv2;
------------------------------------------------------------------
-- Virtex2 DDR PHY -----------------------------------------------
------------------------------------------------------------------
entity virtex2_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of virtex2_ddr_phy is
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component FDDRRSE
-- generic ( INIT : bit := '0');
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component IFDDRRSE
port (
Q0 : out std_ulogic;
Q1 : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component oddrv2
generic ( tech : integer := virtex4);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
signal vcc, gnd, dqsn, oe, lockl : std_ulogic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl : std_ulogic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst, dll2rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal rclk270b, rclk90b, rclk0b : std_ulogic;
signal rclk270, rclk90, rclk0 : std_ulogic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
-- To prevent synplify 9.4 to remove any of these registers.
attribute syn_noprune : boolean;
attribute syn_noprune of FD : component is true;
attribute syn_noprune of FDDRRSE : component is true;
attribute syn_noprune of IFDDRRSE : component is true;
attribute syn_noprune of oddrv2 : component is true;
begin
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
mclk <= clk; mlock <= rst;
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
CLKIN_PERIOD => 10.0)
port map ( CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
-- DDR output clock generation
bufg1 : BUFG port map (I => clk_0ro, O => clk_0r);
-- bufg2 : BUFG port map (I => clk_90ro, O => clk_90r);
clk_90r <= not clk_270r;
-- bufg3 : BUFG port map (I => clk_180ro, O => clk_180r);
clk_180r <= not clk_0r;
bufg4 : BUFG port map (I => clk_270ro, O => clk_270r);
clkout <= clk_270r; clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => mclk, CLKFB => clk_0r, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_0ro,
CLK90 => clk_90ro, CLK180 => clk_180ro, CLK270 => clk_270ro,
LOCKED => lockl);
rstdel : process (mclk, mlock)
begin
if mlock = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
fbdclk0r : FDDRRSE port map ( Q => ddr_clk_fb_outr, C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => vcc, D1 => gnd, R => gnd, S => gnd);
fbclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk_fb_out, ddr_clk_fb_outr);
ddrclocks : for i in 0 to 2 generate
dclk0r : FDDRRSE port map ( Q => ddr_clkl(i), C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => vcc, D1 => gnd, R => gnd, S => gnd);
ddrclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk(i), ddr_clkl(i));
dclk0rb : FDDRRSE port map ( Q => ddr_clkbl(i), C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => gnd, D1 => vcc, R => gnd, S => gnd);
ddrclkb_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clkb(i), ddr_clkbl(i));
end generate;
ddrbanks : for i in 0 to 1 generate
csn0gen : FD port map ( Q => ddr_csnr(i), C => clk0r, D => csn(i));
csn0_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_csb(i), ddr_csnr(i));
ckel(i) <= cke(i) and locked;
ckegen : FD port map ( Q => ddr_ckenr(i), C => clk0r, D => ckel(i));
cke_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_cke(i), ddr_ckenr(i));
end generate;
-- DDR single-edge control signals
rasgen : FD port map ( Q => ddr_rasnr, C => clk0r, D => rasn);
rasn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_rasb, ddr_rasnr);
casgen : FD port map ( Q => ddr_casnr, C => clk0r, D => casn);
casn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_casb, ddr_casnr);
wengen : FD port map ( Q => ddr_wenr, C => clk0r, D => wen);
wen_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_web, ddr_wenr);
dmgen : for i in 0 to dbits/8-1 generate
da0 : oddrv2 port map ( Q => ddr_dmr(i), C1 => clk0r, C2 => clk180r,
CE => vcc, D1 => dm(i+dbits/8), D2 => dm(i), R => gnd, S => gnd);
ddr_bm_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_dm(i), ddr_dmr(i));
end generate;
bagen : for i in 0 to 1 generate
da0 : FD port map ( Q => ddr_bar(i), C => clk0r, D => ba(i));
ddr_ba_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ba(i), ddr_bar(i));
end generate;
dagen : for i in 0 to 13 generate
da0 : FD port map ( Q => ddr_adr(i), C => clk0r, D => addr(i));
ddr_ad_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ad(i), ddr_adr(i));
end generate;
-- DQS generation
dsqreg : FD port map ( Q => dqsn, C => clk180r, D => oe);
dqsgen : for i in 0 to dbits/8-1 generate
da0 : oddrv2
port map ( Q => ddr_dqsin(i), C1 => clk90r, C2 => clk270r,
CE => vcc, D1 => dqsn, D2 => gnd, R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqsoen(i), C => clk0r, D => dqsoen);
dqs_pad : iopad generic map (tech => virtex4, level => sstl2_ii)
port map (pad => ddr_dqs(i), i => ddr_dqsin(i), en => ddr_dqsoen(i),
o => ddr_dqsoutl(i));
end generate;
-- Data bus
ddrref_pad : clkpad generic map (tech => virtex2)
port map (ddr_clk_fb, ddrclkfbl);
read_rstdel : process (clk_0r, lockl)
begin
if lockl = '0' then dll2rst <= (others => '1');
elsif rising_edge(clk_0r) then
dll2rst <= dll2rst(1 to 3) & '0';
end if;
end process;
bufg7 : BUFG port map (I => rclk0, O => rclk0b);
bufg8 : BUFG port map (I => rclk90, O => rclk90b);
-- bufg9 : BUFG port map (I => rclk270, O => rclk270b);
rclk270b <= not rclk90b;
nops : if rskew = 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ps : if rskew /= 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => rskew)
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ddgen : for i in 0 to dbits-1 generate
qi : IFDDRRSE
port map ( Q0 => dqinl(i), --(i+dbits), -- 1-bit output for positive edge of clock
Q1 => dqin(i), -- 1-bit output for negative edge of clock
C0 => rclk90b, -- clk270r, --dqsclk((2*i)/dbits), -- 1-bit clock input
C1 => rclk270b, -- clk90r, --dqsclk((2*i)/dbits), -- 1-bit clock input
CE => vcc, -- 1-bit clock enable input
D => ddr_dq(i), -- 1-bit DDR data input
R => gnd, -- 1-bit reset
S => gnd -- 1-bit set
);
-- dinq1 : FD port map ( Q => dqin(i+dbits), C => clk90r, D => dqinl(i));
dinq1 : FD port map ( Q => dqin(i+dbits), C => rclk270b, D => dqinl(i));
dout : oddrv2
port map ( Q => ddr_dqout(i), C1 => clk0r, C2 => clk180r, CE => vcc,
D1 => dqout(i+dbits), D2 => dqout(i), R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqoen(i), C => clk0r, D => oen);
dq_pad : iopad generic map (tech => virtex4, level => sstl2_ii)
port map (pad => ddr_dq(i), i => ddr_dqout(i), en => ddr_dqoen(i), o => open); -- o => ddr_dqin(i));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.ODDR2;
use unisim.IDDR2;
use unisim.FD;
-- pragma translate_on
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.oddrc3e;
------------------------------------------------------------------
-- Spartan3E DDR PHY -----------------------------------------------
------------------------------------------------------------------
entity spartan3e_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- DDR state clock
clkread : out std_ulogic; -- DDR read clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of spartan3e_ddr_phy is
component oddrc3e
generic ( tech : integer := virtex4);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component ODDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D0 : in std_ulogic;
D1 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component IDDR2
generic
(
DDR_ALIGNMENT : string := "NONE";
INIT_Q0 : bit := '0';
INIT_Q1 : bit := '0';
SRTYPE : string := "SYNC"
);
port
(
Q0 : out std_ulogic;
Q1 : out std_ulogic;
C0 : in std_ulogic;
C1 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
signal vcc, gnd, dqsn, oe, lockl : std_ulogic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl, dllfb : std_ulogic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst, dll2rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal rclk270b, rclk90b, rclk0b : std_ulogic;
signal rclk270, rclk90, rclk0 : std_ulogic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
-- To prevent synplify 9.4 to remove any of these registers.
attribute syn_noprune : boolean;
attribute syn_noprune of FD : component is true;
attribute syn_noprune of IDDR2 : component is true;
attribute syn_noprune of ODDR2 : component is true;
attribute syn_noprune of oddrc3e : component is true;
begin
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
mclk <= clk; mlock <= rst;
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
CLKIN_PERIOD => 10.0)
port map ( CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
-- DDR output clock generation
bufg1 : BUFG port map (I => clk_0ro, O => clk_0r);
-- bufg2 : BUFG port map (I => clk_90ro, O => clk_90r);
clk_90r <= not clk_270r;
-- bufg3 : BUFG port map (I => clk_180ro, O => clk_180r);
clk_180r <= not clk_0r;
bufg4 : BUFG port map (I => clk_270ro, O => clk_270r);
clkout <= clk_270r;
-- clkout <= clk_90r when DDR_FREQ > 120 else clk_0r;
clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2)
port map ( CLKIN => mclk, CLKFB => clk_0r, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_0ro,
CLK90 => clk_90ro, CLK180 => clk_180ro, CLK270 => clk_270ro,
LOCKED => lockl);
rstdel : process (mclk, mlock)
begin
if mlock = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
fbdclk0r : ODDR2 port map ( Q => ddr_clk_fb_outr, C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => vcc, D1 => gnd, R => gnd, S => gnd);
fbclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk_fb_out, ddr_clk_fb_outr);
ddrclocks : for i in 0 to 2 generate
dclk0r : ODDR2 port map ( Q => ddr_clkl(i), C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => vcc, D1 => gnd, R => gnd, S => gnd);
ddrclk_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clk(i), ddr_clkl(i));
dclk0rb : ODDR2 port map ( Q => ddr_clkbl(i), C0 => clk90r, C1 => clk270r,
CE => vcc, D0 => gnd, D1 => vcc, R => gnd, S => gnd);
ddrclkb_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_clkb(i), ddr_clkbl(i));
end generate;
ddrbanks : for i in 0 to 1 generate
csn0gen : FD port map ( Q => ddr_csnr(i), C => clk0r, D => csn(i));
csn0_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_csb(i), ddr_csnr(i));
ckel(i) <= cke(i) and locked;
ckegen : FD port map ( Q => ddr_ckenr(i), C => clk0r, D => ckel(i));
cke_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_cke(i), ddr_ckenr(i));
end generate;
-- DDR single-edge control signals
rasgen : FD port map ( Q => ddr_rasnr, C => clk0r, D => rasn);
rasn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_rasb, ddr_rasnr);
casgen : FD port map ( Q => ddr_casnr, C => clk0r, D => casn);
casn_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_casb, ddr_casnr);
wengen : FD port map ( Q => ddr_wenr, C => clk0r, D => wen);
wen_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_web, ddr_wenr);
dmgen : for i in 0 to dbits/8-1 generate
da0 : oddrc3e
port map ( Q => ddr_dmr(i), C1 => clk0r, C2 => clk180r,
CE => vcc, D1 => dm(i+dbits/8), D2 => dm(i), R => gnd, S => gnd);
ddr_bm_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_dm(i), ddr_dmr(i));
end generate;
bagen : for i in 0 to 1 generate
da0 : FD port map ( Q => ddr_bar(i), C => clk0r, D => ba(i));
ddr_ba_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ba(i), ddr_bar(i));
end generate;
dagen : for i in 0 to 13 generate
da0 : FD port map ( Q => ddr_adr(i), C => clk0r, D => addr(i));
ddr_ad_pad : outpad generic map (tech => virtex4, level => sstl2_i)
port map (ddr_ad(i), ddr_adr(i));
end generate;
-- DQS generation
dsqreg : FD port map ( Q => dqsn, C => clk180r, D => oe);
dqsgen : for i in 0 to dbits/8-1 generate
da0 : oddrc3e
port map ( Q => ddr_dqsin(i), C1 => clk90r, C2 => clk270r,
CE => vcc, D1 => dqsn, D2 => gnd, R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqsoen(i), C => clk0r, D => dqsoen);
dqs_pad : iopad generic map (tech => virtex4, level => sstl2_i)
port map (pad => ddr_dqs(i), i => ddr_dqsin(i), en => ddr_dqsoen(i),
o => ddr_dqsoutl(i));
end generate;
-- Data bus
ddrref_pad : clkpad generic map (tech => virtex2)
port map (ddr_clk_fb, ddrclkfbl);
read_rstdel : process (clk_0r, lockl)
begin
if lockl = '0' then dll2rst <= (others => '1');
elsif rising_edge(clk_0r) then
dll2rst <= dll2rst(1 to 3) & '0';
end if;
end process;
bufg7 : BUFG port map (I => rclk0, O => rclk0b);
bufg8 : BUFG port map (I => rclk90, O => rclk90b);
-- bufg9 : BUFG port map (I => rclk270, O => rclk270b);
rclk270b <= not rclk90b;
clkread <= not rclk90b;
nops : if rskew = 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS")
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ps : if rskew /= 0 generate
read_dll : DCM
generic map (clkin_period => 10.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => rskew)
port map ( CLKIN => ddrclkfbl, CLKFB => rclk0b, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll2rst(0), CLK0 => rclk0,
CLK90 => rclk90, CLK270 => rclk270);
end generate;
ddgen : for i in 0 to dbits-1 generate
qi : IDDR2
port map ( Q0 => dqinl(i), Q1 => dqin(i), C0 => rclk90b, C1 => rclk270b,
CE => vcc, D => ddr_dqin(i), R => gnd, S => gnd );
dinq1 : FD port map ( Q => dqin(i+dbits), C => rclk270b, D => dqinl(i));
dout : oddrc3e
port map ( Q => ddr_dqout(i), C1 => clk0r, C2 => clk180r, CE => vcc,
D1 => dqout(i+dbits), D2 => dqout(i), R => gnd, S => gnd);
doen : FD port map ( Q => ddr_dqoen(i), C => clk0r, D => oen);
dq_pad : iopad generic map (tech => virtex4, level => sstl2_i)
port map (pad => ddr_dq(i), i => ddr_dqout(i), en => ddr_dqoen(i), o => ddr_dqin(i));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.ODDR;
use unisim.FD;
use unisim.IDELAY;
use unisim.ISERDES;
use unisim.BUFIO;
use unisim.IDELAYCTRL;
use unisim.IDDR;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
------------------------------------------------------------------
-- Virtex5 DDR2 PHY ----------------------------------------------
------------------------------------------------------------------
entity virtex5_ddr2_phy_wo_pads is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0; ddelayb8 : integer := 0;
ddelayb9 : integer := 0; ddelayb10: integer := 0; ddelayb11: integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0;
tech : integer := virtex5; odten : integer := 0;
eightbanks : integer range 0 to 1 := 0;
dqsse : integer range 0 to 1 := 0; abits: integer := 14; nclk: integer := 3;
ncs: integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0); -- ddr address
ba : in std_logic_vector ( 2 downto 0); -- ddr bank address
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(ncs-1 downto 0)
);
end;
architecture rtl of virtex5_ddr2_phy_wo_pads is
component DCM
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false
);
port (
CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component ODDR
generic
( DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
-- INIT : bit := '0';
SRTYPE : string := "SYNC");
port
(
Q : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic
);
end component;
component FD
generic ( INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component IDDR
generic ( DDR_CLK_EDGE : string := "SAME_EDGE";
INIT_Q1 : bit := '0';
INIT_Q2 : bit := '0';
SRTYPE : string := "ASYNC");
port
( Q1 : out std_ulogic;
Q2 : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component IDELAY
generic ( IOBDELAY_TYPE : string := "DEFAULT";
IOBDELAY_VALUE : integer := 0);
port ( O : out std_ulogic;
C : in std_ulogic;
CE : in std_ulogic;
I : in std_ulogic;
INC : in std_ulogic;
RST : in std_ulogic);
end component;
component OBUFDS
generic (
CAPACITANCE : string := "DONT_CARE";
IOSTANDARD : string := "DEFAULT";
SLEW : string := "SLOW"
);
port (
O : out std_ulogic;
OB : out std_ulogic;
I : in std_ulogic
);
end component;
component IDELAYCTRL
port ( RDY : out std_ulogic;
REFCLK : in std_ulogic;
RST : in std_ulogic);
end component;
signal vcc, gnd, oe, lockl : std_ulogic;
signal dqsn : std_logic_vector(dbits/8-1 downto 0);
signal cbdqsn : std_logic_vector(dbits/8-1 downto 0);
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_rasnr2, ddr_casnr2, ddr_wenr2 : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(nclk-1 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(ncs-1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl, dllfb : std_ulogic;
signal ddr_dqin, ddr_dqin_nodel : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_cbdqin, ddr_cbdqin_nodel : std_logic_vector (dbits-1 downto 0); -- ddr checkbits
signal ddr_cbdqout : std_logic_vector (dbits-1 downto 0); -- ddr checkbits
signal ddr_cbdqoen : std_logic_vector (dbits-1 downto 0); -- ddr checkbits
signal ddr_adr : std_logic_vector (abits-1 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1+eightbanks downto 0); -- ddr address
signal ddr_adr2 : std_logic_vector (abits-1 downto 0); -- ddr address
signal ddr_bar2 : std_logic_vector (1+eightbanks downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr data mask
signal ddr_cbdmr : std_logic_vector (dbits/8-1 downto 0); -- ddr checkbit mask
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen_reg: std_logic_vector (dbits/8-1 downto 0); -- ddr dqs reg
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_cbdqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_cbdqsoen_reg: std_logic_vector (dbits/8-1 downto 0); -- ddr dqs reg
signal ddr_cbdqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_cbdqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk, dqsclkn : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst, dll2rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal rclk270b, rclk90b, rclk0b : std_ulogic;
signal rclk270, rclk90, rclk0 : std_ulogic;
signal clk200, clk200_0, clk200fb, clk200fx, lock200 : std_logic;
signal odtl : std_logic_vector(ncs-1 downto 0);
signal refclk_rdy : std_logic_vector(numidelctrl-1 downto 0);
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
type ddelay_type is array (0 to 11) of integer;
constant ddelay : ddelay_type := (ddelayb0, ddelayb1, ddelayb2,
ddelayb3, ddelayb4, ddelayb5,
ddelayb6, ddelayb7, ddelayb8,
ddelayb9, ddelayb10, ddelayb11);
attribute syn_noprune : boolean;
attribute syn_noprune of IDELAYCTRL : component is true;
attribute syn_keep : boolean;
attribute syn_keep of dqsclk : signal is true;
attribute syn_preserve : boolean;
attribute syn_preserve of dqsclk : signal is true;
attribute syn_keep of dqsn : signal is true;
attribute syn_preserve of dqsn : signal is true;
-- To prevent synplify 9.4 to remove any of these registers.
attribute syn_noprune of FD : component is true;
attribute syn_noprune of IDDR : component is true;
attribute syn_noprune of ODDR : component is true;
attribute keep : boolean;
attribute keep of mclkfx : signal is true;
attribute keep of clk_90ro : signal is true;
attribute syn_keep of mclkfx : signal is true;
attribute syn_keep of clk_90ro : signal is true;
begin
-- Generate 200 MHz ref clock if not supplied
refclkx : if norefclk = 0 generate
buf_clk200 : BUFG port map( I => clkref200, O => clk200);
lock200 <= '1';
end generate;
norefclkx : if norefclk /= 0 generate
bufg0 : BUFG port map (I => clk200fx, O => clk200);
HMODE_dll200 : if (tech = virtex4 and MHz >= 210) or (tech = virtex5) generate
dll200 : DCM
generic map (
CLKFX_MULTIPLY => 400/MHz, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH",
CLK_FEEDBACK => "NONE")
port map (
CLKIN => clk, CLKFB => clk200fb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0),
LOCKED => lock200, CLKFX => clk200fx);
end generate;
LMODE_dll200 : if not ((tech = virtex4 and MHz >= 210) or (tech = virtex5)) generate
dll200 : DCM
generic map (
CLKFX_MULTIPLY => 400/MHz, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW",
CLK_FEEDBACK => "NONE")
port map (
CLKIN => clk, CLKFB => clk200fb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0),
LOCKED => lock200, CLKFX => clk200fx);
end generate;
end generate;
-- Delay control
idelctrl : for i in 0 to numidelctrl-1 generate
u : IDELAYCTRL port map (rst => dllrst(0), refclk => clk200, rdy => refclk_rdy(i));
end generate;
oe <= not oen;
vcc <= '1';
gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
dll0rst <= dllrst;
mlock <= '1';
mbufg0 : BUFG port map (I => clk, O => mclk);
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then
dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
HMODE_dllm : if (tech = virtex4 and (((MHz*clk_mul)/clk_div >= 210) or (MHz >= 210)))
or (tech = virtex5 and (((MHz*clk_mul)/clk_div > 140) or (MHz > 120))) generate
dllm : DCM
generic map (
CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH")
port map (
CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
LMODE_dllm : if not ((tech = virtex4 and (((MHz*clk_mul)/clk_div >= 210) or (MHz >= 210)))
or (tech = virtex5 and (((MHz*clk_mul)/clk_div > 140) or (MHz > 120)))) generate
dllm : DCM
generic map (
CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW")
port map (
CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
end generate;
-- DDR clock generation
bufg2 : BUFG port map (I => clk_90ro, O => clk90r);
clk180r <= not mclk;
clkout <= mclk;
dllfb <= clk90r;
HMODE_dll : if (tech = virtex4 and ((MHz*clk_mul)/clk_div >= 150))
or (tech = virtex5 and ((MHz*clk_mul)/clk_div >= 120)) generate
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "HIGH", DLL_FREQUENCY_MODE => "HIGH", --"HIGH")
PHASE_SHIFT => 64, CLKOUT_PHASE_SHIFT => "FIXED")--, CLKIN_PERIOD => real((1000*clk_div)/(MHz*clk_mul)))
port map ( CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_90ro,
CLK90 => open, CLK180 => open, CLK270 => open,
LOCKED => lockl);
end generate;
LMODE_dll : if not ((tech = virtex4 and ((MHz*clk_mul)/clk_div >= 150))
or (tech = virtex5 and ((MHz*clk_mul)/clk_div >= 120))) generate
dll : DCM generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
DFS_FREQUENCY_MODE => "LOW", DLL_FREQUENCY_MODE => "LOW", --"HIGH")
PHASE_SHIFT => 64, CLKOUT_PHASE_SHIFT => "FIXED")--, CLKIN_PERIOD => real((1000*clk_div)/(MHz*clk_mul)))
port map ( CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_90ro,
CLK90 => open, CLK180 => open, CLK270 => open,
LOCKED => lockl);
end generate;
rstdel : process (mclk, rst, mlock, lock200)
begin
if rst = '0' or mlock = '0' or lock200 = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
--rcnt : process (clk_0r)
rcnt : process (clkoutret)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
--if rising_edge(clk_0r) then
if rising_edge(clkoutret) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked and orv(refclk_rdy);
-- Generate external DDR clock
ddrclocks : for i in 0 to nclk-1 generate
dclk0r : ODDR port map ( Q => ddr_clk(i), C => clk90r, CE => vcc,
D1 => vcc, D2 => gnd, R => gnd, S => gnd);
ddr_clkb(i) <= '0'; -- unused
end generate;
-- ODT
odtgen : for i in 0 to ncs-1 generate
odtl(i) <= locked and orv(refclk_rdy) and odt(i);
ddr_odt(i) <= odtl(i);
end generate;
ddrbanks : for i in 0 to ncs-1 generate
csn0gen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_csnr(i), C => clk180r, CE => vcc,
D1 => csn(i), D2 => csn(i), R => gnd, S => gnd);
ddr_csb(i) <= ddr_csnr(i);
ckel(i) <= cke(i) and locked;
ckegen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_ckenr(i), C => clk180r, CE => vcc,
D1 => ckel(i), D2 => ckel(i), R => gnd, S => gnd);
ddr_cke(i) <= ddr_ckenr(i);
end generate;
rasgen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_rasnr, C => clk180r, CE => vcc,
D1 => rasn, D2 => rasn, R => gnd, S => gnd);
ddr_rasb <= ddr_rasnr;
casgen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_casnr, C => clk180r, CE => vcc,
D1 => casn, D2 => casn, R => gnd, S => gnd);
ddr_casb <= ddr_casnr;
wengen : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_wenr, C => clk180r, CE => vcc,
D1 => wen, D2 => wen, R => gnd, S => gnd);
ddr_web <= ddr_wenr;
dmgen : for i in 0 to dbits/8-1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dmr(i), C => clkoutret, CE => vcc,
D1 => dm(i+dbits/8), D2 => dm(i), R => gnd, S => gnd);
end generate;
ddr_dm <= ddr_dmr;
bagen : for i in 0 to 1+eightbanks generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_bar(i), C => clk180r, CE => vcc,
D1 => ba(i), D2 => ba(i), R => gnd, S => gnd);
end generate;
ddr_ba <= ddr_bar;
dagen : for i in 0 to abits-1 generate
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_adr(i), C => clk180r, CE => vcc,
D1 => addr(i), D2 => addr(i), R => gnd, S => gnd);
end generate;
ddr_ad <= ddr_adr;
-- DQS generation
dqsgen : for i in 0 to dbits/8-1 generate
dsqreg : FD port map ( Q => dqsn(i), C => clk180r, D => oe);
da0 : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dqsin(i), C => clk90r, CE => vcc,
--D1 => dqsn, D2 => gnd, R => gnd, S => gnd);
D1 => dqsn(i), D2 => gnd, R => gnd, S => gnd);
doen_reg : FD port map ( Q => ddr_dqsoen_reg(i), C => clk180r, D => dqsoen);
doen : FD port map ( Q => ddr_dqsoen(i), C => clk90r, D => ddr_dqsoen_reg(i));
end generate;
ddr_dqs_out <= ddr_dqsin;
ddr_dqs_oen <= ddr_dqsoen;
ddr_dqsoutl <= ddr_dqs_in;
-- Data bus
ddgen : for i in 0 to dbits-1 generate
del_dq0 : IDELAY generic map(IOBDELAY_TYPE => "VARIABLE", IOBDELAY_VALUE => ddelay(i/8))
port map(O => ddr_dqin(i), I => ddr_dqin_nodel(i), C => clkoutret, CE => cal_en(i/8),
INC => cal_inc(i/8), RST => cal_rst);
qi : IDDR generic map (DDR_CLK_EDGE => "OPPOSITE_EDGE")
port map ( Q1 => dqinl(i), --(i+dbits), -- 1-bit output for positive edge of clock
Q2 => dqin(i), --dqin(i), -- 1-bit output for negative edge of clock
C => clk180r, --clk270r, --dqsclk((2*i)/dbits), -- 1-bit clock input
CE => vcc, -- 1-bit clock enable input
D => ddr_dqin(i), -- 1-bit DDR data input
R => gnd, -- 1-bit reset
S => gnd -- 1-bit set
);
dinq1 : FD port map ( Q => dqin(i+dbits), C => clkoutret, D => dqinl(i));
dout : ODDR generic map (DDR_CLK_EDGE => "SAME_EDGE")
port map ( Q => ddr_dqout(i), C => clkoutret, CE => vcc,
D1 => dqout(i+dbits), D2 => dqout(i), R => gnd, S => gnd);
doen : FD
generic map (INIT => '1')
port map ( Q => ddr_dqoen(i), C => clkoutret, D => oen);
end generate;
ddr_dq_out <= ddr_dqout;
ddr_dq_oen <= ddr_dqoen;
ddr_dqin_nodel <= ddr_dq_in;
end;
------------------------------------------------------------------
-- Spartan 3A DDR2 PHY -------------------------------------------
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
use unisim.IDDR2;
use unisim.ODDR2;
use unisim.FD;
use unisim.BUFIO;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity spartan3a_ddr2_phy is
generic (MHz : integer := 125; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2;
clk_div : integer := 2; tech : integer := spartan3;
rskew : integer := 0; eightbanks : integer range 0 to 1 := 0);
port ( rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- DDR clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
addr : in std_logic_vector (13 downto 0); -- row address
ba : in std_logic_vector ( 2 downto 0); -- bank address
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
cal_pll : in std_logic_vector(1 downto 0);
odt : in std_logic_vector(1 downto 0));
end;
architecture rtl of spartan3a_ddr2_phy is
component DCM
generic (CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false);
port ( CLKFB : in std_logic;
CLKIN : in std_logic;
DSSEN : in std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
RST : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKDV : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
LOCKED : out std_logic;
PSDONE : out std_logic;
STATUS : out std_logic_vector (7 downto 0));
end component;
component BUFG
port (O : out std_logic;
I : in std_logic);
end component;
component ODDR2
generic (DDR_ALIGNMENT : string := "NONE"; -- Sets output alignment to "NONE", "C0" or "C1"
INIT : bit := '0'; -- Sets initial state of the Q0
SRTYPE : string := "SYNC"); -- Specifies "SYNC" or "ASYNC" set/reset
port ( Q : out std_ulogic; -- 1-bit DDR output data
C0 : in std_ulogic; -- 1-bit clock input
C1 : in std_ulogic; -- 1-bit clock input
CE : in std_ulogic; -- 1-bit clock enable input
D0 : in std_ulogic; -- 1-bit data input (associated with C1)
D1 : in std_ulogic; -- 1-bit data input (associated with C1)
R : in std_ulogic; -- 1-bit reset input
S : in std_ulogic); -- 1-bit set input
end component;
component FD
generic (INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component IDDR2
generic (DDR_ALIGNMENT : string := "NONE"; -- Sets output alignment to "NONE", "C0" or "C1"
INIT_Q0 : bit := '0'; -- Sets initial state of the Q0
INIT_Q1 : bit := '0'; -- Sets initial state of the Q1
SRTYPE : string := "SYNC"); -- Specifies "SYNC" or "ASYNC" set/reset
port ( Q0 : out std_ulogic; -- 1-bit output captured with C0 clock
Q1 : out std_ulogic; -- 1-bit output captured with C1 clock
C0 : in std_ulogic; -- 1-bit clock input
C1 : in std_ulogic; -- 1-bit clock input
CE : in std_ulogic; -- 1-bit clock enable input
D : in std_ulogic; -- 1-bit DDR data input
R : in std_ulogic; -- 1-bit reset input
S : in std_ulogic); -- 1-bit set input
end component;
signal vcc, gnd, oe, lockl : std_ulogic;
signal dqsn : std_logic_vector(dbits/8-1 downto 0);
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal ddr_clk_fbl, ddr_clk_fb_outl : std_ulogic;
signal clk_90ro : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal rclk0b, rclk90b, rclk180b, rclk270b : std_ulogic;
signal rclk0, rclk90, rclk180, rclk270 : std_ulogic;
signal rclk0b_high, rclk90b_high, rclk270b_high : std_ulogic;
signal rclk0_high, rclk90_high, rclk270_high : std_ulogic;
signal locked, vlockl, dllfb : std_ulogic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr row address
signal ddr_bar : std_logic_vector (1+eightbanks downto 0); -- ddr bank address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr mask
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqinl : std_logic_vector (dbits*2-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst : std_ulogic;
signal dll1rst : std_ulogic;
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal odtl : std_logic_vector(1 downto 0);
--signals needed for alignment with DQS
signal dm_delay : std_logic_vector (dbits/8-1 downto 0);
signal dqout_delay : std_logic_vector (dbits-1 downto 0);
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of dqsn : signal is true;
attribute syn_preserve of dqsn : signal is true;
attribute keep of mclkfx : signal is true;
attribute keep of clk_90ro : signal is true;
attribute syn_keep of mclkfx : signal is true;
attribute syn_keep of clk_90ro : signal is true;
-- To prevent synplify 9.4 to remove any of these registers.
attribute syn_noprune : boolean;
attribute syn_noprune of FD : component is true;
attribute syn_noprune of IDDR2 : component is true;
attribute syn_noprune of ODDR2 : component is true;
begin
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
mlock <= '1';
mbufg0 : BUFG port map (I => clk, O => mclk);
end generate;
clkscale : if clk_mul /= clk_div generate
rstdel : process (clk, rst)
begin
if rst = '0' then
dll0rst <= '1';
elsif rising_edge(clk) then
dll0rst <= '0';
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
dllm : DCM
generic map (CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div)
port map (CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst, CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
-- DDR clock generation (90 degrees phase-shifted DLL)
bufg2 : BUFG port map (I => clk_90ro, O => clk90r);
dllfb <= clk90r;
dll : DCM
generic map (CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => 64)
port map (CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_90ro,
CLK90 => open, CLK180 => open, CLK270 => open,
LOCKED => lockl);
clk0r <= mclk;
clk180r <= not mclk;
clk270r <= not clk90r;
clkout <= mclk;
rstdel : process (mclk, rst, mlock)
begin
if rst = '0' or mlock = '0' then
dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16);
vlock := '0';
elsif vlock = '0' then
cnt := cnt -1;
vlock := cnt(15) and not co;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
ddrclocks : for i in 0 to 2 generate
dclk0r : ODDR2
port map (Q => ddr_clkl(i), C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => vcc, D1 => gnd, R => gnd, S => gnd);
ddrclk_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_clk(i), ddr_clkl(i));
dclk0rb : ODDR2
port map (Q => ddr_clkbl(i), C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => gnd, D1 => vcc, R => gnd, S => gnd);
ddrclkb_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_clkb(i), ddr_clkbl(i));
end generate;
-- Generate the DDR clock to be fed back for DQ synchronization
dclkfb0r : ODDR2
port map (Q => ddr_clk_fb_outl, C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => vcc, D1 => gnd, R => gnd, S => gnd);
ddrclkfb_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_clk_fb_out, ddr_clk_fb_outl);
-- The above clock fed back for DQ synchronization
ddrref_pad : clkpad generic map (tech => virtex4)
port map (ddr_clk_fb, ddr_clk_fbl);
-- ODT pads
odtgen : for i in 0 to 1 generate
odtl(i) <= locked and odt(i);
ddr_odt_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_odt(i), odtl(i));
end generate;
-- DDR single-edge control signals
ddrbanks : for i in 0 to 1 generate
csn0gen : FD
port map ( Q => ddr_csnr(i), C => clk0r, D => csn(i));
csn0_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_csb(i), ddr_csnr(i));
ckel(i) <= cke(i) and locked;
ckegen : FD
port map ( Q => ddr_ckenr(i), C => clk0r, D => ckel(i));
cke_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_cke(i), ddr_ckenr(i));
end generate;
rasgen : FD
port map ( Q => ddr_rasnr, C => clk0r, D => rasn);
rasn_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_rasb, ddr_rasnr);
casgen : FD
port map ( Q => ddr_casnr, C => clk0r, D => casn);
casn_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_casb, ddr_casnr);
wengen : FD
port map ( Q => ddr_wenr, C => clk0r, D => wen);
wen_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_web, ddr_wenr);
bagen : for i in 0 to 1+eightbanks generate
ba0 : FD
port map ( Q => ddr_bar(i), C => clk0r, D => ba(i));
ddr_ba_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_ba(i), ddr_bar(i));
end generate;
addrgen : for i in 0 to 13 generate
addr0 : FD
port map ( Q => ddr_adr(i), C => clk0r, D => addr(i));
ddr_ad_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_ad(i), ddr_adr(i));
end generate;
-- Data mask (DM) generation
dmgen : for i in 0 to dbits/8-1 generate
dq_delay : FD
port map ( Q => dm_delay(i), C => clk0r, D => dm(i));
dm0 : ODDR2
generic map (DDR_ALIGNMENT => "NONE")
port map (Q => ddr_dmr(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => dm(i+dbits/8), D1 => dm_delay(i), R => gnd, S => gnd);
ddr_bm_pad : outpad
generic map (tech => virtex4, level => sstl18_i)
port map (ddr_dm(i), ddr_dmr(i));
end generate;
-- Data strobe (DQS) generation
dqsgen : for i in 0 to dbits/8-1 generate
dsqreg : FD port map ( Q => dqsn(i), C => clk180r, D => oe);
da0 : ODDR2
port map ( Q => ddr_dqsin(i), C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => dqsn(i), D1 => gnd, R => gnd, S => gnd);
doen : FD
port map ( Q => ddr_dqsoen(i), C => clk0r, D => dqsoen);
dqs_pad : iopad_ds
generic map (tech => virtex5, level => sstl18_ii)
port map (padp => ddr_dqs(i), padn => ddr_dqsn(i), i => ddr_dqsin(i),
en => ddr_dqsoen(i), o => ddr_dqsoutl(i));
end generate;
-- Phase shift the feedback clock and use it to latch DQ
rstphase : process (ddr_clk_fbl, rst, lockl)
begin
if rst = '0' or lockl = '0' then
dll1rst <= '1';
elsif rising_edge(ddr_clk_fbl) then
dll1rst <= '0';
end if;
end process;
bufg7 : BUFG port map (I => rclk90, O => rclk90b);
-- bufg8 : BUFG port map (I => rclk270, O => rclk270b);
rclk270b <= not rclk90b;
bufg9 : BUFG port map (I => rclk180, O => rclk180b);
read_dll : DCM
generic map (clkin_period => 8.0, DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
CLKOUT_PHASE_SHIFT => "VARIABLE", PHASE_SHIFT => rskew)
port map ( CLKIN => ddr_clk_fbl, CLKFB => rclk90b, DSSEN => gnd, PSCLK => mclk,
PSEN => cal_pll(0), PSINCDEC => cal_pll(1), RST => dll1rst, CLK0 => rclk90,
CLK90 => rclk180); --, CLK180 => rclk270);
-- Data bus
ddgen : for i in 0 to dbits-1 generate
qi : IDDR2
port map (Q0 => dqinl(i+dbits), -- 1-bit output for positive edge of C0
Q1 => dqinl(i), -- 1-bit output for negative edge of C1
C0 => rclk90b, -- 1-bit clock input
C1 => rclk270b, -- 1-bit clock input
CE => vcc, -- 1-bit clock enable input
D => ddr_dqin(i), -- 1-bit DDR data input
R => gnd, -- 1-bit reset
S => gnd); -- 1-bit set
dinq0 : FD
port map ( Q => dqin(i+dbits), C => rclk180b, D => dqinl(i));
dinq1 : FD
port map ( Q => dqin(i), C => rclk180b, D => dqinl(i+dbits));
dq_delay : FD
port map ( Q => dqout_delay(i), C => clk0r, D => dqout(i));
dout : ODDR2
generic map (DDR_ALIGNMENT => "NONE")
port map (Q => ddr_dqout(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => dqout(i+dbits), D1 => dqout_delay(i), R => gnd, S => gnd);
doen : FD
port map (Q => ddr_dqoen(i), C => clk0r, D => oen);
dq_pad : iopad
generic map (tech => virtex4, level => sstl18_ii)
port map (pad => ddr_dq(i), i => ddr_dqout(i), en => ddr_dqoen(i), o => ddr_dqin(i));
end generate;
end;
------------------------------------------------------------------
-- Spartan 6 DDR2 PHY -------------------------------------------
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM_SP;
use unisim.IDDR2;
use unisim.ODDR2;
use unisim.FD;
use unisim.IODELAY2;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity spartan6_ddr2_phy_wo_pads is
generic (MHz : integer := 125; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2;
clk_div : integer := 2; tech : integer := spartan6;
rskew : integer := 0; eightbanks : integer range 0 to 1 := 0;
abits : integer := 14;
nclk : integer := 3; ncs : integer := 2 );
port ( rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- DDR clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0);
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0);
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0);
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0); -- row address
ba : in std_logic_vector ( 2 downto 0); -- bank address
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(ncs-1 downto 0));
end;
architecture rtl of spartan6_ddr2_phy_wo_pads is
component DCM_SP is
generic (
CLKDV_DIVIDE : real := 2.0;
CLKFX_DIVIDE : integer := 1;
CLKFX_MULTIPLY : integer := 4;
CLKIN_DIVIDE_BY_2 : boolean := false;
CLKIN_PERIOD : real := 10.0;
CLKOUT_PHASE_SHIFT : string := "NONE";
CLK_FEEDBACK : string := "1X";
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS";
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DSS_MODE : string := "NONE";
DUTY_CYCLE_CORRECTION : boolean := true;
FACTORY_JF : bit_vector := X"C080";
PHASE_SHIFT : integer := 0;
STARTUP_WAIT : boolean := false );
port (
CLK0 : out std_ulogic;
CLK180 : out std_ulogic;
CLK270 : out std_ulogic;
CLK2X : out std_ulogic;
CLK2X180 : out std_ulogic;
CLK90 : out std_ulogic;
CLKDV : out std_ulogic;
CLKFX : out std_ulogic;
CLKFX180 : out std_ulogic;
LOCKED : out std_ulogic;
PSDONE : out std_ulogic;
STATUS : out std_logic_vector(7 downto 0);
CLKFB : in std_ulogic;
CLKIN : in std_ulogic;
DSSEN : in std_ulogic;
PSCLK : in std_ulogic;
PSEN : in std_ulogic;
PSINCDEC : in std_ulogic;
RST : in std_ulogic );
end component;
component BUFG
port (O : out std_logic;
I : in std_logic);
end component;
component ODDR2
generic (DDR_ALIGNMENT : string := "NONE"; -- Sets output alignment to "NONE", "C0" or "C1"
INIT : bit := '0'; -- Sets initial state of the Q0
SRTYPE : string := "SYNC"); -- Specifies "SYNC" or "ASYNC" set/reset
port ( Q : out std_ulogic; -- 1-bit DDR output data
C0 : in std_ulogic; -- 1-bit clock input
C1 : in std_ulogic; -- 1-bit clock input
CE : in std_ulogic; -- 1-bit clock enable input
D0 : in std_ulogic; -- 1-bit data input (associated with C1)
D1 : in std_ulogic; -- 1-bit data input (associated with C1)
R : in std_ulogic; -- 1-bit reset input
S : in std_ulogic); -- 1-bit set input
end component;
component FD
generic (INIT : bit := '0');
port ( Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic);
end component;
component IDDR2
generic (DDR_ALIGNMENT : string := "NONE"; -- Sets output alignment to "NONE", "C0" or "C1"
INIT_Q0 : bit := '0'; -- Sets initial state of the Q0
INIT_Q1 : bit := '0'; -- Sets initial state of the Q1
SRTYPE : string := "SYNC"); -- Specifies "SYNC" or "ASYNC" set/reset
port ( Q0 : out std_ulogic; -- 1-bit output captured with C0 clock
Q1 : out std_ulogic; -- 1-bit output captured with C1 clock
C0 : in std_ulogic; -- 1-bit clock input
C1 : in std_ulogic; -- 1-bit clock input
CE : in std_ulogic; -- 1-bit clock enable input
D : in std_ulogic; -- 1-bit DDR data input
R : in std_ulogic; -- 1-bit reset input
S : in std_ulogic); -- 1-bit set input
end component;
component IODELAY2 is
generic (
COUNTER_WRAPAROUND : string := "WRAPAROUND";
DATA_RATE : string := "SDR";
DELAY_SRC : string := "IO";
IDELAY2_VALUE : integer := 0;
IDELAY_MODE : string := "NORMAL";
IDELAY_TYPE : string := "DEFAULT";
IDELAY_VALUE : integer := 0;
ODELAY_VALUE : integer := 0;
SERDES_MODE : string := "NONE";
SIM_TAPDELAY_VALUE : integer := 75 );
port (
BUSY : out std_ulogic;
DATAOUT : out std_ulogic;
DATAOUT2 : out std_ulogic;
DOUT : out std_ulogic;
TOUT : out std_ulogic;
CAL : in std_ulogic;
CE : in std_ulogic;
CLK : in std_ulogic;
IDATAIN : in std_ulogic;
INC : in std_ulogic;
IOCLK0 : in std_ulogic;
IOCLK1 : in std_ulogic;
ODATAIN : in std_ulogic;
RST : in std_ulogic;
T : in std_ulogic );
end component;
signal vcc, gnd, oe, lockl : std_ulogic;
signal dqsn : std_logic_vector(dbits/8-1 downto 0);
signal dqsoen_reg : std_logic_vector(dbits/8-1 downto 0);
signal ddr_dq_indel : std_logic_vector(dbits-1 downto 0);
signal ckel : std_logic_vector(ncs-1 downto 0);
signal clk_90ro : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, dllfb : std_ulogic;
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal delay_cal : std_ulogic;
signal dcal_started : std_ulogic;
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of dqsn : signal is true;
attribute syn_preserve of dqsn : signal is true;
attribute keep of mclkfx : signal is true;
attribute keep of clk_90ro : signal is true;
attribute syn_keep of mclkfx : signal is true;
attribute syn_keep of clk_90ro : signal is true;
-- To prevent synplify 9.4 to remove any of these registers.
attribute syn_noprune : boolean;
attribute syn_noprune of FD : component is true;
attribute syn_noprune of IDDR2 : component is true;
attribute syn_noprune of ODDR2 : component is true;
begin
oe <= not oen;
vcc <= '1'; gnd <= '0';
-- Optional DDR clock multiplication
noclkscale : if clk_mul = clk_div generate
mlock <= '1';
mclk <= clk;
-- mbufg0 : BUFG port map (I => clk, O => mclk);
end generate;
clkscale : if clk_mul /= clk_div generate
-- Extend DCM reset signal.
dll0rstdel : process (clk, rst)
begin
if rst = '0' then
dll0rst <= (others => '1');
elsif rising_edge(clk) then
dll0rst <= dll0rst(1 to 3) & "0";
end if;
end process;
bufg0 : BUFG port map (I => mclkfx, O => mclk);
bufg1 : BUFG port map (I => mclk0, O => mclkfb);
dllm : DCM_SP
generic map (
CLKFX_MULTIPLY => clk_mul, CLKFX_DIVIDE => clk_div,
CLK_FEEDBACK => "1X", CLKIN_PERIOD => 1000.0/real(MHz) )
port map (CLKIN => clk, CLKFB => mclkfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dll0rst(0), CLK0 => mclk0,
LOCKED => mlock, CLKFX => mclkfx );
end generate;
-- DDR clock generation (90 degrees phase-shifted DLL)
bufg2 : BUFG port map (I => clk_90ro, O => clk90r);
dllfb <= clk90r;
dll : DCM_SP
generic map ( CLKFX_MULTIPLY => 2, CLKFX_DIVIDE => 2,
CLKOUT_PHASE_SHIFT => "FIXED", PHASE_SHIFT => 64 )
port map (CLKIN => mclk, CLKFB => dllfb, DSSEN => gnd, PSCLK => gnd,
PSEN => gnd, PSINCDEC => gnd, RST => dllrst(0), CLK0 => clk_90ro,
CLK90 => open, CLK180 => open, CLK270 => open,
LOCKED => lockl);
clk0r <= mclk;
clk180r <= not mclk;
clk270r <= not clk90r;
clkout <= mclk;
-- Extend DCM reset signal.
dllrstdel : process (mclk, rst, mlock)
begin
if rst = '0' or mlock = '0' then
dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & "0";
end if;
end process;
-- Delay lock signal.
rdel : if rstdelay /= 0 generate
rcnt : process (clk0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16);
vlock := '0';
elsif vlock = '0' then
cnt := cnt -1;
vlock := cnt(15) and not co;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
ddrclocks : for i in 0 to nclk-1 generate
dclk0r : ODDR2
port map ( Q => ddr_clk(i), C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => vcc, D1 => gnd, R => gnd, S => gnd );
end generate;
-- DDR single-edge control signals
ddrbanks : for i in 0 to ncs-1 generate
ddr_odt(i) <= locked and odt(i);
csn0gen : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_csb(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => csn(i), D1 => csn(i), R => gnd, S => gnd );
ckel(i) <= cke(i) and locked;
ckegen : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_cke(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => ckel(i), D1 => ckel(i), R => gnd, S => gnd );
end generate;
rasgen : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_rasb, C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => rasn, D1 => rasn, R => gnd, S => gnd );
casgen : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_casb, C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => casn, D1 => casn, R => gnd, S => gnd );
wengen : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_web, C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => wen, D1 => wen, R => gnd, S => gnd );
bagen : for i in 0 to 1+eightbanks generate
ba0 : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_ba(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => ba(i), D1 => ba(i), R => gnd, S => gnd );
end generate;
addrgen : for i in 0 to abits-1 generate
addr0 : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_ad(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => addr(i), D1 => addr(i), R => gnd, S => gnd );
end generate;
-- Data mask (DM) generation
dmgen : for i in 0 to dbits/8-1 generate
dmgen0 : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_dm(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => dm(i+dbits/8), D1 => dm(i), R => gnd, S => gnd );
end generate;
-- Data strobe (DQS) generation
dqsgen : for i in 0 to dbits/8-1 generate
dqsreg : FD
port map ( Q => dqsn(i), C => clk180r, D => oe );
dqsgen0 : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_dqs_out(i), C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => dqsn(i), D1 => gnd, R => gnd, S => gnd );
doenreg : FD
port map ( Q => dqsoen_reg(i), C => clk180r, D => dqsoen );
doen0 : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_dqs_oen(i), C0 => clk90r, C1 => clk270r, CE => vcc,
D0 => dqsoen_reg(i), D1 => dqsoen_reg(i), R => gnd, S => gnd );
end generate;
-- Data bus
ddgen : for i in 0 to dbits-1 generate
dqdelay : IODELAY2
generic map ( DATA_RATE => "DDR", DELAY_SRC => "IDATAIN",
IDELAY_TYPE => "VARIABLE_FROM_ZERO" )
port map ( BUSY => open, CAL => delay_cal, CE => cal_en(i/8), CLK => clk0r,
DATAOUT => ddr_dq_indel(i), DATAOUT2 => open, DOUT => open,
IDATAIN => ddr_dq_in(i), INC => cal_inc(i/8),
IOCLK0 => clk0r, IOCLK1 => clk180r,
ODATAIN => gnd, RST => cal_rst, T => vcc, TOUT => open );
din : IDDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( D => ddr_dq_indel(i), C0 => clk0r, C1 => clk180r, CE => vcc,
R => gnd, S => gnd, Q0 => dqin(i), Q1 => dqin(i+dbits) );
dout : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_dq_out(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => dqout(i+dbits), D1 => dqout(i), R => gnd, S => gnd );
doen : ODDR2
generic map ( DDR_ALIGNMENT => "C0", SRTYPE => "ASYNC" )
port map ( Q => ddr_dq_oen(i), C0 => clk0r, C1 => clk180r, CE => vcc,
D0 => oen, D1 => oen, R => gnd, S => gnd );
end generate;
-- Generate IODELAY calibration command after core reset.
calcmd : process (mclk, rst)
begin
if rst = '0' then
dcal_started <= '0';
delay_cal <= '0';
elsif rising_edge(mclk) then
if mlock = '1' then
dcal_started <= '1';
delay_cal <= not dcal_started;
end if;
end if;
end process;
end architecture;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/maps/syncram.vhd | 1 | 10672 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncram
-- File: syncram.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: syncronous 1-port ram with tech selection
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config.all;
use grlib.config_types.all;
use grlib.stdlib.all;
use work.gencomp.all;
use work.allmem.all;
entity syncram is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
testen : integer := 0; custombits: integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(custombits-1 downto 0));
end;
architecture rtl of syncram is
constant nctrl : integer := abits + (TESTIN_WIDTH-2) + 2;
signal rena, wena : std_logic;
signal dataoutx, databp, testdata : std_logic_vector((dbits -1) downto 0);
constant SCANTESTBP : boolean := (testen = 1) and (tech /= 0) and (tech /= ut90);
signal xenable, xwrite: std_ulogic;
signal custominx,customoutx: std_logic_vector(syncram_customif_maxwidth downto 0);
begin
xenable <= enable and not testin(TESTIN_WIDTH-2) when testen/=0 else enable;
xwrite <= write and not testin(TESTIN_WIDTH-2) when testen/=0 else write;
-- RAM bypass for scan
scanbp : if SCANTESTBP generate
comb : process (address, datain, enable, write, testin)
variable tmp : std_logic_vector((dbits -1) downto 0);
variable ctrlsigs : std_logic_vector((nctrl -1) downto 0);
begin
ctrlsigs := testin(TESTIN_WIDTH-3 downto 0) & write & enable & address;
tmp := datain;
for i in 0 to nctrl-1 loop
tmp(i mod dbits) := tmp(i mod dbits) xor ctrlsigs(i);
end loop;
testdata <= tmp;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
databp <= testdata;
end if;
end process;
dmuxout : for i in 0 to dbits-1 generate
x0: grmux2 generic map (tech)
port map (dataoutx(i), databp(i), testin(TESTIN_WIDTH-1), dataout(i));
end generate;
end generate;
custominx(custominx'high downto custombits) <= (others => '0');
custominx(custombits-1 downto 0) <= customin;
customout <= customoutx(custombits-1 downto 0);
nocust: if syncram_has_customif(tech)=0 generate
customoutx <= (others => '0');
end generate;
noscanbp : if not SCANTESTBP generate dataout <= dataoutx; end generate;
inf : if tech = inferred generate
x0 : generic_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, write);
end generate;
xcv : if (tech = virtex) generate
x0 : virtex_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
xc2v : if (is_unisim(tech) = 1) and (tech /= virtex) generate
x0 : unisim_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
vir : if tech = memvirage generate
x0 : virage_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
atrh : if tech = atc18rha generate
x0 : atc18rha_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite,
testin(TESTIN_WIDTH-1 downto TESTIN_WIDTH-4));
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
x0 : axcel_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
proa : if tech = proasic generate
x0 : proasic_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
umc18 : if tech = umc generate
x0 : umc_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
rhu : if tech = rhumc generate
x0 : rhumc_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
saed : if tech = saed32 generate
x0 : saed32_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
dar : if tech = dare generate
x0 : dare_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
proa3 : if tech = apa3 generate
x0 : proasic3_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
proa3e : if tech = apa3e generate
x0 : proasic3e_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
proa3l : if tech = apa3l generate
x0 : proasic3l_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
fus : if tech = actfus generate
x0 : fusion_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
ihp : if tech = ihp25 generate
x0 : ihp25_syncram generic map(abits, dbits)
port map(clk, address, datain, dataoutx, xenable, xwrite);
end generate;
ihprh : if tech = ihp25rh generate
x0 : ihp25rh_syncram generic map(abits, dbits)
port map(clk, address, datain, dataoutx, xenable, xwrite);
end generate;
alt : if (tech = altera) or (tech = stratix1) or (tech = stratix2) or
(tech = stratix3) or (tech = stratix4) or (tech = cyclone3) generate
x0 : altera_syncram generic map(abits, dbits)
port map(clk, address, datain, dataoutx, xenable, xwrite);
end generate;
rht : if tech = rhlib18t generate
x0 : rh_lib18t_syncram generic map(abits, dbits)
port map(clk, address, datain, dataoutx, xenable, xwrite, testin(TESTIN_WIDTH-3 downto TESTIN_WIDTH-4));
end generate;
lat : if tech = lattice generate
x0 : ec_syncram generic map(abits, dbits)
port map(clk, address, datain, dataoutx, xenable, xwrite);
end generate;
ut025 : if tech = ut25 generate
x0 : ut025crh_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
ut09 : if tech = ut90 generate
x0 : ut90nhbd_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite, testin(TESTIN_WIDTH-3));
end generate;
ut13 : if tech = ut130 generate
x0 : ut130hbd_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
pere : if tech = peregrine generate
x0 : peregrine_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
arti : if tech = memartisan generate
x0 : artisan_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
cust1 : if tech = custom1 generate
x0 : custom1_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
ecl : if tech = eclipse generate
rena <= xenable and not write;
wena <= xenable and write;
x0 : eclipse_syncram_2p generic map(abits, dbits)
port map(clk, rena, address, dataoutx, clk, address,
datain, wena);
end generate;
virage90 : if tech = memvirage90 generate
x0 : virage90_syncram generic map(abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
nex : if tech = easic90 generate
x0 : nextreme_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
smic : if tech = smic013 generate
x0 : smic13_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
tm65gplu : if tech = tm65gplus generate
x0 : tm65gplus_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
cmos9sfx : if tech = cmos9sf generate
x0 : cmos9sf_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
n2x : if tech = easic45 generate
x0 : n2x_syncram generic map (abits, dbits)
port map (clk, address, datain, dataoutx, xenable, xwrite);
end generate;
rh13t : if tech = rhlib13t generate
x0 : rh_lib13t_syncram generic map(abits, dbits)
port map(clk, address, datain, dataoutx, xenable, xwrite, testin(TESTIN_WIDTH-3 downto TESTIN_WIDTH-4));
end generate;
-- pragma translate_off
noram : if has_sram(tech) = 0 generate
x : process
begin
assert false report "syncram: technology " & tech_table(tech) &
" not supported"
severity failure;
wait;
end process;
end generate;
dmsg : if GRLIB_CONFIG_ARRAY(grlib_debug_level) >= 2 generate
x : process
begin
assert false report "syncram: " & tost(2**abits) & "x" & tost(dbits) &
" (" & tech_table(tech) & ")"
severity note;
wait;
end process;
end generate;
-- pragma translate_on
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/irqmp/irqmp.vhd | 1 | 11203 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: irqmp
-- File: irqmp.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Multi-processor APB interrupt controller. Implements a
-- two-level interrupt controller for 15 interrupts.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.leon3.all;
entity irqmp is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
ncpu : integer := 1;
eirq : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
irqi : in irq_out_vector(0 to ncpu-1);
irqo : out irq_in_vector(0 to ncpu-1)
);
end;
architecture rtl of irqmp is
constant REVISION : integer := 3;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_IRQMP, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
type mask_type is array (0 to ncpu-1) of std_logic_vector(15 downto 1);
type mask2_type is array (0 to ncpu-1) of std_logic_vector(15 downto 0);
type irl_type is array (0 to ncpu-1) of std_logic_vector(3 downto 0);
type irl2_type is array (0 to ncpu-1) of std_logic_vector(4 downto 0);
type reg_type is record
imask : mask_type;
ilevel : std_logic_vector(15 downto 1);
ipend : std_logic_vector(15 downto 1);
iforce : mask_type;
ibroadcast : std_logic_vector(15 downto 1);
irl : irl_type;
cpurst : std_logic_vector(ncpu-1 downto 0);
end record;
type ereg_type is record
imask : mask2_type;
ipend : std_logic_vector(15 downto 0);
irl : irl2_type;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RRES : reg_type := (
imask => (others => (others => '0')), ilevel => (others => '0'),
ipend => (others => '0'), iforce => (others => (others => '0')),
ibroadcast => (others => '0'), irl => (others => (others => '0')),
cpurst => (others => '0'));
constant ERES : ereg_type := (
imask => (others => (others => '0')), ipend => (others => '0'),
irl => (others => (others => '0')));
function prioritize(b : std_logic_vector(15 downto 0)) return std_logic_vector is
variable a : std_logic_vector(15 downto 0);
variable irl : std_logic_vector(3 downto 0);
variable level : integer range 0 to 15;
begin
irl := "0000"; level := 0; a := b;
for i in 15 downto 0 loop
level := i;
if a(i) = '1' then exit; end if;
end loop;
irl := conv_std_logic_vector(level, 4);
return(irl);
end;
signal r, rin : reg_type;
signal r2, r2in : ereg_type;
begin
comb : process(rst, r, r2, apbi, irqi)
variable v : reg_type;
variable temp : mask_type;
variable prdata : std_logic_vector(31 downto 0);
variable tmpirq : std_logic_vector(15 downto 0);
variable tmpvar : std_logic_vector(15 downto 1);
variable cpurun : std_logic_vector(ncpu-1 downto 0);
variable v2 : ereg_type;
variable irl2 : std_logic_vector(3 downto 0);
variable ipend2 : std_logic_vector(ncpu-1 downto 0);
variable temp2 : mask2_type;
variable neirq : integer;
begin
v := r; v.cpurst := (others => '0');
cpurun := (others => '0'); cpurun(0) := '1';
tmpvar := (others => '0'); ipend2 := (others => '0');
v2 := r2;
-- prioritize interrupts
if eirq /= 0 then
for i in 0 to ncpu-1 loop
temp2(i) := r2.ipend and r2.imask(i);
ipend2(i) := orv(temp2(i));
end loop;
end if;
for i in 0 to ncpu-1 loop
temp(i) := ((r.iforce(i) or r.ipend) and r.imask(i));
if eirq /= 0 then temp(i)(eirq) := temp(i)(eirq) or ipend2(i); end if;
v.irl(i) := prioritize((temp(i) and r.ilevel) & '0');
if v.irl(i) = "0000" then
if eirq /= 0 then temp(i)(eirq) := temp(i)(eirq) or ipend2(i); end if;
v.irl(i) := prioritize((temp(i) and not r.ilevel) & '0');
end if;
end loop;
-- register read
prdata := (others => '0');
case apbi.paddr(7 downto 6) is
when "00" =>
case apbi.paddr(4 downto 2) is
when "000" => prdata(15 downto 1) := r.ilevel;
when "001" =>
prdata(15 downto 1) := r.ipend;
if eirq /= 0 then prdata(31 downto 16) := r2.ipend; end if;
when "010" => prdata(15 downto 1) := r.iforce(0);
when "011" =>
when "100" | "101" =>
prdata(31 downto 28) := conv_std_logic_vector(ncpu-1, 4);
prdata(19 downto 16) := conv_std_logic_vector(eirq, 4);
for i in 0 to ncpu -1 loop prdata(i) := irqi(i).pwd; end loop;
if ncpu > 1 then
prdata(27) := '1';
case apbi.paddr(4 downto 2) is
when "101" =>
prdata := (others => '0');
prdata(15 downto 1) := r.ibroadcast;
when others =>
end case;
end if;
when others =>
end case;
when "01" =>
for i in 0 to ncpu-1 loop
if i = conv_integer( apbi.paddr(5 downto 2)) then
prdata(15 downto 1) := r.imask(i);
if eirq /= 0 then prdata(31 downto 16) := r2.imask(i); end if;
end if;
end loop;
when "10" =>
for i in 0 to ncpu-1 loop
if i = conv_integer( apbi.paddr(5 downto 2)) then
prdata(15 downto 1) := r.iforce(i);
end if;
end loop;
when "11" =>
if eirq /= 0 then
for i in 0 to ncpu-1 loop
if i = conv_integer( apbi.paddr(5 downto 2)) then
prdata(4 downto 0) := r2.irl(i);
end if;
end loop;
end if;
when others =>
end case;
-- register write
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(7 downto 6) is
when "00" =>
case apbi.paddr(4 downto 2) is
when "000" => v.ilevel := apbi.pwdata(15 downto 1);
when "001" => v.ipend := apbi.pwdata(15 downto 1);
if eirq /= 0 then v2.ipend := apbi.pwdata(31 downto 16); end if;
when "010" => v.iforce(0) := apbi.pwdata(15 downto 1);
when "011" => v.ipend := r.ipend and not apbi.pwdata(15 downto 1);
if eirq /= 0 then v2.ipend := r2.ipend and not apbi.pwdata(31 downto 16); end if;
when "100" =>
for i in 0 to ncpu -1 loop v.cpurst(i) := apbi.pwdata(i); end loop;
when others =>
if ncpu > 1 then
case apbi.paddr(4 downto 2) is
when "101" =>
v.ibroadcast := apbi.pwdata(15 downto 1);
when others =>
end case;
end if;
end case;
when "01" =>
for i in 0 to ncpu-1 loop
if i = conv_integer( apbi.paddr(5 downto 2)) then
v.imask(i) := apbi.pwdata(15 downto 1);
if eirq /= 0 then v2.imask(i) := apbi.pwdata(31 downto 16); end if;
end if;
end loop;
when "10" =>
for i in 0 to ncpu-1 loop
if i = conv_integer( apbi.paddr(5 downto 2)) then
v.iforce(i) := (r.iforce(i) or apbi.pwdata(15 downto 1)) and
not apbi.pwdata(31 downto 17);
end if;
end loop;
when others =>
end case;
end if;
-- register new interrupts
for i in 1 to 15 loop
if i > NAHBIRQ-1 then
exit;
end if;
if ncpu = 1 then
v.ipend(i) := v.ipend(i) or apbi.pirq(i);
else
v.ipend(i) := v.ipend(i) or (apbi.pirq(i) and not r.ibroadcast(i));
for j in 0 to ncpu-1 loop
tmpvar := v.iforce(j);
tmpvar(i) := tmpvar(i) or (apbi.pirq(i) and r.ibroadcast(i));
v.iforce(j) := tmpvar;
end loop;
end if;
end loop;
if eirq /= 0 then
for i in 16 to 31 loop
if i > NAHBIRQ-1 then exit; end if;
v2.ipend(i-16) := v2.ipend(i-16) or apbi.pirq(i);
end loop;
end if;
-- interrupt acknowledge
for i in 0 to ncpu-1 loop
if irqi(i).intack = '1' then
tmpirq := decode(irqi(i).irl);
temp(i) := tmpirq(15 downto 1);
v.iforce(i) := v.iforce(i) and not temp(i);
v.ipend := v.ipend and not ((not r.iforce(i)) and temp(i));
if eirq /= 0 then
if eirq = conv_integer(irqi(i).irl) then
v2.irl(i) := orv(temp2(i)) & prioritize(temp2(i));
if v2.irl(i)(4) = '1' then
v2.ipend(conv_integer(v2.irl(i)(3 downto 0))) := '0';
end if;
end if;
end if;
end if;
end loop;
-- reset
if (not RESET_ALL) and (rst = '0') then
v.imask := RRES.imask; v.iforce := RRES.iforce; v.ipend := RRES.ipend;
if ncpu > 1 then
v.ibroadcast := RRES.ibroadcast;
end if;
v2.ipend := ERES.ipend; v2.imask := ERES.imask; v2.irl := ERES.irl;
end if;
apbo.prdata <= prdata;
for i in 0 to ncpu-1 loop
irqo(i).irl <= r.irl(i); irqo(i).rst <= r.cpurst(i);
irqo(i).run <= cpurun(i);
irqo(i).rstvec <= (others => '0'); -- Alternate reset vector
irqo(i).iact <= '0';
irqo(i).index <= conv_std_logic_vector(i, 4);
irqo(i).hrdrst <= '0';
end loop;
rin <= v; r2in <= v2;
end process;
apbo.pirq <= (others => '0');
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and (rst = '0') then r <= RRES; end if;
end if;
end process;
dor2regs : if eirq /= 0 generate
regs : process(clk)
begin
if rising_edge(clk) then
r2 <= r2in;
if RESET_ALL and (rst = '0') then r2 <= ERES; end if;
end if;
end process;
end generate;
nor2regs : if eirq = 0 generate
-- r2 <= ((others => "0000000000000000"), "0000000000000000", (others => "00000"));
r2.ipend <= (others => '0');
driveregs: for i in 0 to (ncpu-1) generate
r2.imask(i) <= (others => '0');
r2.irl(i) <= (others => '0');
end generate driveregs;
end generate;
-- pragma translate_off
bootmsg : report_version
generic map ("irqmp" &
": Multi-processor Interrupt Controller rev " & tost(REVISION) &
", #cpu " & tost(NCPU) & ", eirq " & tost(eirq));
-- pragma translate_on
end;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/greth/greth_mb.vhd | 1 | 13884 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_mb
-- File: greth_mb.vhd
-- Author: Marko Isomaki
-- Description: Ethernet Media Access Controller with Ethernet Debug
-- Communication Link and dual AHB master interfaces
------------------------------------------------------------------------------
library ieee;
library grlib;
library gaisler;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use gaisler.net.all;
use gaisler.ethernet_mac.all;
library eth;
use eth.ethcomp.all;
entity greth_mb is
generic(
hindex : integer := 0;
ehindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahb : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbmi2 : in ahb_mst_in_type;
ahbmo2 : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end entity;
architecture rtl of greth_mb is
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer is
begin
if (edcl /= 0) and (ebufsize > fifosize) then
return ebufsize;
else
return fifosize;
end if;
end function;
constant fabits : integer := log2(fifosize);
type szvct is array (0 to 6) of integer;
constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256);
constant eabits : integer := log2(edclbufsz) + 8;
constant bufsize : std_logic_vector(2 downto 0) :=
conv_std_logic_vector(log2(edclbufsz), 3);
constant ebufsize : integer := ebuf(log2(edclbufsz));
constant txfifosize : integer := getfifosize(edcl, fifosize, ebufsize);
constant txfabits : integer := log2(txfifosize);
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_ETHMAC, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_ETHMAC, 0, revision, 0),
others => zero32);
constant ehconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_EDCLMST, 0, REVISION, 0),
others => zero32);
signal irq : std_ulogic;
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(10 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(10 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(10 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(10 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--edcl buf
signal erenable : std_ulogic;
signal eraddress : std_logic_vector(15 downto 0);
signal ewritem : std_ulogic;
signal ewritel : std_ulogic;
signal ewaddressm : std_logic_vector(15 downto 0);
signal ewaddressl : std_logic_vector(15 downto 0);
signal ewdata : std_logic_vector(31 downto 0);
signal erdata : std_logic_vector(31 downto 0);
signal lmdio_oe : std_ulogic;
-- Fix for wider bus
signal hwdata : std_logic_vector(31 downto 0);
signal hrdata : std_logic_vector(31 downto 0);
signal ehwdata : std_logic_vector(31 downto 0);
signal ehrdata : std_logic_vector(31 downto 0);
begin
ethc0: grethc
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
mdcscaler => mdcscaler,
enable_mdio => enable_mdio,
fifosize => fifosize,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
rmii => rmii,
oepol => oepol,
scanen => scanen,
mdint_pol => mdint_pol,
enable_mdint => enable_mdint,
multicast => multicast,
edclsepahbg => edclsepahb,
ramdebug => ramdebug,
mdiohold => mdiohold,
maxsize => maxsize,
gmiimode => gmiimode
)
port map(
rst => rst,
clk => clk,
--ahb mst in
hgrant => ahbmi.hgrant(hindex),
hready => ahbmi.hready,
hresp => ahbmi.hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => ahbmo.hbusreq,
hlock => ahbmo.hlock,
htrans => ahbmo.htrans,
haddr => ahbmo.haddr,
hwrite => ahbmo.hwrite,
hsize => ahbmo.hsize,
hburst => ahbmo.hburst,
hprot => ahbmo.hprot,
hwdata => hwdata,
--edcl ahb mst in
ehgrant => ahbmi2.hgrant(ehindex),
ehready => ahbmi2.hready,
ehresp => ahbmi2.hresp,
ehrdata => ehrdata,
--edcl ahb mst out
ehbusreq => ahbmo2.hbusreq,
ehlock => ahbmo2.hlock,
ehtrans => ahbmo2.htrans,
ehaddr => ahbmo2.haddr,
ehwrite => ahbmo2.hwrite,
ehsize => ahbmo2.hsize,
ehburst => ahbmo2.hburst,
ehprot => ahbmo2.hprot,
ehwdata => ehwdata,
--apb slv in
psel => apbi.psel(pindex),
penable => apbi.penable,
paddr => apbi.paddr,
pwrite => apbi.pwrite,
pwdata => apbi.pwdata,
--apb slv out
prdata => apbo.prdata,
--irq
irq => irq,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--edcl buf
erenable => erenable,
eraddress => eraddress,
ewritem => ewritem,
ewritel => ewritel,
ewaddressm => ewaddressm,
ewaddressl => ewaddressl,
ewdata => ewdata,
erdata => erdata,
--ethernet input signals
rmii_clk => ethi.rmii_clk,
tx_clk => ethi.tx_clk,
tx_dv => ethi.tx_dv,
rx_clk => ethi.rx_clk,
rxd => ethi.rxd(3 downto 0),
rx_dv => ethi.rx_dv,
rx_er => ethi.rx_er,
rx_col => ethi.rx_col,
rx_crs => ethi.rx_crs,
rx_en => ethi.rx_en,
mdio_i => ethi.mdio_i,
phyrstaddr => ethi.phyrstaddr,
mdint => ethi.mdint,
--ethernet output signals
reset => etho.reset,
txd => etho.txd(3 downto 0),
tx_en => etho.tx_en,
tx_er => etho.tx_er,
mdc => etho.mdc,
mdio_o => etho.mdio_o,
mdio_oe => lmdio_oe,
--scantest
testrst => ahbmi.testrst,
testen => ahbmi.testen,
testoen => ahbmi.testoen,
edcladdr => ethi.edcladdr,
edclsepahb => ethi.edclsepahb,
edcldisable => ethi.edcldisable);
etho.mdio_oe <= ahbmi.testoen when (scanen = 1) and (ahbmi.testen = '1')
else lmdio_oe;
irqdrv : process(irq)
begin
apbo.pirq <= (others => '0');
apbo.pirq(pirq) <= irq;
end process;
hrdata <= ahbreadword(ahbmi.hrdata);
ahbmo.hwdata <= ahbdrivedata(hwdata);
ahbmo.hconfig <= hconfig;
ahbmo.hindex <= hindex;
ahbmo.hirq <= (others => '0');
ehrdata <= ahbreadword(ahbmi2.hrdata);
ahbmo2.hwdata <= ahbdrivedata(ehwdata);
ahbmo2.hconfig <= ehconfig;
ahbmo2.hindex <= ehindex;
ahbmo2.hirq <= (others => '0');
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
-------------------------------------------------------------------------------
-- FIFOS ----------------------------------------------------------------------
-------------------------------------------------------------------------------
nft : if ft = 0 generate
tx_fifo0 : syncram_2p generic map(tech => memtech, abits => txfabits,
dbits => 32, sepclk => 0)
port map(clk, txrenable, txraddress(txfabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(txfabits-1 downto 0), txwdata);
rx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata);
end generate;
ft1 : if ft /= 0 generate
tx_fifo0 : syncram_2pft generic map(tech => memtech, abits => txfabits,
dbits => 32, sepclk => 0, ft => ft)
port map(clk, txrenable, txraddress(txfabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(txfabits-1 downto 0), txwdata);
rx_fifo0 : syncram_2pft generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0, ft => ft)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata);
end generate;
-------------------------------------------------------------------------------
-- EDCL buffer ram ------------------------------------------------------------
-------------------------------------------------------------------------------
edclramnft : if (edcl /= 0) and (edclft = 0) generate
r0 : syncram_2p generic map (memtech, eabits, 16) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16));
r1 : syncram_2p generic map (memtech, eabits, 16) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0));
end generate;
edclramft1 : if (edcl /= 0) and (edclft /= 0) generate
r0 : syncram_2p generic map (memtech, eabits, 16, 0, 0, ft) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16));
r1 : syncram_2p generic map (memtech, eabits, 16, 0, 0, ft) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0));
end generate;
-- pragma translate_off
bootmsg : report_version
generic map (
"greth" & tost(hindex) & ": 10/100 Mbit Ethernet MAC rev " & tost(REVISION)
& tost(hindex) & ", EDCL " & tost(edcl) & ", buffer " &
tost(edclbufsz) & " kbyte " & tost(txfifosize) & " txfifo," &
" irq " & tost(pirq)
);
-- pragma translate_on
end architecture;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/maps/syncram_2pbw.vhd | 1 | 9245 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncram_2pbw
-- File: syncram_2pbw.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: syncronous 2-port ram with tech selection and 8-bit write
-- strobes
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allmem.all;
library grlib;
use grlib.config.all;
use grlib.config_types.all;
use grlib.stdlib.all;
entity syncram_2pbw is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0; testen : integer := 0;
words : integer := 0; custombits : integer := 1);
port (
rclk : in std_ulogic;
renable : in std_logic_vector((dbits/8-1) downto 0);
raddress : in std_logic_vector((abits-1) downto 0);
dataout : out std_logic_vector((dbits-1) downto 0);
wclk : in std_ulogic;
write : in std_logic_vector((dbits/8-1) downto 0);
waddress : in std_logic_vector((abits-1) downto 0);
datain : in std_logic_vector((dbits-1) downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector((dbits/8)*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector((dbits/8)*custombits-1 downto 0));
end;
architecture rtl of syncram_2pbw is
constant nctrl : integer := abits*2 + 2 + 2*dbits/8;
signal dataoutx : std_logic_vector((dbits -1) downto 0);
signal databp, testdata : std_logic_vector((dbits -1) downto 0);
signal renable2 : std_logic_vector((dbits/8-1) downto 0);
constant SCANTESTBP : boolean := (testen = 1) and (tech /= 0) and (tech /= ut90);
constant iwrfst : integer := (1-syncram_2p_write_through(tech)) * wrfst;
signal xrenable,xwrite : std_logic_vector(dbits/8-1 downto 0);
signal custominx,customoutx: std_logic_vector(syncram_customif_maxwidth downto 0);
begin
xrenable <= renable when testen=0 or testin(TESTIN_WIDTH-2)='0' else (others => '0');
xwrite <= write when testen=0 or testin(TESTIN_WIDTH-2)='0' else (others => '0');
s2pbw : if has_sram_2pbw(tech) = 1 generate
no_wrfst : if iwrfst = 0 generate
scanbp : if SCANTESTBP generate
comb : process (waddress, raddress, datain, renable, write, testin)
variable tmp : std_logic_vector((dbits -1) downto 0);
variable ctrlsigs : std_logic_vector((nctrl -1) downto 0);
begin
ctrlsigs := testin(1 downto 0) & write & renable & raddress & waddress;
tmp := datain;
for i in 0 to nctrl-1 loop
tmp(i mod dbits) := tmp(i mod dbits) xor ctrlsigs(i);
end loop;
testdata <= tmp;
end process;
reg : process(wclk) begin
if rising_edge(wclk) then databp <= testdata; end if;
end process;
dmuxout : for i in 0 to dbits-1 generate
x0 : grmux2 generic map (tech)
port map (dataoutx(i), databp(i), testin(3), dataout(i));
end generate;
end generate;
noscanbp : if not SCANTESTBP generate dataout <= dataoutx; end generate;
-- Write contention check (if applicable)
wcheck : for i in 0 to dbits/8-1 generate
renable2(i) <= '0' when ((sepclk = 0 and syncram_2p_dest_rw_collision(tech) = 1) and
(renable(i) and write(i)) = '1' and raddress = waddress) else renable(i);
end generate;
end generate;
wrfst_gen : if iwrfst = 1 generate
-- No risk for read/write contention. Register addresses and mux on comparator
no_contention_check : if syncram_2p_dest_rw_collision(tech) = 0 generate
wfrstblocknoc : block
type wrfst_type is record
raddr : std_logic_vector((abits-1) downto 0);
waddr : std_logic_vector((abits-1) downto 0);
datain : std_logic_vector((dbits-1) downto 0);
write : std_logic_vector((dbits/8-1) downto 0);
renable : std_logic_vector((dbits/8-1) downto 0);
end record;
signal r : wrfst_type;
begin
comb : process(r, dataoutx, testin) begin
for i in 0 to dbits/8-1 loop
if (SCANTESTBP and (testin(3) = '1')) or
(((r.write(i) and r.renable(i)) = '1') and (r.raddr = r.waddr)) then
dataout(i*8+7 downto i*8) <= r.datain(i*8+7 downto i*8);
else dataout(i*8+7 downto i*8) <= dataoutx(i*8+7 downto i*8); end if;
end loop;
end process;
reg : process(wclk) begin
if rising_edge(wclk) then
r.raddr <= raddress; r.waddr <= waddress;
r.datain <= datain; r.write <= write;
r.renable <= renable;
end if;
end process;
end block wfrstblocknoc;
renable2 <= renable;
end generate;
-- Risk of read/write contention. Use same comparator to gate read enable
-- and mux data.
contention_safe : if syncram_2p_dest_rw_collision(tech) /= 0 generate
wfrstblockc : block
signal col, mux : std_logic_vector((dbits/8-1) downto 0);
signal rdatain : std_logic_vector((dbits-1) downto 0);
begin
comb : process(mux, renable, write, raddress, waddress, rdatain,
dataoutx, testin)
begin
for i in 0 to dbits/8-1 loop
col(i) <= '0'; renable2(i) <= renable(i);
if (write(i) and renable(i)) = '1' and raddress = waddress then
col(i) <= '1'; renable2(i) <= '0';
end if;
if (SCANTESTBP and (testin(3) = '1')) or mux(i) = '1' then
dataout(i*8+7 downto i*8) <= rdatain(i*8+7 downto i*8);
else dataout(i*8+7 downto i*8) <= dataoutx(i*8+7 downto i*8); end if;
end loop;
end process;
reg : process(wclk) begin
if rising_edge(wclk) then
rdatain <= datain; mux <= col;
end if;
end process;
end block wfrstblockc;
end generate;
end generate wrfst_gen;
custominx(custominx'high downto custombits) <= (others => '0');
custominx(custombits-1 downto 0) <= customin;
nocust: if has_sram_2pbw(tech)=0 or syncram_has_customif(tech)=0 generate
customoutx <= (others => '0');
end generate;
co0: if has_sram_2pbw(tech)=1 generate
customout(custombits-1 downto 0) <= customoutx(custombits-1 downto 0);
customout(customout'high downto custombits) <= (others => '0');
end generate;
n2x : if tech = easic45 generate
x0 : n2x_syncram_2p_be generic map (abits, dbits, sepclk, iwrfst)
port map (rclk, renable2, raddress, dataoutx, wclk,
write, waddress, datain);
end generate;
-- pragma translate_off
noram : if has_2pram(tech) = 0 generate
x : process
begin
assert false report "synram_2pbw: technology " & tech_table(tech) &
" not supported"
severity failure;
wait;
end process;
end generate;
dmsg : if GRLIB_CONFIG_ARRAY(grlib_debug_level) >= 2 generate
x : process
begin
assert false report "syncram_2pbw: " & tost(2**abits) & "x" & tost(dbits) &
" (" & tech_table(tech) & ")"
severity note;
wait;
end process;
end generate;
generic_check : process
begin
assert sepclk = 0 or wrfst = 0
report "syncram_2pbw: Write-first not supported for RAM with separate clocks"
severity failure;
wait;
end process;
-- pragma translate_on
end generate;
nos2pbw : if has_sram_2pbw(tech) /= 1 generate
rx : for i in 0 to dbits/8-1 generate
x0 : syncram_2p generic map (tech, abits, 8, sepclk, wrfst, testen, words, custombits)
port map (rclk, renable(i), raddress, dataout(i*8+7 downto i*8), wclk, write(i),
waddress, datain(i*8+7 downto i*8), testin,
customclk, customin((i+1)*custombits-1 downto i*custombits),
customout((i+1)*custombits-1 downto i*custombits));
end generate;
end generate;
end;
| gpl-2.0 |
a4a881d4/ringbus4xilinx | src/cbus/CMaster.vhd | 2 | 7611 | ---------------------------------------------------------------------------------------------------
--
-- Title : Control Bus Master
-- Design : Ring Bus
-- Author : Zhao Ming
-- Company : a4a881d4
--
---------------------------------------------------------------------------------------------------
--
-- File : CMaster.vhd
-- Generated : 2013/9/13
-- From :
-- By :
--
---------------------------------------------------------------------------------------------------
--
-- Description : Control bus master
--
-- Rev: 3.1
--
---------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library work;
use work.rb_config.all;
use work.contr_config.all;
entity CMaster is
generic(
Bwidth : natural := 16;
POS : natural := 0;
MyBusID : natural := 0
);
port(
-- system
clk : in STD_LOGIC;
rst : in STD_LOGIC;
-- send to bus
tx: out std_logic_vector(Bwidth-1 downto 0);
Req : out std_logic;
tx_sop : in std_logic;
en : in std_logic;
-- read from bus
rx_sop : in std_logic;
rx: in std_logic_vector(Bwidth-1 downto 0);
-- Local Bus
CS : in std_logic;
addr : in std_logic_vector(3 downto 0);
Din : in STD_LOGIC_VECTOR(7 downto 0);
Dout : out STD_LOGIC_VECTOR(7 downto 0);
cpuClk : in std_logic;
wr : in std_logic;
rd : in std_logic
--
);
end CMaster;
architecture behave of CMaster is
signal addr_cpu : std_logic_vector( Bwidth-1 downto 0 ) := (others=>'0');
signal word3_cpu : std_logic_vector( Bwidth-1 downto 0 ) := (others=>'0');
signal cs_wr : std_logic := '0';
signal inCommand : std_logic_vector( command_end downto command_start ) := (others => '0');
signal inDBUSID : std_logic_vector( dbusid_end downto dbusid_start ) := (others => '0');
signal inAddr : std_logic_vector( daddr_end downto daddr_start ) := (others => '0');
signal inTag, returnTag, rdTag : std_logic_vector( len_length-1 downto 0 ) := ( others=>'0' );
signal TagState : std_logic_vector( 2**len_length-1 downto 0 ) := ( others=>'0' );
signal req_cpu : std_logic := '0';
signal tstate,rstate : natural := 0;
signal busy_i : std_logic := '0';
signal tagen : std_logic := '0';
signal TagData : std_logic_vector( Bwidth-1 downto 0 ) := (others=>'0');
component AAI
generic(
width : natural := 32;
Baddr : std_logic_vector( 3 downto 0 ) := "0000"
);
port(
-- system signal
rst : in STD_LOGIC;
-- CPU bus
CS : in std_logic;
addr : in std_logic_vector( 3 downto 0 );
Din : in std_logic_vector( 7 downto 0 );
cpuClk : in std_logic;
Q : out std_logic_vector( width-1 downto 0 )
);
end component;
component blockdram
generic(
depth: integer := 256;
Dwidth: integer := 8;
Awidth: integer := 8
);
port(
addra: IN std_logic_VECTOR(Awidth-1 downto 0);
clka: IN std_logic;
addrb: IN std_logic_VECTOR(Awidth-1 downto 0);
clkb: IN std_logic;
dia: IN std_logic_VECTOR(Dwidth-1 downto 0);
wea: IN std_logic;
reb: IN std_logic;
dob: OUT std_logic_VECTOR(Dwidth-1 downto 0) := (others => '0')
);
end component;
begin
cs_wr <= cs and wr;
ADDR_AAI:AAI
generic map(
width => Bwidth,
Baddr => reg_Control_ADDR
)
port map(
rst => rst,
CS => cs_wr,
addr => addr,
Din => Din,
cpuClk => cpuClk,
Q => addr_cpu
);
DATA_AAI:AAI
generic map(
width => Bwidth,
Baddr => reg_Control_DATA
)
port map(
rst => rst,
CS => cs_wr,
addr => addr,
Din => Din,
cpuClk => cpuClk,
Q => word3_cpu
);
tagmem:blockdram
generic map(
depth => 2**len_length,
Dwidth => Bwidth,
Awidth => len_length
)
port map(
addra => returnTag,
clka => clk,
addrb => rdTag,
clkb => clk,
dia => rx,
wea => tagen,
reb => '1',
dob => TagData
);
cpuwriteP:process( cpuClk, rst, tstate )
begin
if rst='1' then
inAddr<=( others=>'0' );
inDBUSID<=( others=>'0' );
inCommand<=( others=>'0' );
inTag<=( others=>'0' );
rdTag<=( others=>'0' );
elsif rising_edge(cpuClk) then
if cs_wr='1' then
case addr is
when reg_Control_BADDR =>
inAddr<=Din( addr_length-1 downto 0 );
when reg_Control_BID =>
inDBUSID<=Din( busid_length-1 downto 0 );
when reg_Control_Tag =>
inTag<=Din( len_length-1 downto 0 );
when reg_Control_rdTag =>
rdTag<=Din( len_length-1 downto 0 );
when reg_Control_Command =>
inCommand<=Din( command_length-1 downto 0 );
when others =>
null;
end case;
end if;
end if;
if tstate=state_loading then
req_cpu<='0';
elsif rising_edge(cpuClk) then
if cs_wr='1' and addr=reg_Control_START then
req_cpu<='1';
end if;
end if;
end process;
TagStateP:process(clk,rst)
begin
if rst='1' then
TagState<=( others=>'0' );
elsif rising_edge(clk) then
if tstate=state_ADDR and inCommand=command_read then
TagState(conv_integer(inTag))<='1';
end if;
if tagen='1' then
TagState(conv_integer(returnTag))<='0';
end if;
end if;
end process;
FSMT:process(clk,rst)
begin
if rst='1' then
tstate<=state_IDLE;
req<='0';
busy_i<='0';
tx <= zeros( Bwidth-1 downto 0 );
elsif rising_edge(clk) then
case tstate is
when state_IDLE =>
if req_cpu='1' then
tstate<=state_LOADING;
busy_i<='1';
else
busy_i<='0';
end if;
req<='0';
when state_LOADING =>
tx( command_end downto command_start )<=inCommand;
tx( dbusid_end downto dbusid_start )<=inDBUSID;
tx( daddr_end downto daddr_start )<=inAddr;
tx( len_end downto len_start ) <= zeros(len_end downto len_start)+2;
req<='1';
tstate<=state_SENDING;
when state_SENDING =>
if en='1' and tx_sop='1' then
tx<=addr_cpu;
tstate<=state_ADDR;
req<='0';
end if;
when state_ADDR =>
if inCommand=command_write then
tx<=word3_cpu;
else
tx( command_end downto command_start )<=command_complete;
tx( dbusid_end downto dbusid_start )<=zeros( dbusid_end downto dbusid_start )+MyBusID;
tx( daddr_end downto daddr_start )<=zeros( daddr_end downto daddr_start )+POS;
tx( len_end downto len_start )<=inTag;
end if;
tstate<=state_IDLE;
busy_i<='0';
when others =>
req<='0';
tstate<=state_IDLE;
end case;
end if;
end process;
FSMR:process(clk,rst)
begin
if rst='1' then
rstate<=state_IDLE;
returnTag<=( others=>'0' );
tagen<='0';
elsif rising_edge(clk) then
case rstate is
when state_IDLE =>
if rx_sop='1' and rx( command_end downto command_start )=command_complete then
rstate<=state_ADDR;
tagen<='0';
end if;
tagen<='0';
when state_ADDR =>
returnTag<=rx( len_end downto len_start );
tagen<='1';
rstate<=state_IDLE;
when others =>
rstate<=state_IDLE;
end case;
end if;
end process;
rdP:process(rd,addr,cs,rdTag)
begin
if rd='1' and cs='1' then
case addr is
when reg_Control_Busy =>
Dout(0)<=busy_i;
Dout( 7 downto 1 )<=(others=>'Z');
when reg_Control_TagState =>
Dout(0)<=TagState(conv_integer(rdTag));
Dout( 7 downto 1 )<=(others=>'Z');
when reg_Control_TagData =>
Dout<=TagData( 7 downto 0 );
when others =>
Dout<=(others=>'Z');
end case;
end if;
end process;
end behave;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/srmmu/mmulrue.vhd | 1 | 3267 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmulrue
-- File: mmulrue.vhd
-- Author: Konrad Eisele, Jiri Gaisler, Gaisler Research
-- Description: MMU LRU logic
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
entity mmulrue is
generic (
position : integer;
entries : integer := 8 );
port (
rst : in std_logic;
clk : in std_logic;
lruei : in mmulrue_in_type;
lrueo : out mmulrue_out_type );
end mmulrue;
architecture rtl of mmulrue is
constant entries_log : integer := log2(entries);
type lru_rtype is record
pos : std_logic_vector(entries_log-1 downto 0);
movetop : std_logic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
signal c,r : lru_rtype;
begin
p0: process (rst, r, lruei)
variable v : lru_rtype;
variable ov : mmulrue_out_type;
begin
v := r; ov := mmulrue_out_none;
-- #init
if (r.movetop) = '1' then
if (lruei.fromleft) = '0' then
v.pos := lruei.left(entries_log-1 downto 0);
v.movetop := '0';
end if;
elsif (lruei.fromright) = '1' then
v.pos := lruei.right(entries_log-1 downto 0);
v.movetop := not lruei.clear;
end if;
if (lruei.touch and not lruei.clear) = '1' then -- touch request
if (v.pos = lruei.pos(entries_log-1 downto 0)) then -- check
v.movetop := '1';
end if;
end if;
if ((not RESET_ALL) and (rst = '0')) or (lruei.flush = '1') then
v.pos := conv_std_logic_vector(position, entries_log);
v.movetop := '0';
end if;
--# Drive signals
ov.pos(entries_log-1 downto 0) := r.pos;
ov.movetop := r.movetop;
lrueo <= ov;
c <= v;
end process p0;
p1: process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and (rst = '0') then
r.pos <= conv_std_logic_vector(position, entries_log);
r.movetop <= '0';
end if;
end if;
end process p1;
end rtl;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-arrow-bemicro-sdk/testbench.vhd | 1 | 7265 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- LEON3 BeMicro SDK design testbench
-- Copyright (C) 2011 - 2013 Aeroflex Gaisler
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20 -- system clock period
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant ct : integer := clkperiod/2;
signal cpu_rst_n : std_ulogic := '0';
signal clk_fpga_50m : std_ulogic := '0';
-- DDR SDRAM
signal ram_a : std_logic_vector (13 downto 0); -- ddr address
signal ram_ck_p : std_logic;
signal ram_ck_n : std_logic;
signal ram_cke : std_logic;
signal ram_cs_n : std_logic;
signal ram_ws_n : std_ulogic; -- ddr write enable
signal ram_ras_n : std_ulogic; -- ddr ras
signal ram_cas_n : std_ulogic; -- ddr cas
signal ram_dm : std_logic_vector(1 downto 0); -- ram_udm & ram_ldm
signal ram_dqs : std_logic_vector (1 downto 0); -- ram_udqs & ram_lqds
signal ram_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ram_d : std_logic_vector (15 downto 0); -- ddr data
-- Ethernet PHY
signal txd : std_logic_vector(3 downto 0);
signal rxd : std_logic_vector(3 downto 0);
signal tx_clk : std_logic;
signal rx_clk : std_logic;
signal tx_en : std_logic;
signal rx_dv : std_logic;
signal eth_crs : std_logic;
signal rx_er : std_logic;
signal eth_col : std_logic;
signal mdio : std_logic;
signal mdc : std_logic;
signal eth_reset_n : std_logic;
-- Temperature sensor
signal temp_sc : std_logic;
signal temp_cs_n : std_logic;
signal temp_sio : std_logic;
-- LEDs
signal f_led : std_logic_vector(7 downto 0);
-- User push-button
signal pbsw_n : std_logic;
-- Reconfig SW1 and SW2
signal reconfig_sw : std_logic_vector(2 downto 1);
-- SD card interface
signal sd_dat0 : std_logic;
signal sd_dat1 : std_logic;
signal sd_dat2 : std_logic;
signal sd_dat3 : std_logic;
signal sd_cmd : std_logic;
signal sd_clk : std_logic;
-- Ethernet PHY sim model
signal phy_tx_er : std_ulogic;
signal phy_gtx_clk : std_ulogic;
signal txdt : std_logic_vector(7 downto 0) := (others => '0');
signal rxdt : std_logic_vector(7 downto 0) := (others => '0');
-- EPCS
signal epcs_data : std_ulogic;
signal epcs_dclk : std_ulogic;
signal epcs_csn : std_logic;
signal epcs_asdi : std_logic;
begin
-- clock and reset
clk_fpga_50m <= not clk_fpga_50m after ct * 1 ns;
cpu_rst_n <= '0', '1' after 200 ns;
-- Push button, connected to DSU break, kept high
pbsw_n <= 'H';
reconfig_sw <= (others => 'H');
-- LEON3 SoC
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech, ncpu, disas, dbguart, pclow)
port map (
cpu_rst_n, clk_fpga_50m,
-- DDR SDRAM
ram_a, ram_ck_p, ram_ck_n, ram_cke, ram_cs_n, ram_ws_n,
ram_ras_n, ram_cas_n, ram_dm, ram_dqs, ram_ba, ram_d,
-- Ethernet PHY
txd, rxd, tx_clk, rx_clk, tx_en, rx_dv, eth_crs, rx_er,
eth_col, mdio, mdc, eth_reset_n,
-- Temperature sensor
temp_sc, temp_cs_n, temp_sio,
-- LEDs
f_led,
-- User push-button
pbsw_n,
-- Reconfig SW1 and SW2
reconfig_sw,
-- SD card interface
sd_dat0, sd_dat1, sd_dat2, sd_dat3, sd_cmd, sd_clk,
-- EPCS
epcs_data, epcs_dclk, epcs_csn, epcs_asdi
);
-- SD card signals
spiflashmod0 : spi_flash
generic map (ftype => 3, debug => 0, dummybyte => 0)
port map (sck => sd_clk, di => sd_cmd, do => sd_dat0, csn => sd_dat3);
sd_dat0 <= 'Z'; sd_cmd <= 'Z';
-- EPCS
spi0: spi_flash
generic map (
ftype => 4, debug => 0, fname => promfile, readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE, dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
memoffset => CFG_SPIMCTRL_OFFSET)
port map (sck => epcs_dclk, di => epcs_asdi, do => epcs_data,
csn => epcs_csn, sd_cmd_timeout => open,
sd_data_timeout => open);
-- On the BeMicro the temp_* signals are connected to a temperature sensor
temp_sc <= 'H'; temp_sio <= 'H';
-- DDR memory
ddr0 : ddrram
generic map(width => 16, abits => 14, colbits => 10, rowbits => 13,
implbanks => 1, fname => sdramfile, density => 2)
port map (ck => ram_ck_p, cke => ram_cke, csn => ram_cs_n,
rasn => ram_ras_n, casn => ram_cas_n, wen => ram_ws_n,
dm => ram_dm, ba => ram_ba, a => ram_a, dq => ram_d,
dqs => ram_dqs);
-- Ethernet PHY
mdio <= 'H'; phy_tx_er <= '0'; phy_gtx_clk <= '0';
txdt(3 downto 0) <= txd; rxd <= rxdt(3 downto 0);
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0, address => 1)
port map(eth_reset_n, mdio, tx_clk, rx_clk, rxdt, rx_dv,
rx_er, eth_col, eth_crs, txdt, tx_en, phy_tx_er, mdc,
phy_gtx_clk);
-- LEDs
f_led <= (others => 'H');
-- Processor error mode indicator is connected to led(6).
iuerr : process
begin
wait for 2500 ns;
if to_x01(f_led(6)) = '1' then wait on f_led(6); end if;
assert (to_x01(f_led(6)) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
end ;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/gr1553b/gr1553b.in.vhd | 4 | 304 | -- MIL-STD-1553 controllers
constant CFG_GR1553B_ENABLE : integer := CONFIG_GR1553B_ENABLE;
constant CFG_GR1553B_RTEN : integer := CONFIG_GR1553B_RTEN;
constant CFG_GR1553B_BCEN : integer := CONFIG_GR1553B_BCEN;
constant CFG_GR1553B_BMEN : integer := CONFIG_GR1553B_BMEN;
| gpl-2.0 |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-sp601/config.vhd | 1 | 7724 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan6;
constant CFG_MEMTECH : integer := spartan6;
constant CFG_PADTECH : integer := spartan6;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan6;
constant CFG_CLKMUL : integer := (18);
constant CFG_CLKDIV : integer := (9);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 0;
constant CFG_DDR2SP_INIT : integer := 0;
constant CFG_DDR2SP_FREQ : integer := 100;
constant CFG_DDR2SP_TRFC : integer := 130;
constant CFG_DDR2SP_DATAWIDTH : integer := 64;
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := 9;
constant CFG_DDR2SP_SIZE : integer := 8;
constant CFG_DDR2SP_DELAY0 : integer := 0;
constant CFG_DDR2SP_DELAY1 : integer := 0;
constant CFG_DDR2SP_DELAY2 : integer := 0;
constant CFG_DDR2SP_DELAY3 : integer := 0;
constant CFG_DDR2SP_DELAY4 : integer := 0;
constant CFG_DDR2SP_DELAY5 : integer := 0;
constant CFG_DDR2SP_DELAY6 : integer := 0;
constant CFG_DDR2SP_DELAY7 : integer := 0;
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_RANKS : integer := (1);
constant CFG_MIG_COLBITS : integer := (10);
constant CFG_MIG_ROWBITS : integer := (13);
constant CFG_MIG_BANKBITS: integer := (2);
constant CFG_MIG_HMASK : integer := 16#F00#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 0;
constant CFG_SPICTRL_NUM : integer := 1;
constant CFG_SPICTRL_SLVS : integer := 1;
constant CFG_SPICTRL_FIFO : integer := 1;
constant CFG_SPICTRL_SLVREG : integer := 0;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := 0;
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 |
keith-epidev/VHDL-lib | src/components/full_adder/full_adder.vhd | 1 | 489 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.VHDL_lib.all;
entity FULL_ADDER is
port (
A,B,CIN : in std_logic;
SUM,CARRY : out std_logic
);
end FULL_ADDER;
architecture arch of FULL_ADDER is
signal I1, I2, I3 : std_logic;
signal concat: std_logic_vector(1 downto 0);
begin
concat <= I3&I2;
u1:HALF_ADDER port map(A,B,I1,I2);
u2:HALF_ADDER port map(I1,CIN,SUM,I3);
u3:OR_GATE generic map(width=>2) port map(concat,CARRY);
end arch;
| gpl-2.0 |
keith-epidev/VHDL-lib | top/mono_radio/ip/xfft/floating_point_v7_0/hdl/shared/delay.vhd | 3 | 11968 | `protect begin_protected
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/mono_radio/ip/xfft/xfft_v9_0/hdl/xfft_v9_0_fp.vhd | 3 | 84613 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 60896)
`protect data_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/dds/xbip_dsp48_addsub_v3_0/hdl/xbip_dsp48_addsub_v3_0_pkg.vhd | 8 | 27921 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 18928)
`protect data_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/stereo_radio/ip/dds/dds_compiler_v6_0/hdl/pkg_dds_compiler_v6_0.vhd | 4 | 179717 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 131296)
`protect data_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/lab_7/part_3/ip/dds/axi_utils_v2_0/hdl/glb_ifx_slave.vhd | 15 | 13849 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8512)
`protect data_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/lab_7/part_3/ip/bram/blk_mem_gen_v8_2/simulation/blk_mem_gen_v8_2.vhd | 7 | 291006 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 213680)
`protect data_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/mono_radio/ip/xfft/xfft_v9_0/hdl/in_ranger.vhd | 3 | 8358 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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lqXmfdZ6gREz3Hp1DVpl+3lFR4KBTeTB3MS7Kw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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HZGoKDMHBZrdCAJbF/k=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4448)
`protect data_block
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GxU=
`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/lab_4/part_1/ip/fft/xfft_v9_0/hdl/r4_control.vhd | 2 | 63948 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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yHYuCh49PA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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6IbW2D86QlmqClDHaw4=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 45600)
`protect data_block
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`protect end_protected
| gpl-2.0 |
keith-epidev/VHDL-lib | top/mono_radio/ip/xfft/xfft_v9_0/hdl/r22_cnt_ctrl.vhd | 3 | 13545 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8288)
`protect data_block
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`protect end_protected
| gpl-2.0 |
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