repo_name
stringlengths 6
79
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stringlengths 5
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stringclasses 54
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stringlengths 1
8
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stringlengths 0
1.04M
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tjyrz/vhdl_fft
|
spi_mux.vhd
|
3
|
717
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity spi_mux is
port(
sck_a_o: out std_logic;
sck_b_o: out std_logic;
sck_i: in std_logic;
conv_a_o: out std_logic;
conv_b_o: out std_logic;
conv_i: in std_logic;
miso_a_i: in std_logic;
miso_b_i: in std_logic;
miso_o: out std_logic;
sel_i: in std_logic
);
end spi_mux;
architecture Behavioral of spi_mux is
begin
sck_a_o <= sck_i when sel_i = '0' else 'Z';
sck_b_o <= sck_i when sel_i = '1' else 'Z';
conv_a_o <= conv_i when sel_i = '0' else 'Z';
conv_b_o <= conv_i when sel_i = '1' else 'Z';
miso_o <= miso_a_i when sel_i = '0' else miso_b_i;
end Behavioral;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/fp_ln1px_s5.vhd
|
10
|
473588
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_ln1px_s5
-- VHDL created on Mon Mar 11 11:48:38 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
-- Text written from /data/tczajkow/polyeval/p4/ip/aion/src/mip_common/hw_model.cpp:1303
entity fp_ln1px_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_ln1px_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllZWF_uid8_fpLogE1pxTest_q : std_logic_vector (22 downto 0);
signal cstBias_uid9_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal cstBiasMO_uid10_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal cstBiasPWFP1_uid13_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal cstBiasMWFP1_uid14_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal cstAllOWE_uid15_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal cstAllZWE_uid17_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal padConst_uid36_fpLogE1pxTest_q : std_logic_vector (23 downto 0);
signal maskIncrementTable_uid52_fpLogE1pxTest_q : std_logic_vector(23 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_a : std_logic_vector(8 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_b : std_logic_vector(8 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_o : std_logic_vector (8 downto 0);
signal eUpdateOPOFracX_uid55_fpLogE1pxTest_q : std_logic_vector (8 downto 0);
signal oPlusOFracXNorm_uid61_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal oPlusOFracXNorm_uid61_fpLogE1pxTest_q : std_logic_vector (23 downto 0);
signal branEnc_uid77_fpLogE1pxTest_q : std_logic_vector(1 downto 0);
signal expB_uid79_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal expB_uid79_fpLogE1pxTest_q : std_logic_vector (8 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch3OrC_uid94_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal o2_uid97_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal z2_uid100_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal sEz_uid102_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal sEz_uid102_fpLogE1pxTest_q : std_logic_vector (24 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_a : std_logic_vector (24 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_b : std_logic_vector (26 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_s1 : std_logic_vector (51 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_pr : SIGNED (51 downto 0);
signal postPEMul_uid103_fpLogE1pxTest_q : std_logic_vector (51 downto 0);
signal wideZero_uid104_fpLogE1pxTest_q : std_logic_vector (34 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_a : std_logic_vector(57 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_b : std_logic_vector(57 downto 0);
signal finalSumOneComp_uid112_fpLogE1pxTest_q : std_logic_vector(57 downto 0);
signal cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q : std_logic_vector (8 downto 0);
signal expRExt_uid121_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal expRExt_uid121_fpLogE1pxTest_q : std_logic_vector (9 downto 0);
signal fracR_uid126_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal fracR_uid126_fpLogE1pxTest_q : std_logic_vector (22 downto 0);
signal expR_uid128_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal expR_uid128_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal InvExcRNaN_uid141_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid141_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid144_fpLogE1pxTest_q : std_logic_vector(1 downto 0);
signal oneFracRPostExc2_uid145_fpLogE1pxTest_q : std_logic_vector (22 downto 0);
signal rightShiftStage0Idx2Pad16_uid160_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage1Idx2Pad4_uid171_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal rightShiftStage1Idx3Pad6_uid174_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (5 downto 0);
signal mO_uid187_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vCount_uid194_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(7 downto 0);
signal vCount_uid194_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(7 downto 0);
signal vCount_uid194_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(1 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(1 downto 0);
signal vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal p1_uid246_constMult_q : std_logic_vector(36 downto 0);
signal zs_uid267_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal mO_uid270_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (4 downto 0);
signal vCount_uid283_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(7 downto 0);
signal vCount_uid283_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(7 downto 0);
signal vCount_uid283_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid295_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(1 downto 0);
signal vCount_uid295_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(1 downto 0);
signal vCount_uid295_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad48_uid311_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal leftShiftStage1Idx3Pad12_uid322_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage2Idx3Pad3_uid333_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (2 downto 0);
signal prodXY_uid339_pT1_uid255_natLogPolyEval_a : std_logic_vector (12 downto 0);
signal prodXY_uid339_pT1_uid255_natLogPolyEval_b : std_logic_vector (12 downto 0);
signal prodXY_uid339_pT1_uid255_natLogPolyEval_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid339_pT1_uid255_natLogPolyEval_pr : SIGNED (26 downto 0);
signal prodXY_uid339_pT1_uid255_natLogPolyEval_q : std_logic_vector (25 downto 0);
signal prodXY_uid342_pT2_uid261_natLogPolyEval_a : std_logic_vector (15 downto 0);
signal prodXY_uid342_pT2_uid261_natLogPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid342_pT2_uid261_natLogPolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid342_pT2_uid261_natLogPolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid342_pT2_uid261_natLogPolyEval_q : std_logic_vector (38 downto 0);
signal memoryC0_uid251_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid251_natLogTabGen_lutmem_ia : std_logic_vector (30 downto 0);
signal memoryC0_uid251_natLogTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC0_uid251_natLogTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC0_uid251_natLogTabGen_lutmem_iq : std_logic_vector (30 downto 0);
signal memoryC0_uid251_natLogTabGen_lutmem_q : std_logic_vector (30 downto 0);
signal memoryC1_uid252_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid252_natLogTabGen_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid252_natLogTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC1_uid252_natLogTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC1_uid252_natLogTabGen_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid252_natLogTabGen_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid253_natLogTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid253_natLogTabGen_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid253_natLogTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC2_uid253_natLogTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC2_uid253_natLogTabGen_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid253_natLogTabGen_lutmem_q : std_logic_vector (12 downto 0);
signal reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_q : std_logic_vector (2 downto 0);
signal reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q : std_logic_vector (3 downto 0);
signal reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q : std_logic_vector (4 downto 0);
signal reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel4Dto3_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q : std_logic_vector (47 downto 0);
signal reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q : std_logic_vector (47 downto 0);
signal reg_rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q : std_logic_vector (47 downto 0);
signal reg_rVStage_uid185_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_1_q : std_logic_vector (15 downto 0);
signal reg_cStage_uid189_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid193_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel2Dto1_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q : std_logic_vector (46 downto 0);
signal reg_leftShiftStage1Idx1_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q : std_logic_vector (46 downto 0);
signal reg_leftShiftStage1Idx2_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q : std_logic_vector (46 downto 0);
signal reg_leftShiftStage1Idx3_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q : std_logic_vector (46 downto 0);
signal reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q : std_logic_vector (23 downto 0);
signal reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q : std_logic_vector (23 downto 0);
signal reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q : std_logic_vector (23 downto 0);
signal reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_addr_uid90_fpLogE1pxTest_0_to_memoryC2_uid253_natLogTabGen_lutmem_0_q : std_logic_vector (8 downto 0);
signal reg_yT1_uid254_natLogPolyEval_0_to_prodXY_uid339_pT1_uid255_natLogPolyEval_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid253_natLogTabGen_lutmem_0_to_prodXY_uid339_pT1_uid255_natLogPolyEval_1_q : std_logic_vector (12 downto 0);
signal reg_memoryC1_uid252_natLogTabGen_lutmem_0_to_sumAHighB_uid258_natLogPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid256_uid259_natLogPolyEval_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_memoryC0_uid251_natLogTabGen_lutmem_0_to_sumAHighB_uid264_natLogPolyEval_0_q : std_logic_vector (30 downto 0);
signal reg_peOR_uid93_fpLogE1pxTest_0_to_postPEMul_uid103_fpLogE1pxTest_1_q : std_logic_vector (26 downto 0);
signal reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q : std_logic_vector (7 downto 0);
signal reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_1_q : std_logic_vector (0 downto 0);
signal reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q : std_logic_vector (7 downto 0);
signal reg_xv1_uid245_constMult_0_to_p1_uid246_constMult_0_q : std_logic_vector (2 downto 0);
signal reg_xv0_uid244_constMult_0_to_p0_uid247_constMult_0_q : std_logic_vector (5 downto 0);
signal reg_sR_uid249_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid268_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid269_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid276_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid277_countZ_uid114_fpLogE1pxTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid278_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid280_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid282_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid286_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid284_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid286_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid294_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid298_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid296_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid298_countZ_uid114_fpLogE1pxTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid289_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid277_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid269_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_5_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid325_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (58 downto 0);
signal reg_leftShiftStage1Idx1_uid318_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_3_q : std_logic_vector (58 downto 0);
signal reg_leftShiftStage1Idx2_uid321_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_4_q : std_logic_vector (58 downto 0);
signal reg_leftShiftStage1Idx3_uid324_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_5_q : std_logic_vector (58 downto 0);
signal reg_leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_2_q : std_logic_vector (58 downto 0);
signal reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q : std_logic_vector (4 downto 0);
signal reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q : std_logic_vector (9 downto 0);
signal reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q : std_logic_vector (33 downto 0);
signal ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q : std_logic_vector (31 downto 0);
signal ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_q : std_logic_vector (48 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_a_q : std_logic_vector (7 downto 0);
signal ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_q : std_logic_vector (3 downto 0);
signal ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_q : std_logic_vector (8 downto 0);
signal ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_q : std_logic_vector (23 downto 0);
signal ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_FullSumAB57_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q : std_logic_vector (9 downto 0);
signal ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q : std_logic_vector (0 downto 0);
signal ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_RightShiftStage047dto2_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (45 downto 0);
signal ld_RightShiftStage047dto4_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (43 downto 0);
signal ld_RightShiftStage047dto6_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q : std_logic_vector (41 downto 0);
signal ld_reg_rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_b_q : std_logic_vector (1 downto 0);
signal ld_rightShiftStageSel0Dto0_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid194_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_d_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel0Dto0_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2_uid242_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_xv0_uid244_constMult_0_to_p0_uid247_constMult_0_q_to_p0_uid247_constMult_a_q : std_logic_vector (5 downto 0);
signal ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid272_countZ_uid114_fpLogE1pxTest_b_q : std_logic_vector (26 downto 0);
signal ld_rVStage_uid268_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid274_countZ_uid114_fpLogE1pxTest_c_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid283_countZ_uid114_fpLogE1pxTest_q_to_r_uid302_countZ_uid114_fpLogE1pxTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid269_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_5_q_to_r_uid302_countZ_uid114_fpLogE1pxTest_f_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage157dto0_uid328_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid329_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (57 downto 0);
signal ld_LeftShiftStage156dto0_uid331_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid332_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (56 downto 0);
signal ld_LeftShiftStage155dto0_uid334_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid335_normVal_uid115_fpLogE1pxTest_b_q : std_logic_vector (55 downto 0);
signal ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC1_uid252_natLogTabGen_lutmem_0_q_to_memoryC1_uid252_natLogTabGen_lutmem_a_q : std_logic_vector (8 downto 0);
signal ld_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_q_to_reg_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid277_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid277_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_b_to_reg_leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q : std_logic_vector (48 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_inputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_reset0 : std_logic;
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_mem_top_q : std_logic_vector (2 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q : std_logic_vector (22 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q : std_logic_vector (23 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_eq : std_logic;
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_mem_top_q : std_logic_vector (2 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q : std_logic_vector (8 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (8 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (8 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (8 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_inputreg_q : std_logic_vector (24 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_reset0 : std_logic;
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_ia : std_logic_vector (24 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_iq : std_logic_vector (24 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_q : std_logic_vector (24 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_eq : std_logic;
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_sticky_ena_q : signal is true;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq : std_logic;
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_eq : std_logic;
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_mem_top_q : std_logic_vector (5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q : signal is true;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0 : std_logic;
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q : signal is true;
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_inputreg_q : std_logic_vector (42 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (42 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (42 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (42 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (26 downto 0);
signal ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (26 downto 0);
signal ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (26 downto 0);
signal ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_inputreg_q : std_logic_vector (10 downto 0);
signal ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 : std_logic;
signal ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia : std_logic_vector (10 downto 0);
signal ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq : std_logic_vector (10 downto 0);
signal ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_q : std_logic_vector (10 downto 0);
signal ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q : signal is true;
signal ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_inputreg_q : std_logic_vector (58 downto 0);
signal ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0 : std_logic;
signal ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia : std_logic_vector (58 downto 0);
signal ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq : std_logic_vector (58 downto 0);
signal ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_q : std_logic_vector (58 downto 0);
signal ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q : signal is true;
signal ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_inputreg_q : std_logic_vector (8 downto 0);
signal ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_ia : std_logic_vector (8 downto 0);
signal ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_iq : std_logic_vector (8 downto 0);
signal ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_q : std_logic_vector (8 downto 0);
signal ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_sticky_ena_q : signal is true;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_reset0 : std_logic;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_eq : std_logic;
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_sticky_ena_q : signal is true;
signal ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_reset0 : std_logic;
signal ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_sticky_ena_q : signal is true;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_inputreg_q : std_logic_vector (4 downto 0);
signal ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_reset0 : std_logic;
signal ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_ia : std_logic_vector (4 downto 0);
signal ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_iq : std_logic_vector (4 downto 0);
signal ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_q : std_logic_vector (4 downto 0);
signal ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_sticky_ena_q : signal is true;
signal pad_o_uid12_uid40_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal fracXz_uid82_fpLogE1pxTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx1_uid329_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (58 downto 0);
signal InvExpXIsZero_uid29_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid29_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_a : std_logic_vector(34 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_b : std_logic_vector(34 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_o : std_logic_vector (34 downto 0);
signal expFracPostRnd_uid124_fpLogE1pxTest_q : std_logic_vector (34 downto 0);
signal mO_uid130_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_a : std_logic_vector(0 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal expX_uid6_fpLogE1pxTest_in : std_logic_vector (30 downto 0);
signal expX_uid6_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal signX_uid7_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal signX_uid7_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal xM1_uid131_fpLogE1pxTest_a : std_logic_vector(31 downto 0);
signal xM1_uid131_fpLogE1pxTest_b : std_logic_vector(31 downto 0);
signal xM1_uid131_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_a : std_logic_vector(34 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_b : std_logic_vector(34 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_o : std_logic_vector (34 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal xLTM1_uid133_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid19_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid21_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_a : std_logic_vector(8 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_b : std_logic_vector(8 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_o : std_logic_vector (8 downto 0);
signal shifterAddrExt_uid34_fpLogE1pxTest_q : std_logic_vector (8 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_a : std_logic_vector(48 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_b : std_logic_vector(48 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_o : std_logic_vector (48 downto 0);
signal oMfracXRSExt_uid40_fpLogE1pxTest_q : std_logic_vector (48 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_a : std_logic_vector(8 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_b : std_logic_vector(8 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_o : std_logic_vector (8 downto 0);
signal addrMaskExt_uid50_fpLogE1pxTest_q : std_logic_vector (8 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_a : std_logic_vector(24 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_b : std_logic_vector(24 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_o : std_logic_vector (24 downto 0);
signal oPlusOFracX_uid53_fpLogE1pxTest_q : std_logic_vector (24 downto 0);
signal resIsX_uid62_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal resIsX_uid62_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal resIsX_uid62_fpLogE1pxTest_o : std_logic_vector (10 downto 0);
signal resIsX_uid62_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal resIsX_uid62_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal branch12_uid63_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal branch12_uid63_fpLogE1pxTest_o : std_logic_vector (10 downto 0);
signal branch12_uid63_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch12_uid63_fpLogE1pxTest_n : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal branch22_uid66_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal branch22_uid66_fpLogE1pxTest_o : std_logic_vector (10 downto 0);
signal branch22_uid66_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal branch22_uid66_fpLogE1pxTest_n : std_logic_vector (0 downto 0);
signal fracB_uid83_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal fracB_uid83_fpLogE1pxTest_q : std_logic_vector (23 downto 0);
signal e_uid84_fpLogE1pxTest_a : std_logic_vector(9 downto 0);
signal e_uid84_fpLogE1pxTest_b : std_logic_vector(9 downto 0);
signal e_uid84_fpLogE1pxTest_o : std_logic_vector (9 downto 0);
signal e_uid84_fpLogE1pxTest_q : std_logic_vector (9 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_o : std_logic_vector (10 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_cin : std_logic_vector (0 downto 0);
signal expXIsMo_uid86_fpLogE1pxTest_c : std_logic_vector (0 downto 0);
signal c_uid87_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal c_uid87_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal c_uid87_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal addTermOne_uid105_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal addTermOne_uid105_fpLogE1pxTest_q : std_logic_vector (34 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_a : std_logic_vector(58 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_b : std_logic_vector(58 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_o : std_logic_vector (58 downto 0);
signal finalSumAbs_uid113_fpLogE1pxTest_q : std_logic_vector (58 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_a : std_logic_vector(5 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_b : std_logic_vector(5 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_o : std_logic_vector (5 downto 0);
signal branch4ExpCorrection_uid118_fpLogE1pxTest_q : std_logic_vector (5 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_a : std_logic_vector(10 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_b : std_logic_vector(10 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_o : std_logic_vector (10 downto 0);
signal expRExt1_uid119_fpLogE1pxTest_q : std_logic_vector (10 downto 0);
signal signRFull_uid142_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal signRFull_uid142_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal signRFull_uid142_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc_uid148_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid148_fpLogE1pxTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid152_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid152_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(15 downto 0);
signal vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(15 downto 0);
signal vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (46 downto 0);
signal p0_uid247_constMult_q : std_logic_vector(33 downto 0);
signal lev1_a0_uid248_constMult_a : std_logic_vector(38 downto 0);
signal lev1_a0_uid248_constMult_b : std_logic_vector(38 downto 0);
signal lev1_a0_uid248_constMult_o : std_logic_vector (38 downto 0);
signal lev1_a0_uid248_constMult_q : std_logic_vector (37 downto 0);
signal vCount_uid269_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(31 downto 0);
signal vCount_uid269_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(31 downto 0);
signal vCount_uid269_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vCount_uid277_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(15 downto 0);
signal vCount_uid277_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(15 downto 0);
signal vCount_uid277_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid280_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid280_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid286_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid286_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid298_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid298_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (58 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal sEz_uid98_fpLogE1pxTest_q : std_logic_vector (24 downto 0);
signal rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal leftShiftStage2Idx2_uid332_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (58 downto 0);
signal lowRangeB_uid106_fpLogE1pxTest_in : std_logic_vector (21 downto 0);
signal lowRangeB_uid106_fpLogE1pxTest_b : std_logic_vector (21 downto 0);
signal highBBits_uid107_fpLogE1pxTest_in : std_logic_vector (51 downto 0);
signal highBBits_uid107_fpLogE1pxTest_b : std_logic_vector (29 downto 0);
signal leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (58 downto 0);
signal rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (58 downto 0);
signal cStage_uid272_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (58 downto 0);
signal leftShiftStage2Idx3_uid335_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (58 downto 0);
signal prodXYTruncFR_uid340_pT1_uid255_natLogPolyEval_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid340_pT1_uid255_natLogPolyEval_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid343_pT2_uid261_natLogPolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid343_pT2_uid261_natLogPolyEval_b : std_logic_vector (23 downto 0);
signal rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (58 downto 0);
signal frac_uid22_fpLogE1pxTest_in : std_logic_vector (22 downto 0);
signal frac_uid22_fpLogE1pxTest_b : std_logic_vector (22 downto 0);
signal redLO_uid47_fpLogE1pxTest_in : std_logic_vector (46 downto 0);
signal redLO_uid47_fpLogE1pxTest_b : std_logic_vector (46 downto 0);
signal zPPolyEval_uid91_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal zPPolyEval_uid91_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal vStagei_uid274_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid274_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_cmp_a : std_logic_vector(2 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_cmp_b : std_logic_vector(2 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_cmp_a : std_logic_vector(2 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_cmp_b : std_logic_vector(2 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a : std_logic_vector(5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b : std_logic_vector(5 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q : std_logic_vector(0 downto 0);
signal RLn_uid153_fpLogE1pxTest_q : std_logic_vector (31 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal fracR0_uid125_fpLogE1pxTest_in : std_logic_vector (23 downto 0);
signal fracR0_uid125_fpLogE1pxTest_b : std_logic_vector (22 downto 0);
signal expR_uid127_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal expR_uid127_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal branch11_uid64_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch11_uid64_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal shifterAddr_uid35_fpLogE1pxTest_in : std_logic_vector (4 downto 0);
signal shifterAddr_uid35_fpLogE1pxTest_b : std_logic_vector (4 downto 0);
signal oMfracXRSLZCIn_uid43_fpLogE1pxTest_in : std_logic_vector (46 downto 0);
signal oMfracXRSLZCIn_uid43_fpLogE1pxTest_b : std_logic_vector (23 downto 0);
signal addrMask_uid51_fpLogE1pxTest_in : std_logic_vector (4 downto 0);
signal addrMask_uid51_fpLogE1pxTest_b : std_logic_vector (4 downto 0);
signal msbUoPlusOFracX_uid54_fpLogE1pxTest_in : std_logic_vector (24 downto 0);
signal msbUoPlusOFracX_uid54_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal oPlusOFracXNormLow_uid57_fpLogE1pxTest_in : std_logic_vector (22 downto 0);
signal oPlusOFracXNormLow_uid57_fpLogE1pxTest_b : std_logic_vector (22 downto 0);
signal oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in : std_logic_vector (23 downto 0);
signal oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b : std_logic_vector (23 downto 0);
signal InvResIsX_uid72_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvResIsX_uid72_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch2_uid69_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch1_uid65_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch3_uid73_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal branch4_uid75_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal zAddrLow_uid89_fpLogE1pxTest_in : std_logic_vector (23 downto 0);
signal zAddrLow_uid89_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal fracBRed_uid99_fpLogE1pxTest_in : std_logic_vector (23 downto 0);
signal fracBRed_uid99_fpLogE1pxTest_b : std_logic_vector (22 downto 0);
signal xv0_uid244_constMult_in : std_logic_vector (5 downto 0);
signal xv0_uid244_constMult_b : std_logic_vector (5 downto 0);
signal xv1_uid245_constMult_in : std_logic_vector (8 downto 0);
signal xv1_uid245_constMult_b : std_logic_vector (2 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_a : std_logic_vector(35 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_b : std_logic_vector(35 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_o : std_logic_vector (35 downto 0);
signal sumAHighB_uid108_fpLogE1pxTest_q : std_logic_vector (35 downto 0);
signal rVStage_uid268_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (58 downto 0);
signal rVStage_uid268_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal vStage_uid271_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (26 downto 0);
signal vStage_uid271_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (26 downto 0);
signal X42dto0_uid306_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (42 downto 0);
signal X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (42 downto 0);
signal X10dto0_uid312_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (10 downto 0);
signal X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (10 downto 0);
signal expRExt1Red_uid120_fpLogE1pxTest_in : std_logic_vector (9 downto 0);
signal expRExt1Red_uid120_fpLogE1pxTest_b : std_logic_vector (9 downto 0);
signal rVStage_uid193_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid193_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal vStage_uid195_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal vStage_uid195_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage145dto0_uid239_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (45 downto 0);
signal LeftShiftStage145dto0_uid239_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (45 downto 0);
signal sR_uid249_constMult_in : std_logic_vector (36 downto 0);
signal sR_uid249_constMult_b : std_logic_vector (34 downto 0);
signal rVStage_uid282_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid282_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal vStage_uid284_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal vStage_uid284_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid288_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid288_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal vStage_uid290_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal vStage_uid290_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid300_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid300_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage157dto0_uid328_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (57 downto 0);
signal LeftShiftStage157dto0_uid328_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (57 downto 0);
signal LeftShiftStage156dto0_uid331_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage156dto0_uid331_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (56 downto 0);
signal LeftShiftStage155dto0_uid334_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (55 downto 0);
signal LeftShiftStage155dto0_uid334_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (55 downto 0);
signal finalSum_uid106_uid109_fpLogE1pxTest_q : std_logic_vector (57 downto 0);
signal lowRangeB_uid256_natLogPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid256_natLogPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid257_natLogPolyEval_in : std_logic_vector (13 downto 0);
signal highBBits_uid257_natLogPolyEval_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid262_natLogPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid262_natLogPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid263_natLogPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid263_natLogPolyEval_b : std_logic_vector (21 downto 0);
signal RightShiftStage147dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (47 downto 0);
signal RightShiftStage147dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (46 downto 0);
signal fracR_uid122_fpLogE1pxTest_in : std_logic_vector (57 downto 0);
signal fracR_uid122_fpLogE1pxTest_b : std_logic_vector (23 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid23_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal oFracX_uid32_fpLogE1pxTest_q : std_logic_vector (23 downto 0);
signal X38dto0_uid217_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (38 downto 0);
signal X38dto0_uid217_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (38 downto 0);
signal X30dto0_uid220_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (30 downto 0);
signal X30dto0_uid220_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (30 downto 0);
signal X22dto0_uid223_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (22 downto 0);
signal X22dto0_uid223_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (22 downto 0);
signal yT1_uid254_natLogPolyEval_in : std_logic_vector (15 downto 0);
signal yT1_uid254_natLogPolyEval_b : std_logic_vector (12 downto 0);
signal rVStage_uid276_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid276_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal vStage_uid278_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (15 downto 0);
signal vStage_uid278_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal rightShiftStageSel4Dto3_uid165_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid165_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid181_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid181_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid185_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (23 downto 0);
signal rVStage_uid185_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (15 downto 0);
signal vStage_uid188_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal vStage_uid188_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal join_uid58_fpLogE1pxTest_q : std_logic_vector (23 downto 0);
signal concBranch_uid76_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal addr_uid90_fpLogE1pxTest_q : std_logic_vector (8 downto 0);
signal sEz_uid101_fpLogE1pxTest_q : std_logic_vector (24 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(3 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(3 downto 0);
signal vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage2Idx1_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (46 downto 0);
signal vCount_uid289_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(3 downto 0);
signal vCount_uid289_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(3 downto 0);
signal vCount_uid289_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid292_countZ_uid114_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid292_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (3 downto 0);
signal vCount_uid301_countZ_uid114_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal vCount_uid301_countZ_uid114_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal vCount_uid301_countZ_uid114_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal FullSumAB57_uid110_fpLogE1pxTest_in : std_logic_vector (57 downto 0);
signal FullSumAB57_uid110_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal sumAHighB_uid258_natLogPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid258_natLogPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid258_natLogPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid258_natLogPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid264_natLogPolyEval_a : std_logic_vector(31 downto 0);
signal sumAHighB_uid264_natLogPolyEval_b : std_logic_vector(31 downto 0);
signal sumAHighB_uid264_natLogPolyEval_o : std_logic_vector (31 downto 0);
signal sumAHighB_uid264_natLogPolyEval_q : std_logic_vector (31 downto 0);
signal rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal expFracConc_uid123_fpLogE1pxTest_q : std_logic_vector (33 downto 0);
signal exc_I_uid24_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid24_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid25_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightPaddedIn_uid37_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal leftShiftStage0Idx1_uid218_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (46 downto 0);
signal leftShiftStage0Idx2_uid221_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (46 downto 0);
signal leftShiftStage0Idx3_uid224_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (46 downto 0);
signal cStage_uid189_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (15 downto 0);
signal rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal r_uid213_leadingZeros_uid44_fpLogE1pxTest_q : std_logic_vector (4 downto 0);
signal leftShiftStage2_uid242_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage2_uid242_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (46 downto 0);
signal rVStage_uid294_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid294_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal vStage_uid296_countZ_uid114_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal vStage_uid296_countZ_uid114_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal r_uid302_countZ_uid114_fpLogE1pxTest_q : std_logic_vector (5 downto 0);
signal s1_uid256_uid259_natLogPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid262_uid265_natLogPolyEval_q : std_logic_vector (33 downto 0);
signal rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal InvExc_I_uid28_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid28_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal posInf_uid136_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal negInf_uid138_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid26_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal X47dto8_uid156_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (47 downto 0);
signal X47dto8_uid156_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (39 downto 0);
signal X47dto16_uid159_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (47 downto 0);
signal X47dto16_uid159_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (31 downto 0);
signal X47dto24_uid162_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (47 downto 0);
signal X47dto24_uid162_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (23 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_a : std_logic_vector(8 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_b : std_logic_vector(8 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_o : std_logic_vector (8 downto 0);
signal expBran3PreExt_uid45_fpLogE1pxTest_q : std_logic_vector (8 downto 0);
signal leftShiftStageSel4Dto3_uid225_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid225_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (0 downto 0);
signal fracXBranch4_uid49_fpLogE1pxTest_in : std_logic_vector (46 downto 0);
signal fracXBranch4_uid49_fpLogE1pxTest_b : std_logic_vector (24 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_a : std_logic_vector(9 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_b : std_logic_vector(9 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_o : std_logic_vector (9 downto 0);
signal expRExt0_uid117_fpLogE1pxTest_q : std_logic_vector (9 downto 0);
signal leftShiftStageSel5Dto4_uid314_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid314_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid325_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid325_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (1 downto 0);
signal peOR_uid93_fpLogE1pxTest_in : std_logic_vector (32 downto 0);
signal peOR_uid93_fpLogE1pxTest_b : std_logic_vector (26 downto 0);
signal fracXRS_uid39_fpLogE1pxTest_in : std_logic_vector (47 downto 0);
signal fracXRS_uid39_fpLogE1pxTest_b : std_logic_vector (24 downto 0);
signal InvExc_N_uid27_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid27_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal expBran3Pre_uid46_fpLogE1pxTest_in : std_logic_vector (7 downto 0);
signal expBran3Pre_uid46_fpLogE1pxTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (46 downto 0);
signal fracXBranch4Red_uid80_fpLogE1pxTest_in : std_logic_vector (23 downto 0);
signal fracXBranch4Red_uid80_fpLogE1pxTest_b : std_logic_vector (23 downto 0);
signal leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (58 downto 0);
signal fracXRSRange_uid81_fpLogE1pxTest_in : std_logic_vector (23 downto 0);
signal fracXRSRange_uid81_fpLogE1pxTest_b : std_logic_vector (23 downto 0);
signal exc_R_uid30_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid30_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q : std_logic_vector (47 downto 0);
signal LeftShiftStage044dto0_uid228_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (44 downto 0);
signal LeftShiftStage044dto0_uid228_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (44 downto 0);
signal LeftShiftStage042dto0_uid231_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (42 downto 0);
signal LeftShiftStage042dto0_uid231_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (42 downto 0);
signal LeftShiftStage040dto0_uid234_fracXBranch4Ext_uid48_fpLogE1pxTest_in : std_logic_vector (40 downto 0);
signal LeftShiftStage040dto0_uid234_fracXBranch4Ext_uid48_fpLogE1pxTest_b : std_logic_vector (40 downto 0);
signal LeftShiftStage054dto0_uid317_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (54 downto 0);
signal LeftShiftStage054dto0_uid317_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (54 downto 0);
signal LeftShiftStage050dto0_uid320_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (50 downto 0);
signal LeftShiftStage050dto0_uid320_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (50 downto 0);
signal LeftShiftStage046dto0_uid323_normVal_uid115_fpLogE1pxTest_in : std_logic_vector (46 downto 0);
signal LeftShiftStage046dto0_uid323_normVal_uid115_fpLogE1pxTest_b : std_logic_vector (46 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRInf0_uid134_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRNaN0_uid139_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage047dto2_uid167_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (47 downto 0);
signal RightShiftStage047dto2_uid167_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (45 downto 0);
signal RightShiftStage047dto4_uid170_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (47 downto 0);
signal RightShiftStage047dto4_uid170_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (43 downto 0);
signal RightShiftStage047dto6_uid173_fracXRSExt_uid36_fpLogE1pxTest_in : std_logic_vector (47 downto 0);
signal RightShiftStage047dto6_uid173_fracXRSExt_uid36_fpLogE1pxTest_b : std_logic_vector (41 downto 0);
signal leftShiftStage1Idx1_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (46 downto 0);
signal leftShiftStage1Idx2_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (46 downto 0);
signal leftShiftStage1Idx3_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_q : std_logic_vector (46 downto 0);
signal leftShiftStage1Idx1_uid318_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (58 downto 0);
signal leftShiftStage1Idx2_uid321_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (58 downto 0);
signal leftShiftStage1Idx3_uid324_normVal_uid115_fpLogE1pxTest_q : std_logic_vector (58 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRInf0_uid137_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid140_fpLogE1pxTest_q : std_logic_vector(0 downto 0);
signal concExc_uid143_fpLogE1pxTest_q : std_logic_vector (2 downto 0);
begin
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable(LOGICAL,845)
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_a <= en;
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q <= not ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_a;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor(LOGICAL,978)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q <= not (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_a or ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_b);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_mem_top(CONSTANT,948)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_mem_top_q <= "011011";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp(LOGICAL,949)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdmux_q);
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg(REG,950)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena(REG,979)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_nor_q = "1") THEN
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd(LOGICAL,980)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_sticky_ena_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b <= en;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_a and ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_b;
--signX_uid7_fpLogE1pxTest(BITSELECT,6)@0
signX_uid7_fpLogE1pxTest_in <= a;
signX_uid7_fpLogE1pxTest_b <= signX_uid7_fpLogE1pxTest_in(31 downto 31);
--ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b(DELAY,562)@0
ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => signX_uid7_fpLogE1pxTest_b, xout => ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWF_uid8_fpLogE1pxTest(CONSTANT,7)
cstAllZWF_uid8_fpLogE1pxTest_q <= "00000000000000000000000";
--ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a(DELAY,418)@0
ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => a, xout => ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--frac_uid22_fpLogE1pxTest(BITSELECT,21)@1
frac_uid22_fpLogE1pxTest_in <= ld_xIn_a_to_frac_uid22_fpLogE1pxTest_a_q(22 downto 0);
frac_uid22_fpLogE1pxTest_b <= frac_uid22_fpLogE1pxTest_in(22 downto 0);
--fracXIsZero_uid23_fpLogE1pxTest(LOGICAL,22)@1
fracXIsZero_uid23_fpLogE1pxTest_a <= frac_uid22_fpLogE1pxTest_b;
fracXIsZero_uid23_fpLogE1pxTest_b <= cstAllZWF_uid8_fpLogE1pxTest_q;
fracXIsZero_uid23_fpLogE1pxTest_q <= "1" when fracXIsZero_uid23_fpLogE1pxTest_a = fracXIsZero_uid23_fpLogE1pxTest_b else "0";
--cstAllOWE_uid15_fpLogE1pxTest(CONSTANT,14)
cstAllOWE_uid15_fpLogE1pxTest_q <= "11111111";
--expX_uid6_fpLogE1pxTest(BITSELECT,5)@0
expX_uid6_fpLogE1pxTest_in <= a(30 downto 0);
expX_uid6_fpLogE1pxTest_b <= expX_uid6_fpLogE1pxTest_in(30 downto 23);
--expXIsMax_uid21_fpLogE1pxTest(LOGICAL,20)@0
expXIsMax_uid21_fpLogE1pxTest_a <= expX_uid6_fpLogE1pxTest_b;
expXIsMax_uid21_fpLogE1pxTest_b <= cstAllOWE_uid15_fpLogE1pxTest_q;
expXIsMax_uid21_fpLogE1pxTest_q <= "1" when expXIsMax_uid21_fpLogE1pxTest_a = expXIsMax_uid21_fpLogE1pxTest_b else "0";
--ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a(DELAY,420)@0
ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsMax_uid21_fpLogE1pxTest_q, xout => ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid24_fpLogE1pxTest(LOGICAL,23)@1
exc_I_uid24_fpLogE1pxTest_a <= ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q;
exc_I_uid24_fpLogE1pxTest_b <= fracXIsZero_uid23_fpLogE1pxTest_q;
exc_I_uid24_fpLogE1pxTest_q <= exc_I_uid24_fpLogE1pxTest_a and exc_I_uid24_fpLogE1pxTest_b;
--ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a(DELAY,553)@0
ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid7_fpLogE1pxTest_b, xout => ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--negInf_uid138_fpLogE1pxTest(LOGICAL,137)@1
negInf_uid138_fpLogE1pxTest_a <= ld_signX_uid7_fpLogE1pxTest_b_to_negInf_uid138_fpLogE1pxTest_a_q;
negInf_uid138_fpLogE1pxTest_b <= exc_I_uid24_fpLogE1pxTest_q;
negInf_uid138_fpLogE1pxTest_q <= negInf_uid138_fpLogE1pxTest_a and negInf_uid138_fpLogE1pxTest_b;
--GND(CONSTANT,0)
GND_q <= "0";
--cstBias_uid9_fpLogE1pxTest(CONSTANT,8)
cstBias_uid9_fpLogE1pxTest_q <= "01111111";
--mO_uid130_fpLogE1pxTest(BITJOIN,129)@0
mO_uid130_fpLogE1pxTest_q <= VCC_q & cstBias_uid9_fpLogE1pxTest_q & cstAllZWF_uid8_fpLogE1pxTest_q;
--xLTM1_uid133_fpLogE1pxTest(COMPARE,132)@0
xLTM1_uid133_fpLogE1pxTest_cin <= GND_q;
xLTM1_uid133_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & mO_uid130_fpLogE1pxTest_q) & '0';
xLTM1_uid133_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & a) & xLTM1_uid133_fpLogE1pxTest_cin(0);
xLTM1_uid133_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xLTM1_uid133_fpLogE1pxTest_a) - UNSIGNED(xLTM1_uid133_fpLogE1pxTest_b));
xLTM1_uid133_fpLogE1pxTest_c(0) <= xLTM1_uid133_fpLogE1pxTest_o(34);
--ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b(DELAY,556)@0
ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xLTM1_uid133_fpLogE1pxTest_c, xout => ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid27_fpLogE1pxTest(LOGICAL,26)@1
InvExc_N_uid27_fpLogE1pxTest_a <= exc_N_uid26_fpLogE1pxTest_q;
InvExc_N_uid27_fpLogE1pxTest_q <= not InvExc_N_uid27_fpLogE1pxTest_a;
--InvExc_I_uid28_fpLogE1pxTest(LOGICAL,27)@1
InvExc_I_uid28_fpLogE1pxTest_a <= exc_I_uid24_fpLogE1pxTest_q;
InvExc_I_uid28_fpLogE1pxTest_q <= not InvExc_I_uid28_fpLogE1pxTest_a;
--cstAllZWE_uid17_fpLogE1pxTest(CONSTANT,16)
cstAllZWE_uid17_fpLogE1pxTest_q <= "00000000";
--expXIsZero_uid19_fpLogE1pxTest(LOGICAL,18)@0
expXIsZero_uid19_fpLogE1pxTest_a <= expX_uid6_fpLogE1pxTest_b;
expXIsZero_uid19_fpLogE1pxTest_b <= cstAllZWE_uid17_fpLogE1pxTest_q;
expXIsZero_uid19_fpLogE1pxTest_q <= "1" when expXIsZero_uid19_fpLogE1pxTest_a = expXIsZero_uid19_fpLogE1pxTest_b else "0";
--ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a(DELAY,427)@0
ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid19_fpLogE1pxTest_q, xout => ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExpXIsZero_uid29_fpLogE1pxTest(LOGICAL,28)@1
InvExpXIsZero_uid29_fpLogE1pxTest_a <= ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q;
InvExpXIsZero_uid29_fpLogE1pxTest_q <= not InvExpXIsZero_uid29_fpLogE1pxTest_a;
--exc_R_uid30_fpLogE1pxTest(LOGICAL,29)@1
exc_R_uid30_fpLogE1pxTest_a <= InvExpXIsZero_uid29_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_b <= InvExc_I_uid28_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_c <= InvExc_N_uid27_fpLogE1pxTest_q;
exc_R_uid30_fpLogE1pxTest_q <= exc_R_uid30_fpLogE1pxTest_a and exc_R_uid30_fpLogE1pxTest_b and exc_R_uid30_fpLogE1pxTest_c;
--excRNaN0_uid139_fpLogE1pxTest(LOGICAL,138)@1
excRNaN0_uid139_fpLogE1pxTest_a <= exc_R_uid30_fpLogE1pxTest_q;
excRNaN0_uid139_fpLogE1pxTest_b <= ld_xLTM1_uid133_fpLogE1pxTest_c_to_excRNaN0_uid139_fpLogE1pxTest_b_q;
excRNaN0_uid139_fpLogE1pxTest_q <= excRNaN0_uid139_fpLogE1pxTest_a and excRNaN0_uid139_fpLogE1pxTest_b;
--InvFracXIsZero_uid25_fpLogE1pxTest(LOGICAL,24)@1
InvFracXIsZero_uid25_fpLogE1pxTest_a <= fracXIsZero_uid23_fpLogE1pxTest_q;
InvFracXIsZero_uid25_fpLogE1pxTest_q <= not InvFracXIsZero_uid25_fpLogE1pxTest_a;
--exc_N_uid26_fpLogE1pxTest(LOGICAL,25)@1
exc_N_uid26_fpLogE1pxTest_a <= ld_expXIsMax_uid21_fpLogE1pxTest_q_to_exc_I_uid24_fpLogE1pxTest_a_q;
exc_N_uid26_fpLogE1pxTest_b <= InvFracXIsZero_uid25_fpLogE1pxTest_q;
exc_N_uid26_fpLogE1pxTest_q <= exc_N_uid26_fpLogE1pxTest_a and exc_N_uid26_fpLogE1pxTest_b;
--excRNaN_uid140_fpLogE1pxTest(LOGICAL,139)@1
excRNaN_uid140_fpLogE1pxTest_a <= exc_N_uid26_fpLogE1pxTest_q;
excRNaN_uid140_fpLogE1pxTest_b <= excRNaN0_uid139_fpLogE1pxTest_q;
excRNaN_uid140_fpLogE1pxTest_c <= negInf_uid138_fpLogE1pxTest_q;
excRNaN_uid140_fpLogE1pxTest_q <= excRNaN_uid140_fpLogE1pxTest_a or excRNaN_uid140_fpLogE1pxTest_b or excRNaN_uid140_fpLogE1pxTest_c;
--InvExcRNaN_uid141_fpLogE1pxTest(LOGICAL,140)@1
InvExcRNaN_uid141_fpLogE1pxTest_a <= excRNaN_uid140_fpLogE1pxTest_q;
InvExcRNaN_uid141_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExcRNaN_uid141_fpLogE1pxTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExcRNaN_uid141_fpLogE1pxTest_q <= not InvExcRNaN_uid141_fpLogE1pxTest_a;
END IF;
END PROCESS;
--signRFull_uid142_fpLogE1pxTest(LOGICAL,141)@2
signRFull_uid142_fpLogE1pxTest_a <= InvExcRNaN_uid141_fpLogE1pxTest_q;
signRFull_uid142_fpLogE1pxTest_b <= ld_signX_uid7_fpLogE1pxTest_b_to_signRFull_uid142_fpLogE1pxTest_b_q;
signRFull_uid142_fpLogE1pxTest_q <= signRFull_uid142_fpLogE1pxTest_a and signRFull_uid142_fpLogE1pxTest_b;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg(DELAY,968)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signRFull_uid142_fpLogE1pxTest_q, xout => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt(COUNTER,944)
-- every=1, low=0, high=27, step=1, init=1
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_i = 26 THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_eq = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_i <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_i - 27;
ELSE
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_i <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_i,5));
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdreg(REG,945)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdreg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--xIn(GPIN,3)@0
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdmux(MUX,946)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdmux_s <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdmux: PROCESS (ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdmux_s, ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdreg_q, ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdmux_s IS
WHEN "0" => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdmux_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdreg_q;
WHEN "1" => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdmux_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem(DUALMEM,969)
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_inputreg_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdreg_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdmux_q;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 28,
width_b => 1,
widthad_b => 5,
numwords_b => 28,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq,
address_a => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_aa,
data_a => ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_ia
);
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_reset0 <= areset;
ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_iq(0 downto 0);
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor(LOGICAL,965)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q <= not (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_a or ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_b);
--ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_mem_top(CONSTANT,935)
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q <= "011100";
--ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_cmp(LOGICAL,936)
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_cmp_a <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_mem_top_q;
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q);
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_cmp_q <= "1" when ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_cmp_a = ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_cmp_b else "0";
--ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_cmpReg(REG,937)
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena(REG,966)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_nor_q = "1") THEN
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd(LOGICAL,967)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_sticky_ena_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b <= en;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_a and ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_b;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg(DELAY,955)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid6_fpLogE1pxTest_b, xout => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt(COUNTER,931)
-- every=1, low=0, high=28, step=1, init=1
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i = 27 THEN
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i - 28;
ELSE
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_i,5));
--ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg(REG,932)
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux(MUX,933)
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s, ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q, ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem(DUALMEM,956)
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_inputreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 5,
numwords_a => 29,
width_b => 8,
widthad_b => 5,
numwords_b => 29,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_ia
);
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_iq(7 downto 0);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor(LOGICAL,925)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q <= not (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_a or ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_b);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top(CONSTANT,921)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q <= "010010";
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp(LOGICAL,922)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_mem_top_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q <= "1" when ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_a = ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_b else "0";
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg(REG,923)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena(REG,926)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_nor_q = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd(LOGICAL,927)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_sticky_ena_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b <= en;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_a and ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_b;
--cstBiasMO_uid10_fpLogE1pxTest(CONSTANT,9)
cstBiasMO_uid10_fpLogE1pxTest_q <= "01111110";
--expXIsMo_uid86_fpLogE1pxTest(COMPARE,85)@0
expXIsMo_uid86_fpLogE1pxTest_cin <= GND_q;
expXIsMo_uid86_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
expXIsMo_uid86_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMO_uid10_fpLogE1pxTest_q) & expXIsMo_uid86_fpLogE1pxTest_cin(0);
expXIsMo_uid86_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXIsMo_uid86_fpLogE1pxTest_a) - UNSIGNED(expXIsMo_uid86_fpLogE1pxTest_b));
expXIsMo_uid86_fpLogE1pxTest_c(0) <= expXIsMo_uid86_fpLogE1pxTest_o(10);
--ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b(DELAY,493)@0
ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 7 )
PORT MAP ( xin => expXIsMo_uid86_fpLogE1pxTest_c, xout => ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cstBiasMWFP1_uid14_fpLogE1pxTest(CONSTANT,13)
cstBiasMWFP1_uid14_fpLogE1pxTest_q <= "01100111";
--resIsX_uid62_fpLogE1pxTest(COMPARE,61)@0
resIsX_uid62_fpLogE1pxTest_cin <= GND_q;
resIsX_uid62_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
resIsX_uid62_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMWFP1_uid14_fpLogE1pxTest_q) & resIsX_uid62_fpLogE1pxTest_cin(0);
resIsX_uid62_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(resIsX_uid62_fpLogE1pxTest_a) - UNSIGNED(resIsX_uid62_fpLogE1pxTest_b));
resIsX_uid62_fpLogE1pxTest_c(0) <= resIsX_uid62_fpLogE1pxTest_o(10);
--InvResIsX_uid72_fpLogE1pxTest(LOGICAL,71)@0
InvResIsX_uid72_fpLogE1pxTest_a <= resIsX_uid62_fpLogE1pxTest_c;
InvResIsX_uid72_fpLogE1pxTest_q <= not InvResIsX_uid72_fpLogE1pxTest_a;
--branch22_uid66_fpLogE1pxTest(COMPARE,65)@0
branch22_uid66_fpLogE1pxTest_cin <= GND_q;
branch22_uid66_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
branch22_uid66_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid9_fpLogE1pxTest_q) & branch22_uid66_fpLogE1pxTest_cin(0);
branch22_uid66_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch22_uid66_fpLogE1pxTest_a) - UNSIGNED(branch22_uid66_fpLogE1pxTest_b));
branch22_uid66_fpLogE1pxTest_c(0) <= branch22_uid66_fpLogE1pxTest_o(10);
branch22_uid66_fpLogE1pxTest_n(0) <= not branch22_uid66_fpLogE1pxTest_o(10);
--branch4_uid75_fpLogE1pxTest(LOGICAL,74)@0
branch4_uid75_fpLogE1pxTest_a <= branch22_uid66_fpLogE1pxTest_c;
branch4_uid75_fpLogE1pxTest_b <= InvResIsX_uid72_fpLogE1pxTest_q;
branch4_uid75_fpLogE1pxTest_c <= signX_uid7_fpLogE1pxTest_b;
branch4_uid75_fpLogE1pxTest_q <= branch4_uid75_fpLogE1pxTest_a and branch4_uid75_fpLogE1pxTest_b and branch4_uid75_fpLogE1pxTest_c;
--ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a(DELAY,492)@0
ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 7 )
PORT MAP ( xin => branch4_uid75_fpLogE1pxTest_q, xout => ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--c_uid87_fpLogE1pxTest(LOGICAL,86)@7
c_uid87_fpLogE1pxTest_a <= ld_branch4_uid75_fpLogE1pxTest_q_to_c_uid87_fpLogE1pxTest_a_q;
c_uid87_fpLogE1pxTest_b <= ld_expXIsMo_uid86_fpLogE1pxTest_c_to_c_uid87_fpLogE1pxTest_b_q;
c_uid87_fpLogE1pxTest_q <= c_uid87_fpLogE1pxTest_a and c_uid87_fpLogE1pxTest_b;
--reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1(REG,373)@7
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q <= c_uid87_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_nor(LOGICAL,1085)
ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_nor_b <= ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_sticky_ena_q;
ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_nor_q <= not (ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_nor_a or ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_nor_b);
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_mem_top(CONSTANT,895)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_mem_top_q <= "0100";
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp(LOGICAL,896)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_mem_top_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdmux_q);
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q <= "1" when ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_a = ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_b else "0";
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg(REG,897)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_sticky_ena(REG,1086)
ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_nor_q = "1") THEN
ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_enaAnd(LOGICAL,1087)
ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_enaAnd_a <= ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_sticky_ena_q;
ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_enaAnd_b <= en;
ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_enaAnd_q <= ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_enaAnd_a and ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_enaAnd_b;
--shifterAddrExt_uid34_fpLogE1pxTest(SUB,33)@0
shifterAddrExt_uid34_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
shifterAddrExt_uid34_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & expX_uid6_fpLogE1pxTest_b);
shifterAddrExt_uid34_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shifterAddrExt_uid34_fpLogE1pxTest_a) - UNSIGNED(shifterAddrExt_uid34_fpLogE1pxTest_b));
shifterAddrExt_uid34_fpLogE1pxTest_q <= shifterAddrExt_uid34_fpLogE1pxTest_o(8 downto 0);
--shifterAddr_uid35_fpLogE1pxTest(BITSELECT,34)@0
shifterAddr_uid35_fpLogE1pxTest_in <= shifterAddrExt_uid34_fpLogE1pxTest_q(4 downto 0);
shifterAddr_uid35_fpLogE1pxTest_b <= shifterAddr_uid35_fpLogE1pxTest_in(4 downto 0);
--ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_inputreg(DELAY,1075)
ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 5, depth => 1 )
PORT MAP ( xin => shifterAddr_uid35_fpLogE1pxTest_b, xout => ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt(COUNTER,891)
-- every=1, low=0, high=4, step=1, init=1
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_i = 3 THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_i <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_i - 4;
ELSE
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_i <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_i,3));
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdreg(REG,892)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdreg_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdmux(MUX,893)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdmux_s, ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdreg_q, ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdmux_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdmux_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem(DUALMEM,1076)
ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_ia <= ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_inputreg_q;
ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdreg_q;
ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdmux_q;
ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 5,
widthad_a => 3,
numwords_a => 5,
width_b => 5,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_iq,
address_a => ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_aa,
data_a => ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_ia
);
ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_reset0 <= areset;
ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_q <= ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_iq(4 downto 0);
--reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0(REG,409)@7
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q <= ld_shifterAddr_uid35_fpLogE1pxTest_b_to_reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--branch4ExpCorrection_uid118_fpLogE1pxTest(SUB,117)@8
branch4ExpCorrection_uid118_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_shifterAddr_uid35_fpLogE1pxTest_0_to_branch4ExpCorrection_uid118_fpLogE1pxTest_0_q);
branch4ExpCorrection_uid118_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00000" & reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q);
branch4ExpCorrection_uid118_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch4ExpCorrection_uid118_fpLogE1pxTest_a) - UNSIGNED(branch4ExpCorrection_uid118_fpLogE1pxTest_b));
branch4ExpCorrection_uid118_fpLogE1pxTest_q <= branch4ExpCorrection_uid118_fpLogE1pxTest_o(5 downto 0);
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg(DELAY,915)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => branch4ExpCorrection_uid118_fpLogE1pxTest_q, xout => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt(COUNTER,917)
-- every=1, low=0, high=18, step=1, init=1
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i = 17 THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_eq = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i - 18;
ELSE
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_i,5));
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg(REG,918)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux(MUX,919)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s, ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q, ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem(DUALMEM,916)
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_inputreg_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdreg_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_rdmux_q;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 6,
widthad_a => 5,
numwords_a => 19,
width_b => 6,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_ia
);
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q <= ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_iq(5 downto 0);
--zs_uid267_countZ_uid114_fpLogE1pxTest(CONSTANT,266)
zs_uid267_countZ_uid114_fpLogE1pxTest_q <= "00000000000000000000000000000000";
--LeftShiftStage145dto0_uid239_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,238)@7
LeftShiftStage145dto0_uid239_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_q(45 downto 0);
LeftShiftStage145dto0_uid239_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage145dto0_uid239_fracXBranch4Ext_uid48_fpLogE1pxTest_in(45 downto 0);
--leftShiftStage2Idx1_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,239)@7
leftShiftStage2Idx1_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage145dto0_uid239_fracXBranch4Ext_uid48_fpLogE1pxTest_b & GND_q;
--X22dto0_uid223_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,222)@6
X22dto0_uid223_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(22 downto 0);
X22dto0_uid223_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X22dto0_uid223_fracXBranch4Ext_uid48_fpLogE1pxTest_in(22 downto 0);
--padConst_uid36_fpLogE1pxTest(CONSTANT,35)
padConst_uid36_fpLogE1pxTest_q <= "000000000000000000000000";
--leftShiftStage0Idx3_uid224_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,223)@6
leftShiftStage0Idx3_uid224_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X22dto0_uid223_fracXBranch4Ext_uid48_fpLogE1pxTest_b & padConst_uid36_fpLogE1pxTest_q;
--X30dto0_uid220_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,219)@6
X30dto0_uid220_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(30 downto 0);
X30dto0_uid220_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X30dto0_uid220_fracXBranch4Ext_uid48_fpLogE1pxTest_in(30 downto 0);
--rightShiftStage0Idx2Pad16_uid160_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,159)
rightShiftStage0Idx2Pad16_uid160_fracXRSExt_uid36_fpLogE1pxTest_q <= "0000000000000000";
--leftShiftStage0Idx2_uid221_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,220)@6
leftShiftStage0Idx2_uid221_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X30dto0_uid220_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage0Idx2Pad16_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
--X38dto0_uid217_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,216)@6
X38dto0_uid217_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= redLO_uid47_fpLogE1pxTest_b(38 downto 0);
X38dto0_uid217_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= X38dto0_uid217_fracXBranch4Ext_uid48_fpLogE1pxTest_in(38 downto 0);
--leftShiftStage0Idx1_uid218_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,217)@6
leftShiftStage0Idx1_uid218_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= X38dto0_uid217_fracXBranch4Ext_uid48_fpLogE1pxTest_b & cstAllZWE_uid17_fpLogE1pxTest_q;
--RightShiftStage147dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,177)@2
RightShiftStage147dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage147dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage147dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_in(47 downto 1);
--rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,179)@2
rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q <= GND_q & RightShiftStage147dto1_uid178_fracXRSExt_uid36_fpLogE1pxTest_b;
--X47dto24_uid162_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,161)@1
X47dto24_uid162_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X47dto24_uid162_fracXRSExt_uid36_fpLogE1pxTest_b <= X47dto24_uid162_fracXRSExt_uid36_fpLogE1pxTest_in(47 downto 24);
--rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,163)@1
rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q <= padConst_uid36_fpLogE1pxTest_q & X47dto24_uid162_fracXRSExt_uid36_fpLogE1pxTest_b;
--X47dto16_uid159_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,158)@1
X47dto16_uid159_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X47dto16_uid159_fracXRSExt_uid36_fpLogE1pxTest_b <= X47dto16_uid159_fracXRSExt_uid36_fpLogE1pxTest_in(47 downto 16);
--rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,160)@1
rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx2Pad16_uid160_fracXRSExt_uid36_fpLogE1pxTest_q & X47dto16_uid159_fracXRSExt_uid36_fpLogE1pxTest_b;
--X47dto8_uid156_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,155)@1
X47dto8_uid156_fracXRSExt_uid36_fpLogE1pxTest_in <= rightPaddedIn_uid37_fpLogE1pxTest_q;
X47dto8_uid156_fracXRSExt_uid36_fpLogE1pxTest_b <= X47dto8_uid156_fracXRSExt_uid36_fpLogE1pxTest_in(47 downto 8);
--rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,157)@1
rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q <= cstAllZWE_uid17_fpLogE1pxTest_q & X47dto8_uid156_fracXRSExt_uid36_fpLogE1pxTest_b;
--oFracX_uid32_fpLogE1pxTest(BITJOIN,31)@1
oFracX_uid32_fpLogE1pxTest_q <= VCC_q & frac_uid22_fpLogE1pxTest_b;
--rightPaddedIn_uid37_fpLogE1pxTest(BITJOIN,36)@1
rightPaddedIn_uid37_fpLogE1pxTest_q <= oFracX_uid32_fpLogE1pxTest_q & padConst_uid36_fpLogE1pxTest_q;
--rightShiftStageSel4Dto3_uid165_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,164)@0
rightShiftStageSel4Dto3_uid165_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b;
rightShiftStageSel4Dto3_uid165_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel4Dto3_uid165_fracXRSExt_uid36_fpLogE1pxTest_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1(REG,351)@0
reg_rightShiftStageSel4Dto3_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q <= rightShiftStageSel4Dto3_uid165_fracXRSExt_uid36_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest(MUX,165)@1
rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s <= reg_rightShiftStageSel4Dto3_uid165_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_1_q;
rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s, en, rightPaddedIn_uid37_fpLogE1pxTest_q, rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightPaddedIn_uid37_fpLogE1pxTest_q;
WHEN "01" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx1_uid158_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx2_uid161_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage0Idx3_uid164_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage047dto6_uid173_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,172)@1
RightShiftStage047dto6_uid173_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage047dto6_uid173_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage047dto6_uid173_fracXRSExt_uid36_fpLogE1pxTest_in(47 downto 6);
--ld_RightShiftStage047dto6_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,591)@1
ld_RightShiftStage047dto6_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 42, depth => 1 )
PORT MAP ( xin => RightShiftStage047dto6_uid173_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage047dto6_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,174)@2
rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx3Pad6_uid174_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage047dto6_uid173_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--rightShiftStage1Idx2Pad4_uid171_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,170)
rightShiftStage1Idx2Pad4_uid171_fracXRSExt_uid36_fpLogE1pxTest_q <= "0000";
--RightShiftStage047dto4_uid170_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,169)@1
RightShiftStage047dto4_uid170_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage047dto4_uid170_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage047dto4_uid170_fracXRSExt_uid36_fpLogE1pxTest_in(47 downto 4);
--ld_RightShiftStage047dto4_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,589)@1
ld_RightShiftStage047dto4_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 44, depth => 1 )
PORT MAP ( xin => RightShiftStage047dto4_uid170_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage047dto4_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,171)@2
rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx2Pad4_uid171_fracXRSExt_uid36_fpLogE1pxTest_q & ld_RightShiftStage047dto4_uid170_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--z2_uid100_fpLogE1pxTest(CONSTANT,99)
z2_uid100_fpLogE1pxTest_q <= "00";
--RightShiftStage047dto2_uid167_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,166)@1
RightShiftStage047dto2_uid167_fracXRSExt_uid36_fpLogE1pxTest_in <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
RightShiftStage047dto2_uid167_fracXRSExt_uid36_fpLogE1pxTest_b <= RightShiftStage047dto2_uid167_fracXRSExt_uid36_fpLogE1pxTest_in(47 downto 2);
--ld_RightShiftStage047dto2_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a(DELAY,587)@1
ld_RightShiftStage047dto2_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => RightShiftStage047dto2_uid167_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_RightShiftStage047dto2_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest(BITJOIN,168)@2
rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q <= z2_uid100_fpLogE1pxTest_q & ld_RightShiftStage047dto2_uid167_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_a_q;
--reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2(REG,353)@1
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q <= "000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q <= rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,175)@0
rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1(REG,352)@0
reg_rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q <= rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_b(DELAY,593)@1
ld_reg_rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q, xout => ld_reg_rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest(MUX,176)@2
rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s <= ld_reg_rightShiftStageSel2Dto1_uid176_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_1_q_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_b_q;
rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s, en, reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q, rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "00" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= reg_rightShiftStage0_uid166_fracXRSExt_uid36_fpLogE1pxTest_0_to_rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_2_q;
WHEN "01" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx1_uid169_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "10" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx2_uid172_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "11" => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1Idx3_uid175_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid181_fracXRSExt_uid36_fpLogE1pxTest(BITSELECT,180)@0
rightShiftStageSel0Dto0_uid181_fracXRSExt_uid36_fpLogE1pxTest_in <= shifterAddr_uid35_fpLogE1pxTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid181_fracXRSExt_uid36_fpLogE1pxTest_b <= rightShiftStageSel0Dto0_uid181_fracXRSExt_uid36_fpLogE1pxTest_in(0 downto 0);
--ld_rightShiftStageSel0Dto0_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_b(DELAY,601)@0
ld_rightShiftStageSel0Dto0_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => rightShiftStageSel0Dto0_uid181_fracXRSExt_uid36_fpLogE1pxTest_b, xout => ld_rightShiftStageSel0Dto0_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest(MUX,181)@2
rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_s <= ld_rightShiftStageSel0Dto0_uid181_fracXRSExt_uid36_fpLogE1pxTest_b_to_rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_b_q;
rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest: PROCESS (rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_s, en, rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q, rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q)
BEGIN
CASE rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_s IS
WHEN "0" => rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage1_uid177_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN "1" => rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_q <= rightShiftStage2Idx1_uid180_fracXRSExt_uid36_fpLogE1pxTest_q;
WHEN OTHERS => rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--reg_rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1(REG,355)@2
reg_rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q <= "000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q <= rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--pad_o_uid12_uid40_fpLogE1pxTest(BITJOIN,39)@2
pad_o_uid12_uid40_fpLogE1pxTest_q <= VCC_q & STD_LOGIC_VECTOR((46 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0(REG,354)@2
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q <= "000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q <= pad_o_uid12_uid40_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--oMfracXRSExt_uid40_fpLogE1pxTest(SUB,40)@3
oMfracXRSExt_uid40_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid12_uid40_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_0_q);
oMfracXRSExt_uid40_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & reg_rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_0_to_oMfracXRSExt_uid40_fpLogE1pxTest_1_q);
oMfracXRSExt_uid40_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMfracXRSExt_uid40_fpLogE1pxTest_a) - UNSIGNED(oMfracXRSExt_uid40_fpLogE1pxTest_b));
oMfracXRSExt_uid40_fpLogE1pxTest_q <= oMfracXRSExt_uid40_fpLogE1pxTest_o(48 downto 0);
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg(DELAY,835)
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 49, depth => 1 )
PORT MAP ( xin => oMfracXRSExt_uid40_fpLogE1pxTest_q, xout => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a(DELAY,441)@3
ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 49, depth => 2 )
PORT MAP ( xin => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_inputreg_q, xout => ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--redLO_uid47_fpLogE1pxTest(BITSELECT,46)@6
redLO_uid47_fpLogE1pxTest_in <= ld_oMfracXRSExt_uid40_fpLogE1pxTest_q_to_redLO_uid47_fpLogE1pxTest_a_q(46 downto 0);
redLO_uid47_fpLogE1pxTest_b <= redLO_uid47_fpLogE1pxTest_in(46 downto 0);
--oMfracXRSLZCIn_uid43_fpLogE1pxTest(BITSELECT,42)@3
oMfracXRSLZCIn_uid43_fpLogE1pxTest_in <= oMfracXRSExt_uid40_fpLogE1pxTest_q(46 downto 0);
oMfracXRSLZCIn_uid43_fpLogE1pxTest_b <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_in(46 downto 23);
--rVStage_uid185_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,184)@3
rVStage_uid185_leadingZeros_uid44_fpLogE1pxTest_in <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_b;
rVStage_uid185_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid185_leadingZeros_uid44_fpLogE1pxTest_in(23 downto 8);
--reg_rVStage_uid185_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_1(REG,356)@3
reg_rVStage_uid185_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid185_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid185_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_1_q <= rVStage_uid185_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid186_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,185)@4
vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_a <= reg_rVStage_uid185_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_1_q;
vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage0Idx2Pad16_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--ld_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_q_to_reg_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_4_a(DELAY,786)@4
ld_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_q_to_reg_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_q, xout => ld_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_q_to_reg_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_4(REG,364)@5
reg_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_4_q <= ld_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_q_to_reg_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid188_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,187)@3
vStage_uid188_leadingZeros_uid44_fpLogE1pxTest_in <= oMfracXRSLZCIn_uid43_fpLogE1pxTest_b(7 downto 0);
vStage_uid188_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid188_leadingZeros_uid44_fpLogE1pxTest_in(7 downto 0);
--mO_uid187_leadingZeros_uid44_fpLogE1pxTest(CONSTANT,186)
mO_uid187_leadingZeros_uid44_fpLogE1pxTest_q <= "11111111";
--cStage_uid189_leadingZeros_uid44_fpLogE1pxTest(BITJOIN,188)@3
cStage_uid189_leadingZeros_uid44_fpLogE1pxTest_q <= vStage_uid188_leadingZeros_uid44_fpLogE1pxTest_b & mO_uid187_leadingZeros_uid44_fpLogE1pxTest_q;
--reg_cStage_uid189_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest_3(REG,358)@3
reg_cStage_uid189_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid189_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid189_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest_3_q <= cStage_uid189_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest(MUX,190)@4
vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid185_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_1_q, reg_cStage_uid189_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid185_leadingZeros_uid44_fpLogE1pxTest_0_to_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest_q <= reg_cStage_uid189_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid193_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,192)@4
rVStage_uid193_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid193_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid193_leadingZeros_uid44_fpLogE1pxTest_in(15 downto 8);
--vCount_uid194_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,193)@4
vCount_uid194_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid193_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid194_leadingZeros_uid44_fpLogE1pxTest_b <= cstAllZWE_uid17_fpLogE1pxTest_q;
vCount_uid194_leadingZeros_uid44_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid194_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid194_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid194_leadingZeros_uid44_fpLogE1pxTest_b) THEN
vCount_uid194_leadingZeros_uid44_fpLogE1pxTest_q <= "1";
ELSE
vCount_uid194_leadingZeros_uid44_fpLogE1pxTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid194_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_d(DELAY,634)@5
ld_vCount_uid194_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid194_leadingZeros_uid44_fpLogE1pxTest_q, xout => ld_vCount_uid194_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid195_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,194)@4
vStage_uid195_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid191_leadingZeros_uid44_fpLogE1pxTest_q(7 downto 0);
vStage_uid195_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid195_leadingZeros_uid44_fpLogE1pxTest_in(7 downto 0);
--reg_vStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3(REG,360)@4
reg_vStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid195_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid193_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_2(REG,359)@4
reg_rVStage_uid193_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid193_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid193_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_2_q <= rVStage_uid193_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest(MUX,196)@5
vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid194_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid193_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_2_q, reg_vStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid193_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid195_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,198)@5
rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_in(7 downto 4);
--vCount_uid200_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,199)@5
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b <= rightShiftStage1Idx2Pad4_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_2(REG,363)@5
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_2_q <= vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid201_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,200)@5
vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid197_leadingZeros_uid44_fpLogE1pxTest_q(3 downto 0);
vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_in(3 downto 0);
--vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest(MUX,202)@5
vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s, en, rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b, vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b)
BEGIN
CASE vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= rVStage_uid199_leadingZeros_uid44_fpLogE1pxTest_b;
WHEN "1" => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= vStage_uid201_leadingZeros_uid44_fpLogE1pxTest_b;
WHEN OTHERS => vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,204)@5
rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_in(3 downto 2);
--vCount_uid206_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,205)@5
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b <= z2_uid100_fpLogE1pxTest_q;
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_b) THEN
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q <= "1";
ELSE
vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid207_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,206)@5
vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid203_leadingZeros_uid44_fpLogE1pxTest_q(1 downto 0);
vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b <= vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_in(1 downto 0);
--reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3(REG,362)@5
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q <= vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2(REG,361)@5
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q <= rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest(MUX,208)@6
vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s <= vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q;
vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest: PROCESS (vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s, en, reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q, reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= reg_rVStage_uid205_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vStage_uid207_leadingZeros_uid44_fpLogE1pxTest_0_to_vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest(BITSELECT,210)@6
rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in <= vStagei_uid209_leadingZeros_uid44_fpLogE1pxTest_q;
rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_in(1 downto 1);
--vCount_uid212_leadingZeros_uid44_fpLogE1pxTest(LOGICAL,211)@6
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a <= rVStage_uid211_leadingZeros_uid44_fpLogE1pxTest_b;
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b <= GND_q;
vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q <= "1" when vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_a = vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_b else "0";
--r_uid213_leadingZeros_uid44_fpLogE1pxTest(BITJOIN,212)@6
r_uid213_leadingZeros_uid44_fpLogE1pxTest_q <= reg_vCount_uid186_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_4_q & ld_vCount_uid194_leadingZeros_uid44_fpLogE1pxTest_q_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_d_q & reg_vCount_uid200_leadingZeros_uid44_fpLogE1pxTest_0_to_r_uid213_leadingZeros_uid44_fpLogE1pxTest_2_q & vCount_uid206_leadingZeros_uid44_fpLogE1pxTest_q & vCount_uid212_leadingZeros_uid44_fpLogE1pxTest_q;
--leftShiftStageSel4Dto3_uid225_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,224)@6
leftShiftStageSel4Dto3_uid225_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid213_leadingZeros_uid44_fpLogE1pxTest_q;
leftShiftStageSel4Dto3_uid225_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel4Dto3_uid225_fracXBranch4Ext_uid48_fpLogE1pxTest_in(4 downto 3);
--leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,225)@6
leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= leftShiftStageSel4Dto3_uid225_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, redLO_uid47_fpLogE1pxTest_b, leftShiftStage0Idx1_uid218_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage0Idx2_uid221_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage0Idx3_uid224_fracXBranch4Ext_uid48_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= redLO_uid47_fpLogE1pxTest_b;
WHEN "01" => leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx1_uid218_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx2_uid221_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage0Idx3_uid224_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage040dto0_uid234_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,233)@6
LeftShiftStage040dto0_uid234_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_q(40 downto 0);
LeftShiftStage040dto0_uid234_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage040dto0_uid234_fracXBranch4Ext_uid48_fpLogE1pxTest_in(40 downto 0);
--rightShiftStage1Idx3Pad6_uid174_fracXRSExt_uid36_fpLogE1pxTest(CONSTANT,173)
rightShiftStage1Idx3Pad6_uid174_fracXRSExt_uid36_fpLogE1pxTest_q <= "000000";
--leftShiftStage1Idx3_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,234)@6
leftShiftStage1Idx3_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage040dto0_uid234_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx3Pad6_uid174_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx3_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_5(REG,369)@6
reg_leftShiftStage1Idx3_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q <= "00000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q <= leftShiftStage1Idx3_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage042dto0_uid231_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,230)@6
LeftShiftStage042dto0_uid231_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_q(42 downto 0);
LeftShiftStage042dto0_uid231_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage042dto0_uid231_fracXBranch4Ext_uid48_fpLogE1pxTest_in(42 downto 0);
--leftShiftStage1Idx2_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,231)@6
leftShiftStage1Idx2_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage042dto0_uid231_fracXBranch4Ext_uid48_fpLogE1pxTest_b & rightShiftStage1Idx2Pad4_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx2_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_4(REG,368)@6
reg_leftShiftStage1Idx2_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q <= "00000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q <= leftShiftStage1Idx2_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage044dto0_uid228_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,227)@6
LeftShiftStage044dto0_uid228_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_q(44 downto 0);
LeftShiftStage044dto0_uid228_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= LeftShiftStage044dto0_uid228_fracXBranch4Ext_uid48_fpLogE1pxTest_in(44 downto 0);
--leftShiftStage1Idx1_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest(BITJOIN,228)@6
leftShiftStage1Idx1_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= LeftShiftStage044dto0_uid228_fracXBranch4Ext_uid48_fpLogE1pxTest_b & z2_uid100_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx1_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_3(REG,367)@6
reg_leftShiftStage1Idx1_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q <= "00000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q <= leftShiftStage1Idx1_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_2(REG,366)@6
reg_leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= "00000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q <= leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,235)@6
leftShiftStageSel2Dto1_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid213_leadingZeros_uid44_fpLogE1pxTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel2Dto1_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_1(REG,365)@6
reg_leftShiftStageSel2Dto1_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q <= leftShiftStageSel2Dto1_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,236)@7
leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= reg_leftShiftStageSel2Dto1_uid236_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_1_q;
leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, reg_leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q, reg_leftShiftStage1Idx1_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q, reg_leftShiftStage1Idx2_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q, reg_leftShiftStage1Idx3_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage0_uid226_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx1_uid229_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx2_uid232_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= reg_leftShiftStage1Idx3_uid235_fracXBranch4Ext_uid48_fpLogE1pxTest_0_to_leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest(BITSELECT,240)@6
leftShiftStageSel0Dto0_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_in <= r_uid213_leadingZeros_uid44_fpLogE1pxTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_b <= leftShiftStageSel0Dto0_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2_uid242_fracXBranch4Ext_uid48_fpLogE1pxTest_b(DELAY,663)@6
ld_leftShiftStageSel0Dto0_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2_uid242_fracXBranch4Ext_uid48_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_b, xout => ld_leftShiftStageSel0Dto0_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2_uid242_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid242_fracXBranch4Ext_uid48_fpLogE1pxTest(MUX,241)@7
leftShiftStage2_uid242_fracXBranch4Ext_uid48_fpLogE1pxTest_s <= ld_leftShiftStageSel0Dto0_uid241_fracXBranch4Ext_uid48_fpLogE1pxTest_b_to_leftShiftStage2_uid242_fracXBranch4Ext_uid48_fpLogE1pxTest_b_q;
leftShiftStage2_uid242_fracXBranch4Ext_uid48_fpLogE1pxTest: PROCESS (leftShiftStage2_uid242_fracXBranch4Ext_uid48_fpLogE1pxTest_s, en, leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_q, leftShiftStage2Idx1_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage2_uid242_fracXBranch4Ext_uid48_fpLogE1pxTest_s IS
WHEN "0" => leftShiftStage2_uid242_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage1_uid237_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN "1" => leftShiftStage2_uid242_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= leftShiftStage2Idx1_uid240_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage2_uid242_fracXBranch4Ext_uid48_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracXBranch4_uid49_fpLogE1pxTest(BITSELECT,48)@7
fracXBranch4_uid49_fpLogE1pxTest_in <= leftShiftStage2_uid242_fracXBranch4Ext_uid48_fpLogE1pxTest_q;
fracXBranch4_uid49_fpLogE1pxTest_b <= fracXBranch4_uid49_fpLogE1pxTest_in(46 downto 22);
--fracXBranch4Red_uid80_fpLogE1pxTest(BITSELECT,79)@7
fracXBranch4Red_uid80_fpLogE1pxTest_in <= fracXBranch4_uid49_fpLogE1pxTest_b(23 downto 0);
fracXBranch4Red_uid80_fpLogE1pxTest_b <= fracXBranch4Red_uid80_fpLogE1pxTest_in(23 downto 0);
--reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5(REG,372)@7
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q <= fracXBranch4Red_uid80_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_nor(LOGICAL,1061)
ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_nor_b <= ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_sticky_ena_q;
ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_nor_q <= not (ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_nor_a or ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_nor_b);
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_mem_top(CONSTANT,868)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_mem_top_q <= "010";
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_cmp(LOGICAL,869)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_cmp_a <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_mem_top_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdmux_q);
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_cmp_q <= "1" when ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_cmp_a = ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_cmp_b else "0";
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_cmpReg(REG,870)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_cmpReg_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_sticky_ena(REG,1062)
ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_nor_q = "1") THEN
ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_sticky_ena_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_enaAnd(LOGICAL,1063)
ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_enaAnd_a <= ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_sticky_ena_q;
ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_enaAnd_b <= en;
ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_enaAnd_q <= ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_enaAnd_a and ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_enaAnd_b;
--fracXRS_uid39_fpLogE1pxTest(BITSELECT,38)@2
fracXRS_uid39_fpLogE1pxTest_in <= rightShiftStage2_uid182_fracXRSExt_uid36_fpLogE1pxTest_q;
fracXRS_uid39_fpLogE1pxTest_b <= fracXRS_uid39_fpLogE1pxTest_in(47 downto 23);
--fracXRSRange_uid81_fpLogE1pxTest(BITSELECT,80)@2
fracXRSRange_uid81_fpLogE1pxTest_in <= fracXRS_uid39_fpLogE1pxTest_b(23 downto 0);
fracXRSRange_uid81_fpLogE1pxTest_b <= fracXRSRange_uid81_fpLogE1pxTest_in(23 downto 0);
--ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_inputreg(DELAY,1051)
ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => fracXRSRange_uid81_fpLogE1pxTest_b, xout => ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt(COUNTER,864)
-- every=1, low=0, high=2, step=1, init=1
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_i = 1 THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_eq = '1') THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_i <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_i - 2;
ELSE
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_i <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_i,2));
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdreg(REG,865)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdreg_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdmux(MUX,866)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdmux_s <= en;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdmux: PROCESS (ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdmux_s, ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdreg_q, ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdmux_s IS
WHEN "0" => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdmux_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdreg_q;
WHEN "1" => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdmux_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem(DUALMEM,1052)
ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_ia <= ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_inputreg_q;
ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_aa <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdreg_q;
ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_ab <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdmux_q;
ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 2,
numwords_a => 3,
width_b => 24,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_iq,
address_a => ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_aa,
data_a => ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_ia
);
ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_reset0 <= areset;
ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_q <= ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_iq(23 downto 0);
--reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4(REG,371)@7
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q <= ld_fracXRSRange_uid81_fpLogE1pxTest_b_to_reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor(LOGICAL,872)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q <= not (ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_a or ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_b);
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena(REG,873)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_nor_q = "1") THEN
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd(LOGICAL,874)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_sticky_ena_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b <= en;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_a and ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_b;
--addrMaskExt_uid50_fpLogE1pxTest(SUB,49)@0
addrMaskExt_uid50_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpLogE1pxTest_b);
addrMaskExt_uid50_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
addrMaskExt_uid50_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(addrMaskExt_uid50_fpLogE1pxTest_a) - UNSIGNED(addrMaskExt_uid50_fpLogE1pxTest_b));
addrMaskExt_uid50_fpLogE1pxTest_q <= addrMaskExt_uid50_fpLogE1pxTest_o(8 downto 0);
--addrMask_uid51_fpLogE1pxTest(BITSELECT,50)@0
addrMask_uid51_fpLogE1pxTest_in <= addrMaskExt_uid50_fpLogE1pxTest_q(4 downto 0);
addrMask_uid51_fpLogE1pxTest_b <= addrMask_uid51_fpLogE1pxTest_in(4 downto 0);
--reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0(REG,349)@0
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q <= addrMask_uid51_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--maskIncrementTable_uid52_fpLogE1pxTest(LOOKUP,51)@1
maskIncrementTable_uid52_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
maskIncrementTable_uid52_fpLogE1pxTest_q <= "100000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_addrMask_uid51_fpLogE1pxTest_0_to_maskIncrementTable_uid52_fpLogE1pxTest_0_q) IS
WHEN "00000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "100000000000000000000000";
WHEN "00001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "010000000000000000000000";
WHEN "00010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "001000000000000000000000";
WHEN "00011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000100000000000000000000";
WHEN "00100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000010000000000000000000";
WHEN "00101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000001000000000000000000";
WHEN "00110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000100000000000000000";
WHEN "00111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000010000000000000000";
WHEN "01000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000001000000000000000";
WHEN "01001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000000100000000000000";
WHEN "01010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000000010000000000000";
WHEN "01011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000000001000000000000";
WHEN "01100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000000000100000000000";
WHEN "01101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000000000010000000000";
WHEN "01110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000000000001000000000";
WHEN "01111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000000000000100000000";
WHEN "10000" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000000000000010000000";
WHEN "10001" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000000000000001000000";
WHEN "10010" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000000000000000100000";
WHEN "10011" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000000000000000010000";
WHEN "10100" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000000000000000001000";
WHEN "10101" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000000000000000000100";
WHEN "10110" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000000000000000000010";
WHEN "10111" => maskIncrementTable_uid52_fpLogE1pxTest_q <= "000000000000000000000001";
WHEN OTHERS =>
maskIncrementTable_uid52_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0(REG,350)@1
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q <= oFracX_uid32_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--oPlusOFracX_uid53_fpLogE1pxTest(ADD,52)@2
oPlusOFracX_uid53_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_oFracX_uid32_fpLogE1pxTest_0_to_oPlusOFracX_uid53_fpLogE1pxTest_0_q);
oPlusOFracX_uid53_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0" & maskIncrementTable_uid52_fpLogE1pxTest_q);
oPlusOFracX_uid53_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oPlusOFracX_uid53_fpLogE1pxTest_a) + UNSIGNED(oPlusOFracX_uid53_fpLogE1pxTest_b));
oPlusOFracX_uid53_fpLogE1pxTest_q <= oPlusOFracX_uid53_fpLogE1pxTest_o(24 downto 0);
--oPlusOFracXNormHigh_uid59_fpLogE1pxTest(BITSELECT,58)@2
oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q(23 downto 0);
oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b <= oPlusOFracXNormHigh_uid59_fpLogE1pxTest_in(23 downto 0);
--oPlusOFracXNormLow_uid57_fpLogE1pxTest(BITSELECT,56)@2
oPlusOFracXNormLow_uid57_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q(22 downto 0);
oPlusOFracXNormLow_uid57_fpLogE1pxTest_b <= oPlusOFracXNormLow_uid57_fpLogE1pxTest_in(22 downto 0);
--join_uid58_fpLogE1pxTest(BITJOIN,57)@2
join_uid58_fpLogE1pxTest_q <= oPlusOFracXNormLow_uid57_fpLogE1pxTest_b & GND_q;
--msbUoPlusOFracX_uid54_fpLogE1pxTest(BITSELECT,53)@2
msbUoPlusOFracX_uid54_fpLogE1pxTest_in <= oPlusOFracX_uid53_fpLogE1pxTest_q;
msbUoPlusOFracX_uid54_fpLogE1pxTest_b <= msbUoPlusOFracX_uid54_fpLogE1pxTest_in(24 downto 24);
--oPlusOFracXNorm_uid61_fpLogE1pxTest(MUX,60)@2
oPlusOFracXNorm_uid61_fpLogE1pxTest_s <= msbUoPlusOFracX_uid54_fpLogE1pxTest_b;
oPlusOFracXNorm_uid61_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE oPlusOFracXNorm_uid61_fpLogE1pxTest_s IS
WHEN "0" => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= join_uid58_fpLogE1pxTest_q;
WHEN "1" => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= oPlusOFracXNormHigh_uid59_fpLogE1pxTest_b;
WHEN OTHERS => oPlusOFracXNorm_uid61_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg(DELAY,862)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => oPlusOFracXNorm_uid61_fpLogE1pxTest_q, xout => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem(DUALMEM,863)
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_inputreg_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdreg_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_rdmux_q;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 2,
numwords_a => 3,
width_b => 24,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_ia
);
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_iq(23 downto 0);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor(LOGICAL,859)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_b);
--ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_mem_top(CONSTANT,842)
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_mem_top_q <= "011";
--ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_cmp(LOGICAL,843)
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_cmp_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_mem_top_q;
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdmux_q);
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_cmp_q <= "1" when ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_cmp_a = ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_cmp_b else "0";
--ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_cmpReg(REG,844)
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_cmpReg_q <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena(REG,860)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd(LOGICAL,861)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_b;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg(DELAY,849)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => frac_uid22_fpLogE1pxTest_b, xout => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdcnt(COUNTER,838)
-- every=1, low=0, high=3, step=1, init=1
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdcnt_i <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdcnt_i,2));
--ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdreg(REG,839)
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdreg_q <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdmux(MUX,840)
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdmux_s <= en;
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdmux: PROCESS (ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdmux_s, ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdreg_q, ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdcnt_q)
BEGIN
CASE ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdmux_s IS
WHEN "0" => ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdmux_q <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdreg_q;
WHEN "1" => ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdmux_q <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem(DUALMEM,850)
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdmux_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 2,
numwords_a => 4,
width_b => 23,
widthad_b => 2,
numwords_b => 4,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_iq(22 downto 0);
--fracXz_uid82_fpLogE1pxTest(BITJOIN,81)@7
fracXz_uid82_fpLogE1pxTest_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_replace_mem_q & GND_q;
--reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2(REG,370)@7
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q <= fracXz_uid82_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--branch11_uid64_fpLogE1pxTest(LOGICAL,63)@0
branch11_uid64_fpLogE1pxTest_a <= signX_uid7_fpLogE1pxTest_b;
branch11_uid64_fpLogE1pxTest_q <= not branch11_uid64_fpLogE1pxTest_a;
--branch3_uid73_fpLogE1pxTest(LOGICAL,72)@0
branch3_uid73_fpLogE1pxTest_a <= branch22_uid66_fpLogE1pxTest_c;
branch3_uid73_fpLogE1pxTest_b <= InvResIsX_uid72_fpLogE1pxTest_q;
branch3_uid73_fpLogE1pxTest_c <= branch11_uid64_fpLogE1pxTest_q;
branch3_uid73_fpLogE1pxTest_q <= branch3_uid73_fpLogE1pxTest_a and branch3_uid73_fpLogE1pxTest_b and branch3_uid73_fpLogE1pxTest_c;
--cstBiasPWFP1_uid13_fpLogE1pxTest(CONSTANT,12)
cstBiasPWFP1_uid13_fpLogE1pxTest_q <= "10010111";
--branch12_uid63_fpLogE1pxTest(COMPARE,62)@0
branch12_uid63_fpLogE1pxTest_cin <= GND_q;
branch12_uid63_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpLogE1pxTest_b) & '0';
branch12_uid63_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBiasPWFP1_uid13_fpLogE1pxTest_q) & branch12_uid63_fpLogE1pxTest_cin(0);
branch12_uid63_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(branch12_uid63_fpLogE1pxTest_a) - UNSIGNED(branch12_uid63_fpLogE1pxTest_b));
branch12_uid63_fpLogE1pxTest_c(0) <= branch12_uid63_fpLogE1pxTest_o(10);
branch12_uid63_fpLogE1pxTest_n(0) <= not branch12_uid63_fpLogE1pxTest_o(10);
--branch2_uid69_fpLogE1pxTest(LOGICAL,68)@0
branch2_uid69_fpLogE1pxTest_a <= branch11_uid64_fpLogE1pxTest_q;
branch2_uid69_fpLogE1pxTest_b <= branch12_uid63_fpLogE1pxTest_c;
branch2_uid69_fpLogE1pxTest_c <= branch22_uid66_fpLogE1pxTest_n;
branch2_uid69_fpLogE1pxTest_q <= branch2_uid69_fpLogE1pxTest_a and branch2_uid69_fpLogE1pxTest_b and branch2_uid69_fpLogE1pxTest_c;
--branch1_uid65_fpLogE1pxTest(LOGICAL,64)@0
branch1_uid65_fpLogE1pxTest_a <= branch11_uid64_fpLogE1pxTest_q;
branch1_uid65_fpLogE1pxTest_b <= branch12_uid63_fpLogE1pxTest_n;
branch1_uid65_fpLogE1pxTest_q <= branch1_uid65_fpLogE1pxTest_a and branch1_uid65_fpLogE1pxTest_b;
--concBranch_uid76_fpLogE1pxTest(BITJOIN,75)@0
concBranch_uid76_fpLogE1pxTest_q <= branch4_uid75_fpLogE1pxTest_q & branch3_uid73_fpLogE1pxTest_q & branch2_uid69_fpLogE1pxTest_q & branch1_uid65_fpLogE1pxTest_q;
--reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0(REG,348)@0
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q <= concBranch_uid76_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a(DELAY,477)@1
ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 4, depth => 5 )
PORT MAP ( xin => reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q, xout => ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--branEnc_uid77_fpLogE1pxTest(LOOKUP,76)@6
branEnc_uid77_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
branEnc_uid77_fpLogE1pxTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (ld_reg_concBranch_uid76_fpLogE1pxTest_0_to_branEnc_uid77_fpLogE1pxTest_0_q_to_branEnc_uid77_fpLogE1pxTest_a_q) IS
WHEN "0000" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0001" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0010" => branEnc_uid77_fpLogE1pxTest_q <= "01";
WHEN "0011" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0100" => branEnc_uid77_fpLogE1pxTest_q <= "10";
WHEN "0101" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0110" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "0111" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1000" => branEnc_uid77_fpLogE1pxTest_q <= "11";
WHEN "1001" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1010" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1011" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1100" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1101" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1110" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN "1111" => branEnc_uid77_fpLogE1pxTest_q <= "00";
WHEN OTHERS =>
branEnc_uid77_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b(DELAY,485)@7
ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => branEnc_uid77_fpLogE1pxTest_q, xout => ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracB_uid83_fpLogE1pxTest(MUX,82)@8
fracB_uid83_fpLogE1pxTest_s <= ld_branEnc_uid77_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_b_q;
fracB_uid83_fpLogE1pxTest: PROCESS (fracB_uid83_fpLogE1pxTest_s, en, reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q, ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q, reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q, reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q)
BEGIN
CASE fracB_uid83_fpLogE1pxTest_s IS
WHEN "00" => fracB_uid83_fpLogE1pxTest_q <= reg_fracXz_uid82_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_2_q;
WHEN "01" => fracB_uid83_fpLogE1pxTest_q <= ld_oPlusOFracXNorm_uid61_fpLogE1pxTest_q_to_fracB_uid83_fpLogE1pxTest_d_replace_mem_q;
WHEN "10" => fracB_uid83_fpLogE1pxTest_q <= reg_fracXRSRange_uid81_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_4_q;
WHEN "11" => fracB_uid83_fpLogE1pxTest_q <= reg_fracXBranch4Red_uid80_fpLogE1pxTest_0_to_fracB_uid83_fpLogE1pxTest_5_q;
WHEN OTHERS => fracB_uid83_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--zAddrLow_uid89_fpLogE1pxTest(BITSELECT,88)@8
zAddrLow_uid89_fpLogE1pxTest_in <= fracB_uid83_fpLogE1pxTest_q;
zAddrLow_uid89_fpLogE1pxTest_b <= zAddrLow_uid89_fpLogE1pxTest_in(23 downto 16);
--addr_uid90_fpLogE1pxTest(BITJOIN,89)@8
addr_uid90_fpLogE1pxTest_q <= reg_c_uid87_fpLogE1pxTest_0_to_addr_uid90_fpLogE1pxTest_1_q & zAddrLow_uid89_fpLogE1pxTest_b;
--reg_addr_uid90_fpLogE1pxTest_0_to_memoryC2_uid253_natLogTabGen_lutmem_0(REG,374)@8
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC2_uid253_natLogTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC2_uid253_natLogTabGen_lutmem_0_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid90_fpLogE1pxTest_0_to_memoryC2_uid253_natLogTabGen_lutmem_0_q <= addr_uid90_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid253_natLogTabGen_lutmem(DUALMEM,346)@9
memoryC2_uid253_natLogTabGen_lutmem_ia <= (others => '0');
memoryC2_uid253_natLogTabGen_lutmem_aa <= (others => '0');
memoryC2_uid253_natLogTabGen_lutmem_ab <= reg_addr_uid90_fpLogE1pxTest_0_to_memoryC2_uid253_natLogTabGen_lutmem_0_q;
memoryC2_uid253_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 9,
numwords_a => 512,
width_b => 13,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1px_s5_memoryC2_uid253_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid253_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid253_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid253_natLogTabGen_lutmem_iq,
address_a => memoryC2_uid253_natLogTabGen_lutmem_aa,
data_a => memoryC2_uid253_natLogTabGen_lutmem_ia
);
memoryC2_uid253_natLogTabGen_lutmem_reset0 <= areset;
memoryC2_uid253_natLogTabGen_lutmem_q <= memoryC2_uid253_natLogTabGen_lutmem_iq(12 downto 0);
--reg_memoryC2_uid253_natLogTabGen_lutmem_0_to_prodXY_uid339_pT1_uid255_natLogPolyEval_1(REG,376)@11
reg_memoryC2_uid253_natLogTabGen_lutmem_0_to_prodXY_uid339_pT1_uid255_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid253_natLogTabGen_lutmem_0_to_prodXY_uid339_pT1_uid255_natLogPolyEval_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid253_natLogTabGen_lutmem_0_to_prodXY_uid339_pT1_uid255_natLogPolyEval_1_q <= memoryC2_uid253_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg(DELAY,888)
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => fracB_uid83_fpLogE1pxTest_q, xout => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a(DELAY,497)@8
ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_inputreg_q, xout => ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--zPPolyEval_uid91_fpLogE1pxTest(BITSELECT,90)@11
zPPolyEval_uid91_fpLogE1pxTest_in <= ld_fracB_uid83_fpLogE1pxTest_q_to_zPPolyEval_uid91_fpLogE1pxTest_a_q(15 downto 0);
zPPolyEval_uid91_fpLogE1pxTest_b <= zPPolyEval_uid91_fpLogE1pxTest_in(15 downto 0);
--yT1_uid254_natLogPolyEval(BITSELECT,253)@11
yT1_uid254_natLogPolyEval_in <= zPPolyEval_uid91_fpLogE1pxTest_b;
yT1_uid254_natLogPolyEval_b <= yT1_uid254_natLogPolyEval_in(15 downto 3);
--reg_yT1_uid254_natLogPolyEval_0_to_prodXY_uid339_pT1_uid255_natLogPolyEval_0(REG,375)@11
reg_yT1_uid254_natLogPolyEval_0_to_prodXY_uid339_pT1_uid255_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid254_natLogPolyEval_0_to_prodXY_uid339_pT1_uid255_natLogPolyEval_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid254_natLogPolyEval_0_to_prodXY_uid339_pT1_uid255_natLogPolyEval_0_q <= yT1_uid254_natLogPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid339_pT1_uid255_natLogPolyEval(MULT,338)@12
prodXY_uid339_pT1_uid255_natLogPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid339_pT1_uid255_natLogPolyEval_a),14)) * SIGNED(prodXY_uid339_pT1_uid255_natLogPolyEval_b);
prodXY_uid339_pT1_uid255_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid339_pT1_uid255_natLogPolyEval_a <= (others => '0');
prodXY_uid339_pT1_uid255_natLogPolyEval_b <= (others => '0');
prodXY_uid339_pT1_uid255_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid339_pT1_uid255_natLogPolyEval_a <= reg_yT1_uid254_natLogPolyEval_0_to_prodXY_uid339_pT1_uid255_natLogPolyEval_0_q;
prodXY_uid339_pT1_uid255_natLogPolyEval_b <= reg_memoryC2_uid253_natLogTabGen_lutmem_0_to_prodXY_uid339_pT1_uid255_natLogPolyEval_1_q;
prodXY_uid339_pT1_uid255_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid339_pT1_uid255_natLogPolyEval_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid339_pT1_uid255_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid339_pT1_uid255_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid339_pT1_uid255_natLogPolyEval_q <= prodXY_uid339_pT1_uid255_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid340_pT1_uid255_natLogPolyEval(BITSELECT,339)@15
prodXYTruncFR_uid340_pT1_uid255_natLogPolyEval_in <= prodXY_uid339_pT1_uid255_natLogPolyEval_q;
prodXYTruncFR_uid340_pT1_uid255_natLogPolyEval_b <= prodXYTruncFR_uid340_pT1_uid255_natLogPolyEval_in(25 downto 12);
--highBBits_uid257_natLogPolyEval(BITSELECT,256)@15
highBBits_uid257_natLogPolyEval_in <= prodXYTruncFR_uid340_pT1_uid255_natLogPolyEval_b;
highBBits_uid257_natLogPolyEval_b <= highBBits_uid257_natLogPolyEval_in(13 downto 1);
--ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC1_uid252_natLogTabGen_lutmem_0_q_to_memoryC1_uid252_natLogTabGen_lutmem_a(DELAY,767)@9
ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC1_uid252_natLogTabGen_lutmem_0_q_to_memoryC1_uid252_natLogTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 9, depth => 3 )
PORT MAP ( xin => reg_addr_uid90_fpLogE1pxTest_0_to_memoryC2_uid253_natLogTabGen_lutmem_0_q, xout => ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC1_uid252_natLogTabGen_lutmem_0_q_to_memoryC1_uid252_natLogTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid252_natLogTabGen_lutmem(DUALMEM,345)@12
memoryC1_uid252_natLogTabGen_lutmem_ia <= (others => '0');
memoryC1_uid252_natLogTabGen_lutmem_aa <= (others => '0');
memoryC1_uid252_natLogTabGen_lutmem_ab <= ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC1_uid252_natLogTabGen_lutmem_0_q_to_memoryC1_uid252_natLogTabGen_lutmem_a_q;
memoryC1_uid252_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 9,
numwords_a => 512,
width_b => 21,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1px_s5_memoryC1_uid252_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid252_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid252_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid252_natLogTabGen_lutmem_iq,
address_a => memoryC1_uid252_natLogTabGen_lutmem_aa,
data_a => memoryC1_uid252_natLogTabGen_lutmem_ia
);
memoryC1_uid252_natLogTabGen_lutmem_reset0 <= areset;
memoryC1_uid252_natLogTabGen_lutmem_q <= memoryC1_uid252_natLogTabGen_lutmem_iq(20 downto 0);
--reg_memoryC1_uid252_natLogTabGen_lutmem_0_to_sumAHighB_uid258_natLogPolyEval_0(REG,378)@14
reg_memoryC1_uid252_natLogTabGen_lutmem_0_to_sumAHighB_uid258_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid252_natLogTabGen_lutmem_0_to_sumAHighB_uid258_natLogPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid252_natLogTabGen_lutmem_0_to_sumAHighB_uid258_natLogPolyEval_0_q <= memoryC1_uid252_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid258_natLogPolyEval(ADD,257)@15
sumAHighB_uid258_natLogPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid252_natLogTabGen_lutmem_0_to_sumAHighB_uid258_natLogPolyEval_0_q(20)) & reg_memoryC1_uid252_natLogTabGen_lutmem_0_to_sumAHighB_uid258_natLogPolyEval_0_q);
sumAHighB_uid258_natLogPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid257_natLogPolyEval_b(12)) & highBBits_uid257_natLogPolyEval_b);
sumAHighB_uid258_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid258_natLogPolyEval_a) + SIGNED(sumAHighB_uid258_natLogPolyEval_b));
sumAHighB_uid258_natLogPolyEval_q <= sumAHighB_uid258_natLogPolyEval_o(21 downto 0);
--lowRangeB_uid256_natLogPolyEval(BITSELECT,255)@15
lowRangeB_uid256_natLogPolyEval_in <= prodXYTruncFR_uid340_pT1_uid255_natLogPolyEval_b(0 downto 0);
lowRangeB_uid256_natLogPolyEval_b <= lowRangeB_uid256_natLogPolyEval_in(0 downto 0);
--s1_uid256_uid259_natLogPolyEval(BITJOIN,258)@15
s1_uid256_uid259_natLogPolyEval_q <= sumAHighB_uid258_natLogPolyEval_q & lowRangeB_uid256_natLogPolyEval_b;
--reg_s1_uid256_uid259_natLogPolyEval_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_1(REG,380)@15
reg_s1_uid256_uid259_natLogPolyEval_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid256_uid259_natLogPolyEval_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid256_uid259_natLogPolyEval_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_1_q <= s1_uid256_uid259_natLogPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_nor(LOGICAL,1072)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_nor_b <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_nor_q <= not (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_nor_a or ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_nor_b);
--ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_cmpReg(REG,987)
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_sticky_ena(REG,1073)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_nor_q = "1") THEN
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_sticky_ena_q <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_enaAnd(LOGICAL,1074)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_enaAnd_a <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_sticky_ena_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_enaAnd_b <= en;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_enaAnd_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_enaAnd_a and ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_enaAnd_b;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_inputreg(DELAY,1064)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => zPPolyEval_uid91_fpLogE1pxTest_b, xout => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdcnt(COUNTER,983)
-- every=1, low=0, high=1, step=1, init=1
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdcnt_i <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdcnt_i,1));
--ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdreg(REG,984)
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdreg_q <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdmux(MUX,985)
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdmux_s <= en;
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdmux: PROCESS (ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdmux_s, ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdreg_q, ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdcnt_q)
BEGIN
CASE ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdmux_s IS
WHEN "0" => ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdmux_q <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdreg_q;
WHEN "1" => ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdmux_q <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem(DUALMEM,1065)
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_ia <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_inputreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_aa <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdreg_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_ab <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdmux_q;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 1,
numwords_a => 2,
width_b => 16,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_ia
);
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_iq(15 downto 0);
--reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0(REG,379)@15
reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_q <= ld_zPPolyEval_uid91_fpLogE1pxTest_b_to_reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid342_pT2_uid261_natLogPolyEval(MULT,341)@16
prodXY_uid342_pT2_uid261_natLogPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid342_pT2_uid261_natLogPolyEval_a),17)) * SIGNED(prodXY_uid342_pT2_uid261_natLogPolyEval_b);
prodXY_uid342_pT2_uid261_natLogPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid342_pT2_uid261_natLogPolyEval_a <= (others => '0');
prodXY_uid342_pT2_uid261_natLogPolyEval_b <= (others => '0');
prodXY_uid342_pT2_uid261_natLogPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid342_pT2_uid261_natLogPolyEval_a <= reg_zPPolyEval_uid91_fpLogE1pxTest_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_0_q;
prodXY_uid342_pT2_uid261_natLogPolyEval_b <= reg_s1_uid256_uid259_natLogPolyEval_0_to_prodXY_uid342_pT2_uid261_natLogPolyEval_1_q;
prodXY_uid342_pT2_uid261_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid342_pT2_uid261_natLogPolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid342_pT2_uid261_natLogPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid342_pT2_uid261_natLogPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid342_pT2_uid261_natLogPolyEval_q <= prodXY_uid342_pT2_uid261_natLogPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid343_pT2_uid261_natLogPolyEval(BITSELECT,342)@19
prodXYTruncFR_uid343_pT2_uid261_natLogPolyEval_in <= prodXY_uid342_pT2_uid261_natLogPolyEval_q;
prodXYTruncFR_uid343_pT2_uid261_natLogPolyEval_b <= prodXYTruncFR_uid343_pT2_uid261_natLogPolyEval_in(38 downto 15);
--highBBits_uid263_natLogPolyEval(BITSELECT,262)@19
highBBits_uid263_natLogPolyEval_in <= prodXYTruncFR_uid343_pT2_uid261_natLogPolyEval_b;
highBBits_uid263_natLogPolyEval_b <= highBBits_uid263_natLogPolyEval_in(23 downto 2);
--ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_nor(LOGICAL,1035)
ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_nor_b <= ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_sticky_ena_q;
ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_nor_q <= not (ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_nor_a or ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_nor_b);
--ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_sticky_ena(REG,1036)
ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_nor_q = "1") THEN
ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_enaAnd(LOGICAL,1037)
ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_enaAnd_a <= ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_sticky_ena_q;
ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_enaAnd_b <= en;
ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_enaAnd_q <= ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_enaAnd_a and ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_enaAnd_b;
--ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_inputreg(DELAY,1025)
ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_inputreg : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => reg_addr_uid90_fpLogE1pxTest_0_to_memoryC2_uid253_natLogTabGen_lutmem_0_q, xout => ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem(DUALMEM,1026)
ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_ia <= ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_inputreg_q;
ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdreg_q;
ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdmux_q;
ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 9,
widthad_a => 3,
numwords_a => 5,
width_b => 9,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_iq,
address_a => ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_aa,
data_a => ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_ia
);
ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_q <= ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_iq(8 downto 0);
--memoryC0_uid251_natLogTabGen_lutmem(DUALMEM,344)@16
memoryC0_uid251_natLogTabGen_lutmem_ia <= (others => '0');
memoryC0_uid251_natLogTabGen_lutmem_aa <= (others => '0');
memoryC0_uid251_natLogTabGen_lutmem_ab <= ld_reg_addr_uid90_fpLogE1pxTest_0_to_memoryC0_uid251_natLogTabGen_lutmem_0_q_to_memoryC0_uid251_natLogTabGen_lutmem_a_replace_mem_q;
memoryC0_uid251_natLogTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 31,
widthad_a => 9,
numwords_a => 512,
width_b => 31,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_ln1px_s5_memoryC0_uid251_natLogTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid251_natLogTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid251_natLogTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid251_natLogTabGen_lutmem_iq,
address_a => memoryC0_uid251_natLogTabGen_lutmem_aa,
data_a => memoryC0_uid251_natLogTabGen_lutmem_ia
);
memoryC0_uid251_natLogTabGen_lutmem_reset0 <= areset;
memoryC0_uid251_natLogTabGen_lutmem_q <= memoryC0_uid251_natLogTabGen_lutmem_iq(30 downto 0);
--reg_memoryC0_uid251_natLogTabGen_lutmem_0_to_sumAHighB_uid264_natLogPolyEval_0(REG,382)@18
reg_memoryC0_uid251_natLogTabGen_lutmem_0_to_sumAHighB_uid264_natLogPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid251_natLogTabGen_lutmem_0_to_sumAHighB_uid264_natLogPolyEval_0_q <= "0000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid251_natLogTabGen_lutmem_0_to_sumAHighB_uid264_natLogPolyEval_0_q <= memoryC0_uid251_natLogTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid264_natLogPolyEval(ADD,263)@19
sumAHighB_uid264_natLogPolyEval_a <= STD_LOGIC_VECTOR((31 downto 31 => reg_memoryC0_uid251_natLogTabGen_lutmem_0_to_sumAHighB_uid264_natLogPolyEval_0_q(30)) & reg_memoryC0_uid251_natLogTabGen_lutmem_0_to_sumAHighB_uid264_natLogPolyEval_0_q);
sumAHighB_uid264_natLogPolyEval_b <= STD_LOGIC_VECTOR((31 downto 22 => highBBits_uid263_natLogPolyEval_b(21)) & highBBits_uid263_natLogPolyEval_b);
sumAHighB_uid264_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid264_natLogPolyEval_a) + SIGNED(sumAHighB_uid264_natLogPolyEval_b));
sumAHighB_uid264_natLogPolyEval_q <= sumAHighB_uid264_natLogPolyEval_o(31 downto 0);
--lowRangeB_uid262_natLogPolyEval(BITSELECT,261)@19
lowRangeB_uid262_natLogPolyEval_in <= prodXYTruncFR_uid343_pT2_uid261_natLogPolyEval_b(1 downto 0);
lowRangeB_uid262_natLogPolyEval_b <= lowRangeB_uid262_natLogPolyEval_in(1 downto 0);
--s2_uid262_uid265_natLogPolyEval(BITJOIN,264)@19
s2_uid262_uid265_natLogPolyEval_q <= sumAHighB_uid264_natLogPolyEval_q & lowRangeB_uid262_natLogPolyEval_b;
--peOR_uid93_fpLogE1pxTest(BITSELECT,92)@19
peOR_uid93_fpLogE1pxTest_in <= s2_uid262_uid265_natLogPolyEval_q(32 downto 0);
peOR_uid93_fpLogE1pxTest_b <= peOR_uid93_fpLogE1pxTest_in(32 downto 6);
--reg_peOR_uid93_fpLogE1pxTest_0_to_postPEMul_uid103_fpLogE1pxTest_1(REG,383)@19
reg_peOR_uid93_fpLogE1pxTest_0_to_postPEMul_uid103_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_peOR_uid93_fpLogE1pxTest_0_to_postPEMul_uid103_fpLogE1pxTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_peOR_uid93_fpLogE1pxTest_0_to_postPEMul_uid103_fpLogE1pxTest_1_q <= peOR_uid93_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_nor(LOGICAL,912)
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_nor_b <= ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_sticky_ena_q;
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_nor_q <= not (ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_nor_a or ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_nor_b);
--ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_mem_top(CONSTANT,908)
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_mem_top_q <= "01000";
--ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_cmp(LOGICAL,909)
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_cmp_a <= ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_mem_top_q;
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdmux_q);
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_cmp_q <= "1" when ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_cmp_a = ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_cmp_b else "0";
--ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_cmpReg(REG,910)
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_cmpReg_q <= ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_sticky_ena(REG,913)
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_nor_q = "1") THEN
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_sticky_ena_q <= ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_enaAnd(LOGICAL,914)
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_enaAnd_a <= ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_sticky_ena_q;
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_enaAnd_b <= en;
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_enaAnd_q <= ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_enaAnd_a and ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_enaAnd_b;
--o2_uid97_fpLogE1pxTest(CONSTANT,96)
o2_uid97_fpLogE1pxTest_q <= "01";
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor(LOGICAL,899)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_b);
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena(REG,900)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd(LOGICAL,901)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_b;
--ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem(DUALMEM,890)
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_rdmux_q;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 3,
numwords_a => 5,
width_b => 23,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_iq(22 downto 0);
--sEz_uid98_fpLogE1pxTest(BITJOIN,97)@8
sEz_uid98_fpLogE1pxTest_q <= o2_uid97_fpLogE1pxTest_q & ld_frac_uid22_fpLogE1pxTest_b_to_sEz_uid98_fpLogE1pxTest_a_replace_mem_q;
--fracBRed_uid99_fpLogE1pxTest(BITSELECT,98)@8
fracBRed_uid99_fpLogE1pxTest_in <= fracB_uid83_fpLogE1pxTest_q;
fracBRed_uid99_fpLogE1pxTest_b <= fracBRed_uid99_fpLogE1pxTest_in(23 downto 1);
--sEz_uid101_fpLogE1pxTest(BITJOIN,100)@8
sEz_uid101_fpLogE1pxTest_q <= z2_uid100_fpLogE1pxTest_q & fracBRed_uid99_fpLogE1pxTest_b;
--ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a(DELAY,499)@0
ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 7 )
PORT MAP ( xin => branch3_uid73_fpLogE1pxTest_q, xout => ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--branch3OrC_uid94_fpLogE1pxTest(LOGICAL,93)@7
branch3OrC_uid94_fpLogE1pxTest_a <= ld_branch3_uid73_fpLogE1pxTest_q_to_branch3OrC_uid94_fpLogE1pxTest_a_q;
branch3OrC_uid94_fpLogE1pxTest_b <= c_uid87_fpLogE1pxTest_q;
branch3OrC_uid94_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
branch3OrC_uid94_fpLogE1pxTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
branch3OrC_uid94_fpLogE1pxTest_q <= branch3OrC_uid94_fpLogE1pxTest_a or branch3OrC_uid94_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--sEz_uid102_fpLogE1pxTest(MUX,101)@8
sEz_uid102_fpLogE1pxTest_s <= branch3OrC_uid94_fpLogE1pxTest_q;
sEz_uid102_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
sEz_uid102_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE sEz_uid102_fpLogE1pxTest_s IS
WHEN "0" => sEz_uid102_fpLogE1pxTest_q <= sEz_uid101_fpLogE1pxTest_q;
WHEN "1" => sEz_uid102_fpLogE1pxTest_q <= sEz_uid98_fpLogE1pxTest_q;
WHEN OTHERS => sEz_uid102_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_inputreg(DELAY,902)
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 25, depth => 1 )
PORT MAP ( xin => sEz_uid102_fpLogE1pxTest_q, xout => ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt(COUNTER,904)
-- every=1, low=0, high=8, step=1, init=1
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_i = 7 THEN
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_i <= ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_i - 8;
ELSE
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_i <= ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_i,4));
--ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdreg(REG,905)
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdreg_q <= ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdmux(MUX,906)
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdmux_s, ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdreg_q, ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdmux_q <= ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdmux_q <= ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem(DUALMEM,903)
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_ia <= ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_inputreg_q;
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_aa <= ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdreg_q;
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_ab <= ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_rdmux_q;
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 25,
widthad_a => 4,
numwords_a => 9,
width_b => 25,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_ia
);
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_q <= ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_iq(24 downto 0);
--postPEMul_uid103_fpLogE1pxTest(MULT,102)@20
postPEMul_uid103_fpLogE1pxTest_pr <= SIGNED(postPEMul_uid103_fpLogE1pxTest_a) * SIGNED(postPEMul_uid103_fpLogE1pxTest_b);
postPEMul_uid103_fpLogE1pxTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_a <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_b <= (others => '0');
postPEMul_uid103_fpLogE1pxTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_a <= ld_sEz_uid102_fpLogE1pxTest_q_to_postPEMul_uid103_fpLogE1pxTest_a_replace_mem_q;
postPEMul_uid103_fpLogE1pxTest_b <= reg_peOR_uid93_fpLogE1pxTest_0_to_postPEMul_uid103_fpLogE1pxTest_1_q;
postPEMul_uid103_fpLogE1pxTest_s1 <= STD_LOGIC_VECTOR(postPEMul_uid103_fpLogE1pxTest_pr);
END IF;
END IF;
END PROCESS;
postPEMul_uid103_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
postPEMul_uid103_fpLogE1pxTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
postPEMul_uid103_fpLogE1pxTest_q <= postPEMul_uid103_fpLogE1pxTest_s1;
END IF;
END IF;
END PROCESS;
--highBBits_uid107_fpLogE1pxTest(BITSELECT,106)@23
highBBits_uid107_fpLogE1pxTest_in <= postPEMul_uid103_fpLogE1pxTest_q;
highBBits_uid107_fpLogE1pxTest_b <= highBBits_uid107_fpLogE1pxTest_in(51 downto 22);
--wideZero_uid104_fpLogE1pxTest(CONSTANT,103)
wideZero_uid104_fpLogE1pxTest_q <= "00000000000000000000000000000000000";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor(LOGICAL,885)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q <= not (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_a or ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_b);
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top(CONSTANT,881)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q <= "01001";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp(LOGICAL,882)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_mem_top_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q <= "1" when ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_a = ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_b else "0";
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg(REG,883)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena(REG,886)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_nor_q = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd(LOGICAL,887)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_sticky_ena_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b <= en;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_a and ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_b;
--expBran3PreExt_uid45_fpLogE1pxTest(SUB,44)@6
expBran3PreExt_uid45_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstBiasMO_uid10_fpLogE1pxTest_q);
expBran3PreExt_uid45_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0000" & r_uid213_leadingZeros_uid44_fpLogE1pxTest_q);
expBran3PreExt_uid45_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expBran3PreExt_uid45_fpLogE1pxTest_a) - UNSIGNED(expBran3PreExt_uid45_fpLogE1pxTest_b));
expBran3PreExt_uid45_fpLogE1pxTest_q <= expBran3PreExt_uid45_fpLogE1pxTest_o(8 downto 0);
--expBran3Pre_uid46_fpLogE1pxTest(BITSELECT,45)@6
expBran3Pre_uid46_fpLogE1pxTest_in <= expBran3PreExt_uid45_fpLogE1pxTest_q(7 downto 0);
expBran3Pre_uid46_fpLogE1pxTest_b <= expBran3Pre_uid46_fpLogE1pxTest_in(7 downto 0);
--reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5(REG,387)@6
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q <= expBran3Pre_uid46_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_1(REG,385)@2
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_1_q <= msbUoPlusOFracX_uid54_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0(REG,384)@0
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q <= expX_uid6_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_a(DELAY,449)@1
ld_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 8, depth => 2 )
PORT MAP ( xin => reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q, xout => ld_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--eUpdateOPOFracX_uid55_fpLogE1pxTest(ADD,54)@3
eUpdateOPOFracX_uid55_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & ld_reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_a_q);
eUpdateOPOFracX_uid55_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00000000" & reg_msbUoPlusOFracX_uid54_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_1_q);
eUpdateOPOFracX_uid55_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
eUpdateOPOFracX_uid55_fpLogE1pxTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
eUpdateOPOFracX_uid55_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(eUpdateOPOFracX_uid55_fpLogE1pxTest_a) + UNSIGNED(eUpdateOPOFracX_uid55_fpLogE1pxTest_b));
END IF;
END IF;
END PROCESS;
eUpdateOPOFracX_uid55_fpLogE1pxTest_q <= eUpdateOPOFracX_uid55_fpLogE1pxTest_o(8 downto 0);
--ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d(DELAY,480)@4
ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d : dspba_delay
GENERIC MAP ( width => 9, depth => 3 )
PORT MAP ( xin => eUpdateOPOFracX_uid55_fpLogE1pxTest_q, xout => ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_nor(LOGICAL,846)
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_nor_b <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_sticky_ena_q;
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_nor_q <= not (ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_nor_a or ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_nor_b);
--ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_sticky_ena(REG,847)
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_nor_q = "1") THEN
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_sticky_ena_q <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_enaAnd(LOGICAL,848)
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_enaAnd_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_sticky_ena_q;
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_enaAnd_b <= en;
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_enaAnd_q <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_enaAnd_a and ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_enaAnd_b;
--ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_inputreg(DELAY,836)
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_expX_uid6_fpLogE1pxTest_0_to_eUpdateOPOFracX_uid55_fpLogE1pxTest_0_q, xout => ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem(DUALMEM,837)
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_ia <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_inputreg_q;
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_aa <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdreg_q;
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_ab <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_rdmux_q;
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 2,
numwords_a => 4,
width_b => 8,
widthad_b => 2,
numwords_b => 4,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_iq,
address_a => ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_aa,
data_a => ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_ia
);
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_reset0 <= areset;
ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_q <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_iq(7 downto 0);
--expB_uid79_fpLogE1pxTest(MUX,78)@7
expB_uid79_fpLogE1pxTest_s <= branEnc_uid77_fpLogE1pxTest_q;
expB_uid79_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expB_uid79_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expB_uid79_fpLogE1pxTest_s IS
WHEN "00" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_replace_mem_q);
WHEN "01" => expB_uid79_fpLogE1pxTest_q <= ld_eUpdateOPOFracX_uid55_fpLogE1pxTest_q_to_expB_uid79_fpLogE1pxTest_d_q;
WHEN "10" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogE1pxTest_q);
WHEN "11" => expB_uid79_fpLogE1pxTest_q <= STD_LOGIC_VECTOR("0" & reg_expBran3Pre_uid46_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_5_q);
WHEN OTHERS => expB_uid79_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg(DELAY,875)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => expB_uid79_fpLogE1pxTest_q, xout => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt(COUNTER,877)
-- every=1, low=0, high=9, step=1, init=1
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i = 8 THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_eq = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i - 9;
ELSE
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_i,4));
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg(REG,878)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux(MUX,879)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s <= en;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux: PROCESS (ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s, ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q, ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_s IS
WHEN "0" => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q;
WHEN "1" => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem(DUALMEM,876)
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_inputreg_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdreg_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_rdmux_q;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 9,
widthad_a => 4,
numwords_a => 10,
width_b => 9,
widthad_b => 4,
numwords_b => 10,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq,
address_a => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_aa,
data_a => ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_ia
);
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_reset0 <= areset;
ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q <= ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_iq(8 downto 0);
--e_uid84_fpLogE1pxTest(SUB,83)@20
e_uid84_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & ld_expB_uid79_fpLogE1pxTest_q_to_e_uid84_fpLogE1pxTest_a_replace_mem_q);
e_uid84_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid9_fpLogE1pxTest_q);
e_uid84_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(e_uid84_fpLogE1pxTest_a) - UNSIGNED(e_uid84_fpLogE1pxTest_b));
e_uid84_fpLogE1pxTest_q <= e_uid84_fpLogE1pxTest_o(9 downto 0);
--xv0_uid244_constMult(BITSELECT,243)@20
xv0_uid244_constMult_in <= e_uid84_fpLogE1pxTest_q(5 downto 0);
xv0_uid244_constMult_b <= xv0_uid244_constMult_in(5 downto 0);
--reg_xv0_uid244_constMult_0_to_p0_uid247_constMult_0(REG,389)@20
reg_xv0_uid244_constMult_0_to_p0_uid247_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv0_uid244_constMult_0_to_p0_uid247_constMult_0_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv0_uid244_constMult_0_to_p0_uid247_constMult_0_q <= xv0_uid244_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_reg_xv0_uid244_constMult_0_to_p0_uid247_constMult_0_q_to_p0_uid247_constMult_a(DELAY,669)@21
ld_reg_xv0_uid244_constMult_0_to_p0_uid247_constMult_0_q_to_p0_uid247_constMult_a : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => reg_xv0_uid244_constMult_0_to_p0_uid247_constMult_0_q, xout => ld_reg_xv0_uid244_constMult_0_to_p0_uid247_constMult_0_q_to_p0_uid247_constMult_a_q, ena => en(0), clk => clk, aclr => areset );
--p0_uid247_constMult(LOOKUP,246)@22
p0_uid247_constMult: PROCESS (ld_reg_xv0_uid244_constMult_0_to_p0_uid247_constMult_0_q_to_p0_uid247_constMult_a_q)
BEGIN
-- Begin reserved scope level
CASE (ld_reg_xv0_uid244_constMult_0_to_p0_uid247_constMult_0_q_to_p0_uid247_constMult_a_q) IS
WHEN "000000" => p0_uid247_constMult_q <= "0000000000000000000000000000000000";
WHEN "000001" => p0_uid247_constMult_q <= "0000001011000101110010000110000000";
WHEN "000010" => p0_uid247_constMult_q <= "0000010110001011100100001100000000";
WHEN "000011" => p0_uid247_constMult_q <= "0000100001010001010110010010000000";
WHEN "000100" => p0_uid247_constMult_q <= "0000101100010111001000011000000000";
WHEN "000101" => p0_uid247_constMult_q <= "0000110111011100111010011110000000";
WHEN "000110" => p0_uid247_constMult_q <= "0001000010100010101100100100000000";
WHEN "000111" => p0_uid247_constMult_q <= "0001001101101000011110101010000000";
WHEN "001000" => p0_uid247_constMult_q <= "0001011000101110010000110000000000";
WHEN "001001" => p0_uid247_constMult_q <= "0001100011110100000010110110000000";
WHEN "001010" => p0_uid247_constMult_q <= "0001101110111001110100111100000000";
WHEN "001011" => p0_uid247_constMult_q <= "0001111001111111100111000010000000";
WHEN "001100" => p0_uid247_constMult_q <= "0010000101000101011001001000000000";
WHEN "001101" => p0_uid247_constMult_q <= "0010010000001011001011001110000000";
WHEN "001110" => p0_uid247_constMult_q <= "0010011011010000111101010100000000";
WHEN "001111" => p0_uid247_constMult_q <= "0010100110010110101111011010000000";
WHEN "010000" => p0_uid247_constMult_q <= "0010110001011100100001100000000000";
WHEN "010001" => p0_uid247_constMult_q <= "0010111100100010010011100110000000";
WHEN "010010" => p0_uid247_constMult_q <= "0011000111101000000101101100000000";
WHEN "010011" => p0_uid247_constMult_q <= "0011010010101101110111110010000000";
WHEN "010100" => p0_uid247_constMult_q <= "0011011101110011101001111000000000";
WHEN "010101" => p0_uid247_constMult_q <= "0011101000111001011011111110000000";
WHEN "010110" => p0_uid247_constMult_q <= "0011110011111111001110000100000000";
WHEN "010111" => p0_uid247_constMult_q <= "0011111111000101000000001010000000";
WHEN "011000" => p0_uid247_constMult_q <= "0100001010001010110010010000000000";
WHEN "011001" => p0_uid247_constMult_q <= "0100010101010000100100010110000000";
WHEN "011010" => p0_uid247_constMult_q <= "0100100000010110010110011100000000";
WHEN "011011" => p0_uid247_constMult_q <= "0100101011011100001000100010000000";
WHEN "011100" => p0_uid247_constMult_q <= "0100110110100001111010101000000000";
WHEN "011101" => p0_uid247_constMult_q <= "0101000001100111101100101110000000";
WHEN "011110" => p0_uid247_constMult_q <= "0101001100101101011110110100000000";
WHEN "011111" => p0_uid247_constMult_q <= "0101010111110011010000111010000000";
WHEN "100000" => p0_uid247_constMult_q <= "0101100010111001000011000000000000";
WHEN "100001" => p0_uid247_constMult_q <= "0101101101111110110101000110000000";
WHEN "100010" => p0_uid247_constMult_q <= "0101111001000100100111001100000000";
WHEN "100011" => p0_uid247_constMult_q <= "0110000100001010011001010010000000";
WHEN "100100" => p0_uid247_constMult_q <= "0110001111010000001011011000000000";
WHEN "100101" => p0_uid247_constMult_q <= "0110011010010101111101011110000000";
WHEN "100110" => p0_uid247_constMult_q <= "0110100101011011101111100100000000";
WHEN "100111" => p0_uid247_constMult_q <= "0110110000100001100001101010000000";
WHEN "101000" => p0_uid247_constMult_q <= "0110111011100111010011110000000000";
WHEN "101001" => p0_uid247_constMult_q <= "0111000110101101000101110110000000";
WHEN "101010" => p0_uid247_constMult_q <= "0111010001110010110111111100000000";
WHEN "101011" => p0_uid247_constMult_q <= "0111011100111000101010000010000000";
WHEN "101100" => p0_uid247_constMult_q <= "0111100111111110011100001000000000";
WHEN "101101" => p0_uid247_constMult_q <= "0111110011000100001110001110000000";
WHEN "101110" => p0_uid247_constMult_q <= "0111111110001010000000010100000000";
WHEN "101111" => p0_uid247_constMult_q <= "1000001001001111110010011010000000";
WHEN "110000" => p0_uid247_constMult_q <= "1000010100010101100100100000000000";
WHEN "110001" => p0_uid247_constMult_q <= "1000011111011011010110100110000000";
WHEN "110010" => p0_uid247_constMult_q <= "1000101010100001001000101100000000";
WHEN "110011" => p0_uid247_constMult_q <= "1000110101100110111010110010000000";
WHEN "110100" => p0_uid247_constMult_q <= "1001000000101100101100111000000000";
WHEN "110101" => p0_uid247_constMult_q <= "1001001011110010011110111110000000";
WHEN "110110" => p0_uid247_constMult_q <= "1001010110111000010001000100000000";
WHEN "110111" => p0_uid247_constMult_q <= "1001100001111110000011001010000000";
WHEN "111000" => p0_uid247_constMult_q <= "1001101101000011110101010000000000";
WHEN "111001" => p0_uid247_constMult_q <= "1001111000001001100111010110000000";
WHEN "111010" => p0_uid247_constMult_q <= "1010000011001111011001011100000000";
WHEN "111011" => p0_uid247_constMult_q <= "1010001110010101001011100010000000";
WHEN "111100" => p0_uid247_constMult_q <= "1010011001011010111101101000000000";
WHEN "111101" => p0_uid247_constMult_q <= "1010100100100000101111101110000000";
WHEN "111110" => p0_uid247_constMult_q <= "1010101111100110100001110100000000";
WHEN "111111" => p0_uid247_constMult_q <= "1010111010101100010011111010000000";
WHEN OTHERS =>
p0_uid247_constMult_q <= "0000000000000000000000000000000000";
END CASE;
-- End reserved scope level
END PROCESS;
--xv1_uid245_constMult(BITSELECT,244)@20
xv1_uid245_constMult_in <= e_uid84_fpLogE1pxTest_q(8 downto 0);
xv1_uid245_constMult_b <= xv1_uid245_constMult_in(8 downto 6);
--reg_xv1_uid245_constMult_0_to_p1_uid246_constMult_0(REG,388)@20
reg_xv1_uid245_constMult_0_to_p1_uid246_constMult_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xv1_uid245_constMult_0_to_p1_uid246_constMult_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xv1_uid245_constMult_0_to_p1_uid246_constMult_0_q <= xv1_uid245_constMult_b;
END IF;
END IF;
END PROCESS;
--p1_uid246_constMult(LOOKUP,245)@21
p1_uid246_constMult: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p1_uid246_constMult_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_xv1_uid245_constMult_0_to_p1_uid246_constMult_0_q) IS
WHEN "000" => p1_uid246_constMult_q <= "0000000000000000000000000000000000000";
WHEN "001" => p1_uid246_constMult_q <= "0001011000101110010000110000000000000";
WHEN "010" => p1_uid246_constMult_q <= "0010110001011100100001100000000000000";
WHEN "011" => p1_uid246_constMult_q <= "0100001010001010110010010000000000000";
WHEN "100" => p1_uid246_constMult_q <= "1010011101000110111101000000000000000";
WHEN "101" => p1_uid246_constMult_q <= "1011110101110101001101110000000000000";
WHEN "110" => p1_uid246_constMult_q <= "1101001110100011011110100000000000000";
WHEN "111" => p1_uid246_constMult_q <= "1110100111010001101111010000000000000";
WHEN OTHERS =>
p1_uid246_constMult_q <= "0000000000000000000000000000000000000";
END CASE;
END IF;
END IF;
END PROCESS;
--lev1_a0_uid248_constMult(ADD,247)@22
lev1_a0_uid248_constMult_a <= STD_LOGIC_VECTOR((38 downto 37 => p1_uid246_constMult_q(36)) & p1_uid246_constMult_q);
lev1_a0_uid248_constMult_b <= STD_LOGIC_VECTOR('0' & "0000" & p0_uid247_constMult_q);
lev1_a0_uid248_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev1_a0_uid248_constMult_a) + SIGNED(lev1_a0_uid248_constMult_b));
lev1_a0_uid248_constMult_q <= lev1_a0_uid248_constMult_o(37 downto 0);
--sR_uid249_constMult(BITSELECT,248)@22
sR_uid249_constMult_in <= lev1_a0_uid248_constMult_q(36 downto 0);
sR_uid249_constMult_b <= sR_uid249_constMult_in(36 downto 2);
--reg_sR_uid249_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2(REG,390)@22
reg_sR_uid249_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sR_uid249_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sR_uid249_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q <= sR_uid249_constMult_b;
END IF;
END IF;
END PROCESS;
--ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b(DELAY,509)@8
ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => branch3OrC_uid94_fpLogE1pxTest_q, xout => ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--addTermOne_uid105_fpLogE1pxTest(MUX,104)@23
addTermOne_uid105_fpLogE1pxTest_s <= ld_branch3OrC_uid94_fpLogE1pxTest_q_to_addTermOne_uid105_fpLogE1pxTest_b_q;
addTermOne_uid105_fpLogE1pxTest: PROCESS (addTermOne_uid105_fpLogE1pxTest_s, en, reg_sR_uid249_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q, wideZero_uid104_fpLogE1pxTest_q)
BEGIN
CASE addTermOne_uid105_fpLogE1pxTest_s IS
WHEN "0" => addTermOne_uid105_fpLogE1pxTest_q <= reg_sR_uid249_constMult_0_to_addTermOne_uid105_fpLogE1pxTest_2_q;
WHEN "1" => addTermOne_uid105_fpLogE1pxTest_q <= wideZero_uid104_fpLogE1pxTest_q;
WHEN OTHERS => addTermOne_uid105_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--sumAHighB_uid108_fpLogE1pxTest(ADD,107)@23
sumAHighB_uid108_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((35 downto 35 => addTermOne_uid105_fpLogE1pxTest_q(34)) & addTermOne_uid105_fpLogE1pxTest_q);
sumAHighB_uid108_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((35 downto 30 => highBBits_uid107_fpLogE1pxTest_b(29)) & highBBits_uid107_fpLogE1pxTest_b);
sumAHighB_uid108_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid108_fpLogE1pxTest_a) + SIGNED(sumAHighB_uid108_fpLogE1pxTest_b));
sumAHighB_uid108_fpLogE1pxTest_q <= sumAHighB_uid108_fpLogE1pxTest_o(35 downto 0);
--lowRangeB_uid106_fpLogE1pxTest(BITSELECT,105)@23
lowRangeB_uid106_fpLogE1pxTest_in <= postPEMul_uid103_fpLogE1pxTest_q(21 downto 0);
lowRangeB_uid106_fpLogE1pxTest_b <= lowRangeB_uid106_fpLogE1pxTest_in(21 downto 0);
--finalSum_uid106_uid109_fpLogE1pxTest(BITJOIN,108)@23
finalSum_uid106_uid109_fpLogE1pxTest_q <= sumAHighB_uid108_fpLogE1pxTest_q & lowRangeB_uid106_fpLogE1pxTest_b;
--FullSumAB57_uid110_fpLogE1pxTest(BITSELECT,109)@23
FullSumAB57_uid110_fpLogE1pxTest_in <= finalSum_uid106_uid109_fpLogE1pxTest_q;
FullSumAB57_uid110_fpLogE1pxTest_b <= FullSumAB57_uid110_fpLogE1pxTest_in(57 downto 57);
--ld_FullSumAB57_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b(DELAY,521)@23
ld_FullSumAB57_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => FullSumAB57_uid110_fpLogE1pxTest_b, xout => ld_FullSumAB57_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalSumOneComp_uid112_fpLogE1pxTest(LOGICAL,111)@23
finalSumOneComp_uid112_fpLogE1pxTest_a <= finalSum_uid106_uid109_fpLogE1pxTest_q;
finalSumOneComp_uid112_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((57 downto 1 => FullSumAB57_uid110_fpLogE1pxTest_b(0)) & FullSumAB57_uid110_fpLogE1pxTest_b);
finalSumOneComp_uid112_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
finalSumOneComp_uid112_fpLogE1pxTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
finalSumOneComp_uid112_fpLogE1pxTest_q <= finalSumOneComp_uid112_fpLogE1pxTest_a xor finalSumOneComp_uid112_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--finalSumAbs_uid113_fpLogE1pxTest(ADD,112)@24
finalSumAbs_uid113_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((58 downto 58 => finalSumOneComp_uid112_fpLogE1pxTest_q(57)) & finalSumOneComp_uid112_fpLogE1pxTest_q);
finalSumAbs_uid113_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((58 downto 1 => ld_FullSumAB57_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q(0)) & ld_FullSumAB57_uid110_fpLogE1pxTest_b_to_finalSumAbs_uid113_fpLogE1pxTest_b_q);
finalSumAbs_uid113_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(finalSumAbs_uid113_fpLogE1pxTest_a) + SIGNED(finalSumAbs_uid113_fpLogE1pxTest_b));
finalSumAbs_uid113_fpLogE1pxTest_q <= finalSumAbs_uid113_fpLogE1pxTest_o(58 downto 0);
--rVStage_uid268_countZ_uid114_fpLogE1pxTest(BITSELECT,267)@24
rVStage_uid268_countZ_uid114_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q;
rVStage_uid268_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid268_countZ_uid114_fpLogE1pxTest_in(58 downto 27);
--reg_rVStage_uid268_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid269_countZ_uid114_fpLogE1pxTest_1(REG,391)@24
reg_rVStage_uid268_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid269_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid268_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid269_countZ_uid114_fpLogE1pxTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid268_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid269_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid268_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid269_countZ_uid114_fpLogE1pxTest(LOGICAL,268)@25
vCount_uid269_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid268_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid269_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid269_countZ_uid114_fpLogE1pxTest_b <= zs_uid267_countZ_uid114_fpLogE1pxTest_q;
vCount_uid269_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid269_countZ_uid114_fpLogE1pxTest_a = vCount_uid269_countZ_uid114_fpLogE1pxTest_b else "0";
--reg_vCount_uid269_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_5(REG,401)@25
reg_vCount_uid269_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid269_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid269_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_5_q <= vCount_uid269_countZ_uid114_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid269_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_5_q_to_r_uid302_countZ_uid114_fpLogE1pxTest_f(DELAY,724)@26
ld_reg_vCount_uid269_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_5_q_to_r_uid302_countZ_uid114_fpLogE1pxTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => reg_vCount_uid269_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_5_q, xout => ld_reg_vCount_uid269_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_5_q_to_r_uid302_countZ_uid114_fpLogE1pxTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid271_countZ_uid114_fpLogE1pxTest(BITSELECT,270)@24
vStage_uid271_countZ_uid114_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(26 downto 0);
vStage_uid271_countZ_uid114_fpLogE1pxTest_b <= vStage_uid271_countZ_uid114_fpLogE1pxTest_in(26 downto 0);
--ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid272_countZ_uid114_fpLogE1pxTest_b(DELAY,689)@24
ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid272_countZ_uid114_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => vStage_uid271_countZ_uid114_fpLogE1pxTest_b, xout => ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid272_countZ_uid114_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid270_countZ_uid114_fpLogE1pxTest(CONSTANT,269)
mO_uid270_countZ_uid114_fpLogE1pxTest_q <= "11111";
--cStage_uid272_countZ_uid114_fpLogE1pxTest(BITJOIN,271)@25
cStage_uid272_countZ_uid114_fpLogE1pxTest_q <= ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid272_countZ_uid114_fpLogE1pxTest_b_q & mO_uid270_countZ_uid114_fpLogE1pxTest_q;
--ld_rVStage_uid268_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid274_countZ_uid114_fpLogE1pxTest_c(DELAY,691)@24
ld_rVStage_uid268_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid274_countZ_uid114_fpLogE1pxTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid268_countZ_uid114_fpLogE1pxTest_b, xout => ld_rVStage_uid268_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid274_countZ_uid114_fpLogE1pxTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid274_countZ_uid114_fpLogE1pxTest(MUX,273)@25
vStagei_uid274_countZ_uid114_fpLogE1pxTest_s <= vCount_uid269_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid274_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid274_countZ_uid114_fpLogE1pxTest_s, en, ld_rVStage_uid268_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid274_countZ_uid114_fpLogE1pxTest_c_q, cStage_uid272_countZ_uid114_fpLogE1pxTest_q)
BEGIN
CASE vStagei_uid274_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid274_countZ_uid114_fpLogE1pxTest_q <= ld_rVStage_uid268_countZ_uid114_fpLogE1pxTest_b_to_vStagei_uid274_countZ_uid114_fpLogE1pxTest_c_q;
WHEN "1" => vStagei_uid274_countZ_uid114_fpLogE1pxTest_q <= cStage_uid272_countZ_uid114_fpLogE1pxTest_q;
WHEN OTHERS => vStagei_uid274_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid276_countZ_uid114_fpLogE1pxTest(BITSELECT,275)@25
rVStage_uid276_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid274_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid276_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid276_countZ_uid114_fpLogE1pxTest_in(31 downto 16);
--reg_rVStage_uid276_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid277_countZ_uid114_fpLogE1pxTest_1(REG,392)@25
reg_rVStage_uid276_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid277_countZ_uid114_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid276_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid277_countZ_uid114_fpLogE1pxTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid276_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid277_countZ_uid114_fpLogE1pxTest_1_q <= rVStage_uid276_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid277_countZ_uid114_fpLogE1pxTest(LOGICAL,276)@26
vCount_uid277_countZ_uid114_fpLogE1pxTest_a <= reg_rVStage_uid276_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid277_countZ_uid114_fpLogE1pxTest_1_q;
vCount_uid277_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage0Idx2Pad16_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid277_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid277_countZ_uid114_fpLogE1pxTest_a = vCount_uid277_countZ_uid114_fpLogE1pxTest_b else "0";
--ld_vCount_uid277_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid277_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_4_a(DELAY,822)@26
ld_vCount_uid277_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid277_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid277_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid277_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid277_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid277_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_4(REG,400)@27
reg_vCount_uid277_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid277_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid277_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_4_q <= ld_vCount_uid277_countZ_uid114_fpLogE1pxTest_q_to_reg_vCount_uid277_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid278_countZ_uid114_fpLogE1pxTest(BITSELECT,277)@25
vStage_uid278_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid274_countZ_uid114_fpLogE1pxTest_q(15 downto 0);
vStage_uid278_countZ_uid114_fpLogE1pxTest_b <= vStage_uid278_countZ_uid114_fpLogE1pxTest_in(15 downto 0);
--reg_vStage_uid278_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid280_countZ_uid114_fpLogE1pxTest_3(REG,394)@25
reg_vStage_uid278_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid280_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid278_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid280_countZ_uid114_fpLogE1pxTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid278_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid280_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid278_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid280_countZ_uid114_fpLogE1pxTest(MUX,279)@26
vStagei_uid280_countZ_uid114_fpLogE1pxTest_s <= vCount_uid277_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid280_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid280_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid276_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid277_countZ_uid114_fpLogE1pxTest_1_q, reg_vStage_uid278_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid280_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid280_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid280_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid276_countZ_uid114_fpLogE1pxTest_0_to_vCount_uid277_countZ_uid114_fpLogE1pxTest_1_q;
WHEN "1" => vStagei_uid280_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid278_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid280_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid280_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid282_countZ_uid114_fpLogE1pxTest(BITSELECT,281)@26
rVStage_uid282_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid280_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid282_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid282_countZ_uid114_fpLogE1pxTest_in(15 downto 8);
--vCount_uid283_countZ_uid114_fpLogE1pxTest(LOGICAL,282)@26
vCount_uid283_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid282_countZ_uid114_fpLogE1pxTest_b;
vCount_uid283_countZ_uid114_fpLogE1pxTest_b <= cstAllZWE_uid17_fpLogE1pxTest_q;
vCount_uid283_countZ_uid114_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid283_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid283_countZ_uid114_fpLogE1pxTest_a = vCount_uid283_countZ_uid114_fpLogE1pxTest_b) THEN
vCount_uid283_countZ_uid114_fpLogE1pxTest_q <= "1";
ELSE
vCount_uid283_countZ_uid114_fpLogE1pxTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid283_countZ_uid114_fpLogE1pxTest_q_to_r_uid302_countZ_uid114_fpLogE1pxTest_d(DELAY,722)@27
ld_vCount_uid283_countZ_uid114_fpLogE1pxTest_q_to_r_uid302_countZ_uid114_fpLogE1pxTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid283_countZ_uid114_fpLogE1pxTest_q, xout => ld_vCount_uid283_countZ_uid114_fpLogE1pxTest_q_to_r_uid302_countZ_uid114_fpLogE1pxTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid284_countZ_uid114_fpLogE1pxTest(BITSELECT,283)@26
vStage_uid284_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid280_countZ_uid114_fpLogE1pxTest_q(7 downto 0);
vStage_uid284_countZ_uid114_fpLogE1pxTest_b <= vStage_uid284_countZ_uid114_fpLogE1pxTest_in(7 downto 0);
--reg_vStage_uid284_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid286_countZ_uid114_fpLogE1pxTest_3(REG,396)@26
reg_vStage_uid284_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid286_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid284_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid286_countZ_uid114_fpLogE1pxTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid284_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid286_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid284_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid282_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid286_countZ_uid114_fpLogE1pxTest_2(REG,395)@26
reg_rVStage_uid282_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid286_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid282_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid286_countZ_uid114_fpLogE1pxTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid282_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid286_countZ_uid114_fpLogE1pxTest_2_q <= rVStage_uid282_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid286_countZ_uid114_fpLogE1pxTest(MUX,285)@27
vStagei_uid286_countZ_uid114_fpLogE1pxTest_s <= vCount_uid283_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid286_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid286_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid282_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid286_countZ_uid114_fpLogE1pxTest_2_q, reg_vStage_uid284_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid286_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid286_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid286_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid282_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid286_countZ_uid114_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid286_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid284_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid286_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid286_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid288_countZ_uid114_fpLogE1pxTest(BITSELECT,287)@27
rVStage_uid288_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid286_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid288_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid288_countZ_uid114_fpLogE1pxTest_in(7 downto 4);
--vCount_uid289_countZ_uid114_fpLogE1pxTest(LOGICAL,288)@27
vCount_uid289_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid288_countZ_uid114_fpLogE1pxTest_b;
vCount_uid289_countZ_uid114_fpLogE1pxTest_b <= rightShiftStage1Idx2Pad4_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
vCount_uid289_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid289_countZ_uid114_fpLogE1pxTest_a = vCount_uid289_countZ_uid114_fpLogE1pxTest_b else "0";
--reg_vCount_uid289_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_2(REG,399)@27
reg_vCount_uid289_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid289_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid289_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_2_q <= vCount_uid289_countZ_uid114_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid290_countZ_uid114_fpLogE1pxTest(BITSELECT,289)@27
vStage_uid290_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid286_countZ_uid114_fpLogE1pxTest_q(3 downto 0);
vStage_uid290_countZ_uid114_fpLogE1pxTest_b <= vStage_uid290_countZ_uid114_fpLogE1pxTest_in(3 downto 0);
--vStagei_uid292_countZ_uid114_fpLogE1pxTest(MUX,291)@27
vStagei_uid292_countZ_uid114_fpLogE1pxTest_s <= vCount_uid289_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid292_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid292_countZ_uid114_fpLogE1pxTest_s, en, rVStage_uid288_countZ_uid114_fpLogE1pxTest_b, vStage_uid290_countZ_uid114_fpLogE1pxTest_b)
BEGIN
CASE vStagei_uid292_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid292_countZ_uid114_fpLogE1pxTest_q <= rVStage_uid288_countZ_uid114_fpLogE1pxTest_b;
WHEN "1" => vStagei_uid292_countZ_uid114_fpLogE1pxTest_q <= vStage_uid290_countZ_uid114_fpLogE1pxTest_b;
WHEN OTHERS => vStagei_uid292_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid294_countZ_uid114_fpLogE1pxTest(BITSELECT,293)@27
rVStage_uid294_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid292_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid294_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid294_countZ_uid114_fpLogE1pxTest_in(3 downto 2);
--vCount_uid295_countZ_uid114_fpLogE1pxTest(LOGICAL,294)@27
vCount_uid295_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid294_countZ_uid114_fpLogE1pxTest_b;
vCount_uid295_countZ_uid114_fpLogE1pxTest_b <= z2_uid100_fpLogE1pxTest_q;
vCount_uid295_countZ_uid114_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid295_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid295_countZ_uid114_fpLogE1pxTest_a = vCount_uid295_countZ_uid114_fpLogE1pxTest_b) THEN
vCount_uid295_countZ_uid114_fpLogE1pxTest_q <= "1";
ELSE
vCount_uid295_countZ_uid114_fpLogE1pxTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid296_countZ_uid114_fpLogE1pxTest(BITSELECT,295)@27
vStage_uid296_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid292_countZ_uid114_fpLogE1pxTest_q(1 downto 0);
vStage_uid296_countZ_uid114_fpLogE1pxTest_b <= vStage_uid296_countZ_uid114_fpLogE1pxTest_in(1 downto 0);
--reg_vStage_uid296_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid298_countZ_uid114_fpLogE1pxTest_3(REG,398)@27
reg_vStage_uid296_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid298_countZ_uid114_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid296_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid298_countZ_uid114_fpLogE1pxTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid296_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid298_countZ_uid114_fpLogE1pxTest_3_q <= vStage_uid296_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid294_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid298_countZ_uid114_fpLogE1pxTest_2(REG,397)@27
reg_rVStage_uid294_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid298_countZ_uid114_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid294_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid298_countZ_uid114_fpLogE1pxTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid294_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid298_countZ_uid114_fpLogE1pxTest_2_q <= rVStage_uid294_countZ_uid114_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid298_countZ_uid114_fpLogE1pxTest(MUX,297)@28
vStagei_uid298_countZ_uid114_fpLogE1pxTest_s <= vCount_uid295_countZ_uid114_fpLogE1pxTest_q;
vStagei_uid298_countZ_uid114_fpLogE1pxTest: PROCESS (vStagei_uid298_countZ_uid114_fpLogE1pxTest_s, en, reg_rVStage_uid294_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid298_countZ_uid114_fpLogE1pxTest_2_q, reg_vStage_uid296_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid298_countZ_uid114_fpLogE1pxTest_3_q)
BEGIN
CASE vStagei_uid298_countZ_uid114_fpLogE1pxTest_s IS
WHEN "0" => vStagei_uid298_countZ_uid114_fpLogE1pxTest_q <= reg_rVStage_uid294_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid298_countZ_uid114_fpLogE1pxTest_2_q;
WHEN "1" => vStagei_uid298_countZ_uid114_fpLogE1pxTest_q <= reg_vStage_uid296_countZ_uid114_fpLogE1pxTest_0_to_vStagei_uid298_countZ_uid114_fpLogE1pxTest_3_q;
WHEN OTHERS => vStagei_uid298_countZ_uid114_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid300_countZ_uid114_fpLogE1pxTest(BITSELECT,299)@28
rVStage_uid300_countZ_uid114_fpLogE1pxTest_in <= vStagei_uid298_countZ_uid114_fpLogE1pxTest_q;
rVStage_uid300_countZ_uid114_fpLogE1pxTest_b <= rVStage_uid300_countZ_uid114_fpLogE1pxTest_in(1 downto 1);
--vCount_uid301_countZ_uid114_fpLogE1pxTest(LOGICAL,300)@28
vCount_uid301_countZ_uid114_fpLogE1pxTest_a <= rVStage_uid300_countZ_uid114_fpLogE1pxTest_b;
vCount_uid301_countZ_uid114_fpLogE1pxTest_b <= GND_q;
vCount_uid301_countZ_uid114_fpLogE1pxTest_q <= "1" when vCount_uid301_countZ_uid114_fpLogE1pxTest_a = vCount_uid301_countZ_uid114_fpLogE1pxTest_b else "0";
--r_uid302_countZ_uid114_fpLogE1pxTest(BITJOIN,301)@28
r_uid302_countZ_uid114_fpLogE1pxTest_q <= ld_reg_vCount_uid269_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_5_q_to_r_uid302_countZ_uid114_fpLogE1pxTest_f_q & reg_vCount_uid277_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_4_q & ld_vCount_uid283_countZ_uid114_fpLogE1pxTest_q_to_r_uid302_countZ_uid114_fpLogE1pxTest_d_q & reg_vCount_uid289_countZ_uid114_fpLogE1pxTest_0_to_r_uid302_countZ_uid114_fpLogE1pxTest_2_q & vCount_uid295_countZ_uid114_fpLogE1pxTest_q & vCount_uid301_countZ_uid114_fpLogE1pxTest_q;
--cstMSBFinalSumPBias_uid116_fpLogE1pxTest(CONSTANT,115)
cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q <= "010001001";
--expRExt0_uid117_fpLogE1pxTest(SUB,116)@28
expRExt0_uid117_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & cstMSBFinalSumPBias_uid116_fpLogE1pxTest_q);
expRExt0_uid117_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0000" & r_uid302_countZ_uid114_fpLogE1pxTest_q);
expRExt0_uid117_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt0_uid117_fpLogE1pxTest_a) - UNSIGNED(expRExt0_uid117_fpLogE1pxTest_b));
expRExt0_uid117_fpLogE1pxTest_q <= expRExt0_uid117_fpLogE1pxTest_o(9 downto 0);
--reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0(REG,411)@28
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q <= "0000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q <= expRExt0_uid117_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--expRExt1_uid119_fpLogE1pxTest(SUB,118)@29
expRExt1_uid119_fpLogE1pxTest_a <= STD_LOGIC_VECTOR((10 downto 10 => reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q(9)) & reg_expRExt0_uid117_fpLogE1pxTest_0_to_expRExt1_uid119_fpLogE1pxTest_0_q);
expRExt1_uid119_fpLogE1pxTest_b <= STD_LOGIC_VECTOR((10 downto 6 => ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q(5)) & ld_branch4ExpCorrection_uid118_fpLogE1pxTest_q_to_expRExt1_uid119_fpLogE1pxTest_b_replace_mem_q);
expRExt1_uid119_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(SIGNED(expRExt1_uid119_fpLogE1pxTest_a) - SIGNED(expRExt1_uid119_fpLogE1pxTest_b));
expRExt1_uid119_fpLogE1pxTest_q <= expRExt1_uid119_fpLogE1pxTest_o(10 downto 0);
--expRExt1Red_uid120_fpLogE1pxTest(BITSELECT,119)@29
expRExt1Red_uid120_fpLogE1pxTest_in <= expRExt1_uid119_fpLogE1pxTest_q(9 downto 0);
expRExt1Red_uid120_fpLogE1pxTest_b <= expRExt1Red_uid120_fpLogE1pxTest_in(9 downto 0);
--ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c(DELAY,529)@28
ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c : dspba_delay
GENERIC MAP ( width => 10, depth => 1 )
PORT MAP ( xin => expRExt0_uid117_fpLogE1pxTest_q, xout => ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_inputreg(DELAY,928)
ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => branch3OrC_uid94_fpLogE1pxTest_q, xout => ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b(DELAY,528)@8
ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 20 )
PORT MAP ( xin => ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_inputreg_q, xout => ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRExt_uid121_fpLogE1pxTest(MUX,120)@29
expRExt_uid121_fpLogE1pxTest_s <= ld_branch3OrC_uid94_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_b_q;
expRExt_uid121_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRExt_uid121_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRExt_uid121_fpLogE1pxTest_s IS
WHEN "0" => expRExt_uid121_fpLogE1pxTest_q <= ld_expRExt0_uid117_fpLogE1pxTest_q_to_expRExt_uid121_fpLogE1pxTest_c_q;
WHEN "1" => expRExt_uid121_fpLogE1pxTest_q <= expRExt1Red_uid120_fpLogE1pxTest_b;
WHEN OTHERS => expRExt_uid121_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1011)
ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1012)
ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1013)
ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--X10dto0_uid312_normVal_uid115_fpLogE1pxTest(BITSELECT,311)@24
X10dto0_uid312_normVal_uid115_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(10 downto 0);
X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b <= X10dto0_uid312_normVal_uid115_fpLogE1pxTest_in(10 downto 0);
--ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_inputreg(DELAY,1003)
ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 11, depth => 1 )
PORT MAP ( xin => X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b, xout => ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,1004)
ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_inputreg_q;
ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdreg_q;
ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdmux_q;
ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 11,
widthad_a => 1,
numwords_a => 2,
width_b => 11,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(10 downto 0);
--leftShiftStage0Idx3Pad48_uid311_normVal_uid115_fpLogE1pxTest(CONSTANT,310)
leftShiftStage0Idx3Pad48_uid311_normVal_uid115_fpLogE1pxTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest(BITJOIN,312)@28
leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_q <= ld_X10dto0_uid312_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & leftShiftStage0Idx3Pad48_uid311_normVal_uid115_fpLogE1pxTest_q;
--ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,1000)
ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,1001)
ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,1002)
ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,993)
ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_cStage_uid272_countZ_uid114_fpLogE1pxTest_b_q;
ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdreg_q;
ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdmux_q;
ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 27,
widthad_a => 1,
numwords_a => 2,
width_b => 27,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(26 downto 0);
--leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest(BITJOIN,309)@28
leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_q <= ld_vStage_uid271_countZ_uid114_fpLogE1pxTest_b_to_leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & zs_uid267_countZ_uid114_fpLogE1pxTest_q;
--ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_nor(LOGICAL,989)
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_nor_b <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_nor_q <= not (ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_nor_a or ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_nor_b);
--ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_sticky_ena(REG,990)
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_nor_q = "1") THEN
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_enaAnd(LOGICAL,991)
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_enaAnd_a <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_sticky_ena_q;
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_enaAnd_b <= en;
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_enaAnd_q <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_enaAnd_a and ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_enaAnd_b;
--X42dto0_uid306_normVal_uid115_fpLogE1pxTest(BITSELECT,305)@24
X42dto0_uid306_normVal_uid115_fpLogE1pxTest_in <= finalSumAbs_uid113_fpLogE1pxTest_q(42 downto 0);
X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b <= X42dto0_uid306_normVal_uid115_fpLogE1pxTest_in(42 downto 0);
--ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_inputreg(DELAY,981)
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 43, depth => 1 )
PORT MAP ( xin => X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b, xout => ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem(DUALMEM,982)
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_inputreg_q;
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdreg_q;
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdmux_q;
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 43,
widthad_a => 1,
numwords_a => 2,
width_b => 43,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_ia
);
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_q <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_iq(42 downto 0);
--leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest(BITJOIN,306)@28
leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_q <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_mem_q & rightShiftStage0Idx2Pad16_uid160_fracXRSExt_uid36_fpLogE1pxTest_q;
--ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_nor(LOGICAL,1022)
ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_nor_b <= ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q;
ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_nor_q <= not (ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_nor_a or ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_nor_b);
--ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_sticky_ena(REG,1023)
ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_nor_q = "1") THEN
ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_enaAnd(LOGICAL,1024)
ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_enaAnd_a <= ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_sticky_ena_q;
ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_enaAnd_b <= en;
ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_enaAnd_q <= ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_enaAnd_a and ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_enaAnd_b;
--ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_inputreg(DELAY,1014)
ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => finalSumAbs_uid113_fpLogE1pxTest_q, xout => ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem(DUALMEM,1015)
ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia <= ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_inputreg_q;
ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdreg_q;
ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab <= ld_X42dto0_uid306_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_b_replace_rdmux_q;
ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 59,
widthad_a => 1,
numwords_a => 2,
width_b => 59,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq,
address_a => ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_aa,
data_a => ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_ia
);
ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_reset0 <= areset;
ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_q <= ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_iq(58 downto 0);
--leftShiftStageSel5Dto4_uid314_normVal_uid115_fpLogE1pxTest(BITSELECT,313)@28
leftShiftStageSel5Dto4_uid314_normVal_uid115_fpLogE1pxTest_in <= r_uid302_countZ_uid114_fpLogE1pxTest_q;
leftShiftStageSel5Dto4_uid314_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel5Dto4_uid314_normVal_uid115_fpLogE1pxTest_in(5 downto 4);
--leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest(MUX,314)@28
leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_s <= leftShiftStageSel5Dto4_uid314_normVal_uid115_fpLogE1pxTest_b;
leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_s, en, ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_q, leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_q, leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_q, leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_q <= ld_finalSumAbs_uid113_fpLogE1pxTest_q_to_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage0Idx1_uid307_normVal_uid115_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage0Idx2_uid310_normVal_uid115_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage0Idx3_uid313_normVal_uid115_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage046dto0_uid323_normVal_uid115_fpLogE1pxTest(BITSELECT,322)@28
LeftShiftStage046dto0_uid323_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_q(46 downto 0);
LeftShiftStage046dto0_uid323_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage046dto0_uid323_normVal_uid115_fpLogE1pxTest_in(46 downto 0);
--leftShiftStage1Idx3Pad12_uid322_normVal_uid115_fpLogE1pxTest(CONSTANT,321)
leftShiftStage1Idx3Pad12_uid322_normVal_uid115_fpLogE1pxTest_q <= "000000000000";
--leftShiftStage1Idx3_uid324_normVal_uid115_fpLogE1pxTest(BITJOIN,323)@28
leftShiftStage1Idx3_uid324_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage046dto0_uid323_normVal_uid115_fpLogE1pxTest_b & leftShiftStage1Idx3Pad12_uid322_normVal_uid115_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx3_uid324_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_5(REG,406)@28
reg_leftShiftStage1Idx3_uid324_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid324_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_5_q <= "00000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid324_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_5_q <= leftShiftStage1Idx3_uid324_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage050dto0_uid320_normVal_uid115_fpLogE1pxTest(BITSELECT,319)@28
LeftShiftStage050dto0_uid320_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_q(50 downto 0);
LeftShiftStage050dto0_uid320_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage050dto0_uid320_normVal_uid115_fpLogE1pxTest_in(50 downto 0);
--leftShiftStage1Idx2_uid321_normVal_uid115_fpLogE1pxTest(BITJOIN,320)@28
leftShiftStage1Idx2_uid321_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage050dto0_uid320_normVal_uid115_fpLogE1pxTest_b & cstAllZWE_uid17_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx2_uid321_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_4(REG,405)@28
reg_leftShiftStage1Idx2_uid321_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid321_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_4_q <= "00000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid321_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_4_q <= leftShiftStage1Idx2_uid321_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage054dto0_uid317_normVal_uid115_fpLogE1pxTest(BITSELECT,316)@28
LeftShiftStage054dto0_uid317_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_q(54 downto 0);
LeftShiftStage054dto0_uid317_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage054dto0_uid317_normVal_uid115_fpLogE1pxTest_in(54 downto 0);
--leftShiftStage1Idx1_uid318_normVal_uid115_fpLogE1pxTest(BITJOIN,317)@28
leftShiftStage1Idx1_uid318_normVal_uid115_fpLogE1pxTest_q <= LeftShiftStage054dto0_uid317_normVal_uid115_fpLogE1pxTest_b & rightShiftStage1Idx2Pad4_uid171_fracXRSExt_uid36_fpLogE1pxTest_q;
--reg_leftShiftStage1Idx1_uid318_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_3(REG,404)@28
reg_leftShiftStage1Idx1_uid318_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid318_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_3_q <= "00000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid318_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_3_q <= leftShiftStage1Idx1_uid318_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_2(REG,403)@28
reg_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_2_q <= "00000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_2_q <= leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid325_normVal_uid115_fpLogE1pxTest(BITSELECT,324)@28
leftShiftStageSel3Dto2_uid325_normVal_uid115_fpLogE1pxTest_in <= r_uid302_countZ_uid114_fpLogE1pxTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid325_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel3Dto2_uid325_normVal_uid115_fpLogE1pxTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid325_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_1(REG,402)@28
reg_leftShiftStageSel3Dto2_uid325_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid325_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid325_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_1_q <= leftShiftStageSel3Dto2_uid325_normVal_uid115_fpLogE1pxTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest(MUX,325)@29
leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_s <= reg_leftShiftStageSel3Dto2_uid325_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_1_q;
leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_s, en, reg_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_2_q, reg_leftShiftStage1Idx1_uid318_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_3_q, reg_leftShiftStage1Idx2_uid321_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_4_q, reg_leftShiftStage1Idx3_uid324_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_5_q)
BEGIN
CASE leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage0_uid315_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx1_uid318_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_3_q;
WHEN "10" => leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx2_uid321_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_4_q;
WHEN "11" => leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1Idx3_uid324_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_5_q;
WHEN OTHERS => leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage155dto0_uid334_normVal_uid115_fpLogE1pxTest(BITSELECT,333)@29
LeftShiftStage155dto0_uid334_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_q(55 downto 0);
LeftShiftStage155dto0_uid334_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage155dto0_uid334_normVal_uid115_fpLogE1pxTest_in(55 downto 0);
--ld_LeftShiftStage155dto0_uid334_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid335_normVal_uid115_fpLogE1pxTest_b(DELAY,753)@29
ld_LeftShiftStage155dto0_uid334_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid335_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 56, depth => 1 )
PORT MAP ( xin => LeftShiftStage155dto0_uid334_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage155dto0_uid334_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid335_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad3_uid333_normVal_uid115_fpLogE1pxTest(CONSTANT,332)
leftShiftStage2Idx3Pad3_uid333_normVal_uid115_fpLogE1pxTest_q <= "000";
--leftShiftStage2Idx3_uid335_normVal_uid115_fpLogE1pxTest(BITJOIN,334)@30
leftShiftStage2Idx3_uid335_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage155dto0_uid334_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx3_uid335_normVal_uid115_fpLogE1pxTest_b_q & leftShiftStage2Idx3Pad3_uid333_normVal_uid115_fpLogE1pxTest_q;
--LeftShiftStage156dto0_uid331_normVal_uid115_fpLogE1pxTest(BITSELECT,330)@29
LeftShiftStage156dto0_uid331_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_q(56 downto 0);
LeftShiftStage156dto0_uid331_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage156dto0_uid331_normVal_uid115_fpLogE1pxTest_in(56 downto 0);
--ld_LeftShiftStage156dto0_uid331_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid332_normVal_uid115_fpLogE1pxTest_b(DELAY,751)@29
ld_LeftShiftStage156dto0_uid331_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid332_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 57, depth => 1 )
PORT MAP ( xin => LeftShiftStage156dto0_uid331_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage156dto0_uid331_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid332_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid332_normVal_uid115_fpLogE1pxTest(BITJOIN,331)@30
leftShiftStage2Idx2_uid332_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage156dto0_uid331_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx2_uid332_normVal_uid115_fpLogE1pxTest_b_q & z2_uid100_fpLogE1pxTest_q;
--LeftShiftStage157dto0_uid328_normVal_uid115_fpLogE1pxTest(BITSELECT,327)@29
LeftShiftStage157dto0_uid328_normVal_uid115_fpLogE1pxTest_in <= leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_q(57 downto 0);
LeftShiftStage157dto0_uid328_normVal_uid115_fpLogE1pxTest_b <= LeftShiftStage157dto0_uid328_normVal_uid115_fpLogE1pxTest_in(57 downto 0);
--ld_LeftShiftStage157dto0_uid328_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid329_normVal_uid115_fpLogE1pxTest_b(DELAY,749)@29
ld_LeftShiftStage157dto0_uid328_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid329_normVal_uid115_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 58, depth => 1 )
PORT MAP ( xin => LeftShiftStage157dto0_uid328_normVal_uid115_fpLogE1pxTest_b, xout => ld_LeftShiftStage157dto0_uid328_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid329_normVal_uid115_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid329_normVal_uid115_fpLogE1pxTest(BITJOIN,328)@30
leftShiftStage2Idx1_uid329_normVal_uid115_fpLogE1pxTest_q <= ld_LeftShiftStage157dto0_uid328_normVal_uid115_fpLogE1pxTest_b_to_leftShiftStage2Idx1_uid329_normVal_uid115_fpLogE1pxTest_b_q & GND_q;
--reg_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_2(REG,408)@29
reg_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_2_q <= "00000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_2_q <= leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest(BITSELECT,335)@28
leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_in <= r_uid302_countZ_uid114_fpLogE1pxTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_b <= leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_b_to_reg_leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_1_a(DELAY,829)@28
ld_leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_b_to_reg_leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_b, xout => ld_leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_b_to_reg_leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_1(REG,407)@29
reg_leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_1_q <= ld_leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_b_to_reg_leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest(MUX,336)@30
leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_s <= reg_leftShiftStageSel1Dto0_uid336_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_1_q;
leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest: PROCESS (leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_s, en, reg_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_2_q, leftShiftStage2Idx1_uid329_normVal_uid115_fpLogE1pxTest_q, leftShiftStage2Idx2_uid332_normVal_uid115_fpLogE1pxTest_q, leftShiftStage2Idx3_uid335_normVal_uid115_fpLogE1pxTest_q)
BEGIN
CASE leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_s IS
WHEN "00" => leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_q <= reg_leftShiftStage1_uid326_normVal_uid115_fpLogE1pxTest_0_to_leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_2_q;
WHEN "01" => leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx1_uid329_normVal_uid115_fpLogE1pxTest_q;
WHEN "10" => leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx2_uid332_normVal_uid115_fpLogE1pxTest_q;
WHEN "11" => leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_q <= leftShiftStage2Idx3_uid335_normVal_uid115_fpLogE1pxTest_q;
WHEN OTHERS => leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracR_uid122_fpLogE1pxTest(BITSELECT,121)@30
fracR_uid122_fpLogE1pxTest_in <= leftShiftStage2_uid337_normVal_uid115_fpLogE1pxTest_q(57 downto 0);
fracR_uid122_fpLogE1pxTest_b <= fracR_uid122_fpLogE1pxTest_in(57 downto 34);
--expFracConc_uid123_fpLogE1pxTest(BITJOIN,122)@30
expFracConc_uid123_fpLogE1pxTest_q <= expRExt_uid121_fpLogE1pxTest_q & fracR_uid122_fpLogE1pxTest_b;
--reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0(REG,412)@30
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q <= "0000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q <= expFracConc_uid123_fpLogE1pxTest_q;
END IF;
END IF;
END PROCESS;
--expFracPostRnd_uid124_fpLogE1pxTest(ADD,123)@31
expFracPostRnd_uid124_fpLogE1pxTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid123_fpLogE1pxTest_0_to_expFracPostRnd_uid124_fpLogE1pxTest_0_q);
expFracPostRnd_uid124_fpLogE1pxTest_b <= STD_LOGIC_VECTOR("0000000000000000000000000000000000" & VCC_q);
expFracPostRnd_uid124_fpLogE1pxTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracPostRnd_uid124_fpLogE1pxTest_a) + UNSIGNED(expFracPostRnd_uid124_fpLogE1pxTest_b));
expFracPostRnd_uid124_fpLogE1pxTest_q <= expFracPostRnd_uid124_fpLogE1pxTest_o(34 downto 0);
--expR_uid127_fpLogE1pxTest(BITSELECT,126)@31
expR_uid127_fpLogE1pxTest_in <= expFracPostRnd_uid124_fpLogE1pxTest_q(31 downto 0);
expR_uid127_fpLogE1pxTest_b <= expR_uid127_fpLogE1pxTest_in(31 downto 24);
--ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_nor(LOGICAL,939)
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_nor_b <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q;
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_nor_q <= not (ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_nor_a or ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_nor_b);
--ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena(REG,940)
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_nor_q = "1") THEN
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_enaAnd(LOGICAL,941)
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_sticky_ena_q;
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b <= en;
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_a and ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_b;
--ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_inputreg(DELAY,929)
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => resIsX_uid62_fpLogE1pxTest_c, xout => ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem(DUALMEM,930)
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_inputreg_q;
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdreg_q;
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_rdmux_q;
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 29,
width_b => 1,
widthad_b => 5,
numwords_b => 29,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq,
address_a => ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_aa,
data_a => ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_ia
);
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_reset0 <= areset;
ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_iq(0 downto 0);
--expR_uid128_fpLogE1pxTest(MUX,127)@31
expR_uid128_fpLogE1pxTest_s <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q;
expR_uid128_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expR_uid128_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expR_uid128_fpLogE1pxTest_s IS
WHEN "0" => expR_uid128_fpLogE1pxTest_q <= expR_uid127_fpLogE1pxTest_b;
WHEN "1" => expR_uid128_fpLogE1pxTest_q <= ld_expX_uid6_fpLogE1pxTest_b_to_expR_uid128_fpLogE1pxTest_d_replace_mem_q;
WHEN OTHERS => expR_uid128_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_nor(LOGICAL,1048)
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_nor_b <= ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_sticky_ena_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_nor_q <= not (ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_nor_a or ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_nor_b);
--ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_mem_top(CONSTANT,1044)
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_mem_top_q <= "011010";
--ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_cmp(LOGICAL,1045)
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_cmp_a <= ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_mem_top_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdmux_q);
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_cmp_q <= "1" when ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_cmp_a = ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_cmp_b else "0";
--ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_cmpReg(REG,1046)
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_cmpReg_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_sticky_ena(REG,1049)
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_nor_q = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_sticky_ena_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_enaAnd(LOGICAL,1050)
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_enaAnd_a <= ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_sticky_ena_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_enaAnd_b <= en;
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_enaAnd_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_enaAnd_a and ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_enaAnd_b;
--xM1_uid131_fpLogE1pxTest(LOGICAL,130)@0
xM1_uid131_fpLogE1pxTest_a <= a;
xM1_uid131_fpLogE1pxTest_b <= mO_uid130_fpLogE1pxTest_q;
xM1_uid131_fpLogE1pxTest_q <= "1" when xM1_uid131_fpLogE1pxTest_a = xM1_uid131_fpLogE1pxTest_b else "0";
--ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b(DELAY,548)@0
ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xM1_uid131_fpLogE1pxTest_q, xout => ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excRInf0_uid134_fpLogE1pxTest(LOGICAL,133)@1
excRInf0_uid134_fpLogE1pxTest_a <= exc_R_uid30_fpLogE1pxTest_q;
excRInf0_uid134_fpLogE1pxTest_b <= ld_xM1_uid131_fpLogE1pxTest_q_to_excRInf0_uid134_fpLogE1pxTest_b_q;
excRInf0_uid134_fpLogE1pxTest_q <= excRInf0_uid134_fpLogE1pxTest_a and excRInf0_uid134_fpLogE1pxTest_b;
--ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a(DELAY,549)@0
ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => branch11_uid64_fpLogE1pxTest_q, xout => ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q, ena => en(0), clk => clk, aclr => areset );
--posInf_uid136_fpLogE1pxTest(LOGICAL,135)@1
posInf_uid136_fpLogE1pxTest_a <= ld_branch11_uid64_fpLogE1pxTest_q_to_posInf_uid136_fpLogE1pxTest_a_q;
posInf_uid136_fpLogE1pxTest_b <= exc_I_uid24_fpLogE1pxTest_q;
posInf_uid136_fpLogE1pxTest_q <= posInf_uid136_fpLogE1pxTest_a and posInf_uid136_fpLogE1pxTest_b;
--excRInf0_uid137_fpLogE1pxTest(LOGICAL,136)@1
excRInf0_uid137_fpLogE1pxTest_a <= posInf_uid136_fpLogE1pxTest_q;
excRInf0_uid137_fpLogE1pxTest_b <= excRInf0_uid134_fpLogE1pxTest_q;
excRInf0_uid137_fpLogE1pxTest_q <= excRInf0_uid137_fpLogE1pxTest_a or excRInf0_uid137_fpLogE1pxTest_b;
--concExc_uid143_fpLogE1pxTest(BITJOIN,142)@1
concExc_uid143_fpLogE1pxTest_q <= excRNaN_uid140_fpLogE1pxTest_q & excRInf0_uid137_fpLogE1pxTest_q & ld_expXIsZero_uid19_fpLogE1pxTest_q_to_InvExpXIsZero_uid29_fpLogE1pxTest_a_q;
--ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_inputreg(DELAY,1038)
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => concExc_uid143_fpLogE1pxTest_q, xout => ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt(COUNTER,1040)
-- every=1, low=0, high=26, step=1, init=1
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_i = 25 THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_eq = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_i <= ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_i - 26;
ELSE
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_i <= ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_i,5));
--ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdreg(REG,1041)
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdreg_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdmux(MUX,1042)
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdmux_s <= en;
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdmux: PROCESS (ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdmux_s, ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdreg_q, ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_q)
BEGIN
CASE ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdmux_s IS
WHEN "0" => ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdmux_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdreg_q;
WHEN "1" => ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdmux_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem(DUALMEM,1039)
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_ia <= ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_inputreg_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_aa <= ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdreg_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_ab <= ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_rdmux_q;
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 5,
numwords_a => 27,
width_b => 3,
widthad_b => 5,
numwords_b => 27,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_iq,
address_a => ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_aa,
data_a => ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_ia
);
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_reset0 <= areset;
ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_iq(2 downto 0);
--reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0(REG,347)@30
reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_q <= ld_concExc_uid143_fpLogE1pxTest_q_to_reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid144_fpLogE1pxTest(LOOKUP,143)@31
excREnc_uid144_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excREnc_uid144_fpLogE1pxTest_q <= "01";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_concExc_uid143_fpLogE1pxTest_0_to_excREnc_uid144_fpLogE1pxTest_0_q) IS
WHEN "000" => excREnc_uid144_fpLogE1pxTest_q <= "01";
WHEN "001" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "010" => excREnc_uid144_fpLogE1pxTest_q <= "10";
WHEN "011" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "100" => excREnc_uid144_fpLogE1pxTest_q <= "11";
WHEN "101" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "110" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN "111" => excREnc_uid144_fpLogE1pxTest_q <= "00";
WHEN OTHERS =>
excREnc_uid144_fpLogE1pxTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid152_fpLogE1pxTest(MUX,151)@32
expRPostExc_uid152_fpLogE1pxTest_s <= excREnc_uid144_fpLogE1pxTest_q;
expRPostExc_uid152_fpLogE1pxTest: PROCESS (expRPostExc_uid152_fpLogE1pxTest_s, en, cstAllZWE_uid17_fpLogE1pxTest_q, expR_uid128_fpLogE1pxTest_q, cstAllOWE_uid15_fpLogE1pxTest_q, cstAllOWE_uid15_fpLogE1pxTest_q)
BEGIN
CASE expRPostExc_uid152_fpLogE1pxTest_s IS
WHEN "00" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllZWE_uid17_fpLogE1pxTest_q;
WHEN "01" => expRPostExc_uid152_fpLogE1pxTest_q <= expR_uid128_fpLogE1pxTest_q;
WHEN "10" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllOWE_uid15_fpLogE1pxTest_q;
WHEN "11" => expRPostExc_uid152_fpLogE1pxTest_q <= cstAllOWE_uid15_fpLogE1pxTest_q;
WHEN OTHERS => expRPostExc_uid152_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid145_fpLogE1pxTest(CONSTANT,144)
oneFracRPostExc2_uid145_fpLogE1pxTest_q <= "00000000000000000000001";
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor(LOGICAL,952)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a <= ld_reg_expX_uid6_fpLogE1pxTest_0_to_expB_uid79_fpLogE1pxTest_2_q_to_expB_uid79_fpLogE1pxTest_c_notEnable_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q <= not (ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_a or ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_b);
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena(REG,953)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_nor_q = "1") THEN
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd(LOGICAL,954)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_sticky_ena_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b <= en;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_a and ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_b;
--ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem(DUALMEM,943)
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia <= ld_frac_uid22_fpLogE1pxTest_b_to_fracXz_uid82_fpLogE1pxTest_b_inputreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdreg_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_rdmux_q;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 5,
numwords_a => 28,
width_b => 23,
widthad_b => 5,
numwords_b => 28,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq,
address_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_aa,
data_a => ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_ia
);
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_reset0 <= areset;
ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_iq(22 downto 0);
--fracR0_uid125_fpLogE1pxTest(BITSELECT,124)@31
fracR0_uid125_fpLogE1pxTest_in <= expFracPostRnd_uid124_fpLogE1pxTest_q(23 downto 0);
fracR0_uid125_fpLogE1pxTest_b <= fracR0_uid125_fpLogE1pxTest_in(23 downto 1);
--fracR_uid126_fpLogE1pxTest(MUX,125)@31
fracR_uid126_fpLogE1pxTest_s <= ld_resIsX_uid62_fpLogE1pxTest_c_to_fracR_uid126_fpLogE1pxTest_b_replace_mem_q;
fracR_uid126_fpLogE1pxTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracR_uid126_fpLogE1pxTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE fracR_uid126_fpLogE1pxTest_s IS
WHEN "0" => fracR_uid126_fpLogE1pxTest_q <= fracR0_uid125_fpLogE1pxTest_b;
WHEN "1" => fracR_uid126_fpLogE1pxTest_q <= ld_frac_uid22_fpLogE1pxTest_b_to_fracR_uid126_fpLogE1pxTest_d_replace_mem_q;
WHEN OTHERS => fracR_uid126_fpLogE1pxTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--fracRPostExc_uid148_fpLogE1pxTest(MUX,147)@32
fracRPostExc_uid148_fpLogE1pxTest_s <= excREnc_uid144_fpLogE1pxTest_q;
fracRPostExc_uid148_fpLogE1pxTest: PROCESS (fracRPostExc_uid148_fpLogE1pxTest_s, en, cstAllZWF_uid8_fpLogE1pxTest_q, fracR_uid126_fpLogE1pxTest_q, cstAllZWF_uid8_fpLogE1pxTest_q, oneFracRPostExc2_uid145_fpLogE1pxTest_q)
BEGIN
CASE fracRPostExc_uid148_fpLogE1pxTest_s IS
WHEN "00" => fracRPostExc_uid148_fpLogE1pxTest_q <= cstAllZWF_uid8_fpLogE1pxTest_q;
WHEN "01" => fracRPostExc_uid148_fpLogE1pxTest_q <= fracR_uid126_fpLogE1pxTest_q;
WHEN "10" => fracRPostExc_uid148_fpLogE1pxTest_q <= cstAllZWF_uid8_fpLogE1pxTest_q;
WHEN "11" => fracRPostExc_uid148_fpLogE1pxTest_q <= oneFracRPostExc2_uid145_fpLogE1pxTest_q;
WHEN OTHERS => fracRPostExc_uid148_fpLogE1pxTest_q <= (others => '0');
END CASE;
END PROCESS;
--RLn_uid153_fpLogE1pxTest(BITJOIN,152)@32
RLn_uid153_fpLogE1pxTest_q <= ld_signRFull_uid142_fpLogE1pxTest_q_to_RLn_uid153_fpLogE1pxTest_c_replace_mem_q & expRPostExc_uid152_fpLogE1pxTest_q & fracRPostExc_uid148_fpLogE1pxTest_q;
--xOut(GPOUT,4)@32
q <= RLn_uid153_fpLogE1pxTest_q;
end normal;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
Dilation/ip/Dilation/fp_mul5418s.vhd
|
10
|
4973
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_MUL5418S.VHD ***
--*** ***
--*** Function: Fixed Point Multiplier ***
--*** 54x18=54, 3 18x18 architecture, ***
--*** Stratix II/III, 3 or 4 pipeline, ***
--*** synthesizable ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 15/01/08 - outputs up to 72 bits now ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_mul5418s IS
GENERIC (
widthcc : positive := 36;
pipes : positive := 3 --3/4
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (18 DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
END fp_mul5418s;
ARCHITECTURE rtl OF fp_mul5418s IS
signal zerovec : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal muloneout, multwoout, multhrout : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal aavec, bbvec : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal resultnode : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal lowff, lowdelff : STD_LOGIC_VECTOR (18 DOWNTO 1);
component dp_fxadd IS
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_mul2s IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 18 GENERATE
zerovec(k) <= '0';
END GENERATE;
mulone: fp_mul2s
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa(18 DOWNTO 1),databb=>databb(18 DOWNTO 1),
result=>muloneout);
multwo: fp_mul2s
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa(36 DOWNTO 19),databb=>databb(18 DOWNTO 1),
result=>multwoout);
multhr: fp_mul2s
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa(54 DOWNTO 37),databb=>databb(18 DOWNTO 1),
result=>multhrout);
aavec <= multhrout & muloneout(36 DOWNTO 19);
bbvec <= zerovec(18 DOWNTO 1) & multwoout;
adder: dp_fxadd
GENERIC MAP (width=>54,pipes=>pipes-2,synthesize=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aavec,bb=>bbvec,carryin=>'0',
cc=>resultnode(72 DOWNTO 19));
gda: IF (pipes = 3) GENERATE
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 18 LOOP
lowff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
lowff <= muloneout(18 DOWNTO 1);
END IF;
END IF;
END PROCESS;
resultnode(18 DOWNTO 1) <= lowff;
END GENERATE;
gdb: IF (pipes = 4) GENERATE
pdb: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 18 LOOP
lowff(k) <= '0';
lowdelff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
lowff <= muloneout(18 DOWNTO 1);
lowdelff <= lowff;
END IF;
END IF;
END PROCESS;
resultnode(18 DOWNTO 1) <= lowdelff;
END GENERATE;
result <= resultnode(72 DOWNTO 73-widthcc);
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/fp_mul5418s.vhd
|
10
|
4973
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_MUL5418S.VHD ***
--*** ***
--*** Function: Fixed Point Multiplier ***
--*** 54x18=54, 3 18x18 architecture, ***
--*** Stratix II/III, 3 or 4 pipeline, ***
--*** synthesizable ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 15/01/08 - outputs up to 72 bits now ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_mul5418s IS
GENERIC (
widthcc : positive := 36;
pipes : positive := 3 --3/4
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (18 DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
END fp_mul5418s;
ARCHITECTURE rtl OF fp_mul5418s IS
signal zerovec : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal muloneout, multwoout, multhrout : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal aavec, bbvec : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal resultnode : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal lowff, lowdelff : STD_LOGIC_VECTOR (18 DOWNTO 1);
component dp_fxadd IS
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_mul2s IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 18 GENERATE
zerovec(k) <= '0';
END GENERATE;
mulone: fp_mul2s
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa(18 DOWNTO 1),databb=>databb(18 DOWNTO 1),
result=>muloneout);
multwo: fp_mul2s
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa(36 DOWNTO 19),databb=>databb(18 DOWNTO 1),
result=>multwoout);
multhr: fp_mul2s
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa(54 DOWNTO 37),databb=>databb(18 DOWNTO 1),
result=>multhrout);
aavec <= multhrout & muloneout(36 DOWNTO 19);
bbvec <= zerovec(18 DOWNTO 1) & multwoout;
adder: dp_fxadd
GENERIC MAP (width=>54,pipes=>pipes-2,synthesize=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aavec,bb=>bbvec,carryin=>'0',
cc=>resultnode(72 DOWNTO 19));
gda: IF (pipes = 3) GENERATE
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 18 LOOP
lowff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
lowff <= muloneout(18 DOWNTO 1);
END IF;
END IF;
END PROCESS;
resultnode(18 DOWNTO 1) <= lowff;
END GENERATE;
gdb: IF (pipes = 4) GENERATE
pdb: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 18 LOOP
lowff(k) <= '0';
lowdelff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
lowff <= muloneout(18 DOWNTO 1);
lowdelff <= lowff;
END IF;
END IF;
END PROCESS;
resultnode(18 DOWNTO 1) <= lowdelff;
END GENERATE;
result <= resultnode(72 DOWNTO 73-widthcc);
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
bin_Sobel_Filter/ip/Sobel/fp_lnclz.vhd
|
10
|
4976
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LNCLZ.VHD ***
--*** ***
--*** Function: Single Precision CLZ ***
--*** ***
--*** 22/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lnclz IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (5 DOWNTO 1)
);
END fp_lnclz;
ARCHITECTURE rtl of fp_lnclz IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (5 DOWNTO 1);
signal position, positionmux : positiontype;
signal zerogroup, firstzero : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal lastman : STD_LOGIC_VECTOR (6 DOWNTO 1);
component fp_pos
GENERIC (start: integer := 0);
PORT
(
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (5 DOWNTO 1)
);
end component;
BEGIN
zerogroup(1) <= mantissa(32) OR mantissa(31) OR mantissa(30) OR mantissa(29) OR mantissa(28) OR mantissa(27);
zerogroup(2) <= mantissa(26) OR mantissa(25) OR mantissa(24) OR mantissa(23) OR mantissa(22) OR mantissa(21);
zerogroup(3) <= mantissa(20) OR mantissa(19) OR mantissa(18) OR mantissa(17) OR mantissa(16) OR mantissa(15);
zerogroup(4) <= mantissa(14) OR mantissa(13) OR mantissa(12) OR mantissa(11) OR mantissa(10) OR mantissa(9);
zerogroup(5) <= mantissa(8) OR mantissa(7) OR mantissa(6) OR mantissa(5) OR mantissa(4) OR mantissa(3);
zerogroup(6) <= mantissa(2) OR mantissa(1);
pa: fp_pos
GENERIC MAP (start=>0)
PORT MAP (ingroup=>mantissa(32 DOWNTO 27),position=>position(1)(5 DOWNTO 1));
pb: fp_pos
GENERIC MAP (start=>6)
PORT MAP (ingroup=>mantissa(26 DOWNTO 21),position=>position(2)(5 DOWNTO 1));
pc: fp_pos
GENERIC MAP (start=>12)
PORT MAP (ingroup=>mantissa(20 DOWNTO 15),position=>position(3)(5 DOWNTO 1));
pd: fp_pos
GENERIC MAP (start=>18)
PORT MAP (ingroup=>mantissa(14 DOWNTO 9),position=>position(4)(5 DOWNTO 1));
pe: fp_pos
GENERIC MAP (start=>24)
PORT MAP (ingroup=>mantissa(8 DOWNTO 3),position=>position(5)(5 DOWNTO 1));
pf: fp_pos
GENERIC MAP (start=>30)
PORT MAP (ingroup=>lastman,position=>position(6)(5 DOWNTO 1));
lastman <= mantissa(2 DOWNTO 1) & "0000";
firstzero(1) <= zerogroup(1);
firstzero(2) <= NOT(zerogroup(1)) AND zerogroup(2);
firstzero(3) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND zerogroup(3);
firstzero(4) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND zerogroup(4);
firstzero(5) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND zerogroup(5);
firstzero(6) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND NOT(zerogroup(4))
AND NOT(zerogroup(5)) AND zerogroup(6);
gma: FOR k IN 1 TO 5 GENERATE
positionmux(1)(k) <= position(1)(k) AND firstzero(1);
gmb: FOR j IN 2 TO 6 GENERATE
positionmux(j)(k) <= positionmux(j-1)(k) OR (position(j)(k) AND firstzero(j));
END GENERATE;
END GENERATE;
leading <= positionmux(6)(5 DOWNTO 1);
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
bin_Sobel_Filter/ip/Sobel/hcc_package_cmd.vhd
|
10
|
23935
|
-- (C) 2010 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_PACKAGE.VHD ***
--*** ***
--*** Function: Component Declarations of ***
--*** compiler instantiated functions ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** Change History ***
--*** ***
--*** 16/04/09 - add components w' NAN support ***
--*** ***
--*** ***
--***************************************************
PACKAGE hcc_package_cmd IS
--***********************************
--*** SINGLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp1x
--GENERIC (
-- mantissa : positive := 36;
-- shiftspeed : integer := 1
-- );
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_alufp1_dot IS
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/8/u23)
xoutput : integer := 1; -- 1 = single x format (s32/36/10)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
mantissa : positive := 32; -- 32 or 36
outputscale : integer := 1; -- 0 = none, 1 = scale
device : integer := 0; -- 0 to 3 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1vec
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp1_dot
GENERIC (
mantissa : positive := 32; -- 32 or 36
device : integer := 0; -- 0 to 2 supported
optimization : positive := 1; -- 1,2,3
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp1x
GENERIC (
mantissa : positive := 32; -- 32/36 mantissa
ieeeoutput : integer := 1; -- 1 = ieee754 (1/u23/8)
xoutput : integer := 0; -- 1 = single x format (s32/13)
multoutput : integer := 0; -- 1 = to another single muliplier (s/1/34/10) - signed
divoutput : integer := 0; -- 1 = to a single divider (s/1/34/10) - signed magnitude
roundconvert : integer := 0;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+multoutput+divoutput) DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp1x
GENERIC (
mantissa : positive := 32; -- 32 or 36
inputnormalize : integer := 1; -- 0 = scale, 1 = normalize
roundnormalize : integer := 1;
normspeed : positive := 2; -- 1 or 2
target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp1x
GENERIC (
mantissa : positive := 32 -- 32/36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_aludot_v2
GENERIC (
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aasign : IN STD_LOGIC;
aaexponent : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
aamantissa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bbsign : IN STD_LOGIC;
bbexponent : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
bbmantissa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (42 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_muldot_v1 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
ccsign : OUT STD_LOGIC;
ccexponent : OUT STD_LOGIC_VECTOR (10 DOWNTO 1);
ccmantissa : OUT STD_LOGIC_VECTOR (32 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************************
--*** DOUBLE PRECISION COMPONENTS ***
--***********************************
component hcc_alufp2x
GENERIC (
shiftspeed : integer := 1; -- '0' for comb. shift, '1' for piped shift
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_mulfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
multoutput : integer := 0; -- 1 = to another double muliplier (s/1u52/13)
roundconvert : integer := 0; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 0; -- global switch - round all normalizations when '1'
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
outputpipe : integer := 0; -- if zero, dont put final pipe for some modes
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 to 2 supported
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*multoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_divfp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
divoutput : integer := 1; -- function output (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*divoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_normfp2x
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
roundnormalize : integer := 1; -- global switch - round all normalizations when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_ldexp2x
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
funcoutput : integer := 1 -- function output (S'1'u54/13)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*funcoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
--***********************
--*** CAST COMPONENTS ***
--***********************
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtof IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftoy
GENERIC (
target : integer := 0; -- 1 (internal), 0 (multiplier,divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
outputpipe : integer := 1; -- if zero, dont put final pipe for some modes
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtox
GENERIC (
target : integer := 0; -- 0 (internal), 1 (multiplier), 2 (divider)
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castxtod
GENERIC (
mantissa : positive := 32;
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 0 -- '0' for unpiped adder, '1' for piped adder
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castxtoy
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castytod
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castytof
GENERIC (
roundconvert : integer := 1 -- global switch - round all conversions when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytox
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtol
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
normspeed : positive := 2
); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftol
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castxtol
GENERIC (
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castytol
GENERIC (normspeed : positive := 2); -- 1,2 pipes for conversion
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aazip, aasat, aanan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltod
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_castltof
GENERIC (
mantissa : integer := 36;
normspeed: positive := 1;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castltox
GENERIC (
mantissa : integer := 36;
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castltoy
GENERIC (
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
end component;
component hcc_castdtof
GENERIC (
roundconvert : integer := 1 -- global switch - round all ieee<=>y conversion when '1'
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_castftod
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
--************************
--*** OTHER COMPONENTS ***
--************************
component hcc_delay
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
END hcc_package_cmd;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
Dilation/ip/Dilation/hcc_mul3236s.vhd
|
10
|
4308
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL3236S.VHD ***
--*** ***
--*** Function: 3 pipeline stage unsigned 32 or ***
--*** 36 bit multiplier (synth'able) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul3236s IS
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
END hcc_mul3236s;
ARCHITECTURE syn OF hcc_mul3236s IS
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (2*width-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "SIGNED",
representation_b => "SIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => width,
width_b => width,
width_result => 2*width
)
PORT MAP (
dataa => mulaa,
datab => mulbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulcc
);
END syn;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/hcc_mul3236s.vhd
|
10
|
4308
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL3236S.VHD ***
--*** ***
--*** Function: 3 pipeline stage unsigned 32 or ***
--*** 36 bit multiplier (synth'able) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul3236s IS
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
END hcc_mul3236s;
ARCHITECTURE syn OF hcc_mul3236s IS
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (2*width-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "SIGNED",
representation_b => "SIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => width,
width_b => width,
width_result => 2*width
)
PORT MAP (
dataa => mulaa,
datab => mulbb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulcc
);
END syn;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
bin_Dilation_Operation/ip/Dilation/dp_ldexp.vhd
|
10
|
4877
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** DP_LDEXP.VHD ***
--*** ***
--*** Function: Single Precision Load Exponent ***
--*** ***
--*** ldexp(x,n) - x*2^n - IEEE in and out ***
--*** ***
--*** Created 12/09/09 ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_ldexp IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
END dp_ldexp;
ARCHITECTURE rtl OF dp_ldexp IS
signal signinff : STD_LOGIC;
signal exponentinff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal mantissainff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal bbff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal signoutff : STD_LOGIC;
signal exponentoutff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal mantissaoutff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal satoutff, zerooutff, nanoutff : STD_LOGIC;
signal satnode, zeronode, nannode : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expzeroin, expmaxin : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expzeronode, expmaxnode : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expzeroout, expmaxout : STD_LOGIC;
signal manzeroin : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal manzero, mannonzero : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
signoutff <= '0';
FOR k IN 1 TO 11 LOOP
exponentinff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 52 LOOP
mantissainff(k) <= '0';
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
bbff(k) <= '0';
END LOOP;
satoutff <= '0';
zerooutff <= '0';
nanoutff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff <= signin;
exponentinff <= exponentin;
mantissainff <= mantissain;
bbff <= bb(13 DOWNTO 1);
signoutff <= signinff;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (expnode(k) AND NOT(zeronode)) OR satnode OR nannode;
END LOOP;
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= (mantissainff(k) AND NOT(zeronode) AND NOT(satnode)) OR nannode;
END LOOP;
satoutff <= satnode;
zerooutff <= zeronode;
nanoutff <= nannode;
END IF;
END IF;
END PROCESS;
expnode <= ("00" & exponentinff) + bbff;
expzeroin(1) <= exponentinff(1);
expmaxin(1) <= exponentinff(1);
gxa: FOR k IN 2 TO 11 GENERATE
expzeroin(k) <= expzeroin(k-1) OR exponentinff(k);
expmaxin(k) <= expmaxin(k-1) AND exponentinff(k);
END GENERATE;
expzeronode(1) <= expnode(1);
expmaxnode(1) <= expnode(1);
gxb: FOR k IN 2 TO 11 GENERATE
expzeronode(k) <= expzeronode(k-1) OR expnode(k);
expmaxnode(k) <= expmaxnode(k-1) AND expnode(k);
END GENERATE;
expzeroout <= NOT(expzeroin(11)) OR (NOT(expzeronode(11)) AND NOT(expnode(12))) OR (expnode(13));
expmaxout <= expmaxin(11) OR (expmaxnode(11) AND NOT(expnode(12))) OR (expnode(12) AND NOT(expnode(13)));
manzeroin(1) <= mantissainff(1);
gma: FOR k IN 2 TO 52 GENERATE
manzeroin(k) <= manzeroin(k-1) OR mantissainff(k);
END GENERATE;
manzero <= NOT(manzeroin(52));
mannonzero <= manzeroin(52);
satnode <= (expmaxin(11) AND NOT(manzeroin(52))) OR expmaxout;
zeronode <= NOT(expzeroin(11)) OR expzeroout;
nannode <= expmaxin(11) AND manzeroin(52);
signout <= signoutff;
exponentout <= exponentoutff;
mantissaout <= mantissaoutff;
satout <= satoutff;
zeroout <= zerooutff;
nanout <= nanoutff;
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
Dilation/ip/Dilation/hcc_mulufp54.vhd
|
10
|
5016
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULUFP54.VHD ***
--*** ***
--*** Function: Double precision multiplier ***
--*** core (unsigned mantissa) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mulufp54 IS
GENERIC (synthesize : integer := 1); -- 0 = behavioral, 1 = instantiated
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bbman : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
bbexp : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
ccman : OUT STD_LOGIC_VECTOR (64 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (13 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_mulufp54;
ARCHITECTURE rtl OF hcc_mulufp54 IS
constant normtype : integer := 0;
type expfftype IS ARRAY (5 DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal mulout : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaexpff, bbexpff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expff : expfftype;
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal ccsatff, cczipff : STD_LOGIC_VECTOR (5 DOWNTO 1);
component hcc_mul54usb
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_mul54uss
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
-- 54 bit mantissa, signed normalized input
-- [S ][1 ][M...M]
-- [54][53][52..1]
-- multiplier outputs (result < 2)
-- [S....S][1 ][M*M...][X...X]
-- [72..70][69][68..17][16..1]
-- multiplier outputs (result >= 2)
-- [S....S][1 ][M*M...][X...X]
-- [72..71][70][69..18][17..1]
-- assume that result > 2
-- output [71..8] for 64 bit mantissa out
pma: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aaexpff <= "0000000000000";
bbexpff <= "0000000000000";
FOR k IN 1 TO 5 LOOP
expff(k)(13 DOWNTO 1) <= "0000000000000";
END LOOP;
aasatff <= '0';
aazipff <= '0';
bbsatff <= '0';
bbzipff <= '0';
ccsatff <= "00000";
cczipff <= "00000";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aasatff <= aasat;
aazipff <= aazip;
bbsatff <= bbsat;
bbzipff <= bbzip;
ccsatff(1) <= aasatff OR bbsatff;
FOR k IN 2 TO 5 LOOP
ccsatff(k) <= ccsatff(k-1);
END LOOP;
cczipff(1) <= aazipff OR bbzipff;
FOR k IN 2 TO 5 LOOP
cczipff(k) <= cczipff(k-1);
END LOOP;
aaexpff <= aaexp;
bbexpff <= bbexp;
expff(1)(13 DOWNTO 1) <= aaexpff + bbexpff - "0001111111111";
FOR k IN 1 TO 13 LOOP
expff(2)(k) <= (expff(1)(k) OR ccsatff(1)) AND NOT(cczipff(1));
END LOOP;
FOR k IN 3 TO 5 LOOP
expff(k)(13 DOWNTO 1) <= expff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
gsa: IF (synthesize = 0) GENERATE
bmult: hcc_mul54usb
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aaman,bb=>bbman,
cc=>mulout);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
smult: hcc_mul54uss
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aaman,mulbb=>bbman,
mulcc=>mulout);
END GENERATE;
--***************
--*** OUTPUTS ***
--***************
ccman <= mulout;
ccexp <= expff(5)(13 DOWNTO 1);
ccsat <= ccsatff(5);
cczip <= cczipff(5);
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/hcc_mulufp54.vhd
|
10
|
5016
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULUFP54.VHD ***
--*** ***
--*** Function: Double precision multiplier ***
--*** core (unsigned mantissa) ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mulufp54 IS
GENERIC (synthesize : integer := 1); -- 0 = behavioral, 1 = instantiated
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bbman : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
bbexp : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
ccman : OUT STD_LOGIC_VECTOR (64 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (13 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_mulufp54;
ARCHITECTURE rtl OF hcc_mulufp54 IS
constant normtype : integer := 0;
type expfftype IS ARRAY (5 DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal mulout : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaexpff, bbexpff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expff : expfftype;
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal ccsatff, cczipff : STD_LOGIC_VECTOR (5 DOWNTO 1);
component hcc_mul54usb
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
component hcc_mul54uss
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
-- 54 bit mantissa, signed normalized input
-- [S ][1 ][M...M]
-- [54][53][52..1]
-- multiplier outputs (result < 2)
-- [S....S][1 ][M*M...][X...X]
-- [72..70][69][68..17][16..1]
-- multiplier outputs (result >= 2)
-- [S....S][1 ][M*M...][X...X]
-- [72..71][70][69..18][17..1]
-- assume that result > 2
-- output [71..8] for 64 bit mantissa out
pma: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aaexpff <= "0000000000000";
bbexpff <= "0000000000000";
FOR k IN 1 TO 5 LOOP
expff(k)(13 DOWNTO 1) <= "0000000000000";
END LOOP;
aasatff <= '0';
aazipff <= '0';
bbsatff <= '0';
bbzipff <= '0';
ccsatff <= "00000";
cczipff <= "00000";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aasatff <= aasat;
aazipff <= aazip;
bbsatff <= bbsat;
bbzipff <= bbzip;
ccsatff(1) <= aasatff OR bbsatff;
FOR k IN 2 TO 5 LOOP
ccsatff(k) <= ccsatff(k-1);
END LOOP;
cczipff(1) <= aazipff OR bbzipff;
FOR k IN 2 TO 5 LOOP
cczipff(k) <= cczipff(k-1);
END LOOP;
aaexpff <= aaexp;
bbexpff <= bbexp;
expff(1)(13 DOWNTO 1) <= aaexpff + bbexpff - "0001111111111";
FOR k IN 1 TO 13 LOOP
expff(2)(k) <= (expff(1)(k) OR ccsatff(1)) AND NOT(cczipff(1));
END LOOP;
FOR k IN 3 TO 5 LOOP
expff(k)(13 DOWNTO 1) <= expff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
gsa: IF (synthesize = 0) GENERATE
bmult: hcc_mul54usb
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aaman,bb=>bbman,
cc=>mulout);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
smult: hcc_mul54uss
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aaman,mulbb=>bbman,
mulcc=>mulout);
END GENERATE;
--***************
--*** OUTPUTS ***
--***************
ccman <= mulout;
ccexp <= expff(5)(13 DOWNTO 1);
ccsat <= ccsatff(5);
cczip <= cczipff(5);
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
Dilation/ip/Dilation/hcc_lsftpipe32.vhd
|
20
|
4030
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_LSFTPIPE32.VHD ***
--*** ***
--*** Function: 1 pipeline stage left shift, 32 ***
--*** bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_lsftpipe32;
ARCHITECTURE rtl OF hcc_lsftpipe32 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal shiftff : STD_LOGIC;
signal levtwoff : STD_LOGIC_VECTOR (32 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 32 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 32 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= '0';
FOR k IN 1 TO 32 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff)) OR
(levtwoff(k-16) AND shiftff);
END GENERATE;
outbus <= levthr;
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
Dilation/ip/Dilation/fp_inv.vhd
|
10
|
8297
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION INVERSE - TOP LEVEL ***
--*** ***
--*** FP_INV.VHD ***
--*** ***
--*** Function: IEEE754 SP Inverse ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 14 ***
--***************************************************
ENTITY fp_inv IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
END fp_inv;
ARCHITECTURE div OF fp_inv IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
constant coredepth : positive := 12;
type expfftype IS ARRAY (coredepth-1 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal signinff : STD_LOGIC;
signal manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal expoffset : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal invertnum : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quotient : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (coredepth-1 DOWNTO 1);
signal expff : expfftype;
-- conditions
signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zeromaninff : STD_LOGIC;
signal zeroexpinff : STD_LOGIC;
signal maxexpinff : STD_LOGIC;
signal zeroinff : STD_LOGIC;
signal infinityinff : STD_LOGIC;
signal naninff : STD_LOGIC;
signal dividebyzeroff, nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1);
component fp_inv_core IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_divrnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentdiv : IN STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
mantissadiv : IN STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
nanin : IN STD_LOGIC;
dividebyzeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (expwidth DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (manwidth DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxa: FOR k IN 1 TO expwidth-1 GENERATE
expoffset(k) <= '1';
END GENERATE;
expoffset(expwidth+2 DOWNTO expwidth) <= "000";
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth LOOP
manff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-1 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-1 LOOP
FOR j IN 1 TO expwidth+2 LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff <= signin;
manff <= mantissain;
expinff <= exponentin;
signff(1) <= signinff;
FOR k IN 2 TO coredepth-1 LOOP
signff(k) <= signff(k-1);
END LOOP;
expff(1)(expwidth+2 DOWNTO 1) <= expoffset - ("00" & expinff);
expff(2)(expwidth+2 DOWNTO 1) <= expff(1)(expwidth+2 DOWNTO 1) + expoffset;
FOR k IN 3 TO coredepth-2 LOOP
expff(k)(expwidth+2 DOWNTO 1) <= expff(k-1)(expwidth+2 DOWNTO 1);
END LOOP;
-- inverse always less than 1, decrement exponent
expff(coredepth-1)(expwidth+2 DOWNTO 1) <= expff(coredepth-2)(expwidth+2 DOWNTO 1) -
(zerovec(expwidth+1 DOWNTO 1) & '1');
END IF;
END IF;
END PROCESS;
--********************
--*** CHECK INPUTS ***
--********************
zeroman(1) <= manff(1);
gca: FOR k IN 2 TO manwidth GENERATE
zeroman(k) <= zeroman(k-1) OR manff(k);
END GENERATE;
zeroexp(1) <= expinff(1);
gcb: FOR k IN 2 TO expwidth GENERATE
zeroexp(k) <= zeroexp(k-1) OR expinff(k);
END GENERATE;
maxexp(1) <= expinff(1);
gcc: FOR k IN 2 TO expwidth GENERATE
maxexp(k) <= maxexp(k-1) AND expinff(k);
END GENERATE;
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
zeromaninff <= '0';
zeroexpinff <= '0';
maxexpinff <= '0';
zeroinff <= '0';
infinityinff <= '0';
naninff <= '0';
FOR k IN 1 TO coredepth-3 LOOP
dividebyzeroff(k) <= '0';
nanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeromaninff <= zeroman(manwidth);
zeroexpinff <= zeroexp(expwidth);
maxexpinff <= maxexp(expwidth);
-- zero when man = 0, exp = 0
-- infinity when man = 0, exp = max
-- nan when man != 0, exp = max
-- all ffs '1' when condition true
zeroinff <= NOT(zeromaninff OR zeroexpinff);
infinityinff <= NOT(zeromaninff) AND maxexpinff;
naninff <= zeromaninff AND maxexpinff;
-- nan output when nan input
nanff(1) <= naninff;
FOR k IN 2 TO coredepth-3 LOOP
nanff(k) <= nanff(k-1);
END LOOP;
dividebyzeroff(1) <= zeroinff;
FOR k IN 2 TO coredepth-3 LOOP
dividebyzeroff(k) <= dividebyzeroff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--*******************
--*** DIVIDE CORE ***
--*******************
invertnum <= '1' & mantissain & "000000000000";
-- will give output between 0.5 and 0.99999...
-- will always need to be normalized
invcore: fp_inv_core
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
divisor=>invertnum,
quotient=>quotient);
--************************
--*** ROUND AND OUTPUT ***
--************************
rndout: fp_divrnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signff(coredepth-1),
exponentdiv=>expff(coredepth-1)(expwidth+2 DOWNTO 1),
mantissadiv=>quotient(34 DOWNTO 11),
nanin=>nanff(coredepth-3),dividebyzeroin=>dividebyzeroff(coredepth-3),
signout=>signout,exponentout=>exponentout,mantissaout=>mantissaout,
nanout=>nanout,invalidout=>invalidout,dividebyzeroout=>dividebyzeroout);
END div;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
bin_Sobel_Filter/ip/Sobel/fp_neg.vhd
|
10
|
3070
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FP_NEG.VHD ***
--*** ***
--*** Function: Single Precision Negative Value ***
--*** ***
--*** Created 11/09/09 ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_neg IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
END fp_neg;
ARCHITECTURE rtl OF fp_neg IS
signal signff : STD_LOGIC;
signal exponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal expnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzerochk, expmaxchk : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzero, expmax : STD_LOGIC;
signal manzerochk : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal manzero, mannonzero : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= '0';
FOR k IN 1 TO 8 LOOP
exponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff <= NOT(signin);
exponentff <= exponentin;
mantissaff <= mantissain;
END IF;
END IF;
END PROCESS;
expzerochk(1) <= exponentff(1);
expmaxchk(1) <= exponentff(1);
gxa: FOR k IN 2 TO 8 GENERATE
expzerochk(k) <= expzerochk(k-1) OR exponentff(k);
expmaxchk(k) <= expmaxchk(k-1) AND exponentff(k);
END GENERATE;
expzero <= NOT(expzerochk(8));
expmax <= expmaxchk(8);
manzerochk(1) <= mantissaff(1);
gma: FOR k IN 2 TO 23 GENERATE
manzerochk(k) <= manzerochk(k-1) OR mantissaff(k);
END GENERATE;
manzero <= NOT(manzerochk(23));
mannonzero <= manzerochk(23);
signout <= signff;
exponentout <= exponentff;
mantissaout <= mantissaff;
satout <= expmax AND manzero;
zeroout <= expzero;
nanout <= expmax AND mannonzero;
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
bin_Sobel_Filter/ip/Sobel/hcc_neg1x.vhd
|
10
|
5243
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NEG1X.VHD ***
--*** ***
--*** Function: Negate Variable ***
--*** ***
--*** Input is normalized S,'1',mantissa,exp ***
--*** ***
--*** 14/03/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_neg1x IS
GENERIC (
mantissa : positive := 32; -- 32/36
ieeeoutput : integer := 0; -- 1 = ieee754 (S/u23/8)
xoutput : integer := 1; -- 1 = single x format (smantissa/10)
funcoutput : integer := 0 -- function output (S'1'umantissa-2/10)
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32*ieeeoutput+(mantissa+10)*(xoutput+funcoutput) DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_neg1x;
ARCHITECTURE rtl OF hcc_neg1x IS
signal aaff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal aasatff, aazipff : STD_LOGIC;
-- x output
signal ccxman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal ccxexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
-- function output
signal ccfuncman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal ccfuncexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
-- ieee output
signal expnode : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal manoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal expoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expmax, expzero : STD_LOGIC;
signal manoutzero, expoutzero, expoutmax : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa+10 LOOP
aaff(k) <= '0';
END LOOP;
aasatff <= '0';
aazipff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
aasatff <= aasat;
aazipff <= aazip;
END IF;
END IF;
END PROCESS;
--******************************
--*** internal format output ***
--******************************
goxa: IF (xoutput = 1) GENERATE
goxb: FOR k IN 1 TO mantissa GENERATE
ccxman(k) <= NOT(aaff(k+10));
END GENERATE;
ccxexp(10 DOWNTO 1) <= aaff(10 DOWNTO 1);
cc <= ccxman & ccxexp;
ccsat <= aasatff;
cczip <= aazipff;
END GENERATE;
--***************************************
--*** internal function format output ***
--***************************************
gofa: IF (funcoutput = 1) GENERATE
ccfuncman(mantissa) <= NOT(aaff(mantissa+10));
ccfuncman(mantissa-1 DOWNTO 1) <= aaff(mantissa+9 DOWNTO 11);
ccfuncexp(10 DOWNTO 1) <= aaff(10 DOWNTO 1);
cc <= ccfuncman & ccfuncexp;
ccsat <= aasatff;
cczip <= aazipff;
END GENERATE;
--**************************
--*** IEEE format output ***
--**************************
goia: IF (ieeeoutput = 1) GENERATE
expnode <= aaff(10 DOWNTO 1);
pio: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 23 LOOP
manoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
expoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
FOR k IN 1 TO 23 LOOP
manoutff(k) <= aaff(k+mantissa-15) AND NOT(manoutzero);
END LOOP;
FOR k IN 1 TO 8 LOOP
expoutff(k) <= (expnode(k) AND NOT(expoutzero)) OR expoutmax;
END LOOP;
END IF;
END PROCESS;
expmax <= expnode(8) AND expnode(7) AND expnode(6) AND expnode(5) AND
expnode(4) AND expnode(3) AND expnode(2) AND expnode(1);
expzero <= NOT(expnode(8) OR expnode(7) OR expnode(6) OR expnode(5) OR
expnode(4) OR expnode(3) OR expnode(2) OR expnode(1));
manoutzero <= aasatff OR aazipff OR expmax OR expzero OR expnode(10) OR expnode(9);
expoutzero <= aazipff OR expzero OR expnode(10);
expoutmax <= aasatff OR expmax OR (NOT(expnode(10)) AND expnode(9));
-- OUTPUTS
cc <= NOT(aaff(mantissa+10)) & expoutff & manoutff;
ccsat <= '0';
cczip <= '0';
END GENERATE;
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
Dilation/ip/Dilation/dotp_core.vhd
|
10
|
11621
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--USE work.hcc_package.all;
--USE work.hcc_library_package.all;
--**********************************************
--*** ***
--*** Generated by Floating Point Compiler ***
--*** ***
--*** Copyright Altera Corporation 2008 ***
--*** ***
--*** ***
--*** Version 2008.2X - April 24,2008 ***
--*** Testing Version Only - ***
--*** Stratix V DSP Benchmarking ***
--*** ***
--**********************************************
ENTITY dotp_core IS
PORT(
clock : IN STD_LOGIC;
resetn : IN STD_LOGIC;
valid_in : IN STD_LOGIC;
valid_out : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(32 DOWNTO 1);
a0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
a3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b0 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b1 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b2 : IN STD_LOGIC_VECTOR(512 DOWNTO 1);
b3 : IN STD_LOGIC_VECTOR(512 DOWNTO 1)
);
END dotp_core;
ARCHITECTURE gen OF dotp_core IS
COMPONENT sgm_fpmm64
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
startin : IN STD_LOGIC;
xx00 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx01 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx02 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx03 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx04 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx05 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx06 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx07 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx08 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx09 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx0f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx10 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx11 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx12 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx13 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx14 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx15 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx16 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx17 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx18 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx19 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx1f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx20 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx21 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx22 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx23 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx24 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx25 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx26 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx27 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx28 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx29 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx2f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx30 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx31 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx32 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx33 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx34 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx35 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx36 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx37 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx38 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx39 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
xx3f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc00 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc01 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc02 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc03 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc04 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc05 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc06 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc07 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc08 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc09 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc0f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc10 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc11 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc12 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc13 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc14 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc15 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc16 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc17 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc18 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc19 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc1f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc20 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc21 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc22 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc23 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc24 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc25 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc26 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc27 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc28 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc29 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc2f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc30 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc31 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc32 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc33 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc34 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc35 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc36 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc37 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc38 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc39 : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3a : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3b : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3c : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3d : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3e : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc3f : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
startout : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END component;
SIGNAL done : STD_LOGIC;
SIGNAL res : STD_LOGIC_VECTOR(32 DOWNTO 1);
SIGNAL reset : STD_LOGIC;
BEGIN
reset <= NOT resetn;
cmp0: sgm_fpmm64
PORT MAP (sysclk=>clock, reset=>reset, enable=>'1', startin=>valid_in,
startout=>done, result=>res,
xx00 => a0(32 DOWNTO 1),
cc00 => b0(32 DOWNTO 1),
xx01 => a0(64 DOWNTO 33),
cc01 => b0(64 DOWNTO 33),
xx02 => a0(96 DOWNTO 65),
cc02 => b0(96 DOWNTO 65),
xx03 => a0(128 DOWNTO 97),
cc03 => b0(128 DOWNTO 97),
xx04 => a0(160 DOWNTO 129),
cc04 => b0(160 DOWNTO 129),
xx05 => a0(192 DOWNTO 161),
cc05 => b0(192 DOWNTO 161),
xx06 => a0(224 DOWNTO 193),
cc06 => b0(224 DOWNTO 193),
xx07 => a0(256 DOWNTO 225),
cc07 => b0(256 DOWNTO 225),
xx08 => a0(288 DOWNTO 257),
cc08 => b0(288 DOWNTO 257),
xx09 => a0(320 DOWNTO 289),
cc09 => b0(320 DOWNTO 289),
xx0a => a0(352 DOWNTO 321),
cc0a => b0(352 DOWNTO 321),
xx0b => a0(384 DOWNTO 353),
cc0b => b0(384 DOWNTO 353),
xx0c => a0(416 DOWNTO 385),
cc0c => b0(416 DOWNTO 385),
xx0d => a0(448 DOWNTO 417),
cc0d => b0(448 DOWNTO 417),
xx0e => a0(480 DOWNTO 449),
cc0e => b0(480 DOWNTO 449),
xx0f => a0(512 DOWNTO 481),
cc0f => b0(512 DOWNTO 481),
xx10 => a1(32 DOWNTO 1),
cc10 => b1(32 DOWNTO 1),
xx11 => a1(64 DOWNTO 33),
cc11 => b1(64 DOWNTO 33),
xx12 => a1(96 DOWNTO 65),
cc12 => b1(96 DOWNTO 65),
xx13 => a1(128 DOWNTO 97),
cc13 => b1(128 DOWNTO 97),
xx14 => a1(160 DOWNTO 129),
cc14 => b1(160 DOWNTO 129),
xx15 => a1(192 DOWNTO 161),
cc15 => b1(192 DOWNTO 161),
xx16 => a1(224 DOWNTO 193),
cc16 => b1(224 DOWNTO 193),
xx17 => a1(256 DOWNTO 225),
cc17 => b1(256 DOWNTO 225),
xx18 => a1(288 DOWNTO 257),
cc18 => b1(288 DOWNTO 257),
xx19 => a1(320 DOWNTO 289),
cc19 => b1(320 DOWNTO 289),
xx1a => a1(352 DOWNTO 321),
cc1a => b1(352 DOWNTO 321),
xx1b => a1(384 DOWNTO 353),
cc1b => b1(384 DOWNTO 353),
xx1c => a1(416 DOWNTO 385),
cc1c => b1(416 DOWNTO 385),
xx1d => a1(448 DOWNTO 417),
cc1d => b1(448 DOWNTO 417),
xx1e => a1(480 DOWNTO 449),
cc1e => b1(480 DOWNTO 449),
xx1f => a1(512 DOWNTO 481),
cc1f => b1(512 DOWNTO 481),
xx20 => a2(32 DOWNTO 1),
cc20 => b2(32 DOWNTO 1),
xx21 => a2(64 DOWNTO 33),
cc21 => b2(64 DOWNTO 33),
xx22 => a2(96 DOWNTO 65),
cc22 => b2(96 DOWNTO 65),
xx23 => a2(128 DOWNTO 97),
cc23 => b2(128 DOWNTO 97),
xx24 => a2(160 DOWNTO 129),
cc24 => b2(160 DOWNTO 129),
xx25 => a2(192 DOWNTO 161),
cc25 => b2(192 DOWNTO 161),
xx26 => a2(224 DOWNTO 193),
cc26 => b2(224 DOWNTO 193),
xx27 => a2(256 DOWNTO 225),
cc27 => b2(256 DOWNTO 225),
xx28 => a2(288 DOWNTO 257),
cc28 => b2(288 DOWNTO 257),
xx29 => a2(320 DOWNTO 289),
cc29 => b2(320 DOWNTO 289),
xx2a => a2(352 DOWNTO 321),
cc2a => b2(352 DOWNTO 321),
xx2b => a2(384 DOWNTO 353),
cc2b => b2(384 DOWNTO 353),
xx2c => a2(416 DOWNTO 385),
cc2c => b2(416 DOWNTO 385),
xx2d => a2(448 DOWNTO 417),
cc2d => b2(448 DOWNTO 417),
xx2e => a2(480 DOWNTO 449),
cc2e => b2(480 DOWNTO 449),
xx2f => a2(512 DOWNTO 481),
cc2f => b2(512 DOWNTO 481),
xx30 => a3(32 DOWNTO 1),
cc30 => b3(32 DOWNTO 1),
xx31 => a3(64 DOWNTO 33),
cc31 => b3(64 DOWNTO 33),
xx32 => a3(96 DOWNTO 65),
cc32 => b3(96 DOWNTO 65),
xx33 => a3(128 DOWNTO 97),
cc33 => b3(128 DOWNTO 97),
xx34 => a3(160 DOWNTO 129),
cc34 => b3(160 DOWNTO 129),
xx35 => a3(192 DOWNTO 161),
cc35 => b3(192 DOWNTO 161),
xx36 => a3(224 DOWNTO 193),
cc36 => b3(224 DOWNTO 193),
xx37 => a3(256 DOWNTO 225),
cc37 => b3(256 DOWNTO 225),
xx38 => a3(288 DOWNTO 257),
cc38 => b3(288 DOWNTO 257),
xx39 => a3(320 DOWNTO 289),
cc39 => b3(320 DOWNTO 289),
xx3a => a3(352 DOWNTO 321),
cc3a => b3(352 DOWNTO 321),
xx3b => a3(384 DOWNTO 353),
cc3b => b3(384 DOWNTO 353),
xx3c => a3(416 DOWNTO 385),
cc3c => b3(416 DOWNTO 385),
xx3d => a3(448 DOWNTO 417),
cc3d => b3(448 DOWNTO 417),
xx3e => a3(480 DOWNTO 449),
cc3e => b3(480 DOWNTO 449),
xx3f => a3(512 DOWNTO 481),
cc3f => b3(512 DOWNTO 481));
result <= res;
valid_out <= done;
END gen;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
bin_Dilation_Operation/ip/Dilation/fp_clz23.vhd
|
10
|
4166
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CLZ23.VHD ***
--*** ***
--*** Function: 23 bit Count Leading Zeros ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_clz23 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (5 DOWNTO 1)
);
END fp_clz23;
ARCHITECTURE zzz of fp_clz23 IS
type positiontype IS ARRAY (4 DOWNTO 1) OF STD_LOGIC_VECTOR (5 DOWNTO 1);
signal position, positionmux : positiontype;
signal zerogroup, firstzero : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal mannode : STD_LOGIC_VECTOR (6 DOWNTO 1);
component fp_pos51
GENERIC (start: integer := 0);
PORT
(
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (5 DOWNTO 1)
);
end component;
BEGIN
zerogroup(1) <= mantissa(23) OR mantissa(22) OR mantissa(21) OR mantissa(20) OR mantissa(19) OR mantissa(18);
zerogroup(2) <= mantissa(17) OR mantissa(16) OR mantissa(15) OR mantissa(14) OR mantissa(13) OR mantissa(12);
zerogroup(3) <= mantissa(11) OR mantissa(10) OR mantissa(9) OR mantissa(8) OR mantissa(7) OR mantissa(6);
zerogroup(4) <= mantissa(5) OR mantissa(4) OR mantissa(3) OR mantissa(2) OR mantissa(1);
firstzero(1) <= zerogroup(1);
firstzero(2) <= NOT(zerogroup(1)) AND zerogroup(2);
firstzero(3) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND zerogroup(3);
firstzero(4) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND zerogroup(4);
pone: fp_pos51
GENERIC MAP (start=>0)
PORT MAP (ingroup=>mantissa(23 DOWNTO 18),position=>position(1)(5 DOWNTO 1));
ptwo: fp_pos51
GENERIC MAP (start=>6)
PORT MAP (ingroup=>mantissa(17 DOWNTO 12),position=>position(2)(5 DOWNTO 1));
pthr: fp_pos51
GENERIC MAP (start=>12)
PORT MAP (ingroup=>mantissa(11 DOWNTO 6),position=>position(3)(5 DOWNTO 1));
pfiv: fp_pos51
GENERIC MAP (start=>18)
PORT MAP (ingroup=>mannode,position=>position(4)(5 DOWNTO 1));
mannode <= mantissa(5 DOWNTO 1) & '0';
gma: FOR k IN 1 TO 5 GENERATE
positionmux(1)(k) <= position(1)(k) AND firstzero(1);
gmb: FOR j IN 2 TO 4 GENERATE
positionmux(j)(k) <= positionmux(j-1)(k) OR (position(j)(k) AND firstzero(j));
END GENERATE;
END GENERATE;
leading <= positionmux(4)(5 DOWNTO 1);
END zzz;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/fp_clz23.vhd
|
10
|
4166
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CLZ23.VHD ***
--*** ***
--*** Function: 23 bit Count Leading Zeros ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_clz23 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (5 DOWNTO 1)
);
END fp_clz23;
ARCHITECTURE zzz of fp_clz23 IS
type positiontype IS ARRAY (4 DOWNTO 1) OF STD_LOGIC_VECTOR (5 DOWNTO 1);
signal position, positionmux : positiontype;
signal zerogroup, firstzero : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal mannode : STD_LOGIC_VECTOR (6 DOWNTO 1);
component fp_pos51
GENERIC (start: integer := 0);
PORT
(
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (5 DOWNTO 1)
);
end component;
BEGIN
zerogroup(1) <= mantissa(23) OR mantissa(22) OR mantissa(21) OR mantissa(20) OR mantissa(19) OR mantissa(18);
zerogroup(2) <= mantissa(17) OR mantissa(16) OR mantissa(15) OR mantissa(14) OR mantissa(13) OR mantissa(12);
zerogroup(3) <= mantissa(11) OR mantissa(10) OR mantissa(9) OR mantissa(8) OR mantissa(7) OR mantissa(6);
zerogroup(4) <= mantissa(5) OR mantissa(4) OR mantissa(3) OR mantissa(2) OR mantissa(1);
firstzero(1) <= zerogroup(1);
firstzero(2) <= NOT(zerogroup(1)) AND zerogroup(2);
firstzero(3) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND zerogroup(3);
firstzero(4) <= NOT(zerogroup(1)) AND NOT(zerogroup(2)) AND NOT(zerogroup(3)) AND zerogroup(4);
pone: fp_pos51
GENERIC MAP (start=>0)
PORT MAP (ingroup=>mantissa(23 DOWNTO 18),position=>position(1)(5 DOWNTO 1));
ptwo: fp_pos51
GENERIC MAP (start=>6)
PORT MAP (ingroup=>mantissa(17 DOWNTO 12),position=>position(2)(5 DOWNTO 1));
pthr: fp_pos51
GENERIC MAP (start=>12)
PORT MAP (ingroup=>mantissa(11 DOWNTO 6),position=>position(3)(5 DOWNTO 1));
pfiv: fp_pos51
GENERIC MAP (start=>18)
PORT MAP (ingroup=>mannode,position=>position(4)(5 DOWNTO 1));
mannode <= mantissa(5 DOWNTO 1) & '0';
gma: FOR k IN 1 TO 5 GENERATE
positionmux(1)(k) <= position(1)(k) AND firstzero(1);
gmb: FOR j IN 2 TO 4 GENERATE
positionmux(j)(k) <= positionmux(j-1)(k) OR (position(j)(k) AND firstzero(j));
END GENERATE;
END GENERATE;
leading <= positionmux(4)(5 DOWNTO 1);
END zzz;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
bin_Dilation_Operation/ip/Dilation/dp_lnnornd.vhd
|
10
|
3920
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_LNNORND.VHD ***
--*** ***
--*** Function: DP LOG Output Block - Simple ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lnnornd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signln : IN STD_LOGIC;
exponentln : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaln : IN STD_LOGIC_VECTOR (53 DOWNTO 1);
nanin : IN STD_LOGIC;
infinityin : IN STD_LOGIC;
zeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END dp_lnnornd;
ARCHITECTURE rtl OF dp_lnnornd IS
constant expwidth : positive := 11;
constant manwidth : positive := 52;
signal nanff : STD_LOGIC;
signal infinityff : STD_LOGIC;
signal zeroff : STD_LOGIC;
signal signff : STD_LOGIC;
signal mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal setmanzero, setexpzero, setmanmax, setexpmax : STD_LOGIC;
BEGIN
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= '0';
signff <= '0';
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponentff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
signff <= signln;
nanff <= nanin;
infinityff <= infinityin;
zeroff <= zeroin;
-- nan takes precedence (set max)
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (mantissaln(k+1) AND NOT(setmanzero)) OR setmanmax;
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponentff(k) <= (exponentln(k) AND NOT(setexpzero)) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- all set to '1' when true
-- set mantissa to 0 when zero or infinity condition
setmanzero <= NOT(zeroin) OR infinityin;
-- setmantissa to "11..11" when nan
setmanmax <= nanin;
-- set exponent to 0 when zero condition
setexpzero <= NOT(zeroin);
-- set exponent to "11..11" when nan or infinity
setexpmax <= nanin OR infinityin;
--***************
--*** OUTPUTS ***
--***************
signout <= signff;
mantissaout <= mantissaff;
exponentout <= exponentff;
-----------------------------------------------
nanout <= nanff;
overflowout <= infinityff;
zeroout <= zeroff;
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
Dilation/ip/Dilation/fp_mul2s.vhd
|
10
|
5503
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_MUL2S.VHD ***
--*** ***
--*** Function: Fixed Point Multiplier ***
--*** ***
--*** 18-36 bit inputs, 2 pipes ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_mul2s IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT
(
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
END fp_mul2s;
ARCHITECTURE SYN OF fp_mul2s IS
SIGNAL resultnode : STD_LOGIC_VECTOR (widthaa+widthbb DOWNTO 1);
COMPONENT altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (widthaa-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (widthbb-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (widthaa+widthbb-1 DOWNTO 0)
);
END COMPONENT;
BEGIN
ALTMULT_ADD_component : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_register => "UNREGISTERED",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => widthaa,
width_b => widthbb,
width_result => widthaa+widthbb
)
PORT MAP (
dataa => dataaa,
datab => databb,
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => resultnode
);
result <= resultnode(widthaa+widthbb DOWNTO widthaa+widthbb-widthcc+1);
END SYN;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/fp_ldexp.vhd
|
10
|
4857
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FP_LDEXP.VHD ***
--*** ***
--*** Function: Single Precision Load Exponent ***
--*** ***
--*** ldexp(x,n) - x*2^n - IEEE in and out ***
--*** ***
--*** Created 11/09/09 ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_ldexp IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
END fp_ldexp;
ARCHITECTURE rtl OF fp_ldexp IS
signal signinff : STD_LOGIC;
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissainff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal bbff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal signoutff : STD_LOGIC;
signal exponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissaoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal satoutff, zerooutff, nanoutff : STD_LOGIC;
signal satnode, zeronode, nannode : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expzeroin, expmaxin : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzeronode, expmaxnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzeroout, expmaxout : STD_LOGIC;
signal manzeroin : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal manzero, mannonzero : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
signoutff <= '0';
FOR k IN 1 TO 8 LOOP
exponentinff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissainff(k) <= '0';
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
bbff(k) <= '0';
END LOOP;
satoutff <= '0';
zerooutff <= '0';
nanoutff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff <= signin;
exponentinff <= exponentin;
mantissainff <= mantissain;
bbff <= bb(10 DOWNTO 1);
signoutff <= signinff;
FOR k IN 1 TO 8 LOOP
exponentoutff(k) <= (expnode(k) AND NOT(zeronode)) OR satnode OR nannode;
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissaoutff(k) <= (mantissainff(k) AND NOT(zeronode) AND NOT(satnode)) OR nannode;
END LOOP;
satoutff <= satnode;
zerooutff <= zeronode;
nanoutff <= nannode;
END IF;
END IF;
END PROCESS;
expnode <= ("00" & exponentinff) + bbff;
expzeroin(1) <= exponentinff(1);
expmaxin(1) <= exponentinff(1);
gxa: FOR k IN 2 TO 8 GENERATE
expzeroin(k) <= expzeroin(k-1) OR exponentinff(k);
expmaxin(k) <= expmaxin(k-1) AND exponentinff(k);
END GENERATE;
expzeronode(1) <= expnode(1);
expmaxnode(1) <= expnode(1);
gxb: FOR k IN 2 TO 8 GENERATE
expzeronode(k) <= expzeronode(k-1) OR expnode(k);
expmaxnode(k) <= expmaxnode(k-1) AND expnode(k);
END GENERATE;
expzeroout <= NOT(expzeroin(8)) OR (NOT(expzeronode(8)) AND NOT(expnode(9))) OR (expnode(10));
expmaxout <= expmaxin(8) OR (expmaxnode(8) AND NOT(expnode(9))) OR (expnode(9) AND NOT(expnode(10)));
manzeroin(1) <= mantissainff(1);
gma: FOR k IN 2 TO 23 GENERATE
manzeroin(k) <= manzeroin(k-1) OR mantissainff(k);
END GENERATE;
manzero <= NOT(manzeroin(23));
mannonzero <= manzeroin(23);
satnode <= (expmaxin(8) AND NOT(manzeroin(23))) OR expmaxout;
zeronode <= NOT(expzeroin(8)) OR expzeroout;
nannode <= expmaxin(8) AND manzeroin(23);
signout <= signoutff;
exponentout <= exponentoutff;
mantissaout <= mantissaoutff;
satout <= satoutff;
zeroout <= zerooutff;
nanout <= nanoutff;
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
Dilation/ip/Dilation/fp_ldexp.vhd
|
10
|
4857
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** FP_LDEXP.VHD ***
--*** ***
--*** Function: Single Precision Load Exponent ***
--*** ***
--*** ldexp(x,n) - x*2^n - IEEE in and out ***
--*** ***
--*** Created 11/09/09 ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_ldexp IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
END fp_ldexp;
ARCHITECTURE rtl OF fp_ldexp IS
signal signinff : STD_LOGIC;
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissainff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal bbff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal signoutff : STD_LOGIC;
signal exponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissaoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal satoutff, zerooutff, nanoutff : STD_LOGIC;
signal satnode, zeronode, nannode : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expzeroin, expmaxin : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzeronode, expmaxnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal expzeroout, expmaxout : STD_LOGIC;
signal manzeroin : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal manzero, mannonzero : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signinff <= '0';
signoutff <= '0';
FOR k IN 1 TO 8 LOOP
exponentinff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissainff(k) <= '0';
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
bbff(k) <= '0';
END LOOP;
satoutff <= '0';
zerooutff <= '0';
nanoutff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff <= signin;
exponentinff <= exponentin;
mantissainff <= mantissain;
bbff <= bb(10 DOWNTO 1);
signoutff <= signinff;
FOR k IN 1 TO 8 LOOP
exponentoutff(k) <= (expnode(k) AND NOT(zeronode)) OR satnode OR nannode;
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissaoutff(k) <= (mantissainff(k) AND NOT(zeronode) AND NOT(satnode)) OR nannode;
END LOOP;
satoutff <= satnode;
zerooutff <= zeronode;
nanoutff <= nannode;
END IF;
END IF;
END PROCESS;
expnode <= ("00" & exponentinff) + bbff;
expzeroin(1) <= exponentinff(1);
expmaxin(1) <= exponentinff(1);
gxa: FOR k IN 2 TO 8 GENERATE
expzeroin(k) <= expzeroin(k-1) OR exponentinff(k);
expmaxin(k) <= expmaxin(k-1) AND exponentinff(k);
END GENERATE;
expzeronode(1) <= expnode(1);
expmaxnode(1) <= expnode(1);
gxb: FOR k IN 2 TO 8 GENERATE
expzeronode(k) <= expzeronode(k-1) OR expnode(k);
expmaxnode(k) <= expmaxnode(k-1) AND expnode(k);
END GENERATE;
expzeroout <= NOT(expzeroin(8)) OR (NOT(expzeronode(8)) AND NOT(expnode(9))) OR (expnode(10));
expmaxout <= expmaxin(8) OR (expmaxnode(8) AND NOT(expnode(9))) OR (expnode(9) AND NOT(expnode(10)));
manzeroin(1) <= mantissainff(1);
gma: FOR k IN 2 TO 23 GENERATE
manzeroin(k) <= manzeroin(k-1) OR mantissainff(k);
END GENERATE;
manzero <= NOT(manzeroin(23));
mannonzero <= manzeroin(23);
satnode <= (expmaxin(8) AND NOT(manzeroin(23))) OR expmaxout;
zeronode <= NOT(expzeroin(8)) OR expzeroout;
nannode <= expmaxin(8) AND manzeroin(23);
signout <= signoutff;
exponentout <= exponentoutff;
mantissaout <= mantissaoutff;
satout <= satoutff;
zeroout <= zerooutff;
nanout <= nanoutff;
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/hcc_castytof.vhd
|
10
|
3181
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTYTOF.VHD ***
--*** ***
--*** Function: Cast Internal Double to ***
--*** External Single ***
--*** ***
--*** 06/03/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castytof IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32;
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castytof;
ARCHITECTURE rtl OF hcc_castytof IS
signal midnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
signal satnode, zipnode : STD_LOGIC;
component hcc_castytox
GENERIC (
roundconvert : integer := 1; -- global switch - round all conversions when '1'
mantissa : positive := 32
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castxtof
GENERIC (
mantissa : positive := 32; -- 32 or 36
normspeed : positive := 2 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
one: hcc_castytox
GENERIC MAP (roundconvert=>roundconvert,mantissa=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,aasat=>aasat,aazip=>aazip,
cc=>midnode,ccsat=>satnode,cczip=>zipnode);
two: hcc_castxtof
GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>midnode,aasat=>satnode,aazip=>zipnode,
cc=>cc);
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
bin_Dilation_Operation/ip/Dilation/hcc_divfp2x.vhd
|
10
|
22387
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DIVFP2X.VHD ***
--*** ***
--*** Function: Internal format double divide - ***
--*** unsigned mantissa ***
--*** ***
--*** Uses new multiplier based divider core ***
--*** from floating point library ***
--*** ***
--*** 24/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 23/04/09 - added NAN support ***
--*** 27/04/09 - added SIII/SIV support ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** ***
--*** Stratix II ***
--*** Latency = 20 + 4*doublespeed + ***
--*** doublespeed*roundconvert (Y) ***
--*** Latency = 20 + 4*doublespeed (F) ***
--*** Latency = 20 + 4*doublespeed + ***
--*** roundconvert*(1+doublespeed) (ieee) ***
--*** ***
--*** Stratix III/IV ***
--*** Latency = 19 + 2*doublespeed + ***
--*** doublespeed*roundconvert (Y) ***
--*** Latency = 19 + 2*doublespeed (F) ***
--*** Latency = 19 + 2*doublespeed + ***
--*** roundconvert*(1+doublespeed) (ieee) ***
--***************************************************
ENTITY hcc_divfp2x IS
GENERIC (
ieeeoutput : integer := 0; -- 1 = ieee754 (1/u52/11)
xoutput : integer := 1; -- 1 = double x format (s64/13)
divoutput : integer := 1; -- output to another multiplier or divider (S'1'u54/13)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
doublespeed : integer := 0; -- global switch - '0' unpiped adders, '1' piped adders for doubles
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (67 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64+13*xoutput+3*divoutput DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_divfp2x;
ARCHITECTURE rtl OF hcc_divfp2x IS
-- SII: div_core latency 19+4*doublespeed
-- SIII/IV: div_core latency 18+2*doublespeed
constant midlatency : positive := 18+4*doublespeed - device - 2*device*doublespeed;
type divinexpfftype IS ARRAY (midlatency DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type divexpdelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
-- divider core interface
signal divinaaman, divinbbman : STD_LOGIC_VECTOR(53 DOWNTO 1);
signal divinaaexp, divinbbexp : STD_LOGIC_VECTOR(13 DOWNTO 1);
signal divinaaexpff, divinbbexpff : STD_LOGIC_VECTOR(13 DOWNTO 1);
signal divinaasat, divinaazip, divinaanan : STD_LOGIC;
signal divinbbsat, divinbbzip, divinbbnan : STD_LOGIC;
signal divinaasatff, divinaazipff, divinaananff : STD_LOGIC;
signal divinbbsatff, divinbbzipff, divinbbnanff : STD_LOGIC;
signal divinaasign, divinbbsign : STD_LOGIC;
signal divinaasignff, divinbbsignff : STD_LOGIC;
signal divinexpff : divinexpfftype;
signal divinsignff : STD_LOGIC_VECTOR (midlatency DOWNTO 1);
signal divinsatff, divinzipff, divinnanff : STD_LOGIC_VECTOR (midlatency DOWNTO 1);
signal dividend, divisor : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal divmannode : STD_LOGIC_VECTOR (55 DOWNTO 1);
-- output section (x out)
signal signeddivmannode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal divroundnode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal divmanout : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal divymanff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal divyexpff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal divysatbitff, divyzipbitff, divynanbitff : STD_LOGIC;
signal divexpplus : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal divyexpdelff : divexpdelfftype;
signal divysatdelff, divyzipdelff, divynandelff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal divsatbase, divzipbase : STD_LOGIC;
-- output section (divout)
signal normmannode : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal divdivmanff : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal divdivexpff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal divdivsatff, divdivzipff, divdivnanff : STD_LOGIC;
-- output section (ieeeout)
signal normsignff, normsatff, normzipff, normnanff : STD_LOGIC;
signal normalize : STD_LOGIC;
signal normalnode : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal normalff : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal normalexpff : STD_LOGIC_VECTOR (13 DOWNTO 1);
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
-- SII: latency 19+4*doublespeed
-- SIII/IV: latency 18+2*doublespeed
component dp_div_core IS
GENERIC (
doublespeed : integer := 0; -- 0/1
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dividend : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
divisor : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (55 DOWNTO 1)
);
end component;
-- latency 1
component hcc_divnornd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (53 DOWNTO 1); -- includes roundbit
satin, zipin, nanin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1)
);
end component;
-- latency 2
component hcc_divrnd
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (53 DOWNTO 1); -- includes roundbit
satin, zipin, nanin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1)
);
end component;
-- latency 3
component hcc_divrndpipe
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (13 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (53 DOWNTO 1); -- includes roundbit
satin, zipin, nanin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
--**************************************************
--*** ***
--*** Input Section ***
--*** ***
--**************************************************
--********************************************************
--*** NOTE THAT THE SIGN BIT IS PACKED IN THE MSB OF ***
--*** THE MANTISSA ***
--********************************************************
divinaaman <= aa(66 DOWNTO 14);
divinaaexp <= aa(13 DOWNTO 1);
divinbbman <= bb(66 DOWNTO 14);
divinbbexp <= bb(13 DOWNTO 1);
divinaasat <= aasat;
divinbbsat <= bbsat;
divinaazip <= aazip;
divinbbzip <= bbzip;
divinaanan <= aanan;
divinbbnan <= bbnan;
-- signbits packed in MSB of mantissas
divinaasign <= aa(67);
divinbbsign <= bb(67);
--**************************************************
--*** ***
--*** Divider Section ***
--*** ***
--**************************************************
dividend <= divinaaman & '0';
divisor <= divinbbman & '0';
-- SII: latency 19+4*doublespeed
-- SIII/IV: latency 18+2*doublespeed
div: dp_div_core
GENERIC MAP (doublespeed=>doublespeed,doubleaccuracy=>doubleaccuracy,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dividend=>dividend,divisor=>divisor,
quotient=>divmannode);
pda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
divinaaexpff(k) <= '0';
divinbbexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO midlatency LOOP
FOR j IN 1 TO 13 LOOP
divinexpff(k)(j) <= '0';
END LOOP;
END LOOP;
divinaasignff <= '0';
divinbbsignff <= '0';
divinaasatff <= '0';
divinbbsatff <= '0';
divinaazipff <= '0';
divinbbzipff <= '0';
divinaananff <= '0';
divinbbnanff <= '0';
FOR k IN 1 TO midlatency LOOP
divinsignff(k) <= '0';
divinsatff(k) <= '0';
divinzipff(k) <= '0';
divinnanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
divinaaexpff <= divinaaexp;
divinbbexpff <= divinbbexp;
divinexpff(1)(13 DOWNTO 1) <= divinaaexpff - divinbbexpff;
divinexpff(2)(13 DOWNTO 1) <= divinexpff(1)(13 DOWNTO 1) + "0001111111111";
FOR k IN 3 TO midlatency LOOP
divinexpff(k)(13 DOWNTO 1) <= divinexpff(k-1)(13 DOWNTO 1);
END LOOP;
divinaasignff <= divinaasign;
divinbbsignff <= divinbbsign;
divinsignff(1) <= divinaasignff XOR divinbbsignff;
FOR k IN 2 TO midlatency LOOP
divinsignff(k) <= divinsignff(k-1);
END LOOP;
divinaasatff <= divinaasat;
divinbbsatff <= divinbbsat;
divinaazipff <= divinaazip;
divinbbzipff <= divinbbzip;
divinaananff <= divinaanan;
divinbbnanff <= divinbbnan;
-- special condition: infinity = x/0
divinsatff(1) <= (divinaasatff OR divinbbsatff) OR
(NOT(divinaazipff) AND divinbbzipff);
divinzipff(1) <= divinaazipff;
-- 0/0 or infinity/infinity is invalid OP, NAN out
divinnanff(1) <= divinaananff OR divinbbnanff OR
(divinaazipff AND divinbbzipff) OR
(divinaasatff AND divinbbsatff);
FOR k IN 2 TO midlatency LOOP
divinsatff(k) <= divinsatff(k-1);
divinzipff(k) <= divinzipff(k-1);
divinnanff(k) <= divinnanff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--**************************************************
--*** ***
--*** Output Section ***
--*** ***
--**************************************************
--********************************************************
--*** internal format output, convert back to signed ***
--*** no need for fine normalization ***
--********************************************************
goya: IF (xoutput = 1) GENERATE
-- output either "01XXXX..RR" (<1) or "1XXXX..RR" (>=1)
-- if <1, SSSSSS1'manSSSSS
-- if >1, SSSSS1'manSSSS
goyb: FOR k IN 1 TO 4 GENERATE
signeddivmannode(k) <= divinsignff(midlatency);
END GENERATE;
goyc: FOR k IN 1 TO 55 GENERATE
signeddivmannode(k+4) <= divmannode(k) XOR divinsignff(midlatency);
END GENERATE;
goyd: FOR k IN 60 TO 64 GENERATE
signeddivmannode(k) <= divinsignff(midlatency);
END GENERATE;
goye: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
goyf: IF (roundconvert = 0) GENERATE
divroundnode <= signeddivmannode;
END GENERATE;
goyg: IF (roundconvert = 1) GENERATE
divroundnode <= signeddivmannode + (zerovec(63 DOWNTO 1) & divinsignff(midlatency));
END GENERATE;
poxa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
divymanff(k) <= '0';
END LOOP;
FOR j IN 1 TO 13 LOOP
divyexpff(j) <= '0';
END LOOP;
divysatbitff <= '0';
divyzipbitff <= '0';
divynanbitff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
divymanff <= divroundnode;
divyexpff <= divinexpff(midlatency)(13 DOWNTO 1);
divysatbitff <= divinsatff(midlatency);
divyzipbitff <= divinzipff(midlatency);
divynanbitff <= divinnanff(midlatency);
END IF;
END IF;
END PROCESS;
cc(77 DOWNTO 14) <= divymanff;
cc(13 DOWNTO 1) <= divyexpff;
ccsat <= divysatbitff;
cczip <= divyzipbitff;
ccnan <= divynanbitff;
END GENERATE;
goyh: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
goyi: IF (synthesize = 0) GENERATE
rndaddone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>signeddivmannode,bb=>zerovec(64 DOWNTO 1),carryin=>divinsignff(midlatency),
cc=>divmanout);
END GENERATE;
goyj: IF (synthesize = 1) GENERATE
rndaddtwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>signeddivmannode,bb=>zerovec(64 DOWNTO 1),carryin=>divinsignff(midlatency),
cc=>divmanout);
END GENERATE;
poxb: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR j IN 1 TO 13 LOOP
divyexpdelff(1)(j) <= '0';
divyexpdelff(2)(j) <= '0';
END LOOP;
divysatdelff <= "00";
divyzipdelff <= "00";
divynandelff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
divyexpdelff(1)(13 DOWNTO 1) <= divinexpff(midlatency)(13 DOWNTO 1);
divyexpdelff(2)(13 DOWNTO 1) <= divyexpdelff(1)(13 DOWNTO 1);
divysatdelff(1) <= divinsatff(midlatency);
divysatdelff(2) <= divysatdelff(1);
divyzipdelff(1) <= divinzipff(midlatency);
divyzipdelff(2) <= divyzipdelff(1);
divynandelff(1) <= divinnanff(midlatency);
divynandelff(2) <= divynandelff(1);
END IF;
END IF;
END PROCESS;
cc(77 DOWNTO 14) <= divmanout;
cc(13 DOWNTO 1) <= divyexpdelff(2)(13 DOWNTO 1);
ccsat <= divysatdelff(2);
cczip <= divyzipdelff(2);
ccnan <= divynandelff(2);
END GENERATE;
END GENERATE;
--**************************************************
--*** if output to another multiplier or divider ***
--*** use output directly ***
--**************************************************
--*** NOTE: roundconvert options must still be added
gofa: IF (divoutput = 1) GENERATE
-- [55:1] output either "01XXXX..RR" (<1) or "1XXXX..RR" (>=1)
normalize <= NOT(divmannode(55));
gofb: FOR k IN 1 TO 53 GENERATE
normmannode(k) <= (divmannode(k+1) AND normalize) OR
(divmannode(k+2) AND NOT(normalize));
END GENERATE;
-- exp[54:1] always '1'manR
poda: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 54 LOOP
divdivmanff(k) <= '0';
END LOOP;
FOR j IN 1 TO 13 LOOP
divdivexpff(j) <= '0';
END LOOP;
divdivsatff <= '0';
divdivzipff <= '0';
divdivnanff <= '0';
ELSIF (rising_edge(sysclk)) THEN
divdivmanff <= divinsignff(midlatency) & normmannode;
-- 20/05/09 add normalize adjustement
divdivexpff <= divinexpff(midlatency)(13 DOWNTO 1) - (zerovec(12 DOWNTO 1) & normalize);
divdivsatff <= divinsatff(midlatency);
divdivzipff <= divinzipff(midlatency);
divdivnanff <= divinnanff(midlatency);
END IF;
END PROCESS;
cc(67 DOWNTO 14) <= divdivmanff;
cc(13 DOWNTO 1) <= divdivexpff;
ccsat <= divdivsatff;
cczip <= divdivzipff;
ccnan <= divdivnanff;
END GENERATE;
--********************************************************
--*** if output directly out of datapath, convert here ***
--*** input to multiplier always "01XXX" format, so ***
--*** just 1 bit normalization required ***
--********************************************************
goea: IF (ieeeoutput = 1) GENERATE -- ieee754 out of datapath, do conversion
-- output either "01XXXX..RR" (<2) or "1XXXX..RR" (>=2), need to make output
-- 01XXXX
normalize <= NOT(divmannode(55));
goeb: FOR k IN 1 TO 54 GENERATE -- format "01"[52..1]R
normalnode(k) <= (divmannode(k+1) AND NOT(normalize)) OR
(divmannode(k) AND normalize);
END GENERATE;
poea: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
normsignff <= '0';
normsatff <= '0';
normzipff <= '0';
normnanff <= '0';
FOR k IN 1 TO 54 LOOP
normalff(k) <= '0';
END LOOP;
FOR k IN 1 TO 13 LOOP
normalexpff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
normsignff <= divinsignff(midlatency);
normsatff <= divinsatff(midlatency);
normzipff <= divinzipff(midlatency);
normnanff <= divinnanff(midlatency);
normalff <= normalnode;
normalexpff <= divinexpff(midlatency)(13 DOWNTO 1) -
(zerovec(12 DOWNTO 1) & normalize);
END IF;
END IF;
END PROCESS;
goec: IF (roundconvert = 0) GENERATE
norndout: hcc_divnornd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>normsignff,
exponentin=>normalexpff,
mantissain=>normalff(53 DOWNTO 1),
satin=>normsatff,
zipin=>normzipff,
nanin=>normnanff,
signout=>cc(64),exponentout=>cc(63 DOWNTO 53),mantissaout=>cc(52 DOWNTO 1));
-- dummy only
ccsat <= '0';
cczip <= '0';
ccnan <= '0';
END GENERATE;
goed: IF ((roundconvert = 1) AND (doublespeed = 0)) GENERATE
rndout: hcc_divrnd
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>normsignff,
exponentin=>normalexpff,
mantissain=>normalff(53 DOWNTO 1),
satin=>normsatff,
zipin=>normzipff,
nanin=>normnanff,
signout=>cc(64),exponentout=>cc(63 DOWNTO 53),mantissaout=>cc(52 DOWNTO 1));
-- dummy only
ccsat <= '0';
cczip <= '0';
ccnan <= '0';
END GENERATE;
goee: IF ((roundconvert = 1) AND (doublespeed = 1)) GENERATE
rndpipout: hcc_divrndpipe
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>normsignff,
exponentin=>normalexpff,
mantissain=>normalff(53 DOWNTO 1),
satin=>normsatff,
zipin=>normzipff,
nanin=>normnanff,
signout=>cc(64),exponentout=>cc(63 DOWNTO 53),mantissaout=>cc(52 DOWNTO 1));
-- dummy only
ccsat <= '0';
cczip <= '0';
ccnan <= '0';
END GENERATE;
END GENERATE;
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/fp_sincos_fused.vhd
|
10
|
17997
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_SIN.VHD ***
--*** ***
--*** Function: Single Precision SIN Core ***
--*** ***
--*** 10/01/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. Input < 0.5 radians, take cos(pi/2-input)***
--*** 2. latency = depth + range_depth (11) + 7 ***
--*** (1 more than cos) ***
--***************************************************
ENTITY fp_sincos_fused IS
GENERIC (
device : integer := 0;
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout_sin : OUT STD_LOGIC;
exponentout_sin : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout_sin : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
signout_cos : OUT STD_LOGIC;
exponentout_cos : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout_cos : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_sincos_fused;
ARCHITECTURE rtl of fp_sincos_fused IS
constant cordic_width : positive := width;
constant cordic_depth : positive := depth;
constant range_depth : positive := 11;
signal piovertwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal input_number : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal input_number_delay : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentcheck : STD_LOGIC_VECTOR (9 DOWNTO 1);
-- range reduction
signal circle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal negcircle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrantsign_sin, quadrantsign_cos, quadrantselect : STD_LOGIC;
signal positive_quadrant, negative_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fraction_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal one_term : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrant : STD_LOGIC_VECTOR (34 DOWNTO 1);
-- circle to radians mult
signal radiansnode : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal indexcheck : STD_LOGIC_VECTOR (16 DOWNTO 1);
signal indexbit : STD_LOGIC;
signal signinff : STD_LOGIC_VECTOR (range_depth DOWNTO 1);
signal selectoutputff : STD_LOGIC_VECTOR (range_depth+cordic_depth+5 DOWNTO 1);
signal signcalcff_sin,signcalcff_cos : STD_LOGIC_VECTOR (cordic_depth+6 DOWNTO 1);
signal quadrant_sumff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal select_sincosff : STD_LOGIC_VECTOR (4+cordic_depth DOWNTO 1);
signal fixed_sin : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal fixed_sinnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fixed_sinff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fixed_cos : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal fixed_cosnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fixed_cosff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal countnode_sin : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal countff_sin : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal mantissanormnode_sin : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissanormff_sin : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentnormnode_sin : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentnormff_sin : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal overflownode_sin : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal mantissaoutff_sin : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentoutff_sin : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal signoutff_sin : STD_LOGIC;
signal countnode_cos : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal countff_cos : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal mantissanormnode_cos : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissanormff_cos : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentnormnode_cos : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentnormff_cos : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal overflownode_cos : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal mantissaoutff_cos : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentoutff_cos : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal signoutff_cos : STD_LOGIC;
component fp_range1
GENERIC (device : integer);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
circle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
negcircle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_cordic_m1_fused
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sin_out : OUT STD_LOGIC_VECTOR (width DOWNTO 1);
cos_out : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_clz36 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- pi/2 = 1.57
piovertwo <= x"c90fdaa22";
zerovec <= x"000000000";
--*** SIN(X) = X when exponent < 115 ***
input_number <= signin & exponentin & mantissain;
-- level 1 in, level range_depth+cordic_depth+7 out
cdin: fp_del
GENERIC MAP (width=>32,pipes=>range_depth+cordic_depth+6)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>input_number,
cc=>input_number_delay);
--*** RANGE REDUCTION ***
crr: fp_range1
GENERIC MAP(device=>device)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signin,exponentin=>exponentin,mantissain=>mantissain,
circle=>circle,negcircle=>negcircle);
quadrantsign_sin <= circle(36); -- sin negative in quadrants 3&4
quadrantsign_cos <= (NOT(circle(36)) AND circle(35)) OR
(circle(36) AND NOT(circle(35))); -- cos negative in quadrants 2&3
quadrantselect <= circle(35); -- sin (1-x) in quadants 2&4
gra: FOR k IN 1 TO 34 GENERATE
quadrant(k) <= (circle(k) AND NOT(quadrantselect)) OR
(negcircle(k) AND quadrantselect);
END GENERATE;
-- if quadrant >0.5 (when quadrant(34) = 1), use quadrant, else use 1-quadrant, and take cos rather than sin
positive_quadrant <= '0' & quadrant & '0';
gnqa: FOR k IN 1 TO 36 GENERATE
negative_quadrant(k) <= NOT(positive_quadrant(k));
fraction_quadrant(k) <= (positive_quadrant(k) AND quadrant(34)) OR
(negative_quadrant(k) AND NOT(quadrant(34)));
END GENERATE;
one_term <= NOT(quadrant(34)) & zerovec(35 DOWNTO 1); -- 0 if positive quadrant
pfa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO range_depth LOOP
signinff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth+6 LOOP
signcalcff_sin(k) <= '0';
signcalcff_cos(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentinff(k) <= '0';
END LOOP;
FOR k IN 1 TO range_depth+cordic_depth+5 LOOP
selectoutputff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
quadrant_sumff(k) <= '0';
END LOOP;
FOR k IN 1 TO 4+cordic_depth LOOP
select_sincosff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff(1) <= signin;
FOR k IN 2 TO range_depth LOOP
signinff(k) <= signinff(k-1);
END LOOP;
-- level range_depth+1 to range_depth+cordic_depth+6
signcalcff_sin(1) <= quadrantsign_sin XOR signinff(range_depth);
FOR k IN 2 TO cordic_depth+6 LOOP
signcalcff_sin(k) <= signcalcff_sin(k-1);
END LOOP;
signcalcff_cos(1) <= quadrantsign_cos;
FOR k IN 2 TO cordic_depth+6 LOOP
signcalcff_cos(k) <= signcalcff_cos(k-1);
END LOOP;
exponentinff <= exponentin; -- level 1
selectoutputff(1) <= exponentcheck(9); -- level 2 to range_depth+cordic_depth+6
FOR k IN 2 TO range_depth+cordic_depth+5 LOOP
selectoutputff(k) <= selectoutputff(k-1);
END LOOP;
-- range 0-0.9999
quadrant_sumff <= one_term + fraction_quadrant + NOT(quadrant(34)); -- level range_depth+1
-- level range depth+1 to range_depth+4
-- Here is an interesting thing - depending on the quadrant the input is in, computation
-- or a sin or cosine can use sin or cosine result. What this means is that we may have to swap
-- results when they come out of the cordic block.
select_sincosff(1) <= quadrant(34);
FOR k IN 2 TO 4+cordic_depth LOOP
select_sincosff(k) <= select_sincosff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- if exponent < 115, sin = input
exponentcheck <= ('0' & exponentinff) - ('0' & x"73");
-- levels range_depth+2,3,4
cmul: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>cordic_width,
pipes=>3,synthesize=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>quadrant_sumff,databb=>piovertwo,
result=>radiansnode);
indexcheck(1) <= radiansnode(cordic_width-1);
gica: FOR k IN 2 TO 16 GENERATE
indexcheck(k) <= indexcheck(k-1) OR radiansnode(cordic_width-k);
END GENERATE;
-- for safety, give an extra bit of space
indexbit <= NOT(indexcheck(indexpoint+1));
ccc: fp_cordic_m1_fused
GENERIC MAP (width=>cordic_width,depth=>cordic_depth,indexpoint=>indexpoint)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radians=>radiansnode,
indexbit=>indexbit,
sin_out=>fixed_sin,
cos_out=>fixed_cos);
gfxa: IF (width < 36) GENERATE
fixed_sinnode <= (fixed_sin & zerovec(36-width DOWNTO 1)) when (select_sincosff(4+cordic_depth) = '1') else (fixed_cos & zerovec(36-width DOWNTO 1));
fixed_cosnode <= (fixed_cos & zerovec(36-width DOWNTO 1)) when (select_sincosff(4+cordic_depth) = '1') else (fixed_sin & zerovec(36-width DOWNTO 1));
END GENERATE;
gfxb: IF (width = 36) GENERATE
fixed_sinnode <= fixed_sin when (select_sincosff(4+cordic_depth) = '1') else fixed_cos;
fixed_cosnode <= fixed_cos when (select_sincosff(4+cordic_depth) = '1') else fixed_sin;
END GENERATE;
clz1: fp_clz36
PORT MAP (mantissa=>fixed_sinnode,leading=>countnode_sin);
clz2: fp_clz36
PORT MAP (mantissa=>fixed_cosnode,leading=>countnode_cos);
sft1: fp_lsft36
PORT MAP (inbus=>fixed_sinff,shift=>countff_sin,
outbus=>mantissanormnode_sin);
sft2: fp_lsft36
PORT MAP (inbus=>fixed_cosff,shift=>countff_cos,
outbus=>mantissanormnode_cos);
-- maximum sin or cos = 1.0 = 1.0e127 single precision
-- 1e128 - 1 (leading one) gives correct number
exponentnormnode_sin <= "10000000" - ("00" & countff_sin);
exponentnormnode_cos <= "10000000" - ("00" & countff_cos);
overflownode_sin(1) <= mantissanormnode_sin(12);
gova1: FOR k IN 2 TO 24 GENERATE
overflownode_sin(k) <= mantissanormnode_sin(k+11) AND overflownode_sin(k-1);
END GENERATE;
overflownode_cos(1) <= mantissanormnode_cos(12);
gova2: FOR k IN 2 TO 24 GENERATE
overflownode_cos(k) <= mantissanormnode_cos(k+11) AND overflownode_cos(k-1);
END GENERATE;
-- OUTPUT
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
fixed_sinff(k) <= '0';
fixed_cosff(k) <= '0';
END LOOP;
countff_sin <= "000000";
countff_cos <= "000000";
FOR k IN 1 TO 23 LOOP
mantissanormff_sin(k) <= '0';
mantissaoutff_sin(k) <= '0';
mantissanormff_cos(k) <= '0';
mantissaoutff_cos(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentnormff_sin(k) <= '0';
exponentoutff_sin(k) <= '0';
exponentnormff_cos(k) <= '0';
exponentoutff_cos(k) <= '0';
END LOOP;
signoutff_sin <= '0';
signoutff_cos <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
fixed_sinff <= fixed_sinnode; -- level range_depth+cordic_depth+5
fixed_cosff <= fixed_cosnode; -- level range_depth+cordic_depth+5
countff_sin <= countnode_sin; -- level range_depth+4+cordic_depth+5
countff_cos <= countnode_cos; -- level range_depth+4+cordic_depth+5
-- level range_depth+cordic_depth+6
mantissanormff_cos <= mantissanormnode_cos(35 DOWNTO 13) + mantissanormnode_cos(12);
exponentnormff_cos <= exponentnormnode_cos(8 DOWNTO 1) + overflownode_cos(24);
mantissanormff_sin <= mantissanormnode_sin(35 DOWNTO 13) + mantissanormnode_sin(12);
exponentnormff_sin <= exponentnormnode_sin(8 DOWNTO 1) + overflownode_sin(24);
-- level range_depth+cordic_depth+7
FOR k IN 1 TO 23 LOOP
mantissaoutff_sin(k) <= (mantissanormff_sin(k) AND NOT(selectoutputff(range_depth+cordic_depth+5))) OR
(input_number_delay(k) AND selectoutputff(range_depth+cordic_depth+5));
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentoutff_sin(k) <= (exponentnormff_sin(k) AND NOT(selectoutputff(range_depth+cordic_depth+5))) OR
(input_number_delay(k+23) AND selectoutputff(range_depth+cordic_depth+5));
END LOOP;
signoutff_sin <= (signcalcff_sin(cordic_depth+6) AND NOT(selectoutputff(range_depth+cordic_depth+5))) OR
(input_number_delay(32) AND selectoutputff(range_depth+cordic_depth+5));
mantissaoutff_cos <= mantissanormff_cos;
exponentoutff_cos <= exponentnormff_cos;
signoutff_cos <= signcalcff_cos(cordic_depth+6);
END IF;
END IF;
END PROCESS;
mantissaout_sin <= mantissaoutff_sin;
exponentout_sin <= exponentoutff_sin;
signout_sin <= signoutff_sin;
mantissaout_cos <= mantissaoutff_cos;
exponentout_cos <= exponentoutff_cos;
signout_cos <= signoutff_cos;
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
bin_Dilation_Operation/ip/Dilation/dp_expnornd.vhd
|
10
|
4802
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** DP_EXPNORND.VHD ***
--*** ***
--*** Function: DP Exponent Output Block - ***
--*** Simple ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_expnornd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaexp : IN STD_LOGIC_VECTOR (53 DOWNTO 1); -- includes roundbit
nanin : IN STD_LOGIC;
rangeerror : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
underflowout : OUT STD_LOGIC
);
END dp_expnornd;
ARCHITECTURE rtl OF dp_expnornd IS
constant expwidth : positive := 11;
constant manwidth : positive := 52;
signal nanff : STD_LOGIC;
signal overflownode, underflownode : STD_LOGIC;
signal overflowff, underflowff : STD_LOGIC;
signal mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal infinitygen : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerogen : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= '0';
overflowff <= '0';
underflowff <= '0';
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponentff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff <= nanin;
overflowff <= overflownode;
underflowff <= underflownode;
-- nan takes precedence (set max)
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (mantissaexp(k+1) AND setmanzero) OR setmanmax;
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponentff(k) <= (exponentexp(k) AND setexpzero) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- infinity if exponent == 255
infinitygen(1) <= exponentexp(1);
gia: FOR k IN 2 TO expwidth GENERATE
infinitygen(k) <= infinitygen(k-1) AND exponentexp(k);
END GENERATE;
-- zero if exponent == 0
zerogen(1) <= exponentexp(1);
gza: FOR k IN 2 TO expwidth GENERATE
zerogen(k) <= zerogen(k-1) OR exponentexp(k);
END GENERATE;
-- trap any other overflow errors
-- when sign = 0 and rangeerror = 1, overflow
-- when sign = 1 and rangeerror = 1, underflow
overflownode <= NOT(signin) AND rangeerror;
underflownode <= signin AND rangeerror;
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(infinitygen(expwidth)) AND zerogen(expwidth) AND NOT(rangeerror);
-- setmantissa to "11..11" when nan
setmanmax <= nanin;
-- set exponent to 0 when zero condition
setexpzero <= zerogen(expwidth);
-- set exponent to "11..11" when nan, infinity, or divide by 0
setexpmax <= nanin OR infinitygen(expwidth) OR rangeerror;
--***************
--*** OUTPUTS ***
--***************
signout <= '0';
mantissaout <= mantissaff;
exponentout <= exponentff;
-----------------------------------------------
nanout <= nanff;
overflowout <= overflowff;
underflowout <= underflowff;
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
bin_Dilation_Operation/ip/Dilation/fp_tan_s5.vhd
|
10
|
744474
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_tan_s5
-- VHDL created on Wed Mar 13 12:44:30 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_tan_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_tan_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpTanTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpTanTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid8_fpTanTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid22_fpTanTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid23_fpTanTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShift_uid24_fpTanTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid25_fpTanTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid26_fpTanTest_q : std_logic_vector (7 downto 0);
signal cstZwShiftP1_uid27_fpTanTest_q : std_logic_vector (13 downto 0);
signal cstNaNwF_uid32_fpTanTest_q : std_logic_vector (22 downto 0);
signal cstZwShiftPwFRR_uid35_fpTanTest_q : std_logic_vector (64 downto 0);
signal cPi_uid70_fpTanTest_q : std_logic_vector (25 downto 0);
signal p_uid72_fpTanTest_s : std_logic_vector (0 downto 0);
signal p_uid72_fpTanTest_q : std_logic_vector (25 downto 0);
signal expPSin_uid75_fpTanTest_s : std_logic_vector (0 downto 0);
signal expPSin_uid75_fpTanTest_q : std_logic_vector (7 downto 0);
signal multSinOp2_uid90_fpTanTest_s : std_logic_vector (0 downto 0);
signal multSinOp2_uid90_fpTanTest_q : std_logic_vector (25 downto 0);
signal mulSin_uid91_fpTanTest_a : std_logic_vector (25 downto 0);
signal mulSin_uid91_fpTanTest_b : std_logic_vector (25 downto 0);
signal mulSin_uid91_fpTanTest_s1 : std_logic_vector (51 downto 0);
signal mulSin_uid91_fpTanTest_pr : UNSIGNED (51 downto 0);
signal mulSin_uid91_fpTanTest_q : std_logic_vector (51 downto 0);
signal mulCos_uid104_fpTanTest_a : std_logic_vector (25 downto 0);
signal mulCos_uid104_fpTanTest_b : std_logic_vector (25 downto 0);
signal mulCos_uid104_fpTanTest_s1 : std_logic_vector (51 downto 0);
signal mulCos_uid104_fpTanTest_pr : UNSIGNED (51 downto 0);
signal mulCos_uid104_fpTanTest_q : std_logic_vector (51 downto 0);
signal excSelSin_uid118_fpTanTest_q : std_logic_vector(1 downto 0);
signal InvSinXIsXRR_uid127_fpTanTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsXRR_uid127_fpTanTest_q : std_logic_vector(0 downto 0);
signal signR_uid129_fpTanTest_a : std_logic_vector(0 downto 0);
signal signR_uid129_fpTanTest_b : std_logic_vector(0 downto 0);
signal signR_uid129_fpTanTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid132_fpTanTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid132_fpTanTest_q : std_logic_vector(0 downto 0);
signal expSelectorCos_uid141_fpTanTest_q : std_logic_vector(1 downto 0);
signal InvCosOne_uid145_fpTanTest_a : std_logic_vector(0 downto 0);
signal InvCosOne_uid145_fpTanTest_q : std_logic_vector(0 downto 0);
signal signRCond2_uid148_fpTanTest_a : std_logic_vector(0 downto 0);
signal signRCond2_uid148_fpTanTest_b : std_logic_vector(0 downto 0);
signal signRCond2_uid148_fpTanTest_c : std_logic_vector(0 downto 0);
signal signRCond2_uid148_fpTanTest_d : std_logic_vector(0 downto 0);
signal signRCond2_uid148_fpTanTest_q : std_logic_vector(0 downto 0);
signal signRCond1_uid153_fpTanTest_a : std_logic_vector(0 downto 0);
signal signRCond1_uid153_fpTanTest_b : std_logic_vector(0 downto 0);
signal signRCond1_uid153_fpTanTest_c : std_logic_vector(0 downto 0);
signal signRCond1_uid153_fpTanTest_d : std_logic_vector(0 downto 0);
signal signRCond1_uid153_fpTanTest_q : std_logic_vector(0 downto 0);
signal xBranch_uid184_rrx_uid34_fpTanTest_a : std_logic_vector(10 downto 0);
signal xBranch_uid184_rrx_uid34_fpTanTest_b : std_logic_vector(10 downto 0);
signal xBranch_uid184_rrx_uid34_fpTanTest_o : std_logic_vector (10 downto 0);
signal xBranch_uid184_rrx_uid34_fpTanTest_cin : std_logic_vector (0 downto 0);
signal xBranch_uid184_rrx_uid34_fpTanTest_n : std_logic_vector (0 downto 0);
signal ZerosGB_uid199_rrx_uid34_fpTanTest_q : std_logic_vector (29 downto 0);
signal leftShiftStage0Idx1Pad4_uid206_fxpX_uid48_fpTanTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid212_fxpX_uid48_fpTanTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid220_fxpX_uid48_fpTanTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid223_fxpX_uid48_fpTanTest_q : std_logic_vector (2 downto 0);
signal zs_uid229_lzcZSin_uid65_fpTanTest_q : std_logic_vector (63 downto 0);
signal vCount_uid231_lzcZSin_uid65_fpTanTest_a : std_logic_vector(63 downto 0);
signal vCount_uid231_lzcZSin_uid65_fpTanTest_b : std_logic_vector(63 downto 0);
signal vCount_uid231_lzcZSin_uid65_fpTanTest_q : std_logic_vector(0 downto 0);
signal mO_uid232_lzcZSin_uid65_fpTanTest_q : std_logic_vector (62 downto 0);
signal zs_uid237_lzcZSin_uid65_fpTanTest_q : std_logic_vector (31 downto 0);
signal vCount_uid239_lzcZSin_uid65_fpTanTest_a : std_logic_vector(31 downto 0);
signal vCount_uid239_lzcZSin_uid65_fpTanTest_b : std_logic_vector(31 downto 0);
signal vCount_uid239_lzcZSin_uid65_fpTanTest_q : std_logic_vector(0 downto 0);
signal zs_uid243_lzcZSin_uid65_fpTanTest_q : std_logic_vector (15 downto 0);
signal vCount_uid257_lzcZSin_uid65_fpTanTest_a : std_logic_vector(3 downto 0);
signal vCount_uid257_lzcZSin_uid65_fpTanTest_b : std_logic_vector(3 downto 0);
signal vCount_uid257_lzcZSin_uid65_fpTanTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage1Idx3Pad24_uid286_alignedZSin_uid66_fpTanTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx3Pad6_uid297_alignedZSin_uid66_fpTanTest_q : std_logic_vector (5 downto 0);
signal vCount_uid310_lzcZCos_uid68_fpTanTest_a : std_logic_vector(63 downto 0);
signal vCount_uid310_lzcZCos_uid68_fpTanTest_b : std_logic_vector(63 downto 0);
signal vCount_uid310_lzcZCos_uid68_fpTanTest_q : std_logic_vector(0 downto 0);
signal vCount_uid318_lzcZCos_uid68_fpTanTest_a : std_logic_vector(31 downto 0);
signal vCount_uid318_lzcZCos_uid68_fpTanTest_b : std_logic_vector(31 downto 0);
signal vCount_uid318_lzcZCos_uid68_fpTanTest_q : std_logic_vector(0 downto 0);
signal vCount_uid336_lzcZCos_uid68_fpTanTest_a : std_logic_vector(3 downto 0);
signal vCount_uid336_lzcZCos_uid68_fpTanTest_b : std_logic_vector(3 downto 0);
signal vCount_uid336_lzcZCos_uid68_fpTanTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid447_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid447_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid448_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid448_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid449_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid449_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid463_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid463_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid464_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid464_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid465_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid465_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal signR_uid467_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(0 downto 0);
signal signR_uid467_fpTanXComp_uid157_fpTanTest_b : std_logic_vector(0 downto 0);
signal signR_uid467_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal expXmY_uid468_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(8 downto 0);
signal expXmY_uid468_fpTanXComp_uid157_fpTanTest_b : std_logic_vector(8 downto 0);
signal expXmY_uid468_fpTanXComp_uid157_fpTanTest_o : std_logic_vector (8 downto 0);
signal expXmY_uid468_fpTanXComp_uid157_fpTanTest_q : std_logic_vector (8 downto 0);
signal expR_uid469_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(10 downto 0);
signal expR_uid469_fpTanXComp_uid157_fpTanTest_b : std_logic_vector(10 downto 0);
signal expR_uid469_fpTanXComp_uid157_fpTanTest_o : std_logic_vector (10 downto 0);
signal expR_uid469_fpTanXComp_uid157_fpTanTest_q : std_logic_vector (9 downto 0);
signal fracYPostZ_uid476_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(0 downto 0);
signal fracYPostZ_uid476_fpTanXComp_uid157_fpTanTest_b : std_logic_vector(0 downto 0);
signal fracYPostZ_uid476_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal excXZYZ_uid509_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(0 downto 0);
signal excXZYZ_uid509_fpTanXComp_uid157_fpTanTest_b : std_logic_vector(0 downto 0);
signal excXZYZ_uid509_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal excXIYI_uid510_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(0 downto 0);
signal excXIYI_uid510_fpTanXComp_uid157_fpTanTest_b : std_logic_vector(0 downto 0);
signal excXIYI_uid510_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal mO_uid529_zCount_uid194_rrx_uid34_fpTanTest_q : std_logic_vector (1 downto 0);
signal vCount_uid536_zCount_uid194_rrx_uid34_fpTanTest_a : std_logic_vector(7 downto 0);
signal vCount_uid536_zCount_uid194_rrx_uid34_fpTanTest_b : std_logic_vector(7 downto 0);
signal vCount_uid536_zCount_uid194_rrx_uid34_fpTanTest_q : std_logic_vector(0 downto 0);
signal vCount_uid548_zCount_uid194_rrx_uid34_fpTanTest_a : std_logic_vector(1 downto 0);
signal vCount_uid548_zCount_uid194_rrx_uid34_fpTanTest_b : std_logic_vector(1 downto 0);
signal vCount_uid548_zCount_uid194_rrx_uid34_fpTanTest_q : std_logic_vector(0 downto 0);
signal prodXY_uid586_pT1_uid400_polyEvalsinPiZ_a : std_logic_vector (12 downto 0);
signal prodXY_uid586_pT1_uid400_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal prodXY_uid586_pT1_uid400_polyEvalsinPiZ_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid586_pT1_uid400_polyEvalsinPiZ_pr : SIGNED (26 downto 0);
signal prodXY_uid586_pT1_uid400_polyEvalsinPiZ_q : std_logic_vector (25 downto 0);
signal prodXY_uid589_pT2_uid406_polyEvalsinPiZ_a : std_logic_vector (14 downto 0);
signal prodXY_uid589_pT2_uid406_polyEvalsinPiZ_b : std_logic_vector (22 downto 0);
signal prodXY_uid589_pT2_uid406_polyEvalsinPiZ_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid589_pT2_uid406_polyEvalsinPiZ_pr : SIGNED (38 downto 0);
signal prodXY_uid589_pT2_uid406_polyEvalsinPiZ_q : std_logic_vector (37 downto 0);
signal prodXY_uid592_pT1_uid413_polyEvalcosPiZ_a : std_logic_vector (12 downto 0);
signal prodXY_uid592_pT1_uid413_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal prodXY_uid592_pT1_uid413_polyEvalcosPiZ_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid592_pT1_uid413_polyEvalcosPiZ_pr : SIGNED (26 downto 0);
signal prodXY_uid592_pT1_uid413_polyEvalcosPiZ_q : std_logic_vector (25 downto 0);
signal prodXY_uid595_pT2_uid419_polyEvalcosPiZ_a : std_logic_vector (14 downto 0);
signal prodXY_uid595_pT2_uid419_polyEvalcosPiZ_b : std_logic_vector (22 downto 0);
signal prodXY_uid595_pT2_uid419_polyEvalcosPiZ_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid595_pT2_uid419_polyEvalcosPiZ_pr : SIGNED (38 downto 0);
signal prodXY_uid595_pT2_uid419_polyEvalcosPiZ_q : std_logic_vector (37 downto 0);
signal prodXY_uid617_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_a : std_logic_vector (25 downto 0);
signal prodXY_uid617_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_b : std_logic_vector (23 downto 0);
signal prodXY_uid617_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_s1 : std_logic_vector (49 downto 0);
signal prodXY_uid617_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_pr : UNSIGNED (49 downto 0);
signal prodXY_uid617_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_q : std_logic_vector (49 downto 0);
signal prodXY_uid620_pT1_uid605_invPE_a : std_logic_vector (11 downto 0);
signal prodXY_uid620_pT1_uid605_invPE_b : std_logic_vector (11 downto 0);
signal prodXY_uid620_pT1_uid605_invPE_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid620_pT1_uid605_invPE_pr : SIGNED (24 downto 0);
signal prodXY_uid620_pT1_uid605_invPE_q : std_logic_vector (23 downto 0);
signal prodXY_uid623_pT2_uid611_invPE_a : std_logic_vector (13 downto 0);
signal prodXY_uid623_pT2_uid611_invPE_b : std_logic_vector (22 downto 0);
signal prodXY_uid623_pT2_uid611_invPE_s1 : std_logic_vector (36 downto 0);
signal prodXY_uid623_pT2_uid611_invPE_pr : SIGNED (37 downto 0);
signal prodXY_uid623_pT2_uid611_invPE_q : std_logic_vector (36 downto 0);
signal rrTable_uid187_rrx_uid34_fpTanTest_lutmem_reset0 : std_logic;
signal rrTable_uid187_rrx_uid34_fpTanTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid187_rrx_uid34_fpTanTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid187_rrx_uid34_fpTanTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid187_rrx_uid34_fpTanTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid187_rrx_uid34_fpTanTest_lutmem_q : std_logic_vector (39 downto 0);
signal rrTable_uid188_rrx_uid34_fpTanTest_lutmem_reset0 : std_logic;
signal rrTable_uid188_rrx_uid34_fpTanTest_lutmem_ia : std_logic_vector (37 downto 0);
signal rrTable_uid188_rrx_uid34_fpTanTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid188_rrx_uid34_fpTanTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid188_rrx_uid34_fpTanTest_lutmem_iq : std_logic_vector (37 downto 0);
signal rrTable_uid188_rrx_uid34_fpTanTest_lutmem_q : std_logic_vector (37 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_a0_b0_a : std_logic_vector (26 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_a0_b0_b : std_logic_vector (26 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_a0_b0_q : std_logic_vector (53 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_a1_b0_a : std_logic_vector (26 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_a1_b0_b : std_logic_vector (26 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_a1_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_a1_b0_q : std_logic_vector (53 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_a2_b0_a : std_logic_vector (26 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_a2_b0_b : std_logic_vector (26 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_a2_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_a2_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_a2_b0_q : std_logic_vector (53 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_result_add_0_0_a : std_logic_vector(81 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_result_add_0_0_b : std_logic_vector(81 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_result_add_0_0_o : std_logic_vector (81 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_result_add_0_0_q : std_logic_vector (81 downto 0);
signal memoryC0_uid387_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC0_uid387_tableGensinPiZ_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid387_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid387_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid387_tableGensinPiZ_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid387_tableGensinPiZ_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid389_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC1_uid389_tableGensinPiZ_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid389_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid389_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid389_tableGensinPiZ_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid389_tableGensinPiZ_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid391_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC2_uid391_tableGensinPiZ_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid391_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid391_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid391_tableGensinPiZ_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid391_tableGensinPiZ_lutmem_q : std_logic_vector (12 downto 0);
signal memoryC0_uid393_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC0_uid393_tableGencosPiZ_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid393_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid393_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid393_tableGencosPiZ_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid393_tableGencosPiZ_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid395_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC1_uid395_tableGencosPiZ_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid395_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid395_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid395_tableGencosPiZ_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid395_tableGencosPiZ_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid397_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC2_uid397_tableGencosPiZ_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid397_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid397_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid397_tableGencosPiZ_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid397_tableGencosPiZ_lutmem_q : std_logic_vector (12 downto 0);
signal memoryC0_uid598_invTab_lutmem_reset0 : std_logic;
signal memoryC0_uid598_invTab_lutmem_ia : std_logic_vector (30 downto 0);
signal memoryC0_uid598_invTab_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC0_uid598_invTab_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC0_uid598_invTab_lutmem_iq : std_logic_vector (30 downto 0);
signal memoryC0_uid598_invTab_lutmem_q : std_logic_vector (30 downto 0);
signal memoryC1_uid600_invTab_lutmem_reset0 : std_logic;
signal memoryC1_uid600_invTab_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid600_invTab_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC1_uid600_invTab_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC1_uid600_invTab_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid600_invTab_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid602_invTab_lutmem_reset0 : std_logic;
signal memoryC2_uid602_invTab_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid602_invTab_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC2_uid602_invTab_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC2_uid602_invTab_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid602_invTab_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_q : std_logic_vector (2 downto 0);
signal reg_expXTableAddr_uid186_rrx_uid34_fpTanTest_0_to_rrTable_uid187_rrx_uid34_fpTanTest_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_rrTable_uid187_rrx_uid34_fpTanTest_lutmem_0_to_os_uid189_rrx_uid34_fpTanTest_0_q : std_logic_vector (39 downto 0);
signal reg_rrTable_uid188_rrx_uid34_fpTanTest_lutmem_0_to_os_uid189_rrx_uid34_fpTanTest_1_q : std_logic_vector (37 downto 0);
signal reg_prod_uid191_rrx_uid34_fpTanTest_a_0_0_to_prod_uid191_rrx_uid34_fpTanTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid191_rrx_uid34_fpTanTest_b_0_0_to_prod_uid191_rrx_uid34_fpTanTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_prod_uid191_rrx_uid34_fpTanTest_a_1_0_to_prod_uid191_rrx_uid34_fpTanTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid191_rrx_uid34_fpTanTest_a_2_0_to_prod_uid191_rrx_uid34_fpTanTest_a2_b0_0_q : std_logic_vector (26 downto 0);
signal reg_rVStage_uid527_zCount_uid194_rrx_uid34_fpTanTest_0_to_vCount_uid528_zCount_uid194_rrx_uid34_fpTanTest_1_q : std_logic_vector (15 downto 0);
signal reg_cStage_uid531_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid533_zCount_uid194_rrx_uid34_fpTanTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid535_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid539_zCount_uid194_rrx_uid34_fpTanTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid537_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid539_zCount_uid194_rrx_uid34_fpTanTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid547_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid551_zCount_uid194_rrx_uid34_fpTanTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid549_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid551_zCount_uid194_rrx_uid34_fpTanTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid542_zCount_uid194_rrx_uid34_fpTanTest_0_to_r_uid555_zCount_uid194_rrx_uid34_fpTanTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid528_zCount_uid194_rrx_uid34_fpTanTest_0_to_r_uid555_zCount_uid194_rrx_uid34_fpTanTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel2Dto1_uid578_normMult_uid195_rrx_uid34_fpTanTest_0_to_leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid568_normMult_uid195_rrx_uid34_fpTanTest_0_to_leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_2_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx1_uid571_normMult_uid195_rrx_uid34_fpTanTest_0_to_leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_3_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx2_uid574_normMult_uid195_rrx_uid34_fpTanTest_0_to_leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_4_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx3_uid577_normMult_uid195_rrx_uid34_fpTanTest_0_to_leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_5_q : std_logic_vector (75 downto 0);
signal reg_fracCompOut_uid196_rrx_uid34_fpTanTest_0_to_finalFrac_uid201_rrx_uid34_fpTanTest_2_q : std_logic_vector (52 downto 0);
signal reg_expCompOut_uid198_rrx_uid34_fpTanTest_0_to_finalExp_uid202_rrx_uid34_fpTanTest_2_q : std_logic_vector (7 downto 0);
signal reg_leftShiftStageSel3Dto2_uid215_fxpX_uid48_fpTanTest_0_to_leftShiftStage0_uid216_fxpX_uid48_fpTanTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel1Dto0_uid226_fxpX_uid48_fpTanTest_0_to_leftShiftStage1_uid227_fxpX_uid48_fpTanTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid216_fxpX_uid48_fpTanTest_0_to_leftShiftStage1_uid227_fxpX_uid48_fpTanTest_2_q : std_logic_vector (67 downto 0);
signal reg_pad_one_uid54_fpTanTest_0_to_oneMinusY_uid54_fpTanTest_0_q : std_logic_vector (66 downto 0);
signal reg_y_uid50_fpTanTest_0_to_oneMinusY_uid54_fpTanTest_1_q : std_logic_vector (65 downto 0);
signal reg_oneMinusY_uid54_fpTanTest_0_to_cmpYToOneMinusY_uid56_fpTanTest_0_q : std_logic_vector (67 downto 0);
signal reg_cmpYToOneMinusY_uid56_fpTanTest_1_to_zSin_uid59_fpTanTest_1_q : std_logic_vector (0 downto 0);
signal reg_zSinYBottom_uid58_fpTanTest_0_to_zSin_uid59_fpTanTest_2_q : std_logic_vector (64 downto 0);
signal reg_zSinOMyBottom_uid57_fpTanTest_0_to_zSin_uid59_fpTanTest_3_q : std_logic_vector (64 downto 0);
signal reg_rVStage_uid250_lzcZSin_uid65_fpTanTest_0_to_vCount_uid251_lzcZSin_uid65_fpTanTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid252_lzcZSin_uid65_fpTanTest_0_to_vStagei_uid254_lzcZSin_uid65_fpTanTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid256_lzcZSin_uid65_fpTanTest_0_to_vStagei_uid260_lzcZSin_uid65_fpTanTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid258_lzcZSin_uid65_fpTanTest_0_to_vStagei_uid260_lzcZSin_uid65_fpTanTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid245_lzcZSin_uid65_fpTanTest_0_to_r_uid270_lzcZSin_uid65_fpTanTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel4Dto3_uid289_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_2_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx1_uid282_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_3_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx2_uid285_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_4_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx3_uid288_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_5_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStageSel2Dto1_uid300_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage2_uid301_alignedZSin_uid66_fpTanTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage2_uid301_alignedZSin_uid66_fpTanTest_2_q : std_logic_vector (64 downto 0);
signal reg_sinXIsXRR_uid42_fpTanTest_2_to_p_uid72_fpTanTest_1_q : std_logic_vector (0 downto 0);
signal reg_pHigh_uid71_fpTanTest_0_to_p_uid72_fpTanTest_2_q : std_logic_vector (25 downto 0);
signal reg_addr_uid80_fpTanTest_0_to_memoryC2_uid391_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid399_polyEvalsinPiZ_0_to_prodXY_uid586_pT1_uid400_polyEvalsinPiZ_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid391_tableGensinPiZ_lutmem_0_to_prodXY_uid586_pT1_uid400_polyEvalsinPiZ_1_q : std_logic_vector (12 downto 0);
signal reg_addr_uid80_fpTanTest_0_to_memoryC1_uid389_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid389_tableGensinPiZ_lutmem_0_to_sumAHighB_uid403_polyEvalsinPiZ_0_q : std_logic_vector (20 downto 0);
signal reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid401_uid404_polyEvalsinPiZ_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_1_q : std_logic_vector (22 downto 0);
signal reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid387_tableGensinPiZ_lutmem_0_to_sumAHighB_uid409_polyEvalsinPiZ_0_q : std_logic_vector (29 downto 0);
signal reg_r_uid270_lzcZSin_uid65_fpTanTest_0_to_expSinHC_uid73_fpTanTest_1_q : std_logic_vector (6 downto 0);
signal reg_sinXIsXRR_uid42_fpTanTest_2_to_expPSin_uid75_fpTanTest_1_q : std_logic_vector (0 downto 0);
signal reg_sinXIsXRR_uid42_fpTanTest_2_to_join_uid98_fpTanTest_1_q : std_logic_vector (0 downto 0);
signal reg_fracRCompSin_uid102_fpTanTest_0_to_fracRPostExcSin_uid121_fpTanTest_2_q : std_logic_vector (22 downto 0);
signal reg_expRCompSin_uid103_fpTanTest_0_to_expRPostExcSin_uid125_fpTanTest_2_q : std_logic_vector (7 downto 0);
signal reg_yHalfCosNotONe_uid134_fpTanTest_0_to_rZeroOrCosOne_uid136_fpTanTest_1_q : std_logic_vector (0 downto 0);
signal reg_sinXIsX_uid41_fpTanTest_2_to_rZeroOrCosOne_uid136_fpTanTest_2_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOneXRR_uid43_fpTanTest_2_to_rZeroOrCosOne_uid136_fpTanTest_3_q : std_logic_vector (0 downto 0);
signal reg_excRNaN_uid116_fpTanTest_0_to_join_uid137_fpTanTest_1_q : std_logic_vector (0 downto 0);
signal reg_InvCmpYToOneMinusY_uid60_fpTanTest_0_to_zCos_uid63_fpTanTest_1_q : std_logic_vector (0 downto 0);
signal reg_rVStage_uid329_lzcZCos_uid68_fpTanTest_0_to_vCount_uid330_lzcZCos_uid68_fpTanTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid331_lzcZCos_uid68_fpTanTest_0_to_vStagei_uid333_lzcZCos_uid68_fpTanTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid335_lzcZCos_uid68_fpTanTest_0_to_vStagei_uid339_lzcZCos_uid68_fpTanTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid337_lzcZCos_uid68_fpTanTest_0_to_vStagei_uid339_lzcZCos_uid68_fpTanTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid324_lzcZCos_uid68_fpTanTest_0_to_r_uid349_lzcZCos_uid68_fpTanTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel4Dto3_uid368_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_2_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx1_uid361_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_3_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx2_uid364_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_4_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx3_uid367_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_5_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStageSel2Dto1_uid379_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_2_q : std_logic_vector (64 downto 0);
signal reg_addr_uid82_fpTanTest_0_to_memoryC2_uid397_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid412_polyEvalcosPiZ_0_to_prodXY_uid592_pT1_uid413_polyEvalcosPiZ_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid397_tableGencosPiZ_lutmem_0_to_prodXY_uid592_pT1_uid413_polyEvalcosPiZ_1_q : std_logic_vector (12 downto 0);
signal reg_addr_uid82_fpTanTest_0_to_memoryC1_uid395_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid395_tableGencosPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalcosPiZ_0_q : std_logic_vector (20 downto 0);
signal reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid414_uid417_polyEvalcosPiZ_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_1_q : std_logic_vector (22 downto 0);
signal reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid393_tableGencosPiZ_lutmem_0_to_sumAHighB_uid422_polyEvalcosPiZ_0_q : std_logic_vector (29 downto 0);
signal reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_q : std_logic_vector (25 downto 0);
signal reg_polyEvalSigcosPiZ_uid88_fpTanTest_0_to_mulCos_uid104_fpTanTest_1_q : std_logic_vector (25 downto 0);
signal reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q : std_logic_vector (6 downto 0);
signal reg_expPCos_uid78_fpTanTest_0_to_expFracRCosPreRnd_uid110_uid110_fpTanTest_1_q : std_logic_vector (7 downto 0);
signal reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q : std_logic_vector (1 downto 0);
signal reg_fracRCompCos_uid114_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_2_q : std_logic_vector (22 downto 0);
signal reg_cosXIsOneXRR_uid43_fpTanTest_2_to_join_uid139_fpTanTest_2_q : std_logic_vector (0 downto 0);
signal reg_expSelBitsCos_uid140_fpTanTest_0_to_expSelectorCos_uid141_fpTanTest_0_q : std_logic_vector (3 downto 0);
signal reg_expRCompSin_uid115_fpTanTest_0_to_expRPostExcCos_uid143_fpTanTest_2_q : std_logic_vector (7 downto 0);
signal reg_expXIsZero_uid439_fpTanXComp_uid157_fpTanTest_0_to_zeroOverReg_uid499_fpTanXComp_uid157_fpTanTest_1_q : std_logic_vector (0 downto 0);
signal reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC2_uid602_invTab_lutmem_0_q : std_logic_vector (8 downto 0);
signal reg_yT1_uid604_invPE_0_to_prodXY_uid620_pT1_uid605_invPE_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid602_invTab_lutmem_0_to_prodXY_uid620_pT1_uid605_invPE_1_q : std_logic_vector (11 downto 0);
signal reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC1_uid600_invTab_lutmem_0_q : std_logic_vector (8 downto 0);
signal reg_memoryC1_uid600_invTab_lutmem_0_to_sumAHighB_uid608_invPE_0_q : std_logic_vector (20 downto 0);
signal reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_q : std_logic_vector (13 downto 0);
signal reg_s1_uid606_uid609_invPE_0_to_prodXY_uid623_pT2_uid611_invPE_1_q : std_logic_vector (22 downto 0);
signal reg_memoryC0_uid598_invTab_lutmem_0_to_sumAHighB_uid614_invPE_0_q : std_logic_vector (30 downto 0);
signal reg_invY_uid474_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid617_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_0_q : std_logic_vector (25 downto 0);
signal reg_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid617_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_1_q : std_logic_vector (23 downto 0);
signal reg_expFracRnd_uid487_fpTanXComp_uid157_fpTanTest_0_to_expFracPostRnd_uid490_fpTanXComp_uid157_fpTanTest_0_q : std_logic_vector (33 downto 0);
signal reg_expRExt_uid494_fpTanXComp_uid157_fpTanTest_0_to_expUdf_uid495_fpTanXComp_uid157_fpTanTest_1_q : std_logic_vector (10 downto 0);
signal reg_exc_I_uid460_fpTanXComp_uid157_fpTanTest_0_to_regOrZeroOverInf_uid502_fpTanXComp_uid157_fpTanTest_2_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid455_fpTanXComp_uid157_fpTanTest_0_to_excXRYZ_uid504_fpTanXComp_uid157_fpTanTest_2_q : std_logic_vector (0 downto 0);
signal reg_exc_I_uid444_fpTanXComp_uid157_fpTanTest_0_to_excXIYR_uid507_fpTanXComp_uid157_fpTanTest_1_q : std_logic_vector (0 downto 0);
signal reg_exc_N_uid446_fpTanXComp_uid157_fpTanTest_0_to_excRNaN_uid511_fpTanXComp_uid157_fpTanTest_2_q : std_logic_vector (0 downto 0);
signal reg_exc_N_uid462_fpTanXComp_uid157_fpTanTest_0_to_excRNaN_uid511_fpTanXComp_uid157_fpTanTest_3_q : std_logic_vector (0 downto 0);
signal reg_concExc_uid512_fpTanXComp_uid157_fpTanTest_0_to_excREnc_uid513_fpTanXComp_uid157_fpTanTest_0_q : std_logic_vector (2 downto 0);
signal ld_fracXRR_uid40_fpTanTest_b_to_oFracXRR_uid44_uid44_fpTanTest_a_q : std_logic_vector (52 downto 0);
signal ld_y_uid50_fpTanTest_b_to_cmpYToOneMinusY_uid56_fpTanTest_b_q : std_logic_vector (65 downto 0);
signal ld_oneMinusY_uid54_fpTanTest_q_to_zSinOMyBottom_uid57_fpTanTest_a_q : std_logic_vector (67 downto 0);
signal ld_sinXIsXRR_uid42_fpTanTest_n_to_multSinOp2_uid90_fpTanTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid17_fpTanTest_q_to_excRNaN_uid116_fpTanTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpTanTest_q_to_excRNaN_uid116_fpTanTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid41_fpTanTest_n_to_excSelBitsSin_uid117_fpTanTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid10_fpTanTest_q_to_excSelBitsSin_uid117_fpTanTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid41_fpTanTest_n_to_InvSinXIsX_uid126_fpTanTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvSinXIsXRR_uid127_fpTanTest_q_to_signComp_uid128_fpTanTest_a_q : std_logic_vector (0 downto 0);
signal ld_signX_uid38_fpTanTest_b_to_signR_uid129_fpTanTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid129_fpTanTest_q_to_fpSin_uid130_fpTanTest_c_q : std_logic_vector (0 downto 0);
signal ld_InvSinXIsX_uid126_fpTanTest_q_to_yHalfCosNotONe_uid134_fpTanTest_b_q : std_logic_vector (0 downto 0);
signal ld_InvCosXIsOneXRR_uid132_fpTanTest_q_to_yHalfCosNotONe_uid134_fpTanTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_sinXIsX_uid41_fpTanTest_2_to_rZeroOrCosOne_uid136_fpTanTest_2_q_to_rZeroOrCosOne_uid136_fpTanTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_cosXIsOneXRR_uid43_fpTanTest_2_to_rZeroOrCosOne_uid136_fpTanTest_3_q_to_rZeroOrCosOne_uid136_fpTanTest_c_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid41_fpTanTest_n_to_cosOne_uid144_fpTanTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosOne_uid144_fpTanTest_q_to_InvCosOne_uid145_fpTanTest_a_q : std_logic_vector (0 downto 0);
signal ld_yIsZero_uid51_fpTanTest_q_to_InvYIsZero_uid147_fpTanTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid49_fpTanTest_b_to_signRCond2_uid148_fpTanTest_b_q : std_logic_vector (0 downto 0);
signal ld_InvIntXParity_uid151_fpTanTest_q_to_signRCond1_uid153_fpTanTest_b_q : std_logic_vector (0 downto 0);
signal ld_signRCos_uid154_fpTanTest_q_to_fpCos_uid155_fpTanTest_c_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid184_rrx_uid34_fpTanTest_n_to_finalFrac_uid201_rrx_uid34_fpTanTest_b_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid184_rrx_uid34_fpTanTest_n_to_finalExp_uid202_rrx_uid34_fpTanTest_b_q : std_logic_vector (0 downto 0);
signal ld_finalExp_uid202_rrx_uid34_fpTanTest_q_to_RRangeRed_uid203_rrx_uid34_fpTanTest_b_q : std_logic_vector (7 downto 0);
signal ld_LeftShiftStage066dto0_uid218_fxpX_uid48_fpTanTest_b_to_leftShiftStage1Idx1_uid219_fxpX_uid48_fpTanTest_b_q : std_logic_vector (66 downto 0);
signal ld_LeftShiftStage065dto0_uid221_fxpX_uid48_fpTanTest_b_to_leftShiftStage1Idx2_uid222_fxpX_uid48_fpTanTest_b_q : std_logic_vector (65 downto 0);
signal ld_LeftShiftStage064dto0_uid224_fxpX_uid48_fpTanTest_b_to_leftShiftStage1Idx3_uid225_fxpX_uid48_fpTanTest_b_q : std_logic_vector (64 downto 0);
signal ld_vStage_uid233_lzcZSin_uid65_fpTanTest_b_to_cStage_uid234_lzcZSin_uid65_fpTanTest_b_q : std_logic_vector (0 downto 0);
signal ld_rVStage_uid230_lzcZSin_uid65_fpTanTest_b_to_vStagei_uid236_lzcZSin_uid65_fpTanTest_c_q : std_logic_vector (63 downto 0);
signal ld_rVStage_uid238_lzcZSin_uid65_fpTanTest_b_to_vStagei_uid242_lzcZSin_uid65_fpTanTest_c_q : std_logic_vector (31 downto 0);
signal ld_vStage_uid240_lzcZSin_uid65_fpTanTest_b_to_vStagei_uid242_lzcZSin_uid65_fpTanTest_d_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid251_lzcZSin_uid65_fpTanTest_q_to_r_uid270_lzcZSin_uid65_fpTanTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid245_lzcZSin_uid65_fpTanTest_0_to_r_uid270_lzcZSin_uid65_fpTanTest_4_q_to_r_uid270_lzcZSin_uid65_fpTanTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid239_lzcZSin_uid65_fpTanTest_q_to_r_uid270_lzcZSin_uid65_fpTanTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid231_lzcZSin_uid65_fpTanTest_q_to_r_uid270_lzcZSin_uid65_fpTanTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage162dto0_uid292_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage2Idx1_uid293_alignedZSin_uid66_fpTanTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage160dto0_uid295_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage2Idx2_uid296_alignedZSin_uid66_fpTanTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage158dto0_uid298_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage2Idx3_uid299_alignedZSin_uid66_fpTanTest_b_q : std_logic_vector (58 downto 0);
signal ld_leftShiftStageSel0Dto0_uid305_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage3_uid306_alignedZSin_uid66_fpTanTest_b_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid312_lzcZCos_uid68_fpTanTest_b_to_cStage_uid313_lzcZCos_uid68_fpTanTest_b_q : std_logic_vector (0 downto 0);
signal ld_rVStage_uid309_lzcZCos_uid68_fpTanTest_b_to_vStagei_uid315_lzcZCos_uid68_fpTanTest_c_q : std_logic_vector (63 downto 0);
signal ld_rVStage_uid317_lzcZCos_uid68_fpTanTest_b_to_vStagei_uid321_lzcZCos_uid68_fpTanTest_c_q : std_logic_vector (31 downto 0);
signal ld_vStage_uid319_lzcZCos_uid68_fpTanTest_b_to_vStagei_uid321_lzcZCos_uid68_fpTanTest_d_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid330_lzcZCos_uid68_fpTanTest_q_to_r_uid349_lzcZCos_uid68_fpTanTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid324_lzcZCos_uid68_fpTanTest_0_to_r_uid349_lzcZCos_uid68_fpTanTest_4_q_to_r_uid349_lzcZCos_uid68_fpTanTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid318_lzcZCos_uid68_fpTanTest_q_to_r_uid349_lzcZCos_uid68_fpTanTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid310_lzcZCos_uid68_fpTanTest_q_to_r_uid349_lzcZCos_uid68_fpTanTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage162dto0_uid371_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage2Idx1_uid372_alignedZCos_uid69_fpTanTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage160dto0_uid374_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage2Idx2_uid375_alignedZCos_uid69_fpTanTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage158dto0_uid377_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage2Idx3_uid378_alignedZCos_uid69_fpTanTest_b_q : std_logic_vector (58 downto 0);
signal ld_reg_leftShiftStageSel2Dto1_uid379_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_1_q_to_leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_b_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel0Dto0_uid384_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage3_uid385_alignedZCos_uid69_fpTanTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracYZero_uid434_fpTanXComp_uid157_fpTanTest_q_to_fracYPostZ_uid476_fpTanXComp_uid157_fpTanTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracYPostZ_uid476_fpTanXComp_uid157_fpTanTest_q_to_divValPreNormTrunc_uid482_fpTanXComp_uid157_fpTanTest_b_q : std_logic_vector (0 downto 0);
signal ld_norm_uid483_fpTanXComp_uid157_fpTanTest_b_to_rndOp_uid489_fpTanXComp_uid157_fpTanTest_c_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid450_fpTanXComp_uid157_fpTanTest_q_to_regOverRegWithUf_uid500_fpTanXComp_uid157_fpTanTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid466_fpTanXComp_uid157_fpTanTest_q_to_regOverRegWithUf_uid500_fpTanXComp_uid157_fpTanTest_c_q : std_logic_vector (0 downto 0);
signal ld_zeroOverReg_uid499_fpTanXComp_uid157_fpTanTest_q_to_excRZero_uid503_fpTanXComp_uid157_fpTanTest_a_q : std_logic_vector (0 downto 0);
signal ld_regOrZeroOverInf_uid502_fpTanXComp_uid157_fpTanTest_q_to_excRZero_uid503_fpTanXComp_uid157_fpTanTest_c_q : std_logic_vector (0 downto 0);
signal ld_excXRYZ_uid504_fpTanXComp_uid157_fpTanTest_q_to_excRInf_uid508_fpTanXComp_uid157_fpTanTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXIYZ_uid506_fpTanXComp_uid157_fpTanTest_q_to_excRInf_uid508_fpTanXComp_uid157_fpTanTest_c_q : std_logic_vector (0 downto 0);
signal ld_excXIYR_uid507_fpTanXComp_uid157_fpTanTest_q_to_excRInf_uid508_fpTanXComp_uid157_fpTanTest_d_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid511_fpTanXComp_uid157_fpTanTest_q_to_concExc_uid512_fpTanXComp_uid157_fpTanTest_c_q : std_logic_vector (0 downto 0);
signal ld_fracRPreExc_uid492_fpTanXComp_uid157_fpTanTest_b_to_fracRPostExc_uid517_fpTanXComp_uid157_fpTanTest_d_q : std_logic_vector (22 downto 0);
signal ld_excRPreExc_uid493_fpTanXComp_uid157_fpTanTest_b_to_expRPostExc_uid521_fpTanXComp_uid157_fpTanTest_d_q : std_logic_vector (7 downto 0);
signal ld_sRPostExc_uid523_fpTanXComp_uid157_fpTanTest_q_to_divR_uid524_fpTanXComp_uid157_fpTanTest_c_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid536_zCount_uid194_rrx_uid34_fpTanTest_q_to_r_uid555_zCount_uid194_rrx_uid34_fpTanTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid528_zCount_uid194_rrx_uid34_fpTanTest_0_to_r_uid555_zCount_uid194_rrx_uid34_fpTanTest_4_q_to_r_uid555_zCount_uid194_rrx_uid34_fpTanTest_e_q : std_logic_vector (0 downto 0);
signal ld_X67dto0_uid559_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage0Idx1_uid560_normMult_uid195_rrx_uid34_fpTanTest_b_q : std_logic_vector (67 downto 0);
signal ld_X59dto0_uid562_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage0Idx2_uid563_normMult_uid195_rrx_uid34_fpTanTest_b_q : std_logic_vector (59 downto 0);
signal ld_X51dto0_uid565_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage0Idx3_uid566_normMult_uid195_rrx_uid34_fpTanTest_b_q : std_logic_vector (51 downto 0);
signal ld_multFracBits_uid192_rrx_uid34_fpTanTest_b_to_leftShiftStage0_uid568_normMult_uid195_rrx_uid34_fpTanTest_c_q : std_logic_vector (75 downto 0);
signal ld_leftShiftStageSel0Dto0_uid583_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage2_uid584_normMult_uid195_rrx_uid34_fpTanTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_yT1_uid412_polyEvalcosPiZ_0_to_prodXY_uid592_pT1_uid413_polyEvalcosPiZ_0_q_to_prodXY_uid592_pT1_uid413_polyEvalcosPiZ_a_q : std_logic_vector (12 downto 0);
signal ld_reg_yT1_uid604_invPE_0_to_prodXY_uid620_pT1_uid605_invPE_0_q_to_prodXY_uid620_pT1_uid605_invPE_a_q : std_logic_vector (11 downto 0);
signal ld_prod_uid191_rrx_uid34_fpTanTest_a2_b0_q_to_prod_uid191_rrx_uid34_fpTanTest_align_2_a_q : std_logic_vector (53 downto 0);
signal ld_leftShiftStageSel1Dto0_uid226_fxpX_uid48_fpTanTest_b_to_reg_leftShiftStageSel1Dto0_uid226_fxpX_uid48_fpTanTest_0_to_leftShiftStage1_uid227_fxpX_uid48_fpTanTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel2Dto1_uid300_alignedZSin_uid66_fpTanTest_b_to_reg_leftShiftStageSel2Dto1_uid300_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage2_uid301_alignedZSin_uid66_fpTanTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_sinXIsXRR_uid42_fpTanTest_n_to_reg_sinXIsXRR_uid42_fpTanTest_2_to_p_uid72_fpTanTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_yT1_uid399_polyEvalsinPiZ_b_to_reg_yT1_uid399_polyEvalsinPiZ_0_to_prodXY_uid586_pT1_uid400_polyEvalsinPiZ_0_a_q : std_logic_vector (12 downto 0);
signal ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC1_uid389_tableGensinPiZ_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_sinXIsXRR_uid42_fpTanTest_n_to_reg_sinXIsXRR_uid42_fpTanTest_2_to_expPSin_uid75_fpTanTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_sinXIsXRR_uid42_fpTanTest_n_to_reg_sinXIsXRR_uid42_fpTanTest_2_to_join_uid98_fpTanTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC1_uid395_tableGencosPiZ_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_cosXIsOneXRR_uid43_fpTanTest_n_to_reg_cosXIsOneXRR_uid43_fpTanTest_2_to_join_uid139_fpTanTest_2_a_q : std_logic_vector (0 downto 0);
signal ld_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_b_to_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC1_uid600_invTab_lutmem_0_a_q : std_logic_vector (8 downto 0);
signal ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_mem_reset0 : std_logic;
signal ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_sticky_ena_q : signal is true;
signal ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_inputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_sticky_ena_q : signal is true;
signal ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_inputreg_q : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_mem_reset0 : std_logic;
signal ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdcnt_eq : std_logic;
signal ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_sticky_ena_q : signal is true;
signal ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_mem_reset0 : std_logic;
signal ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_sticky_ena_q : signal is true;
signal ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_replace_mem_reset0 : std_logic;
signal ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_inputreg_q : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_mem_reset0 : std_logic;
signal ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdcnt_eq : std_logic;
signal ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_mem_top_q : std_logic_vector (6 downto 0);
signal ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_sticky_ena_q : signal is true;
signal ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_replace_mem_reset0 : std_logic;
signal ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_sticky_ena_q : signal is true;
signal ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_sticky_ena_q : signal is true;
signal ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_replace_mem_reset0 : std_logic;
signal ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_sticky_ena_q : signal is true;
signal ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_inputreg_q : std_logic_vector (31 downto 0);
signal ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_replace_mem_reset0 : std_logic;
signal ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_sticky_ena_q : signal is true;
signal ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_inputreg_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_replace_mem_reset0 : std_logic;
signal ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_sticky_ena_q : signal is true;
signal ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_sticky_ena_q : signal is true;
signal ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_inputreg_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_replace_mem_reset0 : std_logic;
signal ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_sticky_ena_q : signal is true;
signal ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_inputreg_q : std_logic_vector (64 downto 0);
signal ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_replace_mem_reset0 : std_logic;
signal ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_replace_mem_ia : std_logic_vector (64 downto 0);
signal ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_replace_mem_iq : std_logic_vector (64 downto 0);
signal ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_replace_mem_q : std_logic_vector (64 downto 0);
signal ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_sticky_ena_q : signal is true;
signal ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_inputreg_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_replace_mem_reset0 : std_logic;
signal ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_sticky_ena_q : signal is true;
signal ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_inputreg_q : std_logic_vector (64 downto 0);
signal ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_replace_mem_reset0 : std_logic;
signal ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_replace_mem_ia : std_logic_vector (64 downto 0);
signal ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_replace_mem_iq : std_logic_vector (64 downto 0);
signal ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_replace_mem_q : std_logic_vector (64 downto 0);
signal ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_sticky_ena_q : signal is true;
signal ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_inputreg_q : std_logic_vector (8 downto 0);
signal ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_replace_mem_reset0 : std_logic;
signal ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_replace_mem_ia : std_logic_vector (8 downto 0);
signal ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_replace_mem_iq : std_logic_vector (8 downto 0);
signal ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_replace_mem_q : std_logic_vector (8 downto 0);
signal ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_sticky_ena_q : signal is true;
signal ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_mem_reset0 : std_logic;
signal ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdcnt_eq : std_logic;
signal ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_sticky_ena_q : signal is true;
signal ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_inputreg_q : std_logic_vector (23 downto 0);
signal ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_replace_mem_reset0 : std_logic;
signal ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_sticky_ena_q : signal is true;
signal ld_X67dto0_uid559_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage0Idx1_uid560_normMult_uid195_rrx_uid34_fpTanTest_b_inputreg_q : std_logic_vector (67 downto 0);
signal ld_X59dto0_uid562_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage0Idx2_uid563_normMult_uid195_rrx_uid34_fpTanTest_b_inputreg_q : std_logic_vector (59 downto 0);
signal ld_X51dto0_uid565_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage0Idx3_uid566_normMult_uid195_rrx_uid34_fpTanTest_b_inputreg_q : std_logic_vector (51 downto 0);
signal ld_multFracBits_uid192_rrx_uid34_fpTanTest_b_to_leftShiftStage0_uid568_normMult_uid195_rrx_uid34_fpTanTest_c_inputreg_q : std_logic_vector (75 downto 0);
signal ld_reg_yT1_uid412_polyEvalcosPiZ_0_to_prodXY_uid592_pT1_uid413_polyEvalcosPiZ_0_q_to_prodXY_uid592_pT1_uid413_polyEvalcosPiZ_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_reg_yT1_uid604_invPE_0_to_prodXY_uid620_pT1_uid605_invPE_0_q_to_prodXY_uid620_pT1_uid605_invPE_a_inputreg_q : std_logic_vector (11 downto 0);
signal ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_inputreg_q : std_logic_vector (8 downto 0);
signal ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_mem_ia : std_logic_vector (8 downto 0);
signal ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_mem_iq : std_logic_vector (8 downto 0);
signal ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_mem_q : std_logic_vector (8 downto 0);
signal ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdcnt_eq : std_logic;
signal ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_sticky_ena_q : signal is true;
signal ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_replace_mem_reset0 : std_logic;
signal ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid399_polyEvalsinPiZ_b_to_reg_yT1_uid399_polyEvalsinPiZ_0_to_prodXY_uid586_pT1_uid400_polyEvalsinPiZ_0_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_replace_mem_reset0 : std_logic;
signal ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_replace_mem_reset0 : std_logic;
signal ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_mem_reset0 : std_logic;
signal ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdcnt_eq : std_logic;
signal ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_sticky_ena_q : signal is true;
signal ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_inputreg_q : std_logic_vector (13 downto 0);
signal ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_replace_mem_reset0 : std_logic;
signal ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_replace_mem_ia : std_logic_vector (13 downto 0);
signal ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_replace_mem_iq : std_logic_vector (13 downto 0);
signal ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_replace_mem_q : std_logic_vector (13 downto 0);
signal ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_sticky_ena_q : signal is true;
signal yIsZero_uid51_fpTanTest_a : std_logic_vector(65 downto 0);
signal yIsZero_uid51_fpTanTest_b : std_logic_vector(65 downto 0);
signal yIsZero_uid51_fpTanTest_q : std_logic_vector(0 downto 0);
signal pad_one_uid54_fpTanTest_q : std_logic_vector (66 downto 0);
signal cmpYToOneMinusY_uid56_fpTanTest_a : std_logic_vector(70 downto 0);
signal cmpYToOneMinusY_uid56_fpTanTest_b : std_logic_vector(70 downto 0);
signal cmpYToOneMinusY_uid56_fpTanTest_o : std_logic_vector (70 downto 0);
signal cmpYToOneMinusY_uid56_fpTanTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid56_fpTanTest_c : std_logic_vector (0 downto 0);
signal expUdf_uid495_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(13 downto 0);
signal expUdf_uid495_fpTanXComp_uid157_fpTanTest_b : std_logic_vector(13 downto 0);
signal expUdf_uid495_fpTanXComp_uid157_fpTanTest_o : std_logic_vector (13 downto 0);
signal expUdf_uid495_fpTanXComp_uid157_fpTanTest_cin : std_logic_vector (0 downto 0);
signal expUdf_uid495_fpTanXComp_uid157_fpTanTest_n : std_logic_vector (0 downto 0);
signal expOvf_uid498_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(13 downto 0);
signal expOvf_uid498_fpTanXComp_uid157_fpTanTest_b : std_logic_vector(13 downto 0);
signal expOvf_uid498_fpTanXComp_uid157_fpTanTest_o : std_logic_vector (13 downto 0);
signal expOvf_uid498_fpTanXComp_uid157_fpTanTest_cin : std_logic_vector (0 downto 0);
signal expOvf_uid498_fpTanXComp_uid157_fpTanTest_n : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid219_fxpX_uid48_fpTanTest_q : std_logic_vector (67 downto 0);
signal InvCmpYToOneMinusY_uid60_fpTanTest_a : std_logic_vector(0 downto 0);
signal InvCmpYToOneMinusY_uid60_fpTanTest_q : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid126_fpTanTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid126_fpTanTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid147_fpTanTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid147_fpTanTest_q : std_logic_vector(0 downto 0);
signal lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q : std_logic_vector (23 downto 0);
signal rndOp_uid489_fpTanXComp_uid157_fpTanTest_q : std_logic_vector (24 downto 0);
signal oFracXRR_uid44_uid44_fpTanTest_q : std_logic_vector (53 downto 0);
signal half_uid52_fpTanTest_q : std_logic_vector (65 downto 0);
signal ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal exp_uid9_fpTanTest_in : std_logic_vector (30 downto 0);
signal exp_uid9_fpTanTest_b : std_logic_vector (7 downto 0);
signal frac_uid13_fpTanTest_in : std_logic_vector (22 downto 0);
signal frac_uid13_fpTanTest_b : std_logic_vector (22 downto 0);
signal signX_uid38_fpTanTest_in : std_logic_vector (31 downto 0);
signal signX_uid38_fpTanTest_b : std_logic_vector (0 downto 0);
signal expFracX_uid159_px_uid33_fpTanTest_in : std_logic_vector (30 downto 0);
signal expFracX_uid159_px_uid33_fpTanTest_b : std_logic_vector (30 downto 0);
signal expXIsZero_uid10_fpTanTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid10_fpTanTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid10_fpTanTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid12_fpTanTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpTanTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpTanTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid14_fpTanTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpTanTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpTanTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpTanTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpTanTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpTanTest_q : std_logic_vector(0 downto 0);
signal sinXIsX_uid41_fpTanTest_a : std_logic_vector(10 downto 0);
signal sinXIsX_uid41_fpTanTest_b : std_logic_vector(10 downto 0);
signal sinXIsX_uid41_fpTanTest_o : std_logic_vector (10 downto 0);
signal sinXIsX_uid41_fpTanTest_cin : std_logic_vector (0 downto 0);
signal sinXIsX_uid41_fpTanTest_n : std_logic_vector (0 downto 0);
signal yIsHalf_uid53_fpTanTest_a : std_logic_vector(65 downto 0);
signal yIsHalf_uid53_fpTanTest_b : std_logic_vector(65 downto 0);
signal yIsHalf_uid53_fpTanTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid54_fpTanTest_a : std_logic_vector(67 downto 0);
signal oneMinusY_uid54_fpTanTest_b : std_logic_vector(67 downto 0);
signal oneMinusY_uid54_fpTanTest_o : std_logic_vector (67 downto 0);
signal oneMinusY_uid54_fpTanTest_q : std_logic_vector (67 downto 0);
signal zSin_uid59_fpTanTest_s : std_logic_vector (0 downto 0);
signal zSin_uid59_fpTanTest_q : std_logic_vector (64 downto 0);
signal zCos_uid63_fpTanTest_s : std_logic_vector (0 downto 0);
signal zCos_uid63_fpTanTest_q : std_logic_vector (64 downto 0);
signal expSinHC_uid73_fpTanTest_a : std_logic_vector(8 downto 0);
signal expSinHC_uid73_fpTanTest_b : std_logic_vector(8 downto 0);
signal expSinHC_uid73_fpTanTest_o : std_logic_vector (8 downto 0);
signal expSinHC_uid73_fpTanTest_q : std_logic_vector (8 downto 0);
signal expHardCase_uid77_fpTanTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid77_fpTanTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid77_fpTanTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid77_fpTanTest_q : std_logic_vector (8 downto 0);
signal excRNaN_uid116_fpTanTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid116_fpTanTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid116_fpTanTest_q : std_logic_vector(0 downto 0);
signal fracRPostExcSin_uid121_fpTanTest_s : std_logic_vector (1 downto 0);
signal fracRPostExcSin_uid121_fpTanTest_q : std_logic_vector (22 downto 0);
signal expRPostExcSin_uid125_fpTanTest_s : std_logic_vector (1 downto 0);
signal expRPostExcSin_uid125_fpTanTest_q : std_logic_vector (7 downto 0);
signal yHalfCosNotONe_uid134_fpTanTest_a : std_logic_vector(0 downto 0);
signal yHalfCosNotONe_uid134_fpTanTest_b : std_logic_vector(0 downto 0);
signal yHalfCosNotONe_uid134_fpTanTest_c : std_logic_vector(0 downto 0);
signal yHalfCosNotONe_uid134_fpTanTest_q : std_logic_vector(0 downto 0);
signal rZeroOrCosOne_uid136_fpTanTest_a : std_logic_vector(0 downto 0);
signal rZeroOrCosOne_uid136_fpTanTest_b : std_logic_vector(0 downto 0);
signal rZeroOrCosOne_uid136_fpTanTest_c : std_logic_vector(0 downto 0);
signal rZeroOrCosOne_uid136_fpTanTest_q : std_logic_vector(0 downto 0);
signal fracRPostExcCos_uid138_fpTanTest_s : std_logic_vector (1 downto 0);
signal fracRPostExcCos_uid138_fpTanTest_q : std_logic_vector (22 downto 0);
signal expRPostExcCos_uid143_fpTanTest_s : std_logic_vector (1 downto 0);
signal expRPostExcCos_uid143_fpTanTest_q : std_logic_vector (7 downto 0);
signal signRCos_uid154_fpTanTest_a : std_logic_vector(0 downto 0);
signal signRCos_uid154_fpTanTest_b : std_logic_vector(0 downto 0);
signal signRCos_uid154_fpTanTest_q : std_logic_vector(0 downto 0);
signal finalExp_uid202_rrx_uid34_fpTanTest_s : std_logic_vector (0 downto 0);
signal finalExp_uid202_rrx_uid34_fpTanTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid242_lzcZSin_uid65_fpTanTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid242_lzcZSin_uid65_fpTanTest_q : std_logic_vector (31 downto 0);
signal vCount_uid251_lzcZSin_uid65_fpTanTest_a : std_logic_vector(7 downto 0);
signal vCount_uid251_lzcZSin_uid65_fpTanTest_b : std_logic_vector(7 downto 0);
signal vCount_uid251_lzcZSin_uid65_fpTanTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid254_lzcZSin_uid65_fpTanTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid254_lzcZSin_uid65_fpTanTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid260_lzcZSin_uid65_fpTanTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid260_lzcZSin_uid65_fpTanTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_q : std_logic_vector (64 downto 0);
signal vStagei_uid321_lzcZCos_uid68_fpTanTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid321_lzcZCos_uid68_fpTanTest_q : std_logic_vector (31 downto 0);
signal vCount_uid330_lzcZCos_uid68_fpTanTest_a : std_logic_vector(7 downto 0);
signal vCount_uid330_lzcZCos_uid68_fpTanTest_b : std_logic_vector(7 downto 0);
signal vCount_uid330_lzcZCos_uid68_fpTanTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid333_lzcZCos_uid68_fpTanTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid333_lzcZCos_uid68_fpTanTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid339_lzcZCos_uid68_fpTanTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid339_lzcZCos_uid68_fpTanTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_q : std_logic_vector (64 downto 0);
signal exc_R_uid450_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid450_fpTanXComp_uid157_fpTanTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid450_fpTanXComp_uid157_fpTanTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid450_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid466_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid466_fpTanXComp_uid157_fpTanTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid466_fpTanXComp_uid157_fpTanTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid466_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal expFracPostRnd_uid490_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(35 downto 0);
signal expFracPostRnd_uid490_fpTanXComp_uid157_fpTanTest_b : std_logic_vector(35 downto 0);
signal expFracPostRnd_uid490_fpTanXComp_uid157_fpTanTest_o : std_logic_vector (35 downto 0);
signal expFracPostRnd_uid490_fpTanXComp_uid157_fpTanTest_q : std_logic_vector (34 downto 0);
signal zeroOverReg_uid499_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(0 downto 0);
signal zeroOverReg_uid499_fpTanXComp_uid157_fpTanTest_b : std_logic_vector(0 downto 0);
signal zeroOverReg_uid499_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal regOverRegWithUf_uid500_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(0 downto 0);
signal regOverRegWithUf_uid500_fpTanXComp_uid157_fpTanTest_b : std_logic_vector(0 downto 0);
signal regOverRegWithUf_uid500_fpTanXComp_uid157_fpTanTest_c : std_logic_vector(0 downto 0);
signal regOverRegWithUf_uid500_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal xRegOrZero_uid501_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(0 downto 0);
signal xRegOrZero_uid501_fpTanXComp_uid157_fpTanTest_b : std_logic_vector(0 downto 0);
signal xRegOrZero_uid501_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal regOrZeroOverInf_uid502_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(0 downto 0);
signal regOrZeroOverInf_uid502_fpTanXComp_uid157_fpTanTest_b : std_logic_vector(0 downto 0);
signal regOrZeroOverInf_uid502_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid503_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid503_fpTanXComp_uid157_fpTanTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid503_fpTanXComp_uid157_fpTanTest_c : std_logic_vector(0 downto 0);
signal excRZero_uid503_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal excXRYZ_uid504_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(0 downto 0);
signal excXRYZ_uid504_fpTanXComp_uid157_fpTanTest_b : std_logic_vector(0 downto 0);
signal excXRYZ_uid504_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal excXRYROvf_uid505_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(0 downto 0);
signal excXRYROvf_uid505_fpTanXComp_uid157_fpTanTest_b : std_logic_vector(0 downto 0);
signal excXRYROvf_uid505_fpTanXComp_uid157_fpTanTest_c : std_logic_vector(0 downto 0);
signal excXRYROvf_uid505_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal excXIYR_uid507_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(0 downto 0);
signal excXIYR_uid507_fpTanXComp_uid157_fpTanTest_b : std_logic_vector(0 downto 0);
signal excXIYR_uid507_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal excRInf_uid508_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(0 downto 0);
signal excRInf_uid508_fpTanXComp_uid157_fpTanTest_b : std_logic_vector(0 downto 0);
signal excRInf_uid508_fpTanXComp_uid157_fpTanTest_c : std_logic_vector(0 downto 0);
signal excRInf_uid508_fpTanXComp_uid157_fpTanTest_d : std_logic_vector(0 downto 0);
signal excRInf_uid508_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid511_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid511_fpTanXComp_uid157_fpTanTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid511_fpTanXComp_uid157_fpTanTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid511_fpTanXComp_uid157_fpTanTest_d : std_logic_vector(0 downto 0);
signal excRNaN_uid511_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid513_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid517_fpTanXComp_uid157_fpTanTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid517_fpTanXComp_uid157_fpTanTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid521_fpTanXComp_uid157_fpTanTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid521_fpTanXComp_uid157_fpTanTest_q : std_logic_vector (7 downto 0);
signal vCount_uid528_zCount_uid194_rrx_uid34_fpTanTest_a : std_logic_vector(15 downto 0);
signal vCount_uid528_zCount_uid194_rrx_uid34_fpTanTest_b : std_logic_vector(15 downto 0);
signal vCount_uid528_zCount_uid194_rrx_uid34_fpTanTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid533_zCount_uid194_rrx_uid34_fpTanTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid533_zCount_uid194_rrx_uid34_fpTanTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid539_zCount_uid194_rrx_uid34_fpTanTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid539_zCount_uid194_rrx_uid34_fpTanTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid551_zCount_uid194_rrx_uid34_fpTanTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid551_zCount_uid194_rrx_uid34_fpTanTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_q : std_logic_vector (75 downto 0);
signal ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1_uid560_normMult_uid195_rrx_uid34_fpTanTest_q : std_logic_vector (75 downto 0);
signal extendedFracX_uid47_fpTanTest_q : std_logic_vector (67 downto 0);
signal normBitSin_uid92_fpTanTest_in : std_logic_vector (51 downto 0);
signal normBitSin_uid92_fpTanTest_b : std_logic_vector (0 downto 0);
signal fracRSinPreRndHigh_uid94_fpTanTest_in : std_logic_vector (50 downto 0);
signal fracRSinPreRndHigh_uid94_fpTanTest_b : std_logic_vector (23 downto 0);
signal fracRSinPreRndLow_uid95_fpTanTest_in : std_logic_vector (49 downto 0);
signal fracRSinPreRndLow_uid95_fpTanTest_b : std_logic_vector (23 downto 0);
signal normBitCos_uid105_fpTanTest_in : std_logic_vector (51 downto 0);
signal normBitCos_uid105_fpTanTest_b : std_logic_vector (0 downto 0);
signal fracRCosPreRndHigh_uid107_fpTanTest_in : std_logic_vector (50 downto 0);
signal fracRCosPreRndHigh_uid107_fpTanTest_b : std_logic_vector (23 downto 0);
signal fracRCosPreRndLow_uid108_fpTanTest_in : std_logic_vector (49 downto 0);
signal fracRCosPreRndLow_uid108_fpTanTest_b : std_logic_vector (23 downto 0);
signal fracXRExt_uid200_rrx_uid34_fpTanTest_q : std_logic_vector (52 downto 0);
signal leftShiftStage2Idx2_uid296_alignedZSin_uid66_fpTanTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid375_alignedZCos_uid69_fpTanTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid222_fxpX_uid48_fpTanTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx1_uid293_alignedZSin_uid66_fpTanTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx1_uid372_alignedZCos_uid69_fpTanTest_q : std_logic_vector (64 downto 0);
signal oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_q : std_logic_vector (25 downto 0);
signal leftShiftStage1Idx3_uid225_fxpX_uid48_fpTanTest_q : std_logic_vector (67 downto 0);
signal cStage_uid234_lzcZSin_uid65_fpTanTest_q : std_logic_vector (63 downto 0);
signal cStage_uid313_lzcZCos_uid68_fpTanTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx2_uid563_normMult_uid195_rrx_uid34_fpTanTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0Idx3_uid566_normMult_uid195_rrx_uid34_fpTanTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage2Idx3_uid299_alignedZSin_uid66_fpTanTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx3_uid378_alignedZCos_uid69_fpTanTest_q : std_logic_vector (64 downto 0);
signal vStagei_uid315_lzcZCos_uid68_fpTanTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid315_lzcZCos_uid68_fpTanTest_q : std_logic_vector (63 downto 0);
signal prodXYTruncFR_uid587_pT1_uid400_polyEvalsinPiZ_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid587_pT1_uid400_polyEvalsinPiZ_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid590_pT2_uid406_polyEvalsinPiZ_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid590_pT2_uid406_polyEvalsinPiZ_b : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid593_pT1_uid413_polyEvalcosPiZ_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid593_pT1_uid413_polyEvalcosPiZ_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid596_pT2_uid419_polyEvalcosPiZ_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid596_pT2_uid419_polyEvalcosPiZ_b : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid618_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_in : std_logic_vector (49 downto 0);
signal prodXYTruncFR_uid618_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_b : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid621_pT1_uid605_invPE_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid621_pT1_uid605_invPE_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid624_pT2_uid611_invPE_in : std_logic_vector (36 downto 0);
signal prodXYTruncFR_uid624_pT2_uid611_invPE_b : std_logic_vector (23 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_align_0_q_int : std_logic_vector (53 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_align_0_q : std_logic_vector (53 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_align_1_q_int : std_logic_vector (80 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_align_1_q : std_logic_vector (80 downto 0);
signal os_uid189_rrx_uid34_fpTanTest_q : std_logic_vector (77 downto 0);
signal finalFrac_uid201_rrx_uid34_fpTanTest_s : std_logic_vector (0 downto 0);
signal finalFrac_uid201_rrx_uid34_fpTanTest_q : std_logic_vector (52 downto 0);
signal leftShiftStage1_uid227_fxpX_uid48_fpTanTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid227_fxpX_uid48_fpTanTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2_uid301_alignedZSin_uid66_fpTanTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid301_alignedZSin_uid66_fpTanTest_q : std_logic_vector (64 downto 0);
signal join_uid98_fpTanTest_q : std_logic_vector (1 downto 0);
signal join_uid137_fpTanTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_q : std_logic_vector (64 downto 0);
signal join_uid139_fpTanTest_q : std_logic_vector (2 downto 0);
signal zSinYBottom_uid58_fpTanTest_in : std_logic_vector (64 downto 0);
signal zSinYBottom_uid58_fpTanTest_b : std_logic_vector (64 downto 0);
signal zSinOMyBottom_uid57_fpTanTest_in : std_logic_vector (64 downto 0);
signal zSinOMyBottom_uid57_fpTanTest_b : std_logic_vector (64 downto 0);
signal excSelBitsSin_uid117_fpTanTest_q : std_logic_vector (2 downto 0);
signal expSelBitsCos_uid140_fpTanTest_q : std_logic_vector (3 downto 0);
signal fpSin_uid130_fpTanTest_q : std_logic_vector (31 downto 0);
signal fpCos_uid155_fpTanTest_q : std_logic_vector (31 downto 0);
signal RRangeRed_uid203_rrx_uid34_fpTanTest_q : std_logic_vector (61 downto 0);
signal vStagei_uid236_lzcZSin_uid65_fpTanTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid236_lzcZSin_uid65_fpTanTest_q : std_logic_vector (63 downto 0);
signal divValPreNormTrunc_uid482_fpTanXComp_uid157_fpTanTest_s : std_logic_vector (0 downto 0);
signal divValPreNormTrunc_uid482_fpTanXComp_uid157_fpTanTest_q : std_logic_vector (25 downto 0);
signal concExc_uid512_fpTanXComp_uid157_fpTanTest_q : std_logic_vector (2 downto 0);
signal divR_uid524_fpTanXComp_uid157_fpTanTest_q : std_logic_vector (31 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_align_2_q_int : std_logic_vector (107 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_align_2_q : std_logic_vector (107 downto 0);
signal ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_cmp_a : std_logic_vector(3 downto 0);
signal ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_cmp_b : std_logic_vector(3 downto 0);
signal ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_nor_q : std_logic_vector(0 downto 0);
signal fracX_uid180_rrx_uid34_fpTanTest_in : std_logic_vector (22 downto 0);
signal fracX_uid180_rrx_uid34_fpTanTest_b : std_logic_vector (22 downto 0);
signal ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_nor_q : std_logic_vector(0 downto 0);
signal oFracXRRSmallXRR_uid89_fpTanTest_in : std_logic_vector (53 downto 0);
signal oFracXRRSmallXRR_uid89_fpTanTest_b : std_logic_vector (25 downto 0);
signal R_uid160_px_uid33_fpTanTest_q : std_logic_vector (31 downto 0);
signal InvFracXIsZero_uid16_fpTanTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid16_fpTanTest_q : std_logic_vector(0 downto 0);
signal addr_uid80_fpTanTest_in : std_logic_vector (64 downto 0);
signal addr_uid80_fpTanTest_b : std_logic_vector (7 downto 0);
signal zPsinPiZ_uid83_fpTanTest_in : std_logic_vector (56 downto 0);
signal zPsinPiZ_uid83_fpTanTest_b : std_logic_vector (14 downto 0);
signal rVStage_uid230_lzcZSin_uid65_fpTanTest_in : std_logic_vector (64 downto 0);
signal rVStage_uid230_lzcZSin_uid65_fpTanTest_b : std_logic_vector (63 downto 0);
signal vStage_uid233_lzcZSin_uid65_fpTanTest_in : std_logic_vector (0 downto 0);
signal vStage_uid233_lzcZSin_uid65_fpTanTest_b : std_logic_vector (0 downto 0);
signal X32dto0_uid274_alignedZSin_uid66_fpTanTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid274_alignedZSin_uid66_fpTanTest_b : std_logic_vector (32 downto 0);
signal addr_uid82_fpTanTest_in : std_logic_vector (64 downto 0);
signal addr_uid82_fpTanTest_b : std_logic_vector (7 downto 0);
signal zPcosPiZ_uid86_fpTanTest_in : std_logic_vector (56 downto 0);
signal zPcosPiZ_uid86_fpTanTest_b : std_logic_vector (14 downto 0);
signal rVStage_uid309_lzcZCos_uid68_fpTanTest_in : std_logic_vector (64 downto 0);
signal rVStage_uid309_lzcZCos_uid68_fpTanTest_b : std_logic_vector (63 downto 0);
signal vStage_uid312_lzcZCos_uid68_fpTanTest_in : std_logic_vector (0 downto 0);
signal vStage_uid312_lzcZCos_uid68_fpTanTest_b : std_logic_vector (0 downto 0);
signal X32dto0_uid353_alignedZCos_uid69_fpTanTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid353_alignedZCos_uid69_fpTanTest_b : std_logic_vector (32 downto 0);
signal expSinHCR_uid74_fpTanTest_in : std_logic_vector (7 downto 0);
signal expSinHCR_uid74_fpTanTest_b : std_logic_vector (7 downto 0);
signal expPCos_uid78_fpTanTest_in : std_logic_vector (7 downto 0);
signal expPCos_uid78_fpTanTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid244_lzcZSin_uid65_fpTanTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid244_lzcZSin_uid65_fpTanTest_b : std_logic_vector (15 downto 0);
signal vStage_uid246_lzcZSin_uid65_fpTanTest_in : std_logic_vector (15 downto 0);
signal vStage_uid246_lzcZSin_uid65_fpTanTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid256_lzcZSin_uid65_fpTanTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid256_lzcZSin_uid65_fpTanTest_b : std_logic_vector (3 downto 0);
signal vStage_uid258_lzcZSin_uid65_fpTanTest_in : std_logic_vector (3 downto 0);
signal vStage_uid258_lzcZSin_uid65_fpTanTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid262_lzcZSin_uid65_fpTanTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid262_lzcZSin_uid65_fpTanTest_b : std_logic_vector (1 downto 0);
signal vStage_uid264_lzcZSin_uid65_fpTanTest_in : std_logic_vector (1 downto 0);
signal vStage_uid264_lzcZSin_uid65_fpTanTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage162dto0_uid292_alignedZSin_uid66_fpTanTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage162dto0_uid292_alignedZSin_uid66_fpTanTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage160dto0_uid295_alignedZSin_uid66_fpTanTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid295_alignedZSin_uid66_fpTanTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage158dto0_uid298_alignedZSin_uid66_fpTanTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid298_alignedZSin_uid66_fpTanTest_b : std_logic_vector (58 downto 0);
signal rVStage_uid323_lzcZCos_uid68_fpTanTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid323_lzcZCos_uid68_fpTanTest_b : std_logic_vector (15 downto 0);
signal vStage_uid325_lzcZCos_uid68_fpTanTest_in : std_logic_vector (15 downto 0);
signal vStage_uid325_lzcZCos_uid68_fpTanTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid335_lzcZCos_uid68_fpTanTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid335_lzcZCos_uid68_fpTanTest_b : std_logic_vector (3 downto 0);
signal vStage_uid337_lzcZCos_uid68_fpTanTest_in : std_logic_vector (3 downto 0);
signal vStage_uid337_lzcZCos_uid68_fpTanTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid341_lzcZCos_uid68_fpTanTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid341_lzcZCos_uid68_fpTanTest_b : std_logic_vector (1 downto 0);
signal vStage_uid343_lzcZCos_uid68_fpTanTest_in : std_logic_vector (1 downto 0);
signal vStage_uid343_lzcZCos_uid68_fpTanTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage162dto0_uid371_alignedZCos_uid69_fpTanTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage162dto0_uid371_alignedZCos_uid69_fpTanTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage160dto0_uid374_alignedZCos_uid69_fpTanTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid374_alignedZCos_uid69_fpTanTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage158dto0_uid377_alignedZCos_uid69_fpTanTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid377_alignedZCos_uid69_fpTanTest_b : std_logic_vector (58 downto 0);
signal fracRPreExc_uid492_fpTanXComp_uid157_fpTanTest_in : std_logic_vector (23 downto 0);
signal fracRPreExc_uid492_fpTanXComp_uid157_fpTanTest_b : std_logic_vector (22 downto 0);
signal excRPreExc_uid493_fpTanXComp_uid157_fpTanTest_in : std_logic_vector (31 downto 0);
signal excRPreExc_uid493_fpTanXComp_uid157_fpTanTest_b : std_logic_vector (7 downto 0);
signal expRExt_uid494_fpTanXComp_uid157_fpTanTest_in : std_logic_vector (34 downto 0);
signal expRExt_uid494_fpTanXComp_uid157_fpTanTest_b : std_logic_vector (10 downto 0);
signal InvExcRNaN_uid522_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid522_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid535_zCount_uid194_rrx_uid34_fpTanTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid535_zCount_uid194_rrx_uid34_fpTanTest_b : std_logic_vector (7 downto 0);
signal vStage_uid537_zCount_uid194_rrx_uid34_fpTanTest_in : std_logic_vector (7 downto 0);
signal vStage_uid537_zCount_uid194_rrx_uid34_fpTanTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid541_zCount_uid194_rrx_uid34_fpTanTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid541_zCount_uid194_rrx_uid34_fpTanTest_b : std_logic_vector (3 downto 0);
signal vStage_uid543_zCount_uid194_rrx_uid34_fpTanTest_in : std_logic_vector (3 downto 0);
signal vStage_uid543_zCount_uid194_rrx_uid34_fpTanTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid553_zCount_uid194_rrx_uid34_fpTanTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid553_zCount_uid194_rrx_uid34_fpTanTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage174dto0_uid581_normMult_uid195_rrx_uid34_fpTanTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid581_normMult_uid195_rrx_uid34_fpTanTest_b : std_logic_vector (74 downto 0);
signal X63dto0_uid207_fxpX_uid48_fpTanTest_in : std_logic_vector (63 downto 0);
signal X63dto0_uid207_fxpX_uid48_fpTanTest_b : std_logic_vector (63 downto 0);
signal X59dto0_uid210_fxpX_uid48_fpTanTest_in : std_logic_vector (59 downto 0);
signal X59dto0_uid210_fxpX_uid48_fpTanTest_b : std_logic_vector (59 downto 0);
signal X55dto0_uid213_fxpX_uid48_fpTanTest_in : std_logic_vector (55 downto 0);
signal X55dto0_uid213_fxpX_uid48_fpTanTest_b : std_logic_vector (55 downto 0);
signal fracRSinPreRnd_uid96_fpTanTest_s : std_logic_vector (0 downto 0);
signal fracRSinPreRnd_uid96_fpTanTest_q : std_logic_vector (23 downto 0);
signal fracRCosPreRnd_uid109_fpTanTest_s : std_logic_vector (0 downto 0);
signal fracRCosPreRnd_uid109_fpTanTest_q : std_logic_vector (23 downto 0);
signal cosRndOp_uid111_uid112_fpTanTest_q : std_logic_vector (24 downto 0);
signal rVStage_uid317_lzcZCos_uid68_fpTanTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid317_lzcZCos_uid68_fpTanTest_b : std_logic_vector (31 downto 0);
signal vStage_uid319_lzcZCos_uid68_fpTanTest_in : std_logic_vector (31 downto 0);
signal vStage_uid319_lzcZCos_uid68_fpTanTest_b : std_logic_vector (31 downto 0);
signal lowRangeB_uid401_polyEvalsinPiZ_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid401_polyEvalsinPiZ_b : std_logic_vector (0 downto 0);
signal highBBits_uid402_polyEvalsinPiZ_in : std_logic_vector (13 downto 0);
signal highBBits_uid402_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid407_polyEvalsinPiZ_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid407_polyEvalsinPiZ_b : std_logic_vector (1 downto 0);
signal highBBits_uid408_polyEvalsinPiZ_in : std_logic_vector (23 downto 0);
signal highBBits_uid408_polyEvalsinPiZ_b : std_logic_vector (21 downto 0);
signal lowRangeB_uid414_polyEvalcosPiZ_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid414_polyEvalcosPiZ_b : std_logic_vector (0 downto 0);
signal highBBits_uid415_polyEvalcosPiZ_in : std_logic_vector (13 downto 0);
signal highBBits_uid415_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid420_polyEvalcosPiZ_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid420_polyEvalcosPiZ_b : std_logic_vector (1 downto 0);
signal highBBits_uid421_polyEvalcosPiZ_in : std_logic_vector (23 downto 0);
signal highBBits_uid421_polyEvalcosPiZ_b : std_logic_vector (21 downto 0);
signal lowRangeB_uid606_invPE_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid606_invPE_b : std_logic_vector (0 downto 0);
signal highBBits_uid607_invPE_in : std_logic_vector (12 downto 0);
signal highBBits_uid607_invPE_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid612_invPE_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid612_invPE_b : std_logic_vector (1 downto 0);
signal highBBits_uid613_invPE_in : std_logic_vector (23 downto 0);
signal highBBits_uid613_invPE_b : std_logic_vector (21 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_a_0_in : std_logic_vector (26 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_a_0_b : std_logic_vector (26 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_a_1_in : std_logic_vector (53 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_a_1_b : std_logic_vector (26 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_a_2_in : std_logic_vector (80 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_a_2_b : std_logic_vector (26 downto 0);
signal intXParity_uid49_fpTanTest_in : std_logic_vector (67 downto 0);
signal intXParity_uid49_fpTanTest_b : std_logic_vector (0 downto 0);
signal y_uid50_fpTanTest_in : std_logic_vector (66 downto 0);
signal y_uid50_fpTanTest_b : std_logic_vector (65 downto 0);
signal LeftShiftStage263dto0_uid303_alignedZSin_uid66_fpTanTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage263dto0_uid303_alignedZSin_uid66_fpTanTest_b : std_logic_vector (63 downto 0);
signal sinRndOp_uid99_uid100_fpTanTest_q : std_logic_vector (25 downto 0);
signal LeftShiftStage263dto0_uid382_alignedZCos_uid69_fpTanTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage263dto0_uid382_alignedZCos_uid69_fpTanTest_b : std_logic_vector (63 downto 0);
signal expX_uid428_fpTanXComp_uid157_fpTanTest_in : std_logic_vector (30 downto 0);
signal expX_uid428_fpTanXComp_uid157_fpTanTest_b : std_logic_vector (7 downto 0);
signal fracX_uid429_fpTanXComp_uid157_fpTanTest_in : std_logic_vector (22 downto 0);
signal fracX_uid429_fpTanXComp_uid157_fpTanTest_b : std_logic_vector (22 downto 0);
signal signX_uid430_fpTanXComp_uid157_fpTanTest_in : std_logic_vector (31 downto 0);
signal signX_uid430_fpTanXComp_uid157_fpTanTest_b : std_logic_vector (0 downto 0);
signal expY_uid431_fpTanXComp_uid157_fpTanTest_in : std_logic_vector (30 downto 0);
signal expY_uid431_fpTanXComp_uid157_fpTanTest_b : std_logic_vector (7 downto 0);
signal fracY_uid432_fpTanXComp_uid157_fpTanTest_in : std_logic_vector (22 downto 0);
signal fracY_uid432_fpTanXComp_uid157_fpTanTest_b : std_logic_vector (22 downto 0);
signal signY_uid433_fpTanXComp_uid157_fpTanTest_in : std_logic_vector (31 downto 0);
signal signY_uid433_fpTanXComp_uid157_fpTanTest_b : std_logic_vector (0 downto 0);
signal fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_in : std_logic_vector (22 downto 0);
signal fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_b : std_logic_vector (8 downto 0);
signal yPE_uid472_fpTanXComp_uid157_fpTanTest_in : std_logic_vector (13 downto 0);
signal yPE_uid472_fpTanXComp_uid157_fpTanTest_b : std_logic_vector (13 downto 0);
signal expXRR_uid39_fpTanTest_in : std_logic_vector (60 downto 0);
signal expXRR_uid39_fpTanTest_b : std_logic_vector (7 downto 0);
signal fracXRR_uid40_fpTanTest_in : std_logic_vector (52 downto 0);
signal fracXRR_uid40_fpTanTest_b : std_logic_vector (52 downto 0);
signal rVStage_uid238_lzcZSin_uid65_fpTanTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid238_lzcZSin_uid65_fpTanTest_b : std_logic_vector (31 downto 0);
signal vStage_uid240_lzcZSin_uid65_fpTanTest_in : std_logic_vector (31 downto 0);
signal vStage_uid240_lzcZSin_uid65_fpTanTest_b : std_logic_vector (31 downto 0);
signal norm_uid483_fpTanXComp_uid157_fpTanTest_in : std_logic_vector (25 downto 0);
signal norm_uid483_fpTanXComp_uid157_fpTanTest_b : std_logic_vector (0 downto 0);
signal divValPreNormHigh_uid484_fpTanXComp_uid157_fpTanTest_in : std_logic_vector (24 downto 0);
signal divValPreNormHigh_uid484_fpTanXComp_uid157_fpTanTest_b : std_logic_vector (23 downto 0);
signal divValPreNormLow_uid485_fpTanXComp_uid157_fpTanTest_in : std_logic_vector (23 downto 0);
signal divValPreNormLow_uid485_fpTanXComp_uid157_fpTanTest_b : std_logic_vector (23 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_result_add_1_0_a : std_logic_vector(108 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_result_add_1_0_b : std_logic_vector(108 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_result_add_1_0_o : std_logic_vector (108 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_result_add_1_0_q : std_logic_vector (108 downto 0);
signal oFracX_uid190_uid190_rrx_uid34_fpTanTest_q : std_logic_vector (23 downto 0);
signal expX_uid179_rrx_uid34_fpTanTest_in : std_logic_vector (30 downto 0);
signal expX_uid179_rrx_uid34_fpTanTest_b : std_logic_vector (7 downto 0);
signal exc_N_uid17_fpTanTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpTanTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpTanTest_q : std_logic_vector(0 downto 0);
signal yT1_uid399_polyEvalsinPiZ_in : std_logic_vector (14 downto 0);
signal yT1_uid399_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal yT1_uid412_polyEvalcosPiZ_in : std_logic_vector (14 downto 0);
signal yT1_uid412_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal vCount_uid245_lzcZSin_uid65_fpTanTest_a : std_logic_vector(15 downto 0);
signal vCount_uid245_lzcZSin_uid65_fpTanTest_b : std_logic_vector(15 downto 0);
signal vCount_uid245_lzcZSin_uid65_fpTanTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid248_lzcZSin_uid65_fpTanTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid248_lzcZSin_uid65_fpTanTest_q : std_logic_vector (15 downto 0);
signal vCount_uid263_lzcZSin_uid65_fpTanTest_a : std_logic_vector(1 downto 0);
signal vCount_uid263_lzcZSin_uid65_fpTanTest_b : std_logic_vector(1 downto 0);
signal vCount_uid263_lzcZSin_uid65_fpTanTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid266_lzcZSin_uid65_fpTanTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid266_lzcZSin_uid65_fpTanTest_q : std_logic_vector (1 downto 0);
signal vCount_uid324_lzcZCos_uid68_fpTanTest_a : std_logic_vector(15 downto 0);
signal vCount_uid324_lzcZCos_uid68_fpTanTest_b : std_logic_vector(15 downto 0);
signal vCount_uid324_lzcZCos_uid68_fpTanTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid327_lzcZCos_uid68_fpTanTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid327_lzcZCos_uid68_fpTanTest_q : std_logic_vector (15 downto 0);
signal vCount_uid342_lzcZCos_uid68_fpTanTest_a : std_logic_vector(1 downto 0);
signal vCount_uid342_lzcZCos_uid68_fpTanTest_b : std_logic_vector(1 downto 0);
signal vCount_uid342_lzcZCos_uid68_fpTanTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid345_lzcZCos_uid68_fpTanTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid345_lzcZCos_uid68_fpTanTest_q : std_logic_vector (1 downto 0);
signal sRPostExc_uid523_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(0 downto 0);
signal sRPostExc_uid523_fpTanXComp_uid157_fpTanTest_b : std_logic_vector(0 downto 0);
signal sRPostExc_uid523_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal vCount_uid542_zCount_uid194_rrx_uid34_fpTanTest_a : std_logic_vector(3 downto 0);
signal vCount_uid542_zCount_uid194_rrx_uid34_fpTanTest_b : std_logic_vector(3 downto 0);
signal vCount_uid542_zCount_uid194_rrx_uid34_fpTanTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid545_zCount_uid194_rrx_uid34_fpTanTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid545_zCount_uid194_rrx_uid34_fpTanTest_q : std_logic_vector (3 downto 0);
signal vCount_uid554_zCount_uid194_rrx_uid34_fpTanTest_a : std_logic_vector(0 downto 0);
signal vCount_uid554_zCount_uid194_rrx_uid34_fpTanTest_b : std_logic_vector(0 downto 0);
signal vCount_uid554_zCount_uid194_rrx_uid34_fpTanTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage2Idx1_uid582_normMult_uid195_rrx_uid34_fpTanTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0Idx1_uid208_fxpX_uid48_fpTanTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage0Idx2_uid211_fxpX_uid48_fpTanTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage0Idx3_uid214_fxpX_uid48_fpTanTest_q : std_logic_vector (67 downto 0);
signal expFracRSinPreRnd_uid97_uid97_fpTanTest_q : std_logic_vector (31 downto 0);
signal expFracRCosPreRnd_uid110_uid110_fpTanTest_q : std_logic_vector (31 downto 0);
signal expFracRCos_uid113_fpTanTest_a : std_logic_vector(32 downto 0);
signal expFracRCos_uid113_fpTanTest_b : std_logic_vector(32 downto 0);
signal expFracRCos_uid113_fpTanTest_o : std_logic_vector (32 downto 0);
signal expFracRCos_uid113_fpTanTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid403_polyEvalsinPiZ_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid403_polyEvalsinPiZ_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid403_polyEvalsinPiZ_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid403_polyEvalsinPiZ_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid409_polyEvalsinPiZ_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid409_polyEvalsinPiZ_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid409_polyEvalsinPiZ_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid409_polyEvalsinPiZ_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid416_polyEvalcosPiZ_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid416_polyEvalcosPiZ_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid416_polyEvalcosPiZ_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid416_polyEvalcosPiZ_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid422_polyEvalcosPiZ_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid422_polyEvalcosPiZ_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid422_polyEvalcosPiZ_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid422_polyEvalcosPiZ_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid608_invPE_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid608_invPE_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid608_invPE_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid608_invPE_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid614_invPE_a : std_logic_vector(31 downto 0);
signal sumAHighB_uid614_invPE_b : std_logic_vector(31 downto 0);
signal sumAHighB_uid614_invPE_o : std_logic_vector (31 downto 0);
signal sumAHighB_uid614_invPE_q : std_logic_vector (31 downto 0);
signal signComp_uid128_fpTanTest_a : std_logic_vector(0 downto 0);
signal signComp_uid128_fpTanTest_b : std_logic_vector(0 downto 0);
signal signComp_uid128_fpTanTest_c : std_logic_vector(0 downto 0);
signal signComp_uid128_fpTanTest_q : std_logic_vector(0 downto 0);
signal InvIntXParity_uid151_fpTanTest_a : std_logic_vector(0 downto 0);
signal InvIntXParity_uid151_fpTanTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage3Idx1_uid304_alignedZSin_uid66_fpTanTest_q : std_logic_vector (64 downto 0);
signal expFracRSin_uid101_fpTanTest_a : std_logic_vector(32 downto 0);
signal expFracRSin_uid101_fpTanTest_b : std_logic_vector(32 downto 0);
signal expFracRSin_uid101_fpTanTest_o : std_logic_vector (32 downto 0);
signal expFracRSin_uid101_fpTanTest_q : std_logic_vector (32 downto 0);
signal leftShiftStage3Idx1_uid383_alignedZCos_uid69_fpTanTest_q : std_logic_vector (64 downto 0);
signal expXIsZero_uid439_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid439_fpTanXComp_uid157_fpTanTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid439_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid441_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid441_fpTanXComp_uid157_fpTanTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid441_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid443_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid443_fpTanXComp_uid157_fpTanTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid443_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal expXIsZero_uid455_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid455_fpTanXComp_uid157_fpTanTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid455_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid457_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid457_fpTanXComp_uid157_fpTanTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid457_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal fracYZero_uid434_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(22 downto 0);
signal fracYZero_uid434_fpTanXComp_uid157_fpTanTest_b : std_logic_vector(22 downto 0);
signal fracYZero_uid434_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid459_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid459_fpTanXComp_uid157_fpTanTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid459_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal yT1_uid604_invPE_in : std_logic_vector (13 downto 0);
signal yT1_uid604_invPE_b : std_logic_vector (11 downto 0);
signal sinXIsXRR_uid42_fpTanTest_a : std_logic_vector(11 downto 0);
signal sinXIsXRR_uid42_fpTanTest_b : std_logic_vector(11 downto 0);
signal sinXIsXRR_uid42_fpTanTest_o : std_logic_vector (11 downto 0);
signal sinXIsXRR_uid42_fpTanTest_cin : std_logic_vector (0 downto 0);
signal sinXIsXRR_uid42_fpTanTest_n : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid43_fpTanTest_a : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid43_fpTanTest_b : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid43_fpTanTest_o : std_logic_vector (11 downto 0);
signal cosXIsOneXRR_uid43_fpTanTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid43_fpTanTest_n : std_logic_vector (0 downto 0);
signal fxpXShiftValExt_uid45_fpTanTest_a : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid45_fpTanTest_b : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid45_fpTanTest_o : std_logic_vector (10 downto 0);
signal fxpXShiftValExt_uid45_fpTanTest_q : std_logic_vector (9 downto 0);
signal normFracRnd_uid486_fpTanXComp_uid157_fpTanTest_s : std_logic_vector (0 downto 0);
signal normFracRnd_uid486_fpTanXComp_uid157_fpTanTest_q : std_logic_vector (23 downto 0);
signal multFracBits_uid192_rrx_uid34_fpTanTest_in : std_logic_vector (75 downto 0);
signal multFracBits_uid192_rrx_uid34_fpTanTest_b : std_logic_vector (75 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_b_0_in : std_logic_vector (26 downto 0);
signal prod_uid191_rrx_uid34_fpTanTest_b_0_b : std_logic_vector (26 downto 0);
signal expXTableAddrExt_uid185_rrx_uid34_fpTanTest_a : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid185_rrx_uid34_fpTanTest_b : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid185_rrx_uid34_fpTanTest_o : std_logic_vector (8 downto 0);
signal expXTableAddrExt_uid185_rrx_uid34_fpTanTest_q : std_logic_vector (8 downto 0);
signal rVStage_uid250_lzcZSin_uid65_fpTanTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid250_lzcZSin_uid65_fpTanTest_b : std_logic_vector (7 downto 0);
signal vStage_uid252_lzcZSin_uid65_fpTanTest_in : std_logic_vector (7 downto 0);
signal vStage_uid252_lzcZSin_uid65_fpTanTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid268_lzcZSin_uid65_fpTanTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid268_lzcZSin_uid65_fpTanTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid329_lzcZCos_uid68_fpTanTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid329_lzcZCos_uid68_fpTanTest_b : std_logic_vector (7 downto 0);
signal vStage_uid331_lzcZCos_uid68_fpTanTest_in : std_logic_vector (7 downto 0);
signal vStage_uid331_lzcZCos_uid68_fpTanTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid347_lzcZCos_uid68_fpTanTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid347_lzcZCos_uid68_fpTanTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid547_zCount_uid194_rrx_uid34_fpTanTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid547_zCount_uid194_rrx_uid34_fpTanTest_b : std_logic_vector (1 downto 0);
signal vStage_uid549_zCount_uid194_rrx_uid34_fpTanTest_in : std_logic_vector (1 downto 0);
signal vStage_uid549_zCount_uid194_rrx_uid34_fpTanTest_b : std_logic_vector (1 downto 0);
signal r_uid555_zCount_uid194_rrx_uid34_fpTanTest_q : std_logic_vector (4 downto 0);
signal leftShiftStage2_uid584_normMult_uid195_rrx_uid34_fpTanTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage2_uid584_normMult_uid195_rrx_uid34_fpTanTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0_uid216_fxpX_uid48_fpTanTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid216_fxpX_uid48_fpTanTest_q : std_logic_vector (67 downto 0);
signal fracRCompCos_uid114_fpTanTest_in : std_logic_vector (23 downto 0);
signal fracRCompCos_uid114_fpTanTest_b : std_logic_vector (22 downto 0);
signal expRCompSin_uid115_fpTanTest_in : std_logic_vector (31 downto 0);
signal expRCompSin_uid115_fpTanTest_b : std_logic_vector (7 downto 0);
signal s1_uid401_uid404_polyEvalsinPiZ_q : std_logic_vector (22 downto 0);
signal s2_uid407_uid410_polyEvalsinPiZ_q : std_logic_vector (32 downto 0);
signal s1_uid414_uid417_polyEvalcosPiZ_q : std_logic_vector (22 downto 0);
signal s2_uid420_uid423_polyEvalcosPiZ_q : std_logic_vector (32 downto 0);
signal s1_uid606_uid609_invPE_q : std_logic_vector (22 downto 0);
signal s2_uid612_uid615_invPE_q : std_logic_vector (33 downto 0);
signal leftShiftStage3_uid306_alignedZSin_uid66_fpTanTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid306_alignedZSin_uid66_fpTanTest_q : std_logic_vector (64 downto 0);
signal fracRCompSin_uid102_fpTanTest_in : std_logic_vector (23 downto 0);
signal fracRCompSin_uid102_fpTanTest_b : std_logic_vector (22 downto 0);
signal expRCompSin_uid103_fpTanTest_in : std_logic_vector (31 downto 0);
signal expRCompSin_uid103_fpTanTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage3_uid385_alignedZCos_uid69_fpTanTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid385_alignedZCos_uid69_fpTanTest_q : std_logic_vector (64 downto 0);
signal exc_I_uid444_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid444_fpTanXComp_uid157_fpTanTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid444_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid445_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid445_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal excXIYZ_uid506_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(0 downto 0);
signal excXIYZ_uid506_fpTanXComp_uid157_fpTanTest_b : std_logic_vector(0 downto 0);
signal excXIYZ_uid506_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid460_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid460_fpTanXComp_uid157_fpTanTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid460_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid461_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid461_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal cosOne_uid144_fpTanTest_a : std_logic_vector(0 downto 0);
signal cosOne_uid144_fpTanTest_b : std_logic_vector(0 downto 0);
signal cosOne_uid144_fpTanTest_q : std_logic_vector(0 downto 0);
signal fxpXShiftVal_uid46_fpTanTest_in : std_logic_vector (3 downto 0);
signal fxpXShiftVal_uid46_fpTanTest_b : std_logic_vector (3 downto 0);
signal expFracRnd_uid487_fpTanXComp_uid157_fpTanTest_q : std_logic_vector (33 downto 0);
signal multFracBitsTop_uid193_rrx_uid34_fpTanTest_in : std_logic_vector (75 downto 0);
signal multFracBitsTop_uid193_rrx_uid34_fpTanTest_b : std_logic_vector (29 downto 0);
signal X67dto0_uid559_normMult_uid195_rrx_uid34_fpTanTest_in : std_logic_vector (67 downto 0);
signal X67dto0_uid559_normMult_uid195_rrx_uid34_fpTanTest_b : std_logic_vector (67 downto 0);
signal X59dto0_uid562_normMult_uid195_rrx_uid34_fpTanTest_in : std_logic_vector (59 downto 0);
signal X59dto0_uid562_normMult_uid195_rrx_uid34_fpTanTest_b : std_logic_vector (59 downto 0);
signal X51dto0_uid565_normMult_uid195_rrx_uid34_fpTanTest_in : std_logic_vector (51 downto 0);
signal X51dto0_uid565_normMult_uid195_rrx_uid34_fpTanTest_b : std_logic_vector (51 downto 0);
signal expXTableAddr_uid186_rrx_uid34_fpTanTest_in : std_logic_vector (7 downto 0);
signal expXTableAddr_uid186_rrx_uid34_fpTanTest_b : std_logic_vector (7 downto 0);
signal vCount_uid269_lzcZSin_uid65_fpTanTest_a : std_logic_vector(0 downto 0);
signal vCount_uid269_lzcZSin_uid65_fpTanTest_b : std_logic_vector(0 downto 0);
signal vCount_uid269_lzcZSin_uid65_fpTanTest_q : std_logic_vector(0 downto 0);
signal vCount_uid348_lzcZCos_uid68_fpTanTest_a : std_logic_vector(0 downto 0);
signal vCount_uid348_lzcZCos_uid68_fpTanTest_b : std_logic_vector(0 downto 0);
signal vCount_uid348_lzcZCos_uid68_fpTanTest_q : std_logic_vector(0 downto 0);
signal expCompOutExt_uid197_rrx_uid34_fpTanTest_a : std_logic_vector(8 downto 0);
signal expCompOutExt_uid197_rrx_uid34_fpTanTest_b : std_logic_vector(8 downto 0);
signal expCompOutExt_uid197_rrx_uid34_fpTanTest_o : std_logic_vector (8 downto 0);
signal expCompOutExt_uid197_rrx_uid34_fpTanTest_q : std_logic_vector (8 downto 0);
signal leftShiftStageSel4Dto3_uid567_normMult_uid195_rrx_uid34_fpTanTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid567_normMult_uid195_rrx_uid34_fpTanTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid578_normMult_uid195_rrx_uid34_fpTanTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid578_normMult_uid195_rrx_uid34_fpTanTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid583_normMult_uid195_rrx_uid34_fpTanTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid583_normMult_uid195_rrx_uid34_fpTanTest_b : std_logic_vector (0 downto 0);
signal fracCompOut_uid196_rrx_uid34_fpTanTest_in : std_logic_vector (74 downto 0);
signal fracCompOut_uid196_rrx_uid34_fpTanTest_b : std_logic_vector (52 downto 0);
signal LeftShiftStage066dto0_uid218_fxpX_uid48_fpTanTest_in : std_logic_vector (66 downto 0);
signal LeftShiftStage066dto0_uid218_fxpX_uid48_fpTanTest_b : std_logic_vector (66 downto 0);
signal LeftShiftStage065dto0_uid221_fxpX_uid48_fpTanTest_in : std_logic_vector (65 downto 0);
signal LeftShiftStage065dto0_uid221_fxpX_uid48_fpTanTest_b : std_logic_vector (65 downto 0);
signal LeftShiftStage064dto0_uid224_fxpX_uid48_fpTanTest_in : std_logic_vector (64 downto 0);
signal LeftShiftStage064dto0_uid224_fxpX_uid48_fpTanTest_b : std_logic_vector (64 downto 0);
signal polyEvalSigsinPiZ_uid85_fpTanTest_in : std_logic_vector (30 downto 0);
signal polyEvalSigsinPiZ_uid85_fpTanTest_b : std_logic_vector (25 downto 0);
signal polyEvalSigcosPiZ_uid88_fpTanTest_in : std_logic_vector (30 downto 0);
signal polyEvalSigcosPiZ_uid88_fpTanTest_b : std_logic_vector (25 downto 0);
signal invY_uid474_fpTanXComp_uid157_fpTanTest_in : std_logic_vector (30 downto 0);
signal invY_uid474_fpTanXComp_uid157_fpTanTest_b : std_logic_vector (25 downto 0);
signal invYO_uid475_fpTanXComp_uid157_fpTanTest_in : std_logic_vector (31 downto 0);
signal invYO_uid475_fpTanXComp_uid157_fpTanTest_b : std_logic_vector (0 downto 0);
signal pHigh_uid71_fpTanTest_in : std_logic_vector (64 downto 0);
signal pHigh_uid71_fpTanTest_b : std_logic_vector (25 downto 0);
signal pCos_uid76_fpTanTest_in : std_logic_vector (64 downto 0);
signal pCos_uid76_fpTanTest_b : std_logic_vector (25 downto 0);
signal exc_N_uid446_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid446_fpTanXComp_uid157_fpTanTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid446_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid462_fpTanXComp_uid157_fpTanTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid462_fpTanXComp_uid157_fpTanTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid462_fpTanXComp_uid157_fpTanTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel3Dto2_uid215_fxpX_uid48_fpTanTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid215_fxpX_uid48_fpTanTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid226_fxpX_uid48_fpTanTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid226_fxpX_uid48_fpTanTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid527_zCount_uid194_rrx_uid34_fpTanTest_in : std_logic_vector (29 downto 0);
signal rVStage_uid527_zCount_uid194_rrx_uid34_fpTanTest_b : std_logic_vector (15 downto 0);
signal vStage_uid530_zCount_uid194_rrx_uid34_fpTanTest_in : std_logic_vector (13 downto 0);
signal vStage_uid530_zCount_uid194_rrx_uid34_fpTanTest_b : std_logic_vector (13 downto 0);
signal r_uid270_lzcZSin_uid65_fpTanTest_q : std_logic_vector (6 downto 0);
signal r_uid349_lzcZCos_uid68_fpTanTest_q : std_logic_vector (6 downto 0);
signal expCompOut_uid198_rrx_uid34_fpTanTest_in : std_logic_vector (7 downto 0);
signal expCompOut_uid198_rrx_uid34_fpTanTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid568_normMult_uid195_rrx_uid34_fpTanTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid568_normMult_uid195_rrx_uid34_fpTanTest_q : std_logic_vector (75 downto 0);
signal cStage_uid531_zCount_uid194_rrx_uid34_fpTanTest_q : std_logic_vector (15 downto 0);
signal leftShiftStageSel6Dto5_uid278_alignedZSin_uid66_fpTanTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid278_alignedZSin_uid66_fpTanTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid289_alignedZSin_uid66_fpTanTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid289_alignedZSin_uid66_fpTanTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid300_alignedZSin_uid66_fpTanTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid300_alignedZSin_uid66_fpTanTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid305_alignedZSin_uid66_fpTanTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid305_alignedZSin_uid66_fpTanTest_b : std_logic_vector (0 downto 0);
signal leftShiftStageSel6Dto5_uid357_alignedZCos_uid69_fpTanTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid357_alignedZCos_uid69_fpTanTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid368_alignedZCos_uid69_fpTanTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid368_alignedZCos_uid69_fpTanTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid379_alignedZCos_uid69_fpTanTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid379_alignedZCos_uid69_fpTanTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid384_alignedZCos_uid69_fpTanTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid384_alignedZCos_uid69_fpTanTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage073dto0_uid570_normMult_uid195_rrx_uid34_fpTanTest_in : std_logic_vector (73 downto 0);
signal LeftShiftStage073dto0_uid570_normMult_uid195_rrx_uid34_fpTanTest_b : std_logic_vector (73 downto 0);
signal LeftShiftStage071dto0_uid573_normMult_uid195_rrx_uid34_fpTanTest_in : std_logic_vector (71 downto 0);
signal LeftShiftStage071dto0_uid573_normMult_uid195_rrx_uid34_fpTanTest_b : std_logic_vector (71 downto 0);
signal LeftShiftStage069dto0_uid576_normMult_uid195_rrx_uid34_fpTanTest_in : std_logic_vector (69 downto 0);
signal LeftShiftStage069dto0_uid576_normMult_uid195_rrx_uid34_fpTanTest_b : std_logic_vector (69 downto 0);
signal leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx1_uid571_normMult_uid195_rrx_uid34_fpTanTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage1Idx2_uid574_normMult_uid195_rrx_uid34_fpTanTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage1Idx3_uid577_normMult_uid195_rrx_uid34_fpTanTest_q : std_logic_vector (75 downto 0);
signal LeftShiftStage056dto0_uid281_alignedZSin_uid66_fpTanTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage056dto0_uid281_alignedZSin_uid66_fpTanTest_b : std_logic_vector (56 downto 0);
signal LeftShiftStage048dto0_uid284_alignedZSin_uid66_fpTanTest_in : std_logic_vector (48 downto 0);
signal LeftShiftStage048dto0_uid284_alignedZSin_uid66_fpTanTest_b : std_logic_vector (48 downto 0);
signal LeftShiftStage040dto0_uid287_alignedZSin_uid66_fpTanTest_in : std_logic_vector (40 downto 0);
signal LeftShiftStage040dto0_uid287_alignedZSin_uid66_fpTanTest_b : std_logic_vector (40 downto 0);
signal LeftShiftStage056dto0_uid360_alignedZCos_uid69_fpTanTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage056dto0_uid360_alignedZCos_uid69_fpTanTest_b : std_logic_vector (56 downto 0);
signal LeftShiftStage048dto0_uid363_alignedZCos_uid69_fpTanTest_in : std_logic_vector (48 downto 0);
signal LeftShiftStage048dto0_uid363_alignedZCos_uid69_fpTanTest_b : std_logic_vector (48 downto 0);
signal LeftShiftStage040dto0_uid366_alignedZCos_uid69_fpTanTest_in : std_logic_vector (40 downto 0);
signal LeftShiftStage040dto0_uid366_alignedZCos_uid69_fpTanTest_b : std_logic_vector (40 downto 0);
signal leftShiftStage1Idx1_uid282_alignedZSin_uid66_fpTanTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid285_alignedZSin_uid66_fpTanTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx3_uid288_alignedZSin_uid66_fpTanTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx1_uid361_alignedZCos_uid69_fpTanTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid364_alignedZCos_uid69_fpTanTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx3_uid367_alignedZCos_uid69_fpTanTest_q : std_logic_vector (64 downto 0);
begin
--xIn(GPIN,3)@0
--cstAllZWF_uid7_fpTanTest(CONSTANT,6)
cstAllZWF_uid7_fpTanTest_q <= "00000000000000000000000";
--GND(CONSTANT,0)
GND_q <= "0";
--ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_notEnable(LOGICAL,1538)
ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_notEnable_a <= en;
ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_notEnable_q <= not ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_notEnable_a;
--ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_nor(LOGICAL,1678)
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_nor_a <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_notEnable_q;
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_nor_b <= ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_sticky_ena_q;
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_nor_q <= not (ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_nor_a or ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_nor_b);
--ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_mem_top(CONSTANT,1674)
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_mem_top_q <= "01010";
--ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_cmp(LOGICAL,1675)
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_cmp_a <= ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_mem_top_q;
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdmux_q);
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_cmp_q <= "1" when ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_cmp_a = ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_cmp_b else "0";
--ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_cmpReg(REG,1676)
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_cmpReg_q <= ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_sticky_ena(REG,1679)
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_nor_q = "1") THEN
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_sticky_ena_q <= ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_enaAnd(LOGICAL,1680)
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_enaAnd_a <= ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_sticky_ena_q;
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_enaAnd_b <= en;
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_enaAnd_q <= ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_enaAnd_a and ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_enaAnd_b;
--expFracX_uid159_px_uid33_fpTanTest(BITSELECT,158)@0
expFracX_uid159_px_uid33_fpTanTest_in <= a(30 downto 0);
expFracX_uid159_px_uid33_fpTanTest_b <= expFracX_uid159_px_uid33_fpTanTest_in(30 downto 0);
--R_uid160_px_uid33_fpTanTest(BITJOIN,159)@0
R_uid160_px_uid33_fpTanTest_q <= GND_q & expFracX_uid159_px_uid33_fpTanTest_b;
--expX_uid179_rrx_uid34_fpTanTest(BITSELECT,178)@0
expX_uid179_rrx_uid34_fpTanTest_in <= R_uid160_px_uid33_fpTanTest_q(30 downto 0);
expX_uid179_rrx_uid34_fpTanTest_b <= expX_uid179_rrx_uid34_fpTanTest_in(30 downto 23);
--ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_inputreg(DELAY,1668)
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid179_rrx_uid34_fpTanTest_b, xout => ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdcnt(COUNTER,1670)
-- every=1, low=0, high=10, step=1, init=1
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdcnt_i = 9 THEN
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdcnt_i <= ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdcnt_i - 10;
ELSE
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdcnt_i <= ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdcnt_i,4));
--ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdreg(REG,1671)
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdreg_q <= ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdmux(MUX,1672)
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdmux_s <= en;
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdmux: PROCESS (ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdmux_s, ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdreg_q, ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdmux_q <= ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdmux_q <= ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_mem(DUALMEM,1669)
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_mem_ia <= ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_inputreg_q;
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_mem_aa <= ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdreg_q;
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_mem_ab <= ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdmux_q;
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 11,
width_b => 8,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_mem_iq,
address_a => ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_mem_aa,
data_a => ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_mem_ia
);
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_mem_reset0 <= areset;
ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_mem_q <= ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_mem_iq(7 downto 0);
--zs_uid243_lzcZSin_uid65_fpTanTest(CONSTANT,242)
zs_uid243_lzcZSin_uid65_fpTanTest_q <= "0000000000000000";
--ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_nor(LOGICAL,1652)
ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_nor_a <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_notEnable_q;
ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_nor_b <= ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_sticky_ena_q;
ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_nor_q <= not (ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_nor_a or ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_nor_b);
--ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_cmpReg(REG,1574)
ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_sticky_ena(REG,1653)
ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_nor_q = "1") THEN
ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_sticky_ena_q <= ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_enaAnd(LOGICAL,1654)
ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_enaAnd_a <= ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_sticky_ena_q;
ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_enaAnd_b <= en;
ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_enaAnd_q <= ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_enaAnd_a and ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_enaAnd_b;
--ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_inputreg(DELAY,1644)
ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid160_px_uid33_fpTanTest_q, xout => ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdcnt(COUNTER,1570)
-- every=1, low=0, high=1, step=1, init=1
ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdcnt_i <= ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdcnt_i,1));
--ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdreg(REG,1571)
ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdreg_q <= ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdmux(MUX,1572)
ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdmux_s <= en;
ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdmux: PROCESS (ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdmux_s, ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdreg_q, ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdcnt_q)
BEGIN
CASE ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdmux_s IS
WHEN "0" => ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdmux_q <= ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdreg_q;
WHEN "1" => ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdmux_q <= ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_replace_mem(DUALMEM,1645)
ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_replace_mem_ia <= ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_inputreg_q;
ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_replace_mem_aa <= ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdreg_q;
ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_replace_mem_ab <= ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdmux_q;
ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 1,
numwords_a => 2,
width_b => 32,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_replace_mem_iq,
address_a => ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_replace_mem_aa,
data_a => ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_replace_mem_ia
);
ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_replace_mem_reset0 <= areset;
ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_replace_mem_q <= ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_replace_mem_iq(31 downto 0);
--fracX_uid180_rrx_uid34_fpTanTest(BITSELECT,179)@4
fracX_uid180_rrx_uid34_fpTanTest_in <= ld_R_uid160_px_uid33_fpTanTest_q_to_fracX_uid180_rrx_uid34_fpTanTest_a_replace_mem_q(22 downto 0);
fracX_uid180_rrx_uid34_fpTanTest_b <= fracX_uid180_rrx_uid34_fpTanTest_in(22 downto 0);
--oFracX_uid190_uid190_rrx_uid34_fpTanTest(BITJOIN,189)@4
oFracX_uid190_uid190_rrx_uid34_fpTanTest_q <= VCC_q & fracX_uid180_rrx_uid34_fpTanTest_b;
--prod_uid191_rrx_uid34_fpTanTest_b_0(BITSELECT,630)@4
prod_uid191_rrx_uid34_fpTanTest_b_0_in <= STD_LOGIC_VECTOR("000" & oFracX_uid190_uid190_rrx_uid34_fpTanTest_q);
prod_uid191_rrx_uid34_fpTanTest_b_0_b <= prod_uid191_rrx_uid34_fpTanTest_b_0_in(26 downto 0);
--reg_prod_uid191_rrx_uid34_fpTanTest_b_0_0_to_prod_uid191_rrx_uid34_fpTanTest_a0_b0_1(REG,654)@4
reg_prod_uid191_rrx_uid34_fpTanTest_b_0_0_to_prod_uid191_rrx_uid34_fpTanTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid191_rrx_uid34_fpTanTest_b_0_0_to_prod_uid191_rrx_uid34_fpTanTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid191_rrx_uid34_fpTanTest_b_0_0_to_prod_uid191_rrx_uid34_fpTanTest_a0_b0_1_q <= prod_uid191_rrx_uid34_fpTanTest_b_0_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShift_uid24_fpTanTest(CONSTANT,23)
cstBiasMwShift_uid24_fpTanTest_q <= "01110011";
--expXTableAddrExt_uid185_rrx_uid34_fpTanTest(SUB,184)@0
expXTableAddrExt_uid185_rrx_uid34_fpTanTest_a <= STD_LOGIC_VECTOR("0" & expX_uid179_rrx_uid34_fpTanTest_b);
expXTableAddrExt_uid185_rrx_uid34_fpTanTest_b <= STD_LOGIC_VECTOR("0" & cstBiasMwShift_uid24_fpTanTest_q);
expXTableAddrExt_uid185_rrx_uid34_fpTanTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXTableAddrExt_uid185_rrx_uid34_fpTanTest_a) - UNSIGNED(expXTableAddrExt_uid185_rrx_uid34_fpTanTest_b));
expXTableAddrExt_uid185_rrx_uid34_fpTanTest_q <= expXTableAddrExt_uid185_rrx_uid34_fpTanTest_o(8 downto 0);
--expXTableAddr_uid186_rrx_uid34_fpTanTest(BITSELECT,185)@0
expXTableAddr_uid186_rrx_uid34_fpTanTest_in <= expXTableAddrExt_uid185_rrx_uid34_fpTanTest_q(7 downto 0);
expXTableAddr_uid186_rrx_uid34_fpTanTest_b <= expXTableAddr_uid186_rrx_uid34_fpTanTest_in(7 downto 0);
--reg_expXTableAddr_uid186_rrx_uid34_fpTanTest_0_to_rrTable_uid187_rrx_uid34_fpTanTest_lutmem_0(REG,649)@0
reg_expXTableAddr_uid186_rrx_uid34_fpTanTest_0_to_rrTable_uid187_rrx_uid34_fpTanTest_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXTableAddr_uid186_rrx_uid34_fpTanTest_0_to_rrTable_uid187_rrx_uid34_fpTanTest_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXTableAddr_uid186_rrx_uid34_fpTanTest_0_to_rrTable_uid187_rrx_uid34_fpTanTest_lutmem_0_q <= expXTableAddr_uid186_rrx_uid34_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--rrTable_uid188_rrx_uid34_fpTanTest_lutmem(DUALMEM,626)@1
rrTable_uid188_rrx_uid34_fpTanTest_lutmem_ia <= (others => '0');
rrTable_uid188_rrx_uid34_fpTanTest_lutmem_aa <= (others => '0');
rrTable_uid188_rrx_uid34_fpTanTest_lutmem_ab <= reg_expXTableAddr_uid186_rrx_uid34_fpTanTest_0_to_rrTable_uid187_rrx_uid34_fpTanTest_lutmem_0_q;
rrTable_uid188_rrx_uid34_fpTanTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 38,
widthad_a => 8,
numwords_a => 140,
width_b => 38,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_tan_s5_rrTable_uid188_rrx_uid34_fpTanTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid188_rrx_uid34_fpTanTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid188_rrx_uid34_fpTanTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid188_rrx_uid34_fpTanTest_lutmem_iq,
address_a => rrTable_uid188_rrx_uid34_fpTanTest_lutmem_aa,
data_a => rrTable_uid188_rrx_uid34_fpTanTest_lutmem_ia
);
rrTable_uid188_rrx_uid34_fpTanTest_lutmem_reset0 <= areset;
rrTable_uid188_rrx_uid34_fpTanTest_lutmem_q <= rrTable_uid188_rrx_uid34_fpTanTest_lutmem_iq(37 downto 0);
--reg_rrTable_uid188_rrx_uid34_fpTanTest_lutmem_0_to_os_uid189_rrx_uid34_fpTanTest_1(REG,652)@3
reg_rrTable_uid188_rrx_uid34_fpTanTest_lutmem_0_to_os_uid189_rrx_uid34_fpTanTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid188_rrx_uid34_fpTanTest_lutmem_0_to_os_uid189_rrx_uid34_fpTanTest_1_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid188_rrx_uid34_fpTanTest_lutmem_0_to_os_uid189_rrx_uid34_fpTanTest_1_q <= rrTable_uid188_rrx_uid34_fpTanTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--rrTable_uid187_rrx_uid34_fpTanTest_lutmem(DUALMEM,625)@1
rrTable_uid187_rrx_uid34_fpTanTest_lutmem_ia <= (others => '0');
rrTable_uid187_rrx_uid34_fpTanTest_lutmem_aa <= (others => '0');
rrTable_uid187_rrx_uid34_fpTanTest_lutmem_ab <= reg_expXTableAddr_uid186_rrx_uid34_fpTanTest_0_to_rrTable_uid187_rrx_uid34_fpTanTest_lutmem_0_q;
rrTable_uid187_rrx_uid34_fpTanTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_tan_s5_rrTable_uid187_rrx_uid34_fpTanTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid187_rrx_uid34_fpTanTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid187_rrx_uid34_fpTanTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid187_rrx_uid34_fpTanTest_lutmem_iq,
address_a => rrTable_uid187_rrx_uid34_fpTanTest_lutmem_aa,
data_a => rrTable_uid187_rrx_uid34_fpTanTest_lutmem_ia
);
rrTable_uid187_rrx_uid34_fpTanTest_lutmem_reset0 <= areset;
rrTable_uid187_rrx_uid34_fpTanTest_lutmem_q <= rrTable_uid187_rrx_uid34_fpTanTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid187_rrx_uid34_fpTanTest_lutmem_0_to_os_uid189_rrx_uid34_fpTanTest_0(REG,651)@3
reg_rrTable_uid187_rrx_uid34_fpTanTest_lutmem_0_to_os_uid189_rrx_uid34_fpTanTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid187_rrx_uid34_fpTanTest_lutmem_0_to_os_uid189_rrx_uid34_fpTanTest_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid187_rrx_uid34_fpTanTest_lutmem_0_to_os_uid189_rrx_uid34_fpTanTest_0_q <= rrTable_uid187_rrx_uid34_fpTanTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid189_rrx_uid34_fpTanTest(BITJOIN,188)@4
os_uid189_rrx_uid34_fpTanTest_q <= reg_rrTable_uid188_rrx_uid34_fpTanTest_lutmem_0_to_os_uid189_rrx_uid34_fpTanTest_1_q & reg_rrTable_uid187_rrx_uid34_fpTanTest_lutmem_0_to_os_uid189_rrx_uid34_fpTanTest_0_q;
--prod_uid191_rrx_uid34_fpTanTest_a_2(BITSELECT,629)@4
prod_uid191_rrx_uid34_fpTanTest_a_2_in <= STD_LOGIC_VECTOR("000" & os_uid189_rrx_uid34_fpTanTest_q);
prod_uid191_rrx_uid34_fpTanTest_a_2_b <= prod_uid191_rrx_uid34_fpTanTest_a_2_in(80 downto 54);
--reg_prod_uid191_rrx_uid34_fpTanTest_a_2_0_to_prod_uid191_rrx_uid34_fpTanTest_a2_b0_0(REG,657)@4
reg_prod_uid191_rrx_uid34_fpTanTest_a_2_0_to_prod_uid191_rrx_uid34_fpTanTest_a2_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid191_rrx_uid34_fpTanTest_a_2_0_to_prod_uid191_rrx_uid34_fpTanTest_a2_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid191_rrx_uid34_fpTanTest_a_2_0_to_prod_uid191_rrx_uid34_fpTanTest_a2_b0_0_q <= prod_uid191_rrx_uid34_fpTanTest_a_2_b;
END IF;
END IF;
END PROCESS;
--prod_uid191_rrx_uid34_fpTanTest_a2_b0(MULT,633)@5
prod_uid191_rrx_uid34_fpTanTest_a2_b0_pr <= UNSIGNED(prod_uid191_rrx_uid34_fpTanTest_a2_b0_a) * UNSIGNED(prod_uid191_rrx_uid34_fpTanTest_a2_b0_b);
prod_uid191_rrx_uid34_fpTanTest_a2_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid191_rrx_uid34_fpTanTest_a2_b0_a <= (others => '0');
prod_uid191_rrx_uid34_fpTanTest_a2_b0_b <= (others => '0');
prod_uid191_rrx_uid34_fpTanTest_a2_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid191_rrx_uid34_fpTanTest_a2_b0_a <= reg_prod_uid191_rrx_uid34_fpTanTest_a_2_0_to_prod_uid191_rrx_uid34_fpTanTest_a2_b0_0_q;
prod_uid191_rrx_uid34_fpTanTest_a2_b0_b <= reg_prod_uid191_rrx_uid34_fpTanTest_b_0_0_to_prod_uid191_rrx_uid34_fpTanTest_a0_b0_1_q;
prod_uid191_rrx_uid34_fpTanTest_a2_b0_s1 <= STD_LOGIC_VECTOR(prod_uid191_rrx_uid34_fpTanTest_a2_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid191_rrx_uid34_fpTanTest_a2_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid191_rrx_uid34_fpTanTest_a2_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid191_rrx_uid34_fpTanTest_a2_b0_q <= prod_uid191_rrx_uid34_fpTanTest_a2_b0_s1;
END IF;
END IF;
END PROCESS;
--ld_prod_uid191_rrx_uid34_fpTanTest_a2_b0_q_to_prod_uid191_rrx_uid34_fpTanTest_align_2_a(DELAY,1388)@8
ld_prod_uid191_rrx_uid34_fpTanTest_a2_b0_q_to_prod_uid191_rrx_uid34_fpTanTest_align_2_a : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => prod_uid191_rrx_uid34_fpTanTest_a2_b0_q, xout => ld_prod_uid191_rrx_uid34_fpTanTest_a2_b0_q_to_prod_uid191_rrx_uid34_fpTanTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--prod_uid191_rrx_uid34_fpTanTest_align_2(BITSHIFT,636)@9
prod_uid191_rrx_uid34_fpTanTest_align_2_q_int <= ld_prod_uid191_rrx_uid34_fpTanTest_a2_b0_q_to_prod_uid191_rrx_uid34_fpTanTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
prod_uid191_rrx_uid34_fpTanTest_align_2_q <= prod_uid191_rrx_uid34_fpTanTest_align_2_q_int(107 downto 0);
--prod_uid191_rrx_uid34_fpTanTest_a_1(BITSELECT,628)@4
prod_uid191_rrx_uid34_fpTanTest_a_1_in <= os_uid189_rrx_uid34_fpTanTest_q(53 downto 0);
prod_uid191_rrx_uid34_fpTanTest_a_1_b <= prod_uid191_rrx_uid34_fpTanTest_a_1_in(53 downto 27);
--reg_prod_uid191_rrx_uid34_fpTanTest_a_1_0_to_prod_uid191_rrx_uid34_fpTanTest_a1_b0_0(REG,655)@4
reg_prod_uid191_rrx_uid34_fpTanTest_a_1_0_to_prod_uid191_rrx_uid34_fpTanTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid191_rrx_uid34_fpTanTest_a_1_0_to_prod_uid191_rrx_uid34_fpTanTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid191_rrx_uid34_fpTanTest_a_1_0_to_prod_uid191_rrx_uid34_fpTanTest_a1_b0_0_q <= prod_uid191_rrx_uid34_fpTanTest_a_1_b;
END IF;
END IF;
END PROCESS;
--prod_uid191_rrx_uid34_fpTanTest_a1_b0(MULT,632)@5
prod_uid191_rrx_uid34_fpTanTest_a1_b0_pr <= UNSIGNED(prod_uid191_rrx_uid34_fpTanTest_a1_b0_a) * UNSIGNED(prod_uid191_rrx_uid34_fpTanTest_a1_b0_b);
prod_uid191_rrx_uid34_fpTanTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid191_rrx_uid34_fpTanTest_a1_b0_a <= (others => '0');
prod_uid191_rrx_uid34_fpTanTest_a1_b0_b <= (others => '0');
prod_uid191_rrx_uid34_fpTanTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid191_rrx_uid34_fpTanTest_a1_b0_a <= reg_prod_uid191_rrx_uid34_fpTanTest_a_1_0_to_prod_uid191_rrx_uid34_fpTanTest_a1_b0_0_q;
prod_uid191_rrx_uid34_fpTanTest_a1_b0_b <= reg_prod_uid191_rrx_uid34_fpTanTest_b_0_0_to_prod_uid191_rrx_uid34_fpTanTest_a0_b0_1_q;
prod_uid191_rrx_uid34_fpTanTest_a1_b0_s1 <= STD_LOGIC_VECTOR(prod_uid191_rrx_uid34_fpTanTest_a1_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid191_rrx_uid34_fpTanTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid191_rrx_uid34_fpTanTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid191_rrx_uid34_fpTanTest_a1_b0_q <= prod_uid191_rrx_uid34_fpTanTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid191_rrx_uid34_fpTanTest_align_1(BITSHIFT,635)@8
prod_uid191_rrx_uid34_fpTanTest_align_1_q_int <= prod_uid191_rrx_uid34_fpTanTest_a1_b0_q & "000000000000000000000000000";
prod_uid191_rrx_uid34_fpTanTest_align_1_q <= prod_uid191_rrx_uid34_fpTanTest_align_1_q_int(80 downto 0);
--prod_uid191_rrx_uid34_fpTanTest_a_0(BITSELECT,627)@4
prod_uid191_rrx_uid34_fpTanTest_a_0_in <= os_uid189_rrx_uid34_fpTanTest_q(26 downto 0);
prod_uid191_rrx_uid34_fpTanTest_a_0_b <= prod_uid191_rrx_uid34_fpTanTest_a_0_in(26 downto 0);
--reg_prod_uid191_rrx_uid34_fpTanTest_a_0_0_to_prod_uid191_rrx_uid34_fpTanTest_a0_b0_0(REG,653)@4
reg_prod_uid191_rrx_uid34_fpTanTest_a_0_0_to_prod_uid191_rrx_uid34_fpTanTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid191_rrx_uid34_fpTanTest_a_0_0_to_prod_uid191_rrx_uid34_fpTanTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid191_rrx_uid34_fpTanTest_a_0_0_to_prod_uid191_rrx_uid34_fpTanTest_a0_b0_0_q <= prod_uid191_rrx_uid34_fpTanTest_a_0_b;
END IF;
END IF;
END PROCESS;
--prod_uid191_rrx_uid34_fpTanTest_a0_b0(MULT,631)@5
prod_uid191_rrx_uid34_fpTanTest_a0_b0_pr <= UNSIGNED(prod_uid191_rrx_uid34_fpTanTest_a0_b0_a) * UNSIGNED(prod_uid191_rrx_uid34_fpTanTest_a0_b0_b);
prod_uid191_rrx_uid34_fpTanTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid191_rrx_uid34_fpTanTest_a0_b0_a <= (others => '0');
prod_uid191_rrx_uid34_fpTanTest_a0_b0_b <= (others => '0');
prod_uid191_rrx_uid34_fpTanTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid191_rrx_uid34_fpTanTest_a0_b0_a <= reg_prod_uid191_rrx_uid34_fpTanTest_a_0_0_to_prod_uid191_rrx_uid34_fpTanTest_a0_b0_0_q;
prod_uid191_rrx_uid34_fpTanTest_a0_b0_b <= reg_prod_uid191_rrx_uid34_fpTanTest_b_0_0_to_prod_uid191_rrx_uid34_fpTanTest_a0_b0_1_q;
prod_uid191_rrx_uid34_fpTanTest_a0_b0_s1 <= STD_LOGIC_VECTOR(prod_uid191_rrx_uid34_fpTanTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid191_rrx_uid34_fpTanTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid191_rrx_uid34_fpTanTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid191_rrx_uid34_fpTanTest_a0_b0_q <= prod_uid191_rrx_uid34_fpTanTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid191_rrx_uid34_fpTanTest_align_0(BITSHIFT,634)@8
prod_uid191_rrx_uid34_fpTanTest_align_0_q_int <= prod_uid191_rrx_uid34_fpTanTest_a0_b0_q;
prod_uid191_rrx_uid34_fpTanTest_align_0_q <= prod_uid191_rrx_uid34_fpTanTest_align_0_q_int(53 downto 0);
--prod_uid191_rrx_uid34_fpTanTest_result_add_0_0(ADD,637)@8
prod_uid191_rrx_uid34_fpTanTest_result_add_0_0_a <= STD_LOGIC_VECTOR("0000000000000000000000000000" & prod_uid191_rrx_uid34_fpTanTest_align_0_q);
prod_uid191_rrx_uid34_fpTanTest_result_add_0_0_b <= STD_LOGIC_VECTOR("0" & prod_uid191_rrx_uid34_fpTanTest_align_1_q);
prod_uid191_rrx_uid34_fpTanTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid191_rrx_uid34_fpTanTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prod_uid191_rrx_uid34_fpTanTest_result_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid191_rrx_uid34_fpTanTest_result_add_0_0_a) + UNSIGNED(prod_uid191_rrx_uid34_fpTanTest_result_add_0_0_b));
END IF;
END PROCESS;
prod_uid191_rrx_uid34_fpTanTest_result_add_0_0_q <= prod_uid191_rrx_uid34_fpTanTest_result_add_0_0_o(81 downto 0);
--prod_uid191_rrx_uid34_fpTanTest_result_add_1_0(ADD,638)@9
prod_uid191_rrx_uid34_fpTanTest_result_add_1_0_a <= STD_LOGIC_VECTOR("000000000000000000000000000" & prod_uid191_rrx_uid34_fpTanTest_result_add_0_0_q);
prod_uid191_rrx_uid34_fpTanTest_result_add_1_0_b <= STD_LOGIC_VECTOR("0" & prod_uid191_rrx_uid34_fpTanTest_align_2_q);
prod_uid191_rrx_uid34_fpTanTest_result_add_1_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid191_rrx_uid34_fpTanTest_result_add_1_0_a) + UNSIGNED(prod_uid191_rrx_uid34_fpTanTest_result_add_1_0_b));
prod_uid191_rrx_uid34_fpTanTest_result_add_1_0_q <= prod_uid191_rrx_uid34_fpTanTest_result_add_1_0_o(108 downto 0);
--multFracBits_uid192_rrx_uid34_fpTanTest(BITSELECT,191)@9
multFracBits_uid192_rrx_uid34_fpTanTest_in <= prod_uid191_rrx_uid34_fpTanTest_result_add_1_0_q(75 downto 0);
multFracBits_uid192_rrx_uid34_fpTanTest_b <= multFracBits_uid192_rrx_uid34_fpTanTest_in(75 downto 0);
--multFracBitsTop_uid193_rrx_uid34_fpTanTest(BITSELECT,192)@9
multFracBitsTop_uid193_rrx_uid34_fpTanTest_in <= multFracBits_uid192_rrx_uid34_fpTanTest_b;
multFracBitsTop_uid193_rrx_uid34_fpTanTest_b <= multFracBitsTop_uid193_rrx_uid34_fpTanTest_in(75 downto 46);
--rVStage_uid527_zCount_uid194_rrx_uid34_fpTanTest(BITSELECT,526)@9
rVStage_uid527_zCount_uid194_rrx_uid34_fpTanTest_in <= multFracBitsTop_uid193_rrx_uid34_fpTanTest_b;
rVStage_uid527_zCount_uid194_rrx_uid34_fpTanTest_b <= rVStage_uid527_zCount_uid194_rrx_uid34_fpTanTest_in(29 downto 14);
--reg_rVStage_uid527_zCount_uid194_rrx_uid34_fpTanTest_0_to_vCount_uid528_zCount_uid194_rrx_uid34_fpTanTest_1(REG,659)@9
reg_rVStage_uid527_zCount_uid194_rrx_uid34_fpTanTest_0_to_vCount_uid528_zCount_uid194_rrx_uid34_fpTanTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid527_zCount_uid194_rrx_uid34_fpTanTest_0_to_vCount_uid528_zCount_uid194_rrx_uid34_fpTanTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid527_zCount_uid194_rrx_uid34_fpTanTest_0_to_vCount_uid528_zCount_uid194_rrx_uid34_fpTanTest_1_q <= rVStage_uid527_zCount_uid194_rrx_uid34_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid528_zCount_uid194_rrx_uid34_fpTanTest(LOGICAL,527)@10
vCount_uid528_zCount_uid194_rrx_uid34_fpTanTest_a <= reg_rVStage_uid527_zCount_uid194_rrx_uid34_fpTanTest_0_to_vCount_uid528_zCount_uid194_rrx_uid34_fpTanTest_1_q;
vCount_uid528_zCount_uid194_rrx_uid34_fpTanTest_b <= zs_uid243_lzcZSin_uid65_fpTanTest_q;
vCount_uid528_zCount_uid194_rrx_uid34_fpTanTest_q <= "1" when vCount_uid528_zCount_uid194_rrx_uid34_fpTanTest_a = vCount_uid528_zCount_uid194_rrx_uid34_fpTanTest_b else "0";
--reg_vCount_uid528_zCount_uid194_rrx_uid34_fpTanTest_0_to_r_uid555_zCount_uid194_rrx_uid34_fpTanTest_4(REG,667)@10
reg_vCount_uid528_zCount_uid194_rrx_uid34_fpTanTest_0_to_r_uid555_zCount_uid194_rrx_uid34_fpTanTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid528_zCount_uid194_rrx_uid34_fpTanTest_0_to_r_uid555_zCount_uid194_rrx_uid34_fpTanTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid528_zCount_uid194_rrx_uid34_fpTanTest_0_to_r_uid555_zCount_uid194_rrx_uid34_fpTanTest_4_q <= vCount_uid528_zCount_uid194_rrx_uid34_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid528_zCount_uid194_rrx_uid34_fpTanTest_0_to_r_uid555_zCount_uid194_rrx_uid34_fpTanTest_4_q_to_r_uid555_zCount_uid194_rrx_uid34_fpTanTest_e(DELAY,1309)@11
ld_reg_vCount_uid528_zCount_uid194_rrx_uid34_fpTanTest_0_to_r_uid555_zCount_uid194_rrx_uid34_fpTanTest_4_q_to_r_uid555_zCount_uid194_rrx_uid34_fpTanTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid528_zCount_uid194_rrx_uid34_fpTanTest_0_to_r_uid555_zCount_uid194_rrx_uid34_fpTanTest_4_q, xout => ld_reg_vCount_uid528_zCount_uid194_rrx_uid34_fpTanTest_0_to_r_uid555_zCount_uid194_rrx_uid34_fpTanTest_4_q_to_r_uid555_zCount_uid194_rrx_uid34_fpTanTest_e_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWE_uid8_fpTanTest(CONSTANT,7)
cstAllZWE_uid8_fpTanTest_q <= "00000000";
--vStage_uid530_zCount_uid194_rrx_uid34_fpTanTest(BITSELECT,529)@9
vStage_uid530_zCount_uid194_rrx_uid34_fpTanTest_in <= multFracBitsTop_uid193_rrx_uid34_fpTanTest_b(13 downto 0);
vStage_uid530_zCount_uid194_rrx_uid34_fpTanTest_b <= vStage_uid530_zCount_uid194_rrx_uid34_fpTanTest_in(13 downto 0);
--mO_uid529_zCount_uid194_rrx_uid34_fpTanTest(CONSTANT,528)
mO_uid529_zCount_uid194_rrx_uid34_fpTanTest_q <= "11";
--cStage_uid531_zCount_uid194_rrx_uid34_fpTanTest(BITJOIN,530)@9
cStage_uid531_zCount_uid194_rrx_uid34_fpTanTest_q <= vStage_uid530_zCount_uid194_rrx_uid34_fpTanTest_b & mO_uid529_zCount_uid194_rrx_uid34_fpTanTest_q;
--reg_cStage_uid531_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid533_zCount_uid194_rrx_uid34_fpTanTest_3(REG,661)@9
reg_cStage_uid531_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid533_zCount_uid194_rrx_uid34_fpTanTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid531_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid533_zCount_uid194_rrx_uid34_fpTanTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid531_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid533_zCount_uid194_rrx_uid34_fpTanTest_3_q <= cStage_uid531_zCount_uid194_rrx_uid34_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid533_zCount_uid194_rrx_uid34_fpTanTest(MUX,532)@10
vStagei_uid533_zCount_uid194_rrx_uid34_fpTanTest_s <= vCount_uid528_zCount_uid194_rrx_uid34_fpTanTest_q;
vStagei_uid533_zCount_uid194_rrx_uid34_fpTanTest: PROCESS (vStagei_uid533_zCount_uid194_rrx_uid34_fpTanTest_s, en, reg_rVStage_uid527_zCount_uid194_rrx_uid34_fpTanTest_0_to_vCount_uid528_zCount_uid194_rrx_uid34_fpTanTest_1_q, reg_cStage_uid531_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid533_zCount_uid194_rrx_uid34_fpTanTest_3_q)
BEGIN
CASE vStagei_uid533_zCount_uid194_rrx_uid34_fpTanTest_s IS
WHEN "0" => vStagei_uid533_zCount_uid194_rrx_uid34_fpTanTest_q <= reg_rVStage_uid527_zCount_uid194_rrx_uid34_fpTanTest_0_to_vCount_uid528_zCount_uid194_rrx_uid34_fpTanTest_1_q;
WHEN "1" => vStagei_uid533_zCount_uid194_rrx_uid34_fpTanTest_q <= reg_cStage_uid531_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid533_zCount_uid194_rrx_uid34_fpTanTest_3_q;
WHEN OTHERS => vStagei_uid533_zCount_uid194_rrx_uid34_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid535_zCount_uid194_rrx_uid34_fpTanTest(BITSELECT,534)@10
rVStage_uid535_zCount_uid194_rrx_uid34_fpTanTest_in <= vStagei_uid533_zCount_uid194_rrx_uid34_fpTanTest_q;
rVStage_uid535_zCount_uid194_rrx_uid34_fpTanTest_b <= rVStage_uid535_zCount_uid194_rrx_uid34_fpTanTest_in(15 downto 8);
--vCount_uid536_zCount_uid194_rrx_uid34_fpTanTest(LOGICAL,535)@10
vCount_uid536_zCount_uid194_rrx_uid34_fpTanTest_a <= rVStage_uid535_zCount_uid194_rrx_uid34_fpTanTest_b;
vCount_uid536_zCount_uid194_rrx_uid34_fpTanTest_b <= cstAllZWE_uid8_fpTanTest_q;
vCount_uid536_zCount_uid194_rrx_uid34_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid536_zCount_uid194_rrx_uid34_fpTanTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid536_zCount_uid194_rrx_uid34_fpTanTest_a = vCount_uid536_zCount_uid194_rrx_uid34_fpTanTest_b) THEN
vCount_uid536_zCount_uid194_rrx_uid34_fpTanTest_q <= "1";
ELSE
vCount_uid536_zCount_uid194_rrx_uid34_fpTanTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid536_zCount_uid194_rrx_uid34_fpTanTest_q_to_r_uid555_zCount_uid194_rrx_uid34_fpTanTest_d(DELAY,1308)@11
ld_vCount_uid536_zCount_uid194_rrx_uid34_fpTanTest_q_to_r_uid555_zCount_uid194_rrx_uid34_fpTanTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid536_zCount_uid194_rrx_uid34_fpTanTest_q, xout => ld_vCount_uid536_zCount_uid194_rrx_uid34_fpTanTest_q_to_r_uid555_zCount_uid194_rrx_uid34_fpTanTest_d_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1Pad4_uid206_fxpX_uid48_fpTanTest(CONSTANT,205)
leftShiftStage0Idx1Pad4_uid206_fxpX_uid48_fpTanTest_q <= "0000";
--vStage_uid537_zCount_uid194_rrx_uid34_fpTanTest(BITSELECT,536)@10
vStage_uid537_zCount_uid194_rrx_uid34_fpTanTest_in <= vStagei_uid533_zCount_uid194_rrx_uid34_fpTanTest_q(7 downto 0);
vStage_uid537_zCount_uid194_rrx_uid34_fpTanTest_b <= vStage_uid537_zCount_uid194_rrx_uid34_fpTanTest_in(7 downto 0);
--reg_vStage_uid537_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid539_zCount_uid194_rrx_uid34_fpTanTest_3(REG,663)@10
reg_vStage_uid537_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid539_zCount_uid194_rrx_uid34_fpTanTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid537_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid539_zCount_uid194_rrx_uid34_fpTanTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid537_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid539_zCount_uid194_rrx_uid34_fpTanTest_3_q <= vStage_uid537_zCount_uid194_rrx_uid34_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid535_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid539_zCount_uid194_rrx_uid34_fpTanTest_2(REG,662)@10
reg_rVStage_uid535_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid539_zCount_uid194_rrx_uid34_fpTanTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid535_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid539_zCount_uid194_rrx_uid34_fpTanTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid535_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid539_zCount_uid194_rrx_uid34_fpTanTest_2_q <= rVStage_uid535_zCount_uid194_rrx_uid34_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid539_zCount_uid194_rrx_uid34_fpTanTest(MUX,538)@11
vStagei_uid539_zCount_uid194_rrx_uid34_fpTanTest_s <= vCount_uid536_zCount_uid194_rrx_uid34_fpTanTest_q;
vStagei_uid539_zCount_uid194_rrx_uid34_fpTanTest: PROCESS (vStagei_uid539_zCount_uid194_rrx_uid34_fpTanTest_s, en, reg_rVStage_uid535_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid539_zCount_uid194_rrx_uid34_fpTanTest_2_q, reg_vStage_uid537_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid539_zCount_uid194_rrx_uid34_fpTanTest_3_q)
BEGIN
CASE vStagei_uid539_zCount_uid194_rrx_uid34_fpTanTest_s IS
WHEN "0" => vStagei_uid539_zCount_uid194_rrx_uid34_fpTanTest_q <= reg_rVStage_uid535_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid539_zCount_uid194_rrx_uid34_fpTanTest_2_q;
WHEN "1" => vStagei_uid539_zCount_uid194_rrx_uid34_fpTanTest_q <= reg_vStage_uid537_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid539_zCount_uid194_rrx_uid34_fpTanTest_3_q;
WHEN OTHERS => vStagei_uid539_zCount_uid194_rrx_uid34_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid541_zCount_uid194_rrx_uid34_fpTanTest(BITSELECT,540)@11
rVStage_uid541_zCount_uid194_rrx_uid34_fpTanTest_in <= vStagei_uid539_zCount_uid194_rrx_uid34_fpTanTest_q;
rVStage_uid541_zCount_uid194_rrx_uid34_fpTanTest_b <= rVStage_uid541_zCount_uid194_rrx_uid34_fpTanTest_in(7 downto 4);
--vCount_uid542_zCount_uid194_rrx_uid34_fpTanTest(LOGICAL,541)@11
vCount_uid542_zCount_uid194_rrx_uid34_fpTanTest_a <= rVStage_uid541_zCount_uid194_rrx_uid34_fpTanTest_b;
vCount_uid542_zCount_uid194_rrx_uid34_fpTanTest_b <= leftShiftStage0Idx1Pad4_uid206_fxpX_uid48_fpTanTest_q;
vCount_uid542_zCount_uid194_rrx_uid34_fpTanTest_q <= "1" when vCount_uid542_zCount_uid194_rrx_uid34_fpTanTest_a = vCount_uid542_zCount_uid194_rrx_uid34_fpTanTest_b else "0";
--reg_vCount_uid542_zCount_uid194_rrx_uid34_fpTanTest_0_to_r_uid555_zCount_uid194_rrx_uid34_fpTanTest_2(REG,666)@11
reg_vCount_uid542_zCount_uid194_rrx_uid34_fpTanTest_0_to_r_uid555_zCount_uid194_rrx_uid34_fpTanTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid542_zCount_uid194_rrx_uid34_fpTanTest_0_to_r_uid555_zCount_uid194_rrx_uid34_fpTanTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid542_zCount_uid194_rrx_uid34_fpTanTest_0_to_r_uid555_zCount_uid194_rrx_uid34_fpTanTest_2_q <= vCount_uid542_zCount_uid194_rrx_uid34_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1Idx2Pad2_uid220_fxpX_uid48_fpTanTest(CONSTANT,219)
leftShiftStage1Idx2Pad2_uid220_fxpX_uid48_fpTanTest_q <= "00";
--vStage_uid543_zCount_uid194_rrx_uid34_fpTanTest(BITSELECT,542)@11
vStage_uid543_zCount_uid194_rrx_uid34_fpTanTest_in <= vStagei_uid539_zCount_uid194_rrx_uid34_fpTanTest_q(3 downto 0);
vStage_uid543_zCount_uid194_rrx_uid34_fpTanTest_b <= vStage_uid543_zCount_uid194_rrx_uid34_fpTanTest_in(3 downto 0);
--vStagei_uid545_zCount_uid194_rrx_uid34_fpTanTest(MUX,544)@11
vStagei_uid545_zCount_uid194_rrx_uid34_fpTanTest_s <= vCount_uid542_zCount_uid194_rrx_uid34_fpTanTest_q;
vStagei_uid545_zCount_uid194_rrx_uid34_fpTanTest: PROCESS (vStagei_uid545_zCount_uid194_rrx_uid34_fpTanTest_s, en, rVStage_uid541_zCount_uid194_rrx_uid34_fpTanTest_b, vStage_uid543_zCount_uid194_rrx_uid34_fpTanTest_b)
BEGIN
CASE vStagei_uid545_zCount_uid194_rrx_uid34_fpTanTest_s IS
WHEN "0" => vStagei_uid545_zCount_uid194_rrx_uid34_fpTanTest_q <= rVStage_uid541_zCount_uid194_rrx_uid34_fpTanTest_b;
WHEN "1" => vStagei_uid545_zCount_uid194_rrx_uid34_fpTanTest_q <= vStage_uid543_zCount_uid194_rrx_uid34_fpTanTest_b;
WHEN OTHERS => vStagei_uid545_zCount_uid194_rrx_uid34_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid547_zCount_uid194_rrx_uid34_fpTanTest(BITSELECT,546)@11
rVStage_uid547_zCount_uid194_rrx_uid34_fpTanTest_in <= vStagei_uid545_zCount_uid194_rrx_uid34_fpTanTest_q;
rVStage_uid547_zCount_uid194_rrx_uid34_fpTanTest_b <= rVStage_uid547_zCount_uid194_rrx_uid34_fpTanTest_in(3 downto 2);
--vCount_uid548_zCount_uid194_rrx_uid34_fpTanTest(LOGICAL,547)@11
vCount_uid548_zCount_uid194_rrx_uid34_fpTanTest_a <= rVStage_uid547_zCount_uid194_rrx_uid34_fpTanTest_b;
vCount_uid548_zCount_uid194_rrx_uid34_fpTanTest_b <= leftShiftStage1Idx2Pad2_uid220_fxpX_uid48_fpTanTest_q;
vCount_uid548_zCount_uid194_rrx_uid34_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid548_zCount_uid194_rrx_uid34_fpTanTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid548_zCount_uid194_rrx_uid34_fpTanTest_a = vCount_uid548_zCount_uid194_rrx_uid34_fpTanTest_b) THEN
vCount_uid548_zCount_uid194_rrx_uid34_fpTanTest_q <= "1";
ELSE
vCount_uid548_zCount_uid194_rrx_uid34_fpTanTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid549_zCount_uid194_rrx_uid34_fpTanTest(BITSELECT,548)@11
vStage_uid549_zCount_uid194_rrx_uid34_fpTanTest_in <= vStagei_uid545_zCount_uid194_rrx_uid34_fpTanTest_q(1 downto 0);
vStage_uid549_zCount_uid194_rrx_uid34_fpTanTest_b <= vStage_uid549_zCount_uid194_rrx_uid34_fpTanTest_in(1 downto 0);
--reg_vStage_uid549_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid551_zCount_uid194_rrx_uid34_fpTanTest_3(REG,665)@11
reg_vStage_uid549_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid551_zCount_uid194_rrx_uid34_fpTanTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid549_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid551_zCount_uid194_rrx_uid34_fpTanTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid549_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid551_zCount_uid194_rrx_uid34_fpTanTest_3_q <= vStage_uid549_zCount_uid194_rrx_uid34_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid547_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid551_zCount_uid194_rrx_uid34_fpTanTest_2(REG,664)@11
reg_rVStage_uid547_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid551_zCount_uid194_rrx_uid34_fpTanTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid547_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid551_zCount_uid194_rrx_uid34_fpTanTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid547_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid551_zCount_uid194_rrx_uid34_fpTanTest_2_q <= rVStage_uid547_zCount_uid194_rrx_uid34_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid551_zCount_uid194_rrx_uid34_fpTanTest(MUX,550)@12
vStagei_uid551_zCount_uid194_rrx_uid34_fpTanTest_s <= vCount_uid548_zCount_uid194_rrx_uid34_fpTanTest_q;
vStagei_uid551_zCount_uid194_rrx_uid34_fpTanTest: PROCESS (vStagei_uid551_zCount_uid194_rrx_uid34_fpTanTest_s, en, reg_rVStage_uid547_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid551_zCount_uid194_rrx_uid34_fpTanTest_2_q, reg_vStage_uid549_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid551_zCount_uid194_rrx_uid34_fpTanTest_3_q)
BEGIN
CASE vStagei_uid551_zCount_uid194_rrx_uid34_fpTanTest_s IS
WHEN "0" => vStagei_uid551_zCount_uid194_rrx_uid34_fpTanTest_q <= reg_rVStage_uid547_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid551_zCount_uid194_rrx_uid34_fpTanTest_2_q;
WHEN "1" => vStagei_uid551_zCount_uid194_rrx_uid34_fpTanTest_q <= reg_vStage_uid549_zCount_uid194_rrx_uid34_fpTanTest_0_to_vStagei_uid551_zCount_uid194_rrx_uid34_fpTanTest_3_q;
WHEN OTHERS => vStagei_uid551_zCount_uid194_rrx_uid34_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid553_zCount_uid194_rrx_uid34_fpTanTest(BITSELECT,552)@12
rVStage_uid553_zCount_uid194_rrx_uid34_fpTanTest_in <= vStagei_uid551_zCount_uid194_rrx_uid34_fpTanTest_q;
rVStage_uid553_zCount_uid194_rrx_uid34_fpTanTest_b <= rVStage_uid553_zCount_uid194_rrx_uid34_fpTanTest_in(1 downto 1);
--vCount_uid554_zCount_uid194_rrx_uid34_fpTanTest(LOGICAL,553)@12
vCount_uid554_zCount_uid194_rrx_uid34_fpTanTest_a <= rVStage_uid553_zCount_uid194_rrx_uid34_fpTanTest_b;
vCount_uid554_zCount_uid194_rrx_uid34_fpTanTest_b <= GND_q;
vCount_uid554_zCount_uid194_rrx_uid34_fpTanTest_q <= "1" when vCount_uid554_zCount_uid194_rrx_uid34_fpTanTest_a = vCount_uid554_zCount_uid194_rrx_uid34_fpTanTest_b else "0";
--r_uid555_zCount_uid194_rrx_uid34_fpTanTest(BITJOIN,554)@12
r_uid555_zCount_uid194_rrx_uid34_fpTanTest_q <= ld_reg_vCount_uid528_zCount_uid194_rrx_uid34_fpTanTest_0_to_r_uid555_zCount_uid194_rrx_uid34_fpTanTest_4_q_to_r_uid555_zCount_uid194_rrx_uid34_fpTanTest_e_q & ld_vCount_uid536_zCount_uid194_rrx_uid34_fpTanTest_q_to_r_uid555_zCount_uid194_rrx_uid34_fpTanTest_d_q & reg_vCount_uid542_zCount_uid194_rrx_uid34_fpTanTest_0_to_r_uid555_zCount_uid194_rrx_uid34_fpTanTest_2_q & vCount_uid548_zCount_uid194_rrx_uid34_fpTanTest_q & vCount_uid554_zCount_uid194_rrx_uid34_fpTanTest_q;
--cstBiasM1_uid23_fpTanTest(CONSTANT,22)
cstBiasM1_uid23_fpTanTest_q <= "01111110";
--expCompOutExt_uid197_rrx_uid34_fpTanTest(SUB,196)@12
expCompOutExt_uid197_rrx_uid34_fpTanTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpTanTest_q);
expCompOutExt_uid197_rrx_uid34_fpTanTest_b <= STD_LOGIC_VECTOR("0000" & r_uid555_zCount_uid194_rrx_uid34_fpTanTest_q);
expCompOutExt_uid197_rrx_uid34_fpTanTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expCompOutExt_uid197_rrx_uid34_fpTanTest_a) - UNSIGNED(expCompOutExt_uid197_rrx_uid34_fpTanTest_b));
expCompOutExt_uid197_rrx_uid34_fpTanTest_q <= expCompOutExt_uid197_rrx_uid34_fpTanTest_o(8 downto 0);
--expCompOut_uid198_rrx_uid34_fpTanTest(BITSELECT,197)@12
expCompOut_uid198_rrx_uid34_fpTanTest_in <= expCompOutExt_uid197_rrx_uid34_fpTanTest_q(7 downto 0);
expCompOut_uid198_rrx_uid34_fpTanTest_b <= expCompOut_uid198_rrx_uid34_fpTanTest_in(7 downto 0);
--reg_expCompOut_uid198_rrx_uid34_fpTanTest_0_to_finalExp_uid202_rrx_uid34_fpTanTest_2(REG,674)@12
reg_expCompOut_uid198_rrx_uid34_fpTanTest_0_to_finalExp_uid202_rrx_uid34_fpTanTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expCompOut_uid198_rrx_uid34_fpTanTest_0_to_finalExp_uid202_rrx_uid34_fpTanTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expCompOut_uid198_rrx_uid34_fpTanTest_0_to_finalExp_uid202_rrx_uid34_fpTanTest_2_q <= expCompOut_uid198_rrx_uid34_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--xBranch_uid184_rrx_uid34_fpTanTest(COMPARE,183)@0
xBranch_uid184_rrx_uid34_fpTanTest_cin <= GND_q;
xBranch_uid184_rrx_uid34_fpTanTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid24_fpTanTest_q) & '0';
xBranch_uid184_rrx_uid34_fpTanTest_b <= STD_LOGIC_VECTOR("00" & expX_uid179_rrx_uid34_fpTanTest_b) & xBranch_uid184_rrx_uid34_fpTanTest_cin(0);
xBranch_uid184_rrx_uid34_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xBranch_uid184_rrx_uid34_fpTanTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
xBranch_uid184_rrx_uid34_fpTanTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xBranch_uid184_rrx_uid34_fpTanTest_a) - UNSIGNED(xBranch_uid184_rrx_uid34_fpTanTest_b));
END IF;
END IF;
END PROCESS;
xBranch_uid184_rrx_uid34_fpTanTest_n(0) <= not xBranch_uid184_rrx_uid34_fpTanTest_o(10);
--ld_xBranch_uid184_rrx_uid34_fpTanTest_n_to_finalExp_uid202_rrx_uid34_fpTanTest_b(DELAY,945)@1
ld_xBranch_uid184_rrx_uid34_fpTanTest_n_to_finalExp_uid202_rrx_uid34_fpTanTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => xBranch_uid184_rrx_uid34_fpTanTest_n, xout => ld_xBranch_uid184_rrx_uid34_fpTanTest_n_to_finalExp_uid202_rrx_uid34_fpTanTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalExp_uid202_rrx_uid34_fpTanTest(MUX,201)@13
finalExp_uid202_rrx_uid34_fpTanTest_s <= ld_xBranch_uid184_rrx_uid34_fpTanTest_n_to_finalExp_uid202_rrx_uid34_fpTanTest_b_q;
finalExp_uid202_rrx_uid34_fpTanTest: PROCESS (finalExp_uid202_rrx_uid34_fpTanTest_s, en, reg_expCompOut_uid198_rrx_uid34_fpTanTest_0_to_finalExp_uid202_rrx_uid34_fpTanTest_2_q, ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_mem_q)
BEGIN
CASE finalExp_uid202_rrx_uid34_fpTanTest_s IS
WHEN "0" => finalExp_uid202_rrx_uid34_fpTanTest_q <= reg_expCompOut_uid198_rrx_uid34_fpTanTest_0_to_finalExp_uid202_rrx_uid34_fpTanTest_2_q;
WHEN "1" => finalExp_uid202_rrx_uid34_fpTanTest_q <= ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_mem_q;
WHEN OTHERS => finalExp_uid202_rrx_uid34_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_finalExp_uid202_rrx_uid34_fpTanTest_q_to_RRangeRed_uid203_rrx_uid34_fpTanTest_b(DELAY,949)@13
ld_finalExp_uid202_rrx_uid34_fpTanTest_q_to_RRangeRed_uid203_rrx_uid34_fpTanTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => finalExp_uid202_rrx_uid34_fpTanTest_q, xout => ld_finalExp_uid202_rrx_uid34_fpTanTest_q_to_RRangeRed_uid203_rrx_uid34_fpTanTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_nor(LOGICAL,1665)
ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_nor_a <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_notEnable_q;
ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_nor_b <= ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_sticky_ena_q;
ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_nor_q <= not (ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_nor_a or ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_nor_b);
--ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_mem_top(CONSTANT,1535)
ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_mem_top_q <= "0111";
--ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_cmp(LOGICAL,1536)
ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_cmp_a <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_mem_top_q;
ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_rdmux_q);
ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_cmp_q <= "1" when ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_cmp_a = ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_cmp_b else "0";
--ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_cmpReg(REG,1537)
ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_cmpReg_q <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_sticky_ena(REG,1666)
ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_nor_q = "1") THEN
ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_sticky_ena_q <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_enaAnd(LOGICAL,1667)
ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_enaAnd_a <= ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_sticky_ena_q;
ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_enaAnd_b <= en;
ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_enaAnd_q <= ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_enaAnd_a and ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_enaAnd_b;
--ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_inputreg(DELAY,1655)
ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid180_rrx_uid34_fpTanTest_b, xout => ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_rdcnt(COUNTER,1531)
-- every=1, low=0, high=7, step=1, init=1
ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_rdcnt_i <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_rdcnt_i,3));
--ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_rdreg(REG,1532)
ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_rdreg_q <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_rdmux(MUX,1533)
ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_rdmux_s <= en;
ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_rdmux: PROCESS (ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_rdmux_s, ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_rdreg_q, ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_rdmux_s IS
WHEN "0" => ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_rdmux_q <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_rdreg_q;
WHEN "1" => ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_rdmux_q <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_replace_mem(DUALMEM,1656)
ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_replace_mem_ia <= ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_inputreg_q;
ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_replace_mem_aa <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_rdreg_q;
ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_replace_mem_ab <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_rdmux_q;
ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 3,
numwords_a => 8,
width_b => 23,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_replace_mem_iq,
address_a => ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_replace_mem_aa,
data_a => ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_replace_mem_ia
);
ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_replace_mem_reset0 <= areset;
ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_replace_mem_q <= ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_replace_mem_iq(22 downto 0);
--ZerosGB_uid199_rrx_uid34_fpTanTest(CONSTANT,198)
ZerosGB_uid199_rrx_uid34_fpTanTest_q <= "000000000000000000000000000000";
--fracXRExt_uid200_rrx_uid34_fpTanTest(BITJOIN,199)@14
fracXRExt_uid200_rrx_uid34_fpTanTest_q <= ld_fracX_uid180_rrx_uid34_fpTanTest_b_to_fracXRExt_uid200_rrx_uid34_fpTanTest_b_replace_mem_q & ZerosGB_uid199_rrx_uid34_fpTanTest_q;
--LeftShiftStage174dto0_uid581_normMult_uid195_rrx_uid34_fpTanTest(BITSELECT,580)@13
LeftShiftStage174dto0_uid581_normMult_uid195_rrx_uid34_fpTanTest_in <= leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_q(74 downto 0);
LeftShiftStage174dto0_uid581_normMult_uid195_rrx_uid34_fpTanTest_b <= LeftShiftStage174dto0_uid581_normMult_uid195_rrx_uid34_fpTanTest_in(74 downto 0);
--leftShiftStage2Idx1_uid582_normMult_uid195_rrx_uid34_fpTanTest(BITJOIN,581)@13
leftShiftStage2Idx1_uid582_normMult_uid195_rrx_uid34_fpTanTest_q <= LeftShiftStage174dto0_uid581_normMult_uid195_rrx_uid34_fpTanTest_b & GND_q;
--X51dto0_uid565_normMult_uid195_rrx_uid34_fpTanTest(BITSELECT,564)@9
X51dto0_uid565_normMult_uid195_rrx_uid34_fpTanTest_in <= multFracBits_uid192_rrx_uid34_fpTanTest_b(51 downto 0);
X51dto0_uid565_normMult_uid195_rrx_uid34_fpTanTest_b <= X51dto0_uid565_normMult_uid195_rrx_uid34_fpTanTest_in(51 downto 0);
--ld_X51dto0_uid565_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage0Idx3_uid566_normMult_uid195_rrx_uid34_fpTanTest_b_inputreg(DELAY,1764)
ld_X51dto0_uid565_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage0Idx3_uid566_normMult_uid195_rrx_uid34_fpTanTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => X51dto0_uid565_normMult_uid195_rrx_uid34_fpTanTest_b, xout => ld_X51dto0_uid565_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage0Idx3_uid566_normMult_uid195_rrx_uid34_fpTanTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X51dto0_uid565_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage0Idx3_uid566_normMult_uid195_rrx_uid34_fpTanTest_b(DELAY,1315)@9
ld_X51dto0_uid565_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage0Idx3_uid566_normMult_uid195_rrx_uid34_fpTanTest_b : dspba_delay
GENERIC MAP ( width => 52, depth => 2 )
PORT MAP ( xin => ld_X51dto0_uid565_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage0Idx3_uid566_normMult_uid195_rrx_uid34_fpTanTest_b_inputreg_q, xout => ld_X51dto0_uid565_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage0Idx3_uid566_normMult_uid195_rrx_uid34_fpTanTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad24_uid286_alignedZSin_uid66_fpTanTest(CONSTANT,285)
leftShiftStage1Idx3Pad24_uid286_alignedZSin_uid66_fpTanTest_q <= "000000000000000000000000";
--leftShiftStage0Idx3_uid566_normMult_uid195_rrx_uid34_fpTanTest(BITJOIN,565)@12
leftShiftStage0Idx3_uid566_normMult_uid195_rrx_uid34_fpTanTest_q <= ld_X51dto0_uid565_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage0Idx3_uid566_normMult_uid195_rrx_uid34_fpTanTest_b_q & leftShiftStage1Idx3Pad24_uid286_alignedZSin_uid66_fpTanTest_q;
--X59dto0_uid562_normMult_uid195_rrx_uid34_fpTanTest(BITSELECT,561)@9
X59dto0_uid562_normMult_uid195_rrx_uid34_fpTanTest_in <= multFracBits_uid192_rrx_uid34_fpTanTest_b(59 downto 0);
X59dto0_uid562_normMult_uid195_rrx_uid34_fpTanTest_b <= X59dto0_uid562_normMult_uid195_rrx_uid34_fpTanTest_in(59 downto 0);
--ld_X59dto0_uid562_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage0Idx2_uid563_normMult_uid195_rrx_uid34_fpTanTest_b_inputreg(DELAY,1763)
ld_X59dto0_uid562_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage0Idx2_uid563_normMult_uid195_rrx_uid34_fpTanTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => X59dto0_uid562_normMult_uid195_rrx_uid34_fpTanTest_b, xout => ld_X59dto0_uid562_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage0Idx2_uid563_normMult_uid195_rrx_uid34_fpTanTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X59dto0_uid562_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage0Idx2_uid563_normMult_uid195_rrx_uid34_fpTanTest_b(DELAY,1313)@9
ld_X59dto0_uid562_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage0Idx2_uid563_normMult_uid195_rrx_uid34_fpTanTest_b : dspba_delay
GENERIC MAP ( width => 60, depth => 2 )
PORT MAP ( xin => ld_X59dto0_uid562_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage0Idx2_uid563_normMult_uid195_rrx_uid34_fpTanTest_b_inputreg_q, xout => ld_X59dto0_uid562_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage0Idx2_uid563_normMult_uid195_rrx_uid34_fpTanTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid563_normMult_uid195_rrx_uid34_fpTanTest(BITJOIN,562)@12
leftShiftStage0Idx2_uid563_normMult_uid195_rrx_uid34_fpTanTest_q <= ld_X59dto0_uid562_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage0Idx2_uid563_normMult_uid195_rrx_uid34_fpTanTest_b_q & zs_uid243_lzcZSin_uid65_fpTanTest_q;
--X67dto0_uid559_normMult_uid195_rrx_uid34_fpTanTest(BITSELECT,558)@9
X67dto0_uid559_normMult_uid195_rrx_uid34_fpTanTest_in <= multFracBits_uid192_rrx_uid34_fpTanTest_b(67 downto 0);
X67dto0_uid559_normMult_uid195_rrx_uid34_fpTanTest_b <= X67dto0_uid559_normMult_uid195_rrx_uid34_fpTanTest_in(67 downto 0);
--ld_X67dto0_uid559_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage0Idx1_uid560_normMult_uid195_rrx_uid34_fpTanTest_b_inputreg(DELAY,1762)
ld_X67dto0_uid559_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage0Idx1_uid560_normMult_uid195_rrx_uid34_fpTanTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 68, depth => 1 )
PORT MAP ( xin => X67dto0_uid559_normMult_uid195_rrx_uid34_fpTanTest_b, xout => ld_X67dto0_uid559_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage0Idx1_uid560_normMult_uid195_rrx_uid34_fpTanTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X67dto0_uid559_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage0Idx1_uid560_normMult_uid195_rrx_uid34_fpTanTest_b(DELAY,1311)@9
ld_X67dto0_uid559_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage0Idx1_uid560_normMult_uid195_rrx_uid34_fpTanTest_b : dspba_delay
GENERIC MAP ( width => 68, depth => 2 )
PORT MAP ( xin => ld_X67dto0_uid559_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage0Idx1_uid560_normMult_uid195_rrx_uid34_fpTanTest_b_inputreg_q, xout => ld_X67dto0_uid559_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage0Idx1_uid560_normMult_uid195_rrx_uid34_fpTanTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1_uid560_normMult_uid195_rrx_uid34_fpTanTest(BITJOIN,559)@12
leftShiftStage0Idx1_uid560_normMult_uid195_rrx_uid34_fpTanTest_q <= ld_X67dto0_uid559_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage0Idx1_uid560_normMult_uid195_rrx_uid34_fpTanTest_b_q & cstAllZWE_uid8_fpTanTest_q;
--ld_multFracBits_uid192_rrx_uid34_fpTanTest_b_to_leftShiftStage0_uid568_normMult_uid195_rrx_uid34_fpTanTest_c_inputreg(DELAY,1765)
ld_multFracBits_uid192_rrx_uid34_fpTanTest_b_to_leftShiftStage0_uid568_normMult_uid195_rrx_uid34_fpTanTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 76, depth => 1 )
PORT MAP ( xin => multFracBits_uid192_rrx_uid34_fpTanTest_b, xout => ld_multFracBits_uid192_rrx_uid34_fpTanTest_b_to_leftShiftStage0_uid568_normMult_uid195_rrx_uid34_fpTanTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_multFracBits_uid192_rrx_uid34_fpTanTest_b_to_leftShiftStage0_uid568_normMult_uid195_rrx_uid34_fpTanTest_c(DELAY,1318)@9
ld_multFracBits_uid192_rrx_uid34_fpTanTest_b_to_leftShiftStage0_uid568_normMult_uid195_rrx_uid34_fpTanTest_c : dspba_delay
GENERIC MAP ( width => 76, depth => 2 )
PORT MAP ( xin => ld_multFracBits_uid192_rrx_uid34_fpTanTest_b_to_leftShiftStage0_uid568_normMult_uid195_rrx_uid34_fpTanTest_c_inputreg_q, xout => ld_multFracBits_uid192_rrx_uid34_fpTanTest_b_to_leftShiftStage0_uid568_normMult_uid195_rrx_uid34_fpTanTest_c_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStageSel4Dto3_uid567_normMult_uid195_rrx_uid34_fpTanTest(BITSELECT,566)@12
leftShiftStageSel4Dto3_uid567_normMult_uid195_rrx_uid34_fpTanTest_in <= r_uid555_zCount_uid194_rrx_uid34_fpTanTest_q;
leftShiftStageSel4Dto3_uid567_normMult_uid195_rrx_uid34_fpTanTest_b <= leftShiftStageSel4Dto3_uid567_normMult_uid195_rrx_uid34_fpTanTest_in(4 downto 3);
--leftShiftStage0_uid568_normMult_uid195_rrx_uid34_fpTanTest(MUX,567)@12
leftShiftStage0_uid568_normMult_uid195_rrx_uid34_fpTanTest_s <= leftShiftStageSel4Dto3_uid567_normMult_uid195_rrx_uid34_fpTanTest_b;
leftShiftStage0_uid568_normMult_uid195_rrx_uid34_fpTanTest: PROCESS (leftShiftStage0_uid568_normMult_uid195_rrx_uid34_fpTanTest_s, en, ld_multFracBits_uid192_rrx_uid34_fpTanTest_b_to_leftShiftStage0_uid568_normMult_uid195_rrx_uid34_fpTanTest_c_q, leftShiftStage0Idx1_uid560_normMult_uid195_rrx_uid34_fpTanTest_q, leftShiftStage0Idx2_uid563_normMult_uid195_rrx_uid34_fpTanTest_q, leftShiftStage0Idx3_uid566_normMult_uid195_rrx_uid34_fpTanTest_q)
BEGIN
CASE leftShiftStage0_uid568_normMult_uid195_rrx_uid34_fpTanTest_s IS
WHEN "00" => leftShiftStage0_uid568_normMult_uid195_rrx_uid34_fpTanTest_q <= ld_multFracBits_uid192_rrx_uid34_fpTanTest_b_to_leftShiftStage0_uid568_normMult_uid195_rrx_uid34_fpTanTest_c_q;
WHEN "01" => leftShiftStage0_uid568_normMult_uid195_rrx_uid34_fpTanTest_q <= leftShiftStage0Idx1_uid560_normMult_uid195_rrx_uid34_fpTanTest_q;
WHEN "10" => leftShiftStage0_uid568_normMult_uid195_rrx_uid34_fpTanTest_q <= leftShiftStage0Idx2_uid563_normMult_uid195_rrx_uid34_fpTanTest_q;
WHEN "11" => leftShiftStage0_uid568_normMult_uid195_rrx_uid34_fpTanTest_q <= leftShiftStage0Idx3_uid566_normMult_uid195_rrx_uid34_fpTanTest_q;
WHEN OTHERS => leftShiftStage0_uid568_normMult_uid195_rrx_uid34_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage069dto0_uid576_normMult_uid195_rrx_uid34_fpTanTest(BITSELECT,575)@12
LeftShiftStage069dto0_uid576_normMult_uid195_rrx_uid34_fpTanTest_in <= leftShiftStage0_uid568_normMult_uid195_rrx_uid34_fpTanTest_q(69 downto 0);
LeftShiftStage069dto0_uid576_normMult_uid195_rrx_uid34_fpTanTest_b <= LeftShiftStage069dto0_uid576_normMult_uid195_rrx_uid34_fpTanTest_in(69 downto 0);
--leftShiftStage2Idx3Pad6_uid297_alignedZSin_uid66_fpTanTest(CONSTANT,296)
leftShiftStage2Idx3Pad6_uid297_alignedZSin_uid66_fpTanTest_q <= "000000";
--leftShiftStage1Idx3_uid577_normMult_uid195_rrx_uid34_fpTanTest(BITJOIN,576)@12
leftShiftStage1Idx3_uid577_normMult_uid195_rrx_uid34_fpTanTest_q <= LeftShiftStage069dto0_uid576_normMult_uid195_rrx_uid34_fpTanTest_b & leftShiftStage2Idx3Pad6_uid297_alignedZSin_uid66_fpTanTest_q;
--reg_leftShiftStage1Idx3_uid577_normMult_uid195_rrx_uid34_fpTanTest_0_to_leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_5(REG,672)@12
reg_leftShiftStage1Idx3_uid577_normMult_uid195_rrx_uid34_fpTanTest_0_to_leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid577_normMult_uid195_rrx_uid34_fpTanTest_0_to_leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_5_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid577_normMult_uid195_rrx_uid34_fpTanTest_0_to_leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_5_q <= leftShiftStage1Idx3_uid577_normMult_uid195_rrx_uid34_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage071dto0_uid573_normMult_uid195_rrx_uid34_fpTanTest(BITSELECT,572)@12
LeftShiftStage071dto0_uid573_normMult_uid195_rrx_uid34_fpTanTest_in <= leftShiftStage0_uid568_normMult_uid195_rrx_uid34_fpTanTest_q(71 downto 0);
LeftShiftStage071dto0_uid573_normMult_uid195_rrx_uid34_fpTanTest_b <= LeftShiftStage071dto0_uid573_normMult_uid195_rrx_uid34_fpTanTest_in(71 downto 0);
--leftShiftStage1Idx2_uid574_normMult_uid195_rrx_uid34_fpTanTest(BITJOIN,573)@12
leftShiftStage1Idx2_uid574_normMult_uid195_rrx_uid34_fpTanTest_q <= LeftShiftStage071dto0_uid573_normMult_uid195_rrx_uid34_fpTanTest_b & leftShiftStage0Idx1Pad4_uid206_fxpX_uid48_fpTanTest_q;
--reg_leftShiftStage1Idx2_uid574_normMult_uid195_rrx_uid34_fpTanTest_0_to_leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_4(REG,671)@12
reg_leftShiftStage1Idx2_uid574_normMult_uid195_rrx_uid34_fpTanTest_0_to_leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid574_normMult_uid195_rrx_uid34_fpTanTest_0_to_leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_4_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid574_normMult_uid195_rrx_uid34_fpTanTest_0_to_leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_4_q <= leftShiftStage1Idx2_uid574_normMult_uid195_rrx_uid34_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage073dto0_uid570_normMult_uid195_rrx_uid34_fpTanTest(BITSELECT,569)@12
LeftShiftStage073dto0_uid570_normMult_uid195_rrx_uid34_fpTanTest_in <= leftShiftStage0_uid568_normMult_uid195_rrx_uid34_fpTanTest_q(73 downto 0);
LeftShiftStage073dto0_uid570_normMult_uid195_rrx_uid34_fpTanTest_b <= LeftShiftStage073dto0_uid570_normMult_uid195_rrx_uid34_fpTanTest_in(73 downto 0);
--leftShiftStage1Idx1_uid571_normMult_uid195_rrx_uid34_fpTanTest(BITJOIN,570)@12
leftShiftStage1Idx1_uid571_normMult_uid195_rrx_uid34_fpTanTest_q <= LeftShiftStage073dto0_uid570_normMult_uid195_rrx_uid34_fpTanTest_b & leftShiftStage1Idx2Pad2_uid220_fxpX_uid48_fpTanTest_q;
--reg_leftShiftStage1Idx1_uid571_normMult_uid195_rrx_uid34_fpTanTest_0_to_leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_3(REG,670)@12
reg_leftShiftStage1Idx1_uid571_normMult_uid195_rrx_uid34_fpTanTest_0_to_leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid571_normMult_uid195_rrx_uid34_fpTanTest_0_to_leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_3_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid571_normMult_uid195_rrx_uid34_fpTanTest_0_to_leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_3_q <= leftShiftStage1Idx1_uid571_normMult_uid195_rrx_uid34_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid568_normMult_uid195_rrx_uid34_fpTanTest_0_to_leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_2(REG,669)@12
reg_leftShiftStage0_uid568_normMult_uid195_rrx_uid34_fpTanTest_0_to_leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid568_normMult_uid195_rrx_uid34_fpTanTest_0_to_leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid568_normMult_uid195_rrx_uid34_fpTanTest_0_to_leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_2_q <= leftShiftStage0_uid568_normMult_uid195_rrx_uid34_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid578_normMult_uid195_rrx_uid34_fpTanTest(BITSELECT,577)@12
leftShiftStageSel2Dto1_uid578_normMult_uid195_rrx_uid34_fpTanTest_in <= r_uid555_zCount_uid194_rrx_uid34_fpTanTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid578_normMult_uid195_rrx_uid34_fpTanTest_b <= leftShiftStageSel2Dto1_uid578_normMult_uid195_rrx_uid34_fpTanTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid578_normMult_uid195_rrx_uid34_fpTanTest_0_to_leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_1(REG,668)@12
reg_leftShiftStageSel2Dto1_uid578_normMult_uid195_rrx_uid34_fpTanTest_0_to_leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid578_normMult_uid195_rrx_uid34_fpTanTest_0_to_leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid578_normMult_uid195_rrx_uid34_fpTanTest_0_to_leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_1_q <= leftShiftStageSel2Dto1_uid578_normMult_uid195_rrx_uid34_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest(MUX,578)@13
leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_s <= reg_leftShiftStageSel2Dto1_uid578_normMult_uid195_rrx_uid34_fpTanTest_0_to_leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_1_q;
leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest: PROCESS (leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_s, en, reg_leftShiftStage0_uid568_normMult_uid195_rrx_uid34_fpTanTest_0_to_leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_2_q, reg_leftShiftStage1Idx1_uid571_normMult_uid195_rrx_uid34_fpTanTest_0_to_leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_3_q, reg_leftShiftStage1Idx2_uid574_normMult_uid195_rrx_uid34_fpTanTest_0_to_leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_4_q, reg_leftShiftStage1Idx3_uid577_normMult_uid195_rrx_uid34_fpTanTest_0_to_leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_5_q)
BEGIN
CASE leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_s IS
WHEN "00" => leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_q <= reg_leftShiftStage0_uid568_normMult_uid195_rrx_uid34_fpTanTest_0_to_leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_2_q;
WHEN "01" => leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_q <= reg_leftShiftStage1Idx1_uid571_normMult_uid195_rrx_uid34_fpTanTest_0_to_leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_3_q;
WHEN "10" => leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_q <= reg_leftShiftStage1Idx2_uid574_normMult_uid195_rrx_uid34_fpTanTest_0_to_leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_4_q;
WHEN "11" => leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_q <= reg_leftShiftStage1Idx3_uid577_normMult_uid195_rrx_uid34_fpTanTest_0_to_leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_5_q;
WHEN OTHERS => leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid583_normMult_uid195_rrx_uid34_fpTanTest(BITSELECT,582)@12
leftShiftStageSel0Dto0_uid583_normMult_uid195_rrx_uid34_fpTanTest_in <= r_uid555_zCount_uid194_rrx_uid34_fpTanTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid583_normMult_uid195_rrx_uid34_fpTanTest_b <= leftShiftStageSel0Dto0_uid583_normMult_uid195_rrx_uid34_fpTanTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid583_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage2_uid584_normMult_uid195_rrx_uid34_fpTanTest_b(DELAY,1337)@12
ld_leftShiftStageSel0Dto0_uid583_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage2_uid584_normMult_uid195_rrx_uid34_fpTanTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid583_normMult_uid195_rrx_uid34_fpTanTest_b, xout => ld_leftShiftStageSel0Dto0_uid583_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage2_uid584_normMult_uid195_rrx_uid34_fpTanTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid584_normMult_uid195_rrx_uid34_fpTanTest(MUX,583)@13
leftShiftStage2_uid584_normMult_uid195_rrx_uid34_fpTanTest_s <= ld_leftShiftStageSel0Dto0_uid583_normMult_uid195_rrx_uid34_fpTanTest_b_to_leftShiftStage2_uid584_normMult_uid195_rrx_uid34_fpTanTest_b_q;
leftShiftStage2_uid584_normMult_uid195_rrx_uid34_fpTanTest: PROCESS (leftShiftStage2_uid584_normMult_uid195_rrx_uid34_fpTanTest_s, en, leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_q, leftShiftStage2Idx1_uid582_normMult_uid195_rrx_uid34_fpTanTest_q)
BEGIN
CASE leftShiftStage2_uid584_normMult_uid195_rrx_uid34_fpTanTest_s IS
WHEN "0" => leftShiftStage2_uid584_normMult_uid195_rrx_uid34_fpTanTest_q <= leftShiftStage1_uid579_normMult_uid195_rrx_uid34_fpTanTest_q;
WHEN "1" => leftShiftStage2_uid584_normMult_uid195_rrx_uid34_fpTanTest_q <= leftShiftStage2Idx1_uid582_normMult_uid195_rrx_uid34_fpTanTest_q;
WHEN OTHERS => leftShiftStage2_uid584_normMult_uid195_rrx_uid34_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracCompOut_uid196_rrx_uid34_fpTanTest(BITSELECT,195)@13
fracCompOut_uid196_rrx_uid34_fpTanTest_in <= leftShiftStage2_uid584_normMult_uid195_rrx_uid34_fpTanTest_q(74 downto 0);
fracCompOut_uid196_rrx_uid34_fpTanTest_b <= fracCompOut_uid196_rrx_uid34_fpTanTest_in(74 downto 22);
--reg_fracCompOut_uid196_rrx_uid34_fpTanTest_0_to_finalFrac_uid201_rrx_uid34_fpTanTest_2(REG,673)@13
reg_fracCompOut_uid196_rrx_uid34_fpTanTest_0_to_finalFrac_uid201_rrx_uid34_fpTanTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracCompOut_uid196_rrx_uid34_fpTanTest_0_to_finalFrac_uid201_rrx_uid34_fpTanTest_2_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracCompOut_uid196_rrx_uid34_fpTanTest_0_to_finalFrac_uid201_rrx_uid34_fpTanTest_2_q <= fracCompOut_uid196_rrx_uid34_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--ld_xBranch_uid184_rrx_uid34_fpTanTest_n_to_finalFrac_uid201_rrx_uid34_fpTanTest_b(DELAY,942)@1
ld_xBranch_uid184_rrx_uid34_fpTanTest_n_to_finalFrac_uid201_rrx_uid34_fpTanTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => xBranch_uid184_rrx_uid34_fpTanTest_n, xout => ld_xBranch_uid184_rrx_uid34_fpTanTest_n_to_finalFrac_uid201_rrx_uid34_fpTanTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalFrac_uid201_rrx_uid34_fpTanTest(MUX,200)@14
finalFrac_uid201_rrx_uid34_fpTanTest_s <= ld_xBranch_uid184_rrx_uid34_fpTanTest_n_to_finalFrac_uid201_rrx_uid34_fpTanTest_b_q;
finalFrac_uid201_rrx_uid34_fpTanTest: PROCESS (finalFrac_uid201_rrx_uid34_fpTanTest_s, en, reg_fracCompOut_uid196_rrx_uid34_fpTanTest_0_to_finalFrac_uid201_rrx_uid34_fpTanTest_2_q, fracXRExt_uid200_rrx_uid34_fpTanTest_q)
BEGIN
CASE finalFrac_uid201_rrx_uid34_fpTanTest_s IS
WHEN "0" => finalFrac_uid201_rrx_uid34_fpTanTest_q <= reg_fracCompOut_uid196_rrx_uid34_fpTanTest_0_to_finalFrac_uid201_rrx_uid34_fpTanTest_2_q;
WHEN "1" => finalFrac_uid201_rrx_uid34_fpTanTest_q <= fracXRExt_uid200_rrx_uid34_fpTanTest_q;
WHEN OTHERS => finalFrac_uid201_rrx_uid34_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--RRangeRed_uid203_rrx_uid34_fpTanTest(BITJOIN,202)@14
RRangeRed_uid203_rrx_uid34_fpTanTest_q <= GND_q & ld_finalExp_uid202_rrx_uid34_fpTanTest_q_to_RRangeRed_uid203_rrx_uid34_fpTanTest_b_q & finalFrac_uid201_rrx_uid34_fpTanTest_q;
--expXRR_uid39_fpTanTest(BITSELECT,38)@14
expXRR_uid39_fpTanTest_in <= RRangeRed_uid203_rrx_uid34_fpTanTest_q(60 downto 0);
expXRR_uid39_fpTanTest_b <= expXRR_uid39_fpTanTest_in(60 downto 53);
--cstBiasMwShiftM2_uid26_fpTanTest(CONSTANT,25)
cstBiasMwShiftM2_uid26_fpTanTest_q <= "01110000";
--cosXIsOneXRR_uid43_fpTanTest(COMPARE,42)@14
cosXIsOneXRR_uid43_fpTanTest_cin <= GND_q;
cosXIsOneXRR_uid43_fpTanTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid26_fpTanTest_q) & '0';
cosXIsOneXRR_uid43_fpTanTest_b <= STD_LOGIC_VECTOR((10 downto 8 => expXRR_uid39_fpTanTest_b(7)) & expXRR_uid39_fpTanTest_b) & cosXIsOneXRR_uid43_fpTanTest_cin(0);
cosXIsOneXRR_uid43_fpTanTest_o <= STD_LOGIC_VECTOR(SIGNED(cosXIsOneXRR_uid43_fpTanTest_a) - SIGNED(cosXIsOneXRR_uid43_fpTanTest_b));
cosXIsOneXRR_uid43_fpTanTest_n(0) <= not cosXIsOneXRR_uid43_fpTanTest_o(11);
--exp_uid9_fpTanTest(BITSELECT,8)@0
exp_uid9_fpTanTest_in <= a(30 downto 0);
exp_uid9_fpTanTest_b <= exp_uid9_fpTanTest_in(30 downto 23);
--sinXIsX_uid41_fpTanTest(COMPARE,40)@0
sinXIsX_uid41_fpTanTest_cin <= GND_q;
sinXIsX_uid41_fpTanTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid24_fpTanTest_q) & '0';
sinXIsX_uid41_fpTanTest_b <= STD_LOGIC_VECTOR("00" & exp_uid9_fpTanTest_b) & sinXIsX_uid41_fpTanTest_cin(0);
sinXIsX_uid41_fpTanTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid41_fpTanTest_a) - UNSIGNED(sinXIsX_uid41_fpTanTest_b));
sinXIsX_uid41_fpTanTest_n(0) <= not sinXIsX_uid41_fpTanTest_o(10);
--ld_sinXIsX_uid41_fpTanTest_n_to_cosOne_uid144_fpTanTest_a(DELAY,908)@0
ld_sinXIsX_uid41_fpTanTest_n_to_cosOne_uid144_fpTanTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 14 )
PORT MAP ( xin => sinXIsX_uid41_fpTanTest_n, xout => ld_sinXIsX_uid41_fpTanTest_n_to_cosOne_uid144_fpTanTest_a_q, ena => en(0), clk => clk, aclr => areset );
--cosOne_uid144_fpTanTest(LOGICAL,143)@14
cosOne_uid144_fpTanTest_a <= ld_sinXIsX_uid41_fpTanTest_n_to_cosOne_uid144_fpTanTest_a_q;
cosOne_uid144_fpTanTest_b <= cosXIsOneXRR_uid43_fpTanTest_n;
cosOne_uid144_fpTanTest_q <= cosOne_uid144_fpTanTest_a or cosOne_uid144_fpTanTest_b;
--ld_cosOne_uid144_fpTanTest_q_to_InvCosOne_uid145_fpTanTest_a(DELAY,910)@14
ld_cosOne_uid144_fpTanTest_q_to_InvCosOne_uid145_fpTanTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => cosOne_uid144_fpTanTest_q, xout => ld_cosOne_uid144_fpTanTest_q_to_InvCosOne_uid145_fpTanTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvCosOne_uid145_fpTanTest(LOGICAL,144)@17
InvCosOne_uid145_fpTanTest_a <= ld_cosOne_uid144_fpTanTest_q_to_InvCosOne_uid145_fpTanTest_a_q;
InvCosOne_uid145_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvCosOne_uid145_fpTanTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvCosOne_uid145_fpTanTest_q <= not InvCosOne_uid145_fpTanTest_a;
END IF;
END PROCESS;
--X55dto0_uid213_fxpX_uid48_fpTanTest(BITSELECT,212)@15
X55dto0_uid213_fxpX_uid48_fpTanTest_in <= extendedFracX_uid47_fpTanTest_q(55 downto 0);
X55dto0_uid213_fxpX_uid48_fpTanTest_b <= X55dto0_uid213_fxpX_uid48_fpTanTest_in(55 downto 0);
--leftShiftStage0Idx3Pad12_uid212_fxpX_uid48_fpTanTest(CONSTANT,211)
leftShiftStage0Idx3Pad12_uid212_fxpX_uid48_fpTanTest_q <= "000000000000";
--leftShiftStage0Idx3_uid214_fxpX_uid48_fpTanTest(BITJOIN,213)@15
leftShiftStage0Idx3_uid214_fxpX_uid48_fpTanTest_q <= X55dto0_uid213_fxpX_uid48_fpTanTest_b & leftShiftStage0Idx3Pad12_uid212_fxpX_uid48_fpTanTest_q;
--X59dto0_uid210_fxpX_uid48_fpTanTest(BITSELECT,209)@15
X59dto0_uid210_fxpX_uid48_fpTanTest_in <= extendedFracX_uid47_fpTanTest_q(59 downto 0);
X59dto0_uid210_fxpX_uid48_fpTanTest_b <= X59dto0_uid210_fxpX_uid48_fpTanTest_in(59 downto 0);
--leftShiftStage0Idx2_uid211_fxpX_uid48_fpTanTest(BITJOIN,210)@15
leftShiftStage0Idx2_uid211_fxpX_uid48_fpTanTest_q <= X59dto0_uid210_fxpX_uid48_fpTanTest_b & cstAllZWE_uid8_fpTanTest_q;
--X63dto0_uid207_fxpX_uid48_fpTanTest(BITSELECT,206)@15
X63dto0_uid207_fxpX_uid48_fpTanTest_in <= extendedFracX_uid47_fpTanTest_q(63 downto 0);
X63dto0_uid207_fxpX_uid48_fpTanTest_b <= X63dto0_uid207_fxpX_uid48_fpTanTest_in(63 downto 0);
--leftShiftStage0Idx1_uid208_fxpX_uid48_fpTanTest(BITJOIN,207)@15
leftShiftStage0Idx1_uid208_fxpX_uid48_fpTanTest_q <= X63dto0_uid207_fxpX_uid48_fpTanTest_b & leftShiftStage0Idx1Pad4_uid206_fxpX_uid48_fpTanTest_q;
--cstZwShiftP1_uid27_fpTanTest(CONSTANT,26)
cstZwShiftP1_uid27_fpTanTest_q <= "00000000000000";
--fracXRR_uid40_fpTanTest(BITSELECT,39)@14
fracXRR_uid40_fpTanTest_in <= RRangeRed_uid203_rrx_uid34_fpTanTest_q(52 downto 0);
fracXRR_uid40_fpTanTest_b <= fracXRR_uid40_fpTanTest_in(52 downto 0);
--ld_fracXRR_uid40_fpTanTest_b_to_oFracXRR_uid44_uid44_fpTanTest_a(DELAY,792)@14
ld_fracXRR_uid40_fpTanTest_b_to_oFracXRR_uid44_uid44_fpTanTest_a : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => fracXRR_uid40_fpTanTest_b, xout => ld_fracXRR_uid40_fpTanTest_b_to_oFracXRR_uid44_uid44_fpTanTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracXRR_uid44_uid44_fpTanTest(BITJOIN,43)@15
oFracXRR_uid44_uid44_fpTanTest_q <= VCC_q & ld_fracXRR_uid40_fpTanTest_b_to_oFracXRR_uid44_uid44_fpTanTest_a_q;
--extendedFracX_uid47_fpTanTest(BITJOIN,46)@15
extendedFracX_uid47_fpTanTest_q <= cstZwShiftP1_uid27_fpTanTest_q & oFracXRR_uid44_uid44_fpTanTest_q;
--fxpXShiftValExt_uid45_fpTanTest(SUB,44)@14
fxpXShiftValExt_uid45_fpTanTest_a <= STD_LOGIC_VECTOR((10 downto 8 => expXRR_uid39_fpTanTest_b(7)) & expXRR_uid39_fpTanTest_b);
fxpXShiftValExt_uid45_fpTanTest_b <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid26_fpTanTest_q);
fxpXShiftValExt_uid45_fpTanTest_o <= STD_LOGIC_VECTOR(SIGNED(fxpXShiftValExt_uid45_fpTanTest_a) - SIGNED(fxpXShiftValExt_uid45_fpTanTest_b));
fxpXShiftValExt_uid45_fpTanTest_q <= fxpXShiftValExt_uid45_fpTanTest_o(9 downto 0);
--fxpXShiftVal_uid46_fpTanTest(BITSELECT,45)@14
fxpXShiftVal_uid46_fpTanTest_in <= fxpXShiftValExt_uid45_fpTanTest_q(3 downto 0);
fxpXShiftVal_uid46_fpTanTest_b <= fxpXShiftVal_uid46_fpTanTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid215_fxpX_uid48_fpTanTest(BITSELECT,214)@14
leftShiftStageSel3Dto2_uid215_fxpX_uid48_fpTanTest_in <= fxpXShiftVal_uid46_fpTanTest_b;
leftShiftStageSel3Dto2_uid215_fxpX_uid48_fpTanTest_b <= leftShiftStageSel3Dto2_uid215_fxpX_uid48_fpTanTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid215_fxpX_uid48_fpTanTest_0_to_leftShiftStage0_uid216_fxpX_uid48_fpTanTest_1(REG,675)@14
reg_leftShiftStageSel3Dto2_uid215_fxpX_uid48_fpTanTest_0_to_leftShiftStage0_uid216_fxpX_uid48_fpTanTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid215_fxpX_uid48_fpTanTest_0_to_leftShiftStage0_uid216_fxpX_uid48_fpTanTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid215_fxpX_uid48_fpTanTest_0_to_leftShiftStage0_uid216_fxpX_uid48_fpTanTest_1_q <= leftShiftStageSel3Dto2_uid215_fxpX_uid48_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid216_fxpX_uid48_fpTanTest(MUX,215)@15
leftShiftStage0_uid216_fxpX_uid48_fpTanTest_s <= reg_leftShiftStageSel3Dto2_uid215_fxpX_uid48_fpTanTest_0_to_leftShiftStage0_uid216_fxpX_uid48_fpTanTest_1_q;
leftShiftStage0_uid216_fxpX_uid48_fpTanTest: PROCESS (leftShiftStage0_uid216_fxpX_uid48_fpTanTest_s, en, extendedFracX_uid47_fpTanTest_q, leftShiftStage0Idx1_uid208_fxpX_uid48_fpTanTest_q, leftShiftStage0Idx2_uid211_fxpX_uid48_fpTanTest_q, leftShiftStage0Idx3_uid214_fxpX_uid48_fpTanTest_q)
BEGIN
CASE leftShiftStage0_uid216_fxpX_uid48_fpTanTest_s IS
WHEN "00" => leftShiftStage0_uid216_fxpX_uid48_fpTanTest_q <= extendedFracX_uid47_fpTanTest_q;
WHEN "01" => leftShiftStage0_uid216_fxpX_uid48_fpTanTest_q <= leftShiftStage0Idx1_uid208_fxpX_uid48_fpTanTest_q;
WHEN "10" => leftShiftStage0_uid216_fxpX_uid48_fpTanTest_q <= leftShiftStage0Idx2_uid211_fxpX_uid48_fpTanTest_q;
WHEN "11" => leftShiftStage0_uid216_fxpX_uid48_fpTanTest_q <= leftShiftStage0Idx3_uid214_fxpX_uid48_fpTanTest_q;
WHEN OTHERS => leftShiftStage0_uid216_fxpX_uid48_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage064dto0_uid224_fxpX_uid48_fpTanTest(BITSELECT,223)@15
LeftShiftStage064dto0_uid224_fxpX_uid48_fpTanTest_in <= leftShiftStage0_uid216_fxpX_uid48_fpTanTest_q(64 downto 0);
LeftShiftStage064dto0_uid224_fxpX_uid48_fpTanTest_b <= LeftShiftStage064dto0_uid224_fxpX_uid48_fpTanTest_in(64 downto 0);
--ld_LeftShiftStage064dto0_uid224_fxpX_uid48_fpTanTest_b_to_leftShiftStage1Idx3_uid225_fxpX_uid48_fpTanTest_b(DELAY,967)@15
ld_LeftShiftStage064dto0_uid224_fxpX_uid48_fpTanTest_b_to_leftShiftStage1Idx3_uid225_fxpX_uid48_fpTanTest_b : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => LeftShiftStage064dto0_uid224_fxpX_uid48_fpTanTest_b, xout => ld_LeftShiftStage064dto0_uid224_fxpX_uid48_fpTanTest_b_to_leftShiftStage1Idx3_uid225_fxpX_uid48_fpTanTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid223_fxpX_uid48_fpTanTest(CONSTANT,222)
leftShiftStage1Idx3Pad3_uid223_fxpX_uid48_fpTanTest_q <= "000";
--leftShiftStage1Idx3_uid225_fxpX_uid48_fpTanTest(BITJOIN,224)@16
leftShiftStage1Idx3_uid225_fxpX_uid48_fpTanTest_q <= ld_LeftShiftStage064dto0_uid224_fxpX_uid48_fpTanTest_b_to_leftShiftStage1Idx3_uid225_fxpX_uid48_fpTanTest_b_q & leftShiftStage1Idx3Pad3_uid223_fxpX_uid48_fpTanTest_q;
--LeftShiftStage065dto0_uid221_fxpX_uid48_fpTanTest(BITSELECT,220)@15
LeftShiftStage065dto0_uid221_fxpX_uid48_fpTanTest_in <= leftShiftStage0_uid216_fxpX_uid48_fpTanTest_q(65 downto 0);
LeftShiftStage065dto0_uid221_fxpX_uid48_fpTanTest_b <= LeftShiftStage065dto0_uid221_fxpX_uid48_fpTanTest_in(65 downto 0);
--ld_LeftShiftStage065dto0_uid221_fxpX_uid48_fpTanTest_b_to_leftShiftStage1Idx2_uid222_fxpX_uid48_fpTanTest_b(DELAY,965)@15
ld_LeftShiftStage065dto0_uid221_fxpX_uid48_fpTanTest_b_to_leftShiftStage1Idx2_uid222_fxpX_uid48_fpTanTest_b : dspba_delay
GENERIC MAP ( width => 66, depth => 1 )
PORT MAP ( xin => LeftShiftStage065dto0_uid221_fxpX_uid48_fpTanTest_b, xout => ld_LeftShiftStage065dto0_uid221_fxpX_uid48_fpTanTest_b_to_leftShiftStage1Idx2_uid222_fxpX_uid48_fpTanTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid222_fxpX_uid48_fpTanTest(BITJOIN,221)@16
leftShiftStage1Idx2_uid222_fxpX_uid48_fpTanTest_q <= ld_LeftShiftStage065dto0_uid221_fxpX_uid48_fpTanTest_b_to_leftShiftStage1Idx2_uid222_fxpX_uid48_fpTanTest_b_q & leftShiftStage1Idx2Pad2_uid220_fxpX_uid48_fpTanTest_q;
--LeftShiftStage066dto0_uid218_fxpX_uid48_fpTanTest(BITSELECT,217)@15
LeftShiftStage066dto0_uid218_fxpX_uid48_fpTanTest_in <= leftShiftStage0_uid216_fxpX_uid48_fpTanTest_q(66 downto 0);
LeftShiftStage066dto0_uid218_fxpX_uid48_fpTanTest_b <= LeftShiftStage066dto0_uid218_fxpX_uid48_fpTanTest_in(66 downto 0);
--ld_LeftShiftStage066dto0_uid218_fxpX_uid48_fpTanTest_b_to_leftShiftStage1Idx1_uid219_fxpX_uid48_fpTanTest_b(DELAY,963)@15
ld_LeftShiftStage066dto0_uid218_fxpX_uid48_fpTanTest_b_to_leftShiftStage1Idx1_uid219_fxpX_uid48_fpTanTest_b : dspba_delay
GENERIC MAP ( width => 67, depth => 1 )
PORT MAP ( xin => LeftShiftStage066dto0_uid218_fxpX_uid48_fpTanTest_b, xout => ld_LeftShiftStage066dto0_uid218_fxpX_uid48_fpTanTest_b_to_leftShiftStage1Idx1_uid219_fxpX_uid48_fpTanTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid219_fxpX_uid48_fpTanTest(BITJOIN,218)@16
leftShiftStage1Idx1_uid219_fxpX_uid48_fpTanTest_q <= ld_LeftShiftStage066dto0_uid218_fxpX_uid48_fpTanTest_b_to_leftShiftStage1Idx1_uid219_fxpX_uid48_fpTanTest_b_q & GND_q;
--reg_leftShiftStage0_uid216_fxpX_uid48_fpTanTest_0_to_leftShiftStage1_uid227_fxpX_uid48_fpTanTest_2(REG,677)@15
reg_leftShiftStage0_uid216_fxpX_uid48_fpTanTest_0_to_leftShiftStage1_uid227_fxpX_uid48_fpTanTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid216_fxpX_uid48_fpTanTest_0_to_leftShiftStage1_uid227_fxpX_uid48_fpTanTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid216_fxpX_uid48_fpTanTest_0_to_leftShiftStage1_uid227_fxpX_uid48_fpTanTest_2_q <= leftShiftStage0_uid216_fxpX_uid48_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid226_fxpX_uid48_fpTanTest(BITSELECT,225)@14
leftShiftStageSel1Dto0_uid226_fxpX_uid48_fpTanTest_in <= fxpXShiftVal_uid46_fpTanTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid226_fxpX_uid48_fpTanTest_b <= leftShiftStageSel1Dto0_uid226_fxpX_uid48_fpTanTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid226_fxpX_uid48_fpTanTest_b_to_reg_leftShiftStageSel1Dto0_uid226_fxpX_uid48_fpTanTest_0_to_leftShiftStage1_uid227_fxpX_uid48_fpTanTest_1_a(DELAY,1430)@14
ld_leftShiftStageSel1Dto0_uid226_fxpX_uid48_fpTanTest_b_to_reg_leftShiftStageSel1Dto0_uid226_fxpX_uid48_fpTanTest_0_to_leftShiftStage1_uid227_fxpX_uid48_fpTanTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid226_fxpX_uid48_fpTanTest_b, xout => ld_leftShiftStageSel1Dto0_uid226_fxpX_uid48_fpTanTest_b_to_reg_leftShiftStageSel1Dto0_uid226_fxpX_uid48_fpTanTest_0_to_leftShiftStage1_uid227_fxpX_uid48_fpTanTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid226_fxpX_uid48_fpTanTest_0_to_leftShiftStage1_uid227_fxpX_uid48_fpTanTest_1(REG,676)@15
reg_leftShiftStageSel1Dto0_uid226_fxpX_uid48_fpTanTest_0_to_leftShiftStage1_uid227_fxpX_uid48_fpTanTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid226_fxpX_uid48_fpTanTest_0_to_leftShiftStage1_uid227_fxpX_uid48_fpTanTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid226_fxpX_uid48_fpTanTest_0_to_leftShiftStage1_uid227_fxpX_uid48_fpTanTest_1_q <= ld_leftShiftStageSel1Dto0_uid226_fxpX_uid48_fpTanTest_b_to_reg_leftShiftStageSel1Dto0_uid226_fxpX_uid48_fpTanTest_0_to_leftShiftStage1_uid227_fxpX_uid48_fpTanTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid227_fxpX_uid48_fpTanTest(MUX,226)@16
leftShiftStage1_uid227_fxpX_uid48_fpTanTest_s <= reg_leftShiftStageSel1Dto0_uid226_fxpX_uid48_fpTanTest_0_to_leftShiftStage1_uid227_fxpX_uid48_fpTanTest_1_q;
leftShiftStage1_uid227_fxpX_uid48_fpTanTest: PROCESS (leftShiftStage1_uid227_fxpX_uid48_fpTanTest_s, en, reg_leftShiftStage0_uid216_fxpX_uid48_fpTanTest_0_to_leftShiftStage1_uid227_fxpX_uid48_fpTanTest_2_q, leftShiftStage1Idx1_uid219_fxpX_uid48_fpTanTest_q, leftShiftStage1Idx2_uid222_fxpX_uid48_fpTanTest_q, leftShiftStage1Idx3_uid225_fxpX_uid48_fpTanTest_q)
BEGIN
CASE leftShiftStage1_uid227_fxpX_uid48_fpTanTest_s IS
WHEN "00" => leftShiftStage1_uid227_fxpX_uid48_fpTanTest_q <= reg_leftShiftStage0_uid216_fxpX_uid48_fpTanTest_0_to_leftShiftStage1_uid227_fxpX_uid48_fpTanTest_2_q;
WHEN "01" => leftShiftStage1_uid227_fxpX_uid48_fpTanTest_q <= leftShiftStage1Idx1_uid219_fxpX_uid48_fpTanTest_q;
WHEN "10" => leftShiftStage1_uid227_fxpX_uid48_fpTanTest_q <= leftShiftStage1Idx2_uid222_fxpX_uid48_fpTanTest_q;
WHEN "11" => leftShiftStage1_uid227_fxpX_uid48_fpTanTest_q <= leftShiftStage1Idx3_uid225_fxpX_uid48_fpTanTest_q;
WHEN OTHERS => leftShiftStage1_uid227_fxpX_uid48_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid50_fpTanTest(BITSELECT,49)@16
y_uid50_fpTanTest_in <= leftShiftStage1_uid227_fxpX_uid48_fpTanTest_q(66 downto 0);
y_uid50_fpTanTest_b <= y_uid50_fpTanTest_in(66 downto 1);
--ld_y_uid50_fpTanTest_b_to_cmpYToOneMinusY_uid56_fpTanTest_b(DELAY,804)@16
ld_y_uid50_fpTanTest_b_to_cmpYToOneMinusY_uid56_fpTanTest_b : dspba_delay
GENERIC MAP ( width => 66, depth => 2 )
PORT MAP ( xin => y_uid50_fpTanTest_b, xout => ld_y_uid50_fpTanTest_b_to_cmpYToOneMinusY_uid56_fpTanTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_y_uid50_fpTanTest_0_to_oneMinusY_uid54_fpTanTest_1(REG,679)@16
reg_y_uid50_fpTanTest_0_to_oneMinusY_uid54_fpTanTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid50_fpTanTest_0_to_oneMinusY_uid54_fpTanTest_1_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid50_fpTanTest_0_to_oneMinusY_uid54_fpTanTest_1_q <= y_uid50_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--pad_one_uid54_fpTanTest(BITJOIN,53)@16
pad_one_uid54_fpTanTest_q <= VCC_q & STD_LOGIC_VECTOR((65 downto 1 => GND_q(0)) & GND_q);
--reg_pad_one_uid54_fpTanTest_0_to_oneMinusY_uid54_fpTanTest_0(REG,678)@16
reg_pad_one_uid54_fpTanTest_0_to_oneMinusY_uid54_fpTanTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_one_uid54_fpTanTest_0_to_oneMinusY_uid54_fpTanTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_one_uid54_fpTanTest_0_to_oneMinusY_uid54_fpTanTest_0_q <= pad_one_uid54_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--oneMinusY_uid54_fpTanTest(SUB,54)@17
oneMinusY_uid54_fpTanTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_one_uid54_fpTanTest_0_to_oneMinusY_uid54_fpTanTest_0_q);
oneMinusY_uid54_fpTanTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid50_fpTanTest_0_to_oneMinusY_uid54_fpTanTest_1_q);
oneMinusY_uid54_fpTanTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid54_fpTanTest_a) - UNSIGNED(oneMinusY_uid54_fpTanTest_b));
oneMinusY_uid54_fpTanTest_q <= oneMinusY_uid54_fpTanTest_o(67 downto 0);
--reg_oneMinusY_uid54_fpTanTest_0_to_cmpYToOneMinusY_uid56_fpTanTest_0(REG,680)@17
reg_oneMinusY_uid54_fpTanTest_0_to_cmpYToOneMinusY_uid56_fpTanTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid54_fpTanTest_0_to_cmpYToOneMinusY_uid56_fpTanTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid54_fpTanTest_0_to_cmpYToOneMinusY_uid56_fpTanTest_0_q <= oneMinusY_uid54_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid56_fpTanTest(COMPARE,55)@18
cmpYToOneMinusY_uid56_fpTanTest_cin <= GND_q;
cmpYToOneMinusY_uid56_fpTanTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid54_fpTanTest_0_to_cmpYToOneMinusY_uid56_fpTanTest_0_q) & '0';
cmpYToOneMinusY_uid56_fpTanTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid50_fpTanTest_b_to_cmpYToOneMinusY_uid56_fpTanTest_b_q) & cmpYToOneMinusY_uid56_fpTanTest_cin(0);
cmpYToOneMinusY_uid56_fpTanTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid56_fpTanTest_a) - UNSIGNED(cmpYToOneMinusY_uid56_fpTanTest_b));
cmpYToOneMinusY_uid56_fpTanTest_c(0) <= cmpYToOneMinusY_uid56_fpTanTest_o(70);
--InvCmpYToOneMinusY_uid60_fpTanTest(LOGICAL,59)@18
InvCmpYToOneMinusY_uid60_fpTanTest_a <= cmpYToOneMinusY_uid56_fpTanTest_c;
InvCmpYToOneMinusY_uid60_fpTanTest_q <= not InvCmpYToOneMinusY_uid60_fpTanTest_a;
--intXParity_uid49_fpTanTest(BITSELECT,48)@16
intXParity_uid49_fpTanTest_in <= leftShiftStage1_uid227_fxpX_uid48_fpTanTest_q;
intXParity_uid49_fpTanTest_b <= intXParity_uid49_fpTanTest_in(67 downto 67);
--ld_intXParity_uid49_fpTanTest_b_to_signRCond2_uid148_fpTanTest_b(DELAY,913)@16
ld_intXParity_uid49_fpTanTest_b_to_signRCond2_uid148_fpTanTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => intXParity_uid49_fpTanTest_b, xout => ld_intXParity_uid49_fpTanTest_b_to_signRCond2_uid148_fpTanTest_b_q, ena => en(0), clk => clk, aclr => areset );
--yIsZero_uid51_fpTanTest(LOGICAL,50)@17
yIsZero_uid51_fpTanTest_a <= reg_y_uid50_fpTanTest_0_to_oneMinusY_uid54_fpTanTest_1_q;
yIsZero_uid51_fpTanTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000000000000000000000000000000000" & GND_q);
yIsZero_uid51_fpTanTest_q <= "1" when yIsZero_uid51_fpTanTest_a = yIsZero_uid51_fpTanTest_b else "0";
--ld_yIsZero_uid51_fpTanTest_q_to_InvYIsZero_uid147_fpTanTest_a(DELAY,911)@17
ld_yIsZero_uid51_fpTanTest_q_to_InvYIsZero_uid147_fpTanTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => yIsZero_uid51_fpTanTest_q, xout => ld_yIsZero_uid51_fpTanTest_q_to_InvYIsZero_uid147_fpTanTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvYIsZero_uid147_fpTanTest(LOGICAL,146)@18
InvYIsZero_uid147_fpTanTest_a <= ld_yIsZero_uid51_fpTanTest_q_to_InvYIsZero_uid147_fpTanTest_a_q;
InvYIsZero_uid147_fpTanTest_q <= not InvYIsZero_uid147_fpTanTest_a;
--signRCond2_uid148_fpTanTest(LOGICAL,147)@18
signRCond2_uid148_fpTanTest_a <= InvYIsZero_uid147_fpTanTest_q;
signRCond2_uid148_fpTanTest_b <= ld_intXParity_uid49_fpTanTest_b_to_signRCond2_uid148_fpTanTest_b_q;
signRCond2_uid148_fpTanTest_c <= InvCmpYToOneMinusY_uid60_fpTanTest_q;
signRCond2_uid148_fpTanTest_d <= InvCosOne_uid145_fpTanTest_q;
signRCond2_uid148_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRCond2_uid148_fpTanTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signRCond2_uid148_fpTanTest_q <= signRCond2_uid148_fpTanTest_a and signRCond2_uid148_fpTanTest_b and signRCond2_uid148_fpTanTest_c and signRCond2_uid148_fpTanTest_d;
END IF;
END IF;
END PROCESS;
--InvIntXParity_uid151_fpTanTest(LOGICAL,150)@16
InvIntXParity_uid151_fpTanTest_a <= intXParity_uid49_fpTanTest_b;
InvIntXParity_uid151_fpTanTest_q <= not InvIntXParity_uid151_fpTanTest_a;
--ld_InvIntXParity_uid151_fpTanTest_q_to_signRCond1_uid153_fpTanTest_b(DELAY,918)@16
ld_InvIntXParity_uid151_fpTanTest_q_to_signRCond1_uid153_fpTanTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => InvIntXParity_uid151_fpTanTest_q, xout => ld_InvIntXParity_uid151_fpTanTest_q_to_signRCond1_uid153_fpTanTest_b_q, ena => en(0), clk => clk, aclr => areset );
--signRCond1_uid153_fpTanTest(LOGICAL,152)@18
signRCond1_uid153_fpTanTest_a <= InvYIsZero_uid147_fpTanTest_q;
signRCond1_uid153_fpTanTest_b <= ld_InvIntXParity_uid151_fpTanTest_q_to_signRCond1_uid153_fpTanTest_b_q;
signRCond1_uid153_fpTanTest_c <= cmpYToOneMinusY_uid56_fpTanTest_c;
signRCond1_uid153_fpTanTest_d <= InvCosOne_uid145_fpTanTest_q;
signRCond1_uid153_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRCond1_uid153_fpTanTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signRCond1_uid153_fpTanTest_q <= signRCond1_uid153_fpTanTest_a and signRCond1_uid153_fpTanTest_b and signRCond1_uid153_fpTanTest_c and signRCond1_uid153_fpTanTest_d;
END IF;
END IF;
END PROCESS;
--signRCos_uid154_fpTanTest(LOGICAL,153)@19
signRCos_uid154_fpTanTest_a <= signRCond1_uid153_fpTanTest_q;
signRCos_uid154_fpTanTest_b <= signRCond2_uid148_fpTanTest_q;
signRCos_uid154_fpTanTest_q <= signRCos_uid154_fpTanTest_a or signRCos_uid154_fpTanTest_b;
--ld_signRCos_uid154_fpTanTest_q_to_fpCos_uid155_fpTanTest_c(DELAY,925)@19
ld_signRCos_uid154_fpTanTest_q_to_fpCos_uid155_fpTanTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRCos_uid154_fpTanTest_q, xout => ld_signRCos_uid154_fpTanTest_q_to_fpCos_uid155_fpTanTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstAllOWE_uid6_fpTanTest(CONSTANT,5)
cstAllOWE_uid6_fpTanTest_q <= "11111111";
--cstBias_uid22_fpTanTest(CONSTANT,21)
cstBias_uid22_fpTanTest_q <= "01111111";
--ld_oneMinusY_uid54_fpTanTest_q_to_zSinOMyBottom_uid57_fpTanTest_a(DELAY,805)@17
ld_oneMinusY_uid54_fpTanTest_q_to_zSinOMyBottom_uid57_fpTanTest_a : dspba_delay
GENERIC MAP ( width => 68, depth => 1 )
PORT MAP ( xin => oneMinusY_uid54_fpTanTest_q, xout => ld_oneMinusY_uid54_fpTanTest_q_to_zSinOMyBottom_uid57_fpTanTest_a_q, ena => en(0), clk => clk, aclr => areset );
--zSinOMyBottom_uid57_fpTanTest(BITSELECT,56)@18
zSinOMyBottom_uid57_fpTanTest_in <= ld_oneMinusY_uid54_fpTanTest_q_to_zSinOMyBottom_uid57_fpTanTest_a_q(64 downto 0);
zSinOMyBottom_uid57_fpTanTest_b <= zSinOMyBottom_uid57_fpTanTest_in(64 downto 0);
--reg_zSinOMyBottom_uid57_fpTanTest_0_to_zSin_uid59_fpTanTest_3(REG,683)@18
reg_zSinOMyBottom_uid57_fpTanTest_0_to_zSin_uid59_fpTanTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zSinOMyBottom_uid57_fpTanTest_0_to_zSin_uid59_fpTanTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zSinOMyBottom_uid57_fpTanTest_0_to_zSin_uid59_fpTanTest_3_q <= zSinOMyBottom_uid57_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--zSinYBottom_uid58_fpTanTest(BITSELECT,57)@18
zSinYBottom_uid58_fpTanTest_in <= ld_y_uid50_fpTanTest_b_to_cmpYToOneMinusY_uid56_fpTanTest_b_q(64 downto 0);
zSinYBottom_uid58_fpTanTest_b <= zSinYBottom_uid58_fpTanTest_in(64 downto 0);
--reg_zSinYBottom_uid58_fpTanTest_0_to_zSin_uid59_fpTanTest_2(REG,682)@18
reg_zSinYBottom_uid58_fpTanTest_0_to_zSin_uid59_fpTanTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zSinYBottom_uid58_fpTanTest_0_to_zSin_uid59_fpTanTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zSinYBottom_uid58_fpTanTest_0_to_zSin_uid59_fpTanTest_2_q <= zSinYBottom_uid58_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--reg_InvCmpYToOneMinusY_uid60_fpTanTest_0_to_zCos_uid63_fpTanTest_1(REG,718)@18
reg_InvCmpYToOneMinusY_uid60_fpTanTest_0_to_zCos_uid63_fpTanTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvCmpYToOneMinusY_uid60_fpTanTest_0_to_zCos_uid63_fpTanTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvCmpYToOneMinusY_uid60_fpTanTest_0_to_zCos_uid63_fpTanTest_1_q <= InvCmpYToOneMinusY_uid60_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--zCos_uid63_fpTanTest(MUX,62)@19
zCos_uid63_fpTanTest_s <= reg_InvCmpYToOneMinusY_uid60_fpTanTest_0_to_zCos_uid63_fpTanTest_1_q;
zCos_uid63_fpTanTest: PROCESS (zCos_uid63_fpTanTest_s, en, reg_zSinYBottom_uid58_fpTanTest_0_to_zSin_uid59_fpTanTest_2_q, reg_zSinOMyBottom_uid57_fpTanTest_0_to_zSin_uid59_fpTanTest_3_q)
BEGIN
CASE zCos_uid63_fpTanTest_s IS
WHEN "0" => zCos_uid63_fpTanTest_q <= reg_zSinYBottom_uid58_fpTanTest_0_to_zSin_uid59_fpTanTest_2_q;
WHEN "1" => zCos_uid63_fpTanTest_q <= reg_zSinOMyBottom_uid57_fpTanTest_0_to_zSin_uid59_fpTanTest_3_q;
WHEN OTHERS => zCos_uid63_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--addr_uid82_fpTanTest(BITSELECT,81)@19
addr_uid82_fpTanTest_in <= zCos_uid63_fpTanTest_q;
addr_uid82_fpTanTest_b <= addr_uid82_fpTanTest_in(64 downto 57);
--reg_addr_uid82_fpTanTest_0_to_memoryC2_uid397_tableGencosPiZ_lutmem_0(REG,734)@19
reg_addr_uid82_fpTanTest_0_to_memoryC2_uid397_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid82_fpTanTest_0_to_memoryC2_uid397_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid82_fpTanTest_0_to_memoryC2_uid397_tableGencosPiZ_lutmem_0_q <= addr_uid82_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid397_tableGencosPiZ_lutmem(DUALMEM,644)@20
memoryC2_uid397_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC2_uid397_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC2_uid397_tableGencosPiZ_lutmem_ab <= reg_addr_uid82_fpTanTest_0_to_memoryC2_uid397_tableGencosPiZ_lutmem_0_q;
memoryC2_uid397_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_tan_s5_memoryC2_uid397_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid397_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid397_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid397_tableGencosPiZ_lutmem_iq,
address_a => memoryC2_uid397_tableGencosPiZ_lutmem_aa,
data_a => memoryC2_uid397_tableGencosPiZ_lutmem_ia
);
memoryC2_uid397_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC2_uid397_tableGencosPiZ_lutmem_q <= memoryC2_uid397_tableGencosPiZ_lutmem_iq(12 downto 0);
--reg_memoryC2_uid397_tableGencosPiZ_lutmem_0_to_prodXY_uid592_pT1_uid413_polyEvalcosPiZ_1(REG,736)@22
reg_memoryC2_uid397_tableGencosPiZ_lutmem_0_to_prodXY_uid592_pT1_uid413_polyEvalcosPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid397_tableGencosPiZ_lutmem_0_to_prodXY_uid592_pT1_uid413_polyEvalcosPiZ_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid397_tableGencosPiZ_lutmem_0_to_prodXY_uid592_pT1_uid413_polyEvalcosPiZ_1_q <= memoryC2_uid397_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPcosPiZ_uid86_fpTanTest(BITSELECT,85)@19
zPcosPiZ_uid86_fpTanTest_in <= zCos_uid63_fpTanTest_q(56 downto 0);
zPcosPiZ_uid86_fpTanTest_b <= zPcosPiZ_uid86_fpTanTest_in(56 downto 42);
--yT1_uid412_polyEvalcosPiZ(BITSELECT,411)@19
yT1_uid412_polyEvalcosPiZ_in <= zPcosPiZ_uid86_fpTanTest_b;
yT1_uid412_polyEvalcosPiZ_b <= yT1_uid412_polyEvalcosPiZ_in(14 downto 2);
--reg_yT1_uid412_polyEvalcosPiZ_0_to_prodXY_uid592_pT1_uid413_polyEvalcosPiZ_0(REG,735)@19
reg_yT1_uid412_polyEvalcosPiZ_0_to_prodXY_uid592_pT1_uid413_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid412_polyEvalcosPiZ_0_to_prodXY_uid592_pT1_uid413_polyEvalcosPiZ_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid412_polyEvalcosPiZ_0_to_prodXY_uid592_pT1_uid413_polyEvalcosPiZ_0_q <= yT1_uid412_polyEvalcosPiZ_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid412_polyEvalcosPiZ_0_to_prodXY_uid592_pT1_uid413_polyEvalcosPiZ_0_q_to_prodXY_uid592_pT1_uid413_polyEvalcosPiZ_a_inputreg(DELAY,1766)
ld_reg_yT1_uid412_polyEvalcosPiZ_0_to_prodXY_uid592_pT1_uid413_polyEvalcosPiZ_0_q_to_prodXY_uid592_pT1_uid413_polyEvalcosPiZ_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => reg_yT1_uid412_polyEvalcosPiZ_0_to_prodXY_uid592_pT1_uid413_polyEvalcosPiZ_0_q, xout => ld_reg_yT1_uid412_polyEvalcosPiZ_0_to_prodXY_uid592_pT1_uid413_polyEvalcosPiZ_0_q_to_prodXY_uid592_pT1_uid413_polyEvalcosPiZ_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yT1_uid412_polyEvalcosPiZ_0_to_prodXY_uid592_pT1_uid413_polyEvalcosPiZ_0_q_to_prodXY_uid592_pT1_uid413_polyEvalcosPiZ_a(DELAY,1346)@20
ld_reg_yT1_uid412_polyEvalcosPiZ_0_to_prodXY_uid592_pT1_uid413_polyEvalcosPiZ_0_q_to_prodXY_uid592_pT1_uid413_polyEvalcosPiZ_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_reg_yT1_uid412_polyEvalcosPiZ_0_to_prodXY_uid592_pT1_uid413_polyEvalcosPiZ_0_q_to_prodXY_uid592_pT1_uid413_polyEvalcosPiZ_a_inputreg_q, xout => ld_reg_yT1_uid412_polyEvalcosPiZ_0_to_prodXY_uid592_pT1_uid413_polyEvalcosPiZ_0_q_to_prodXY_uid592_pT1_uid413_polyEvalcosPiZ_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid592_pT1_uid413_polyEvalcosPiZ(MULT,591)@23
prodXY_uid592_pT1_uid413_polyEvalcosPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid592_pT1_uid413_polyEvalcosPiZ_a),14)) * SIGNED(prodXY_uid592_pT1_uid413_polyEvalcosPiZ_b);
prodXY_uid592_pT1_uid413_polyEvalcosPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid592_pT1_uid413_polyEvalcosPiZ_a <= (others => '0');
prodXY_uid592_pT1_uid413_polyEvalcosPiZ_b <= (others => '0');
prodXY_uid592_pT1_uid413_polyEvalcosPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid592_pT1_uid413_polyEvalcosPiZ_a <= ld_reg_yT1_uid412_polyEvalcosPiZ_0_to_prodXY_uid592_pT1_uid413_polyEvalcosPiZ_0_q_to_prodXY_uid592_pT1_uid413_polyEvalcosPiZ_a_q;
prodXY_uid592_pT1_uid413_polyEvalcosPiZ_b <= reg_memoryC2_uid397_tableGencosPiZ_lutmem_0_to_prodXY_uid592_pT1_uid413_polyEvalcosPiZ_1_q;
prodXY_uid592_pT1_uid413_polyEvalcosPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid592_pT1_uid413_polyEvalcosPiZ_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid592_pT1_uid413_polyEvalcosPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid592_pT1_uid413_polyEvalcosPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid592_pT1_uid413_polyEvalcosPiZ_q <= prodXY_uid592_pT1_uid413_polyEvalcosPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid593_pT1_uid413_polyEvalcosPiZ(BITSELECT,592)@26
prodXYTruncFR_uid593_pT1_uid413_polyEvalcosPiZ_in <= prodXY_uid592_pT1_uid413_polyEvalcosPiZ_q;
prodXYTruncFR_uid593_pT1_uid413_polyEvalcosPiZ_b <= prodXYTruncFR_uid593_pT1_uid413_polyEvalcosPiZ_in(25 downto 12);
--highBBits_uid415_polyEvalcosPiZ(BITSELECT,414)@26
highBBits_uid415_polyEvalcosPiZ_in <= prodXYTruncFR_uid593_pT1_uid413_polyEvalcosPiZ_b;
highBBits_uid415_polyEvalcosPiZ_b <= highBBits_uid415_polyEvalcosPiZ_in(13 downto 1);
--ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC1_uid395_tableGencosPiZ_lutmem_0_a(DELAY,1491)@19
ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC1_uid395_tableGencosPiZ_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addr_uid82_fpTanTest_b, xout => ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC1_uid395_tableGencosPiZ_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid82_fpTanTest_0_to_memoryC1_uid395_tableGencosPiZ_lutmem_0(REG,737)@22
reg_addr_uid82_fpTanTest_0_to_memoryC1_uid395_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid82_fpTanTest_0_to_memoryC1_uid395_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid82_fpTanTest_0_to_memoryC1_uid395_tableGencosPiZ_lutmem_0_q <= ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC1_uid395_tableGencosPiZ_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid395_tableGencosPiZ_lutmem(DUALMEM,643)@23
memoryC1_uid395_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC1_uid395_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC1_uid395_tableGencosPiZ_lutmem_ab <= reg_addr_uid82_fpTanTest_0_to_memoryC1_uid395_tableGencosPiZ_lutmem_0_q;
memoryC1_uid395_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_tan_s5_memoryC1_uid395_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid395_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid395_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid395_tableGencosPiZ_lutmem_iq,
address_a => memoryC1_uid395_tableGencosPiZ_lutmem_aa,
data_a => memoryC1_uid395_tableGencosPiZ_lutmem_ia
);
memoryC1_uid395_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC1_uid395_tableGencosPiZ_lutmem_q <= memoryC1_uid395_tableGencosPiZ_lutmem_iq(20 downto 0);
--reg_memoryC1_uid395_tableGencosPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalcosPiZ_0(REG,738)@25
reg_memoryC1_uid395_tableGencosPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid395_tableGencosPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalcosPiZ_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid395_tableGencosPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalcosPiZ_0_q <= memoryC1_uid395_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid416_polyEvalcosPiZ(ADD,415)@26
sumAHighB_uid416_polyEvalcosPiZ_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid395_tableGencosPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalcosPiZ_0_q(20)) & reg_memoryC1_uid395_tableGencosPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalcosPiZ_0_q);
sumAHighB_uid416_polyEvalcosPiZ_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid415_polyEvalcosPiZ_b(12)) & highBBits_uid415_polyEvalcosPiZ_b);
sumAHighB_uid416_polyEvalcosPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid416_polyEvalcosPiZ_a) + SIGNED(sumAHighB_uid416_polyEvalcosPiZ_b));
sumAHighB_uid416_polyEvalcosPiZ_q <= sumAHighB_uid416_polyEvalcosPiZ_o(21 downto 0);
--lowRangeB_uid414_polyEvalcosPiZ(BITSELECT,413)@26
lowRangeB_uid414_polyEvalcosPiZ_in <= prodXYTruncFR_uid593_pT1_uid413_polyEvalcosPiZ_b(0 downto 0);
lowRangeB_uid414_polyEvalcosPiZ_b <= lowRangeB_uid414_polyEvalcosPiZ_in(0 downto 0);
--s1_uid414_uid417_polyEvalcosPiZ(BITJOIN,416)@26
s1_uid414_uid417_polyEvalcosPiZ_q <= sumAHighB_uid416_polyEvalcosPiZ_q & lowRangeB_uid414_polyEvalcosPiZ_b;
--reg_s1_uid414_uid417_polyEvalcosPiZ_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_1(REG,740)@26
reg_s1_uid414_uid417_polyEvalcosPiZ_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid414_uid417_polyEvalcosPiZ_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid414_uid417_polyEvalcosPiZ_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_1_q <= s1_uid414_uid417_polyEvalcosPiZ_q;
END IF;
END IF;
END PROCESS;
--ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_nor(LOGICAL,1831)
ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_nor_a <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_notEnable_q;
ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_nor_b <= ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_sticky_ena_q;
ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_nor_q <= not (ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_nor_a or ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_nor_b);
--ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_mem_top(CONSTANT,1774)
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_mem_top_q <= "0100";
--ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_cmp(LOGICAL,1775)
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_cmp_a <= ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_mem_top_q;
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdmux_q);
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_cmp_q <= "1" when ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_cmp_a = ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_cmp_b else "0";
--ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_cmpReg(REG,1776)
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_cmpReg_q <= ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_sticky_ena(REG,1832)
ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_nor_q = "1") THEN
ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_sticky_ena_q <= ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_enaAnd(LOGICAL,1833)
ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_enaAnd_a <= ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_sticky_ena_q;
ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_enaAnd_b <= en;
ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_enaAnd_q <= ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_enaAnd_a and ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_enaAnd_b;
--ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_inputreg(DELAY,1821)
ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => zPcosPiZ_uid86_fpTanTest_b, xout => ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdcnt(COUNTER,1770)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdcnt_i = 3 THEN
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdcnt_eq = '1') THEN
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdcnt_i <= ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdcnt_i - 4;
ELSE
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdcnt_i <= ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdcnt_i,3));
--ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdreg(REG,1771)
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdreg_q <= ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdmux(MUX,1772)
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdmux_s <= en;
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdmux: PROCESS (ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdmux_s, ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdreg_q, ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdmux_s IS
WHEN "0" => ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdmux_q <= ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdreg_q;
WHEN "1" => ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdmux_q <= ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_replace_mem(DUALMEM,1822)
ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_replace_mem_ia <= ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_inputreg_q;
ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_replace_mem_aa <= ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdreg_q;
ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_replace_mem_ab <= ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdmux_q;
ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_replace_mem_iq,
address_a => ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_replace_mem_aa,
data_a => ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_replace_mem_ia
);
ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_replace_mem_reset0 <= areset;
ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_replace_mem_q <= ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_replace_mem_iq(14 downto 0);
--reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0(REG,739)@26
reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_q <= ld_zPcosPiZ_uid86_fpTanTest_b_to_reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid595_pT2_uid419_polyEvalcosPiZ(MULT,594)@27
prodXY_uid595_pT2_uid419_polyEvalcosPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid595_pT2_uid419_polyEvalcosPiZ_a),16)) * SIGNED(prodXY_uid595_pT2_uid419_polyEvalcosPiZ_b);
prodXY_uid595_pT2_uid419_polyEvalcosPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid595_pT2_uid419_polyEvalcosPiZ_a <= (others => '0');
prodXY_uid595_pT2_uid419_polyEvalcosPiZ_b <= (others => '0');
prodXY_uid595_pT2_uid419_polyEvalcosPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid595_pT2_uid419_polyEvalcosPiZ_a <= reg_zPcosPiZ_uid86_fpTanTest_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_0_q;
prodXY_uid595_pT2_uid419_polyEvalcosPiZ_b <= reg_s1_uid414_uid417_polyEvalcosPiZ_0_to_prodXY_uid595_pT2_uid419_polyEvalcosPiZ_1_q;
prodXY_uid595_pT2_uid419_polyEvalcosPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid595_pT2_uid419_polyEvalcosPiZ_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid595_pT2_uid419_polyEvalcosPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid595_pT2_uid419_polyEvalcosPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid595_pT2_uid419_polyEvalcosPiZ_q <= prodXY_uid595_pT2_uid419_polyEvalcosPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid596_pT2_uid419_polyEvalcosPiZ(BITSELECT,595)@30
prodXYTruncFR_uid596_pT2_uid419_polyEvalcosPiZ_in <= prodXY_uid595_pT2_uid419_polyEvalcosPiZ_q;
prodXYTruncFR_uid596_pT2_uid419_polyEvalcosPiZ_b <= prodXYTruncFR_uid596_pT2_uid419_polyEvalcosPiZ_in(37 downto 14);
--highBBits_uid421_polyEvalcosPiZ(BITSELECT,420)@30
highBBits_uid421_polyEvalcosPiZ_in <= prodXYTruncFR_uid596_pT2_uid419_polyEvalcosPiZ_b;
highBBits_uid421_polyEvalcosPiZ_b <= highBBits_uid421_polyEvalcosPiZ_in(23 downto 2);
--ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_nor(LOGICAL,1844)
ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_nor_a <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_notEnable_q;
ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_nor_b <= ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_nor_q <= not (ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_nor_a or ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_nor_b);
--ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_sticky_ena(REG,1845)
ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_nor_q = "1") THEN
ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_sticky_ena_q <= ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_enaAnd(LOGICAL,1846)
ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_enaAnd_a <= ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_enaAnd_b <= en;
ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_enaAnd_q <= ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_enaAnd_a and ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_enaAnd_b;
--ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_inputreg(DELAY,1834)
ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addr_uid82_fpTanTest_b, xout => ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_replace_mem(DUALMEM,1835)
ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_replace_mem_ia <= ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_inputreg_q;
ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_replace_mem_aa <= ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdreg_q;
ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_replace_mem_ab <= ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdmux_q;
ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_replace_mem_iq,
address_a => ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_replace_mem_aa,
data_a => ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_replace_mem_ia
);
ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_replace_mem_q <= ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0(REG,741)@26
reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_q <= ld_addr_uid82_fpTanTest_b_to_reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid393_tableGencosPiZ_lutmem(DUALMEM,642)@27
memoryC0_uid393_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC0_uid393_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC0_uid393_tableGencosPiZ_lutmem_ab <= reg_addr_uid82_fpTanTest_0_to_memoryC0_uid393_tableGencosPiZ_lutmem_0_q;
memoryC0_uid393_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_tan_s5_memoryC0_uid393_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid393_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid393_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid393_tableGencosPiZ_lutmem_iq,
address_a => memoryC0_uid393_tableGencosPiZ_lutmem_aa,
data_a => memoryC0_uid393_tableGencosPiZ_lutmem_ia
);
memoryC0_uid393_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC0_uid393_tableGencosPiZ_lutmem_q <= memoryC0_uid393_tableGencosPiZ_lutmem_iq(29 downto 0);
--reg_memoryC0_uid393_tableGencosPiZ_lutmem_0_to_sumAHighB_uid422_polyEvalcosPiZ_0(REG,742)@29
reg_memoryC0_uid393_tableGencosPiZ_lutmem_0_to_sumAHighB_uid422_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid393_tableGencosPiZ_lutmem_0_to_sumAHighB_uid422_polyEvalcosPiZ_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid393_tableGencosPiZ_lutmem_0_to_sumAHighB_uid422_polyEvalcosPiZ_0_q <= memoryC0_uid393_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid422_polyEvalcosPiZ(ADD,421)@30
sumAHighB_uid422_polyEvalcosPiZ_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid393_tableGencosPiZ_lutmem_0_to_sumAHighB_uid422_polyEvalcosPiZ_0_q(29)) & reg_memoryC0_uid393_tableGencosPiZ_lutmem_0_to_sumAHighB_uid422_polyEvalcosPiZ_0_q);
sumAHighB_uid422_polyEvalcosPiZ_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid421_polyEvalcosPiZ_b(21)) & highBBits_uid421_polyEvalcosPiZ_b);
sumAHighB_uid422_polyEvalcosPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid422_polyEvalcosPiZ_a) + SIGNED(sumAHighB_uid422_polyEvalcosPiZ_b));
sumAHighB_uid422_polyEvalcosPiZ_q <= sumAHighB_uid422_polyEvalcosPiZ_o(30 downto 0);
--lowRangeB_uid420_polyEvalcosPiZ(BITSELECT,419)@30
lowRangeB_uid420_polyEvalcosPiZ_in <= prodXYTruncFR_uid596_pT2_uid419_polyEvalcosPiZ_b(1 downto 0);
lowRangeB_uid420_polyEvalcosPiZ_b <= lowRangeB_uid420_polyEvalcosPiZ_in(1 downto 0);
--s2_uid420_uid423_polyEvalcosPiZ(BITJOIN,422)@30
s2_uid420_uid423_polyEvalcosPiZ_q <= sumAHighB_uid422_polyEvalcosPiZ_q & lowRangeB_uid420_polyEvalcosPiZ_b;
--polyEvalSigcosPiZ_uid88_fpTanTest(BITSELECT,87)@30
polyEvalSigcosPiZ_uid88_fpTanTest_in <= s2_uid420_uid423_polyEvalcosPiZ_q(30 downto 0);
polyEvalSigcosPiZ_uid88_fpTanTest_b <= polyEvalSigcosPiZ_uid88_fpTanTest_in(30 downto 5);
--reg_polyEvalSigcosPiZ_uid88_fpTanTest_0_to_mulCos_uid104_fpTanTest_1(REG,744)@30
reg_polyEvalSigcosPiZ_uid88_fpTanTest_0_to_mulCos_uid104_fpTanTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_polyEvalSigcosPiZ_uid88_fpTanTest_0_to_mulCos_uid104_fpTanTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_polyEvalSigcosPiZ_uid88_fpTanTest_0_to_mulCos_uid104_fpTanTest_1_q <= polyEvalSigcosPiZ_uid88_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_nor(LOGICAL,1857)
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_nor_a <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_notEnable_q;
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_nor_b <= ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_sticky_ena_q;
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_nor_q <= not (ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_nor_a or ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_nor_b);
--ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_mem_top(CONSTANT,1853)
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_mem_top_q <= "010";
--ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_cmp(LOGICAL,1854)
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_cmp_a <= ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_mem_top_q;
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdmux_q);
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_cmp_q <= "1" when ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_cmp_a = ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_cmp_b else "0";
--ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_cmpReg(REG,1855)
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_cmpReg_q <= ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_sticky_ena(REG,1858)
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_nor_q = "1") THEN
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_sticky_ena_q <= ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_enaAnd(LOGICAL,1859)
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_enaAnd_a <= ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_sticky_ena_q;
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_enaAnd_b <= en;
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_enaAnd_q <= ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_enaAnd_a and ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_enaAnd_b;
--LeftShiftStage263dto0_uid382_alignedZCos_uid69_fpTanTest(BITSELECT,381)@25
LeftShiftStage263dto0_uid382_alignedZCos_uid69_fpTanTest_in <= leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_q(63 downto 0);
LeftShiftStage263dto0_uid382_alignedZCos_uid69_fpTanTest_b <= LeftShiftStage263dto0_uid382_alignedZCos_uid69_fpTanTest_in(63 downto 0);
--leftShiftStage3Idx1_uid383_alignedZCos_uid69_fpTanTest(BITJOIN,382)@25
leftShiftStage3Idx1_uid383_alignedZCos_uid69_fpTanTest_q <= LeftShiftStage263dto0_uid382_alignedZCos_uid69_fpTanTest_b & GND_q;
--cstZwShiftPwFRR_uid35_fpTanTest(CONSTANT,34)
cstZwShiftPwFRR_uid35_fpTanTest_q <= "00000000000000000000000000000000000000000000000000000000000000000";
--ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_nor(LOGICAL,1711)
ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_nor_a <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_notEnable_q;
ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_nor_b <= ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_sticky_ena_q;
ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_nor_q <= not (ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_nor_a or ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_nor_b);
--ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_sticky_ena(REG,1712)
ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_nor_q = "1") THEN
ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_sticky_ena_q <= ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_enaAnd(LOGICAL,1713)
ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_enaAnd_a <= ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_sticky_ena_q;
ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_enaAnd_b <= en;
ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_enaAnd_q <= ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_enaAnd_a and ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_enaAnd_b;
--X32dto0_uid353_alignedZCos_uid69_fpTanTest(BITSELECT,352)@19
X32dto0_uid353_alignedZCos_uid69_fpTanTest_in <= zCos_uid63_fpTanTest_q(32 downto 0);
X32dto0_uid353_alignedZCos_uid69_fpTanTest_b <= X32dto0_uid353_alignedZCos_uid69_fpTanTest_in(32 downto 0);
--ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_inputreg(DELAY,1703)
ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => X32dto0_uid353_alignedZCos_uid69_fpTanTest_b, xout => ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_replace_mem(DUALMEM,1704)
ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_replace_mem_ia <= ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_inputreg_q;
ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_replace_mem_aa <= ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdreg_q;
ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_replace_mem_ab <= ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdmux_q;
ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 1,
numwords_a => 2,
width_b => 33,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_replace_mem_iq,
address_a => ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_replace_mem_aa,
data_a => ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_replace_mem_ia
);
ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_replace_mem_reset0 <= areset;
ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_replace_mem_q <= ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_replace_mem_iq(32 downto 0);
--zs_uid237_lzcZSin_uid65_fpTanTest(CONSTANT,236)
zs_uid237_lzcZSin_uid65_fpTanTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest(BITJOIN,353)@23
leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_q <= ld_X32dto0_uid353_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_b_replace_mem_q & zs_uid237_lzcZSin_uid65_fpTanTest_q;
--ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_nor(LOGICAL,1722)
ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_nor_a <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_notEnable_q;
ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_nor_b <= ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_sticky_ena_q;
ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_nor_q <= not (ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_nor_a or ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_nor_b);
--ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_sticky_ena(REG,1723)
ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_nor_q = "1") THEN
ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_sticky_ena_q <= ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_enaAnd(LOGICAL,1724)
ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_enaAnd_a <= ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_sticky_ena_q;
ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_enaAnd_b <= en;
ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_enaAnd_q <= ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_enaAnd_a and ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_enaAnd_b;
--ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_inputreg(DELAY,1714)
ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => zCos_uid63_fpTanTest_q, xout => ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_replace_mem(DUALMEM,1715)
ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_replace_mem_ia <= ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_inputreg_q;
ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_replace_mem_aa <= ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdreg_q;
ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_replace_mem_ab <= ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdmux_q;
ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 65,
widthad_a => 1,
numwords_a => 2,
width_b => 65,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_replace_mem_iq,
address_a => ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_replace_mem_aa,
data_a => ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_replace_mem_ia
);
ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_replace_mem_reset0 <= areset;
ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_replace_mem_q <= ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_replace_mem_iq(64 downto 0);
--zs_uid229_lzcZSin_uid65_fpTanTest(CONSTANT,228)
zs_uid229_lzcZSin_uid65_fpTanTest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--rVStage_uid309_lzcZCos_uid68_fpTanTest(BITSELECT,308)@19
rVStage_uid309_lzcZCos_uid68_fpTanTest_in <= zCos_uid63_fpTanTest_q;
rVStage_uid309_lzcZCos_uid68_fpTanTest_b <= rVStage_uid309_lzcZCos_uid68_fpTanTest_in(64 downto 1);
--vCount_uid310_lzcZCos_uid68_fpTanTest(LOGICAL,309)@19
vCount_uid310_lzcZCos_uid68_fpTanTest_a <= rVStage_uid309_lzcZCos_uid68_fpTanTest_b;
vCount_uid310_lzcZCos_uid68_fpTanTest_b <= zs_uid229_lzcZSin_uid65_fpTanTest_q;
vCount_uid310_lzcZCos_uid68_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid310_lzcZCos_uid68_fpTanTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid310_lzcZCos_uid68_fpTanTest_a = vCount_uid310_lzcZCos_uid68_fpTanTest_b) THEN
vCount_uid310_lzcZCos_uid68_fpTanTest_q <= "1";
ELSE
vCount_uid310_lzcZCos_uid68_fpTanTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid310_lzcZCos_uid68_fpTanTest_q_to_r_uid349_lzcZCos_uid68_fpTanTest_g(DELAY,1101)@20
ld_vCount_uid310_lzcZCos_uid68_fpTanTest_q_to_r_uid349_lzcZCos_uid68_fpTanTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => vCount_uid310_lzcZCos_uid68_fpTanTest_q, xout => ld_vCount_uid310_lzcZCos_uid68_fpTanTest_q_to_r_uid349_lzcZCos_uid68_fpTanTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid312_lzcZCos_uid68_fpTanTest(BITSELECT,311)@19
vStage_uid312_lzcZCos_uid68_fpTanTest_in <= zCos_uid63_fpTanTest_q(0 downto 0);
vStage_uid312_lzcZCos_uid68_fpTanTest_b <= vStage_uid312_lzcZCos_uid68_fpTanTest_in(0 downto 0);
--ld_vStage_uid312_lzcZCos_uid68_fpTanTest_b_to_cStage_uid313_lzcZCos_uid68_fpTanTest_b(DELAY,1059)@19
ld_vStage_uid312_lzcZCos_uid68_fpTanTest_b_to_cStage_uid313_lzcZCos_uid68_fpTanTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vStage_uid312_lzcZCos_uid68_fpTanTest_b, xout => ld_vStage_uid312_lzcZCos_uid68_fpTanTest_b_to_cStage_uid313_lzcZCos_uid68_fpTanTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid232_lzcZSin_uid65_fpTanTest(CONSTANT,231)
mO_uid232_lzcZSin_uid65_fpTanTest_q <= "111111111111111111111111111111111111111111111111111111111111111";
--cStage_uid313_lzcZCos_uid68_fpTanTest(BITJOIN,312)@20
cStage_uid313_lzcZCos_uid68_fpTanTest_q <= ld_vStage_uid312_lzcZCos_uid68_fpTanTest_b_to_cStage_uid313_lzcZCos_uid68_fpTanTest_b_q & mO_uid232_lzcZSin_uid65_fpTanTest_q;
--ld_rVStage_uid309_lzcZCos_uid68_fpTanTest_b_to_vStagei_uid315_lzcZCos_uid68_fpTanTest_c(DELAY,1061)@19
ld_rVStage_uid309_lzcZCos_uid68_fpTanTest_b_to_vStagei_uid315_lzcZCos_uid68_fpTanTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid309_lzcZCos_uid68_fpTanTest_b, xout => ld_rVStage_uid309_lzcZCos_uid68_fpTanTest_b_to_vStagei_uid315_lzcZCos_uid68_fpTanTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid315_lzcZCos_uid68_fpTanTest(MUX,314)@20
vStagei_uid315_lzcZCos_uid68_fpTanTest_s <= vCount_uid310_lzcZCos_uid68_fpTanTest_q;
vStagei_uid315_lzcZCos_uid68_fpTanTest: PROCESS (vStagei_uid315_lzcZCos_uid68_fpTanTest_s, en, ld_rVStage_uid309_lzcZCos_uid68_fpTanTest_b_to_vStagei_uid315_lzcZCos_uid68_fpTanTest_c_q, cStage_uid313_lzcZCos_uid68_fpTanTest_q)
BEGIN
CASE vStagei_uid315_lzcZCos_uid68_fpTanTest_s IS
WHEN "0" => vStagei_uid315_lzcZCos_uid68_fpTanTest_q <= ld_rVStage_uid309_lzcZCos_uid68_fpTanTest_b_to_vStagei_uid315_lzcZCos_uid68_fpTanTest_c_q;
WHEN "1" => vStagei_uid315_lzcZCos_uid68_fpTanTest_q <= cStage_uid313_lzcZCos_uid68_fpTanTest_q;
WHEN OTHERS => vStagei_uid315_lzcZCos_uid68_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid317_lzcZCos_uid68_fpTanTest(BITSELECT,316)@20
rVStage_uid317_lzcZCos_uid68_fpTanTest_in <= vStagei_uid315_lzcZCos_uid68_fpTanTest_q;
rVStage_uid317_lzcZCos_uid68_fpTanTest_b <= rVStage_uid317_lzcZCos_uid68_fpTanTest_in(63 downto 32);
--vCount_uid318_lzcZCos_uid68_fpTanTest(LOGICAL,317)@20
vCount_uid318_lzcZCos_uid68_fpTanTest_a <= rVStage_uid317_lzcZCos_uid68_fpTanTest_b;
vCount_uid318_lzcZCos_uid68_fpTanTest_b <= zs_uid237_lzcZSin_uid65_fpTanTest_q;
vCount_uid318_lzcZCos_uid68_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid318_lzcZCos_uid68_fpTanTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid318_lzcZCos_uid68_fpTanTest_a = vCount_uid318_lzcZCos_uid68_fpTanTest_b) THEN
vCount_uid318_lzcZCos_uid68_fpTanTest_q <= "1";
ELSE
vCount_uid318_lzcZCos_uid68_fpTanTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid318_lzcZCos_uid68_fpTanTest_q_to_r_uid349_lzcZCos_uid68_fpTanTest_f(DELAY,1100)@21
ld_vCount_uid318_lzcZCos_uid68_fpTanTest_q_to_r_uid349_lzcZCos_uid68_fpTanTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid318_lzcZCos_uid68_fpTanTest_q, xout => ld_vCount_uid318_lzcZCos_uid68_fpTanTest_q_to_r_uid349_lzcZCos_uid68_fpTanTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid319_lzcZCos_uid68_fpTanTest(BITSELECT,318)@20
vStage_uid319_lzcZCos_uid68_fpTanTest_in <= vStagei_uid315_lzcZCos_uid68_fpTanTest_q(31 downto 0);
vStage_uid319_lzcZCos_uid68_fpTanTest_b <= vStage_uid319_lzcZCos_uid68_fpTanTest_in(31 downto 0);
--ld_vStage_uid319_lzcZCos_uid68_fpTanTest_b_to_vStagei_uid321_lzcZCos_uid68_fpTanTest_d(DELAY,1068)@20
ld_vStage_uid319_lzcZCos_uid68_fpTanTest_b_to_vStagei_uid321_lzcZCos_uid68_fpTanTest_d : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => vStage_uid319_lzcZCos_uid68_fpTanTest_b, xout => ld_vStage_uid319_lzcZCos_uid68_fpTanTest_b_to_vStagei_uid321_lzcZCos_uid68_fpTanTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_rVStage_uid317_lzcZCos_uid68_fpTanTest_b_to_vStagei_uid321_lzcZCos_uid68_fpTanTest_c(DELAY,1067)@20
ld_rVStage_uid317_lzcZCos_uid68_fpTanTest_b_to_vStagei_uid321_lzcZCos_uid68_fpTanTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid317_lzcZCos_uid68_fpTanTest_b, xout => ld_rVStage_uid317_lzcZCos_uid68_fpTanTest_b_to_vStagei_uid321_lzcZCos_uid68_fpTanTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid321_lzcZCos_uid68_fpTanTest(MUX,320)@21
vStagei_uid321_lzcZCos_uid68_fpTanTest_s <= vCount_uid318_lzcZCos_uid68_fpTanTest_q;
vStagei_uid321_lzcZCos_uid68_fpTanTest: PROCESS (vStagei_uid321_lzcZCos_uid68_fpTanTest_s, en, ld_rVStage_uid317_lzcZCos_uid68_fpTanTest_b_to_vStagei_uid321_lzcZCos_uid68_fpTanTest_c_q, ld_vStage_uid319_lzcZCos_uid68_fpTanTest_b_to_vStagei_uid321_lzcZCos_uid68_fpTanTest_d_q)
BEGIN
CASE vStagei_uid321_lzcZCos_uid68_fpTanTest_s IS
WHEN "0" => vStagei_uid321_lzcZCos_uid68_fpTanTest_q <= ld_rVStage_uid317_lzcZCos_uid68_fpTanTest_b_to_vStagei_uid321_lzcZCos_uid68_fpTanTest_c_q;
WHEN "1" => vStagei_uid321_lzcZCos_uid68_fpTanTest_q <= ld_vStage_uid319_lzcZCos_uid68_fpTanTest_b_to_vStagei_uid321_lzcZCos_uid68_fpTanTest_d_q;
WHEN OTHERS => vStagei_uid321_lzcZCos_uid68_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid323_lzcZCos_uid68_fpTanTest(BITSELECT,322)@21
rVStage_uid323_lzcZCos_uid68_fpTanTest_in <= vStagei_uid321_lzcZCos_uid68_fpTanTest_q;
rVStage_uid323_lzcZCos_uid68_fpTanTest_b <= rVStage_uid323_lzcZCos_uid68_fpTanTest_in(31 downto 16);
--vCount_uid324_lzcZCos_uid68_fpTanTest(LOGICAL,323)@21
vCount_uid324_lzcZCos_uid68_fpTanTest_a <= rVStage_uid323_lzcZCos_uid68_fpTanTest_b;
vCount_uid324_lzcZCos_uid68_fpTanTest_b <= zs_uid243_lzcZSin_uid65_fpTanTest_q;
vCount_uid324_lzcZCos_uid68_fpTanTest_q <= "1" when vCount_uid324_lzcZCos_uid68_fpTanTest_a = vCount_uid324_lzcZCos_uid68_fpTanTest_b else "0";
--reg_vCount_uid324_lzcZCos_uid68_fpTanTest_0_to_r_uid349_lzcZCos_uid68_fpTanTest_4(REG,726)@21
reg_vCount_uid324_lzcZCos_uid68_fpTanTest_0_to_r_uid349_lzcZCos_uid68_fpTanTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid324_lzcZCos_uid68_fpTanTest_0_to_r_uid349_lzcZCos_uid68_fpTanTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid324_lzcZCos_uid68_fpTanTest_0_to_r_uid349_lzcZCos_uid68_fpTanTest_4_q <= vCount_uid324_lzcZCos_uid68_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid324_lzcZCos_uid68_fpTanTest_0_to_r_uid349_lzcZCos_uid68_fpTanTest_4_q_to_r_uid349_lzcZCos_uid68_fpTanTest_e(DELAY,1099)@22
ld_reg_vCount_uid324_lzcZCos_uid68_fpTanTest_0_to_r_uid349_lzcZCos_uid68_fpTanTest_4_q_to_r_uid349_lzcZCos_uid68_fpTanTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid324_lzcZCos_uid68_fpTanTest_0_to_r_uid349_lzcZCos_uid68_fpTanTest_4_q, xout => ld_reg_vCount_uid324_lzcZCos_uid68_fpTanTest_0_to_r_uid349_lzcZCos_uid68_fpTanTest_4_q_to_r_uid349_lzcZCos_uid68_fpTanTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid325_lzcZCos_uid68_fpTanTest(BITSELECT,324)@21
vStage_uid325_lzcZCos_uid68_fpTanTest_in <= vStagei_uid321_lzcZCos_uid68_fpTanTest_q(15 downto 0);
vStage_uid325_lzcZCos_uid68_fpTanTest_b <= vStage_uid325_lzcZCos_uid68_fpTanTest_in(15 downto 0);
--vStagei_uid327_lzcZCos_uid68_fpTanTest(MUX,326)@21
vStagei_uid327_lzcZCos_uid68_fpTanTest_s <= vCount_uid324_lzcZCos_uid68_fpTanTest_q;
vStagei_uid327_lzcZCos_uid68_fpTanTest: PROCESS (vStagei_uid327_lzcZCos_uid68_fpTanTest_s, en, rVStage_uid323_lzcZCos_uid68_fpTanTest_b, vStage_uid325_lzcZCos_uid68_fpTanTest_b)
BEGIN
CASE vStagei_uid327_lzcZCos_uid68_fpTanTest_s IS
WHEN "0" => vStagei_uid327_lzcZCos_uid68_fpTanTest_q <= rVStage_uid323_lzcZCos_uid68_fpTanTest_b;
WHEN "1" => vStagei_uid327_lzcZCos_uid68_fpTanTest_q <= vStage_uid325_lzcZCos_uid68_fpTanTest_b;
WHEN OTHERS => vStagei_uid327_lzcZCos_uid68_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid329_lzcZCos_uid68_fpTanTest(BITSELECT,328)@21
rVStage_uid329_lzcZCos_uid68_fpTanTest_in <= vStagei_uid327_lzcZCos_uid68_fpTanTest_q;
rVStage_uid329_lzcZCos_uid68_fpTanTest_b <= rVStage_uid329_lzcZCos_uid68_fpTanTest_in(15 downto 8);
--reg_rVStage_uid329_lzcZCos_uid68_fpTanTest_0_to_vCount_uid330_lzcZCos_uid68_fpTanTest_1(REG,721)@21
reg_rVStage_uid329_lzcZCos_uid68_fpTanTest_0_to_vCount_uid330_lzcZCos_uid68_fpTanTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid329_lzcZCos_uid68_fpTanTest_0_to_vCount_uid330_lzcZCos_uid68_fpTanTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid329_lzcZCos_uid68_fpTanTest_0_to_vCount_uid330_lzcZCos_uid68_fpTanTest_1_q <= rVStage_uid329_lzcZCos_uid68_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid330_lzcZCos_uid68_fpTanTest(LOGICAL,329)@22
vCount_uid330_lzcZCos_uid68_fpTanTest_a <= reg_rVStage_uid329_lzcZCos_uid68_fpTanTest_0_to_vCount_uid330_lzcZCos_uid68_fpTanTest_1_q;
vCount_uid330_lzcZCos_uid68_fpTanTest_b <= cstAllZWE_uid8_fpTanTest_q;
vCount_uid330_lzcZCos_uid68_fpTanTest_q <= "1" when vCount_uid330_lzcZCos_uid68_fpTanTest_a = vCount_uid330_lzcZCos_uid68_fpTanTest_b else "0";
--ld_vCount_uid330_lzcZCos_uid68_fpTanTest_q_to_r_uid349_lzcZCos_uid68_fpTanTest_d(DELAY,1098)@22
ld_vCount_uid330_lzcZCos_uid68_fpTanTest_q_to_r_uid349_lzcZCos_uid68_fpTanTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid330_lzcZCos_uid68_fpTanTest_q, xout => ld_vCount_uid330_lzcZCos_uid68_fpTanTest_q_to_r_uid349_lzcZCos_uid68_fpTanTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid331_lzcZCos_uid68_fpTanTest(BITSELECT,330)@21
vStage_uid331_lzcZCos_uid68_fpTanTest_in <= vStagei_uid327_lzcZCos_uid68_fpTanTest_q(7 downto 0);
vStage_uid331_lzcZCos_uid68_fpTanTest_b <= vStage_uid331_lzcZCos_uid68_fpTanTest_in(7 downto 0);
--reg_vStage_uid331_lzcZCos_uid68_fpTanTest_0_to_vStagei_uid333_lzcZCos_uid68_fpTanTest_3(REG,723)@21
reg_vStage_uid331_lzcZCos_uid68_fpTanTest_0_to_vStagei_uid333_lzcZCos_uid68_fpTanTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid331_lzcZCos_uid68_fpTanTest_0_to_vStagei_uid333_lzcZCos_uid68_fpTanTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid331_lzcZCos_uid68_fpTanTest_0_to_vStagei_uid333_lzcZCos_uid68_fpTanTest_3_q <= vStage_uid331_lzcZCos_uid68_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid333_lzcZCos_uid68_fpTanTest(MUX,332)@22
vStagei_uid333_lzcZCos_uid68_fpTanTest_s <= vCount_uid330_lzcZCos_uid68_fpTanTest_q;
vStagei_uid333_lzcZCos_uid68_fpTanTest: PROCESS (vStagei_uid333_lzcZCos_uid68_fpTanTest_s, en, reg_rVStage_uid329_lzcZCos_uid68_fpTanTest_0_to_vCount_uid330_lzcZCos_uid68_fpTanTest_1_q, reg_vStage_uid331_lzcZCos_uid68_fpTanTest_0_to_vStagei_uid333_lzcZCos_uid68_fpTanTest_3_q)
BEGIN
CASE vStagei_uid333_lzcZCos_uid68_fpTanTest_s IS
WHEN "0" => vStagei_uid333_lzcZCos_uid68_fpTanTest_q <= reg_rVStage_uid329_lzcZCos_uid68_fpTanTest_0_to_vCount_uid330_lzcZCos_uid68_fpTanTest_1_q;
WHEN "1" => vStagei_uid333_lzcZCos_uid68_fpTanTest_q <= reg_vStage_uid331_lzcZCos_uid68_fpTanTest_0_to_vStagei_uid333_lzcZCos_uid68_fpTanTest_3_q;
WHEN OTHERS => vStagei_uid333_lzcZCos_uid68_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid335_lzcZCos_uid68_fpTanTest(BITSELECT,334)@22
rVStage_uid335_lzcZCos_uid68_fpTanTest_in <= vStagei_uid333_lzcZCos_uid68_fpTanTest_q;
rVStage_uid335_lzcZCos_uid68_fpTanTest_b <= rVStage_uid335_lzcZCos_uid68_fpTanTest_in(7 downto 4);
--vCount_uid336_lzcZCos_uid68_fpTanTest(LOGICAL,335)@22
vCount_uid336_lzcZCos_uid68_fpTanTest_a <= rVStage_uid335_lzcZCos_uid68_fpTanTest_b;
vCount_uid336_lzcZCos_uid68_fpTanTest_b <= leftShiftStage0Idx1Pad4_uid206_fxpX_uid48_fpTanTest_q;
vCount_uid336_lzcZCos_uid68_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid336_lzcZCos_uid68_fpTanTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid336_lzcZCos_uid68_fpTanTest_a = vCount_uid336_lzcZCos_uid68_fpTanTest_b) THEN
vCount_uid336_lzcZCos_uid68_fpTanTest_q <= "1";
ELSE
vCount_uid336_lzcZCos_uid68_fpTanTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid337_lzcZCos_uid68_fpTanTest(BITSELECT,336)@22
vStage_uid337_lzcZCos_uid68_fpTanTest_in <= vStagei_uid333_lzcZCos_uid68_fpTanTest_q(3 downto 0);
vStage_uid337_lzcZCos_uid68_fpTanTest_b <= vStage_uid337_lzcZCos_uid68_fpTanTest_in(3 downto 0);
--reg_vStage_uid337_lzcZCos_uid68_fpTanTest_0_to_vStagei_uid339_lzcZCos_uid68_fpTanTest_3(REG,725)@22
reg_vStage_uid337_lzcZCos_uid68_fpTanTest_0_to_vStagei_uid339_lzcZCos_uid68_fpTanTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid337_lzcZCos_uid68_fpTanTest_0_to_vStagei_uid339_lzcZCos_uid68_fpTanTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid337_lzcZCos_uid68_fpTanTest_0_to_vStagei_uid339_lzcZCos_uid68_fpTanTest_3_q <= vStage_uid337_lzcZCos_uid68_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid335_lzcZCos_uid68_fpTanTest_0_to_vStagei_uid339_lzcZCos_uid68_fpTanTest_2(REG,724)@22
reg_rVStage_uid335_lzcZCos_uid68_fpTanTest_0_to_vStagei_uid339_lzcZCos_uid68_fpTanTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid335_lzcZCos_uid68_fpTanTest_0_to_vStagei_uid339_lzcZCos_uid68_fpTanTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid335_lzcZCos_uid68_fpTanTest_0_to_vStagei_uid339_lzcZCos_uid68_fpTanTest_2_q <= rVStage_uid335_lzcZCos_uid68_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid339_lzcZCos_uid68_fpTanTest(MUX,338)@23
vStagei_uid339_lzcZCos_uid68_fpTanTest_s <= vCount_uid336_lzcZCos_uid68_fpTanTest_q;
vStagei_uid339_lzcZCos_uid68_fpTanTest: PROCESS (vStagei_uid339_lzcZCos_uid68_fpTanTest_s, en, reg_rVStage_uid335_lzcZCos_uid68_fpTanTest_0_to_vStagei_uid339_lzcZCos_uid68_fpTanTest_2_q, reg_vStage_uid337_lzcZCos_uid68_fpTanTest_0_to_vStagei_uid339_lzcZCos_uid68_fpTanTest_3_q)
BEGIN
CASE vStagei_uid339_lzcZCos_uid68_fpTanTest_s IS
WHEN "0" => vStagei_uid339_lzcZCos_uid68_fpTanTest_q <= reg_rVStage_uid335_lzcZCos_uid68_fpTanTest_0_to_vStagei_uid339_lzcZCos_uid68_fpTanTest_2_q;
WHEN "1" => vStagei_uid339_lzcZCos_uid68_fpTanTest_q <= reg_vStage_uid337_lzcZCos_uid68_fpTanTest_0_to_vStagei_uid339_lzcZCos_uid68_fpTanTest_3_q;
WHEN OTHERS => vStagei_uid339_lzcZCos_uid68_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid341_lzcZCos_uid68_fpTanTest(BITSELECT,340)@23
rVStage_uid341_lzcZCos_uid68_fpTanTest_in <= vStagei_uid339_lzcZCos_uid68_fpTanTest_q;
rVStage_uid341_lzcZCos_uid68_fpTanTest_b <= rVStage_uid341_lzcZCos_uid68_fpTanTest_in(3 downto 2);
--vCount_uid342_lzcZCos_uid68_fpTanTest(LOGICAL,341)@23
vCount_uid342_lzcZCos_uid68_fpTanTest_a <= rVStage_uid341_lzcZCos_uid68_fpTanTest_b;
vCount_uid342_lzcZCos_uid68_fpTanTest_b <= leftShiftStage1Idx2Pad2_uid220_fxpX_uid48_fpTanTest_q;
vCount_uid342_lzcZCos_uid68_fpTanTest_q <= "1" when vCount_uid342_lzcZCos_uid68_fpTanTest_a = vCount_uid342_lzcZCos_uid68_fpTanTest_b else "0";
--vStage_uid343_lzcZCos_uid68_fpTanTest(BITSELECT,342)@23
vStage_uid343_lzcZCos_uid68_fpTanTest_in <= vStagei_uid339_lzcZCos_uid68_fpTanTest_q(1 downto 0);
vStage_uid343_lzcZCos_uid68_fpTanTest_b <= vStage_uid343_lzcZCos_uid68_fpTanTest_in(1 downto 0);
--vStagei_uid345_lzcZCos_uid68_fpTanTest(MUX,344)@23
vStagei_uid345_lzcZCos_uid68_fpTanTest_s <= vCount_uid342_lzcZCos_uid68_fpTanTest_q;
vStagei_uid345_lzcZCos_uid68_fpTanTest: PROCESS (vStagei_uid345_lzcZCos_uid68_fpTanTest_s, en, rVStage_uid341_lzcZCos_uid68_fpTanTest_b, vStage_uid343_lzcZCos_uid68_fpTanTest_b)
BEGIN
CASE vStagei_uid345_lzcZCos_uid68_fpTanTest_s IS
WHEN "0" => vStagei_uid345_lzcZCos_uid68_fpTanTest_q <= rVStage_uid341_lzcZCos_uid68_fpTanTest_b;
WHEN "1" => vStagei_uid345_lzcZCos_uid68_fpTanTest_q <= vStage_uid343_lzcZCos_uid68_fpTanTest_b;
WHEN OTHERS => vStagei_uid345_lzcZCos_uid68_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid347_lzcZCos_uid68_fpTanTest(BITSELECT,346)@23
rVStage_uid347_lzcZCos_uid68_fpTanTest_in <= vStagei_uid345_lzcZCos_uid68_fpTanTest_q;
rVStage_uid347_lzcZCos_uid68_fpTanTest_b <= rVStage_uid347_lzcZCos_uid68_fpTanTest_in(1 downto 1);
--vCount_uid348_lzcZCos_uid68_fpTanTest(LOGICAL,347)@23
vCount_uid348_lzcZCos_uid68_fpTanTest_a <= rVStage_uid347_lzcZCos_uid68_fpTanTest_b;
vCount_uid348_lzcZCos_uid68_fpTanTest_b <= GND_q;
vCount_uid348_lzcZCos_uid68_fpTanTest_q <= "1" when vCount_uid348_lzcZCos_uid68_fpTanTest_a = vCount_uid348_lzcZCos_uid68_fpTanTest_b else "0";
--r_uid349_lzcZCos_uid68_fpTanTest(BITJOIN,348)@23
r_uid349_lzcZCos_uid68_fpTanTest_q <= ld_vCount_uid310_lzcZCos_uid68_fpTanTest_q_to_r_uid349_lzcZCos_uid68_fpTanTest_g_q & ld_vCount_uid318_lzcZCos_uid68_fpTanTest_q_to_r_uid349_lzcZCos_uid68_fpTanTest_f_q & ld_reg_vCount_uid324_lzcZCos_uid68_fpTanTest_0_to_r_uid349_lzcZCos_uid68_fpTanTest_4_q_to_r_uid349_lzcZCos_uid68_fpTanTest_e_q & ld_vCount_uid330_lzcZCos_uid68_fpTanTest_q_to_r_uid349_lzcZCos_uid68_fpTanTest_d_q & vCount_uid336_lzcZCos_uid68_fpTanTest_q & vCount_uid342_lzcZCos_uid68_fpTanTest_q & vCount_uid348_lzcZCos_uid68_fpTanTest_q;
--leftShiftStageSel6Dto5_uid357_alignedZCos_uid69_fpTanTest(BITSELECT,356)@23
leftShiftStageSel6Dto5_uid357_alignedZCos_uid69_fpTanTest_in <= r_uid349_lzcZCos_uid68_fpTanTest_q;
leftShiftStageSel6Dto5_uid357_alignedZCos_uid69_fpTanTest_b <= leftShiftStageSel6Dto5_uid357_alignedZCos_uid69_fpTanTest_in(6 downto 5);
--leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest(MUX,357)@23
leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_s <= leftShiftStageSel6Dto5_uid357_alignedZCos_uid69_fpTanTest_b;
leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest: PROCESS (leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_s, en, ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_replace_mem_q, leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_q, cstZwShiftPwFRR_uid35_fpTanTest_q, cstZwShiftPwFRR_uid35_fpTanTest_q)
BEGIN
CASE leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_s IS
WHEN "00" => leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_q <= ld_zCos_uid63_fpTanTest_q_to_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_q <= leftShiftStage0Idx1_uid354_alignedZCos_uid69_fpTanTest_q;
WHEN "10" => leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_q <= cstZwShiftPwFRR_uid35_fpTanTest_q;
WHEN "11" => leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_q <= cstZwShiftPwFRR_uid35_fpTanTest_q;
WHEN OTHERS => leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage040dto0_uid366_alignedZCos_uid69_fpTanTest(BITSELECT,365)@23
LeftShiftStage040dto0_uid366_alignedZCos_uid69_fpTanTest_in <= leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_q(40 downto 0);
LeftShiftStage040dto0_uid366_alignedZCos_uid69_fpTanTest_b <= LeftShiftStage040dto0_uid366_alignedZCos_uid69_fpTanTest_in(40 downto 0);
--leftShiftStage1Idx3_uid367_alignedZCos_uid69_fpTanTest(BITJOIN,366)@23
leftShiftStage1Idx3_uid367_alignedZCos_uid69_fpTanTest_q <= LeftShiftStage040dto0_uid366_alignedZCos_uid69_fpTanTest_b & leftShiftStage1Idx3Pad24_uid286_alignedZSin_uid66_fpTanTest_q;
--reg_leftShiftStage1Idx3_uid367_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_5(REG,731)@23
reg_leftShiftStage1Idx3_uid367_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid367_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid367_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_5_q <= leftShiftStage1Idx3_uid367_alignedZCos_uid69_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage048dto0_uid363_alignedZCos_uid69_fpTanTest(BITSELECT,362)@23
LeftShiftStage048dto0_uid363_alignedZCos_uid69_fpTanTest_in <= leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_q(48 downto 0);
LeftShiftStage048dto0_uid363_alignedZCos_uid69_fpTanTest_b <= LeftShiftStage048dto0_uid363_alignedZCos_uid69_fpTanTest_in(48 downto 0);
--leftShiftStage1Idx2_uid364_alignedZCos_uid69_fpTanTest(BITJOIN,363)@23
leftShiftStage1Idx2_uid364_alignedZCos_uid69_fpTanTest_q <= LeftShiftStage048dto0_uid363_alignedZCos_uid69_fpTanTest_b & zs_uid243_lzcZSin_uid65_fpTanTest_q;
--reg_leftShiftStage1Idx2_uid364_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_4(REG,730)@23
reg_leftShiftStage1Idx2_uid364_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid364_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid364_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_4_q <= leftShiftStage1Idx2_uid364_alignedZCos_uid69_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage056dto0_uid360_alignedZCos_uid69_fpTanTest(BITSELECT,359)@23
LeftShiftStage056dto0_uid360_alignedZCos_uid69_fpTanTest_in <= leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_q(56 downto 0);
LeftShiftStage056dto0_uid360_alignedZCos_uid69_fpTanTest_b <= LeftShiftStage056dto0_uid360_alignedZCos_uid69_fpTanTest_in(56 downto 0);
--leftShiftStage1Idx1_uid361_alignedZCos_uid69_fpTanTest(BITJOIN,360)@23
leftShiftStage1Idx1_uid361_alignedZCos_uid69_fpTanTest_q <= LeftShiftStage056dto0_uid360_alignedZCos_uid69_fpTanTest_b & cstAllZWE_uid8_fpTanTest_q;
--reg_leftShiftStage1Idx1_uid361_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_3(REG,729)@23
reg_leftShiftStage1Idx1_uid361_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid361_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid361_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_3_q <= leftShiftStage1Idx1_uid361_alignedZCos_uid69_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_2(REG,728)@23
reg_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_2_q <= leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid368_alignedZCos_uid69_fpTanTest(BITSELECT,367)@23
leftShiftStageSel4Dto3_uid368_alignedZCos_uid69_fpTanTest_in <= r_uid349_lzcZCos_uid68_fpTanTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid368_alignedZCos_uid69_fpTanTest_b <= leftShiftStageSel4Dto3_uid368_alignedZCos_uid69_fpTanTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid368_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_1(REG,727)@23
reg_leftShiftStageSel4Dto3_uid368_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid368_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid368_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_1_q <= leftShiftStageSel4Dto3_uid368_alignedZCos_uid69_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest(MUX,368)@24
leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_s <= reg_leftShiftStageSel4Dto3_uid368_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_1_q;
leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest: PROCESS (leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_s, en, reg_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_2_q, reg_leftShiftStage1Idx1_uid361_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_3_q, reg_leftShiftStage1Idx2_uid364_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_4_q, reg_leftShiftStage1Idx3_uid367_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_5_q)
BEGIN
CASE leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_s IS
WHEN "00" => leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_q <= reg_leftShiftStage0_uid358_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_2_q;
WHEN "01" => leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_q <= reg_leftShiftStage1Idx1_uid361_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_3_q;
WHEN "10" => leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_q <= reg_leftShiftStage1Idx2_uid364_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_4_q;
WHEN "11" => leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_q <= reg_leftShiftStage1Idx3_uid367_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_5_q;
WHEN OTHERS => leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid377_alignedZCos_uid69_fpTanTest(BITSELECT,376)@24
LeftShiftStage158dto0_uid377_alignedZCos_uid69_fpTanTest_in <= leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_q(58 downto 0);
LeftShiftStage158dto0_uid377_alignedZCos_uid69_fpTanTest_b <= LeftShiftStage158dto0_uid377_alignedZCos_uid69_fpTanTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid377_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage2Idx3_uid378_alignedZCos_uid69_fpTanTest_b(DELAY,1125)@24
ld_LeftShiftStage158dto0_uid377_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage2Idx3_uid378_alignedZCos_uid69_fpTanTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid377_alignedZCos_uid69_fpTanTest_b, xout => ld_LeftShiftStage158dto0_uid377_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage2Idx3_uid378_alignedZCos_uid69_fpTanTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid378_alignedZCos_uid69_fpTanTest(BITJOIN,377)@25
leftShiftStage2Idx3_uid378_alignedZCos_uid69_fpTanTest_q <= ld_LeftShiftStage158dto0_uid377_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage2Idx3_uid378_alignedZCos_uid69_fpTanTest_b_q & leftShiftStage2Idx3Pad6_uid297_alignedZSin_uid66_fpTanTest_q;
--LeftShiftStage160dto0_uid374_alignedZCos_uid69_fpTanTest(BITSELECT,373)@24
LeftShiftStage160dto0_uid374_alignedZCos_uid69_fpTanTest_in <= leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_q(60 downto 0);
LeftShiftStage160dto0_uid374_alignedZCos_uid69_fpTanTest_b <= LeftShiftStage160dto0_uid374_alignedZCos_uid69_fpTanTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid374_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage2Idx2_uid375_alignedZCos_uid69_fpTanTest_b(DELAY,1123)@24
ld_LeftShiftStage160dto0_uid374_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage2Idx2_uid375_alignedZCos_uid69_fpTanTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid374_alignedZCos_uid69_fpTanTest_b, xout => ld_LeftShiftStage160dto0_uid374_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage2Idx2_uid375_alignedZCos_uid69_fpTanTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid375_alignedZCos_uid69_fpTanTest(BITJOIN,374)@25
leftShiftStage2Idx2_uid375_alignedZCos_uid69_fpTanTest_q <= ld_LeftShiftStage160dto0_uid374_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage2Idx2_uid375_alignedZCos_uid69_fpTanTest_b_q & leftShiftStage0Idx1Pad4_uid206_fxpX_uid48_fpTanTest_q;
--LeftShiftStage162dto0_uid371_alignedZCos_uid69_fpTanTest(BITSELECT,370)@24
LeftShiftStage162dto0_uid371_alignedZCos_uid69_fpTanTest_in <= leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_q(62 downto 0);
LeftShiftStage162dto0_uid371_alignedZCos_uid69_fpTanTest_b <= LeftShiftStage162dto0_uid371_alignedZCos_uid69_fpTanTest_in(62 downto 0);
--ld_LeftShiftStage162dto0_uid371_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage2Idx1_uid372_alignedZCos_uid69_fpTanTest_b(DELAY,1121)@24
ld_LeftShiftStage162dto0_uid371_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage2Idx1_uid372_alignedZCos_uid69_fpTanTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage162dto0_uid371_alignedZCos_uid69_fpTanTest_b, xout => ld_LeftShiftStage162dto0_uid371_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage2Idx1_uid372_alignedZCos_uid69_fpTanTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid372_alignedZCos_uid69_fpTanTest(BITJOIN,371)@25
leftShiftStage2Idx1_uid372_alignedZCos_uid69_fpTanTest_q <= ld_LeftShiftStage162dto0_uid371_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage2Idx1_uid372_alignedZCos_uid69_fpTanTest_b_q & leftShiftStage1Idx2Pad2_uid220_fxpX_uid48_fpTanTest_q;
--reg_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_2(REG,733)@24
reg_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_2_q <= leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid379_alignedZCos_uid69_fpTanTest(BITSELECT,378)@23
leftShiftStageSel2Dto1_uid379_alignedZCos_uid69_fpTanTest_in <= r_uid349_lzcZCos_uid68_fpTanTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid379_alignedZCos_uid69_fpTanTest_b <= leftShiftStageSel2Dto1_uid379_alignedZCos_uid69_fpTanTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid379_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_1(REG,732)@23
reg_leftShiftStageSel2Dto1_uid379_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid379_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid379_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_1_q <= leftShiftStageSel2Dto1_uid379_alignedZCos_uid69_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel2Dto1_uid379_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_1_q_to_leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_b(DELAY,1127)@24
ld_reg_leftShiftStageSel2Dto1_uid379_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_1_q_to_leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid379_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid379_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_1_q_to_leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest(MUX,379)@25
leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_s <= ld_reg_leftShiftStageSel2Dto1_uid379_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_1_q_to_leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_b_q;
leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest: PROCESS (leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_s, en, reg_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_2_q, leftShiftStage2Idx1_uid372_alignedZCos_uid69_fpTanTest_q, leftShiftStage2Idx2_uid375_alignedZCos_uid69_fpTanTest_q, leftShiftStage2Idx3_uid378_alignedZCos_uid69_fpTanTest_q)
BEGIN
CASE leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_s IS
WHEN "00" => leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_q <= reg_leftShiftStage1_uid369_alignedZCos_uid69_fpTanTest_0_to_leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_2_q;
WHEN "01" => leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_q <= leftShiftStage2Idx1_uid372_alignedZCos_uid69_fpTanTest_q;
WHEN "10" => leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_q <= leftShiftStage2Idx2_uid375_alignedZCos_uid69_fpTanTest_q;
WHEN "11" => leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_q <= leftShiftStage2Idx3_uid378_alignedZCos_uid69_fpTanTest_q;
WHEN OTHERS => leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid384_alignedZCos_uid69_fpTanTest(BITSELECT,383)@23
leftShiftStageSel0Dto0_uid384_alignedZCos_uid69_fpTanTest_in <= r_uid349_lzcZCos_uid68_fpTanTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid384_alignedZCos_uid69_fpTanTest_b <= leftShiftStageSel0Dto0_uid384_alignedZCos_uid69_fpTanTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid384_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage3_uid385_alignedZCos_uid69_fpTanTest_b(DELAY,1135)@23
ld_leftShiftStageSel0Dto0_uid384_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage3_uid385_alignedZCos_uid69_fpTanTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid384_alignedZCos_uid69_fpTanTest_b, xout => ld_leftShiftStageSel0Dto0_uid384_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage3_uid385_alignedZCos_uid69_fpTanTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid385_alignedZCos_uid69_fpTanTest(MUX,384)@25
leftShiftStage3_uid385_alignedZCos_uid69_fpTanTest_s <= ld_leftShiftStageSel0Dto0_uid384_alignedZCos_uid69_fpTanTest_b_to_leftShiftStage3_uid385_alignedZCos_uid69_fpTanTest_b_q;
leftShiftStage3_uid385_alignedZCos_uid69_fpTanTest: PROCESS (leftShiftStage3_uid385_alignedZCos_uid69_fpTanTest_s, en, leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_q, leftShiftStage3Idx1_uid383_alignedZCos_uid69_fpTanTest_q)
BEGIN
CASE leftShiftStage3_uid385_alignedZCos_uid69_fpTanTest_s IS
WHEN "0" => leftShiftStage3_uid385_alignedZCos_uid69_fpTanTest_q <= leftShiftStage2_uid380_alignedZCos_uid69_fpTanTest_q;
WHEN "1" => leftShiftStage3_uid385_alignedZCos_uid69_fpTanTest_q <= leftShiftStage3Idx1_uid383_alignedZCos_uid69_fpTanTest_q;
WHEN OTHERS => leftShiftStage3_uid385_alignedZCos_uid69_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--pCos_uid76_fpTanTest(BITSELECT,75)@25
pCos_uid76_fpTanTest_in <= leftShiftStage3_uid385_alignedZCos_uid69_fpTanTest_q;
pCos_uid76_fpTanTest_b <= pCos_uid76_fpTanTest_in(64 downto 39);
--ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_inputreg(DELAY,1847)
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => pCos_uid76_fpTanTest_b, xout => ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdcnt(COUNTER,1849)
-- every=1, low=0, high=2, step=1, init=1
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdcnt_i = 1 THEN
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdcnt_eq = '1') THEN
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdcnt_i <= ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdcnt_i - 2;
ELSE
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdcnt_i <= ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdcnt_i,2));
--ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdreg(REG,1850)
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdreg_q <= ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdmux(MUX,1851)
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdmux_s <= en;
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdmux: PROCESS (ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdmux_s, ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdreg_q, ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdcnt_q)
BEGIN
CASE ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdmux_s IS
WHEN "0" => ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdmux_q <= ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdreg_q;
WHEN "1" => ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdmux_q <= ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_mem(DUALMEM,1848)
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_mem_ia <= ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_inputreg_q;
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_mem_aa <= ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdreg_q;
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_mem_ab <= ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_rdmux_q;
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 2,
numwords_a => 3,
width_b => 26,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_mem_iq,
address_a => ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_mem_aa,
data_a => ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_mem_ia
);
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_mem_reset0 <= areset;
ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_mem_q <= ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_mem_iq(25 downto 0);
--reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0(REG,743)@30
reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_q <= ld_pCos_uid76_fpTanTest_b_to_reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--mulCos_uid104_fpTanTest(MULT,103)@31
mulCos_uid104_fpTanTest_pr <= UNSIGNED(mulCos_uid104_fpTanTest_a) * UNSIGNED(mulCos_uid104_fpTanTest_b);
mulCos_uid104_fpTanTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulCos_uid104_fpTanTest_a <= (others => '0');
mulCos_uid104_fpTanTest_b <= (others => '0');
mulCos_uid104_fpTanTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulCos_uid104_fpTanTest_a <= reg_pCos_uid76_fpTanTest_0_to_mulCos_uid104_fpTanTest_0_q;
mulCos_uid104_fpTanTest_b <= reg_polyEvalSigcosPiZ_uid88_fpTanTest_0_to_mulCos_uid104_fpTanTest_1_q;
mulCos_uid104_fpTanTest_s1 <= STD_LOGIC_VECTOR(mulCos_uid104_fpTanTest_pr);
END IF;
END IF;
END PROCESS;
mulCos_uid104_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulCos_uid104_fpTanTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulCos_uid104_fpTanTest_q <= mulCos_uid104_fpTanTest_s1;
END IF;
END IF;
END PROCESS;
--normBitCos_uid105_fpTanTest(BITSELECT,104)@34
normBitCos_uid105_fpTanTest_in <= mulCos_uid104_fpTanTest_q;
normBitCos_uid105_fpTanTest_b <= normBitCos_uid105_fpTanTest_in(51 downto 51);
--cosRndOp_uid111_uid112_fpTanTest(BITJOIN,111)@34
cosRndOp_uid111_uid112_fpTanTest_q <= normBitCos_uid105_fpTanTest_b & cstAllZWF_uid7_fpTanTest_q & VCC_q;
--ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_nor(LOGICAL,1552)
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_nor_a <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_notEnable_q;
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_nor_b <= ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_sticky_ena_q;
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_nor_q <= not (ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_nor_a or ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_nor_b);
--ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_mem_top(CONSTANT,1548)
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_mem_top_q <= "0110";
--ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_cmp(LOGICAL,1549)
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_cmp_a <= ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_mem_top_q;
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdmux_q);
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_cmp_q <= "1" when ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_cmp_a = ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_cmp_b else "0";
--ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_cmpReg(REG,1550)
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_cmpReg_q <= ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_sticky_ena(REG,1553)
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_nor_q = "1") THEN
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_sticky_ena_q <= ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_enaAnd(LOGICAL,1554)
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_enaAnd_a <= ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_sticky_ena_q;
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_enaAnd_b <= en;
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_enaAnd_q <= ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_enaAnd_a and ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_enaAnd_b;
--reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1(REG,745)@23
reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q <= r_uid349_lzcZCos_uid68_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_inputreg(DELAY,1542)
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q, xout => ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdcnt(COUNTER,1544)
-- every=1, low=0, high=6, step=1, init=1
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdcnt_i = 5 THEN
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdcnt_i <= ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdcnt_i - 6;
ELSE
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdcnt_i <= ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdreg(REG,1545)
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdreg_q <= ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdmux(MUX,1546)
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdmux_s <= en;
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdmux: PROCESS (ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdmux_s, ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdreg_q, ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdmux_q <= ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdmux_q <= ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_mem(DUALMEM,1543)
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_mem_ia <= ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_inputreg_q;
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_mem_aa <= ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdreg_q;
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_mem_ab <= ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdmux_q;
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 7,
width_b => 7,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_mem_iq,
address_a => ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_mem_aa,
data_a => ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_mem_ia
);
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_mem_q <= ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_mem_iq(6 downto 0);
--expHardCase_uid77_fpTanTest(SUB,76)@33
expHardCase_uid77_fpTanTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpTanTest_q);
expHardCase_uid77_fpTanTest_b <= STD_LOGIC_VECTOR("00" & ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_mem_q);
expHardCase_uid77_fpTanTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid77_fpTanTest_a) - UNSIGNED(expHardCase_uid77_fpTanTest_b));
expHardCase_uid77_fpTanTest_q <= expHardCase_uid77_fpTanTest_o(8 downto 0);
--expPCos_uid78_fpTanTest(BITSELECT,77)@33
expPCos_uid78_fpTanTest_in <= expHardCase_uid77_fpTanTest_q(7 downto 0);
expPCos_uid78_fpTanTest_b <= expPCos_uid78_fpTanTest_in(7 downto 0);
--reg_expPCos_uid78_fpTanTest_0_to_expFracRCosPreRnd_uid110_uid110_fpTanTest_1(REG,746)@33
reg_expPCos_uid78_fpTanTest_0_to_expFracRCosPreRnd_uid110_uid110_fpTanTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expPCos_uid78_fpTanTest_0_to_expFracRCosPreRnd_uid110_uid110_fpTanTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expPCos_uid78_fpTanTest_0_to_expFracRCosPreRnd_uid110_uid110_fpTanTest_1_q <= expPCos_uid78_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--fracRCosPreRndHigh_uid107_fpTanTest(BITSELECT,106)@34
fracRCosPreRndHigh_uid107_fpTanTest_in <= mulCos_uid104_fpTanTest_q(50 downto 0);
fracRCosPreRndHigh_uid107_fpTanTest_b <= fracRCosPreRndHigh_uid107_fpTanTest_in(50 downto 27);
--fracRCosPreRndLow_uid108_fpTanTest(BITSELECT,107)@34
fracRCosPreRndLow_uid108_fpTanTest_in <= mulCos_uid104_fpTanTest_q(49 downto 0);
fracRCosPreRndLow_uid108_fpTanTest_b <= fracRCosPreRndLow_uid108_fpTanTest_in(49 downto 26);
--fracRCosPreRnd_uid109_fpTanTest(MUX,108)@34
fracRCosPreRnd_uid109_fpTanTest_s <= normBitCos_uid105_fpTanTest_b;
fracRCosPreRnd_uid109_fpTanTest: PROCESS (fracRCosPreRnd_uid109_fpTanTest_s, en, fracRCosPreRndLow_uid108_fpTanTest_b, fracRCosPreRndHigh_uid107_fpTanTest_b)
BEGIN
CASE fracRCosPreRnd_uid109_fpTanTest_s IS
WHEN "0" => fracRCosPreRnd_uid109_fpTanTest_q <= fracRCosPreRndLow_uid108_fpTanTest_b;
WHEN "1" => fracRCosPreRnd_uid109_fpTanTest_q <= fracRCosPreRndHigh_uid107_fpTanTest_b;
WHEN OTHERS => fracRCosPreRnd_uid109_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracRCosPreRnd_uid110_uid110_fpTanTest(BITJOIN,109)@34
expFracRCosPreRnd_uid110_uid110_fpTanTest_q <= reg_expPCos_uid78_fpTanTest_0_to_expFracRCosPreRnd_uid110_uid110_fpTanTest_1_q & fracRCosPreRnd_uid109_fpTanTest_q;
--expFracRCos_uid113_fpTanTest(ADD,112)@34
expFracRCos_uid113_fpTanTest_a <= STD_LOGIC_VECTOR("0" & expFracRCosPreRnd_uid110_uid110_fpTanTest_q);
expFracRCos_uid113_fpTanTest_b <= STD_LOGIC_VECTOR("00000000" & cosRndOp_uid111_uid112_fpTanTest_q);
expFracRCos_uid113_fpTanTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRCos_uid113_fpTanTest_a) + UNSIGNED(expFracRCos_uid113_fpTanTest_b));
expFracRCos_uid113_fpTanTest_q <= expFracRCos_uid113_fpTanTest_o(32 downto 0);
--expRCompSin_uid115_fpTanTest(BITSELECT,114)@34
expRCompSin_uid115_fpTanTest_in <= expFracRCos_uid113_fpTanTest_q(31 downto 0);
expRCompSin_uid115_fpTanTest_b <= expRCompSin_uid115_fpTanTest_in(31 downto 24);
--reg_expRCompSin_uid115_fpTanTest_0_to_expRPostExcCos_uid143_fpTanTest_2(REG,751)@34
reg_expRCompSin_uid115_fpTanTest_0_to_expRPostExcCos_uid143_fpTanTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRCompSin_uid115_fpTanTest_0_to_expRPostExcCos_uid143_fpTanTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRCompSin_uid115_fpTanTest_0_to_expRPostExcCos_uid143_fpTanTest_2_q <= expRCompSin_uid115_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_nor(LOGICAL,1641)
ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_nor_a <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_notEnable_q;
ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_nor_b <= ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_sticky_ena_q;
ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_nor_q <= not (ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_nor_a or ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_nor_b);
--ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_mem_top(CONSTANT,1624)
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_mem_top_q <= "01101";
--ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_cmp(LOGICAL,1625)
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_cmp_a <= ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_mem_top_q;
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdmux_q);
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_cmp_q <= "1" when ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_cmp_a = ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_cmp_b else "0";
--ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_cmpReg(REG,1626)
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_cmpReg_q <= ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_sticky_ena(REG,1642)
ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_nor_q = "1") THEN
ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_sticky_ena_q <= ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_enaAnd(LOGICAL,1643)
ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_enaAnd_a <= ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_sticky_ena_q;
ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_enaAnd_b <= en;
ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_enaAnd_q <= ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_enaAnd_a and ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_enaAnd_b;
--ld_sinXIsX_uid41_fpTanTest_n_to_excSelBitsSin_uid117_fpTanTest_a(DELAY,869)@0
ld_sinXIsX_uid41_fpTanTest_n_to_excSelBitsSin_uid117_fpTanTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => sinXIsX_uid41_fpTanTest_n, xout => ld_sinXIsX_uid41_fpTanTest_n_to_excSelBitsSin_uid117_fpTanTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_cosXIsOneXRR_uid43_fpTanTest_n_to_reg_cosXIsOneXRR_uid43_fpTanTest_2_to_join_uid139_fpTanTest_2_a(DELAY,1503)@14
ld_cosXIsOneXRR_uid43_fpTanTest_n_to_reg_cosXIsOneXRR_uid43_fpTanTest_2_to_join_uid139_fpTanTest_2_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => cosXIsOneXRR_uid43_fpTanTest_n, xout => ld_cosXIsOneXRR_uid43_fpTanTest_n_to_reg_cosXIsOneXRR_uid43_fpTanTest_2_to_join_uid139_fpTanTest_2_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_cosXIsOneXRR_uid43_fpTanTest_2_to_join_uid139_fpTanTest_2(REG,749)@16
reg_cosXIsOneXRR_uid43_fpTanTest_2_to_join_uid139_fpTanTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid43_fpTanTest_2_to_join_uid139_fpTanTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid43_fpTanTest_2_to_join_uid139_fpTanTest_2_q <= ld_cosXIsOneXRR_uid43_fpTanTest_n_to_reg_cosXIsOneXRR_uid43_fpTanTest_2_to_join_uid139_fpTanTest_2_a_q;
END IF;
END IF;
END PROCESS;
--InvCosXIsOneXRR_uid132_fpTanTest(LOGICAL,131)@14
InvCosXIsOneXRR_uid132_fpTanTest_a <= cosXIsOneXRR_uid43_fpTanTest_n;
InvCosXIsOneXRR_uid132_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvCosXIsOneXRR_uid132_fpTanTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvCosXIsOneXRR_uid132_fpTanTest_q <= not InvCosXIsOneXRR_uid132_fpTanTest_a;
END IF;
END PROCESS;
--ld_InvCosXIsOneXRR_uid132_fpTanTest_q_to_yHalfCosNotONe_uid134_fpTanTest_c(DELAY,892)@15
ld_InvCosXIsOneXRR_uid132_fpTanTest_q_to_yHalfCosNotONe_uid134_fpTanTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => InvCosXIsOneXRR_uid132_fpTanTest_q, xout => ld_InvCosXIsOneXRR_uid132_fpTanTest_q_to_yHalfCosNotONe_uid134_fpTanTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_sinXIsX_uid41_fpTanTest_n_to_InvSinXIsX_uid126_fpTanTest_a(DELAY,879)@0
ld_sinXIsX_uid41_fpTanTest_n_to_InvSinXIsX_uid126_fpTanTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => sinXIsX_uid41_fpTanTest_n, xout => ld_sinXIsX_uid41_fpTanTest_n_to_InvSinXIsX_uid126_fpTanTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsX_uid126_fpTanTest(LOGICAL,125)@16
InvSinXIsX_uid126_fpTanTest_a <= ld_sinXIsX_uid41_fpTanTest_n_to_InvSinXIsX_uid126_fpTanTest_a_q;
InvSinXIsX_uid126_fpTanTest_q <= not InvSinXIsX_uid126_fpTanTest_a;
--ld_InvSinXIsX_uid126_fpTanTest_q_to_yHalfCosNotONe_uid134_fpTanTest_b(DELAY,891)@16
ld_InvSinXIsX_uid126_fpTanTest_q_to_yHalfCosNotONe_uid134_fpTanTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => InvSinXIsX_uid126_fpTanTest_q, xout => ld_InvSinXIsX_uid126_fpTanTest_q_to_yHalfCosNotONe_uid134_fpTanTest_b_q, ena => en(0), clk => clk, aclr => areset );
--half_uid52_fpTanTest(BITJOIN,51)@17
half_uid52_fpTanTest_q <= VCC_q & cstZwShiftPwFRR_uid35_fpTanTest_q;
--yIsHalf_uid53_fpTanTest(LOGICAL,52)@17
yIsHalf_uid53_fpTanTest_a <= reg_y_uid50_fpTanTest_0_to_oneMinusY_uid54_fpTanTest_1_q;
yIsHalf_uid53_fpTanTest_b <= half_uid52_fpTanTest_q;
yIsHalf_uid53_fpTanTest_q <= "1" when yIsHalf_uid53_fpTanTest_a = yIsHalf_uid53_fpTanTest_b else "0";
--yHalfCosNotONe_uid134_fpTanTest(LOGICAL,133)@17
yHalfCosNotONe_uid134_fpTanTest_a <= yIsHalf_uid53_fpTanTest_q;
yHalfCosNotONe_uid134_fpTanTest_b <= ld_InvSinXIsX_uid126_fpTanTest_q_to_yHalfCosNotONe_uid134_fpTanTest_b_q;
yHalfCosNotONe_uid134_fpTanTest_c <= ld_InvCosXIsOneXRR_uid132_fpTanTest_q_to_yHalfCosNotONe_uid134_fpTanTest_c_q;
yHalfCosNotONe_uid134_fpTanTest_q <= yHalfCosNotONe_uid134_fpTanTest_a and yHalfCosNotONe_uid134_fpTanTest_b and yHalfCosNotONe_uid134_fpTanTest_c;
--frac_uid13_fpTanTest(BITSELECT,12)@0
frac_uid13_fpTanTest_in <= a(22 downto 0);
frac_uid13_fpTanTest_b <= frac_uid13_fpTanTest_in(22 downto 0);
--fracXIsZero_uid14_fpTanTest(LOGICAL,13)@0
fracXIsZero_uid14_fpTanTest_a <= frac_uid13_fpTanTest_b;
fracXIsZero_uid14_fpTanTest_b <= cstAllZWF_uid7_fpTanTest_q;
fracXIsZero_uid14_fpTanTest_q <= "1" when fracXIsZero_uid14_fpTanTest_a = fracXIsZero_uid14_fpTanTest_b else "0";
--expXIsMax_uid12_fpTanTest(LOGICAL,11)@0
expXIsMax_uid12_fpTanTest_a <= exp_uid9_fpTanTest_b;
expXIsMax_uid12_fpTanTest_b <= cstAllOWE_uid6_fpTanTest_q;
expXIsMax_uid12_fpTanTest_q <= "1" when expXIsMax_uid12_fpTanTest_a = expXIsMax_uid12_fpTanTest_b else "0";
--exc_I_uid15_fpTanTest(LOGICAL,14)@0
exc_I_uid15_fpTanTest_a <= expXIsMax_uid12_fpTanTest_q;
exc_I_uid15_fpTanTest_b <= fracXIsZero_uid14_fpTanTest_q;
exc_I_uid15_fpTanTest_q <= exc_I_uid15_fpTanTest_a and exc_I_uid15_fpTanTest_b;
--ld_exc_I_uid15_fpTanTest_q_to_excRNaN_uid116_fpTanTest_b(DELAY,868)@0
ld_exc_I_uid15_fpTanTest_q_to_excRNaN_uid116_fpTanTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => exc_I_uid15_fpTanTest_q, xout => ld_exc_I_uid15_fpTanTest_q_to_excRNaN_uid116_fpTanTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvFracXIsZero_uid16_fpTanTest(LOGICAL,15)@0
InvFracXIsZero_uid16_fpTanTest_a <= fracXIsZero_uid14_fpTanTest_q;
InvFracXIsZero_uid16_fpTanTest_q <= not InvFracXIsZero_uid16_fpTanTest_a;
--exc_N_uid17_fpTanTest(LOGICAL,16)@0
exc_N_uid17_fpTanTest_a <= expXIsMax_uid12_fpTanTest_q;
exc_N_uid17_fpTanTest_b <= InvFracXIsZero_uid16_fpTanTest_q;
exc_N_uid17_fpTanTest_q <= exc_N_uid17_fpTanTest_a and exc_N_uid17_fpTanTest_b;
--ld_exc_N_uid17_fpTanTest_q_to_excRNaN_uid116_fpTanTest_a(DELAY,867)@0
ld_exc_N_uid17_fpTanTest_q_to_excRNaN_uid116_fpTanTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => exc_N_uid17_fpTanTest_q, xout => ld_exc_N_uid17_fpTanTest_q_to_excRNaN_uid116_fpTanTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRNaN_uid116_fpTanTest(LOGICAL,115)@17
excRNaN_uid116_fpTanTest_a <= ld_exc_N_uid17_fpTanTest_q_to_excRNaN_uid116_fpTanTest_a_q;
excRNaN_uid116_fpTanTest_b <= ld_exc_I_uid15_fpTanTest_q_to_excRNaN_uid116_fpTanTest_b_q;
excRNaN_uid116_fpTanTest_q <= excRNaN_uid116_fpTanTest_a or excRNaN_uid116_fpTanTest_b;
--join_uid139_fpTanTest(BITJOIN,138)@17
join_uid139_fpTanTest_q <= reg_cosXIsOneXRR_uid43_fpTanTest_2_to_join_uid139_fpTanTest_2_q & yHalfCosNotONe_uid134_fpTanTest_q & excRNaN_uid116_fpTanTest_q;
--expSelBitsCos_uid140_fpTanTest(BITJOIN,139)@17
expSelBitsCos_uid140_fpTanTest_q <= ld_sinXIsX_uid41_fpTanTest_n_to_excSelBitsSin_uid117_fpTanTest_a_q & join_uid139_fpTanTest_q;
--reg_expSelBitsCos_uid140_fpTanTest_0_to_expSelectorCos_uid141_fpTanTest_0(REG,750)@17
reg_expSelBitsCos_uid140_fpTanTest_0_to_expSelectorCos_uid141_fpTanTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expSelBitsCos_uid140_fpTanTest_0_to_expSelectorCos_uid141_fpTanTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expSelBitsCos_uid140_fpTanTest_0_to_expSelectorCos_uid141_fpTanTest_0_q <= expSelBitsCos_uid140_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--expSelectorCos_uid141_fpTanTest(LOOKUP,140)@18
expSelectorCos_uid141_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSelectorCos_uid141_fpTanTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_expSelBitsCos_uid140_fpTanTest_0_to_expSelectorCos_uid141_fpTanTest_0_q) IS
WHEN "0000" => expSelectorCos_uid141_fpTanTest_q <= "00";
WHEN "0001" => expSelectorCos_uid141_fpTanTest_q <= "11";
WHEN "0010" => expSelectorCos_uid141_fpTanTest_q <= "10";
WHEN "0011" => expSelectorCos_uid141_fpTanTest_q <= "00";
WHEN "0100" => expSelectorCos_uid141_fpTanTest_q <= "01";
WHEN "0101" => expSelectorCos_uid141_fpTanTest_q <= "11";
WHEN "0110" => expSelectorCos_uid141_fpTanTest_q <= "10";
WHEN "0111" => expSelectorCos_uid141_fpTanTest_q <= "00";
WHEN "1000" => expSelectorCos_uid141_fpTanTest_q <= "01";
WHEN "1001" => expSelectorCos_uid141_fpTanTest_q <= "11";
WHEN "1010" => expSelectorCos_uid141_fpTanTest_q <= "10";
WHEN "1011" => expSelectorCos_uid141_fpTanTest_q <= "00";
WHEN "1100" => expSelectorCos_uid141_fpTanTest_q <= "01";
WHEN "1101" => expSelectorCos_uid141_fpTanTest_q <= "11";
WHEN "1110" => expSelectorCos_uid141_fpTanTest_q <= "10";
WHEN "1111" => expSelectorCos_uid141_fpTanTest_q <= "00";
WHEN OTHERS =>
expSelectorCos_uid141_fpTanTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_inputreg(DELAY,1631)
ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => expSelectorCos_uid141_fpTanTest_q, xout => ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdcnt(COUNTER,1620)
-- every=1, low=0, high=13, step=1, init=1
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdcnt_i = 12 THEN
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdcnt_i <= ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdcnt_i - 13;
ELSE
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdcnt_i <= ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdcnt_i,4));
--ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdreg(REG,1621)
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdreg_q <= ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdmux(MUX,1622)
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdmux_s <= en;
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdmux: PROCESS (ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdmux_s, ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdreg_q, ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdmux_q <= ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdmux_q <= ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_replace_mem(DUALMEM,1632)
ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_replace_mem_ia <= ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_inputreg_q;
ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_replace_mem_aa <= ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdreg_q;
ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_replace_mem_ab <= ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdmux_q;
ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_replace_mem_iq,
address_a => ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_replace_mem_aa,
data_a => ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_replace_mem_ia
);
ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_replace_mem_reset0 <= areset;
ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_replace_mem_q <= ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_replace_mem_iq(1 downto 0);
--expRPostExcCos_uid143_fpTanTest(MUX,142)@35
expRPostExcCos_uid143_fpTanTest_s <= ld_expSelectorCos_uid141_fpTanTest_q_to_expRPostExcCos_uid143_fpTanTest_b_replace_mem_q;
expRPostExcCos_uid143_fpTanTest: PROCESS (expRPostExcCos_uid143_fpTanTest_s, en, reg_expRCompSin_uid115_fpTanTest_0_to_expRPostExcCos_uid143_fpTanTest_2_q, cstBias_uid22_fpTanTest_q, cstAllZWE_uid8_fpTanTest_q, cstAllOWE_uid6_fpTanTest_q)
BEGIN
CASE expRPostExcCos_uid143_fpTanTest_s IS
WHEN "00" => expRPostExcCos_uid143_fpTanTest_q <= reg_expRCompSin_uid115_fpTanTest_0_to_expRPostExcCos_uid143_fpTanTest_2_q;
WHEN "01" => expRPostExcCos_uid143_fpTanTest_q <= cstBias_uid22_fpTanTest_q;
WHEN "10" => expRPostExcCos_uid143_fpTanTest_q <= cstAllZWE_uid8_fpTanTest_q;
WHEN "11" => expRPostExcCos_uid143_fpTanTest_q <= cstAllOWE_uid6_fpTanTest_q;
WHEN OTHERS => expRPostExcCos_uid143_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstNaNwF_uid32_fpTanTest(CONSTANT,31)
cstNaNwF_uid32_fpTanTest_q <= "00000000000000000000001";
--fracRCompCos_uid114_fpTanTest(BITSELECT,113)@34
fracRCompCos_uid114_fpTanTest_in <= expFracRCos_uid113_fpTanTest_q(23 downto 0);
fracRCompCos_uid114_fpTanTest_b <= fracRCompCos_uid114_fpTanTest_in(23 downto 1);
--reg_fracRCompCos_uid114_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_2(REG,748)@34
reg_fracRCompCos_uid114_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRCompCos_uid114_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRCompCos_uid114_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_2_q <= fracRCompCos_uid114_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_nor(LOGICAL,1628)
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_nor_a <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_notEnable_q;
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_nor_b <= ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_sticky_ena_q;
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_nor_q <= not (ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_nor_a or ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_nor_b);
--ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_sticky_ena(REG,1629)
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_nor_q = "1") THEN
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_sticky_ena_q <= ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_enaAnd(LOGICAL,1630)
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_enaAnd_a <= ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_sticky_ena_q;
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_enaAnd_b <= en;
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_enaAnd_q <= ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_enaAnd_a and ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_enaAnd_b;
--reg_excRNaN_uid116_fpTanTest_0_to_join_uid137_fpTanTest_1(REG,717)@17
reg_excRNaN_uid116_fpTanTest_0_to_join_uid137_fpTanTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid116_fpTanTest_0_to_join_uid137_fpTanTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid116_fpTanTest_0_to_join_uid137_fpTanTest_1_q <= excRNaN_uid116_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOneXRR_uid43_fpTanTest_2_to_rZeroOrCosOne_uid136_fpTanTest_3(REG,716)@14
reg_cosXIsOneXRR_uid43_fpTanTest_2_to_rZeroOrCosOne_uid136_fpTanTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid43_fpTanTest_2_to_rZeroOrCosOne_uid136_fpTanTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid43_fpTanTest_2_to_rZeroOrCosOne_uid136_fpTanTest_3_q <= cosXIsOneXRR_uid43_fpTanTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_cosXIsOneXRR_uid43_fpTanTest_2_to_rZeroOrCosOne_uid136_fpTanTest_3_q_to_rZeroOrCosOne_uid136_fpTanTest_c(DELAY,895)@15
ld_reg_cosXIsOneXRR_uid43_fpTanTest_2_to_rZeroOrCosOne_uid136_fpTanTest_3_q_to_rZeroOrCosOne_uid136_fpTanTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => reg_cosXIsOneXRR_uid43_fpTanTest_2_to_rZeroOrCosOne_uid136_fpTanTest_3_q, xout => ld_reg_cosXIsOneXRR_uid43_fpTanTest_2_to_rZeroOrCosOne_uid136_fpTanTest_3_q_to_rZeroOrCosOne_uid136_fpTanTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_sinXIsX_uid41_fpTanTest_2_to_rZeroOrCosOne_uid136_fpTanTest_2(REG,715)@0
reg_sinXIsX_uid41_fpTanTest_2_to_rZeroOrCosOne_uid136_fpTanTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsX_uid41_fpTanTest_2_to_rZeroOrCosOne_uid136_fpTanTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsX_uid41_fpTanTest_2_to_rZeroOrCosOne_uid136_fpTanTest_2_q <= sinXIsX_uid41_fpTanTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_sinXIsX_uid41_fpTanTest_2_to_rZeroOrCosOne_uid136_fpTanTest_2_q_to_rZeroOrCosOne_uid136_fpTanTest_b(DELAY,894)@1
ld_reg_sinXIsX_uid41_fpTanTest_2_to_rZeroOrCosOne_uid136_fpTanTest_2_q_to_rZeroOrCosOne_uid136_fpTanTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => reg_sinXIsX_uid41_fpTanTest_2_to_rZeroOrCosOne_uid136_fpTanTest_2_q, xout => ld_reg_sinXIsX_uid41_fpTanTest_2_to_rZeroOrCosOne_uid136_fpTanTest_2_q_to_rZeroOrCosOne_uid136_fpTanTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_yHalfCosNotONe_uid134_fpTanTest_0_to_rZeroOrCosOne_uid136_fpTanTest_1(REG,714)@17
reg_yHalfCosNotONe_uid134_fpTanTest_0_to_rZeroOrCosOne_uid136_fpTanTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yHalfCosNotONe_uid134_fpTanTest_0_to_rZeroOrCosOne_uid136_fpTanTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yHalfCosNotONe_uid134_fpTanTest_0_to_rZeroOrCosOne_uid136_fpTanTest_1_q <= yHalfCosNotONe_uid134_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--rZeroOrCosOne_uid136_fpTanTest(LOGICAL,135)@18
rZeroOrCosOne_uid136_fpTanTest_a <= reg_yHalfCosNotONe_uid134_fpTanTest_0_to_rZeroOrCosOne_uid136_fpTanTest_1_q;
rZeroOrCosOne_uid136_fpTanTest_b <= ld_reg_sinXIsX_uid41_fpTanTest_2_to_rZeroOrCosOne_uid136_fpTanTest_2_q_to_rZeroOrCosOne_uid136_fpTanTest_b_q;
rZeroOrCosOne_uid136_fpTanTest_c <= ld_reg_cosXIsOneXRR_uid43_fpTanTest_2_to_rZeroOrCosOne_uid136_fpTanTest_3_q_to_rZeroOrCosOne_uid136_fpTanTest_c_q;
rZeroOrCosOne_uid136_fpTanTest_q <= rZeroOrCosOne_uid136_fpTanTest_a or rZeroOrCosOne_uid136_fpTanTest_b or rZeroOrCosOne_uid136_fpTanTest_c;
--join_uid137_fpTanTest(BITJOIN,136)@18
join_uid137_fpTanTest_q <= reg_excRNaN_uid116_fpTanTest_0_to_join_uid137_fpTanTest_1_q & rZeroOrCosOne_uid136_fpTanTest_q;
--reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1(REG,747)@18
reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q <= join_uid137_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_inputreg(DELAY,1618)
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q, xout => ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_mem(DUALMEM,1619)
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_mem_ia <= ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_inputreg_q;
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_mem_aa <= ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdreg_q;
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_mem_ab <= ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdmux_q;
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_mem_iq,
address_a => ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_mem_aa,
data_a => ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_mem_ia
);
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_mem_reset0 <= areset;
ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_mem_q <= ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_mem_iq(1 downto 0);
--fracRPostExcCos_uid138_fpTanTest(MUX,137)@35
fracRPostExcCos_uid138_fpTanTest_s <= ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_mem_q;
fracRPostExcCos_uid138_fpTanTest: PROCESS (fracRPostExcCos_uid138_fpTanTest_s, en, reg_fracRCompCos_uid114_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_2_q, cstAllZWF_uid7_fpTanTest_q, cstNaNwF_uid32_fpTanTest_q, cstNaNwF_uid32_fpTanTest_q)
BEGIN
CASE fracRPostExcCos_uid138_fpTanTest_s IS
WHEN "00" => fracRPostExcCos_uid138_fpTanTest_q <= reg_fracRCompCos_uid114_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_2_q;
WHEN "01" => fracRPostExcCos_uid138_fpTanTest_q <= cstAllZWF_uid7_fpTanTest_q;
WHEN "10" => fracRPostExcCos_uid138_fpTanTest_q <= cstNaNwF_uid32_fpTanTest_q;
WHEN "11" => fracRPostExcCos_uid138_fpTanTest_q <= cstNaNwF_uid32_fpTanTest_q;
WHEN OTHERS => fracRPostExcCos_uid138_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpCos_uid155_fpTanTest(BITJOIN,154)@35
fpCos_uid155_fpTanTest_q <= ld_signRCos_uid154_fpTanTest_q_to_fpCos_uid155_fpTanTest_c_q & expRPostExcCos_uid143_fpTanTest_q & fracRPostExcCos_uid138_fpTanTest_q;
--fracY_uid432_fpTanXComp_uid157_fpTanTest(BITSELECT,431)@35
fracY_uid432_fpTanXComp_uid157_fpTanTest_in <= fpCos_uid155_fpTanTest_q(22 downto 0);
fracY_uid432_fpTanXComp_uid157_fpTanTest_b <= fracY_uid432_fpTanXComp_uid157_fpTanTest_in(22 downto 0);
--fracXIsZero_uid459_fpTanXComp_uid157_fpTanTest(LOGICAL,458)@35
fracXIsZero_uid459_fpTanXComp_uid157_fpTanTest_a <= fracY_uid432_fpTanXComp_uid157_fpTanTest_b;
fracXIsZero_uid459_fpTanXComp_uid157_fpTanTest_b <= cstAllZWF_uid7_fpTanTest_q;
fracXIsZero_uid459_fpTanXComp_uid157_fpTanTest_q <= "1" when fracXIsZero_uid459_fpTanXComp_uid157_fpTanTest_a = fracXIsZero_uid459_fpTanXComp_uid157_fpTanTest_b else "0";
--expY_uid431_fpTanXComp_uid157_fpTanTest(BITSELECT,430)@35
expY_uid431_fpTanXComp_uid157_fpTanTest_in <= fpCos_uid155_fpTanTest_q(30 downto 0);
expY_uid431_fpTanXComp_uid157_fpTanTest_b <= expY_uid431_fpTanXComp_uid157_fpTanTest_in(30 downto 23);
--expXIsMax_uid457_fpTanXComp_uid157_fpTanTest(LOGICAL,456)@35
expXIsMax_uid457_fpTanXComp_uid157_fpTanTest_a <= expY_uid431_fpTanXComp_uid157_fpTanTest_b;
expXIsMax_uid457_fpTanXComp_uid157_fpTanTest_b <= cstAllOWE_uid6_fpTanTest_q;
expXIsMax_uid457_fpTanXComp_uid157_fpTanTest_q <= "1" when expXIsMax_uid457_fpTanXComp_uid157_fpTanTest_a = expXIsMax_uid457_fpTanXComp_uid157_fpTanTest_b else "0";
--exc_I_uid460_fpTanXComp_uid157_fpTanTest(LOGICAL,459)@35
exc_I_uid460_fpTanXComp_uid157_fpTanTest_a <= expXIsMax_uid457_fpTanXComp_uid157_fpTanTest_q;
exc_I_uid460_fpTanXComp_uid157_fpTanTest_b <= fracXIsZero_uid459_fpTanXComp_uid157_fpTanTest_q;
exc_I_uid460_fpTanXComp_uid157_fpTanTest_q <= exc_I_uid460_fpTanXComp_uid157_fpTanTest_a and exc_I_uid460_fpTanXComp_uid157_fpTanTest_b;
--cstBiasMwShiftM2_uid25_fpTanTest(CONSTANT,24)
cstBiasMwShiftM2_uid25_fpTanTest_q <= "01110001";
--sinXIsXRR_uid42_fpTanTest(COMPARE,41)@14
sinXIsXRR_uid42_fpTanTest_cin <= GND_q;
sinXIsXRR_uid42_fpTanTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid25_fpTanTest_q) & '0';
sinXIsXRR_uid42_fpTanTest_b <= STD_LOGIC_VECTOR((10 downto 8 => expXRR_uid39_fpTanTest_b(7)) & expXRR_uid39_fpTanTest_b) & sinXIsXRR_uid42_fpTanTest_cin(0);
sinXIsXRR_uid42_fpTanTest_o <= STD_LOGIC_VECTOR(SIGNED(sinXIsXRR_uid42_fpTanTest_a) - SIGNED(sinXIsXRR_uid42_fpTanTest_b));
sinXIsXRR_uid42_fpTanTest_n(0) <= not sinXIsXRR_uid42_fpTanTest_o(11);
--InvSinXIsXRR_uid127_fpTanTest(LOGICAL,126)@14
InvSinXIsXRR_uid127_fpTanTest_a <= sinXIsXRR_uid42_fpTanTest_n;
InvSinXIsXRR_uid127_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvSinXIsXRR_uid127_fpTanTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvSinXIsXRR_uid127_fpTanTest_q <= not InvSinXIsXRR_uid127_fpTanTest_a;
END IF;
END PROCESS;
--ld_InvSinXIsXRR_uid127_fpTanTest_q_to_signComp_uid128_fpTanTest_a(DELAY,881)@15
ld_InvSinXIsXRR_uid127_fpTanTest_q_to_signComp_uid128_fpTanTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => InvSinXIsXRR_uid127_fpTanTest_q, xout => ld_InvSinXIsXRR_uid127_fpTanTest_q_to_signComp_uid128_fpTanTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signComp_uid128_fpTanTest(LOGICAL,127)@16
signComp_uid128_fpTanTest_a <= ld_InvSinXIsXRR_uid127_fpTanTest_q_to_signComp_uid128_fpTanTest_a_q;
signComp_uid128_fpTanTest_b <= InvSinXIsX_uid126_fpTanTest_q;
signComp_uid128_fpTanTest_c <= intXParity_uid49_fpTanTest_b;
signComp_uid128_fpTanTest_q <= signComp_uid128_fpTanTest_a and signComp_uid128_fpTanTest_b and signComp_uid128_fpTanTest_c;
--signX_uid38_fpTanTest(BITSELECT,37)@0
signX_uid38_fpTanTest_in <= a;
signX_uid38_fpTanTest_b <= signX_uid38_fpTanTest_in(31 downto 31);
--ld_signX_uid38_fpTanTest_b_to_signR_uid129_fpTanTest_a(DELAY,884)@0
ld_signX_uid38_fpTanTest_b_to_signR_uid129_fpTanTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signX_uid38_fpTanTest_b, xout => ld_signX_uid38_fpTanTest_b_to_signR_uid129_fpTanTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid129_fpTanTest(LOGICAL,128)@16
signR_uid129_fpTanTest_a <= ld_signX_uid38_fpTanTest_b_to_signR_uid129_fpTanTest_a_q;
signR_uid129_fpTanTest_b <= signComp_uid128_fpTanTest_q;
signR_uid129_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid129_fpTanTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signR_uid129_fpTanTest_q <= signR_uid129_fpTanTest_a xor signR_uid129_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--ld_signR_uid129_fpTanTest_q_to_fpSin_uid130_fpTanTest_c(DELAY,888)@17
ld_signR_uid129_fpTanTest_q_to_fpSin_uid130_fpTanTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => signR_uid129_fpTanTest_q, xout => ld_signR_uid129_fpTanTest_q_to_fpSin_uid130_fpTanTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_nor(LOGICAL,1615)
ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_nor_a <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_notEnable_q;
ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_nor_b <= ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_sticky_ena_q;
ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_nor_q <= not (ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_nor_a or ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_nor_b);
--ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_mem_top(CONSTANT,1598)
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_mem_top_q <= "0100000";
--ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_cmp(LOGICAL,1599)
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_cmp_a <= ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_mem_top_q;
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdmux_q);
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_cmp_q <= "1" when ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_cmp_a = ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_cmp_b else "0";
--ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_cmpReg(REG,1600)
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_cmpReg_q <= ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_sticky_ena(REG,1616)
ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_nor_q = "1") THEN
ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_sticky_ena_q <= ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_enaAnd(LOGICAL,1617)
ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_enaAnd_a <= ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_sticky_ena_q;
ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_enaAnd_b <= en;
ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_enaAnd_q <= ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_enaAnd_a and ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_enaAnd_b;
--ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_inputreg(DELAY,1605)
ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => exp_uid9_fpTanTest_b, xout => ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdcnt(COUNTER,1594)
-- every=1, low=0, high=32, step=1, init=1
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdcnt_i = 31 THEN
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdcnt_eq = '1') THEN
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdcnt_i <= ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdcnt_i - 32;
ELSE
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdcnt_i <= ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdcnt_i,6));
--ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdreg(REG,1595)
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdreg_q <= ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdmux(MUX,1596)
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdmux_s <= en;
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdmux: PROCESS (ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdmux_s, ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdreg_q, ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdmux_s IS
WHEN "0" => ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdmux_q <= ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdreg_q;
WHEN "1" => ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdmux_q <= ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_replace_mem(DUALMEM,1606)
ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_replace_mem_ia <= ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_inputreg_q;
ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_replace_mem_aa <= ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdreg_q;
ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_replace_mem_ab <= ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdmux_q;
ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 33,
width_b => 8,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_replace_mem_iq,
address_a => ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_replace_mem_aa,
data_a => ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_replace_mem_ia
);
ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_replace_mem_reset0 <= areset;
ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_replace_mem_q <= ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_replace_mem_iq(7 downto 0);
--ld_sinXIsXRR_uid42_fpTanTest_n_to_reg_sinXIsXRR_uid42_fpTanTest_2_to_join_uid98_fpTanTest_1_a(DELAY,1464)@14
ld_sinXIsXRR_uid42_fpTanTest_n_to_reg_sinXIsXRR_uid42_fpTanTest_2_to_join_uid98_fpTanTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => sinXIsXRR_uid42_fpTanTest_n, xout => ld_sinXIsXRR_uid42_fpTanTest_n_to_reg_sinXIsXRR_uid42_fpTanTest_2_to_join_uid98_fpTanTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sinXIsXRR_uid42_fpTanTest_2_to_join_uid98_fpTanTest_1(REG,710)@33
reg_sinXIsXRR_uid42_fpTanTest_2_to_join_uid98_fpTanTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid42_fpTanTest_2_to_join_uid98_fpTanTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid42_fpTanTest_2_to_join_uid98_fpTanTest_1_q <= ld_sinXIsXRR_uid42_fpTanTest_n_to_reg_sinXIsXRR_uid42_fpTanTest_2_to_join_uid98_fpTanTest_1_a_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_nor(LOGICAL,1565)
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_nor_a <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_notEnable_q;
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_nor_b <= ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_sticky_ena_q;
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_nor_q <= not (ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_nor_a or ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_nor_b);
--ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_mem_top(CONSTANT,1561)
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_mem_top_q <= "01100";
--ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_cmp(LOGICAL,1562)
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_cmp_a <= ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_mem_top_q;
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdmux_q);
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_cmp_q <= "1" when ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_cmp_a = ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_cmp_b else "0";
--ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_cmpReg(REG,1563)
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_cmpReg_q <= ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_sticky_ena(REG,1566)
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_nor_q = "1") THEN
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_sticky_ena_q <= ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_enaAnd(LOGICAL,1567)
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_enaAnd_a <= ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_sticky_ena_q;
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_enaAnd_b <= en;
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_enaAnd_q <= ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_enaAnd_a and ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_enaAnd_b;
--oFracXRRSmallXRR_uid89_fpTanTest(BITSELECT,88)@15
oFracXRRSmallXRR_uid89_fpTanTest_in <= oFracXRR_uid44_uid44_fpTanTest_q;
oFracXRRSmallXRR_uid89_fpTanTest_b <= oFracXRRSmallXRR_uid89_fpTanTest_in(53 downto 28);
--ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_inputreg(DELAY,1555)
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => oFracXRRSmallXRR_uid89_fpTanTest_b, xout => ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdcnt(COUNTER,1557)
-- every=1, low=0, high=12, step=1, init=1
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdcnt_i = 11 THEN
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdcnt_eq = '1') THEN
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdcnt_i <= ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdcnt_i - 12;
ELSE
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdcnt_i <= ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdcnt_i,4));
--ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdreg(REG,1558)
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdreg_q <= ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdmux(MUX,1559)
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdmux_s <= en;
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdmux: PROCESS (ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdmux_s, ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdreg_q, ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdmux_s IS
WHEN "0" => ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdmux_q <= ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdreg_q;
WHEN "1" => ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdmux_q <= ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_mem(DUALMEM,1556)
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_mem_ia <= ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_inputreg_q;
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_mem_aa <= ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdreg_q;
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_mem_ab <= ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_rdmux_q;
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 4,
numwords_a => 13,
width_b => 26,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_mem_iq,
address_a => ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_mem_aa,
data_a => ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_mem_ia
);
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_mem_reset0 <= areset;
ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_mem_q <= ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_mem_iq(25 downto 0);
--reg_cmpYToOneMinusY_uid56_fpTanTest_1_to_zSin_uid59_fpTanTest_1(REG,681)@18
reg_cmpYToOneMinusY_uid56_fpTanTest_1_to_zSin_uid59_fpTanTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cmpYToOneMinusY_uid56_fpTanTest_1_to_zSin_uid59_fpTanTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cmpYToOneMinusY_uid56_fpTanTest_1_to_zSin_uid59_fpTanTest_1_q <= cmpYToOneMinusY_uid56_fpTanTest_c;
END IF;
END IF;
END PROCESS;
--zSin_uid59_fpTanTest(MUX,58)@19
zSin_uid59_fpTanTest_s <= reg_cmpYToOneMinusY_uid56_fpTanTest_1_to_zSin_uid59_fpTanTest_1_q;
zSin_uid59_fpTanTest: PROCESS (zSin_uid59_fpTanTest_s, en, reg_zSinYBottom_uid58_fpTanTest_0_to_zSin_uid59_fpTanTest_2_q, reg_zSinOMyBottom_uid57_fpTanTest_0_to_zSin_uid59_fpTanTest_3_q)
BEGIN
CASE zSin_uid59_fpTanTest_s IS
WHEN "0" => zSin_uid59_fpTanTest_q <= reg_zSinYBottom_uid58_fpTanTest_0_to_zSin_uid59_fpTanTest_2_q;
WHEN "1" => zSin_uid59_fpTanTest_q <= reg_zSinOMyBottom_uid57_fpTanTest_0_to_zSin_uid59_fpTanTest_3_q;
WHEN OTHERS => zSin_uid59_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--addr_uid80_fpTanTest(BITSELECT,79)@19
addr_uid80_fpTanTest_in <= zSin_uid59_fpTanTest_q;
addr_uid80_fpTanTest_b <= addr_uid80_fpTanTest_in(64 downto 57);
--reg_addr_uid80_fpTanTest_0_to_memoryC2_uid391_tableGensinPiZ_lutmem_0(REG,699)@19
reg_addr_uid80_fpTanTest_0_to_memoryC2_uid391_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid80_fpTanTest_0_to_memoryC2_uid391_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid80_fpTanTest_0_to_memoryC2_uid391_tableGensinPiZ_lutmem_0_q <= addr_uid80_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid391_tableGensinPiZ_lutmem(DUALMEM,641)@20
memoryC2_uid391_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC2_uid391_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC2_uid391_tableGensinPiZ_lutmem_ab <= reg_addr_uid80_fpTanTest_0_to_memoryC2_uid391_tableGensinPiZ_lutmem_0_q;
memoryC2_uid391_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_tan_s5_memoryC2_uid391_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid391_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid391_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid391_tableGensinPiZ_lutmem_iq,
address_a => memoryC2_uid391_tableGensinPiZ_lutmem_aa,
data_a => memoryC2_uid391_tableGensinPiZ_lutmem_ia
);
memoryC2_uid391_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC2_uid391_tableGensinPiZ_lutmem_q <= memoryC2_uid391_tableGensinPiZ_lutmem_iq(12 downto 0);
--reg_memoryC2_uid391_tableGensinPiZ_lutmem_0_to_prodXY_uid586_pT1_uid400_polyEvalsinPiZ_1(REG,701)@22
reg_memoryC2_uid391_tableGensinPiZ_lutmem_0_to_prodXY_uid586_pT1_uid400_polyEvalsinPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid391_tableGensinPiZ_lutmem_0_to_prodXY_uid586_pT1_uid400_polyEvalsinPiZ_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid391_tableGensinPiZ_lutmem_0_to_prodXY_uid586_pT1_uid400_polyEvalsinPiZ_1_q <= memoryC2_uid391_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPsinPiZ_uid83_fpTanTest(BITSELECT,82)@19
zPsinPiZ_uid83_fpTanTest_in <= zSin_uid59_fpTanTest_q(56 downto 0);
zPsinPiZ_uid83_fpTanTest_b <= zPsinPiZ_uid83_fpTanTest_in(56 downto 42);
--yT1_uid399_polyEvalsinPiZ(BITSELECT,398)@19
yT1_uid399_polyEvalsinPiZ_in <= zPsinPiZ_uid83_fpTanTest_b;
yT1_uid399_polyEvalsinPiZ_b <= yT1_uid399_polyEvalsinPiZ_in(14 downto 2);
--ld_yT1_uid399_polyEvalsinPiZ_b_to_reg_yT1_uid399_polyEvalsinPiZ_0_to_prodXY_uid586_pT1_uid400_polyEvalsinPiZ_0_a_inputreg(DELAY,1794)
ld_yT1_uid399_polyEvalsinPiZ_b_to_reg_yT1_uid399_polyEvalsinPiZ_0_to_prodXY_uid586_pT1_uid400_polyEvalsinPiZ_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => yT1_uid399_polyEvalsinPiZ_b, xout => ld_yT1_uid399_polyEvalsinPiZ_b_to_reg_yT1_uid399_polyEvalsinPiZ_0_to_prodXY_uid586_pT1_uid400_polyEvalsinPiZ_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid399_polyEvalsinPiZ_b_to_reg_yT1_uid399_polyEvalsinPiZ_0_to_prodXY_uid586_pT1_uid400_polyEvalsinPiZ_0_a(DELAY,1454)@19
ld_yT1_uid399_polyEvalsinPiZ_b_to_reg_yT1_uid399_polyEvalsinPiZ_0_to_prodXY_uid586_pT1_uid400_polyEvalsinPiZ_0_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_yT1_uid399_polyEvalsinPiZ_b_to_reg_yT1_uid399_polyEvalsinPiZ_0_to_prodXY_uid586_pT1_uid400_polyEvalsinPiZ_0_a_inputreg_q, xout => ld_yT1_uid399_polyEvalsinPiZ_b_to_reg_yT1_uid399_polyEvalsinPiZ_0_to_prodXY_uid586_pT1_uid400_polyEvalsinPiZ_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid399_polyEvalsinPiZ_0_to_prodXY_uid586_pT1_uid400_polyEvalsinPiZ_0(REG,700)@22
reg_yT1_uid399_polyEvalsinPiZ_0_to_prodXY_uid586_pT1_uid400_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid399_polyEvalsinPiZ_0_to_prodXY_uid586_pT1_uid400_polyEvalsinPiZ_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid399_polyEvalsinPiZ_0_to_prodXY_uid586_pT1_uid400_polyEvalsinPiZ_0_q <= ld_yT1_uid399_polyEvalsinPiZ_b_to_reg_yT1_uid399_polyEvalsinPiZ_0_to_prodXY_uid586_pT1_uid400_polyEvalsinPiZ_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid586_pT1_uid400_polyEvalsinPiZ(MULT,585)@23
prodXY_uid586_pT1_uid400_polyEvalsinPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid586_pT1_uid400_polyEvalsinPiZ_a),14)) * SIGNED(prodXY_uid586_pT1_uid400_polyEvalsinPiZ_b);
prodXY_uid586_pT1_uid400_polyEvalsinPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid586_pT1_uid400_polyEvalsinPiZ_a <= (others => '0');
prodXY_uid586_pT1_uid400_polyEvalsinPiZ_b <= (others => '0');
prodXY_uid586_pT1_uid400_polyEvalsinPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid586_pT1_uid400_polyEvalsinPiZ_a <= reg_yT1_uid399_polyEvalsinPiZ_0_to_prodXY_uid586_pT1_uid400_polyEvalsinPiZ_0_q;
prodXY_uid586_pT1_uid400_polyEvalsinPiZ_b <= reg_memoryC2_uid391_tableGensinPiZ_lutmem_0_to_prodXY_uid586_pT1_uid400_polyEvalsinPiZ_1_q;
prodXY_uid586_pT1_uid400_polyEvalsinPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid586_pT1_uid400_polyEvalsinPiZ_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid586_pT1_uid400_polyEvalsinPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid586_pT1_uid400_polyEvalsinPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid586_pT1_uid400_polyEvalsinPiZ_q <= prodXY_uid586_pT1_uid400_polyEvalsinPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid587_pT1_uid400_polyEvalsinPiZ(BITSELECT,586)@26
prodXYTruncFR_uid587_pT1_uid400_polyEvalsinPiZ_in <= prodXY_uid586_pT1_uid400_polyEvalsinPiZ_q;
prodXYTruncFR_uid587_pT1_uid400_polyEvalsinPiZ_b <= prodXYTruncFR_uid587_pT1_uid400_polyEvalsinPiZ_in(25 downto 12);
--highBBits_uid402_polyEvalsinPiZ(BITSELECT,401)@26
highBBits_uid402_polyEvalsinPiZ_in <= prodXYTruncFR_uid587_pT1_uid400_polyEvalsinPiZ_b;
highBBits_uid402_polyEvalsinPiZ_b <= highBBits_uid402_polyEvalsinPiZ_in(13 downto 1);
--ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC1_uid389_tableGensinPiZ_lutmem_0_a(DELAY,1456)@19
ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC1_uid389_tableGensinPiZ_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addr_uid80_fpTanTest_b, xout => ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC1_uid389_tableGensinPiZ_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid80_fpTanTest_0_to_memoryC1_uid389_tableGensinPiZ_lutmem_0(REG,702)@22
reg_addr_uid80_fpTanTest_0_to_memoryC1_uid389_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid80_fpTanTest_0_to_memoryC1_uid389_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid80_fpTanTest_0_to_memoryC1_uid389_tableGensinPiZ_lutmem_0_q <= ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC1_uid389_tableGensinPiZ_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid389_tableGensinPiZ_lutmem(DUALMEM,640)@23
memoryC1_uid389_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC1_uid389_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC1_uid389_tableGensinPiZ_lutmem_ab <= reg_addr_uid80_fpTanTest_0_to_memoryC1_uid389_tableGensinPiZ_lutmem_0_q;
memoryC1_uid389_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_tan_s5_memoryC1_uid389_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid389_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid389_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid389_tableGensinPiZ_lutmem_iq,
address_a => memoryC1_uid389_tableGensinPiZ_lutmem_aa,
data_a => memoryC1_uid389_tableGensinPiZ_lutmem_ia
);
memoryC1_uid389_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC1_uid389_tableGensinPiZ_lutmem_q <= memoryC1_uid389_tableGensinPiZ_lutmem_iq(20 downto 0);
--reg_memoryC1_uid389_tableGensinPiZ_lutmem_0_to_sumAHighB_uid403_polyEvalsinPiZ_0(REG,703)@25
reg_memoryC1_uid389_tableGensinPiZ_lutmem_0_to_sumAHighB_uid403_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid389_tableGensinPiZ_lutmem_0_to_sumAHighB_uid403_polyEvalsinPiZ_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid389_tableGensinPiZ_lutmem_0_to_sumAHighB_uid403_polyEvalsinPiZ_0_q <= memoryC1_uid389_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid403_polyEvalsinPiZ(ADD,402)@26
sumAHighB_uid403_polyEvalsinPiZ_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid389_tableGensinPiZ_lutmem_0_to_sumAHighB_uid403_polyEvalsinPiZ_0_q(20)) & reg_memoryC1_uid389_tableGensinPiZ_lutmem_0_to_sumAHighB_uid403_polyEvalsinPiZ_0_q);
sumAHighB_uid403_polyEvalsinPiZ_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid402_polyEvalsinPiZ_b(12)) & highBBits_uid402_polyEvalsinPiZ_b);
sumAHighB_uid403_polyEvalsinPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid403_polyEvalsinPiZ_a) + SIGNED(sumAHighB_uid403_polyEvalsinPiZ_b));
sumAHighB_uid403_polyEvalsinPiZ_q <= sumAHighB_uid403_polyEvalsinPiZ_o(21 downto 0);
--lowRangeB_uid401_polyEvalsinPiZ(BITSELECT,400)@26
lowRangeB_uid401_polyEvalsinPiZ_in <= prodXYTruncFR_uid587_pT1_uid400_polyEvalsinPiZ_b(0 downto 0);
lowRangeB_uid401_polyEvalsinPiZ_b <= lowRangeB_uid401_polyEvalsinPiZ_in(0 downto 0);
--s1_uid401_uid404_polyEvalsinPiZ(BITJOIN,403)@26
s1_uid401_uid404_polyEvalsinPiZ_q <= sumAHighB_uid403_polyEvalsinPiZ_q & lowRangeB_uid401_polyEvalsinPiZ_b;
--reg_s1_uid401_uid404_polyEvalsinPiZ_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_1(REG,705)@26
reg_s1_uid401_uid404_polyEvalsinPiZ_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid401_uid404_polyEvalsinPiZ_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid401_uid404_polyEvalsinPiZ_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_1_q <= s1_uid401_uid404_polyEvalsinPiZ_q;
END IF;
END IF;
END PROCESS;
--ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_nor(LOGICAL,1805)
ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_nor_a <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_notEnable_q;
ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_nor_b <= ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_sticky_ena_q;
ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_nor_q <= not (ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_nor_a or ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_nor_b);
--ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_sticky_ena(REG,1806)
ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_nor_q = "1") THEN
ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_sticky_ena_q <= ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_enaAnd(LOGICAL,1807)
ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_enaAnd_a <= ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_sticky_ena_q;
ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_enaAnd_b <= en;
ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_enaAnd_q <= ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_enaAnd_a and ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_enaAnd_b;
--ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_inputreg(DELAY,1795)
ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => zPsinPiZ_uid83_fpTanTest_b, xout => ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_replace_mem(DUALMEM,1796)
ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_replace_mem_ia <= ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_inputreg_q;
ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_replace_mem_aa <= ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdreg_q;
ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_replace_mem_ab <= ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdmux_q;
ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_replace_mem_iq,
address_a => ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_replace_mem_aa,
data_a => ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_replace_mem_ia
);
ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_replace_mem_reset0 <= areset;
ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_replace_mem_q <= ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_replace_mem_iq(14 downto 0);
--reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0(REG,704)@26
reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_q <= ld_zPsinPiZ_uid83_fpTanTest_b_to_reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid589_pT2_uid406_polyEvalsinPiZ(MULT,588)@27
prodXY_uid589_pT2_uid406_polyEvalsinPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid589_pT2_uid406_polyEvalsinPiZ_a),16)) * SIGNED(prodXY_uid589_pT2_uid406_polyEvalsinPiZ_b);
prodXY_uid589_pT2_uid406_polyEvalsinPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid589_pT2_uid406_polyEvalsinPiZ_a <= (others => '0');
prodXY_uid589_pT2_uid406_polyEvalsinPiZ_b <= (others => '0');
prodXY_uid589_pT2_uid406_polyEvalsinPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid589_pT2_uid406_polyEvalsinPiZ_a <= reg_zPsinPiZ_uid83_fpTanTest_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_0_q;
prodXY_uid589_pT2_uid406_polyEvalsinPiZ_b <= reg_s1_uid401_uid404_polyEvalsinPiZ_0_to_prodXY_uid589_pT2_uid406_polyEvalsinPiZ_1_q;
prodXY_uid589_pT2_uid406_polyEvalsinPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid589_pT2_uid406_polyEvalsinPiZ_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid589_pT2_uid406_polyEvalsinPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid589_pT2_uid406_polyEvalsinPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid589_pT2_uid406_polyEvalsinPiZ_q <= prodXY_uid589_pT2_uid406_polyEvalsinPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid590_pT2_uid406_polyEvalsinPiZ(BITSELECT,589)@30
prodXYTruncFR_uid590_pT2_uid406_polyEvalsinPiZ_in <= prodXY_uid589_pT2_uid406_polyEvalsinPiZ_q;
prodXYTruncFR_uid590_pT2_uid406_polyEvalsinPiZ_b <= prodXYTruncFR_uid590_pT2_uid406_polyEvalsinPiZ_in(37 downto 14);
--highBBits_uid408_polyEvalsinPiZ(BITSELECT,407)@30
highBBits_uid408_polyEvalsinPiZ_in <= prodXYTruncFR_uid590_pT2_uid406_polyEvalsinPiZ_b;
highBBits_uid408_polyEvalsinPiZ_b <= highBBits_uid408_polyEvalsinPiZ_in(23 downto 2);
--ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_nor(LOGICAL,1818)
ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_nor_a <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_notEnable_q;
ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_nor_b <= ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_nor_q <= not (ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_nor_a or ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_nor_b);
--ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_sticky_ena(REG,1819)
ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_nor_q = "1") THEN
ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_sticky_ena_q <= ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_enaAnd(LOGICAL,1820)
ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_enaAnd_a <= ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_enaAnd_b <= en;
ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_enaAnd_q <= ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_enaAnd_a and ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_enaAnd_b;
--ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_inputreg(DELAY,1808)
ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addr_uid80_fpTanTest_b, xout => ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_replace_mem(DUALMEM,1809)
ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_replace_mem_ia <= ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_inputreg_q;
ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_replace_mem_aa <= ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdreg_q;
ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_replace_mem_ab <= ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdmux_q;
ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_replace_mem_iq,
address_a => ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_replace_mem_aa,
data_a => ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_replace_mem_ia
);
ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_replace_mem_q <= ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0(REG,706)@26
reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_q <= ld_addr_uid80_fpTanTest_b_to_reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid387_tableGensinPiZ_lutmem(DUALMEM,639)@27
memoryC0_uid387_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC0_uid387_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC0_uid387_tableGensinPiZ_lutmem_ab <= reg_addr_uid80_fpTanTest_0_to_memoryC0_uid387_tableGensinPiZ_lutmem_0_q;
memoryC0_uid387_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_tan_s5_memoryC0_uid387_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid387_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid387_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid387_tableGensinPiZ_lutmem_iq,
address_a => memoryC0_uid387_tableGensinPiZ_lutmem_aa,
data_a => memoryC0_uid387_tableGensinPiZ_lutmem_ia
);
memoryC0_uid387_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC0_uid387_tableGensinPiZ_lutmem_q <= memoryC0_uid387_tableGensinPiZ_lutmem_iq(29 downto 0);
--reg_memoryC0_uid387_tableGensinPiZ_lutmem_0_to_sumAHighB_uid409_polyEvalsinPiZ_0(REG,707)@29
reg_memoryC0_uid387_tableGensinPiZ_lutmem_0_to_sumAHighB_uid409_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid387_tableGensinPiZ_lutmem_0_to_sumAHighB_uid409_polyEvalsinPiZ_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid387_tableGensinPiZ_lutmem_0_to_sumAHighB_uid409_polyEvalsinPiZ_0_q <= memoryC0_uid387_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid409_polyEvalsinPiZ(ADD,408)@30
sumAHighB_uid409_polyEvalsinPiZ_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid387_tableGensinPiZ_lutmem_0_to_sumAHighB_uid409_polyEvalsinPiZ_0_q(29)) & reg_memoryC0_uid387_tableGensinPiZ_lutmem_0_to_sumAHighB_uid409_polyEvalsinPiZ_0_q);
sumAHighB_uid409_polyEvalsinPiZ_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid408_polyEvalsinPiZ_b(21)) & highBBits_uid408_polyEvalsinPiZ_b);
sumAHighB_uid409_polyEvalsinPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid409_polyEvalsinPiZ_a) + SIGNED(sumAHighB_uid409_polyEvalsinPiZ_b));
sumAHighB_uid409_polyEvalsinPiZ_q <= sumAHighB_uid409_polyEvalsinPiZ_o(30 downto 0);
--lowRangeB_uid407_polyEvalsinPiZ(BITSELECT,406)@30
lowRangeB_uid407_polyEvalsinPiZ_in <= prodXYTruncFR_uid590_pT2_uid406_polyEvalsinPiZ_b(1 downto 0);
lowRangeB_uid407_polyEvalsinPiZ_b <= lowRangeB_uid407_polyEvalsinPiZ_in(1 downto 0);
--s2_uid407_uid410_polyEvalsinPiZ(BITJOIN,409)@30
s2_uid407_uid410_polyEvalsinPiZ_q <= sumAHighB_uid409_polyEvalsinPiZ_q & lowRangeB_uid407_polyEvalsinPiZ_b;
--polyEvalSigsinPiZ_uid85_fpTanTest(BITSELECT,84)@30
polyEvalSigsinPiZ_uid85_fpTanTest_in <= s2_uid407_uid410_polyEvalsinPiZ_q(30 downto 0);
polyEvalSigsinPiZ_uid85_fpTanTest_b <= polyEvalSigsinPiZ_uid85_fpTanTest_in(30 downto 5);
--ld_sinXIsXRR_uid42_fpTanTest_n_to_multSinOp2_uid90_fpTanTest_b(DELAY,832)@14
ld_sinXIsXRR_uid42_fpTanTest_n_to_multSinOp2_uid90_fpTanTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => sinXIsXRR_uid42_fpTanTest_n, xout => ld_sinXIsXRR_uid42_fpTanTest_n_to_multSinOp2_uid90_fpTanTest_b_q, ena => en(0), clk => clk, aclr => areset );
--multSinOp2_uid90_fpTanTest(MUX,89)@30
multSinOp2_uid90_fpTanTest_s <= ld_sinXIsXRR_uid42_fpTanTest_n_to_multSinOp2_uid90_fpTanTest_b_q;
multSinOp2_uid90_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSinOp2_uid90_fpTanTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE multSinOp2_uid90_fpTanTest_s IS
WHEN "0" => multSinOp2_uid90_fpTanTest_q <= polyEvalSigsinPiZ_uid85_fpTanTest_b;
WHEN "1" => multSinOp2_uid90_fpTanTest_q <= ld_oFracXRRSmallXRR_uid89_fpTanTest_b_to_multSinOp2_uid90_fpTanTest_d_replace_mem_q;
WHEN OTHERS => multSinOp2_uid90_fpTanTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_nor(LOGICAL,1576)
ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_nor_a <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_notEnable_q;
ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_nor_b <= ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_sticky_ena_q;
ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_nor_q <= not (ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_nor_a or ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_nor_b);
--ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_sticky_ena(REG,1577)
ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_nor_q = "1") THEN
ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_sticky_ena_q <= ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_enaAnd(LOGICAL,1578)
ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_enaAnd_a <= ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_sticky_ena_q;
ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_enaAnd_b <= en;
ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_enaAnd_q <= ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_enaAnd_a and ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_enaAnd_b;
--cPi_uid70_fpTanTest(CONSTANT,69)
cPi_uid70_fpTanTest_q <= "11001001000011111101101011";
--LeftShiftStage263dto0_uid303_alignedZSin_uid66_fpTanTest(BITSELECT,302)@25
LeftShiftStage263dto0_uid303_alignedZSin_uid66_fpTanTest_in <= leftShiftStage2_uid301_alignedZSin_uid66_fpTanTest_q(63 downto 0);
LeftShiftStage263dto0_uid303_alignedZSin_uid66_fpTanTest_b <= LeftShiftStage263dto0_uid303_alignedZSin_uid66_fpTanTest_in(63 downto 0);
--leftShiftStage3Idx1_uid304_alignedZSin_uid66_fpTanTest(BITJOIN,303)@25
leftShiftStage3Idx1_uid304_alignedZSin_uid66_fpTanTest_q <= LeftShiftStage263dto0_uid303_alignedZSin_uid66_fpTanTest_b & GND_q;
--ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_nor(LOGICAL,1689)
ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_nor_a <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_notEnable_q;
ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_nor_b <= ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_sticky_ena_q;
ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_nor_q <= not (ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_nor_a or ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_nor_b);
--ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_sticky_ena(REG,1690)
ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_nor_q = "1") THEN
ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_sticky_ena_q <= ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_enaAnd(LOGICAL,1691)
ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_enaAnd_a <= ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_sticky_ena_q;
ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_enaAnd_b <= en;
ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_enaAnd_q <= ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_enaAnd_a and ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_enaAnd_b;
--X32dto0_uid274_alignedZSin_uid66_fpTanTest(BITSELECT,273)@19
X32dto0_uid274_alignedZSin_uid66_fpTanTest_in <= zSin_uid59_fpTanTest_q(32 downto 0);
X32dto0_uid274_alignedZSin_uid66_fpTanTest_b <= X32dto0_uid274_alignedZSin_uid66_fpTanTest_in(32 downto 0);
--ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_inputreg(DELAY,1681)
ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => X32dto0_uid274_alignedZSin_uid66_fpTanTest_b, xout => ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_replace_mem(DUALMEM,1682)
ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_replace_mem_ia <= ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_inputreg_q;
ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_replace_mem_aa <= ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdreg_q;
ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_replace_mem_ab <= ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdmux_q;
ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 1,
numwords_a => 2,
width_b => 33,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_replace_mem_iq,
address_a => ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_replace_mem_aa,
data_a => ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_replace_mem_ia
);
ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_replace_mem_reset0 <= areset;
ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_replace_mem_q <= ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_replace_mem_iq(32 downto 0);
--leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest(BITJOIN,274)@23
leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_q <= ld_X32dto0_uid274_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_b_replace_mem_q & zs_uid237_lzcZSin_uid65_fpTanTest_q;
--ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_nor(LOGICAL,1700)
ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_nor_a <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_notEnable_q;
ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_nor_b <= ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_sticky_ena_q;
ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_nor_q <= not (ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_nor_a or ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_nor_b);
--ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_sticky_ena(REG,1701)
ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_nor_q = "1") THEN
ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_sticky_ena_q <= ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_enaAnd(LOGICAL,1702)
ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_enaAnd_a <= ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_sticky_ena_q;
ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_enaAnd_b <= en;
ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_enaAnd_q <= ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_enaAnd_a and ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_enaAnd_b;
--ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_inputreg(DELAY,1692)
ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => zSin_uid59_fpTanTest_q, xout => ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_replace_mem(DUALMEM,1693)
ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_replace_mem_ia <= ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_inputreg_q;
ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_replace_mem_aa <= ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdreg_q;
ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_replace_mem_ab <= ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdmux_q;
ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 65,
widthad_a => 1,
numwords_a => 2,
width_b => 65,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_replace_mem_iq,
address_a => ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_replace_mem_aa,
data_a => ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_replace_mem_ia
);
ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_replace_mem_reset0 <= areset;
ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_replace_mem_q <= ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_replace_mem_iq(64 downto 0);
--rVStage_uid230_lzcZSin_uid65_fpTanTest(BITSELECT,229)@19
rVStage_uid230_lzcZSin_uid65_fpTanTest_in <= zSin_uid59_fpTanTest_q;
rVStage_uid230_lzcZSin_uid65_fpTanTest_b <= rVStage_uid230_lzcZSin_uid65_fpTanTest_in(64 downto 1);
--vCount_uid231_lzcZSin_uid65_fpTanTest(LOGICAL,230)@19
vCount_uid231_lzcZSin_uid65_fpTanTest_a <= rVStage_uid230_lzcZSin_uid65_fpTanTest_b;
vCount_uid231_lzcZSin_uid65_fpTanTest_b <= zs_uid229_lzcZSin_uid65_fpTanTest_q;
vCount_uid231_lzcZSin_uid65_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid231_lzcZSin_uid65_fpTanTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid231_lzcZSin_uid65_fpTanTest_a = vCount_uid231_lzcZSin_uid65_fpTanTest_b) THEN
vCount_uid231_lzcZSin_uid65_fpTanTest_q <= "1";
ELSE
vCount_uid231_lzcZSin_uid65_fpTanTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid231_lzcZSin_uid65_fpTanTest_q_to_r_uid270_lzcZSin_uid65_fpTanTest_g(DELAY,1019)@20
ld_vCount_uid231_lzcZSin_uid65_fpTanTest_q_to_r_uid270_lzcZSin_uid65_fpTanTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => vCount_uid231_lzcZSin_uid65_fpTanTest_q, xout => ld_vCount_uid231_lzcZSin_uid65_fpTanTest_q_to_r_uid270_lzcZSin_uid65_fpTanTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid233_lzcZSin_uid65_fpTanTest(BITSELECT,232)@19
vStage_uid233_lzcZSin_uid65_fpTanTest_in <= zSin_uid59_fpTanTest_q(0 downto 0);
vStage_uid233_lzcZSin_uid65_fpTanTest_b <= vStage_uid233_lzcZSin_uid65_fpTanTest_in(0 downto 0);
--ld_vStage_uid233_lzcZSin_uid65_fpTanTest_b_to_cStage_uid234_lzcZSin_uid65_fpTanTest_b(DELAY,977)@19
ld_vStage_uid233_lzcZSin_uid65_fpTanTest_b_to_cStage_uid234_lzcZSin_uid65_fpTanTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vStage_uid233_lzcZSin_uid65_fpTanTest_b, xout => ld_vStage_uid233_lzcZSin_uid65_fpTanTest_b_to_cStage_uid234_lzcZSin_uid65_fpTanTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cStage_uid234_lzcZSin_uid65_fpTanTest(BITJOIN,233)@20
cStage_uid234_lzcZSin_uid65_fpTanTest_q <= ld_vStage_uid233_lzcZSin_uid65_fpTanTest_b_to_cStage_uid234_lzcZSin_uid65_fpTanTest_b_q & mO_uid232_lzcZSin_uid65_fpTanTest_q;
--ld_rVStage_uid230_lzcZSin_uid65_fpTanTest_b_to_vStagei_uid236_lzcZSin_uid65_fpTanTest_c(DELAY,979)@19
ld_rVStage_uid230_lzcZSin_uid65_fpTanTest_b_to_vStagei_uid236_lzcZSin_uid65_fpTanTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid230_lzcZSin_uid65_fpTanTest_b, xout => ld_rVStage_uid230_lzcZSin_uid65_fpTanTest_b_to_vStagei_uid236_lzcZSin_uid65_fpTanTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid236_lzcZSin_uid65_fpTanTest(MUX,235)@20
vStagei_uid236_lzcZSin_uid65_fpTanTest_s <= vCount_uid231_lzcZSin_uid65_fpTanTest_q;
vStagei_uid236_lzcZSin_uid65_fpTanTest: PROCESS (vStagei_uid236_lzcZSin_uid65_fpTanTest_s, en, ld_rVStage_uid230_lzcZSin_uid65_fpTanTest_b_to_vStagei_uid236_lzcZSin_uid65_fpTanTest_c_q, cStage_uid234_lzcZSin_uid65_fpTanTest_q)
BEGIN
CASE vStagei_uid236_lzcZSin_uid65_fpTanTest_s IS
WHEN "0" => vStagei_uid236_lzcZSin_uid65_fpTanTest_q <= ld_rVStage_uid230_lzcZSin_uid65_fpTanTest_b_to_vStagei_uid236_lzcZSin_uid65_fpTanTest_c_q;
WHEN "1" => vStagei_uid236_lzcZSin_uid65_fpTanTest_q <= cStage_uid234_lzcZSin_uid65_fpTanTest_q;
WHEN OTHERS => vStagei_uid236_lzcZSin_uid65_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid238_lzcZSin_uid65_fpTanTest(BITSELECT,237)@20
rVStage_uid238_lzcZSin_uid65_fpTanTest_in <= vStagei_uid236_lzcZSin_uid65_fpTanTest_q;
rVStage_uid238_lzcZSin_uid65_fpTanTest_b <= rVStage_uid238_lzcZSin_uid65_fpTanTest_in(63 downto 32);
--vCount_uid239_lzcZSin_uid65_fpTanTest(LOGICAL,238)@20
vCount_uid239_lzcZSin_uid65_fpTanTest_a <= rVStage_uid238_lzcZSin_uid65_fpTanTest_b;
vCount_uid239_lzcZSin_uid65_fpTanTest_b <= zs_uid237_lzcZSin_uid65_fpTanTest_q;
vCount_uid239_lzcZSin_uid65_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid239_lzcZSin_uid65_fpTanTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid239_lzcZSin_uid65_fpTanTest_a = vCount_uid239_lzcZSin_uid65_fpTanTest_b) THEN
vCount_uid239_lzcZSin_uid65_fpTanTest_q <= "1";
ELSE
vCount_uid239_lzcZSin_uid65_fpTanTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid239_lzcZSin_uid65_fpTanTest_q_to_r_uid270_lzcZSin_uid65_fpTanTest_f(DELAY,1018)@21
ld_vCount_uid239_lzcZSin_uid65_fpTanTest_q_to_r_uid270_lzcZSin_uid65_fpTanTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid239_lzcZSin_uid65_fpTanTest_q, xout => ld_vCount_uid239_lzcZSin_uid65_fpTanTest_q_to_r_uid270_lzcZSin_uid65_fpTanTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid240_lzcZSin_uid65_fpTanTest(BITSELECT,239)@20
vStage_uid240_lzcZSin_uid65_fpTanTest_in <= vStagei_uid236_lzcZSin_uid65_fpTanTest_q(31 downto 0);
vStage_uid240_lzcZSin_uid65_fpTanTest_b <= vStage_uid240_lzcZSin_uid65_fpTanTest_in(31 downto 0);
--ld_vStage_uid240_lzcZSin_uid65_fpTanTest_b_to_vStagei_uid242_lzcZSin_uid65_fpTanTest_d(DELAY,986)@20
ld_vStage_uid240_lzcZSin_uid65_fpTanTest_b_to_vStagei_uid242_lzcZSin_uid65_fpTanTest_d : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => vStage_uid240_lzcZSin_uid65_fpTanTest_b, xout => ld_vStage_uid240_lzcZSin_uid65_fpTanTest_b_to_vStagei_uid242_lzcZSin_uid65_fpTanTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_rVStage_uid238_lzcZSin_uid65_fpTanTest_b_to_vStagei_uid242_lzcZSin_uid65_fpTanTest_c(DELAY,985)@20
ld_rVStage_uid238_lzcZSin_uid65_fpTanTest_b_to_vStagei_uid242_lzcZSin_uid65_fpTanTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid238_lzcZSin_uid65_fpTanTest_b, xout => ld_rVStage_uid238_lzcZSin_uid65_fpTanTest_b_to_vStagei_uid242_lzcZSin_uid65_fpTanTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid242_lzcZSin_uid65_fpTanTest(MUX,241)@21
vStagei_uid242_lzcZSin_uid65_fpTanTest_s <= vCount_uid239_lzcZSin_uid65_fpTanTest_q;
vStagei_uid242_lzcZSin_uid65_fpTanTest: PROCESS (vStagei_uid242_lzcZSin_uid65_fpTanTest_s, en, ld_rVStage_uid238_lzcZSin_uid65_fpTanTest_b_to_vStagei_uid242_lzcZSin_uid65_fpTanTest_c_q, ld_vStage_uid240_lzcZSin_uid65_fpTanTest_b_to_vStagei_uid242_lzcZSin_uid65_fpTanTest_d_q)
BEGIN
CASE vStagei_uid242_lzcZSin_uid65_fpTanTest_s IS
WHEN "0" => vStagei_uid242_lzcZSin_uid65_fpTanTest_q <= ld_rVStage_uid238_lzcZSin_uid65_fpTanTest_b_to_vStagei_uid242_lzcZSin_uid65_fpTanTest_c_q;
WHEN "1" => vStagei_uid242_lzcZSin_uid65_fpTanTest_q <= ld_vStage_uid240_lzcZSin_uid65_fpTanTest_b_to_vStagei_uid242_lzcZSin_uid65_fpTanTest_d_q;
WHEN OTHERS => vStagei_uid242_lzcZSin_uid65_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid244_lzcZSin_uid65_fpTanTest(BITSELECT,243)@21
rVStage_uid244_lzcZSin_uid65_fpTanTest_in <= vStagei_uid242_lzcZSin_uid65_fpTanTest_q;
rVStage_uid244_lzcZSin_uid65_fpTanTest_b <= rVStage_uid244_lzcZSin_uid65_fpTanTest_in(31 downto 16);
--vCount_uid245_lzcZSin_uid65_fpTanTest(LOGICAL,244)@21
vCount_uid245_lzcZSin_uid65_fpTanTest_a <= rVStage_uid244_lzcZSin_uid65_fpTanTest_b;
vCount_uid245_lzcZSin_uid65_fpTanTest_b <= zs_uid243_lzcZSin_uid65_fpTanTest_q;
vCount_uid245_lzcZSin_uid65_fpTanTest_q <= "1" when vCount_uid245_lzcZSin_uid65_fpTanTest_a = vCount_uid245_lzcZSin_uid65_fpTanTest_b else "0";
--reg_vCount_uid245_lzcZSin_uid65_fpTanTest_0_to_r_uid270_lzcZSin_uid65_fpTanTest_4(REG,689)@21
reg_vCount_uid245_lzcZSin_uid65_fpTanTest_0_to_r_uid270_lzcZSin_uid65_fpTanTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid245_lzcZSin_uid65_fpTanTest_0_to_r_uid270_lzcZSin_uid65_fpTanTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid245_lzcZSin_uid65_fpTanTest_0_to_r_uid270_lzcZSin_uid65_fpTanTest_4_q <= vCount_uid245_lzcZSin_uid65_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid245_lzcZSin_uid65_fpTanTest_0_to_r_uid270_lzcZSin_uid65_fpTanTest_4_q_to_r_uid270_lzcZSin_uid65_fpTanTest_e(DELAY,1017)@22
ld_reg_vCount_uid245_lzcZSin_uid65_fpTanTest_0_to_r_uid270_lzcZSin_uid65_fpTanTest_4_q_to_r_uid270_lzcZSin_uid65_fpTanTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid245_lzcZSin_uid65_fpTanTest_0_to_r_uid270_lzcZSin_uid65_fpTanTest_4_q, xout => ld_reg_vCount_uid245_lzcZSin_uid65_fpTanTest_0_to_r_uid270_lzcZSin_uid65_fpTanTest_4_q_to_r_uid270_lzcZSin_uid65_fpTanTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid246_lzcZSin_uid65_fpTanTest(BITSELECT,245)@21
vStage_uid246_lzcZSin_uid65_fpTanTest_in <= vStagei_uid242_lzcZSin_uid65_fpTanTest_q(15 downto 0);
vStage_uid246_lzcZSin_uid65_fpTanTest_b <= vStage_uid246_lzcZSin_uid65_fpTanTest_in(15 downto 0);
--vStagei_uid248_lzcZSin_uid65_fpTanTest(MUX,247)@21
vStagei_uid248_lzcZSin_uid65_fpTanTest_s <= vCount_uid245_lzcZSin_uid65_fpTanTest_q;
vStagei_uid248_lzcZSin_uid65_fpTanTest: PROCESS (vStagei_uid248_lzcZSin_uid65_fpTanTest_s, en, rVStage_uid244_lzcZSin_uid65_fpTanTest_b, vStage_uid246_lzcZSin_uid65_fpTanTest_b)
BEGIN
CASE vStagei_uid248_lzcZSin_uid65_fpTanTest_s IS
WHEN "0" => vStagei_uid248_lzcZSin_uid65_fpTanTest_q <= rVStage_uid244_lzcZSin_uid65_fpTanTest_b;
WHEN "1" => vStagei_uid248_lzcZSin_uid65_fpTanTest_q <= vStage_uid246_lzcZSin_uid65_fpTanTest_b;
WHEN OTHERS => vStagei_uid248_lzcZSin_uid65_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid250_lzcZSin_uid65_fpTanTest(BITSELECT,249)@21
rVStage_uid250_lzcZSin_uid65_fpTanTest_in <= vStagei_uid248_lzcZSin_uid65_fpTanTest_q;
rVStage_uid250_lzcZSin_uid65_fpTanTest_b <= rVStage_uid250_lzcZSin_uid65_fpTanTest_in(15 downto 8);
--reg_rVStage_uid250_lzcZSin_uid65_fpTanTest_0_to_vCount_uid251_lzcZSin_uid65_fpTanTest_1(REG,684)@21
reg_rVStage_uid250_lzcZSin_uid65_fpTanTest_0_to_vCount_uid251_lzcZSin_uid65_fpTanTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid250_lzcZSin_uid65_fpTanTest_0_to_vCount_uid251_lzcZSin_uid65_fpTanTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid250_lzcZSin_uid65_fpTanTest_0_to_vCount_uid251_lzcZSin_uid65_fpTanTest_1_q <= rVStage_uid250_lzcZSin_uid65_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid251_lzcZSin_uid65_fpTanTest(LOGICAL,250)@22
vCount_uid251_lzcZSin_uid65_fpTanTest_a <= reg_rVStage_uid250_lzcZSin_uid65_fpTanTest_0_to_vCount_uid251_lzcZSin_uid65_fpTanTest_1_q;
vCount_uid251_lzcZSin_uid65_fpTanTest_b <= cstAllZWE_uid8_fpTanTest_q;
vCount_uid251_lzcZSin_uid65_fpTanTest_q <= "1" when vCount_uid251_lzcZSin_uid65_fpTanTest_a = vCount_uid251_lzcZSin_uid65_fpTanTest_b else "0";
--ld_vCount_uid251_lzcZSin_uid65_fpTanTest_q_to_r_uid270_lzcZSin_uid65_fpTanTest_d(DELAY,1016)@22
ld_vCount_uid251_lzcZSin_uid65_fpTanTest_q_to_r_uid270_lzcZSin_uid65_fpTanTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid251_lzcZSin_uid65_fpTanTest_q, xout => ld_vCount_uid251_lzcZSin_uid65_fpTanTest_q_to_r_uid270_lzcZSin_uid65_fpTanTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid252_lzcZSin_uid65_fpTanTest(BITSELECT,251)@21
vStage_uid252_lzcZSin_uid65_fpTanTest_in <= vStagei_uid248_lzcZSin_uid65_fpTanTest_q(7 downto 0);
vStage_uid252_lzcZSin_uid65_fpTanTest_b <= vStage_uid252_lzcZSin_uid65_fpTanTest_in(7 downto 0);
--reg_vStage_uid252_lzcZSin_uid65_fpTanTest_0_to_vStagei_uid254_lzcZSin_uid65_fpTanTest_3(REG,686)@21
reg_vStage_uid252_lzcZSin_uid65_fpTanTest_0_to_vStagei_uid254_lzcZSin_uid65_fpTanTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid252_lzcZSin_uid65_fpTanTest_0_to_vStagei_uid254_lzcZSin_uid65_fpTanTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid252_lzcZSin_uid65_fpTanTest_0_to_vStagei_uid254_lzcZSin_uid65_fpTanTest_3_q <= vStage_uid252_lzcZSin_uid65_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid254_lzcZSin_uid65_fpTanTest(MUX,253)@22
vStagei_uid254_lzcZSin_uid65_fpTanTest_s <= vCount_uid251_lzcZSin_uid65_fpTanTest_q;
vStagei_uid254_lzcZSin_uid65_fpTanTest: PROCESS (vStagei_uid254_lzcZSin_uid65_fpTanTest_s, en, reg_rVStage_uid250_lzcZSin_uid65_fpTanTest_0_to_vCount_uid251_lzcZSin_uid65_fpTanTest_1_q, reg_vStage_uid252_lzcZSin_uid65_fpTanTest_0_to_vStagei_uid254_lzcZSin_uid65_fpTanTest_3_q)
BEGIN
CASE vStagei_uid254_lzcZSin_uid65_fpTanTest_s IS
WHEN "0" => vStagei_uid254_lzcZSin_uid65_fpTanTest_q <= reg_rVStage_uid250_lzcZSin_uid65_fpTanTest_0_to_vCount_uid251_lzcZSin_uid65_fpTanTest_1_q;
WHEN "1" => vStagei_uid254_lzcZSin_uid65_fpTanTest_q <= reg_vStage_uid252_lzcZSin_uid65_fpTanTest_0_to_vStagei_uid254_lzcZSin_uid65_fpTanTest_3_q;
WHEN OTHERS => vStagei_uid254_lzcZSin_uid65_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid256_lzcZSin_uid65_fpTanTest(BITSELECT,255)@22
rVStage_uid256_lzcZSin_uid65_fpTanTest_in <= vStagei_uid254_lzcZSin_uid65_fpTanTest_q;
rVStage_uid256_lzcZSin_uid65_fpTanTest_b <= rVStage_uid256_lzcZSin_uid65_fpTanTest_in(7 downto 4);
--vCount_uid257_lzcZSin_uid65_fpTanTest(LOGICAL,256)@22
vCount_uid257_lzcZSin_uid65_fpTanTest_a <= rVStage_uid256_lzcZSin_uid65_fpTanTest_b;
vCount_uid257_lzcZSin_uid65_fpTanTest_b <= leftShiftStage0Idx1Pad4_uid206_fxpX_uid48_fpTanTest_q;
vCount_uid257_lzcZSin_uid65_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid257_lzcZSin_uid65_fpTanTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid257_lzcZSin_uid65_fpTanTest_a = vCount_uid257_lzcZSin_uid65_fpTanTest_b) THEN
vCount_uid257_lzcZSin_uid65_fpTanTest_q <= "1";
ELSE
vCount_uid257_lzcZSin_uid65_fpTanTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid258_lzcZSin_uid65_fpTanTest(BITSELECT,257)@22
vStage_uid258_lzcZSin_uid65_fpTanTest_in <= vStagei_uid254_lzcZSin_uid65_fpTanTest_q(3 downto 0);
vStage_uid258_lzcZSin_uid65_fpTanTest_b <= vStage_uid258_lzcZSin_uid65_fpTanTest_in(3 downto 0);
--reg_vStage_uid258_lzcZSin_uid65_fpTanTest_0_to_vStagei_uid260_lzcZSin_uid65_fpTanTest_3(REG,688)@22
reg_vStage_uid258_lzcZSin_uid65_fpTanTest_0_to_vStagei_uid260_lzcZSin_uid65_fpTanTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid258_lzcZSin_uid65_fpTanTest_0_to_vStagei_uid260_lzcZSin_uid65_fpTanTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid258_lzcZSin_uid65_fpTanTest_0_to_vStagei_uid260_lzcZSin_uid65_fpTanTest_3_q <= vStage_uid258_lzcZSin_uid65_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid256_lzcZSin_uid65_fpTanTest_0_to_vStagei_uid260_lzcZSin_uid65_fpTanTest_2(REG,687)@22
reg_rVStage_uid256_lzcZSin_uid65_fpTanTest_0_to_vStagei_uid260_lzcZSin_uid65_fpTanTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid256_lzcZSin_uid65_fpTanTest_0_to_vStagei_uid260_lzcZSin_uid65_fpTanTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid256_lzcZSin_uid65_fpTanTest_0_to_vStagei_uid260_lzcZSin_uid65_fpTanTest_2_q <= rVStage_uid256_lzcZSin_uid65_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid260_lzcZSin_uid65_fpTanTest(MUX,259)@23
vStagei_uid260_lzcZSin_uid65_fpTanTest_s <= vCount_uid257_lzcZSin_uid65_fpTanTest_q;
vStagei_uid260_lzcZSin_uid65_fpTanTest: PROCESS (vStagei_uid260_lzcZSin_uid65_fpTanTest_s, en, reg_rVStage_uid256_lzcZSin_uid65_fpTanTest_0_to_vStagei_uid260_lzcZSin_uid65_fpTanTest_2_q, reg_vStage_uid258_lzcZSin_uid65_fpTanTest_0_to_vStagei_uid260_lzcZSin_uid65_fpTanTest_3_q)
BEGIN
CASE vStagei_uid260_lzcZSin_uid65_fpTanTest_s IS
WHEN "0" => vStagei_uid260_lzcZSin_uid65_fpTanTest_q <= reg_rVStage_uid256_lzcZSin_uid65_fpTanTest_0_to_vStagei_uid260_lzcZSin_uid65_fpTanTest_2_q;
WHEN "1" => vStagei_uid260_lzcZSin_uid65_fpTanTest_q <= reg_vStage_uid258_lzcZSin_uid65_fpTanTest_0_to_vStagei_uid260_lzcZSin_uid65_fpTanTest_3_q;
WHEN OTHERS => vStagei_uid260_lzcZSin_uid65_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid262_lzcZSin_uid65_fpTanTest(BITSELECT,261)@23
rVStage_uid262_lzcZSin_uid65_fpTanTest_in <= vStagei_uid260_lzcZSin_uid65_fpTanTest_q;
rVStage_uid262_lzcZSin_uid65_fpTanTest_b <= rVStage_uid262_lzcZSin_uid65_fpTanTest_in(3 downto 2);
--vCount_uid263_lzcZSin_uid65_fpTanTest(LOGICAL,262)@23
vCount_uid263_lzcZSin_uid65_fpTanTest_a <= rVStage_uid262_lzcZSin_uid65_fpTanTest_b;
vCount_uid263_lzcZSin_uid65_fpTanTest_b <= leftShiftStage1Idx2Pad2_uid220_fxpX_uid48_fpTanTest_q;
vCount_uid263_lzcZSin_uid65_fpTanTest_q <= "1" when vCount_uid263_lzcZSin_uid65_fpTanTest_a = vCount_uid263_lzcZSin_uid65_fpTanTest_b else "0";
--vStage_uid264_lzcZSin_uid65_fpTanTest(BITSELECT,263)@23
vStage_uid264_lzcZSin_uid65_fpTanTest_in <= vStagei_uid260_lzcZSin_uid65_fpTanTest_q(1 downto 0);
vStage_uid264_lzcZSin_uid65_fpTanTest_b <= vStage_uid264_lzcZSin_uid65_fpTanTest_in(1 downto 0);
--vStagei_uid266_lzcZSin_uid65_fpTanTest(MUX,265)@23
vStagei_uid266_lzcZSin_uid65_fpTanTest_s <= vCount_uid263_lzcZSin_uid65_fpTanTest_q;
vStagei_uid266_lzcZSin_uid65_fpTanTest: PROCESS (vStagei_uid266_lzcZSin_uid65_fpTanTest_s, en, rVStage_uid262_lzcZSin_uid65_fpTanTest_b, vStage_uid264_lzcZSin_uid65_fpTanTest_b)
BEGIN
CASE vStagei_uid266_lzcZSin_uid65_fpTanTest_s IS
WHEN "0" => vStagei_uid266_lzcZSin_uid65_fpTanTest_q <= rVStage_uid262_lzcZSin_uid65_fpTanTest_b;
WHEN "1" => vStagei_uid266_lzcZSin_uid65_fpTanTest_q <= vStage_uid264_lzcZSin_uid65_fpTanTest_b;
WHEN OTHERS => vStagei_uid266_lzcZSin_uid65_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid268_lzcZSin_uid65_fpTanTest(BITSELECT,267)@23
rVStage_uid268_lzcZSin_uid65_fpTanTest_in <= vStagei_uid266_lzcZSin_uid65_fpTanTest_q;
rVStage_uid268_lzcZSin_uid65_fpTanTest_b <= rVStage_uid268_lzcZSin_uid65_fpTanTest_in(1 downto 1);
--vCount_uid269_lzcZSin_uid65_fpTanTest(LOGICAL,268)@23
vCount_uid269_lzcZSin_uid65_fpTanTest_a <= rVStage_uid268_lzcZSin_uid65_fpTanTest_b;
vCount_uid269_lzcZSin_uid65_fpTanTest_b <= GND_q;
vCount_uid269_lzcZSin_uid65_fpTanTest_q <= "1" when vCount_uid269_lzcZSin_uid65_fpTanTest_a = vCount_uid269_lzcZSin_uid65_fpTanTest_b else "0";
--r_uid270_lzcZSin_uid65_fpTanTest(BITJOIN,269)@23
r_uid270_lzcZSin_uid65_fpTanTest_q <= ld_vCount_uid231_lzcZSin_uid65_fpTanTest_q_to_r_uid270_lzcZSin_uid65_fpTanTest_g_q & ld_vCount_uid239_lzcZSin_uid65_fpTanTest_q_to_r_uid270_lzcZSin_uid65_fpTanTest_f_q & ld_reg_vCount_uid245_lzcZSin_uid65_fpTanTest_0_to_r_uid270_lzcZSin_uid65_fpTanTest_4_q_to_r_uid270_lzcZSin_uid65_fpTanTest_e_q & ld_vCount_uid251_lzcZSin_uid65_fpTanTest_q_to_r_uid270_lzcZSin_uid65_fpTanTest_d_q & vCount_uid257_lzcZSin_uid65_fpTanTest_q & vCount_uid263_lzcZSin_uid65_fpTanTest_q & vCount_uid269_lzcZSin_uid65_fpTanTest_q;
--leftShiftStageSel6Dto5_uid278_alignedZSin_uid66_fpTanTest(BITSELECT,277)@23
leftShiftStageSel6Dto5_uid278_alignedZSin_uid66_fpTanTest_in <= r_uid270_lzcZSin_uid65_fpTanTest_q;
leftShiftStageSel6Dto5_uid278_alignedZSin_uid66_fpTanTest_b <= leftShiftStageSel6Dto5_uid278_alignedZSin_uid66_fpTanTest_in(6 downto 5);
--leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest(MUX,278)@23
leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_s <= leftShiftStageSel6Dto5_uid278_alignedZSin_uid66_fpTanTest_b;
leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest: PROCESS (leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_s, en, ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_replace_mem_q, leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_q, cstZwShiftPwFRR_uid35_fpTanTest_q, cstZwShiftPwFRR_uid35_fpTanTest_q)
BEGIN
CASE leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_s IS
WHEN "00" => leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_q <= ld_zSin_uid59_fpTanTest_q_to_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_q <= leftShiftStage0Idx1_uid275_alignedZSin_uid66_fpTanTest_q;
WHEN "10" => leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_q <= cstZwShiftPwFRR_uid35_fpTanTest_q;
WHEN "11" => leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_q <= cstZwShiftPwFRR_uid35_fpTanTest_q;
WHEN OTHERS => leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage040dto0_uid287_alignedZSin_uid66_fpTanTest(BITSELECT,286)@23
LeftShiftStage040dto0_uid287_alignedZSin_uid66_fpTanTest_in <= leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_q(40 downto 0);
LeftShiftStage040dto0_uid287_alignedZSin_uid66_fpTanTest_b <= LeftShiftStage040dto0_uid287_alignedZSin_uid66_fpTanTest_in(40 downto 0);
--leftShiftStage1Idx3_uid288_alignedZSin_uid66_fpTanTest(BITJOIN,287)@23
leftShiftStage1Idx3_uid288_alignedZSin_uid66_fpTanTest_q <= LeftShiftStage040dto0_uid287_alignedZSin_uid66_fpTanTest_b & leftShiftStage1Idx3Pad24_uid286_alignedZSin_uid66_fpTanTest_q;
--reg_leftShiftStage1Idx3_uid288_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_5(REG,694)@23
reg_leftShiftStage1Idx3_uid288_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid288_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid288_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_5_q <= leftShiftStage1Idx3_uid288_alignedZSin_uid66_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage048dto0_uid284_alignedZSin_uid66_fpTanTest(BITSELECT,283)@23
LeftShiftStage048dto0_uid284_alignedZSin_uid66_fpTanTest_in <= leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_q(48 downto 0);
LeftShiftStage048dto0_uid284_alignedZSin_uid66_fpTanTest_b <= LeftShiftStage048dto0_uid284_alignedZSin_uid66_fpTanTest_in(48 downto 0);
--leftShiftStage1Idx2_uid285_alignedZSin_uid66_fpTanTest(BITJOIN,284)@23
leftShiftStage1Idx2_uid285_alignedZSin_uid66_fpTanTest_q <= LeftShiftStage048dto0_uid284_alignedZSin_uid66_fpTanTest_b & zs_uid243_lzcZSin_uid65_fpTanTest_q;
--reg_leftShiftStage1Idx2_uid285_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_4(REG,693)@23
reg_leftShiftStage1Idx2_uid285_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid285_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid285_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_4_q <= leftShiftStage1Idx2_uid285_alignedZSin_uid66_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage056dto0_uid281_alignedZSin_uid66_fpTanTest(BITSELECT,280)@23
LeftShiftStage056dto0_uid281_alignedZSin_uid66_fpTanTest_in <= leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_q(56 downto 0);
LeftShiftStage056dto0_uid281_alignedZSin_uid66_fpTanTest_b <= LeftShiftStage056dto0_uid281_alignedZSin_uid66_fpTanTest_in(56 downto 0);
--leftShiftStage1Idx1_uid282_alignedZSin_uid66_fpTanTest(BITJOIN,281)@23
leftShiftStage1Idx1_uid282_alignedZSin_uid66_fpTanTest_q <= LeftShiftStage056dto0_uid281_alignedZSin_uid66_fpTanTest_b & cstAllZWE_uid8_fpTanTest_q;
--reg_leftShiftStage1Idx1_uid282_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_3(REG,692)@23
reg_leftShiftStage1Idx1_uid282_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid282_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid282_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_3_q <= leftShiftStage1Idx1_uid282_alignedZSin_uid66_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_2(REG,691)@23
reg_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_2_q <= leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid289_alignedZSin_uid66_fpTanTest(BITSELECT,288)@23
leftShiftStageSel4Dto3_uid289_alignedZSin_uid66_fpTanTest_in <= r_uid270_lzcZSin_uid65_fpTanTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid289_alignedZSin_uid66_fpTanTest_b <= leftShiftStageSel4Dto3_uid289_alignedZSin_uid66_fpTanTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid289_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_1(REG,690)@23
reg_leftShiftStageSel4Dto3_uid289_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid289_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid289_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_1_q <= leftShiftStageSel4Dto3_uid289_alignedZSin_uid66_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest(MUX,289)@24
leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_s <= reg_leftShiftStageSel4Dto3_uid289_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_1_q;
leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest: PROCESS (leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_s, en, reg_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_2_q, reg_leftShiftStage1Idx1_uid282_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_3_q, reg_leftShiftStage1Idx2_uid285_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_4_q, reg_leftShiftStage1Idx3_uid288_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_5_q)
BEGIN
CASE leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_s IS
WHEN "00" => leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_q <= reg_leftShiftStage0_uid279_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_2_q;
WHEN "01" => leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_q <= reg_leftShiftStage1Idx1_uid282_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_3_q;
WHEN "10" => leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_q <= reg_leftShiftStage1Idx2_uid285_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_4_q;
WHEN "11" => leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_q <= reg_leftShiftStage1Idx3_uid288_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_5_q;
WHEN OTHERS => leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid298_alignedZSin_uid66_fpTanTest(BITSELECT,297)@24
LeftShiftStage158dto0_uid298_alignedZSin_uid66_fpTanTest_in <= leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_q(58 downto 0);
LeftShiftStage158dto0_uid298_alignedZSin_uid66_fpTanTest_b <= LeftShiftStage158dto0_uid298_alignedZSin_uid66_fpTanTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid298_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage2Idx3_uid299_alignedZSin_uid66_fpTanTest_b(DELAY,1043)@24
ld_LeftShiftStage158dto0_uid298_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage2Idx3_uid299_alignedZSin_uid66_fpTanTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid298_alignedZSin_uid66_fpTanTest_b, xout => ld_LeftShiftStage158dto0_uid298_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage2Idx3_uid299_alignedZSin_uid66_fpTanTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid299_alignedZSin_uid66_fpTanTest(BITJOIN,298)@25
leftShiftStage2Idx3_uid299_alignedZSin_uid66_fpTanTest_q <= ld_LeftShiftStage158dto0_uid298_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage2Idx3_uid299_alignedZSin_uid66_fpTanTest_b_q & leftShiftStage2Idx3Pad6_uid297_alignedZSin_uid66_fpTanTest_q;
--LeftShiftStage160dto0_uid295_alignedZSin_uid66_fpTanTest(BITSELECT,294)@24
LeftShiftStage160dto0_uid295_alignedZSin_uid66_fpTanTest_in <= leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_q(60 downto 0);
LeftShiftStage160dto0_uid295_alignedZSin_uid66_fpTanTest_b <= LeftShiftStage160dto0_uid295_alignedZSin_uid66_fpTanTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid295_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage2Idx2_uid296_alignedZSin_uid66_fpTanTest_b(DELAY,1041)@24
ld_LeftShiftStage160dto0_uid295_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage2Idx2_uid296_alignedZSin_uid66_fpTanTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid295_alignedZSin_uid66_fpTanTest_b, xout => ld_LeftShiftStage160dto0_uid295_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage2Idx2_uid296_alignedZSin_uid66_fpTanTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid296_alignedZSin_uid66_fpTanTest(BITJOIN,295)@25
leftShiftStage2Idx2_uid296_alignedZSin_uid66_fpTanTest_q <= ld_LeftShiftStage160dto0_uid295_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage2Idx2_uid296_alignedZSin_uid66_fpTanTest_b_q & leftShiftStage0Idx1Pad4_uid206_fxpX_uid48_fpTanTest_q;
--LeftShiftStage162dto0_uid292_alignedZSin_uid66_fpTanTest(BITSELECT,291)@24
LeftShiftStage162dto0_uid292_alignedZSin_uid66_fpTanTest_in <= leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_q(62 downto 0);
LeftShiftStage162dto0_uid292_alignedZSin_uid66_fpTanTest_b <= LeftShiftStage162dto0_uid292_alignedZSin_uid66_fpTanTest_in(62 downto 0);
--ld_LeftShiftStage162dto0_uid292_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage2Idx1_uid293_alignedZSin_uid66_fpTanTest_b(DELAY,1039)@24
ld_LeftShiftStage162dto0_uid292_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage2Idx1_uid293_alignedZSin_uid66_fpTanTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage162dto0_uid292_alignedZSin_uid66_fpTanTest_b, xout => ld_LeftShiftStage162dto0_uid292_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage2Idx1_uid293_alignedZSin_uid66_fpTanTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid293_alignedZSin_uid66_fpTanTest(BITJOIN,292)@25
leftShiftStage2Idx1_uid293_alignedZSin_uid66_fpTanTest_q <= ld_LeftShiftStage162dto0_uid292_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage2Idx1_uid293_alignedZSin_uid66_fpTanTest_b_q & leftShiftStage1Idx2Pad2_uid220_fxpX_uid48_fpTanTest_q;
--reg_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage2_uid301_alignedZSin_uid66_fpTanTest_2(REG,696)@24
reg_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage2_uid301_alignedZSin_uid66_fpTanTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage2_uid301_alignedZSin_uid66_fpTanTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage2_uid301_alignedZSin_uid66_fpTanTest_2_q <= leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid300_alignedZSin_uid66_fpTanTest(BITSELECT,299)@23
leftShiftStageSel2Dto1_uid300_alignedZSin_uid66_fpTanTest_in <= r_uid270_lzcZSin_uid65_fpTanTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid300_alignedZSin_uid66_fpTanTest_b <= leftShiftStageSel2Dto1_uid300_alignedZSin_uid66_fpTanTest_in(2 downto 1);
--ld_leftShiftStageSel2Dto1_uid300_alignedZSin_uid66_fpTanTest_b_to_reg_leftShiftStageSel2Dto1_uid300_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage2_uid301_alignedZSin_uid66_fpTanTest_1_a(DELAY,1449)@23
ld_leftShiftStageSel2Dto1_uid300_alignedZSin_uid66_fpTanTest_b_to_reg_leftShiftStageSel2Dto1_uid300_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage2_uid301_alignedZSin_uid66_fpTanTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel2Dto1_uid300_alignedZSin_uid66_fpTanTest_b, xout => ld_leftShiftStageSel2Dto1_uid300_alignedZSin_uid66_fpTanTest_b_to_reg_leftShiftStageSel2Dto1_uid300_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage2_uid301_alignedZSin_uid66_fpTanTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel2Dto1_uid300_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage2_uid301_alignedZSin_uid66_fpTanTest_1(REG,695)@24
reg_leftShiftStageSel2Dto1_uid300_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage2_uid301_alignedZSin_uid66_fpTanTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid300_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage2_uid301_alignedZSin_uid66_fpTanTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid300_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage2_uid301_alignedZSin_uid66_fpTanTest_1_q <= ld_leftShiftStageSel2Dto1_uid300_alignedZSin_uid66_fpTanTest_b_to_reg_leftShiftStageSel2Dto1_uid300_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage2_uid301_alignedZSin_uid66_fpTanTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid301_alignedZSin_uid66_fpTanTest(MUX,300)@25
leftShiftStage2_uid301_alignedZSin_uid66_fpTanTest_s <= reg_leftShiftStageSel2Dto1_uid300_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage2_uid301_alignedZSin_uid66_fpTanTest_1_q;
leftShiftStage2_uid301_alignedZSin_uid66_fpTanTest: PROCESS (leftShiftStage2_uid301_alignedZSin_uid66_fpTanTest_s, en, reg_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage2_uid301_alignedZSin_uid66_fpTanTest_2_q, leftShiftStage2Idx1_uid293_alignedZSin_uid66_fpTanTest_q, leftShiftStage2Idx2_uid296_alignedZSin_uid66_fpTanTest_q, leftShiftStage2Idx3_uid299_alignedZSin_uid66_fpTanTest_q)
BEGIN
CASE leftShiftStage2_uid301_alignedZSin_uid66_fpTanTest_s IS
WHEN "00" => leftShiftStage2_uid301_alignedZSin_uid66_fpTanTest_q <= reg_leftShiftStage1_uid290_alignedZSin_uid66_fpTanTest_0_to_leftShiftStage2_uid301_alignedZSin_uid66_fpTanTest_2_q;
WHEN "01" => leftShiftStage2_uid301_alignedZSin_uid66_fpTanTest_q <= leftShiftStage2Idx1_uid293_alignedZSin_uid66_fpTanTest_q;
WHEN "10" => leftShiftStage2_uid301_alignedZSin_uid66_fpTanTest_q <= leftShiftStage2Idx2_uid296_alignedZSin_uid66_fpTanTest_q;
WHEN "11" => leftShiftStage2_uid301_alignedZSin_uid66_fpTanTest_q <= leftShiftStage2Idx3_uid299_alignedZSin_uid66_fpTanTest_q;
WHEN OTHERS => leftShiftStage2_uid301_alignedZSin_uid66_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid305_alignedZSin_uid66_fpTanTest(BITSELECT,304)@23
leftShiftStageSel0Dto0_uid305_alignedZSin_uid66_fpTanTest_in <= r_uid270_lzcZSin_uid65_fpTanTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid305_alignedZSin_uid66_fpTanTest_b <= leftShiftStageSel0Dto0_uid305_alignedZSin_uid66_fpTanTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid305_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage3_uid306_alignedZSin_uid66_fpTanTest_b(DELAY,1053)@23
ld_leftShiftStageSel0Dto0_uid305_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage3_uid306_alignedZSin_uid66_fpTanTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid305_alignedZSin_uid66_fpTanTest_b, xout => ld_leftShiftStageSel0Dto0_uid305_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage3_uid306_alignedZSin_uid66_fpTanTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid306_alignedZSin_uid66_fpTanTest(MUX,305)@25
leftShiftStage3_uid306_alignedZSin_uid66_fpTanTest_s <= ld_leftShiftStageSel0Dto0_uid305_alignedZSin_uid66_fpTanTest_b_to_leftShiftStage3_uid306_alignedZSin_uid66_fpTanTest_b_q;
leftShiftStage3_uid306_alignedZSin_uid66_fpTanTest: PROCESS (leftShiftStage3_uid306_alignedZSin_uid66_fpTanTest_s, en, leftShiftStage2_uid301_alignedZSin_uid66_fpTanTest_q, leftShiftStage3Idx1_uid304_alignedZSin_uid66_fpTanTest_q)
BEGIN
CASE leftShiftStage3_uid306_alignedZSin_uid66_fpTanTest_s IS
WHEN "0" => leftShiftStage3_uid306_alignedZSin_uid66_fpTanTest_q <= leftShiftStage2_uid301_alignedZSin_uid66_fpTanTest_q;
WHEN "1" => leftShiftStage3_uid306_alignedZSin_uid66_fpTanTest_q <= leftShiftStage3Idx1_uid304_alignedZSin_uid66_fpTanTest_q;
WHEN OTHERS => leftShiftStage3_uid306_alignedZSin_uid66_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--pHigh_uid71_fpTanTest(BITSELECT,70)@25
pHigh_uid71_fpTanTest_in <= leftShiftStage3_uid306_alignedZSin_uid66_fpTanTest_q;
pHigh_uid71_fpTanTest_b <= pHigh_uid71_fpTanTest_in(64 downto 39);
--reg_pHigh_uid71_fpTanTest_0_to_p_uid72_fpTanTest_2(REG,698)@25
reg_pHigh_uid71_fpTanTest_0_to_p_uid72_fpTanTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pHigh_uid71_fpTanTest_0_to_p_uid72_fpTanTest_2_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pHigh_uid71_fpTanTest_0_to_p_uid72_fpTanTest_2_q <= pHigh_uid71_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--ld_sinXIsXRR_uid42_fpTanTest_n_to_reg_sinXIsXRR_uid42_fpTanTest_2_to_p_uid72_fpTanTest_1_a(DELAY,1451)@14
ld_sinXIsXRR_uid42_fpTanTest_n_to_reg_sinXIsXRR_uid42_fpTanTest_2_to_p_uid72_fpTanTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => sinXIsXRR_uid42_fpTanTest_n, xout => ld_sinXIsXRR_uid42_fpTanTest_n_to_reg_sinXIsXRR_uid42_fpTanTest_2_to_p_uid72_fpTanTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sinXIsXRR_uid42_fpTanTest_2_to_p_uid72_fpTanTest_1(REG,697)@25
reg_sinXIsXRR_uid42_fpTanTest_2_to_p_uid72_fpTanTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid42_fpTanTest_2_to_p_uid72_fpTanTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid42_fpTanTest_2_to_p_uid72_fpTanTest_1_q <= ld_sinXIsXRR_uid42_fpTanTest_n_to_reg_sinXIsXRR_uid42_fpTanTest_2_to_p_uid72_fpTanTest_1_a_q;
END IF;
END IF;
END PROCESS;
--p_uid72_fpTanTest(MUX,71)@26
p_uid72_fpTanTest_s <= reg_sinXIsXRR_uid42_fpTanTest_2_to_p_uid72_fpTanTest_1_q;
p_uid72_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p_uid72_fpTanTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE p_uid72_fpTanTest_s IS
WHEN "0" => p_uid72_fpTanTest_q <= reg_pHigh_uid71_fpTanTest_0_to_p_uid72_fpTanTest_2_q;
WHEN "1" => p_uid72_fpTanTest_q <= cPi_uid70_fpTanTest_q;
WHEN OTHERS => p_uid72_fpTanTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_inputreg(DELAY,1568)
ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => p_uid72_fpTanTest_q, xout => ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_mem(DUALMEM,1569)
ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_mem_ia <= ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_inputreg_q;
ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_mem_aa <= ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdreg_q;
ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_mem_ab <= ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdmux_q;
ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 1,
numwords_a => 2,
width_b => 26,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_mem_iq,
address_a => ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_mem_aa,
data_a => ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_mem_ia
);
ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_mem_reset0 <= areset;
ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_mem_q <= ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_mem_iq(25 downto 0);
--mulSin_uid91_fpTanTest(MULT,90)@31
mulSin_uid91_fpTanTest_pr <= UNSIGNED(mulSin_uid91_fpTanTest_a) * UNSIGNED(mulSin_uid91_fpTanTest_b);
mulSin_uid91_fpTanTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulSin_uid91_fpTanTest_a <= (others => '0');
mulSin_uid91_fpTanTest_b <= (others => '0');
mulSin_uid91_fpTanTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulSin_uid91_fpTanTest_a <= ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_mem_q;
mulSin_uid91_fpTanTest_b <= multSinOp2_uid90_fpTanTest_q;
mulSin_uid91_fpTanTest_s1 <= STD_LOGIC_VECTOR(mulSin_uid91_fpTanTest_pr);
END IF;
END IF;
END PROCESS;
mulSin_uid91_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulSin_uid91_fpTanTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulSin_uid91_fpTanTest_q <= mulSin_uid91_fpTanTest_s1;
END IF;
END IF;
END PROCESS;
--normBitSin_uid92_fpTanTest(BITSELECT,91)@34
normBitSin_uid92_fpTanTest_in <= mulSin_uid91_fpTanTest_q;
normBitSin_uid92_fpTanTest_b <= normBitSin_uid92_fpTanTest_in(51 downto 51);
--join_uid98_fpTanTest(BITJOIN,97)@34
join_uid98_fpTanTest_q <= reg_sinXIsXRR_uid42_fpTanTest_2_to_join_uid98_fpTanTest_1_q & normBitSin_uid92_fpTanTest_b;
--sinRndOp_uid99_uid100_fpTanTest(BITJOIN,99)@34
sinRndOp_uid99_uid100_fpTanTest_q <= join_uid98_fpTanTest_q & cstAllZWF_uid7_fpTanTest_q & VCC_q;
--ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_nor(LOGICAL,1589)
ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_nor_a <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_notEnable_q;
ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_nor_b <= ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_sticky_ena_q;
ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_nor_q <= not (ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_nor_a or ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_nor_b);
--ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_sticky_ena(REG,1590)
ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_nor_q = "1") THEN
ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_sticky_ena_q <= ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_enaAnd(LOGICAL,1591)
ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_enaAnd_a <= ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_sticky_ena_q;
ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_enaAnd_b <= en;
ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_enaAnd_q <= ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_enaAnd_a and ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_enaAnd_b;
--ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_nor(LOGICAL,1539)
ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_nor_a <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_notEnable_q;
ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_nor_b <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_sticky_ena_q;
ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_nor_q <= not (ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_nor_a or ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_nor_b);
--ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_sticky_ena(REG,1540)
ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_nor_q = "1") THEN
ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_sticky_ena_q <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_enaAnd(LOGICAL,1541)
ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_enaAnd_a <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_sticky_ena_q;
ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_enaAnd_b <= en;
ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_enaAnd_q <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_enaAnd_a and ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_enaAnd_b;
--ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_inputreg(DELAY,1529)
ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expXRR_uid39_fpTanTest_b, xout => ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_mem(DUALMEM,1530)
ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_mem_ia <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_inputreg_q;
ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_mem_aa <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_rdreg_q;
ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_mem_ab <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_rdmux_q;
ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_mem_iq,
address_a => ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_mem_aa,
data_a => ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_mem_ia
);
ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_mem_reset0 <= areset;
ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_mem_q <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_mem_iq(7 downto 0);
--reg_r_uid270_lzcZSin_uid65_fpTanTest_0_to_expSinHC_uid73_fpTanTest_1(REG,708)@23
reg_r_uid270_lzcZSin_uid65_fpTanTest_0_to_expSinHC_uid73_fpTanTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid270_lzcZSin_uid65_fpTanTest_0_to_expSinHC_uid73_fpTanTest_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid270_lzcZSin_uid65_fpTanTest_0_to_expSinHC_uid73_fpTanTest_1_q <= r_uid270_lzcZSin_uid65_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--expSinHC_uid73_fpTanTest(SUB,72)@24
expSinHC_uid73_fpTanTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpTanTest_q);
expSinHC_uid73_fpTanTest_b <= STD_LOGIC_VECTOR("00" & reg_r_uid270_lzcZSin_uid65_fpTanTest_0_to_expSinHC_uid73_fpTanTest_1_q);
expSinHC_uid73_fpTanTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSinHC_uid73_fpTanTest_a) - UNSIGNED(expSinHC_uid73_fpTanTest_b));
expSinHC_uid73_fpTanTest_q <= expSinHC_uid73_fpTanTest_o(8 downto 0);
--expSinHCR_uid74_fpTanTest(BITSELECT,73)@24
expSinHCR_uid74_fpTanTest_in <= expSinHC_uid73_fpTanTest_q(7 downto 0);
expSinHCR_uid74_fpTanTest_b <= expSinHCR_uid74_fpTanTest_in(7 downto 0);
--ld_sinXIsXRR_uid42_fpTanTest_n_to_reg_sinXIsXRR_uid42_fpTanTest_2_to_expPSin_uid75_fpTanTest_1_a(DELAY,1463)@14
ld_sinXIsXRR_uid42_fpTanTest_n_to_reg_sinXIsXRR_uid42_fpTanTest_2_to_expPSin_uid75_fpTanTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 9 )
PORT MAP ( xin => sinXIsXRR_uid42_fpTanTest_n, xout => ld_sinXIsXRR_uid42_fpTanTest_n_to_reg_sinXIsXRR_uid42_fpTanTest_2_to_expPSin_uid75_fpTanTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sinXIsXRR_uid42_fpTanTest_2_to_expPSin_uid75_fpTanTest_1(REG,709)@23
reg_sinXIsXRR_uid42_fpTanTest_2_to_expPSin_uid75_fpTanTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid42_fpTanTest_2_to_expPSin_uid75_fpTanTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid42_fpTanTest_2_to_expPSin_uid75_fpTanTest_1_q <= ld_sinXIsXRR_uid42_fpTanTest_n_to_reg_sinXIsXRR_uid42_fpTanTest_2_to_expPSin_uid75_fpTanTest_1_a_q;
END IF;
END IF;
END PROCESS;
--expPSin_uid75_fpTanTest(MUX,74)@24
expPSin_uid75_fpTanTest_s <= reg_sinXIsXRR_uid42_fpTanTest_2_to_expPSin_uid75_fpTanTest_1_q;
expPSin_uid75_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expPSin_uid75_fpTanTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expPSin_uid75_fpTanTest_s IS
WHEN "0" => expPSin_uid75_fpTanTest_q <= expSinHCR_uid74_fpTanTest_b;
WHEN "1" => expPSin_uid75_fpTanTest_q <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_replace_mem_q;
WHEN OTHERS => expPSin_uid75_fpTanTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_inputreg(DELAY,1579)
ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expPSin_uid75_fpTanTest_q, xout => ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_replace_mem(DUALMEM,1580)
ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_replace_mem_ia <= ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_inputreg_q;
ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_replace_mem_aa <= ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdreg_q;
ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_replace_mem_ab <= ld_reg_r_uid349_lzcZCos_uid68_fpTanTest_0_to_expHardCase_uid77_fpTanTest_1_q_to_expHardCase_uid77_fpTanTest_b_replace_rdmux_q;
ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 7,
width_b => 8,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_replace_mem_iq,
address_a => ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_replace_mem_aa,
data_a => ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_replace_mem_ia
);
ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_replace_mem_reset0 <= areset;
ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_replace_mem_q <= ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_replace_mem_iq(7 downto 0);
--fracRSinPreRndHigh_uid94_fpTanTest(BITSELECT,93)@34
fracRSinPreRndHigh_uid94_fpTanTest_in <= mulSin_uid91_fpTanTest_q(50 downto 0);
fracRSinPreRndHigh_uid94_fpTanTest_b <= fracRSinPreRndHigh_uid94_fpTanTest_in(50 downto 27);
--fracRSinPreRndLow_uid95_fpTanTest(BITSELECT,94)@34
fracRSinPreRndLow_uid95_fpTanTest_in <= mulSin_uid91_fpTanTest_q(49 downto 0);
fracRSinPreRndLow_uid95_fpTanTest_b <= fracRSinPreRndLow_uid95_fpTanTest_in(49 downto 26);
--fracRSinPreRnd_uid96_fpTanTest(MUX,95)@34
fracRSinPreRnd_uid96_fpTanTest_s <= normBitSin_uid92_fpTanTest_b;
fracRSinPreRnd_uid96_fpTanTest: PROCESS (fracRSinPreRnd_uid96_fpTanTest_s, en, fracRSinPreRndLow_uid95_fpTanTest_b, fracRSinPreRndHigh_uid94_fpTanTest_b)
BEGIN
CASE fracRSinPreRnd_uid96_fpTanTest_s IS
WHEN "0" => fracRSinPreRnd_uid96_fpTanTest_q <= fracRSinPreRndLow_uid95_fpTanTest_b;
WHEN "1" => fracRSinPreRnd_uid96_fpTanTest_q <= fracRSinPreRndHigh_uid94_fpTanTest_b;
WHEN OTHERS => fracRSinPreRnd_uid96_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracRSinPreRnd_uid97_uid97_fpTanTest(BITJOIN,96)@34
expFracRSinPreRnd_uid97_uid97_fpTanTest_q <= ld_expPSin_uid75_fpTanTest_q_to_expFracRSinPreRnd_uid97_uid97_fpTanTest_b_replace_mem_q & fracRSinPreRnd_uid96_fpTanTest_q;
--expFracRSin_uid101_fpTanTest(ADD,100)@34
expFracRSin_uid101_fpTanTest_a <= STD_LOGIC_VECTOR("0" & expFracRSinPreRnd_uid97_uid97_fpTanTest_q);
expFracRSin_uid101_fpTanTest_b <= STD_LOGIC_VECTOR("0000000" & sinRndOp_uid99_uid100_fpTanTest_q);
expFracRSin_uid101_fpTanTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRSin_uid101_fpTanTest_a) + UNSIGNED(expFracRSin_uid101_fpTanTest_b));
expFracRSin_uid101_fpTanTest_q <= expFracRSin_uid101_fpTanTest_o(32 downto 0);
--expRCompSin_uid103_fpTanTest(BITSELECT,102)@34
expRCompSin_uid103_fpTanTest_in <= expFracRSin_uid101_fpTanTest_q(31 downto 0);
expRCompSin_uid103_fpTanTest_b <= expRCompSin_uid103_fpTanTest_in(31 downto 24);
--reg_expRCompSin_uid103_fpTanTest_0_to_expRPostExcSin_uid125_fpTanTest_2(REG,712)@34
reg_expRCompSin_uid103_fpTanTest_0_to_expRPostExcSin_uid125_fpTanTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRCompSin_uid103_fpTanTest_0_to_expRPostExcSin_uid125_fpTanTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRCompSin_uid103_fpTanTest_0_to_expRPostExcSin_uid125_fpTanTest_2_q <= expRCompSin_uid103_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_nor(LOGICAL,1791)
ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_nor_a <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_notEnable_q;
ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_nor_b <= ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_sticky_ena_q;
ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_nor_q <= not (ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_nor_a or ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_nor_b);
--ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_sticky_ena(REG,1792)
ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_nor_q = "1") THEN
ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_sticky_ena_q <= ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_enaAnd(LOGICAL,1793)
ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_enaAnd_a <= ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_sticky_ena_q;
ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_enaAnd_b <= en;
ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_enaAnd_q <= ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_enaAnd_a and ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_enaAnd_b;
--expXIsZero_uid10_fpTanTest(LOGICAL,9)@0
expXIsZero_uid10_fpTanTest_a <= exp_uid9_fpTanTest_b;
expXIsZero_uid10_fpTanTest_b <= cstAllZWE_uid8_fpTanTest_q;
expXIsZero_uid10_fpTanTest_q <= "1" when expXIsZero_uid10_fpTanTest_a = expXIsZero_uid10_fpTanTest_b else "0";
--ld_expXIsZero_uid10_fpTanTest_q_to_excSelBitsSin_uid117_fpTanTest_b(DELAY,870)@0
ld_expXIsZero_uid10_fpTanTest_q_to_excSelBitsSin_uid117_fpTanTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => expXIsZero_uid10_fpTanTest_q, xout => ld_expXIsZero_uid10_fpTanTest_q_to_excSelBitsSin_uid117_fpTanTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excSelBitsSin_uid117_fpTanTest(BITJOIN,116)@17
excSelBitsSin_uid117_fpTanTest_q <= excRNaN_uid116_fpTanTest_q & ld_expXIsZero_uid10_fpTanTest_q_to_excSelBitsSin_uid117_fpTanTest_b_q & ld_sinXIsX_uid41_fpTanTest_n_to_excSelBitsSin_uid117_fpTanTest_a_q;
--ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_inputreg(DELAY,1781)
ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => excSelBitsSin_uid117_fpTanTest_q, xout => ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_replace_mem(DUALMEM,1782)
ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_replace_mem_ia <= ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_inputreg_q;
ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_replace_mem_aa <= ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdreg_q;
ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_replace_mem_ab <= ld_reg_join_uid137_fpTanTest_0_to_fracRPostExcCos_uid138_fpTanTest_1_q_to_fracRPostExcCos_uid138_fpTanTest_b_replace_rdmux_q;
ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 4,
numwords_a => 14,
width_b => 3,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_replace_mem_iq,
address_a => ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_replace_mem_aa,
data_a => ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_replace_mem_ia
);
ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_replace_mem_reset0 <= areset;
ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_replace_mem_q <= ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_replace_mem_iq(2 downto 0);
--reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0(REG,648)@33
reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_q <= ld_excSelBitsSin_uid117_fpTanTest_q_to_reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--excSelSin_uid118_fpTanTest(LOOKUP,117)@34
excSelSin_uid118_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excSelSin_uid118_fpTanTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_excSelBitsSin_uid117_fpTanTest_0_to_excSelSin_uid118_fpTanTest_0_q) IS
WHEN "000" => excSelSin_uid118_fpTanTest_q <= "00";
WHEN "001" => excSelSin_uid118_fpTanTest_q <= "01";
WHEN "010" => excSelSin_uid118_fpTanTest_q <= "10";
WHEN "011" => excSelSin_uid118_fpTanTest_q <= "10";
WHEN "100" => excSelSin_uid118_fpTanTest_q <= "11";
WHEN "101" => excSelSin_uid118_fpTanTest_q <= "11";
WHEN "110" => excSelSin_uid118_fpTanTest_q <= "00";
WHEN "111" => excSelSin_uid118_fpTanTest_q <= "00";
WHEN OTHERS =>
excSelSin_uid118_fpTanTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExcSin_uid125_fpTanTest(MUX,124)@35
expRPostExcSin_uid125_fpTanTest_s <= excSelSin_uid118_fpTanTest_q;
expRPostExcSin_uid125_fpTanTest: PROCESS (expRPostExcSin_uid125_fpTanTest_s, en, reg_expRCompSin_uid103_fpTanTest_0_to_expRPostExcSin_uid125_fpTanTest_2_q, ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_replace_mem_q, cstAllZWE_uid8_fpTanTest_q, cstAllOWE_uid6_fpTanTest_q)
BEGIN
CASE expRPostExcSin_uid125_fpTanTest_s IS
WHEN "00" => expRPostExcSin_uid125_fpTanTest_q <= reg_expRCompSin_uid103_fpTanTest_0_to_expRPostExcSin_uid125_fpTanTest_2_q;
WHEN "01" => expRPostExcSin_uid125_fpTanTest_q <= ld_exp_uid9_fpTanTest_b_to_expRPostExcSin_uid125_fpTanTest_d_replace_mem_q;
WHEN "10" => expRPostExcSin_uid125_fpTanTest_q <= cstAllZWE_uid8_fpTanTest_q;
WHEN "11" => expRPostExcSin_uid125_fpTanTest_q <= cstAllOWE_uid6_fpTanTest_q;
WHEN OTHERS => expRPostExcSin_uid125_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_nor(LOGICAL,1602)
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_nor_a <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_notEnable_q;
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_nor_b <= ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_sticky_ena_q;
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_nor_q <= not (ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_nor_a or ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_nor_b);
--ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_sticky_ena(REG,1603)
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_nor_q = "1") THEN
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_sticky_ena_q <= ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_enaAnd(LOGICAL,1604)
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_enaAnd_a <= ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_sticky_ena_q;
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_enaAnd_b <= en;
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_enaAnd_q <= ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_enaAnd_a and ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_enaAnd_b;
--ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_inputreg(DELAY,1592)
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => frac_uid13_fpTanTest_b, xout => ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_mem(DUALMEM,1593)
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_mem_ia <= ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_inputreg_q;
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_mem_aa <= ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdreg_q;
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_mem_ab <= ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_rdmux_q;
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 6,
numwords_a => 33,
width_b => 23,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_mem_iq,
address_a => ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_mem_aa,
data_a => ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_mem_ia
);
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_mem_reset0 <= areset;
ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_mem_q <= ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_mem_iq(22 downto 0);
--fracRCompSin_uid102_fpTanTest(BITSELECT,101)@34
fracRCompSin_uid102_fpTanTest_in <= expFracRSin_uid101_fpTanTest_q(23 downto 0);
fracRCompSin_uid102_fpTanTest_b <= fracRCompSin_uid102_fpTanTest_in(23 downto 1);
--reg_fracRCompSin_uid102_fpTanTest_0_to_fracRPostExcSin_uid121_fpTanTest_2(REG,711)@34
reg_fracRCompSin_uid102_fpTanTest_0_to_fracRPostExcSin_uid121_fpTanTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRCompSin_uid102_fpTanTest_0_to_fracRPostExcSin_uid121_fpTanTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRCompSin_uid102_fpTanTest_0_to_fracRPostExcSin_uid121_fpTanTest_2_q <= fracRCompSin_uid102_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--fracRPostExcSin_uid121_fpTanTest(MUX,120)@35
fracRPostExcSin_uid121_fpTanTest_s <= excSelSin_uid118_fpTanTest_q;
fracRPostExcSin_uid121_fpTanTest: PROCESS (fracRPostExcSin_uid121_fpTanTest_s, en, reg_fracRCompSin_uid102_fpTanTest_0_to_fracRPostExcSin_uid121_fpTanTest_2_q, ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_mem_q, cstAllZWF_uid7_fpTanTest_q, cstNaNwF_uid32_fpTanTest_q)
BEGIN
CASE fracRPostExcSin_uid121_fpTanTest_s IS
WHEN "00" => fracRPostExcSin_uid121_fpTanTest_q <= reg_fracRCompSin_uid102_fpTanTest_0_to_fracRPostExcSin_uid121_fpTanTest_2_q;
WHEN "01" => fracRPostExcSin_uid121_fpTanTest_q <= ld_frac_uid13_fpTanTest_b_to_fracRPostExcSin_uid121_fpTanTest_d_replace_mem_q;
WHEN "10" => fracRPostExcSin_uid121_fpTanTest_q <= cstAllZWF_uid7_fpTanTest_q;
WHEN "11" => fracRPostExcSin_uid121_fpTanTest_q <= cstNaNwF_uid32_fpTanTest_q;
WHEN OTHERS => fracRPostExcSin_uid121_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpSin_uid130_fpTanTest(BITJOIN,129)@35
fpSin_uid130_fpTanTest_q <= ld_signR_uid129_fpTanTest_q_to_fpSin_uid130_fpTanTest_c_q & expRPostExcSin_uid125_fpTanTest_q & fracRPostExcSin_uid121_fpTanTest_q;
--fracX_uid429_fpTanXComp_uid157_fpTanTest(BITSELECT,428)@35
fracX_uid429_fpTanXComp_uid157_fpTanTest_in <= fpSin_uid130_fpTanTest_q(22 downto 0);
fracX_uid429_fpTanXComp_uid157_fpTanTest_b <= fracX_uid429_fpTanXComp_uid157_fpTanTest_in(22 downto 0);
--fracXIsZero_uid443_fpTanXComp_uid157_fpTanTest(LOGICAL,442)@35
fracXIsZero_uid443_fpTanXComp_uid157_fpTanTest_a <= fracX_uid429_fpTanXComp_uid157_fpTanTest_b;
fracXIsZero_uid443_fpTanXComp_uid157_fpTanTest_b <= cstAllZWF_uid7_fpTanTest_q;
fracXIsZero_uid443_fpTanXComp_uid157_fpTanTest_q <= "1" when fracXIsZero_uid443_fpTanXComp_uid157_fpTanTest_a = fracXIsZero_uid443_fpTanXComp_uid157_fpTanTest_b else "0";
--expX_uid428_fpTanXComp_uid157_fpTanTest(BITSELECT,427)@35
expX_uid428_fpTanXComp_uid157_fpTanTest_in <= fpSin_uid130_fpTanTest_q(30 downto 0);
expX_uid428_fpTanXComp_uid157_fpTanTest_b <= expX_uid428_fpTanXComp_uid157_fpTanTest_in(30 downto 23);
--expXIsMax_uid441_fpTanXComp_uid157_fpTanTest(LOGICAL,440)@35
expXIsMax_uid441_fpTanXComp_uid157_fpTanTest_a <= expX_uid428_fpTanXComp_uid157_fpTanTest_b;
expXIsMax_uid441_fpTanXComp_uid157_fpTanTest_b <= cstAllOWE_uid6_fpTanTest_q;
expXIsMax_uid441_fpTanXComp_uid157_fpTanTest_q <= "1" when expXIsMax_uid441_fpTanXComp_uid157_fpTanTest_a = expXIsMax_uid441_fpTanXComp_uid157_fpTanTest_b else "0";
--exc_I_uid444_fpTanXComp_uid157_fpTanTest(LOGICAL,443)@35
exc_I_uid444_fpTanXComp_uid157_fpTanTest_a <= expXIsMax_uid441_fpTanXComp_uid157_fpTanTest_q;
exc_I_uid444_fpTanXComp_uid157_fpTanTest_b <= fracXIsZero_uid443_fpTanXComp_uid157_fpTanTest_q;
exc_I_uid444_fpTanXComp_uid157_fpTanTest_q <= exc_I_uid444_fpTanXComp_uid157_fpTanTest_a and exc_I_uid444_fpTanXComp_uid157_fpTanTest_b;
--excXIYI_uid510_fpTanXComp_uid157_fpTanTest(LOGICAL,509)@35
excXIYI_uid510_fpTanXComp_uid157_fpTanTest_a <= exc_I_uid444_fpTanXComp_uid157_fpTanTest_q;
excXIYI_uid510_fpTanXComp_uid157_fpTanTest_b <= exc_I_uid460_fpTanXComp_uid157_fpTanTest_q;
excXIYI_uid510_fpTanXComp_uid157_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excXIYI_uid510_fpTanXComp_uid157_fpTanTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
excXIYI_uid510_fpTanXComp_uid157_fpTanTest_q <= excXIYI_uid510_fpTanXComp_uid157_fpTanTest_a and excXIYI_uid510_fpTanXComp_uid157_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--InvFracXIsZero_uid461_fpTanXComp_uid157_fpTanTest(LOGICAL,460)@35
InvFracXIsZero_uid461_fpTanXComp_uid157_fpTanTest_a <= fracXIsZero_uid459_fpTanXComp_uid157_fpTanTest_q;
InvFracXIsZero_uid461_fpTanXComp_uid157_fpTanTest_q <= not InvFracXIsZero_uid461_fpTanXComp_uid157_fpTanTest_a;
--exc_N_uid462_fpTanXComp_uid157_fpTanTest(LOGICAL,461)@35
exc_N_uid462_fpTanXComp_uid157_fpTanTest_a <= expXIsMax_uid457_fpTanXComp_uid157_fpTanTest_q;
exc_N_uid462_fpTanXComp_uid157_fpTanTest_b <= InvFracXIsZero_uid461_fpTanXComp_uid157_fpTanTest_q;
exc_N_uid462_fpTanXComp_uid157_fpTanTest_q <= exc_N_uid462_fpTanXComp_uid157_fpTanTest_a and exc_N_uid462_fpTanXComp_uid157_fpTanTest_b;
--reg_exc_N_uid462_fpTanXComp_uid157_fpTanTest_0_to_excRNaN_uid511_fpTanXComp_uid157_fpTanTest_3(REG,773)@35
reg_exc_N_uid462_fpTanXComp_uid157_fpTanTest_0_to_excRNaN_uid511_fpTanXComp_uid157_fpTanTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_N_uid462_fpTanXComp_uid157_fpTanTest_0_to_excRNaN_uid511_fpTanXComp_uid157_fpTanTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_N_uid462_fpTanXComp_uid157_fpTanTest_0_to_excRNaN_uid511_fpTanXComp_uid157_fpTanTest_3_q <= exc_N_uid462_fpTanXComp_uid157_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--InvFracXIsZero_uid445_fpTanXComp_uid157_fpTanTest(LOGICAL,444)@35
InvFracXIsZero_uid445_fpTanXComp_uid157_fpTanTest_a <= fracXIsZero_uid443_fpTanXComp_uid157_fpTanTest_q;
InvFracXIsZero_uid445_fpTanXComp_uid157_fpTanTest_q <= not InvFracXIsZero_uid445_fpTanXComp_uid157_fpTanTest_a;
--exc_N_uid446_fpTanXComp_uid157_fpTanTest(LOGICAL,445)@35
exc_N_uid446_fpTanXComp_uid157_fpTanTest_a <= expXIsMax_uid441_fpTanXComp_uid157_fpTanTest_q;
exc_N_uid446_fpTanXComp_uid157_fpTanTest_b <= InvFracXIsZero_uid445_fpTanXComp_uid157_fpTanTest_q;
exc_N_uid446_fpTanXComp_uid157_fpTanTest_q <= exc_N_uid446_fpTanXComp_uid157_fpTanTest_a and exc_N_uid446_fpTanXComp_uid157_fpTanTest_b;
--reg_exc_N_uid446_fpTanXComp_uid157_fpTanTest_0_to_excRNaN_uid511_fpTanXComp_uid157_fpTanTest_2(REG,772)@35
reg_exc_N_uid446_fpTanXComp_uid157_fpTanTest_0_to_excRNaN_uid511_fpTanXComp_uid157_fpTanTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_N_uid446_fpTanXComp_uid157_fpTanTest_0_to_excRNaN_uid511_fpTanXComp_uid157_fpTanTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_N_uid446_fpTanXComp_uid157_fpTanTest_0_to_excRNaN_uid511_fpTanXComp_uid157_fpTanTest_2_q <= exc_N_uid446_fpTanXComp_uid157_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--expXIsZero_uid455_fpTanXComp_uid157_fpTanTest(LOGICAL,454)@35
expXIsZero_uid455_fpTanXComp_uid157_fpTanTest_a <= expY_uid431_fpTanXComp_uid157_fpTanTest_b;
expXIsZero_uid455_fpTanXComp_uid157_fpTanTest_b <= cstAllZWE_uid8_fpTanTest_q;
expXIsZero_uid455_fpTanXComp_uid157_fpTanTest_q <= "1" when expXIsZero_uid455_fpTanXComp_uid157_fpTanTest_a = expXIsZero_uid455_fpTanXComp_uid157_fpTanTest_b else "0";
--expXIsZero_uid439_fpTanXComp_uid157_fpTanTest(LOGICAL,438)@35
expXIsZero_uid439_fpTanXComp_uid157_fpTanTest_a <= expX_uid428_fpTanXComp_uid157_fpTanTest_b;
expXIsZero_uid439_fpTanXComp_uid157_fpTanTest_b <= cstAllZWE_uid8_fpTanTest_q;
expXIsZero_uid439_fpTanXComp_uid157_fpTanTest_q <= "1" when expXIsZero_uid439_fpTanXComp_uid157_fpTanTest_a = expXIsZero_uid439_fpTanXComp_uid157_fpTanTest_b else "0";
--excXZYZ_uid509_fpTanXComp_uid157_fpTanTest(LOGICAL,508)@35
excXZYZ_uid509_fpTanXComp_uid157_fpTanTest_a <= expXIsZero_uid439_fpTanXComp_uid157_fpTanTest_q;
excXZYZ_uid509_fpTanXComp_uid157_fpTanTest_b <= expXIsZero_uid455_fpTanXComp_uid157_fpTanTest_q;
excXZYZ_uid509_fpTanXComp_uid157_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excXZYZ_uid509_fpTanXComp_uid157_fpTanTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
excXZYZ_uid509_fpTanXComp_uid157_fpTanTest_q <= excXZYZ_uid509_fpTanXComp_uid157_fpTanTest_a and excXZYZ_uid509_fpTanXComp_uid157_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--excRNaN_uid511_fpTanXComp_uid157_fpTanTest(LOGICAL,510)@36
excRNaN_uid511_fpTanXComp_uid157_fpTanTest_a <= excXZYZ_uid509_fpTanXComp_uid157_fpTanTest_q;
excRNaN_uid511_fpTanXComp_uid157_fpTanTest_b <= reg_exc_N_uid446_fpTanXComp_uid157_fpTanTest_0_to_excRNaN_uid511_fpTanXComp_uid157_fpTanTest_2_q;
excRNaN_uid511_fpTanXComp_uid157_fpTanTest_c <= reg_exc_N_uid462_fpTanXComp_uid157_fpTanTest_0_to_excRNaN_uid511_fpTanXComp_uid157_fpTanTest_3_q;
excRNaN_uid511_fpTanXComp_uid157_fpTanTest_d <= excXIYI_uid510_fpTanXComp_uid157_fpTanTest_q;
excRNaN_uid511_fpTanXComp_uid157_fpTanTest_q <= excRNaN_uid511_fpTanXComp_uid157_fpTanTest_a or excRNaN_uid511_fpTanXComp_uid157_fpTanTest_b or excRNaN_uid511_fpTanXComp_uid157_fpTanTest_c or excRNaN_uid511_fpTanXComp_uid157_fpTanTest_d;
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvExcRNaN_uid522_fpTanXComp_uid157_fpTanTest(LOGICAL,521)@36
InvExcRNaN_uid522_fpTanXComp_uid157_fpTanTest_a <= excRNaN_uid511_fpTanXComp_uid157_fpTanTest_q;
InvExcRNaN_uid522_fpTanXComp_uid157_fpTanTest_q <= not InvExcRNaN_uid522_fpTanXComp_uid157_fpTanTest_a;
--signY_uid433_fpTanXComp_uid157_fpTanTest(BITSELECT,432)@35
signY_uid433_fpTanXComp_uid157_fpTanTest_in <= fpCos_uid155_fpTanTest_q;
signY_uid433_fpTanXComp_uid157_fpTanTest_b <= signY_uid433_fpTanXComp_uid157_fpTanTest_in(31 downto 31);
--signX_uid430_fpTanXComp_uid157_fpTanTest(BITSELECT,429)@35
signX_uid430_fpTanXComp_uid157_fpTanTest_in <= fpSin_uid130_fpTanTest_q;
signX_uid430_fpTanXComp_uid157_fpTanTest_b <= signX_uid430_fpTanXComp_uid157_fpTanTest_in(31 downto 31);
--signR_uid467_fpTanXComp_uid157_fpTanTest(LOGICAL,466)@35
signR_uid467_fpTanXComp_uid157_fpTanTest_a <= signX_uid430_fpTanXComp_uid157_fpTanTest_b;
signR_uid467_fpTanXComp_uid157_fpTanTest_b <= signY_uid433_fpTanXComp_uid157_fpTanTest_b;
signR_uid467_fpTanXComp_uid157_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid467_fpTanXComp_uid157_fpTanTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
signR_uid467_fpTanXComp_uid157_fpTanTest_q <= signR_uid467_fpTanXComp_uid157_fpTanTest_a xor signR_uid467_fpTanXComp_uid157_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--sRPostExc_uid523_fpTanXComp_uid157_fpTanTest(LOGICAL,522)@36
sRPostExc_uid523_fpTanXComp_uid157_fpTanTest_a <= signR_uid467_fpTanXComp_uid157_fpTanTest_q;
sRPostExc_uid523_fpTanXComp_uid157_fpTanTest_b <= InvExcRNaN_uid522_fpTanXComp_uid157_fpTanTest_q;
sRPostExc_uid523_fpTanXComp_uid157_fpTanTest_q <= sRPostExc_uid523_fpTanXComp_uid157_fpTanTest_a and sRPostExc_uid523_fpTanXComp_uid157_fpTanTest_b;
--ld_sRPostExc_uid523_fpTanXComp_uid157_fpTanTest_q_to_divR_uid524_fpTanXComp_uid157_fpTanTest_c(DELAY,1277)@36
ld_sRPostExc_uid523_fpTanXComp_uid157_fpTanTest_q_to_divR_uid524_fpTanXComp_uid157_fpTanTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => sRPostExc_uid523_fpTanXComp_uid157_fpTanTest_q, xout => ld_sRPostExc_uid523_fpTanXComp_uid157_fpTanTest_q_to_divR_uid524_fpTanXComp_uid157_fpTanTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_nor(LOGICAL,1759)
ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_nor_a <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_notEnable_q;
ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_nor_b <= ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_sticky_ena_q;
ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_nor_q <= not (ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_nor_a or ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_nor_b);
--ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_sticky_ena(REG,1760)
ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_nor_q = "1") THEN
ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_sticky_ena_q <= ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_enaAnd(LOGICAL,1761)
ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_enaAnd_a <= ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_sticky_ena_q;
ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_enaAnd_b <= en;
ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_enaAnd_q <= ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_enaAnd_a and ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_enaAnd_b;
--ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_nor(LOGICAL,1748)
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_nor_a <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_notEnable_q;
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_nor_b <= ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_sticky_ena_q;
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_nor_q <= not (ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_nor_a or ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_nor_b);
--ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_mem_top(CONSTANT,1744)
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_mem_top_q <= "01000";
--ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_cmp(LOGICAL,1745)
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_cmp_a <= ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_mem_top_q;
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdmux_q);
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_cmp_q <= "1" when ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_cmp_a = ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_cmp_b else "0";
--ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_cmpReg(REG,1746)
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_cmpReg_q <= ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_sticky_ena(REG,1749)
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_nor_q = "1") THEN
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_sticky_ena_q <= ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_enaAnd(LOGICAL,1750)
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_enaAnd_a <= ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_sticky_ena_q;
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_enaAnd_b <= en;
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_enaAnd_q <= ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_enaAnd_a and ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_enaAnd_b;
--ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_inputreg(DELAY,1738)
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid429_fpTanXComp_uid157_fpTanTest_b, xout => ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdcnt(COUNTER,1740)
-- every=1, low=0, high=8, step=1, init=1
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdcnt_i = 7 THEN
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdcnt_eq = '1') THEN
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdcnt_i <= ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdcnt_i - 8;
ELSE
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdcnt_i <= ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdcnt_i,4));
--ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdreg(REG,1741)
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdreg_q <= ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdmux(MUX,1742)
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdmux_s <= en;
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdmux: PROCESS (ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdmux_s, ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdreg_q, ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdcnt_q)
BEGIN
CASE ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdmux_s IS
WHEN "0" => ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdmux_q <= ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdreg_q;
WHEN "1" => ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdmux_q <= ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_mem(DUALMEM,1739)
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_mem_ia <= ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_inputreg_q;
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_mem_aa <= ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdreg_q;
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_mem_ab <= ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_rdmux_q;
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 4,
numwords_a => 9,
width_b => 23,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_mem_iq,
address_a => ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_mem_aa,
data_a => ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_mem_ia
);
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_mem_reset0 <= areset;
ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_mem_q <= ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_mem_iq(22 downto 0);
--lOAdded_uid477_fpTanXComp_uid157_fpTanTest(BITJOIN,476)@46
lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q <= VCC_q & ld_fracX_uid429_fpTanXComp_uid157_fpTanTest_b_to_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_a_replace_mem_q;
--ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_inputreg(DELAY,1751)
ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q, xout => ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_replace_mem(DUALMEM,1752)
ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_replace_mem_ia <= ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_inputreg_q;
ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_replace_mem_aa <= ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdreg_q;
ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_replace_mem_ab <= ld_p_uid72_fpTanTest_q_to_mulSin_uid91_fpTanTest_a_replace_rdmux_q;
ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 1,
numwords_a => 2,
width_b => 24,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_replace_mem_iq,
address_a => ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_replace_mem_aa,
data_a => ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_replace_mem_ia
);
ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_replace_mem_reset0 <= areset;
ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_replace_mem_q <= ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_replace_mem_iq(23 downto 0);
--oFracXExt_uid480_fpTanXComp_uid157_fpTanTest(BITJOIN,479)@50
oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_q <= ld_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q_to_oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_b_replace_mem_q & leftShiftStage1Idx2Pad2_uid220_fxpX_uid48_fpTanTest_q;
--reg_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid617_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_1(REG,764)@46
reg_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid617_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid617_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid617_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_1_q <= lOAdded_uid477_fpTanXComp_uid157_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--fracYAddr_uid471_fpTanXComp_uid157_fpTanTest(BITSELECT,470)@35
fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_in <= fpCos_uid155_fpTanTest_q(22 downto 0);
fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_b <= fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_in(22 downto 14);
--reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC2_uid602_invTab_lutmem_0(REG,754)@35
reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC2_uid602_invTab_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC2_uid602_invTab_lutmem_0_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC2_uid602_invTab_lutmem_0_q <= fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid602_invTab_lutmem(DUALMEM,647)@36
memoryC2_uid602_invTab_lutmem_ia <= (others => '0');
memoryC2_uid602_invTab_lutmem_aa <= (others => '0');
memoryC2_uid602_invTab_lutmem_ab <= reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC2_uid602_invTab_lutmem_0_q;
memoryC2_uid602_invTab_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 9,
numwords_a => 512,
width_b => 12,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_tan_s5_memoryC2_uid602_invTab_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid602_invTab_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid602_invTab_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid602_invTab_lutmem_iq,
address_a => memoryC2_uid602_invTab_lutmem_aa,
data_a => memoryC2_uid602_invTab_lutmem_ia
);
memoryC2_uid602_invTab_lutmem_reset0 <= areset;
memoryC2_uid602_invTab_lutmem_q <= memoryC2_uid602_invTab_lutmem_iq(11 downto 0);
--reg_memoryC2_uid602_invTab_lutmem_0_to_prodXY_uid620_pT1_uid605_invPE_1(REG,756)@38
reg_memoryC2_uid602_invTab_lutmem_0_to_prodXY_uid620_pT1_uid605_invPE_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid602_invTab_lutmem_0_to_prodXY_uid620_pT1_uid605_invPE_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid602_invTab_lutmem_0_to_prodXY_uid620_pT1_uid605_invPE_1_q <= memoryC2_uid602_invTab_lutmem_q;
END IF;
END IF;
END PROCESS;
--yPE_uid472_fpTanXComp_uid157_fpTanTest(BITSELECT,471)@35
yPE_uid472_fpTanXComp_uid157_fpTanTest_in <= fpCos_uid155_fpTanTest_q(13 downto 0);
yPE_uid472_fpTanXComp_uid157_fpTanTest_b <= yPE_uid472_fpTanXComp_uid157_fpTanTest_in(13 downto 0);
--yT1_uid604_invPE(BITSELECT,603)@35
yT1_uid604_invPE_in <= yPE_uid472_fpTanXComp_uid157_fpTanTest_b;
yT1_uid604_invPE_b <= yT1_uid604_invPE_in(13 downto 2);
--reg_yT1_uid604_invPE_0_to_prodXY_uid620_pT1_uid605_invPE_0(REG,755)@35
reg_yT1_uid604_invPE_0_to_prodXY_uid620_pT1_uid605_invPE_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid604_invPE_0_to_prodXY_uid620_pT1_uid605_invPE_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid604_invPE_0_to_prodXY_uid620_pT1_uid605_invPE_0_q <= yT1_uid604_invPE_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid604_invPE_0_to_prodXY_uid620_pT1_uid605_invPE_0_q_to_prodXY_uid620_pT1_uid605_invPE_a_inputreg(DELAY,1767)
ld_reg_yT1_uid604_invPE_0_to_prodXY_uid620_pT1_uid605_invPE_0_q_to_prodXY_uid620_pT1_uid605_invPE_a_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => reg_yT1_uid604_invPE_0_to_prodXY_uid620_pT1_uid605_invPE_0_q, xout => ld_reg_yT1_uid604_invPE_0_to_prodXY_uid620_pT1_uid605_invPE_0_q_to_prodXY_uid620_pT1_uid605_invPE_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yT1_uid604_invPE_0_to_prodXY_uid620_pT1_uid605_invPE_0_q_to_prodXY_uid620_pT1_uid605_invPE_a(DELAY,1368)@36
ld_reg_yT1_uid604_invPE_0_to_prodXY_uid620_pT1_uid605_invPE_0_q_to_prodXY_uid620_pT1_uid605_invPE_a : dspba_delay
GENERIC MAP ( width => 12, depth => 2 )
PORT MAP ( xin => ld_reg_yT1_uid604_invPE_0_to_prodXY_uid620_pT1_uid605_invPE_0_q_to_prodXY_uid620_pT1_uid605_invPE_a_inputreg_q, xout => ld_reg_yT1_uid604_invPE_0_to_prodXY_uid620_pT1_uid605_invPE_0_q_to_prodXY_uid620_pT1_uid605_invPE_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid620_pT1_uid605_invPE(MULT,619)@39
prodXY_uid620_pT1_uid605_invPE_pr <= signed(resize(UNSIGNED(prodXY_uid620_pT1_uid605_invPE_a),13)) * SIGNED(prodXY_uid620_pT1_uid605_invPE_b);
prodXY_uid620_pT1_uid605_invPE_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid620_pT1_uid605_invPE_a <= (others => '0');
prodXY_uid620_pT1_uid605_invPE_b <= (others => '0');
prodXY_uid620_pT1_uid605_invPE_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid620_pT1_uid605_invPE_a <= ld_reg_yT1_uid604_invPE_0_to_prodXY_uid620_pT1_uid605_invPE_0_q_to_prodXY_uid620_pT1_uid605_invPE_a_q;
prodXY_uid620_pT1_uid605_invPE_b <= reg_memoryC2_uid602_invTab_lutmem_0_to_prodXY_uid620_pT1_uid605_invPE_1_q;
prodXY_uid620_pT1_uid605_invPE_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid620_pT1_uid605_invPE_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid620_pT1_uid605_invPE: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid620_pT1_uid605_invPE_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid620_pT1_uid605_invPE_q <= prodXY_uid620_pT1_uid605_invPE_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid621_pT1_uid605_invPE(BITSELECT,620)@42
prodXYTruncFR_uid621_pT1_uid605_invPE_in <= prodXY_uid620_pT1_uid605_invPE_q;
prodXYTruncFR_uid621_pT1_uid605_invPE_b <= prodXYTruncFR_uid621_pT1_uid605_invPE_in(23 downto 11);
--highBBits_uid607_invPE(BITSELECT,606)@42
highBBits_uid607_invPE_in <= prodXYTruncFR_uid621_pT1_uid605_invPE_b;
highBBits_uid607_invPE_b <= highBBits_uid607_invPE_in(12 downto 1);
--ld_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_b_to_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC1_uid600_invTab_lutmem_0_a(DELAY,1511)@35
ld_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_b_to_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC1_uid600_invTab_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 9, depth => 3 )
PORT MAP ( xin => fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_b, xout => ld_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_b_to_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC1_uid600_invTab_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC1_uid600_invTab_lutmem_0(REG,757)@38
reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC1_uid600_invTab_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC1_uid600_invTab_lutmem_0_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC1_uid600_invTab_lutmem_0_q <= ld_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_b_to_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC1_uid600_invTab_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid600_invTab_lutmem(DUALMEM,646)@39
memoryC1_uid600_invTab_lutmem_ia <= (others => '0');
memoryC1_uid600_invTab_lutmem_aa <= (others => '0');
memoryC1_uid600_invTab_lutmem_ab <= reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC1_uid600_invTab_lutmem_0_q;
memoryC1_uid600_invTab_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 9,
numwords_a => 512,
width_b => 21,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_tan_s5_memoryC1_uid600_invTab_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid600_invTab_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid600_invTab_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid600_invTab_lutmem_iq,
address_a => memoryC1_uid600_invTab_lutmem_aa,
data_a => memoryC1_uid600_invTab_lutmem_ia
);
memoryC1_uid600_invTab_lutmem_reset0 <= areset;
memoryC1_uid600_invTab_lutmem_q <= memoryC1_uid600_invTab_lutmem_iq(20 downto 0);
--reg_memoryC1_uid600_invTab_lutmem_0_to_sumAHighB_uid608_invPE_0(REG,758)@41
reg_memoryC1_uid600_invTab_lutmem_0_to_sumAHighB_uid608_invPE_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid600_invTab_lutmem_0_to_sumAHighB_uid608_invPE_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid600_invTab_lutmem_0_to_sumAHighB_uid608_invPE_0_q <= memoryC1_uid600_invTab_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid608_invPE(ADD,607)@42
sumAHighB_uid608_invPE_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid600_invTab_lutmem_0_to_sumAHighB_uid608_invPE_0_q(20)) & reg_memoryC1_uid600_invTab_lutmem_0_to_sumAHighB_uid608_invPE_0_q);
sumAHighB_uid608_invPE_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid607_invPE_b(11)) & highBBits_uid607_invPE_b);
sumAHighB_uid608_invPE_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid608_invPE_a) + SIGNED(sumAHighB_uid608_invPE_b));
sumAHighB_uid608_invPE_q <= sumAHighB_uid608_invPE_o(21 downto 0);
--lowRangeB_uid606_invPE(BITSELECT,605)@42
lowRangeB_uid606_invPE_in <= prodXYTruncFR_uid621_pT1_uid605_invPE_b(0 downto 0);
lowRangeB_uid606_invPE_b <= lowRangeB_uid606_invPE_in(0 downto 0);
--s1_uid606_uid609_invPE(BITJOIN,608)@42
s1_uid606_uid609_invPE_q <= sumAHighB_uid608_invPE_q & lowRangeB_uid606_invPE_b;
--reg_s1_uid606_uid609_invPE_0_to_prodXY_uid623_pT2_uid611_invPE_1(REG,760)@42
reg_s1_uid606_uid609_invPE_0_to_prodXY_uid623_pT2_uid611_invPE_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid606_uid609_invPE_0_to_prodXY_uid623_pT2_uid611_invPE_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid606_uid609_invPE_0_to_prodXY_uid623_pT2_uid611_invPE_1_q <= s1_uid606_uid609_invPE_q;
END IF;
END IF;
END PROCESS;
--ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_nor(LOGICAL,1870)
ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_nor_a <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_notEnable_q;
ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_nor_b <= ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_sticky_ena_q;
ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_nor_q <= not (ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_nor_a or ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_nor_b);
--ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_sticky_ena(REG,1871)
ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_nor_q = "1") THEN
ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_sticky_ena_q <= ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_enaAnd(LOGICAL,1872)
ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_enaAnd_a <= ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_sticky_ena_q;
ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_enaAnd_b <= en;
ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_enaAnd_q <= ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_enaAnd_a and ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_enaAnd_b;
--ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_inputreg(DELAY,1860)
ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 14, depth => 1 )
PORT MAP ( xin => yPE_uid472_fpTanXComp_uid157_fpTanTest_b, xout => ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_replace_mem(DUALMEM,1861)
ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_replace_mem_ia <= ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_inputreg_q;
ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_replace_mem_aa <= ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdreg_q;
ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_replace_mem_ab <= ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdmux_q;
ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 14,
widthad_a => 3,
numwords_a => 5,
width_b => 14,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_replace_mem_iq,
address_a => ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_replace_mem_aa,
data_a => ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_replace_mem_ia
);
ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_replace_mem_reset0 <= areset;
ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_replace_mem_q <= ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_replace_mem_iq(13 downto 0);
--reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0(REG,759)@42
reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_q <= "00000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_q <= ld_yPE_uid472_fpTanXComp_uid157_fpTanTest_b_to_reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid623_pT2_uid611_invPE(MULT,622)@43
prodXY_uid623_pT2_uid611_invPE_pr <= signed(resize(UNSIGNED(prodXY_uid623_pT2_uid611_invPE_a),15)) * SIGNED(prodXY_uid623_pT2_uid611_invPE_b);
prodXY_uid623_pT2_uid611_invPE_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid623_pT2_uid611_invPE_a <= (others => '0');
prodXY_uid623_pT2_uid611_invPE_b <= (others => '0');
prodXY_uid623_pT2_uid611_invPE_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid623_pT2_uid611_invPE_a <= reg_yPE_uid472_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid623_pT2_uid611_invPE_0_q;
prodXY_uid623_pT2_uid611_invPE_b <= reg_s1_uid606_uid609_invPE_0_to_prodXY_uid623_pT2_uid611_invPE_1_q;
prodXY_uid623_pT2_uid611_invPE_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid623_pT2_uid611_invPE_pr,37));
END IF;
END IF;
END PROCESS;
prodXY_uid623_pT2_uid611_invPE: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid623_pT2_uid611_invPE_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid623_pT2_uid611_invPE_q <= prodXY_uid623_pT2_uid611_invPE_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid624_pT2_uid611_invPE(BITSELECT,623)@46
prodXYTruncFR_uid624_pT2_uid611_invPE_in <= prodXY_uid623_pT2_uid611_invPE_q;
prodXYTruncFR_uid624_pT2_uid611_invPE_b <= prodXYTruncFR_uid624_pT2_uid611_invPE_in(36 downto 13);
--highBBits_uid613_invPE(BITSELECT,612)@46
highBBits_uid613_invPE_in <= prodXYTruncFR_uid624_pT2_uid611_invPE_b;
highBBits_uid613_invPE_b <= highBBits_uid613_invPE_in(23 downto 2);
--ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_nor(LOGICAL,1778)
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_nor_a <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_notEnable_q;
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_nor_b <= ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_sticky_ena_q;
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_nor_q <= not (ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_nor_a or ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_nor_b);
--ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_sticky_ena(REG,1779)
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_nor_q = "1") THEN
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_sticky_ena_q <= ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_enaAnd(LOGICAL,1780)
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_enaAnd_a <= ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_sticky_ena_q;
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_enaAnd_b <= en;
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_enaAnd_q <= ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_enaAnd_a and ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_enaAnd_b;
--ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_inputreg(DELAY,1768)
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_inputreg : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC2_uid602_invTab_lutmem_0_q, xout => ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_mem(DUALMEM,1769)
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_mem_ia <= ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_inputreg_q;
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_mem_aa <= ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdreg_q;
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_mem_ab <= ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_rdmux_q;
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 9,
widthad_a => 3,
numwords_a => 5,
width_b => 9,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_mem_iq,
address_a => ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_mem_aa,
data_a => ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_mem_ia
);
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_mem_q <= ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_mem_iq(8 downto 0);
--memoryC0_uid598_invTab_lutmem(DUALMEM,645)@43
memoryC0_uid598_invTab_lutmem_ia <= (others => '0');
memoryC0_uid598_invTab_lutmem_aa <= (others => '0');
memoryC0_uid598_invTab_lutmem_ab <= ld_reg_fracYAddr_uid471_fpTanXComp_uid157_fpTanTest_0_to_memoryC0_uid598_invTab_lutmem_0_q_to_memoryC0_uid598_invTab_lutmem_a_replace_mem_q;
memoryC0_uid598_invTab_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 31,
widthad_a => 9,
numwords_a => 512,
width_b => 31,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_tan_s5_memoryC0_uid598_invTab_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid598_invTab_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid598_invTab_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid598_invTab_lutmem_iq,
address_a => memoryC0_uid598_invTab_lutmem_aa,
data_a => memoryC0_uid598_invTab_lutmem_ia
);
memoryC0_uid598_invTab_lutmem_reset0 <= areset;
memoryC0_uid598_invTab_lutmem_q <= memoryC0_uid598_invTab_lutmem_iq(30 downto 0);
--reg_memoryC0_uid598_invTab_lutmem_0_to_sumAHighB_uid614_invPE_0(REG,762)@45
reg_memoryC0_uid598_invTab_lutmem_0_to_sumAHighB_uid614_invPE_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid598_invTab_lutmem_0_to_sumAHighB_uid614_invPE_0_q <= "0000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid598_invTab_lutmem_0_to_sumAHighB_uid614_invPE_0_q <= memoryC0_uid598_invTab_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid614_invPE(ADD,613)@46
sumAHighB_uid614_invPE_a <= STD_LOGIC_VECTOR((31 downto 31 => reg_memoryC0_uid598_invTab_lutmem_0_to_sumAHighB_uid614_invPE_0_q(30)) & reg_memoryC0_uid598_invTab_lutmem_0_to_sumAHighB_uid614_invPE_0_q);
sumAHighB_uid614_invPE_b <= STD_LOGIC_VECTOR((31 downto 22 => highBBits_uid613_invPE_b(21)) & highBBits_uid613_invPE_b);
sumAHighB_uid614_invPE_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid614_invPE_a) + SIGNED(sumAHighB_uid614_invPE_b));
sumAHighB_uid614_invPE_q <= sumAHighB_uid614_invPE_o(31 downto 0);
--lowRangeB_uid612_invPE(BITSELECT,611)@46
lowRangeB_uid612_invPE_in <= prodXYTruncFR_uid624_pT2_uid611_invPE_b(1 downto 0);
lowRangeB_uid612_invPE_b <= lowRangeB_uid612_invPE_in(1 downto 0);
--s2_uid612_uid615_invPE(BITJOIN,614)@46
s2_uid612_uid615_invPE_q <= sumAHighB_uid614_invPE_q & lowRangeB_uid612_invPE_b;
--invY_uid474_fpTanXComp_uid157_fpTanTest(BITSELECT,473)@46
invY_uid474_fpTanXComp_uid157_fpTanTest_in <= s2_uid612_uid615_invPE_q(30 downto 0);
invY_uid474_fpTanXComp_uid157_fpTanTest_b <= invY_uid474_fpTanXComp_uid157_fpTanTest_in(30 downto 5);
--reg_invY_uid474_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid617_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_0(REG,763)@46
reg_invY_uid474_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid617_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_invY_uid474_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid617_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_0_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_invY_uid474_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid617_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_0_q <= invY_uid474_fpTanXComp_uid157_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid617_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest(MULT,616)@47
prodXY_uid617_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_pr <= UNSIGNED(prodXY_uid617_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_a) * UNSIGNED(prodXY_uid617_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_b);
prodXY_uid617_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid617_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_a <= (others => '0');
prodXY_uid617_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_b <= (others => '0');
prodXY_uid617_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid617_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_a <= reg_invY_uid474_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid617_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_0_q;
prodXY_uid617_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_b <= reg_lOAdded_uid477_fpTanXComp_uid157_fpTanTest_0_to_prodXY_uid617_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_1_q;
prodXY_uid617_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_s1 <= STD_LOGIC_VECTOR(prodXY_uid617_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_pr);
END IF;
END IF;
END PROCESS;
prodXY_uid617_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid617_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid617_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_q <= prodXY_uid617_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid618_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest(BITSELECT,617)@50
prodXYTruncFR_uid618_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_in <= prodXY_uid617_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_q;
prodXYTruncFR_uid618_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_b <= prodXYTruncFR_uid618_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_in(49 downto 24);
--invYO_uid475_fpTanXComp_uid157_fpTanTest(BITSELECT,474)@46
invYO_uid475_fpTanXComp_uid157_fpTanTest_in <= s2_uid612_uid615_invPE_q(31 downto 0);
invYO_uid475_fpTanXComp_uid157_fpTanTest_b <= invYO_uid475_fpTanXComp_uid157_fpTanTest_in(31 downto 31);
--fracYZero_uid434_fpTanXComp_uid157_fpTanTest(LOGICAL,433)@35
fracYZero_uid434_fpTanXComp_uid157_fpTanTest_a <= fracY_uid432_fpTanXComp_uid157_fpTanTest_b;
fracYZero_uid434_fpTanXComp_uid157_fpTanTest_b <= STD_LOGIC_VECTOR("0000000000000000000000" & GND_q);
fracYZero_uid434_fpTanXComp_uid157_fpTanTest_q <= "1" when fracYZero_uid434_fpTanXComp_uid157_fpTanTest_a = fracYZero_uid434_fpTanXComp_uid157_fpTanTest_b else "0";
--ld_fracYZero_uid434_fpTanXComp_uid157_fpTanTest_q_to_fracYPostZ_uid476_fpTanXComp_uid157_fpTanTest_a(DELAY,1208)@35
ld_fracYZero_uid434_fpTanXComp_uid157_fpTanTest_q_to_fracYPostZ_uid476_fpTanXComp_uid157_fpTanTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => fracYZero_uid434_fpTanXComp_uid157_fpTanTest_q, xout => ld_fracYZero_uid434_fpTanXComp_uid157_fpTanTest_q_to_fracYPostZ_uid476_fpTanXComp_uid157_fpTanTest_a_q, ena => en(0), clk => clk, aclr => areset );
--fracYPostZ_uid476_fpTanXComp_uid157_fpTanTest(LOGICAL,475)@46
fracYPostZ_uid476_fpTanXComp_uid157_fpTanTest_a <= ld_fracYZero_uid434_fpTanXComp_uid157_fpTanTest_q_to_fracYPostZ_uid476_fpTanXComp_uid157_fpTanTest_a_q;
fracYPostZ_uid476_fpTanXComp_uid157_fpTanTest_b <= invYO_uid475_fpTanXComp_uid157_fpTanTest_b;
fracYPostZ_uid476_fpTanXComp_uid157_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracYPostZ_uid476_fpTanXComp_uid157_fpTanTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
fracYPostZ_uid476_fpTanXComp_uid157_fpTanTest_q <= fracYPostZ_uid476_fpTanXComp_uid157_fpTanTest_a or fracYPostZ_uid476_fpTanXComp_uid157_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--ld_fracYPostZ_uid476_fpTanXComp_uid157_fpTanTest_q_to_divValPreNormTrunc_uid482_fpTanXComp_uid157_fpTanTest_b(DELAY,1212)@47
ld_fracYPostZ_uid476_fpTanXComp_uid157_fpTanTest_q_to_divValPreNormTrunc_uid482_fpTanXComp_uid157_fpTanTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => fracYPostZ_uid476_fpTanXComp_uid157_fpTanTest_q, xout => ld_fracYPostZ_uid476_fpTanXComp_uid157_fpTanTest_q_to_divValPreNormTrunc_uid482_fpTanXComp_uid157_fpTanTest_b_q, ena => en(0), clk => clk, aclr => areset );
--divValPreNormTrunc_uid482_fpTanXComp_uid157_fpTanTest(MUX,481)@50
divValPreNormTrunc_uid482_fpTanXComp_uid157_fpTanTest_s <= ld_fracYPostZ_uid476_fpTanXComp_uid157_fpTanTest_q_to_divValPreNormTrunc_uid482_fpTanXComp_uid157_fpTanTest_b_q;
divValPreNormTrunc_uid482_fpTanXComp_uid157_fpTanTest: PROCESS (divValPreNormTrunc_uid482_fpTanXComp_uid157_fpTanTest_s, en, prodXYTruncFR_uid618_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_b, oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_q)
BEGIN
CASE divValPreNormTrunc_uid482_fpTanXComp_uid157_fpTanTest_s IS
WHEN "0" => divValPreNormTrunc_uid482_fpTanXComp_uid157_fpTanTest_q <= prodXYTruncFR_uid618_prodDivPreNormProd_uid478_fpTanXComp_uid157_fpTanTest_b;
WHEN "1" => divValPreNormTrunc_uid482_fpTanXComp_uid157_fpTanTest_q <= oFracXExt_uid480_fpTanXComp_uid157_fpTanTest_q;
WHEN OTHERS => divValPreNormTrunc_uid482_fpTanXComp_uid157_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--norm_uid483_fpTanXComp_uid157_fpTanTest(BITSELECT,482)@50
norm_uid483_fpTanXComp_uid157_fpTanTest_in <= divValPreNormTrunc_uid482_fpTanXComp_uid157_fpTanTest_q;
norm_uid483_fpTanXComp_uid157_fpTanTest_b <= norm_uid483_fpTanXComp_uid157_fpTanTest_in(25 downto 25);
--ld_norm_uid483_fpTanXComp_uid157_fpTanTest_b_to_rndOp_uid489_fpTanXComp_uid157_fpTanTest_c(DELAY,1223)@50
ld_norm_uid483_fpTanXComp_uid157_fpTanTest_b_to_rndOp_uid489_fpTanXComp_uid157_fpTanTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => norm_uid483_fpTanXComp_uid157_fpTanTest_b, xout => ld_norm_uid483_fpTanXComp_uid157_fpTanTest_b_to_rndOp_uid489_fpTanXComp_uid157_fpTanTest_c_q, ena => en(0), clk => clk, aclr => areset );
--rndOp_uid489_fpTanXComp_uid157_fpTanTest(BITJOIN,488)@51
rndOp_uid489_fpTanXComp_uid157_fpTanTest_q <= ld_norm_uid483_fpTanXComp_uid157_fpTanTest_b_to_rndOp_uid489_fpTanXComp_uid157_fpTanTest_c_q & cstAllZWF_uid7_fpTanTest_q & VCC_q;
--ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_nor(LOGICAL,1735)
ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_nor_a <= ld_expXRR_uid39_fpTanTest_b_to_expPSin_uid75_fpTanTest_d_notEnable_q;
ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_nor_b <= ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_sticky_ena_q;
ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_nor_q <= not (ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_nor_a or ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_nor_b);
--ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_sticky_ena(REG,1736)
ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_nor_q = "1") THEN
ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_sticky_ena_q <= ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_enaAnd(LOGICAL,1737)
ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_enaAnd_a <= ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_sticky_ena_q;
ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_enaAnd_b <= en;
ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_enaAnd_q <= ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_enaAnd_a and ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_enaAnd_b;
--expXmY_uid468_fpTanXComp_uid157_fpTanTest(SUB,467)@35
expXmY_uid468_fpTanXComp_uid157_fpTanTest_a <= STD_LOGIC_VECTOR("0" & expX_uid428_fpTanXComp_uid157_fpTanTest_b);
expXmY_uid468_fpTanXComp_uid157_fpTanTest_b <= STD_LOGIC_VECTOR("0" & expY_uid431_fpTanXComp_uid157_fpTanTest_b);
expXmY_uid468_fpTanXComp_uid157_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expXmY_uid468_fpTanXComp_uid157_fpTanTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expXmY_uid468_fpTanXComp_uid157_fpTanTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXmY_uid468_fpTanXComp_uid157_fpTanTest_a) - UNSIGNED(expXmY_uid468_fpTanXComp_uid157_fpTanTest_b));
END IF;
END IF;
END PROCESS;
expXmY_uid468_fpTanXComp_uid157_fpTanTest_q <= expXmY_uid468_fpTanXComp_uid157_fpTanTest_o(8 downto 0);
--ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_inputreg(DELAY,1725)
ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => expXmY_uid468_fpTanXComp_uid157_fpTanTest_q, xout => ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_replace_mem(DUALMEM,1726)
ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_replace_mem_ia <= ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_inputreg_q;
ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_replace_mem_aa <= ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdreg_q;
ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_replace_mem_ab <= ld_expX_uid179_rrx_uid34_fpTanTest_b_to_finalExp_uid202_rrx_uid34_fpTanTest_d_replace_rdmux_q;
ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 9,
widthad_a => 4,
numwords_a => 11,
width_b => 9,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_replace_mem_iq,
address_a => ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_replace_mem_aa,
data_a => ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_replace_mem_ia
);
ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_replace_mem_reset0 <= areset;
ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_replace_mem_q <= ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_replace_mem_iq(8 downto 0);
--expR_uid469_fpTanXComp_uid157_fpTanTest(ADD,468)@49
expR_uid469_fpTanXComp_uid157_fpTanTest_a <= STD_LOGIC_VECTOR((10 downto 9 => ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_replace_mem_q(8)) & ld_expXmY_uid468_fpTanXComp_uid157_fpTanTest_q_to_expR_uid469_fpTanXComp_uid157_fpTanTest_a_replace_mem_q);
expR_uid469_fpTanXComp_uid157_fpTanTest_b <= STD_LOGIC_VECTOR('0' & "00" & cstBiasM1_uid23_fpTanTest_q);
expR_uid469_fpTanXComp_uid157_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expR_uid469_fpTanXComp_uid157_fpTanTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expR_uid469_fpTanXComp_uid157_fpTanTest_o <= STD_LOGIC_VECTOR(SIGNED(expR_uid469_fpTanXComp_uid157_fpTanTest_a) + SIGNED(expR_uid469_fpTanXComp_uid157_fpTanTest_b));
END IF;
END IF;
END PROCESS;
expR_uid469_fpTanXComp_uid157_fpTanTest_q <= expR_uid469_fpTanXComp_uid157_fpTanTest_o(9 downto 0);
--divValPreNormHigh_uid484_fpTanXComp_uid157_fpTanTest(BITSELECT,483)@50
divValPreNormHigh_uid484_fpTanXComp_uid157_fpTanTest_in <= divValPreNormTrunc_uid482_fpTanXComp_uid157_fpTanTest_q(24 downto 0);
divValPreNormHigh_uid484_fpTanXComp_uid157_fpTanTest_b <= divValPreNormHigh_uid484_fpTanXComp_uid157_fpTanTest_in(24 downto 1);
--divValPreNormLow_uid485_fpTanXComp_uid157_fpTanTest(BITSELECT,484)@50
divValPreNormLow_uid485_fpTanXComp_uid157_fpTanTest_in <= divValPreNormTrunc_uid482_fpTanXComp_uid157_fpTanTest_q(23 downto 0);
divValPreNormLow_uid485_fpTanXComp_uid157_fpTanTest_b <= divValPreNormLow_uid485_fpTanXComp_uid157_fpTanTest_in(23 downto 0);
--normFracRnd_uid486_fpTanXComp_uid157_fpTanTest(MUX,485)@50
normFracRnd_uid486_fpTanXComp_uid157_fpTanTest_s <= norm_uid483_fpTanXComp_uid157_fpTanTest_b;
normFracRnd_uid486_fpTanXComp_uid157_fpTanTest: PROCESS (normFracRnd_uid486_fpTanXComp_uid157_fpTanTest_s, en, divValPreNormLow_uid485_fpTanXComp_uid157_fpTanTest_b, divValPreNormHigh_uid484_fpTanXComp_uid157_fpTanTest_b)
BEGIN
CASE normFracRnd_uid486_fpTanXComp_uid157_fpTanTest_s IS
WHEN "0" => normFracRnd_uid486_fpTanXComp_uid157_fpTanTest_q <= divValPreNormLow_uid485_fpTanXComp_uid157_fpTanTest_b;
WHEN "1" => normFracRnd_uid486_fpTanXComp_uid157_fpTanTest_q <= divValPreNormHigh_uid484_fpTanXComp_uid157_fpTanTest_b;
WHEN OTHERS => normFracRnd_uid486_fpTanXComp_uid157_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracRnd_uid487_fpTanXComp_uid157_fpTanTest(BITJOIN,486)@50
expFracRnd_uid487_fpTanXComp_uid157_fpTanTest_q <= expR_uid469_fpTanXComp_uid157_fpTanTest_q & normFracRnd_uid486_fpTanXComp_uid157_fpTanTest_q;
--reg_expFracRnd_uid487_fpTanXComp_uid157_fpTanTest_0_to_expFracPostRnd_uid490_fpTanXComp_uid157_fpTanTest_0(REG,765)@50
reg_expFracRnd_uid487_fpTanXComp_uid157_fpTanTest_0_to_expFracPostRnd_uid490_fpTanXComp_uid157_fpTanTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracRnd_uid487_fpTanXComp_uid157_fpTanTest_0_to_expFracPostRnd_uid490_fpTanXComp_uid157_fpTanTest_0_q <= "0000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracRnd_uid487_fpTanXComp_uid157_fpTanTest_0_to_expFracPostRnd_uid490_fpTanXComp_uid157_fpTanTest_0_q <= expFracRnd_uid487_fpTanXComp_uid157_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--expFracPostRnd_uid490_fpTanXComp_uid157_fpTanTest(ADD,489)@51
expFracPostRnd_uid490_fpTanXComp_uid157_fpTanTest_a <= STD_LOGIC_VECTOR((35 downto 34 => reg_expFracRnd_uid487_fpTanXComp_uid157_fpTanTest_0_to_expFracPostRnd_uid490_fpTanXComp_uid157_fpTanTest_0_q(33)) & reg_expFracRnd_uid487_fpTanXComp_uid157_fpTanTest_0_to_expFracPostRnd_uid490_fpTanXComp_uid157_fpTanTest_0_q);
expFracPostRnd_uid490_fpTanXComp_uid157_fpTanTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & rndOp_uid489_fpTanXComp_uid157_fpTanTest_q);
expFracPostRnd_uid490_fpTanXComp_uid157_fpTanTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracPostRnd_uid490_fpTanXComp_uid157_fpTanTest_a) + SIGNED(expFracPostRnd_uid490_fpTanXComp_uid157_fpTanTest_b));
expFracPostRnd_uid490_fpTanXComp_uid157_fpTanTest_q <= expFracPostRnd_uid490_fpTanXComp_uid157_fpTanTest_o(34 downto 0);
--excRPreExc_uid493_fpTanXComp_uid157_fpTanTest(BITSELECT,492)@51
excRPreExc_uid493_fpTanXComp_uid157_fpTanTest_in <= expFracPostRnd_uid490_fpTanXComp_uid157_fpTanTest_q(31 downto 0);
excRPreExc_uid493_fpTanXComp_uid157_fpTanTest_b <= excRPreExc_uid493_fpTanXComp_uid157_fpTanTest_in(31 downto 24);
--ld_excRPreExc_uid493_fpTanXComp_uid157_fpTanTest_b_to_expRPostExc_uid521_fpTanXComp_uid157_fpTanTest_d(DELAY,1271)@51
ld_excRPreExc_uid493_fpTanXComp_uid157_fpTanTest_b_to_expRPostExc_uid521_fpTanXComp_uid157_fpTanTest_d : dspba_delay
GENERIC MAP ( width => 8, depth => 2 )
PORT MAP ( xin => excRPreExc_uid493_fpTanXComp_uid157_fpTanTest_b, xout => ld_excRPreExc_uid493_fpTanXComp_uid157_fpTanTest_b_to_expRPostExc_uid521_fpTanXComp_uid157_fpTanTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid511_fpTanXComp_uid157_fpTanTest_q_to_concExc_uid512_fpTanXComp_uid157_fpTanTest_c(DELAY,1266)@36
ld_excRNaN_uid511_fpTanXComp_uid157_fpTanTest_q_to_concExc_uid512_fpTanXComp_uid157_fpTanTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => excRNaN_uid511_fpTanXComp_uid157_fpTanTest_q, xout => ld_excRNaN_uid511_fpTanXComp_uid157_fpTanTest_q_to_concExc_uid512_fpTanXComp_uid157_fpTanTest_c_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid463_fpTanXComp_uid157_fpTanTest(LOGICAL,462)@35
InvExc_N_uid463_fpTanXComp_uid157_fpTanTest_a <= exc_N_uid462_fpTanXComp_uid157_fpTanTest_q;
InvExc_N_uid463_fpTanXComp_uid157_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExc_N_uid463_fpTanXComp_uid157_fpTanTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExc_N_uid463_fpTanXComp_uid157_fpTanTest_q <= not InvExc_N_uid463_fpTanXComp_uid157_fpTanTest_a;
END IF;
END PROCESS;
--InvExc_I_uid464_fpTanXComp_uid157_fpTanTest(LOGICAL,463)@35
InvExc_I_uid464_fpTanXComp_uid157_fpTanTest_a <= exc_I_uid460_fpTanXComp_uid157_fpTanTest_q;
InvExc_I_uid464_fpTanXComp_uid157_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExc_I_uid464_fpTanXComp_uid157_fpTanTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExc_I_uid464_fpTanXComp_uid157_fpTanTest_q <= not InvExc_I_uid464_fpTanXComp_uid157_fpTanTest_a;
END IF;
END PROCESS;
--InvExpXIsZero_uid465_fpTanXComp_uid157_fpTanTest(LOGICAL,464)@35
InvExpXIsZero_uid465_fpTanXComp_uid157_fpTanTest_a <= expXIsZero_uid455_fpTanXComp_uid157_fpTanTest_q;
InvExpXIsZero_uid465_fpTanXComp_uid157_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExpXIsZero_uid465_fpTanXComp_uid157_fpTanTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExpXIsZero_uid465_fpTanXComp_uid157_fpTanTest_q <= not InvExpXIsZero_uid465_fpTanXComp_uid157_fpTanTest_a;
END IF;
END PROCESS;
--exc_R_uid466_fpTanXComp_uid157_fpTanTest(LOGICAL,465)@36
exc_R_uid466_fpTanXComp_uid157_fpTanTest_a <= InvExpXIsZero_uid465_fpTanXComp_uid157_fpTanTest_q;
exc_R_uid466_fpTanXComp_uid157_fpTanTest_b <= InvExc_I_uid464_fpTanXComp_uid157_fpTanTest_q;
exc_R_uid466_fpTanXComp_uid157_fpTanTest_c <= InvExc_N_uid463_fpTanXComp_uid157_fpTanTest_q;
exc_R_uid466_fpTanXComp_uid157_fpTanTest_q <= exc_R_uid466_fpTanXComp_uid157_fpTanTest_a and exc_R_uid466_fpTanXComp_uid157_fpTanTest_b and exc_R_uid466_fpTanXComp_uid157_fpTanTest_c;
--reg_exc_I_uid444_fpTanXComp_uid157_fpTanTest_0_to_excXIYR_uid507_fpTanXComp_uid157_fpTanTest_1(REG,771)@35
reg_exc_I_uid444_fpTanXComp_uid157_fpTanTest_0_to_excXIYR_uid507_fpTanXComp_uid157_fpTanTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_I_uid444_fpTanXComp_uid157_fpTanTest_0_to_excXIYR_uid507_fpTanXComp_uid157_fpTanTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_I_uid444_fpTanXComp_uid157_fpTanTest_0_to_excXIYR_uid507_fpTanXComp_uid157_fpTanTest_1_q <= exc_I_uid444_fpTanXComp_uid157_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--excXIYR_uid507_fpTanXComp_uid157_fpTanTest(LOGICAL,506)@36
excXIYR_uid507_fpTanXComp_uid157_fpTanTest_a <= reg_exc_I_uid444_fpTanXComp_uid157_fpTanTest_0_to_excXIYR_uid507_fpTanXComp_uid157_fpTanTest_1_q;
excXIYR_uid507_fpTanXComp_uid157_fpTanTest_b <= exc_R_uid466_fpTanXComp_uid157_fpTanTest_q;
excXIYR_uid507_fpTanXComp_uid157_fpTanTest_q <= excXIYR_uid507_fpTanXComp_uid157_fpTanTest_a and excXIYR_uid507_fpTanXComp_uid157_fpTanTest_b;
--ld_excXIYR_uid507_fpTanXComp_uid157_fpTanTest_q_to_excRInf_uid508_fpTanXComp_uid157_fpTanTest_d(DELAY,1255)@36
ld_excXIYR_uid507_fpTanXComp_uid157_fpTanTest_q_to_excRInf_uid508_fpTanXComp_uid157_fpTanTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => excXIYR_uid507_fpTanXComp_uid157_fpTanTest_q, xout => ld_excXIYR_uid507_fpTanXComp_uid157_fpTanTest_q_to_excRInf_uid508_fpTanXComp_uid157_fpTanTest_d_q, ena => en(0), clk => clk, aclr => areset );
--excXIYZ_uid506_fpTanXComp_uid157_fpTanTest(LOGICAL,505)@35
excXIYZ_uid506_fpTanXComp_uid157_fpTanTest_a <= exc_I_uid444_fpTanXComp_uid157_fpTanTest_q;
excXIYZ_uid506_fpTanXComp_uid157_fpTanTest_b <= expXIsZero_uid455_fpTanXComp_uid157_fpTanTest_q;
excXIYZ_uid506_fpTanXComp_uid157_fpTanTest_q <= excXIYZ_uid506_fpTanXComp_uid157_fpTanTest_a and excXIYZ_uid506_fpTanXComp_uid157_fpTanTest_b;
--ld_excXIYZ_uid506_fpTanXComp_uid157_fpTanTest_q_to_excRInf_uid508_fpTanXComp_uid157_fpTanTest_c(DELAY,1254)@35
ld_excXIYZ_uid506_fpTanXComp_uid157_fpTanTest_q_to_excRInf_uid508_fpTanXComp_uid157_fpTanTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 17 )
PORT MAP ( xin => excXIYZ_uid506_fpTanXComp_uid157_fpTanTest_q, xout => ld_excXIYZ_uid506_fpTanXComp_uid157_fpTanTest_q_to_excRInf_uid508_fpTanXComp_uid157_fpTanTest_c_q, ena => en(0), clk => clk, aclr => areset );
--expRExt_uid494_fpTanXComp_uid157_fpTanTest(BITSELECT,493)@51
expRExt_uid494_fpTanXComp_uid157_fpTanTest_in <= expFracPostRnd_uid490_fpTanXComp_uid157_fpTanTest_q;
expRExt_uid494_fpTanXComp_uid157_fpTanTest_b <= expRExt_uid494_fpTanXComp_uid157_fpTanTest_in(34 downto 24);
--reg_expRExt_uid494_fpTanXComp_uid157_fpTanTest_0_to_expUdf_uid495_fpTanXComp_uid157_fpTanTest_1(REG,766)@51
reg_expRExt_uid494_fpTanXComp_uid157_fpTanTest_0_to_expUdf_uid495_fpTanXComp_uid157_fpTanTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRExt_uid494_fpTanXComp_uid157_fpTanTest_0_to_expUdf_uid495_fpTanXComp_uid157_fpTanTest_1_q <= "00000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRExt_uid494_fpTanXComp_uid157_fpTanTest_0_to_expUdf_uid495_fpTanXComp_uid157_fpTanTest_1_q <= expRExt_uid494_fpTanXComp_uid157_fpTanTest_b;
END IF;
END IF;
END PROCESS;
--expOvf_uid498_fpTanXComp_uid157_fpTanTest(COMPARE,497)@52
expOvf_uid498_fpTanXComp_uid157_fpTanTest_cin <= GND_q;
expOvf_uid498_fpTanXComp_uid157_fpTanTest_a <= STD_LOGIC_VECTOR((12 downto 11 => reg_expRExt_uid494_fpTanXComp_uid157_fpTanTest_0_to_expUdf_uid495_fpTanXComp_uid157_fpTanTest_1_q(10)) & reg_expRExt_uid494_fpTanXComp_uid157_fpTanTest_0_to_expUdf_uid495_fpTanXComp_uid157_fpTanTest_1_q) & '0';
expOvf_uid498_fpTanXComp_uid157_fpTanTest_b <= STD_LOGIC_VECTOR('0' & "0000" & cstAllOWE_uid6_fpTanTest_q) & expOvf_uid498_fpTanXComp_uid157_fpTanTest_cin(0);
expOvf_uid498_fpTanXComp_uid157_fpTanTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid498_fpTanXComp_uid157_fpTanTest_a) - SIGNED(expOvf_uid498_fpTanXComp_uid157_fpTanTest_b));
expOvf_uid498_fpTanXComp_uid157_fpTanTest_n(0) <= not expOvf_uid498_fpTanXComp_uid157_fpTanTest_o(13);
--ld_exc_R_uid466_fpTanXComp_uid157_fpTanTest_q_to_regOverRegWithUf_uid500_fpTanXComp_uid157_fpTanTest_c(DELAY,1235)@36
ld_exc_R_uid466_fpTanXComp_uid157_fpTanTest_q_to_regOverRegWithUf_uid500_fpTanXComp_uid157_fpTanTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => exc_R_uid466_fpTanXComp_uid157_fpTanTest_q, xout => ld_exc_R_uid466_fpTanXComp_uid157_fpTanTest_q_to_regOverRegWithUf_uid500_fpTanXComp_uid157_fpTanTest_c_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid447_fpTanXComp_uid157_fpTanTest(LOGICAL,446)@35
InvExc_N_uid447_fpTanXComp_uid157_fpTanTest_a <= exc_N_uid446_fpTanXComp_uid157_fpTanTest_q;
InvExc_N_uid447_fpTanXComp_uid157_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExc_N_uid447_fpTanXComp_uid157_fpTanTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExc_N_uid447_fpTanXComp_uid157_fpTanTest_q <= not InvExc_N_uid447_fpTanXComp_uid157_fpTanTest_a;
END IF;
END PROCESS;
--InvExc_I_uid448_fpTanXComp_uid157_fpTanTest(LOGICAL,447)@35
InvExc_I_uid448_fpTanXComp_uid157_fpTanTest_a <= exc_I_uid444_fpTanXComp_uid157_fpTanTest_q;
InvExc_I_uid448_fpTanXComp_uid157_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExc_I_uid448_fpTanXComp_uid157_fpTanTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExc_I_uid448_fpTanXComp_uid157_fpTanTest_q <= not InvExc_I_uid448_fpTanXComp_uid157_fpTanTest_a;
END IF;
END PROCESS;
--InvExpXIsZero_uid449_fpTanXComp_uid157_fpTanTest(LOGICAL,448)@35
InvExpXIsZero_uid449_fpTanXComp_uid157_fpTanTest_a <= expXIsZero_uid439_fpTanXComp_uid157_fpTanTest_q;
InvExpXIsZero_uid449_fpTanXComp_uid157_fpTanTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExpXIsZero_uid449_fpTanXComp_uid157_fpTanTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvExpXIsZero_uid449_fpTanXComp_uid157_fpTanTest_q <= not InvExpXIsZero_uid449_fpTanXComp_uid157_fpTanTest_a;
END IF;
END PROCESS;
--exc_R_uid450_fpTanXComp_uid157_fpTanTest(LOGICAL,449)@36
exc_R_uid450_fpTanXComp_uid157_fpTanTest_a <= InvExpXIsZero_uid449_fpTanXComp_uid157_fpTanTest_q;
exc_R_uid450_fpTanXComp_uid157_fpTanTest_b <= InvExc_I_uid448_fpTanXComp_uid157_fpTanTest_q;
exc_R_uid450_fpTanXComp_uid157_fpTanTest_c <= InvExc_N_uid447_fpTanXComp_uid157_fpTanTest_q;
exc_R_uid450_fpTanXComp_uid157_fpTanTest_q <= exc_R_uid450_fpTanXComp_uid157_fpTanTest_a and exc_R_uid450_fpTanXComp_uid157_fpTanTest_b and exc_R_uid450_fpTanXComp_uid157_fpTanTest_c;
--ld_exc_R_uid450_fpTanXComp_uid157_fpTanTest_q_to_regOverRegWithUf_uid500_fpTanXComp_uid157_fpTanTest_b(DELAY,1234)@36
ld_exc_R_uid450_fpTanXComp_uid157_fpTanTest_q_to_regOverRegWithUf_uid500_fpTanXComp_uid157_fpTanTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => exc_R_uid450_fpTanXComp_uid157_fpTanTest_q, xout => ld_exc_R_uid450_fpTanXComp_uid157_fpTanTest_q_to_regOverRegWithUf_uid500_fpTanXComp_uid157_fpTanTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXRYROvf_uid505_fpTanXComp_uid157_fpTanTest(LOGICAL,504)@52
excXRYROvf_uid505_fpTanXComp_uid157_fpTanTest_a <= ld_exc_R_uid450_fpTanXComp_uid157_fpTanTest_q_to_regOverRegWithUf_uid500_fpTanXComp_uid157_fpTanTest_b_q;
excXRYROvf_uid505_fpTanXComp_uid157_fpTanTest_b <= ld_exc_R_uid466_fpTanXComp_uid157_fpTanTest_q_to_regOverRegWithUf_uid500_fpTanXComp_uid157_fpTanTest_c_q;
excXRYROvf_uid505_fpTanXComp_uid157_fpTanTest_c <= expOvf_uid498_fpTanXComp_uid157_fpTanTest_n;
excXRYROvf_uid505_fpTanXComp_uid157_fpTanTest_q <= excXRYROvf_uid505_fpTanXComp_uid157_fpTanTest_a and excXRYROvf_uid505_fpTanXComp_uid157_fpTanTest_b and excXRYROvf_uid505_fpTanXComp_uid157_fpTanTest_c;
--reg_expXIsZero_uid455_fpTanXComp_uid157_fpTanTest_0_to_excXRYZ_uid504_fpTanXComp_uid157_fpTanTest_2(REG,769)@35
reg_expXIsZero_uid455_fpTanXComp_uid157_fpTanTest_0_to_excXRYZ_uid504_fpTanXComp_uid157_fpTanTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid455_fpTanXComp_uid157_fpTanTest_0_to_excXRYZ_uid504_fpTanXComp_uid157_fpTanTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid455_fpTanXComp_uid157_fpTanTest_0_to_excXRYZ_uid504_fpTanXComp_uid157_fpTanTest_2_q <= expXIsZero_uid455_fpTanXComp_uid157_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--excXRYZ_uid504_fpTanXComp_uid157_fpTanTest(LOGICAL,503)@36
excXRYZ_uid504_fpTanXComp_uid157_fpTanTest_a <= exc_R_uid450_fpTanXComp_uid157_fpTanTest_q;
excXRYZ_uid504_fpTanXComp_uid157_fpTanTest_b <= reg_expXIsZero_uid455_fpTanXComp_uid157_fpTanTest_0_to_excXRYZ_uid504_fpTanXComp_uid157_fpTanTest_2_q;
excXRYZ_uid504_fpTanXComp_uid157_fpTanTest_q <= excXRYZ_uid504_fpTanXComp_uid157_fpTanTest_a and excXRYZ_uid504_fpTanXComp_uid157_fpTanTest_b;
--ld_excXRYZ_uid504_fpTanXComp_uid157_fpTanTest_q_to_excRInf_uid508_fpTanXComp_uid157_fpTanTest_a(DELAY,1252)@36
ld_excXRYZ_uid504_fpTanXComp_uid157_fpTanTest_q_to_excRInf_uid508_fpTanXComp_uid157_fpTanTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => excXRYZ_uid504_fpTanXComp_uid157_fpTanTest_q, xout => ld_excXRYZ_uid504_fpTanXComp_uid157_fpTanTest_q_to_excRInf_uid508_fpTanXComp_uid157_fpTanTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid508_fpTanXComp_uid157_fpTanTest(LOGICAL,507)@52
excRInf_uid508_fpTanXComp_uid157_fpTanTest_a <= ld_excXRYZ_uid504_fpTanXComp_uid157_fpTanTest_q_to_excRInf_uid508_fpTanXComp_uid157_fpTanTest_a_q;
excRInf_uid508_fpTanXComp_uid157_fpTanTest_b <= excXRYROvf_uid505_fpTanXComp_uid157_fpTanTest_q;
excRInf_uid508_fpTanXComp_uid157_fpTanTest_c <= ld_excXIYZ_uid506_fpTanXComp_uid157_fpTanTest_q_to_excRInf_uid508_fpTanXComp_uid157_fpTanTest_c_q;
excRInf_uid508_fpTanXComp_uid157_fpTanTest_d <= ld_excXIYR_uid507_fpTanXComp_uid157_fpTanTest_q_to_excRInf_uid508_fpTanXComp_uid157_fpTanTest_d_q;
excRInf_uid508_fpTanXComp_uid157_fpTanTest_q <= excRInf_uid508_fpTanXComp_uid157_fpTanTest_a or excRInf_uid508_fpTanXComp_uid157_fpTanTest_b or excRInf_uid508_fpTanXComp_uid157_fpTanTest_c or excRInf_uid508_fpTanXComp_uid157_fpTanTest_d;
--reg_exc_I_uid460_fpTanXComp_uid157_fpTanTest_0_to_regOrZeroOverInf_uid502_fpTanXComp_uid157_fpTanTest_2(REG,768)@35
reg_exc_I_uid460_fpTanXComp_uid157_fpTanTest_0_to_regOrZeroOverInf_uid502_fpTanXComp_uid157_fpTanTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_I_uid460_fpTanXComp_uid157_fpTanTest_0_to_regOrZeroOverInf_uid502_fpTanXComp_uid157_fpTanTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_I_uid460_fpTanXComp_uid157_fpTanTest_0_to_regOrZeroOverInf_uid502_fpTanXComp_uid157_fpTanTest_2_q <= exc_I_uid460_fpTanXComp_uid157_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--reg_expXIsZero_uid439_fpTanXComp_uid157_fpTanTest_0_to_zeroOverReg_uid499_fpTanXComp_uid157_fpTanTest_1(REG,753)@35
reg_expXIsZero_uid439_fpTanXComp_uid157_fpTanTest_0_to_zeroOverReg_uid499_fpTanXComp_uid157_fpTanTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid439_fpTanXComp_uid157_fpTanTest_0_to_zeroOverReg_uid499_fpTanXComp_uid157_fpTanTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid439_fpTanXComp_uid157_fpTanTest_0_to_zeroOverReg_uid499_fpTanXComp_uid157_fpTanTest_1_q <= expXIsZero_uid439_fpTanXComp_uid157_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--xRegOrZero_uid501_fpTanXComp_uid157_fpTanTest(LOGICAL,500)@36
xRegOrZero_uid501_fpTanXComp_uid157_fpTanTest_a <= exc_R_uid450_fpTanXComp_uid157_fpTanTest_q;
xRegOrZero_uid501_fpTanXComp_uid157_fpTanTest_b <= reg_expXIsZero_uid439_fpTanXComp_uid157_fpTanTest_0_to_zeroOverReg_uid499_fpTanXComp_uid157_fpTanTest_1_q;
xRegOrZero_uid501_fpTanXComp_uid157_fpTanTest_q <= xRegOrZero_uid501_fpTanXComp_uid157_fpTanTest_a or xRegOrZero_uid501_fpTanXComp_uid157_fpTanTest_b;
--regOrZeroOverInf_uid502_fpTanXComp_uid157_fpTanTest(LOGICAL,501)@36
regOrZeroOverInf_uid502_fpTanXComp_uid157_fpTanTest_a <= xRegOrZero_uid501_fpTanXComp_uid157_fpTanTest_q;
regOrZeroOverInf_uid502_fpTanXComp_uid157_fpTanTest_b <= reg_exc_I_uid460_fpTanXComp_uid157_fpTanTest_0_to_regOrZeroOverInf_uid502_fpTanXComp_uid157_fpTanTest_2_q;
regOrZeroOverInf_uid502_fpTanXComp_uid157_fpTanTest_q <= regOrZeroOverInf_uid502_fpTanXComp_uid157_fpTanTest_a and regOrZeroOverInf_uid502_fpTanXComp_uid157_fpTanTest_b;
--ld_regOrZeroOverInf_uid502_fpTanXComp_uid157_fpTanTest_q_to_excRZero_uid503_fpTanXComp_uid157_fpTanTest_c(DELAY,1242)@36
ld_regOrZeroOverInf_uid502_fpTanXComp_uid157_fpTanTest_q_to_excRZero_uid503_fpTanXComp_uid157_fpTanTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => regOrZeroOverInf_uid502_fpTanXComp_uid157_fpTanTest_q, xout => ld_regOrZeroOverInf_uid502_fpTanXComp_uid157_fpTanTest_q_to_excRZero_uid503_fpTanXComp_uid157_fpTanTest_c_q, ena => en(0), clk => clk, aclr => areset );
--expUdf_uid495_fpTanXComp_uid157_fpTanTest(COMPARE,494)@52
expUdf_uid495_fpTanXComp_uid157_fpTanTest_cin <= GND_q;
expUdf_uid495_fpTanXComp_uid157_fpTanTest_a <= STD_LOGIC_VECTOR('0' & "00000000000" & GND_q) & '0';
expUdf_uid495_fpTanXComp_uid157_fpTanTest_b <= STD_LOGIC_VECTOR((12 downto 11 => reg_expRExt_uid494_fpTanXComp_uid157_fpTanTest_0_to_expUdf_uid495_fpTanXComp_uid157_fpTanTest_1_q(10)) & reg_expRExt_uid494_fpTanXComp_uid157_fpTanTest_0_to_expUdf_uid495_fpTanXComp_uid157_fpTanTest_1_q) & expUdf_uid495_fpTanXComp_uid157_fpTanTest_cin(0);
expUdf_uid495_fpTanXComp_uid157_fpTanTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid495_fpTanXComp_uid157_fpTanTest_a) - SIGNED(expUdf_uid495_fpTanXComp_uid157_fpTanTest_b));
expUdf_uid495_fpTanXComp_uid157_fpTanTest_n(0) <= not expUdf_uid495_fpTanXComp_uid157_fpTanTest_o(13);
--regOverRegWithUf_uid500_fpTanXComp_uid157_fpTanTest(LOGICAL,499)@52
regOverRegWithUf_uid500_fpTanXComp_uid157_fpTanTest_a <= expUdf_uid495_fpTanXComp_uid157_fpTanTest_n;
regOverRegWithUf_uid500_fpTanXComp_uid157_fpTanTest_b <= ld_exc_R_uid450_fpTanXComp_uid157_fpTanTest_q_to_regOverRegWithUf_uid500_fpTanXComp_uid157_fpTanTest_b_q;
regOverRegWithUf_uid500_fpTanXComp_uid157_fpTanTest_c <= ld_exc_R_uid466_fpTanXComp_uid157_fpTanTest_q_to_regOverRegWithUf_uid500_fpTanXComp_uid157_fpTanTest_c_q;
regOverRegWithUf_uid500_fpTanXComp_uid157_fpTanTest_q <= regOverRegWithUf_uid500_fpTanXComp_uid157_fpTanTest_a and regOverRegWithUf_uid500_fpTanXComp_uid157_fpTanTest_b and regOverRegWithUf_uid500_fpTanXComp_uid157_fpTanTest_c;
--zeroOverReg_uid499_fpTanXComp_uid157_fpTanTest(LOGICAL,498)@36
zeroOverReg_uid499_fpTanXComp_uid157_fpTanTest_a <= reg_expXIsZero_uid439_fpTanXComp_uid157_fpTanTest_0_to_zeroOverReg_uid499_fpTanXComp_uid157_fpTanTest_1_q;
zeroOverReg_uid499_fpTanXComp_uid157_fpTanTest_b <= exc_R_uid466_fpTanXComp_uid157_fpTanTest_q;
zeroOverReg_uid499_fpTanXComp_uid157_fpTanTest_q <= zeroOverReg_uid499_fpTanXComp_uid157_fpTanTest_a and zeroOverReg_uid499_fpTanXComp_uid157_fpTanTest_b;
--ld_zeroOverReg_uid499_fpTanXComp_uid157_fpTanTest_q_to_excRZero_uid503_fpTanXComp_uid157_fpTanTest_a(DELAY,1240)@36
ld_zeroOverReg_uid499_fpTanXComp_uid157_fpTanTest_q_to_excRZero_uid503_fpTanXComp_uid157_fpTanTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => zeroOverReg_uid499_fpTanXComp_uid157_fpTanTest_q, xout => ld_zeroOverReg_uid499_fpTanXComp_uid157_fpTanTest_q_to_excRZero_uid503_fpTanXComp_uid157_fpTanTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRZero_uid503_fpTanXComp_uid157_fpTanTest(LOGICAL,502)@52
excRZero_uid503_fpTanXComp_uid157_fpTanTest_a <= ld_zeroOverReg_uid499_fpTanXComp_uid157_fpTanTest_q_to_excRZero_uid503_fpTanXComp_uid157_fpTanTest_a_q;
excRZero_uid503_fpTanXComp_uid157_fpTanTest_b <= regOverRegWithUf_uid500_fpTanXComp_uid157_fpTanTest_q;
excRZero_uid503_fpTanXComp_uid157_fpTanTest_c <= ld_regOrZeroOverInf_uid502_fpTanXComp_uid157_fpTanTest_q_to_excRZero_uid503_fpTanXComp_uid157_fpTanTest_c_q;
excRZero_uid503_fpTanXComp_uid157_fpTanTest_q <= excRZero_uid503_fpTanXComp_uid157_fpTanTest_a or excRZero_uid503_fpTanXComp_uid157_fpTanTest_b or excRZero_uid503_fpTanXComp_uid157_fpTanTest_c;
--concExc_uid512_fpTanXComp_uid157_fpTanTest(BITJOIN,511)@52
concExc_uid512_fpTanXComp_uid157_fpTanTest_q <= ld_excRNaN_uid511_fpTanXComp_uid157_fpTanTest_q_to_concExc_uid512_fpTanXComp_uid157_fpTanTest_c_q & excRInf_uid508_fpTanXComp_uid157_fpTanTest_q & excRZero_uid503_fpTanXComp_uid157_fpTanTest_q;
--reg_concExc_uid512_fpTanXComp_uid157_fpTanTest_0_to_excREnc_uid513_fpTanXComp_uid157_fpTanTest_0(REG,774)@52
reg_concExc_uid512_fpTanXComp_uid157_fpTanTest_0_to_excREnc_uid513_fpTanXComp_uid157_fpTanTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid512_fpTanXComp_uid157_fpTanTest_0_to_excREnc_uid513_fpTanXComp_uid157_fpTanTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid512_fpTanXComp_uid157_fpTanTest_0_to_excREnc_uid513_fpTanXComp_uid157_fpTanTest_0_q <= concExc_uid512_fpTanXComp_uid157_fpTanTest_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid513_fpTanXComp_uid157_fpTanTest(LOOKUP,512)@53
excREnc_uid513_fpTanXComp_uid157_fpTanTest: PROCESS (reg_concExc_uid512_fpTanXComp_uid157_fpTanTest_0_to_excREnc_uid513_fpTanXComp_uid157_fpTanTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid512_fpTanXComp_uid157_fpTanTest_0_to_excREnc_uid513_fpTanXComp_uid157_fpTanTest_0_q) IS
WHEN "000" => excREnc_uid513_fpTanXComp_uid157_fpTanTest_q <= "01";
WHEN "001" => excREnc_uid513_fpTanXComp_uid157_fpTanTest_q <= "00";
WHEN "010" => excREnc_uid513_fpTanXComp_uid157_fpTanTest_q <= "10";
WHEN "011" => excREnc_uid513_fpTanXComp_uid157_fpTanTest_q <= "00";
WHEN "100" => excREnc_uid513_fpTanXComp_uid157_fpTanTest_q <= "11";
WHEN "101" => excREnc_uid513_fpTanXComp_uid157_fpTanTest_q <= "00";
WHEN "110" => excREnc_uid513_fpTanXComp_uid157_fpTanTest_q <= "00";
WHEN "111" => excREnc_uid513_fpTanXComp_uid157_fpTanTest_q <= "00";
WHEN OTHERS =>
excREnc_uid513_fpTanXComp_uid157_fpTanTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid521_fpTanXComp_uid157_fpTanTest(MUX,520)@53
expRPostExc_uid521_fpTanXComp_uid157_fpTanTest_s <= excREnc_uid513_fpTanXComp_uid157_fpTanTest_q;
expRPostExc_uid521_fpTanXComp_uid157_fpTanTest: PROCESS (expRPostExc_uid521_fpTanXComp_uid157_fpTanTest_s, en, cstAllZWE_uid8_fpTanTest_q, ld_excRPreExc_uid493_fpTanXComp_uid157_fpTanTest_b_to_expRPostExc_uid521_fpTanXComp_uid157_fpTanTest_d_q, cstAllOWE_uid6_fpTanTest_q, cstAllOWE_uid6_fpTanTest_q)
BEGIN
CASE expRPostExc_uid521_fpTanXComp_uid157_fpTanTest_s IS
WHEN "00" => expRPostExc_uid521_fpTanXComp_uid157_fpTanTest_q <= cstAllZWE_uid8_fpTanTest_q;
WHEN "01" => expRPostExc_uid521_fpTanXComp_uid157_fpTanTest_q <= ld_excRPreExc_uid493_fpTanXComp_uid157_fpTanTest_b_to_expRPostExc_uid521_fpTanXComp_uid157_fpTanTest_d_q;
WHEN "10" => expRPostExc_uid521_fpTanXComp_uid157_fpTanTest_q <= cstAllOWE_uid6_fpTanTest_q;
WHEN "11" => expRPostExc_uid521_fpTanXComp_uid157_fpTanTest_q <= cstAllOWE_uid6_fpTanTest_q;
WHEN OTHERS => expRPostExc_uid521_fpTanXComp_uid157_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPreExc_uid492_fpTanXComp_uid157_fpTanTest(BITSELECT,491)@51
fracRPreExc_uid492_fpTanXComp_uid157_fpTanTest_in <= expFracPostRnd_uid490_fpTanXComp_uid157_fpTanTest_q(23 downto 0);
fracRPreExc_uid492_fpTanXComp_uid157_fpTanTest_b <= fracRPreExc_uid492_fpTanXComp_uid157_fpTanTest_in(23 downto 1);
--ld_fracRPreExc_uid492_fpTanXComp_uid157_fpTanTest_b_to_fracRPostExc_uid517_fpTanXComp_uid157_fpTanTest_d(DELAY,1269)@51
ld_fracRPreExc_uid492_fpTanXComp_uid157_fpTanTest_b_to_fracRPostExc_uid517_fpTanXComp_uid157_fpTanTest_d : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => fracRPreExc_uid492_fpTanXComp_uid157_fpTanTest_b, xout => ld_fracRPreExc_uid492_fpTanXComp_uid157_fpTanTest_b_to_fracRPostExc_uid517_fpTanXComp_uid157_fpTanTest_d_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid517_fpTanXComp_uid157_fpTanTest(MUX,516)@53
fracRPostExc_uid517_fpTanXComp_uid157_fpTanTest_s <= excREnc_uid513_fpTanXComp_uid157_fpTanTest_q;
fracRPostExc_uid517_fpTanXComp_uid157_fpTanTest: PROCESS (fracRPostExc_uid517_fpTanXComp_uid157_fpTanTest_s, en, cstAllZWF_uid7_fpTanTest_q, ld_fracRPreExc_uid492_fpTanXComp_uid157_fpTanTest_b_to_fracRPostExc_uid517_fpTanXComp_uid157_fpTanTest_d_q, cstAllZWF_uid7_fpTanTest_q, cstNaNwF_uid32_fpTanTest_q)
BEGIN
CASE fracRPostExc_uid517_fpTanXComp_uid157_fpTanTest_s IS
WHEN "00" => fracRPostExc_uid517_fpTanXComp_uid157_fpTanTest_q <= cstAllZWF_uid7_fpTanTest_q;
WHEN "01" => fracRPostExc_uid517_fpTanXComp_uid157_fpTanTest_q <= ld_fracRPreExc_uid492_fpTanXComp_uid157_fpTanTest_b_to_fracRPostExc_uid517_fpTanXComp_uid157_fpTanTest_d_q;
WHEN "10" => fracRPostExc_uid517_fpTanXComp_uid157_fpTanTest_q <= cstAllZWF_uid7_fpTanTest_q;
WHEN "11" => fracRPostExc_uid517_fpTanXComp_uid157_fpTanTest_q <= cstNaNwF_uid32_fpTanTest_q;
WHEN OTHERS => fracRPostExc_uid517_fpTanXComp_uid157_fpTanTest_q <= (others => '0');
END CASE;
END PROCESS;
--divR_uid524_fpTanXComp_uid157_fpTanTest(BITJOIN,523)@53
divR_uid524_fpTanXComp_uid157_fpTanTest_q <= ld_sRPostExc_uid523_fpTanXComp_uid157_fpTanTest_q_to_divR_uid524_fpTanXComp_uid157_fpTanTest_c_q & expRPostExc_uid521_fpTanXComp_uid157_fpTanTest_q & fracRPostExc_uid517_fpTanXComp_uid157_fpTanTest_q;
--xOut(GPOUT,4)@53
q <= divR_uid524_fpTanXComp_uid157_fpTanTest_q;
end normal;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
bin_Sobel_Filter/ip/Sobel/dp_inv_core.vhd
|
10
|
9935
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION INVERSE - CORE ***
--*** ***
--*** DP_INV_CORE.VHD ***
--*** ***
--*** Function: 54 bit Inverse ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 24/04/09 - SIII/SIV multiplier support ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** SII Latency = 19 + 2*doublepeed ***
--*** SIII Latency = 18 + doublespeed ***
--***************************************************
ENTITY dp_inv_core IS
GENERIC (
doublespeed : integer := 0; -- 0/1
doubleaccuracy : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (55 DOWNTO 1)
);
END dp_inv_core;
ARCHITECTURE rtl OF dp_inv_core IS
--SII mullatency = doublespeed+5, SIII/IV mullatency = 4
constant mullatency : positive := doublespeed+5 - device*(1+doublespeed);
signal zerovec : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal divisordel : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal invdivisor : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal delinvdivisor : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal scaleden : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal twonode, subscaleden : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal guessone : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal guessonevec : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal absoluteval : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal absolutevalff, absoluteff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal abscarryff : STD_LOGIC;
signal iteratenumnode : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal iteratenum : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal absoluteerror : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal mulabsguessff : STD_LOGIC_VECTOR (19 DOWNTO 1);
signal mulabsguess : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal quotientnode : STD_LOGIC_VECTOR (72 DOWNTO 1);
component fp_div_est IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (19 DOWNTO 1);
invdivisor : OUT STD_LOGIC_VECTOR (18 DOWNTO 1)
);
end component;
component fp_fxmul IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component dp_fxadd
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 54 GENERATE
zerovec(k) <= '0';
END GENERATE;
invcore: fp_div_est
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
divisor=>divisor(54 DOWNTO 36),invdivisor=>invdivisor);
delinone: fp_del
GENERIC MAP (width=>54,pipes=>5)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>divisor,cc=>divisordel);
--**********************************
--*** ITERATION 0 - SCALE INPUTS ***
--**********************************
-- in level 5, out level 8+speed
mulscaleone: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>18,widthcc=>54,
pipes=>3+doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>divisordel,databb=>invdivisor,
result=>scaleden);
--********************
--*** ITERATION 1 ***
--********************
twonode <= '1' & zerovec(54 DOWNTO 1);
gta: FOR k IN 1 TO 54 GENERATE
subscaleden(k) <= NOT(scaleden(k));
END GENERATE;
subscaleden(55) <= '1';
-- in level 8+doublespeed, outlevel 9+2*doublespeed
addtwoone: dp_fxadd
GENERIC MAP (width=>55,pipes=>doublespeed+1,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>twonode,bb=>subscaleden,carryin=>'1',
cc=>guessone);
guessonevec <= guessone(54 DOWNTO 1);
-- absolute value of guess lower 36 bits
-- this is still correct, because (for positive), value will be 1.(17 zeros)error
-- can also be calculated from guessonevec (code below)
-- gabs: FOR k IN 1 TO 36 GENERATE
-- absoluteval(k) <= guessonevec(k) XOR NOT(guessonevec(54));
-- END GENERATE;
gabs: FOR k IN 1 TO 36 GENERATE
absoluteval(k) <= scaleden(k) XOR NOT(scaleden(54));
END GENERATE;
pta: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
absolutevalff(k) <= '0';
absoluteff(k) <= '0';
END LOOP;
abscarryff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
absolutevalff <= absoluteval; -- out level 9+speed
abscarryff <= NOT(scaleden(54));
absoluteff <= absolutevalff + (zerovec(35 DOWNTO 1) & abscarryff); -- out level 10+speed
END IF;
END IF;
END PROCESS;
deloneone: fp_del
GENERIC MAP (width=>18,pipes=>4+2*doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>invdivisor,
cc=>delinvdivisor);
-- in level 9+2*doublespeed, out level 12+3*doublespeed
muloneone: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>18,widthcc=>54,
pipes=>3+doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guessonevec,databb=>delinvdivisor,
result=>iteratenumnode);
-- in level 10+doublespeed, out level 13+doublespeed
mulonetwo: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>72,
pipes=>3,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>absoluteff,databb=>absoluteff,
result=>absoluteerror);
-- if speed = 0, delay absoluteerror 1 clock, else 2
-- this guess always positive (check??)
-- change here, error can be [19:1], not [18:1] - this is because (1.[17 zeros].error)^2
-- gives 1.[34 zeros].error
pgaa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 19 LOOP
mulabsguessff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
mulabsguessff <= absoluteerror(72 DOWNTO 54) +
(zerovec(18 DOWNTO 1) & absoluteerror(53));
END IF;
END IF;
END PROCESS;
mulabsguess(19 DOWNTO 1) <= mulabsguessff;
gmga: FOR k IN 20 TO 53 GENERATE
mulabsguess(k) <= '0';
END GENERATE;
mulabsguess(54) <= '1';
-- mulabsguess at 14+doublespeed depth
-- iteratenum at 12+3*doublespeed depth
-- mulabsguess 5 (5)clocks from absolutevalff
-- iteratenum 3+2doublespeed (3/5)clocks from abssolutevalff
-- delay iterate num
gdoa: IF (doublespeed = 0) GENERATE
delonetwo: fp_del
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>iteratenumnode,
cc=>iteratenum);
END GENERATE;
gdob: IF (doublespeed = 1) GENERATE
iteratenum <= iteratenumnode;
END GENERATE;
--*********************
--*** OUTPUT SCALE ***
--*********************
-- in level 14+doublespeed
-- SII out level 19+2*doublespeed
-- SIII/IV out level 18+doublespeed
mulout: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>54,widthcc=>72,pipes=>mullatency,
accuracy=>doubleaccuracy,device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>iteratenum,databb=>mulabsguess,
result=>quotientnode);
quotient <= quotientnode(71 DOWNTO 17);
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
bin_Sobel_Filter/ip/Sobel/hcc_normsgn3236.vhd
|
20
|
5168
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit signed ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normsgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normsgn3236;
ARCHITECTURE rtl OF hcc_normsgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntsgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntsgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntsgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntsgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
--pcc: PROCESS (sysclk,reset)
--BEGIN
-- IF (reset = '1') THEN
-- countff <= "000000";
-- ELSIF (rising_edge(sysclk)) THEN
-- IF (enable = '1') THEN
-- countff <= count;
-- END IF;
-- END IF;
--END PROCESS;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
bin_Sobel_Filter/ip/Sobel/fp_acos.vhd
|
10
|
10938
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** Notes: Latency = 53 ***
--***************************************************
-- input -1 to 1, output 0 to pi
ENTITY fp_acos IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_acos ;
ARCHITECTURE rtl OF fp_acos IS
type term_exponentfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (9 DOWNTO 1);
type acos_sumfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (36 DOWNTO 1);
signal pi : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal prep_signout : STD_LOGIC;
signal numerator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal numerator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal denominator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (43 DOWNTO 1);
signal invsqr_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal invsqr_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal del_numerator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal del_numerator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal term_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal pi_term, acos_term, acos_sum : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal acos_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal term_exponentff : term_exponentfftype;
signal acos_sumff : acos_sumfftype;
signal acos_shift, acos_shiftff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal shiftzeroout : STD_LOGIC;
signal acos_mantissabus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal acos_mantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissaoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal zeroexponentff : STD_LOGIC;
signal exponentadjustff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
-- latency = 8
component fp_acos_prep1
GENERIC (synthesize : integer := 0);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
numerator_exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
numerator_mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
denominator_exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
denominator_mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
-- latency = 17
component fp_invsqr_trig1
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
-- latency = 22
component fp_atan_core1 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
atan : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_clz36
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pi <= x"C90FDAA22";
-- latency 8: input level 0, output level 8
cprep: fp_acos_prep1
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signin,exponentin=>exponentin,mantissain=>mantissain,
signout=>prep_signout,
numerator_exponent=>numerator_exponent,
numerator_mantissa=>numerator_mantissa,
denominator_exponent=>denominator_exponent,
denominator_mantissa=>denominator_mantissa);
-- latency 17: input level 8, output level 25
cisqr: fp_invsqr_trig1
GENERIC MAP (synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
exponentin=>denominator_exponent,
mantissain=>denominator_mantissa,
exponentout=>invsqr_exponent,
mantissaout=>invsqr_mantissa);
-- input level 8, output level 25
cdnx: fp_del
GENERIC MAP (width=>8,pipes=>17)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numerator_exponent,
cc=>del_numerator_exponent);
-- input level 8, output level 25
cdnm: fp_del
GENERIC MAP (width=>36,pipes=>17)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numerator_mantissa,
cc=>del_numerator_mantissa);
-- input level 25, output level 28
cma: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>36,pipes=>3,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>del_numerator_mantissa,
databb=>invsqr_mantissa,
result=>term_mantissa);
pxa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 3 LOOP
FOR j IN 1 TO 9 LOOP
term_exponentff(1)(k) <= '0';
term_exponentff(2)(k) <= '0';
term_exponentff(3)(k) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
term_exponentff(1)(9 DOWNTO 1) <= ('0' & del_numerator_exponent) + ('0' & invsqr_exponent) - 126;
term_exponentff(2)(9 DOWNTO 1) <= term_exponentff(1)(9 DOWNTO 1);
term_exponentff(3)(9 DOWNTO 1) <= term_exponentff(2)(9 DOWNTO 1);
END IF;
END IF;
END PROCESS;
-- input level 28, output level 49
cat: fp_atan_core1
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
exponentin=>term_exponentff(3)(8 DOWNTO 1),
mantissain=>term_mantissa,
atan=>acos_fixedpoint);
gpa: FOR k IN 1 TO 36 GENERATE
pi_term(k) <= pi(k) AND signff(41);
acos_term(k) <= acos_fixedpoint(k) XOR signff(41);
END GENERATE;
acos_sum <= pi_term + acos_term + signff(41);
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 43 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO 6 LOOP
acos_shiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
acos_sumff(1)(k) <= '0';
acos_sumff(2)(k) <= '0';
acos_mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissaoutff(k) <= '0';
END LOOP;
zeroexponentff <= '0';
FOR k IN 1 TO 8 LOOP
exponentadjustff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff(1) <= prep_signout;
FOR k IN 2 TO 43 LOOP
signff(k) <= signff(k-1);
END LOOP;
acos_sumff(1)(36 DOWNTO 1) <= acos_sum; -- level 50
acos_sumff(2)(36 DOWNTO 1) <= acos_sumff(1)(36 DOWNTO 1); -- level 51
acos_shiftff <= acos_shift; -- level 51
acos_mantissaff <= acos_mantissabus; -- level 52
-- check for overflow not needed?
mantissaoutff <= acos_mantissaff(35 DOWNTO 13) + acos_mantissaff(12); -- level 52
-- if CLZ output = 0 and positive input, output = 0
zeroexponentff <= NOT(signff(43)) AND shiftzeroout;
exponentadjustff <= 128 - ("00" & acos_shiftff); -- level 52
FOR k IN 1 TO 8 LOOP
exponentoutff(k) <= exponentadjustff(k) AND NOT(zeroexponentff); -- level 53
END LOOP;
END IF;
END IF;
END PROCESS;
czo: fp_clz36
PORT MAP (mantissa=>acos_sumff(1)(36 DOWNTO 1),
leading=>acos_shift);
clso: fp_lsft36
PORT MAP (inbus=>acos_sumff(2)(36 DOWNTO 1),
shift=>acos_shiftff,
outbus=>acos_mantissabus);
shiftzeroout <= NOT(acos_shiftff(6) OR acos_shiftff(5) OR acos_shiftff(4) OR
acos_shiftff(3) OR acos_shiftff(2) OR acos_shiftff(1));
--*** OUTPUTS ***
signout <= '0';
exponentout <= exponentoutff;
mantissaout <= mantissaoutff;
END rtl;
|
mit
|
Given-Jiang/Sobel_Filter_Altera_OpenCL_DE1-SoC
|
Sobel/ip/Sobel/fp_acos.vhd
|
10
|
10938
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** Notes: Latency = 53 ***
--***************************************************
-- input -1 to 1, output 0 to pi
ENTITY fp_acos IS
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_acos ;
ARCHITECTURE rtl OF fp_acos IS
type term_exponentfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (9 DOWNTO 1);
type acos_sumfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (36 DOWNTO 1);
signal pi : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal prep_signout : STD_LOGIC;
signal numerator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal numerator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal denominator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (43 DOWNTO 1);
signal invsqr_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal invsqr_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal del_numerator_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal del_numerator_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal term_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal pi_term, acos_term, acos_sum : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal acos_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal term_exponentff : term_exponentfftype;
signal acos_sumff : acos_sumfftype;
signal acos_shift, acos_shiftff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal shiftzeroout : STD_LOGIC;
signal acos_mantissabus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal acos_mantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissaoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal zeroexponentff : STD_LOGIC;
signal exponentadjustff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
-- latency = 8
component fp_acos_prep1
GENERIC (synthesize : integer := 0);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
numerator_exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
numerator_mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
denominator_exponent : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
denominator_mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
-- latency = 17
component fp_invsqr_trig1
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
-- latency = 22
component fp_atan_core1 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
atan : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_clz36
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pi <= x"C90FDAA22";
-- latency 8: input level 0, output level 8
cprep: fp_acos_prep1
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signin,exponentin=>exponentin,mantissain=>mantissain,
signout=>prep_signout,
numerator_exponent=>numerator_exponent,
numerator_mantissa=>numerator_mantissa,
denominator_exponent=>denominator_exponent,
denominator_mantissa=>denominator_mantissa);
-- latency 17: input level 8, output level 25
cisqr: fp_invsqr_trig1
GENERIC MAP (synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
exponentin=>denominator_exponent,
mantissain=>denominator_mantissa,
exponentout=>invsqr_exponent,
mantissaout=>invsqr_mantissa);
-- input level 8, output level 25
cdnx: fp_del
GENERIC MAP (width=>8,pipes=>17)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numerator_exponent,
cc=>del_numerator_exponent);
-- input level 8, output level 25
cdnm: fp_del
GENERIC MAP (width=>36,pipes=>17)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numerator_mantissa,
cc=>del_numerator_mantissa);
-- input level 25, output level 28
cma: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>36,pipes=>3,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>del_numerator_mantissa,
databb=>invsqr_mantissa,
result=>term_mantissa);
pxa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 3 LOOP
FOR j IN 1 TO 9 LOOP
term_exponentff(1)(k) <= '0';
term_exponentff(2)(k) <= '0';
term_exponentff(3)(k) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
term_exponentff(1)(9 DOWNTO 1) <= ('0' & del_numerator_exponent) + ('0' & invsqr_exponent) - 126;
term_exponentff(2)(9 DOWNTO 1) <= term_exponentff(1)(9 DOWNTO 1);
term_exponentff(3)(9 DOWNTO 1) <= term_exponentff(2)(9 DOWNTO 1);
END IF;
END IF;
END PROCESS;
-- input level 28, output level 49
cat: fp_atan_core1
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
exponentin=>term_exponentff(3)(8 DOWNTO 1),
mantissain=>term_mantissa,
atan=>acos_fixedpoint);
gpa: FOR k IN 1 TO 36 GENERATE
pi_term(k) <= pi(k) AND signff(41);
acos_term(k) <= acos_fixedpoint(k) XOR signff(41);
END GENERATE;
acos_sum <= pi_term + acos_term + signff(41);
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 43 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO 6 LOOP
acos_shiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
acos_sumff(1)(k) <= '0';
acos_sumff(2)(k) <= '0';
acos_mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 23 LOOP
mantissaoutff(k) <= '0';
END LOOP;
zeroexponentff <= '0';
FOR k IN 1 TO 8 LOOP
exponentadjustff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff(1) <= prep_signout;
FOR k IN 2 TO 43 LOOP
signff(k) <= signff(k-1);
END LOOP;
acos_sumff(1)(36 DOWNTO 1) <= acos_sum; -- level 50
acos_sumff(2)(36 DOWNTO 1) <= acos_sumff(1)(36 DOWNTO 1); -- level 51
acos_shiftff <= acos_shift; -- level 51
acos_mantissaff <= acos_mantissabus; -- level 52
-- check for overflow not needed?
mantissaoutff <= acos_mantissaff(35 DOWNTO 13) + acos_mantissaff(12); -- level 52
-- if CLZ output = 0 and positive input, output = 0
zeroexponentff <= NOT(signff(43)) AND shiftzeroout;
exponentadjustff <= 128 - ("00" & acos_shiftff); -- level 52
FOR k IN 1 TO 8 LOOP
exponentoutff(k) <= exponentadjustff(k) AND NOT(zeroexponentff); -- level 53
END LOOP;
END IF;
END IF;
END PROCESS;
czo: fp_clz36
PORT MAP (mantissa=>acos_sumff(1)(36 DOWNTO 1),
leading=>acos_shift);
clso: fp_lsft36
PORT MAP (inbus=>acos_sumff(2)(36 DOWNTO 1),
shift=>acos_shiftff,
outbus=>acos_mantissabus);
shiftzeroout <= NOT(acos_shiftff(6) OR acos_shiftff(5) OR acos_shiftff(4) OR
acos_shiftff(3) OR acos_shiftff(2) OR acos_shiftff(1));
--*** OUTPUTS ***
signout <= '0';
exponentout <= exponentoutff;
mantissaout <= mantissaoutff;
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
Dilation/ip/Dilation/fp_sin_s5.vhd
|
10
|
431526
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_sin_s5
-- VHDL created on Wed Mar 13 12:44:09 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_sin_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_sin_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid8_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal exc_R_uid21_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid21_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid21_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid21_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal cstBiasMwShift_uid22_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid23_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid24_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal cstZwShiftP1_uid25_fpSinPiTest_q : std_logic_vector (13 downto 0);
signal cmpYToOneMinusY_uid45_fpSinPiTest_a : std_logic_vector(70 downto 0);
signal cmpYToOneMinusY_uid45_fpSinPiTest_b : std_logic_vector(70 downto 0);
signal cmpYToOneMinusY_uid45_fpSinPiTest_o : std_logic_vector (70 downto 0);
signal cmpYToOneMinusY_uid45_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid45_fpSinPiTest_c : std_logic_vector (0 downto 0);
signal cPi_uid52_fpSinPiTest_q : std_logic_vector (25 downto 0);
signal p_uid54_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal p_uid54_fpSinPiTest_q : std_logic_vector (25 downto 0);
signal biasM1_uid55_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal expP_uid59_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal expP_uid59_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal multSecondOperand_uid66_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal multSecondOperand_uid66_fpSinPiTest_q : std_logic_vector (25 downto 0);
signal mul2xSinRes_uid67_fpSinPiTest_a : std_logic_vector (25 downto 0);
signal mul2xSinRes_uid67_fpSinPiTest_b : std_logic_vector (25 downto 0);
signal mul2xSinRes_uid67_fpSinPiTest_s1 : std_logic_vector (51 downto 0);
signal mul2xSinRes_uid67_fpSinPiTest_pr : UNSIGNED (51 downto 0);
signal mul2xSinRes_uid67_fpSinPiTest_q : std_logic_vector (51 downto 0);
signal fracNaN_uid86_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal InvSinXIsXRR_uid94_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsXRR_uid94_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal xBranch_uid124_rrx_uid28_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal xBranch_uid124_rrx_uid28_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal xBranch_uid124_rrx_uid28_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal xBranch_uid124_rrx_uid28_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal xBranch_uid124_rrx_uid28_fpSinPiTest_n : std_logic_vector (0 downto 0);
signal ZerosGB_uid139_rrx_uid28_fpSinPiTest_q : std_logic_vector (29 downto 0);
signal leftShiftStage0Idx1Pad4_uid146_fxpX_uid40_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid152_fxpX_uid40_fpSinPiTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid160_fxpX_uid40_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid163_fxpX_uid40_fpSinPiTest_q : std_logic_vector (2 downto 0);
signal zs_uid169_lzcZ_uid50_fpSinPiTest_q : std_logic_vector (63 downto 0);
signal vCount_uid171_lzcZ_uid50_fpSinPiTest_a : std_logic_vector(63 downto 0);
signal vCount_uid171_lzcZ_uid50_fpSinPiTest_b : std_logic_vector(63 downto 0);
signal vCount_uid171_lzcZ_uid50_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal mO_uid172_lzcZ_uid50_fpSinPiTest_q : std_logic_vector (62 downto 0);
signal zs_uid177_lzcZ_uid50_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal vCount_uid179_lzcZ_uid50_fpSinPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid179_lzcZ_uid50_fpSinPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid179_lzcZ_uid50_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal zs_uid183_lzcZ_uid50_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal vCount_uid197_lzcZ_uid50_fpSinPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid197_lzcZ_uid50_fpSinPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid197_lzcZ_uid50_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx2_uid216_alignedZ_uid51_fpSinPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx3Pad24_uid226_alignedZ_uid51_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx3Pad6_uid237_alignedZ_uid51_fpSinPiTest_q : std_logic_vector (5 downto 0);
signal mO_uid270_zCount_uid134_rrx_uid28_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid289_zCount_uid134_rrx_uid28_fpSinPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid289_zCount_uid134_rrx_uid28_fpSinPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid289_zCount_uid134_rrx_uid28_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal prodXY_uid327_pT1_uid255_sinPiZPolyEval_a : std_logic_vector (12 downto 0);
signal prodXY_uid327_pT1_uid255_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal prodXY_uid327_pT1_uid255_sinPiZPolyEval_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid327_pT1_uid255_sinPiZPolyEval_pr : SIGNED (26 downto 0);
signal prodXY_uid327_pT1_uid255_sinPiZPolyEval_q : std_logic_vector (25 downto 0);
signal prodXY_uid330_pT2_uid261_sinPiZPolyEval_a : std_logic_vector (17 downto 0);
signal prodXY_uid330_pT2_uid261_sinPiZPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid330_pT2_uid261_sinPiZPolyEval_s1 : std_logic_vector (40 downto 0);
signal prodXY_uid330_pT2_uid261_sinPiZPolyEval_pr : SIGNED (41 downto 0);
signal prodXY_uid330_pT2_uid261_sinPiZPolyEval_q : std_logic_vector (40 downto 0);
signal rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_reset0 : std_logic;
signal rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_q : std_logic_vector (39 downto 0);
signal rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_reset0 : std_logic;
signal rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_ia : std_logic_vector (37 downto 0);
signal rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_iq : std_logic_vector (37 downto 0);
signal rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_q : std_logic_vector (37 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_a : std_logic_vector (26 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_b : std_logic_vector (26 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_q : std_logic_vector (53 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_a : std_logic_vector (26 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_b : std_logic_vector (26 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_q : std_logic_vector (53 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_a : std_logic_vector (26 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_b : std_logic_vector (26 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_q : std_logic_vector (53 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_result_add_0_0_a : std_logic_vector(81 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_result_add_0_0_b : std_logic_vector(81 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_result_add_0_0_o : std_logic_vector (81 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_result_add_0_0_q : std_logic_vector (81 downto 0);
signal memoryC0_uid248_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid248_sinPiZTableGenerator_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid248_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid248_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid248_sinPiZTableGenerator_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid248_sinPiZTableGenerator_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid250_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid250_sinPiZTableGenerator_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid250_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid250_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid250_sinPiZTableGenerator_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid250_sinPiZTableGenerator_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid252_sinPiZTableGenerator_lutmem_reset0 : std_logic;
signal memoryC2_uid252_sinPiZTableGenerator_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid252_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid252_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid252_sinPiZTableGenerator_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid252_sinPiZTableGenerator_lutmem_q : std_logic_vector (12 downto 0);
signal reg_expXTableAddr_uid126_rrx_uid28_fpSinPiTest_0_to_rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_0_to_os_uid129_rrx_uid28_fpSinPiTest_0_q : std_logic_vector (39 downto 0);
signal reg_rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_0_to_os_uid129_rrx_uid28_fpSinPiTest_1_q : std_logic_vector (37 downto 0);
signal reg_prod_uid131_rrx_uid28_fpSinPiTest_a_0_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid131_rrx_uid28_fpSinPiTest_b_0_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_prod_uid131_rrx_uid28_fpSinPiTest_a_1_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid131_rrx_uid28_fpSinPiTest_a_2_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_0_q : std_logic_vector (26 downto 0);
signal reg_rVStage_uid268_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_1_q : std_logic_vector (15 downto 0);
signal reg_cStage_uid272_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid276_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid278_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid288_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid290_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid283_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel2Dto1_uid319_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_2_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx1_uid312_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_3_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx2_uid315_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_4_q : std_logic_vector (75 downto 0);
signal reg_leftShiftStage1Idx3_uid318_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_5_q : std_logic_vector (75 downto 0);
signal reg_fracCompOut_uid136_rrx_uid28_fpSinPiTest_0_to_finalFrac_uid141_rrx_uid28_fpSinPiTest_2_q : std_logic_vector (52 downto 0);
signal reg_expCompOut_uid138_rrx_uid28_fpSinPiTest_0_to_finalExp_uid142_rrx_uid28_fpSinPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_leftShiftStageSel3Dto2_uid155_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_2_q : std_logic_vector (67 downto 0);
signal reg_pad_one_uid43_fpSinPiTest_0_to_oneMinusY_uid43_fpSinPiTest_0_q : std_logic_vector (66 downto 0);
signal reg_y_uid42_fpSinPiTest_0_to_oneMinusY_uid43_fpSinPiTest_1_q : std_logic_vector (65 downto 0);
signal reg_oneMinusY_uid43_fpSinPiTest_0_to_cmpYToOneMinusY_uid45_fpSinPiTest_0_q : std_logic_vector (67 downto 0);
signal reg_yBottom_uid47_fpSinPiTest_0_to_z_uid48_fpSinPiTest_2_q : std_logic_vector (64 downto 0);
signal reg_oMyBottom_uid46_fpSinPiTest_0_to_z_uid48_fpSinPiTest_3_q : std_logic_vector (64 downto 0);
signal reg_rVStage_uid190_lzcZ_uid50_fpSinPiTest_0_to_vCount_uid191_lzcZ_uid50_fpSinPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid192_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid194_lzcZ_uid50_fpSinPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid196_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid200_lzcZ_uid50_fpSinPiTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid198_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid200_lzcZ_uid50_fpSinPiTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid185_lzcZ_uid50_fpSinPiTest_0_to_r_uid210_lzcZ_uid50_fpSinPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel4Dto3_uid229_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_2_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx1_uid222_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_3_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx2_uid225_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_4_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx3_uid228_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_5_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_2_q : std_logic_vector (64 downto 0);
signal reg_sinXIsXRR_uid35_fpSinPiTest_2_to_p_uid54_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_pHigh_uid53_fpSinPiTest_0_to_p_uid54_fpSinPiTest_2_q : std_logic_vector (25 downto 0);
signal reg_zAddr_uid61_fpSinPiTest_0_to_memoryC2_uid252_sinPiZTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid254_sinPiZPolyEval_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid252_sinPiZTableGenerator_lutmem_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_1_q : std_logic_vector (12 downto 0);
signal reg_zAddr_uid61_fpSinPiTest_0_to_memoryC1_uid250_sinPiZTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid250_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid258_sinPiZPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q : std_logic_vector (17 downto 0);
signal reg_s1_uid256_uid259_sinPiZPolyEval_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid264_sinPiZPolyEval_0_q : std_logic_vector (29 downto 0);
signal reg_r_uid210_lzcZ_uid50_fpSinPiTest_0_to_expHardCase_uid56_fpSinPiTest_1_q : std_logic_vector (6 downto 0);
signal reg_sinXIsXRR_uid35_fpSinPiTest_2_to_expP_uid59_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_sinXIsXRR_uid35_fpSinPiTest_2_to_join_uid73_fpSinPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_expRCompE_uid78_fpSinPiTest_0_to_udf_uid80_fpSinPiTest_1_q : std_logic_vector (8 downto 0);
signal reg_excSelBits_uid84_fpSinPiTest_0_to_excSel_uid85_fpSinPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_fracRComp_uid77_fpSinPiTest_0_to_fracRPostExc_uid88_fpSinPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_expRComp_uid79_fpSinPiTest_0_to_expRPostExc_uid92_fpSinPiTest_2_q : std_logic_vector (7 downto 0);
signal ld_fracXRR_uid33_fpSinPiTest_b_to_oFracXRR_uid36_uid36_fpSinPiTest_a_q : std_logic_vector (52 downto 0);
signal ld_y_uid42_fpSinPiTest_b_to_cmpYToOneMinusY_uid45_fpSinPiTest_b_q : std_logic_vector (65 downto 0);
signal ld_reg_sinXIsXRR_uid35_fpSinPiTest_2_to_p_uid54_fpSinPiTest_1_q_to_p_uid54_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsXRR_uid35_fpSinPiTest_n_to_multSecondOperand_uid66_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRComp_uid77_fpSinPiTest_0_to_fracRPostExc_uid88_fpSinPiTest_2_q_to_fracRPostExc_uid88_fpSinPiTest_c_q : std_logic_vector (22 downto 0);
signal ld_reg_expRComp_uid79_fpSinPiTest_0_to_expRPostExc_uid92_fpSinPiTest_2_q_to_expRPostExc_uid92_fpSinPiTest_c_q : std_logic_vector (7 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_n_to_InvSinXIsX_uid93_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_sinXIsXRR_uid35_fpSinPiTest_n_to_InvSinXIsXRR_uid94_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signX_uid31_fpSinPiTest_b_to_signR_uid96_fpSinPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid96_fpSinPiTest_q_to_sinXR_uid97_fpSinPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid124_rrx_uid28_fpSinPiTest_n_to_finalFrac_uid141_rrx_uid28_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid124_rrx_uid28_fpSinPiTest_n_to_finalExp_uid142_rrx_uid28_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_finalExp_uid142_rrx_uid28_fpSinPiTest_q_to_RRangeRed_uid143_rrx_uid28_fpSinPiTest_b_q : std_logic_vector (7 downto 0);
signal ld_LeftShiftStage066dto0_uid158_fxpX_uid40_fpSinPiTest_b_to_leftShiftStage1Idx1_uid159_fxpX_uid40_fpSinPiTest_b_q : std_logic_vector (66 downto 0);
signal ld_LeftShiftStage065dto0_uid161_fxpX_uid40_fpSinPiTest_b_to_leftShiftStage1Idx2_uid162_fxpX_uid40_fpSinPiTest_b_q : std_logic_vector (65 downto 0);
signal ld_LeftShiftStage064dto0_uid164_fxpX_uid40_fpSinPiTest_b_to_leftShiftStage1Idx3_uid165_fxpX_uid40_fpSinPiTest_b_q : std_logic_vector (64 downto 0);
signal ld_reg_leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_1_q_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_b_q : std_logic_vector (1 downto 0);
signal ld_vStage_uid173_lzcZ_uid50_fpSinPiTest_b_to_cStage_uid174_lzcZ_uid50_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_rVStage_uid170_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid176_lzcZ_uid50_fpSinPiTest_c_q : std_logic_vector (63 downto 0);
signal ld_rVStage_uid178_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid182_lzcZ_uid50_fpSinPiTest_c_q : std_logic_vector (31 downto 0);
signal ld_vStage_uid180_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid182_lzcZ_uid50_fpSinPiTest_d_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid191_lzcZ_uid50_fpSinPiTest_q_to_r_uid210_lzcZ_uid50_fpSinPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid179_lzcZ_uid50_fpSinPiTest_q_to_r_uid210_lzcZ_uid50_fpSinPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid171_lzcZ_uid50_fpSinPiTest_q_to_r_uid210_lzcZ_uid50_fpSinPiTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage162dto0_uid232_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage2Idx1_uid233_alignedZ_uid51_fpSinPiTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage160dto0_uid235_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage2Idx2_uid236_alignedZ_uid51_fpSinPiTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage158dto0_uid238_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage2Idx3_uid239_alignedZ_uid51_fpSinPiTest_b_q : std_logic_vector (58 downto 0);
signal ld_leftShiftStageSel0Dto0_uid245_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage3_uid246_alignedZ_uid51_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest_q_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_X67dto0_uid300_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx1_uid301_normMult_uid135_rrx_uid28_fpSinPiTest_b_q : std_logic_vector (67 downto 0);
signal ld_X59dto0_uid303_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx2_uid304_normMult_uid135_rrx_uid28_fpSinPiTest_b_q : std_logic_vector (59 downto 0);
signal ld_X51dto0_uid306_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx3_uid307_normMult_uid135_rrx_uid28_fpSinPiTest_b_q : std_logic_vector (51 downto 0);
signal ld_multFracBits_uid132_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_c_q : std_logic_vector (75 downto 0);
signal ld_leftShiftStageSel0Dto0_uid324_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage2_uid325_normMult_uid135_rrx_uid28_fpSinPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_q_to_prod_uid131_rrx_uid28_fpSinPiTest_align_2_a_q : std_logic_vector (53 downto 0);
signal ld_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_q_to_reg_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_yBottom_uid47_fpSinPiTest_b_to_reg_yBottom_uid47_fpSinPiTest_0_to_z_uid48_fpSinPiTest_2_a_q : std_logic_vector (64 downto 0);
signal ld_oMyBottom_uid46_fpSinPiTest_b_to_reg_oMyBottom_uid46_fpSinPiTest_0_to_z_uid48_fpSinPiTest_3_a_q : std_logic_vector (64 downto 0);
signal ld_vCount_uid185_lzcZ_uid50_fpSinPiTest_q_to_reg_vCount_uid185_lzcZ_uid50_fpSinPiTest_0_to_r_uid210_lzcZ_uid50_fpSinPiTest_4_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_b_to_reg_leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_yT1_uid254_sinPiZPolyEval_b_to_reg_yT1_uid254_sinPiZPolyEval_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_0_a_q : std_logic_vector (12 downto 0);
signal ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC1_uid250_sinPiZTableGenerator_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_sinXIsXRR_uid35_fpSinPiTest_n_to_reg_sinXIsXRR_uid35_fpSinPiTest_2_to_expP_uid59_fpSinPiTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_sinXIsXRR_uid35_fpSinPiTest_n_to_reg_sinXIsXRR_uid35_fpSinPiTest_2_to_join_uid73_fpSinPiTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_sticky_ena_q : signal is true;
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_inputreg_q : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_reset0 : std_logic;
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_sticky_ena_q : signal is true;
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_reset0 : std_logic;
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_sticky_ena_q : signal is true;
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_inputreg_q : std_logic_vector (8 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_ia : std_logic_vector (8 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_iq : std_logic_vector (8 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_q : std_logic_vector (8 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_reset0 : std_logic;
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_sticky_ena_q : signal is true;
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_reset0 : std_logic;
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_eq : std_logic;
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_sticky_ena_q : signal is true;
signal ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_inputreg_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_reset0 : std_logic;
signal ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_sticky_ena_q : signal is true;
signal ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_reset0 : std_logic;
signal ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_sticky_ena_q : signal is true;
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_inputreg_q : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_reset0 : std_logic;
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_mem_top_q : std_logic_vector (6 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_sticky_ena_q : signal is true;
signal ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_reset0 : std_logic;
signal ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_sticky_ena_q : signal is true;
signal ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_inputreg_q : std_logic_vector (31 downto 0);
signal ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_reset0 : std_logic;
signal ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_sticky_ena_q : signal is true;
signal ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_inputreg_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_sticky_ena_q : signal is true;
signal ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_inputreg_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_sticky_ena_q : signal is true;
signal ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_inputreg_q : std_logic_vector (64 downto 0);
signal ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_reset0 : std_logic;
signal ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_ia : std_logic_vector (64 downto 0);
signal ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_iq : std_logic_vector (64 downto 0);
signal ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_q : std_logic_vector (64 downto 0);
signal ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_sticky_ena_q : signal is true;
signal ld_X67dto0_uid300_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx1_uid301_normMult_uid135_rrx_uid28_fpSinPiTest_b_inputreg_q : std_logic_vector (67 downto 0);
signal ld_X59dto0_uid303_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx2_uid304_normMult_uid135_rrx_uid28_fpSinPiTest_b_inputreg_q : std_logic_vector (59 downto 0);
signal ld_X51dto0_uid306_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx3_uid307_normMult_uid135_rrx_uid28_fpSinPiTest_b_inputreg_q : std_logic_vector (51 downto 0);
signal ld_multFracBits_uid132_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_c_inputreg_q : std_logic_vector (75 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_inputreg_q : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (17 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_sticky_ena_q : signal is true;
signal ld_yT1_uid254_sinPiZPolyEval_b_to_reg_yT1_uid254_sinPiZPolyEval_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_0_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q : signal is true;
signal pad_one_uid43_fpSinPiTest_q : std_logic_vector (66 downto 0);
signal signExtExpXRR_uid57_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal udf_uid80_fpSinPiTest_a : std_logic_vector(11 downto 0);
signal udf_uid80_fpSinPiTest_b : std_logic_vector(11 downto 0);
signal udf_uid80_fpSinPiTest_o : std_logic_vector (11 downto 0);
signal udf_uid80_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal udf_uid80_fpSinPiTest_n : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid159_fxpX_uid40_fpSinPiTest_q : std_logic_vector (67 downto 0);
signal InvSinXIsX_uid93_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid93_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oFracXRR_uid36_uid36_fpSinPiTest_q : std_logic_vector (53 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal exp_uid9_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal exp_uid9_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal frac_uid13_fpSinPiTest_in : std_logic_vector (22 downto 0);
signal frac_uid13_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal signX_uid31_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid31_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal expFracX_uid99_px_uid27_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal expFracX_uid99_px_uid27_fpSinPiTest_b : std_logic_vector (30 downto 0);
signal expXIsZero_uid10_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid10_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid10_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid12_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid14_fpSinPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpSinPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal sinXIsX_uid34_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal sinXIsX_uid34_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal sinXIsX_uid34_fpSinPiTest_n : std_logic_vector (0 downto 0);
signal oneMinusY_uid43_fpSinPiTest_a : std_logic_vector(67 downto 0);
signal oneMinusY_uid43_fpSinPiTest_b : std_logic_vector(67 downto 0);
signal oneMinusY_uid43_fpSinPiTest_o : std_logic_vector (67 downto 0);
signal oneMinusY_uid43_fpSinPiTest_q : std_logic_vector (67 downto 0);
signal z_uid48_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal z_uid48_fpSinPiTest_q : std_logic_vector (64 downto 0);
signal expHardCase_uid56_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid56_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid56_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid56_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal xRegAndUdf_uid81_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal xRegAndUdf_uid81_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal xRegAndUdf_uid81_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid82_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid82_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid82_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excSel_uid85_fpSinPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid88_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid88_fpSinPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid92_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid92_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal finalExp_uid142_rrx_uid28_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal finalExp_uid142_rrx_uid28_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid182_lzcZ_uid50_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid182_lzcZ_uid50_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal vCount_uid191_lzcZ_uid50_fpSinPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid191_lzcZ_uid50_fpSinPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid191_lzcZ_uid50_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid194_lzcZ_uid50_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid194_lzcZ_uid50_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid200_lzcZ_uid50_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid200_lzcZ_uid50_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_q : std_logic_vector (64 downto 0);
signal vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_q : std_logic_vector (75 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1_uid301_normMult_uid135_rrx_uid28_fpSinPiTest_q : std_logic_vector (75 downto 0);
signal extendedFracX_uid39_fpSinPiTest_q : std_logic_vector (67 downto 0);
signal normBit_uid68_fpSinPiTest_in : std_logic_vector (51 downto 0);
signal normBit_uid68_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid69_fpSinPiTest_in : std_logic_vector (50 downto 0);
signal highRes_uid69_fpSinPiTest_b : std_logic_vector (23 downto 0);
signal lowRes_uid70_fpSinPiTest_in : std_logic_vector (49 downto 0);
signal lowRes_uid70_fpSinPiTest_b : std_logic_vector (23 downto 0);
signal fracXRExt_uid140_rrx_uid28_fpSinPiTest_q : std_logic_vector (52 downto 0);
signal leftShiftStage2Idx2_uid236_alignedZ_uid51_fpSinPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid162_fxpX_uid40_fpSinPiTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx1_uid233_alignedZ_uid51_fpSinPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx3_uid165_fxpX_uid40_fpSinPiTest_q : std_logic_vector (67 downto 0);
signal cStage_uid174_lzcZ_uid50_fpSinPiTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx2_uid304_normMult_uid135_rrx_uid28_fpSinPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0Idx3_uid307_normMult_uid135_rrx_uid28_fpSinPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage2Idx3_uid239_alignedZ_uid51_fpSinPiTest_q : std_logic_vector (64 downto 0);
signal prodXYTruncFR_uid328_pT1_uid255_sinPiZPolyEval_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid328_pT1_uid255_sinPiZPolyEval_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid331_pT2_uid261_sinPiZPolyEval_in : std_logic_vector (40 downto 0);
signal prodXYTruncFR_uid331_pT2_uid261_sinPiZPolyEval_b : std_logic_vector (23 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_align_0_q_int : std_logic_vector (53 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_align_0_q : std_logic_vector (53 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_align_1_q_int : std_logic_vector (80 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_align_1_q : std_logic_vector (80 downto 0);
signal os_uid129_rrx_uid28_fpSinPiTest_q : std_logic_vector (77 downto 0);
signal finalFrac_uid141_rrx_uid28_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal finalFrac_uid141_rrx_uid28_fpSinPiTest_q : std_logic_vector (52 downto 0);
signal leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_q : std_logic_vector (64 downto 0);
signal join_uid73_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal sinXR_uid97_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal RRangeRed_uid143_rrx_uid28_fpSinPiTest_q : std_logic_vector (61 downto 0);
signal vStagei_uid176_lzcZ_uid50_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid176_lzcZ_uid50_fpSinPiTest_q : std_logic_vector (63 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_align_2_q_int : std_logic_vector (107 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_align_2_q : std_logic_vector (107 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal excSelBits_uid84_fpSinPiTest_q : std_logic_vector (2 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal fracX_uid120_rrx_uid28_fpSinPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid120_rrx_uid28_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal oFracXRRSmallXRR_uid65_fpSinPiTest_in : std_logic_vector (53 downto 0);
signal oFracXRRSmallXRR_uid65_fpSinPiTest_b : std_logic_vector (25 downto 0);
signal R_uid100_px_uid27_fpSinPiTest_q : std_logic_vector (31 downto 0);
signal InvExpXIsZero_uid20_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid20_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid16_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid16_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid19_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid19_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal oMyBottom_uid46_fpSinPiTest_in : std_logic_vector (64 downto 0);
signal oMyBottom_uid46_fpSinPiTest_b : std_logic_vector (64 downto 0);
signal zAddr_uid61_fpSinPiTest_in : std_logic_vector (64 downto 0);
signal zAddr_uid61_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal zPPolyEval_uid62_fpSinPiTest_in : std_logic_vector (56 downto 0);
signal zPPolyEval_uid62_fpSinPiTest_b : std_logic_vector (17 downto 0);
signal rVStage_uid170_lzcZ_uid50_fpSinPiTest_in : std_logic_vector (64 downto 0);
signal rVStage_uid170_lzcZ_uid50_fpSinPiTest_b : std_logic_vector (63 downto 0);
signal vStage_uid173_lzcZ_uid50_fpSinPiTest_in : std_logic_vector (0 downto 0);
signal vStage_uid173_lzcZ_uid50_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal X32dto0_uid214_alignedZ_uid51_fpSinPiTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b : std_logic_vector (32 downto 0);
signal rVStage_uid184_lzcZ_uid50_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid184_lzcZ_uid50_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid186_lzcZ_uid50_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid186_lzcZ_uid50_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid196_lzcZ_uid50_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid196_lzcZ_uid50_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid198_lzcZ_uid50_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid198_lzcZ_uid50_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid202_lzcZ_uid50_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid202_lzcZ_uid50_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid204_lzcZ_uid50_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid204_lzcZ_uid50_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage162dto0_uid232_alignedZ_uid51_fpSinPiTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage162dto0_uid232_alignedZ_uid51_fpSinPiTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage160dto0_uid235_alignedZ_uid51_fpSinPiTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid235_alignedZ_uid51_fpSinPiTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage158dto0_uid238_alignedZ_uid51_fpSinPiTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid238_alignedZ_uid51_fpSinPiTest_b : std_logic_vector (58 downto 0);
signal rVStage_uid276_zCount_uid134_rrx_uid28_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid276_zCount_uid134_rrx_uid28_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid278_zCount_uid134_rrx_uid28_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid278_zCount_uid134_rrx_uid28_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid282_zCount_uid134_rrx_uid28_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid282_zCount_uid134_rrx_uid28_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid284_zCount_uid134_rrx_uid28_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid284_zCount_uid134_rrx_uid28_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid294_zCount_uid134_rrx_uid28_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid294_zCount_uid134_rrx_uid28_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage174dto0_uid322_normMult_uid135_rrx_uid28_fpSinPiTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid322_normMult_uid135_rrx_uid28_fpSinPiTest_b : std_logic_vector (74 downto 0);
signal X63dto0_uid147_fxpX_uid40_fpSinPiTest_in : std_logic_vector (63 downto 0);
signal X63dto0_uid147_fxpX_uid40_fpSinPiTest_b : std_logic_vector (63 downto 0);
signal X59dto0_uid150_fxpX_uid40_fpSinPiTest_in : std_logic_vector (59 downto 0);
signal X59dto0_uid150_fxpX_uid40_fpSinPiTest_b : std_logic_vector (59 downto 0);
signal X55dto0_uid153_fxpX_uid40_fpSinPiTest_in : std_logic_vector (55 downto 0);
signal X55dto0_uid153_fxpX_uid40_fpSinPiTest_b : std_logic_vector (55 downto 0);
signal fracRCompPreRnd_uid71_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid71_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal lowRangeB_uid256_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid256_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid257_sinPiZPolyEval_in : std_logic_vector (13 downto 0);
signal highBBits_uid257_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid262_sinPiZPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid262_sinPiZPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid263_sinPiZPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid263_sinPiZPolyEval_b : std_logic_vector (21 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a_0_in : std_logic_vector (26 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a_0_b : std_logic_vector (26 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a_1_in : std_logic_vector (53 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a_1_b : std_logic_vector (26 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a_2_in : std_logic_vector (80 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_a_2_b : std_logic_vector (26 downto 0);
signal intXParity_uid41_fpSinPiTest_in : std_logic_vector (67 downto 0);
signal intXParity_uid41_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal y_uid42_fpSinPiTest_in : std_logic_vector (66 downto 0);
signal y_uid42_fpSinPiTest_b : std_logic_vector (65 downto 0);
signal LeftShiftStage263dto0_uid243_alignedZ_uid51_fpSinPiTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage263dto0_uid243_alignedZ_uid51_fpSinPiTest_b : std_logic_vector (63 downto 0);
signal rndOp_uid74_uid75_fpSinPiTest_q : std_logic_vector (25 downto 0);
signal expXRR_uid32_fpSinPiTest_in : std_logic_vector (60 downto 0);
signal expXRR_uid32_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal fracXRR_uid33_fpSinPiTest_in : std_logic_vector (52 downto 0);
signal fracXRR_uid33_fpSinPiTest_b : std_logic_vector (52 downto 0);
signal rVStage_uid178_lzcZ_uid50_fpSinPiTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid178_lzcZ_uid50_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid180_lzcZ_uid50_fpSinPiTest_in : std_logic_vector (31 downto 0);
signal vStage_uid180_lzcZ_uid50_fpSinPiTest_b : std_logic_vector (31 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_result_add_1_0_a : std_logic_vector(108 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_result_add_1_0_b : std_logic_vector(108 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_result_add_1_0_o : std_logic_vector (108 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_result_add_1_0_q : std_logic_vector (108 downto 0);
signal oFracX_uid130_uid130_rrx_uid28_fpSinPiTest_q : std_logic_vector (23 downto 0);
signal expX_uid119_rrx_uid28_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid119_rrx_uid28_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal exc_N_uid17_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal yT1_uid254_sinPiZPolyEval_in : std_logic_vector (17 downto 0);
signal yT1_uid254_sinPiZPolyEval_b : std_logic_vector (12 downto 0);
signal vCount_uid185_lzcZ_uid50_fpSinPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid185_lzcZ_uid50_fpSinPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid185_lzcZ_uid50_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid188_lzcZ_uid50_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid188_lzcZ_uid50_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal vCount_uid203_lzcZ_uid50_fpSinPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid203_lzcZ_uid50_fpSinPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid203_lzcZ_uid50_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid206_lzcZ_uid50_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid206_lzcZ_uid50_fpSinPiTest_q : std_logic_vector (1 downto 0);
signal vCount_uid283_zCount_uid134_rrx_uid28_fpSinPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid283_zCount_uid134_rrx_uid28_fpSinPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid283_zCount_uid134_rrx_uid28_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid286_zCount_uid134_rrx_uid28_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid286_zCount_uid134_rrx_uid28_fpSinPiTest_q : std_logic_vector (3 downto 0);
signal vCount_uid295_zCount_uid134_rrx_uid28_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid295_zCount_uid134_rrx_uid28_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid295_zCount_uid134_rrx_uid28_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage2Idx1_uid323_normMult_uid135_rrx_uid28_fpSinPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0Idx1_uid148_fxpX_uid40_fpSinPiTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage0Idx2_uid151_fxpX_uid40_fpSinPiTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage0Idx3_uid154_fxpX_uid40_fpSinPiTest_q : std_logic_vector (67 downto 0);
signal expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid258_sinPiZPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid258_sinPiZPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid258_sinPiZPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid258_sinPiZPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid264_sinPiZPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid264_sinPiZPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid264_sinPiZPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid264_sinPiZPolyEval_q : std_logic_vector (30 downto 0);
signal signComp_uid95_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signComp_uid95_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signComp_uid95_fpSinPiTest_c : std_logic_vector(0 downto 0);
signal signComp_uid95_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal yBottom_uid47_fpSinPiTest_in : std_logic_vector (64 downto 0);
signal yBottom_uid47_fpSinPiTest_b : std_logic_vector (64 downto 0);
signal leftShiftStage3Idx1_uid244_alignedZ_uid51_fpSinPiTest_q : std_logic_vector (64 downto 0);
signal expRCompFracRComp_uid76_fpSinPiTest_a : std_logic_vector(34 downto 0);
signal expRCompFracRComp_uid76_fpSinPiTest_b : std_logic_vector(34 downto 0);
signal expRCompFracRComp_uid76_fpSinPiTest_o : std_logic_vector (34 downto 0);
signal expRCompFracRComp_uid76_fpSinPiTest_q : std_logic_vector (33 downto 0);
signal sinXIsXRR_uid35_fpSinPiTest_a : std_logic_vector(11 downto 0);
signal sinXIsXRR_uid35_fpSinPiTest_b : std_logic_vector(11 downto 0);
signal sinXIsXRR_uid35_fpSinPiTest_o : std_logic_vector (11 downto 0);
signal sinXIsXRR_uid35_fpSinPiTest_cin : std_logic_vector (0 downto 0);
signal sinXIsXRR_uid35_fpSinPiTest_n : std_logic_vector (0 downto 0);
signal fxpXShiftValExt_uid37_fpSinPiTest_a : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid37_fpSinPiTest_b : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid37_fpSinPiTest_o : std_logic_vector (10 downto 0);
signal fxpXShiftValExt_uid37_fpSinPiTest_q : std_logic_vector (9 downto 0);
signal multFracBits_uid132_rrx_uid28_fpSinPiTest_in : std_logic_vector (75 downto 0);
signal multFracBits_uid132_rrx_uid28_fpSinPiTest_b : std_logic_vector (75 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_b_0_in : std_logic_vector (26 downto 0);
signal prod_uid131_rrx_uid28_fpSinPiTest_b_0_b : std_logic_vector (26 downto 0);
signal expXTableAddrExt_uid125_rrx_uid28_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid125_rrx_uid28_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid125_rrx_uid28_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expXTableAddrExt_uid125_rrx_uid28_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal InvExc_N_uid18_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid18_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid83_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid83_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid83_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid190_lzcZ_uid50_fpSinPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid190_lzcZ_uid50_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid192_lzcZ_uid50_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid192_lzcZ_uid50_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid208_lzcZ_uid50_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid208_lzcZ_uid50_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid288_zCount_uid134_rrx_uid28_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid288_zCount_uid134_rrx_uid28_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid290_zCount_uid134_rrx_uid28_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid290_zCount_uid134_rrx_uid28_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_q : std_logic_vector (4 downto 0);
signal leftShiftStage2_uid325_normMult_uid135_rrx_uid28_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage2_uid325_normMult_uid135_rrx_uid28_fpSinPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_q : std_logic_vector (67 downto 0);
signal s1_uid256_uid259_sinPiZPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid262_uid265_sinPiZPolyEval_q : std_logic_vector (32 downto 0);
signal signR_uid96_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid96_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid96_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage3_uid246_alignedZ_uid51_fpSinPiTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid246_alignedZ_uid51_fpSinPiTest_q : std_logic_vector (64 downto 0);
signal fracRComp_uid77_fpSinPiTest_in : std_logic_vector (23 downto 0);
signal fracRComp_uid77_fpSinPiTest_b : std_logic_vector (22 downto 0);
signal expRCompE_uid78_fpSinPiTest_in : std_logic_vector (32 downto 0);
signal expRCompE_uid78_fpSinPiTest_b : std_logic_vector (8 downto 0);
signal fxpXShiftVal_uid38_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal fxpXShiftVal_uid38_fpSinPiTest_b : std_logic_vector (3 downto 0);
signal multFracBitsTop_uid133_rrx_uid28_fpSinPiTest_in : std_logic_vector (75 downto 0);
signal multFracBitsTop_uid133_rrx_uid28_fpSinPiTest_b : std_logic_vector (29 downto 0);
signal X67dto0_uid300_normMult_uid135_rrx_uid28_fpSinPiTest_in : std_logic_vector (67 downto 0);
signal X67dto0_uid300_normMult_uid135_rrx_uid28_fpSinPiTest_b : std_logic_vector (67 downto 0);
signal X59dto0_uid303_normMult_uid135_rrx_uid28_fpSinPiTest_in : std_logic_vector (59 downto 0);
signal X59dto0_uid303_normMult_uid135_rrx_uid28_fpSinPiTest_b : std_logic_vector (59 downto 0);
signal X51dto0_uid306_normMult_uid135_rrx_uid28_fpSinPiTest_in : std_logic_vector (51 downto 0);
signal X51dto0_uid306_normMult_uid135_rrx_uid28_fpSinPiTest_b : std_logic_vector (51 downto 0);
signal expXTableAddr_uid126_rrx_uid28_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expXTableAddr_uid126_rrx_uid28_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal vCount_uid209_lzcZ_uid50_fpSinPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid209_lzcZ_uid50_fpSinPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid209_lzcZ_uid50_fpSinPiTest_q : std_logic_vector(0 downto 0);
signal expCompOutExt_uid137_rrx_uid28_fpSinPiTest_a : std_logic_vector(8 downto 0);
signal expCompOutExt_uid137_rrx_uid28_fpSinPiTest_b : std_logic_vector(8 downto 0);
signal expCompOutExt_uid137_rrx_uid28_fpSinPiTest_o : std_logic_vector (8 downto 0);
signal expCompOutExt_uid137_rrx_uid28_fpSinPiTest_q : std_logic_vector (8 downto 0);
signal leftShiftStageSel4Dto3_uid308_normMult_uid135_rrx_uid28_fpSinPiTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid308_normMult_uid135_rrx_uid28_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid319_normMult_uid135_rrx_uid28_fpSinPiTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid319_normMult_uid135_rrx_uid28_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid324_normMult_uid135_rrx_uid28_fpSinPiTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid324_normMult_uid135_rrx_uid28_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal fracCompOut_uid136_rrx_uid28_fpSinPiTest_in : std_logic_vector (74 downto 0);
signal fracCompOut_uid136_rrx_uid28_fpSinPiTest_b : std_logic_vector (52 downto 0);
signal LeftShiftStage066dto0_uid158_fxpX_uid40_fpSinPiTest_in : std_logic_vector (66 downto 0);
signal LeftShiftStage066dto0_uid158_fxpX_uid40_fpSinPiTest_b : std_logic_vector (66 downto 0);
signal LeftShiftStage065dto0_uid161_fxpX_uid40_fpSinPiTest_in : std_logic_vector (65 downto 0);
signal LeftShiftStage065dto0_uid161_fxpX_uid40_fpSinPiTest_b : std_logic_vector (65 downto 0);
signal LeftShiftStage064dto0_uid164_fxpX_uid40_fpSinPiTest_in : std_logic_vector (64 downto 0);
signal LeftShiftStage064dto0_uid164_fxpX_uid40_fpSinPiTest_b : std_logic_vector (64 downto 0);
signal fxpSinRes_uid64_fpSinPiTest_in : std_logic_vector (30 downto 0);
signal fxpSinRes_uid64_fpSinPiTest_b : std_logic_vector (25 downto 0);
signal pHigh_uid53_fpSinPiTest_in : std_logic_vector (64 downto 0);
signal pHigh_uid53_fpSinPiTest_b : std_logic_vector (25 downto 0);
signal expRComp_uid79_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expRComp_uid79_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal leftShiftStageSel3Dto2_uid155_fxpX_uid40_fpSinPiTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid155_fxpX_uid40_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal rVStage_uid268_zCount_uid134_rrx_uid28_fpSinPiTest_in : std_logic_vector (29 downto 0);
signal rVStage_uid268_zCount_uid134_rrx_uid28_fpSinPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid271_zCount_uid134_rrx_uid28_fpSinPiTest_in : std_logic_vector (13 downto 0);
signal vStage_uid271_zCount_uid134_rrx_uid28_fpSinPiTest_b : std_logic_vector (13 downto 0);
signal r_uid210_lzcZ_uid50_fpSinPiTest_q : std_logic_vector (6 downto 0);
signal expCompOut_uid138_rrx_uid28_fpSinPiTest_in : std_logic_vector (7 downto 0);
signal expCompOut_uid138_rrx_uid28_fpSinPiTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_q : std_logic_vector (75 downto 0);
signal cStage_uid272_zCount_uid134_rrx_uid28_fpSinPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStageSel6Dto5_uid218_alignedZ_uid51_fpSinPiTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid218_alignedZ_uid51_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid229_alignedZ_uid51_fpSinPiTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid229_alignedZ_uid51_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid245_alignedZ_uid51_fpSinPiTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid245_alignedZ_uid51_fpSinPiTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage073dto0_uid311_normMult_uid135_rrx_uid28_fpSinPiTest_in : std_logic_vector (73 downto 0);
signal LeftShiftStage073dto0_uid311_normMult_uid135_rrx_uid28_fpSinPiTest_b : std_logic_vector (73 downto 0);
signal LeftShiftStage071dto0_uid314_normMult_uid135_rrx_uid28_fpSinPiTest_in : std_logic_vector (71 downto 0);
signal LeftShiftStage071dto0_uid314_normMult_uid135_rrx_uid28_fpSinPiTest_b : std_logic_vector (71 downto 0);
signal LeftShiftStage069dto0_uid317_normMult_uid135_rrx_uid28_fpSinPiTest_in : std_logic_vector (69 downto 0);
signal LeftShiftStage069dto0_uid317_normMult_uid135_rrx_uid28_fpSinPiTest_b : std_logic_vector (69 downto 0);
signal leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx1_uid312_normMult_uid135_rrx_uid28_fpSinPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage1Idx2_uid315_normMult_uid135_rrx_uid28_fpSinPiTest_q : std_logic_vector (75 downto 0);
signal leftShiftStage1Idx3_uid318_normMult_uid135_rrx_uid28_fpSinPiTest_q : std_logic_vector (75 downto 0);
signal LeftShiftStage056dto0_uid221_alignedZ_uid51_fpSinPiTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage056dto0_uid221_alignedZ_uid51_fpSinPiTest_b : std_logic_vector (56 downto 0);
signal LeftShiftStage048dto0_uid224_alignedZ_uid51_fpSinPiTest_in : std_logic_vector (48 downto 0);
signal LeftShiftStage048dto0_uid224_alignedZ_uid51_fpSinPiTest_b : std_logic_vector (48 downto 0);
signal LeftShiftStage040dto0_uid227_alignedZ_uid51_fpSinPiTest_in : std_logic_vector (40 downto 0);
signal LeftShiftStage040dto0_uid227_alignedZ_uid51_fpSinPiTest_b : std_logic_vector (40 downto 0);
signal leftShiftStage1Idx1_uid222_alignedZ_uid51_fpSinPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid225_alignedZ_uid51_fpSinPiTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx3_uid228_alignedZ_uid51_fpSinPiTest_q : std_logic_vector (64 downto 0);
begin
--xIn(GPIN,3)@0
--X55dto0_uid153_fxpX_uid40_fpSinPiTest(BITSELECT,152)@15
X55dto0_uid153_fxpX_uid40_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(55 downto 0);
X55dto0_uid153_fxpX_uid40_fpSinPiTest_b <= X55dto0_uid153_fxpX_uid40_fpSinPiTest_in(55 downto 0);
--leftShiftStage0Idx3Pad12_uid152_fxpX_uid40_fpSinPiTest(CONSTANT,151)
leftShiftStage0Idx3Pad12_uid152_fxpX_uid40_fpSinPiTest_q <= "000000000000";
--leftShiftStage0Idx3_uid154_fxpX_uid40_fpSinPiTest(BITJOIN,153)@15
leftShiftStage0Idx3_uid154_fxpX_uid40_fpSinPiTest_q <= X55dto0_uid153_fxpX_uid40_fpSinPiTest_b & leftShiftStage0Idx3Pad12_uid152_fxpX_uid40_fpSinPiTest_q;
--X59dto0_uid150_fxpX_uid40_fpSinPiTest(BITSELECT,149)@15
X59dto0_uid150_fxpX_uid40_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(59 downto 0);
X59dto0_uid150_fxpX_uid40_fpSinPiTest_b <= X59dto0_uid150_fxpX_uid40_fpSinPiTest_in(59 downto 0);
--cstAllZWE_uid8_fpSinPiTest(CONSTANT,7)
cstAllZWE_uid8_fpSinPiTest_q <= "00000000";
--leftShiftStage0Idx2_uid151_fxpX_uid40_fpSinPiTest(BITJOIN,150)@15
leftShiftStage0Idx2_uid151_fxpX_uid40_fpSinPiTest_q <= X59dto0_uid150_fxpX_uid40_fpSinPiTest_b & cstAllZWE_uid8_fpSinPiTest_q;
--X63dto0_uid147_fxpX_uid40_fpSinPiTest(BITSELECT,146)@15
X63dto0_uid147_fxpX_uid40_fpSinPiTest_in <= extendedFracX_uid39_fpSinPiTest_q(63 downto 0);
X63dto0_uid147_fxpX_uid40_fpSinPiTest_b <= X63dto0_uid147_fxpX_uid40_fpSinPiTest_in(63 downto 0);
--leftShiftStage0Idx1Pad4_uid146_fxpX_uid40_fpSinPiTest(CONSTANT,145)
leftShiftStage0Idx1Pad4_uid146_fxpX_uid40_fpSinPiTest_q <= "0000";
--leftShiftStage0Idx1_uid148_fxpX_uid40_fpSinPiTest(BITJOIN,147)@15
leftShiftStage0Idx1_uid148_fxpX_uid40_fpSinPiTest_q <= X63dto0_uid147_fxpX_uid40_fpSinPiTest_b & leftShiftStage0Idx1Pad4_uid146_fxpX_uid40_fpSinPiTest_q;
--cstZwShiftP1_uid25_fpSinPiTest(CONSTANT,24)
cstZwShiftP1_uid25_fpSinPiTest_q <= "00000000000000";
--VCC(CONSTANT,1)
VCC_q <= "1";
--GND(CONSTANT,0)
GND_q <= "0";
--ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable(LOGICAL,818)
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_a <= en;
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q <= not ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_a;
--ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_nor(LOGICAL,971)
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_nor_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q;
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_nor_b <= ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_sticky_ena_q;
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_nor_q <= not (ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_nor_a or ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_nor_b);
--ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_mem_top(CONSTANT,967)
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_mem_top_q <= "01010";
--ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_cmp(LOGICAL,968)
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_cmp_a <= ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_mem_top_q;
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdmux_q);
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_cmp_q <= "1" when ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_cmp_a = ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_cmp_b else "0";
--ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_cmpReg(REG,969)
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_cmpReg_q <= ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_sticky_ena(REG,972)
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_nor_q = "1") THEN
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_sticky_ena_q <= ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_enaAnd(LOGICAL,973)
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_enaAnd_a <= ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_sticky_ena_q;
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_enaAnd_b <= en;
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_enaAnd_q <= ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_enaAnd_a and ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_enaAnd_b;
--expFracX_uid99_px_uid27_fpSinPiTest(BITSELECT,98)@0
expFracX_uid99_px_uid27_fpSinPiTest_in <= a(30 downto 0);
expFracX_uid99_px_uid27_fpSinPiTest_b <= expFracX_uid99_px_uid27_fpSinPiTest_in(30 downto 0);
--R_uid100_px_uid27_fpSinPiTest(BITJOIN,99)@0
R_uid100_px_uid27_fpSinPiTest_q <= GND_q & expFracX_uid99_px_uid27_fpSinPiTest_b;
--expX_uid119_rrx_uid28_fpSinPiTest(BITSELECT,118)@0
expX_uid119_rrx_uid28_fpSinPiTest_in <= R_uid100_px_uid27_fpSinPiTest_q(30 downto 0);
expX_uid119_rrx_uid28_fpSinPiTest_b <= expX_uid119_rrx_uid28_fpSinPiTest_in(30 downto 23);
--ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_inputreg(DELAY,961)
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid119_rrx_uid28_fpSinPiTest_b, xout => ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt(COUNTER,963)
-- every=1, low=0, high=10, step=1, init=1
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_i = 9 THEN
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_i <= ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_i - 10;
ELSE
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_i <= ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_i,4));
--ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdreg(REG,964)
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdreg_q <= ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdmux(MUX,965)
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdmux_s <= en;
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdmux: PROCESS (ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdmux_s, ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdreg_q, ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdmux_q <= ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdmux_q <= ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem(DUALMEM,962)
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_ia <= ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_inputreg_q;
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_aa <= ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdreg_q;
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_ab <= ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_rdmux_q;
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 11,
width_b => 8,
widthad_b => 4,
numwords_b => 11,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_iq,
address_a => ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_aa,
data_a => ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_ia
);
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_reset0 <= areset;
ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_q <= ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_iq(7 downto 0);
--zs_uid183_lzcZ_uid50_fpSinPiTest(CONSTANT,182)
zs_uid183_lzcZ_uid50_fpSinPiTest_q <= "0000000000000000";
--ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_nor(LOGICAL,945)
ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_nor_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q;
ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_nor_b <= ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_sticky_ena_q;
ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_nor_q <= not (ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_nor_a or ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_nor_b);
--ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_cmpReg(REG,841)
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_sticky_ena(REG,946)
ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_nor_q = "1") THEN
ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_sticky_ena_q <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_enaAnd(LOGICAL,947)
ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_enaAnd_a <= ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_sticky_ena_q;
ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_enaAnd_b <= en;
ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_enaAnd_q <= ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_enaAnd_a and ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_enaAnd_b;
--ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_inputreg(DELAY,937)
ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid100_px_uid27_fpSinPiTest_q, xout => ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdcnt(COUNTER,837)
-- every=1, low=0, high=1, step=1, init=1
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdcnt_i <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdcnt_i,1));
--ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdreg(REG,838)
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdreg_q <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdmux(MUX,839)
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdmux_s <= en;
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdmux: PROCESS (ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdmux_s, ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdreg_q, ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdmux_q <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdreg_q;
WHEN "1" => ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdmux_q <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem(DUALMEM,938)
ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_ia <= ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_inputreg_q;
ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_aa <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdreg_q;
ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_ab <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdmux_q;
ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 1,
numwords_a => 2,
width_b => 32,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_iq,
address_a => ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_aa,
data_a => ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_ia
);
ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_reset0 <= areset;
ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_q <= ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_iq(31 downto 0);
--fracX_uid120_rrx_uid28_fpSinPiTest(BITSELECT,119)@4
fracX_uid120_rrx_uid28_fpSinPiTest_in <= ld_R_uid100_px_uid27_fpSinPiTest_q_to_fracX_uid120_rrx_uid28_fpSinPiTest_a_replace_mem_q(22 downto 0);
fracX_uid120_rrx_uid28_fpSinPiTest_b <= fracX_uid120_rrx_uid28_fpSinPiTest_in(22 downto 0);
--oFracX_uid130_uid130_rrx_uid28_fpSinPiTest(BITJOIN,129)@4
oFracX_uid130_uid130_rrx_uid28_fpSinPiTest_q <= VCC_q & fracX_uid120_rrx_uid28_fpSinPiTest_b;
--prod_uid131_rrx_uid28_fpSinPiTest_b_0(BITSELECT,337)@4
prod_uid131_rrx_uid28_fpSinPiTest_b_0_in <= STD_LOGIC_VECTOR("000" & oFracX_uid130_uid130_rrx_uid28_fpSinPiTest_q);
prod_uid131_rrx_uid28_fpSinPiTest_b_0_b <= prod_uid131_rrx_uid28_fpSinPiTest_b_0_in(26 downto 0);
--reg_prod_uid131_rrx_uid28_fpSinPiTest_b_0_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_1(REG,354)@4
reg_prod_uid131_rrx_uid28_fpSinPiTest_b_0_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid131_rrx_uid28_fpSinPiTest_b_0_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid131_rrx_uid28_fpSinPiTest_b_0_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_1_q <= prod_uid131_rrx_uid28_fpSinPiTest_b_0_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShift_uid22_fpSinPiTest(CONSTANT,21)
cstBiasMwShift_uid22_fpSinPiTest_q <= "01110011";
--expXTableAddrExt_uid125_rrx_uid28_fpSinPiTest(SUB,124)@0
expXTableAddrExt_uid125_rrx_uid28_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid119_rrx_uid28_fpSinPiTest_b);
expXTableAddrExt_uid125_rrx_uid28_fpSinPiTest_b <= STD_LOGIC_VECTOR("0" & cstBiasMwShift_uid22_fpSinPiTest_q);
expXTableAddrExt_uid125_rrx_uid28_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXTableAddrExt_uid125_rrx_uid28_fpSinPiTest_a) - UNSIGNED(expXTableAddrExt_uid125_rrx_uid28_fpSinPiTest_b));
expXTableAddrExt_uid125_rrx_uid28_fpSinPiTest_q <= expXTableAddrExt_uid125_rrx_uid28_fpSinPiTest_o(8 downto 0);
--expXTableAddr_uid126_rrx_uid28_fpSinPiTest(BITSELECT,125)@0
expXTableAddr_uid126_rrx_uid28_fpSinPiTest_in <= expXTableAddrExt_uid125_rrx_uid28_fpSinPiTest_q(7 downto 0);
expXTableAddr_uid126_rrx_uid28_fpSinPiTest_b <= expXTableAddr_uid126_rrx_uid28_fpSinPiTest_in(7 downto 0);
--reg_expXTableAddr_uid126_rrx_uid28_fpSinPiTest_0_to_rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_0(REG,349)@0
reg_expXTableAddr_uid126_rrx_uid28_fpSinPiTest_0_to_rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXTableAddr_uid126_rrx_uid28_fpSinPiTest_0_to_rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXTableAddr_uid126_rrx_uid28_fpSinPiTest_0_to_rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_0_q <= expXTableAddr_uid126_rrx_uid28_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem(DUALMEM,333)@1
rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_ia <= (others => '0');
rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_aa <= (others => '0');
rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_ab <= reg_expXTableAddr_uid126_rrx_uid28_fpSinPiTest_0_to_rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_0_q;
rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 38,
widthad_a => 8,
numwords_a => 140,
width_b => 38,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sin_s5_rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_iq,
address_a => rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_aa,
data_a => rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_ia
);
rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_reset0 <= areset;
rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_q <= rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_iq(37 downto 0);
--reg_rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_0_to_os_uid129_rrx_uid28_fpSinPiTest_1(REG,352)@3
reg_rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_0_to_os_uid129_rrx_uid28_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_0_to_os_uid129_rrx_uid28_fpSinPiTest_1_q <= "00000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_0_to_os_uid129_rrx_uid28_fpSinPiTest_1_q <= rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem(DUALMEM,332)@1
rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_ia <= (others => '0');
rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_aa <= (others => '0');
rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_ab <= reg_expXTableAddr_uid126_rrx_uid28_fpSinPiTest_0_to_rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_0_q;
rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sin_s5_rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_iq,
address_a => rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_aa,
data_a => rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_ia
);
rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_reset0 <= areset;
rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_q <= rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_0_to_os_uid129_rrx_uid28_fpSinPiTest_0(REG,351)@3
reg_rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_0_to_os_uid129_rrx_uid28_fpSinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_0_to_os_uid129_rrx_uid28_fpSinPiTest_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_0_to_os_uid129_rrx_uid28_fpSinPiTest_0_q <= rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid129_rrx_uid28_fpSinPiTest(BITJOIN,128)@4
os_uid129_rrx_uid28_fpSinPiTest_q <= reg_rrTable_uid128_rrx_uid28_fpSinPiTest_lutmem_0_to_os_uid129_rrx_uid28_fpSinPiTest_1_q & reg_rrTable_uid127_rrx_uid28_fpSinPiTest_lutmem_0_to_os_uid129_rrx_uid28_fpSinPiTest_0_q;
--prod_uid131_rrx_uid28_fpSinPiTest_a_2(BITSELECT,336)@4
prod_uid131_rrx_uid28_fpSinPiTest_a_2_in <= STD_LOGIC_VECTOR("000" & os_uid129_rrx_uid28_fpSinPiTest_q);
prod_uid131_rrx_uid28_fpSinPiTest_a_2_b <= prod_uid131_rrx_uid28_fpSinPiTest_a_2_in(80 downto 54);
--reg_prod_uid131_rrx_uid28_fpSinPiTest_a_2_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_0(REG,357)@4
reg_prod_uid131_rrx_uid28_fpSinPiTest_a_2_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid131_rrx_uid28_fpSinPiTest_a_2_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid131_rrx_uid28_fpSinPiTest_a_2_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_0_q <= prod_uid131_rrx_uid28_fpSinPiTest_a_2_b;
END IF;
END IF;
END PROCESS;
--prod_uid131_rrx_uid28_fpSinPiTest_a2_b0(MULT,340)@5
prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_pr <= UNSIGNED(prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_a) * UNSIGNED(prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_b);
prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_a <= (others => '0');
prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_b <= (others => '0');
prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_a <= reg_prod_uid131_rrx_uid28_fpSinPiTest_a_2_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_0_q;
prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_b <= reg_prod_uid131_rrx_uid28_fpSinPiTest_b_0_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_1_q;
prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_s1 <= STD_LOGIC_VECTOR(prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid131_rrx_uid28_fpSinPiTest_a2_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_q <= prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_s1;
END IF;
END IF;
END PROCESS;
--ld_prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_q_to_prod_uid131_rrx_uid28_fpSinPiTest_align_2_a(DELAY,736)@8
ld_prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_q_to_prod_uid131_rrx_uid28_fpSinPiTest_align_2_a : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_q, xout => ld_prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_q_to_prod_uid131_rrx_uid28_fpSinPiTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--prod_uid131_rrx_uid28_fpSinPiTest_align_2(BITSHIFT,343)@9
prod_uid131_rrx_uid28_fpSinPiTest_align_2_q_int <= ld_prod_uid131_rrx_uid28_fpSinPiTest_a2_b0_q_to_prod_uid131_rrx_uid28_fpSinPiTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
prod_uid131_rrx_uid28_fpSinPiTest_align_2_q <= prod_uid131_rrx_uid28_fpSinPiTest_align_2_q_int(107 downto 0);
--prod_uid131_rrx_uid28_fpSinPiTest_a_1(BITSELECT,335)@4
prod_uid131_rrx_uid28_fpSinPiTest_a_1_in <= os_uid129_rrx_uid28_fpSinPiTest_q(53 downto 0);
prod_uid131_rrx_uid28_fpSinPiTest_a_1_b <= prod_uid131_rrx_uid28_fpSinPiTest_a_1_in(53 downto 27);
--reg_prod_uid131_rrx_uid28_fpSinPiTest_a_1_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_0(REG,355)@4
reg_prod_uid131_rrx_uid28_fpSinPiTest_a_1_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid131_rrx_uid28_fpSinPiTest_a_1_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid131_rrx_uid28_fpSinPiTest_a_1_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_0_q <= prod_uid131_rrx_uid28_fpSinPiTest_a_1_b;
END IF;
END IF;
END PROCESS;
--prod_uid131_rrx_uid28_fpSinPiTest_a1_b0(MULT,339)@5
prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_pr <= UNSIGNED(prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_a) * UNSIGNED(prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_b);
prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_a <= (others => '0');
prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_b <= (others => '0');
prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_a <= reg_prod_uid131_rrx_uid28_fpSinPiTest_a_1_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_0_q;
prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_b <= reg_prod_uid131_rrx_uid28_fpSinPiTest_b_0_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_1_q;
prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_s1 <= STD_LOGIC_VECTOR(prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid131_rrx_uid28_fpSinPiTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_q <= prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid131_rrx_uid28_fpSinPiTest_align_1(BITSHIFT,342)@8
prod_uid131_rrx_uid28_fpSinPiTest_align_1_q_int <= prod_uid131_rrx_uid28_fpSinPiTest_a1_b0_q & "000000000000000000000000000";
prod_uid131_rrx_uid28_fpSinPiTest_align_1_q <= prod_uid131_rrx_uid28_fpSinPiTest_align_1_q_int(80 downto 0);
--prod_uid131_rrx_uid28_fpSinPiTest_a_0(BITSELECT,334)@4
prod_uid131_rrx_uid28_fpSinPiTest_a_0_in <= os_uid129_rrx_uid28_fpSinPiTest_q(26 downto 0);
prod_uid131_rrx_uid28_fpSinPiTest_a_0_b <= prod_uid131_rrx_uid28_fpSinPiTest_a_0_in(26 downto 0);
--reg_prod_uid131_rrx_uid28_fpSinPiTest_a_0_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_0(REG,353)@4
reg_prod_uid131_rrx_uid28_fpSinPiTest_a_0_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid131_rrx_uid28_fpSinPiTest_a_0_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid131_rrx_uid28_fpSinPiTest_a_0_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_0_q <= prod_uid131_rrx_uid28_fpSinPiTest_a_0_b;
END IF;
END IF;
END PROCESS;
--prod_uid131_rrx_uid28_fpSinPiTest_a0_b0(MULT,338)@5
prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_pr <= UNSIGNED(prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_a) * UNSIGNED(prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_b);
prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_a <= (others => '0');
prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_b <= (others => '0');
prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_a <= reg_prod_uid131_rrx_uid28_fpSinPiTest_a_0_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_0_q;
prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_b <= reg_prod_uid131_rrx_uid28_fpSinPiTest_b_0_0_to_prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_1_q;
prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_s1 <= STD_LOGIC_VECTOR(prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid131_rrx_uid28_fpSinPiTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_q <= prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid131_rrx_uid28_fpSinPiTest_align_0(BITSHIFT,341)@8
prod_uid131_rrx_uid28_fpSinPiTest_align_0_q_int <= prod_uid131_rrx_uid28_fpSinPiTest_a0_b0_q;
prod_uid131_rrx_uid28_fpSinPiTest_align_0_q <= prod_uid131_rrx_uid28_fpSinPiTest_align_0_q_int(53 downto 0);
--prod_uid131_rrx_uid28_fpSinPiTest_result_add_0_0(ADD,344)@8
prod_uid131_rrx_uid28_fpSinPiTest_result_add_0_0_a <= STD_LOGIC_VECTOR("0000000000000000000000000000" & prod_uid131_rrx_uid28_fpSinPiTest_align_0_q);
prod_uid131_rrx_uid28_fpSinPiTest_result_add_0_0_b <= STD_LOGIC_VECTOR("0" & prod_uid131_rrx_uid28_fpSinPiTest_align_1_q);
prod_uid131_rrx_uid28_fpSinPiTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid131_rrx_uid28_fpSinPiTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prod_uid131_rrx_uid28_fpSinPiTest_result_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid131_rrx_uid28_fpSinPiTest_result_add_0_0_a) + UNSIGNED(prod_uid131_rrx_uid28_fpSinPiTest_result_add_0_0_b));
END IF;
END PROCESS;
prod_uid131_rrx_uid28_fpSinPiTest_result_add_0_0_q <= prod_uid131_rrx_uid28_fpSinPiTest_result_add_0_0_o(81 downto 0);
--prod_uid131_rrx_uid28_fpSinPiTest_result_add_1_0(ADD,345)@9
prod_uid131_rrx_uid28_fpSinPiTest_result_add_1_0_a <= STD_LOGIC_VECTOR("000000000000000000000000000" & prod_uid131_rrx_uid28_fpSinPiTest_result_add_0_0_q);
prod_uid131_rrx_uid28_fpSinPiTest_result_add_1_0_b <= STD_LOGIC_VECTOR("0" & prod_uid131_rrx_uid28_fpSinPiTest_align_2_q);
prod_uid131_rrx_uid28_fpSinPiTest_result_add_1_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid131_rrx_uid28_fpSinPiTest_result_add_1_0_a) + UNSIGNED(prod_uid131_rrx_uid28_fpSinPiTest_result_add_1_0_b));
prod_uid131_rrx_uid28_fpSinPiTest_result_add_1_0_q <= prod_uid131_rrx_uid28_fpSinPiTest_result_add_1_0_o(108 downto 0);
--multFracBits_uid132_rrx_uid28_fpSinPiTest(BITSELECT,131)@9
multFracBits_uid132_rrx_uid28_fpSinPiTest_in <= prod_uid131_rrx_uid28_fpSinPiTest_result_add_1_0_q(75 downto 0);
multFracBits_uid132_rrx_uid28_fpSinPiTest_b <= multFracBits_uid132_rrx_uid28_fpSinPiTest_in(75 downto 0);
--multFracBitsTop_uid133_rrx_uid28_fpSinPiTest(BITSELECT,132)@9
multFracBitsTop_uid133_rrx_uid28_fpSinPiTest_in <= multFracBits_uid132_rrx_uid28_fpSinPiTest_b;
multFracBitsTop_uid133_rrx_uid28_fpSinPiTest_b <= multFracBitsTop_uid133_rrx_uid28_fpSinPiTest_in(75 downto 46);
--rVStage_uid268_zCount_uid134_rrx_uid28_fpSinPiTest(BITSELECT,267)@9
rVStage_uid268_zCount_uid134_rrx_uid28_fpSinPiTest_in <= multFracBitsTop_uid133_rrx_uid28_fpSinPiTest_b;
rVStage_uid268_zCount_uid134_rrx_uid28_fpSinPiTest_b <= rVStage_uid268_zCount_uid134_rrx_uid28_fpSinPiTest_in(29 downto 14);
--reg_rVStage_uid268_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_1(REG,359)@9
reg_rVStage_uid268_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid268_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid268_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_1_q <= rVStage_uid268_zCount_uid134_rrx_uid28_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest(LOGICAL,268)@10
vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_a <= reg_rVStage_uid268_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_1_q;
vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_b <= zs_uid183_lzcZ_uid50_fpSinPiTest_q;
vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_q <= "1" when vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_a = vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_b else "0";
--ld_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_q_to_reg_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_4_a(DELAY,762)@10
ld_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_q_to_reg_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_q, xout => ld_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_q_to_reg_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_4(REG,367)@11
reg_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_4_q <= ld_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_q_to_reg_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid271_zCount_uid134_rrx_uid28_fpSinPiTest(BITSELECT,270)@9
vStage_uid271_zCount_uid134_rrx_uid28_fpSinPiTest_in <= multFracBitsTop_uid133_rrx_uid28_fpSinPiTest_b(13 downto 0);
vStage_uid271_zCount_uid134_rrx_uid28_fpSinPiTest_b <= vStage_uid271_zCount_uid134_rrx_uid28_fpSinPiTest_in(13 downto 0);
--mO_uid270_zCount_uid134_rrx_uid28_fpSinPiTest(CONSTANT,269)
mO_uid270_zCount_uid134_rrx_uid28_fpSinPiTest_q <= "11";
--cStage_uid272_zCount_uid134_rrx_uid28_fpSinPiTest(BITJOIN,271)@9
cStage_uid272_zCount_uid134_rrx_uid28_fpSinPiTest_q <= vStage_uid271_zCount_uid134_rrx_uid28_fpSinPiTest_b & mO_uid270_zCount_uid134_rrx_uid28_fpSinPiTest_q;
--reg_cStage_uid272_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest_3(REG,361)@9
reg_cStage_uid272_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid272_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid272_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest_3_q <= cStage_uid272_zCount_uid134_rrx_uid28_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest(MUX,273)@10
vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest_s <= vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_q;
vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest: PROCESS (vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest_s, en, reg_rVStage_uid268_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_1_q, reg_cStage_uid272_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest_s IS
WHEN "0" => vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest_q <= reg_rVStage_uid268_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_1_q;
WHEN "1" => vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest_q <= reg_cStage_uid272_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid276_zCount_uid134_rrx_uid28_fpSinPiTest(BITSELECT,275)@10
rVStage_uid276_zCount_uid134_rrx_uid28_fpSinPiTest_in <= vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest_q;
rVStage_uid276_zCount_uid134_rrx_uid28_fpSinPiTest_b <= rVStage_uid276_zCount_uid134_rrx_uid28_fpSinPiTest_in(15 downto 8);
--vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest(LOGICAL,276)@10
vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest_a <= rVStage_uid276_zCount_uid134_rrx_uid28_fpSinPiTest_b;
vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest_b <= cstAllZWE_uid8_fpSinPiTest_q;
vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest_a = vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest_b) THEN
vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest_q <= "1";
ELSE
vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest_q_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_d(DELAY,684)@11
ld_vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest_q_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest_q, xout => ld_vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest_q_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid278_zCount_uid134_rrx_uid28_fpSinPiTest(BITSELECT,277)@10
vStage_uid278_zCount_uid134_rrx_uid28_fpSinPiTest_in <= vStagei_uid274_zCount_uid134_rrx_uid28_fpSinPiTest_q(7 downto 0);
vStage_uid278_zCount_uid134_rrx_uid28_fpSinPiTest_b <= vStage_uid278_zCount_uid134_rrx_uid28_fpSinPiTest_in(7 downto 0);
--reg_vStage_uid278_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_3(REG,363)@10
reg_vStage_uid278_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid278_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid278_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_3_q <= vStage_uid278_zCount_uid134_rrx_uid28_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid276_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_2(REG,362)@10
reg_rVStage_uid276_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid276_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid276_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_2_q <= rVStage_uid276_zCount_uid134_rrx_uid28_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest(MUX,279)@11
vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_s <= vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest_q;
vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest: PROCESS (vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_s, en, reg_rVStage_uid276_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_2_q, reg_vStage_uid278_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_s IS
WHEN "0" => vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_q <= reg_rVStage_uid276_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_2_q;
WHEN "1" => vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_q <= reg_vStage_uid278_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid282_zCount_uid134_rrx_uid28_fpSinPiTest(BITSELECT,281)@11
rVStage_uid282_zCount_uid134_rrx_uid28_fpSinPiTest_in <= vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_q;
rVStage_uid282_zCount_uid134_rrx_uid28_fpSinPiTest_b <= rVStage_uid282_zCount_uid134_rrx_uid28_fpSinPiTest_in(7 downto 4);
--vCount_uid283_zCount_uid134_rrx_uid28_fpSinPiTest(LOGICAL,282)@11
vCount_uid283_zCount_uid134_rrx_uid28_fpSinPiTest_a <= rVStage_uid282_zCount_uid134_rrx_uid28_fpSinPiTest_b;
vCount_uid283_zCount_uid134_rrx_uid28_fpSinPiTest_b <= leftShiftStage0Idx1Pad4_uid146_fxpX_uid40_fpSinPiTest_q;
vCount_uid283_zCount_uid134_rrx_uid28_fpSinPiTest_q <= "1" when vCount_uid283_zCount_uid134_rrx_uid28_fpSinPiTest_a = vCount_uid283_zCount_uid134_rrx_uid28_fpSinPiTest_b else "0";
--reg_vCount_uid283_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_2(REG,366)@11
reg_vCount_uid283_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid283_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid283_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_2_q <= vCount_uid283_zCount_uid134_rrx_uid28_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1Idx2Pad2_uid160_fxpX_uid40_fpSinPiTest(CONSTANT,159)
leftShiftStage1Idx2Pad2_uid160_fxpX_uid40_fpSinPiTest_q <= "00";
--vStage_uid284_zCount_uid134_rrx_uid28_fpSinPiTest(BITSELECT,283)@11
vStage_uid284_zCount_uid134_rrx_uid28_fpSinPiTest_in <= vStagei_uid280_zCount_uid134_rrx_uid28_fpSinPiTest_q(3 downto 0);
vStage_uid284_zCount_uid134_rrx_uid28_fpSinPiTest_b <= vStage_uid284_zCount_uid134_rrx_uid28_fpSinPiTest_in(3 downto 0);
--vStagei_uid286_zCount_uid134_rrx_uid28_fpSinPiTest(MUX,285)@11
vStagei_uid286_zCount_uid134_rrx_uid28_fpSinPiTest_s <= vCount_uid283_zCount_uid134_rrx_uid28_fpSinPiTest_q;
vStagei_uid286_zCount_uid134_rrx_uid28_fpSinPiTest: PROCESS (vStagei_uid286_zCount_uid134_rrx_uid28_fpSinPiTest_s, en, rVStage_uid282_zCount_uid134_rrx_uid28_fpSinPiTest_b, vStage_uid284_zCount_uid134_rrx_uid28_fpSinPiTest_b)
BEGIN
CASE vStagei_uid286_zCount_uid134_rrx_uid28_fpSinPiTest_s IS
WHEN "0" => vStagei_uid286_zCount_uid134_rrx_uid28_fpSinPiTest_q <= rVStage_uid282_zCount_uid134_rrx_uid28_fpSinPiTest_b;
WHEN "1" => vStagei_uid286_zCount_uid134_rrx_uid28_fpSinPiTest_q <= vStage_uid284_zCount_uid134_rrx_uid28_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid286_zCount_uid134_rrx_uid28_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid288_zCount_uid134_rrx_uid28_fpSinPiTest(BITSELECT,287)@11
rVStage_uid288_zCount_uid134_rrx_uid28_fpSinPiTest_in <= vStagei_uid286_zCount_uid134_rrx_uid28_fpSinPiTest_q;
rVStage_uid288_zCount_uid134_rrx_uid28_fpSinPiTest_b <= rVStage_uid288_zCount_uid134_rrx_uid28_fpSinPiTest_in(3 downto 2);
--vCount_uid289_zCount_uid134_rrx_uid28_fpSinPiTest(LOGICAL,288)@11
vCount_uid289_zCount_uid134_rrx_uid28_fpSinPiTest_a <= rVStage_uid288_zCount_uid134_rrx_uid28_fpSinPiTest_b;
vCount_uid289_zCount_uid134_rrx_uid28_fpSinPiTest_b <= leftShiftStage1Idx2Pad2_uid160_fxpX_uid40_fpSinPiTest_q;
vCount_uid289_zCount_uid134_rrx_uid28_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid289_zCount_uid134_rrx_uid28_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid289_zCount_uid134_rrx_uid28_fpSinPiTest_a = vCount_uid289_zCount_uid134_rrx_uid28_fpSinPiTest_b) THEN
vCount_uid289_zCount_uid134_rrx_uid28_fpSinPiTest_q <= "1";
ELSE
vCount_uid289_zCount_uid134_rrx_uid28_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid290_zCount_uid134_rrx_uid28_fpSinPiTest(BITSELECT,289)@11
vStage_uid290_zCount_uid134_rrx_uid28_fpSinPiTest_in <= vStagei_uid286_zCount_uid134_rrx_uid28_fpSinPiTest_q(1 downto 0);
vStage_uid290_zCount_uid134_rrx_uid28_fpSinPiTest_b <= vStage_uid290_zCount_uid134_rrx_uid28_fpSinPiTest_in(1 downto 0);
--reg_vStage_uid290_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_3(REG,365)@11
reg_vStage_uid290_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid290_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid290_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_3_q <= vStage_uid290_zCount_uid134_rrx_uid28_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid288_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_2(REG,364)@11
reg_rVStage_uid288_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid288_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid288_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_2_q <= rVStage_uid288_zCount_uid134_rrx_uid28_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest(MUX,291)@12
vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_s <= vCount_uid289_zCount_uid134_rrx_uid28_fpSinPiTest_q;
vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest: PROCESS (vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_s, en, reg_rVStage_uid288_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_2_q, reg_vStage_uid290_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_s IS
WHEN "0" => vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_q <= reg_rVStage_uid288_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_2_q;
WHEN "1" => vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_q <= reg_vStage_uid290_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid294_zCount_uid134_rrx_uid28_fpSinPiTest(BITSELECT,293)@12
rVStage_uid294_zCount_uid134_rrx_uid28_fpSinPiTest_in <= vStagei_uid292_zCount_uid134_rrx_uid28_fpSinPiTest_q;
rVStage_uid294_zCount_uid134_rrx_uid28_fpSinPiTest_b <= rVStage_uid294_zCount_uid134_rrx_uid28_fpSinPiTest_in(1 downto 1);
--vCount_uid295_zCount_uid134_rrx_uid28_fpSinPiTest(LOGICAL,294)@12
vCount_uid295_zCount_uid134_rrx_uid28_fpSinPiTest_a <= rVStage_uid294_zCount_uid134_rrx_uid28_fpSinPiTest_b;
vCount_uid295_zCount_uid134_rrx_uid28_fpSinPiTest_b <= GND_q;
vCount_uid295_zCount_uid134_rrx_uid28_fpSinPiTest_q <= "1" when vCount_uid295_zCount_uid134_rrx_uid28_fpSinPiTest_a = vCount_uid295_zCount_uid134_rrx_uid28_fpSinPiTest_b else "0";
--r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest(BITJOIN,295)@12
r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_q <= reg_vCount_uid269_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_4_q & ld_vCount_uid277_zCount_uid134_rrx_uid28_fpSinPiTest_q_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_d_q & reg_vCount_uid283_zCount_uid134_rrx_uid28_fpSinPiTest_0_to_r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_2_q & vCount_uid289_zCount_uid134_rrx_uid28_fpSinPiTest_q & vCount_uid295_zCount_uid134_rrx_uid28_fpSinPiTest_q;
--biasM1_uid55_fpSinPiTest(CONSTANT,54)
biasM1_uid55_fpSinPiTest_q <= "01111110";
--expCompOutExt_uid137_rrx_uid28_fpSinPiTest(SUB,136)@12
expCompOutExt_uid137_rrx_uid28_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid55_fpSinPiTest_q);
expCompOutExt_uid137_rrx_uid28_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000" & r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_q);
expCompOutExt_uid137_rrx_uid28_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expCompOutExt_uid137_rrx_uid28_fpSinPiTest_a) - UNSIGNED(expCompOutExt_uid137_rrx_uid28_fpSinPiTest_b));
expCompOutExt_uid137_rrx_uid28_fpSinPiTest_q <= expCompOutExt_uid137_rrx_uid28_fpSinPiTest_o(8 downto 0);
--expCompOut_uid138_rrx_uid28_fpSinPiTest(BITSELECT,137)@12
expCompOut_uid138_rrx_uid28_fpSinPiTest_in <= expCompOutExt_uid137_rrx_uid28_fpSinPiTest_q(7 downto 0);
expCompOut_uid138_rrx_uid28_fpSinPiTest_b <= expCompOut_uid138_rrx_uid28_fpSinPiTest_in(7 downto 0);
--reg_expCompOut_uid138_rrx_uid28_fpSinPiTest_0_to_finalExp_uid142_rrx_uid28_fpSinPiTest_2(REG,374)@12
reg_expCompOut_uid138_rrx_uid28_fpSinPiTest_0_to_finalExp_uid142_rrx_uid28_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expCompOut_uid138_rrx_uid28_fpSinPiTest_0_to_finalExp_uid142_rrx_uid28_fpSinPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expCompOut_uid138_rrx_uid28_fpSinPiTest_0_to_finalExp_uid142_rrx_uid28_fpSinPiTest_2_q <= expCompOut_uid138_rrx_uid28_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--xBranch_uid124_rrx_uid28_fpSinPiTest(COMPARE,123)@0
xBranch_uid124_rrx_uid28_fpSinPiTest_cin <= GND_q;
xBranch_uid124_rrx_uid28_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid22_fpSinPiTest_q) & '0';
xBranch_uid124_rrx_uid28_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid119_rrx_uid28_fpSinPiTest_b) & xBranch_uid124_rrx_uid28_fpSinPiTest_cin(0);
xBranch_uid124_rrx_uid28_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xBranch_uid124_rrx_uid28_fpSinPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
xBranch_uid124_rrx_uid28_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xBranch_uid124_rrx_uid28_fpSinPiTest_a) - UNSIGNED(xBranch_uid124_rrx_uid28_fpSinPiTest_b));
END IF;
END IF;
END PROCESS;
xBranch_uid124_rrx_uid28_fpSinPiTest_n(0) <= not xBranch_uid124_rrx_uid28_fpSinPiTest_o(10);
--ld_xBranch_uid124_rrx_uid28_fpSinPiTest_n_to_finalExp_uid142_rrx_uid28_fpSinPiTest_b(DELAY,530)@1
ld_xBranch_uid124_rrx_uid28_fpSinPiTest_n_to_finalExp_uid142_rrx_uid28_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => xBranch_uid124_rrx_uid28_fpSinPiTest_n, xout => ld_xBranch_uid124_rrx_uid28_fpSinPiTest_n_to_finalExp_uid142_rrx_uid28_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalExp_uid142_rrx_uid28_fpSinPiTest(MUX,141)@13
finalExp_uid142_rrx_uid28_fpSinPiTest_s <= ld_xBranch_uid124_rrx_uid28_fpSinPiTest_n_to_finalExp_uid142_rrx_uid28_fpSinPiTest_b_q;
finalExp_uid142_rrx_uid28_fpSinPiTest: PROCESS (finalExp_uid142_rrx_uid28_fpSinPiTest_s, en, reg_expCompOut_uid138_rrx_uid28_fpSinPiTest_0_to_finalExp_uid142_rrx_uid28_fpSinPiTest_2_q, ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_q)
BEGIN
CASE finalExp_uid142_rrx_uid28_fpSinPiTest_s IS
WHEN "0" => finalExp_uid142_rrx_uid28_fpSinPiTest_q <= reg_expCompOut_uid138_rrx_uid28_fpSinPiTest_0_to_finalExp_uid142_rrx_uid28_fpSinPiTest_2_q;
WHEN "1" => finalExp_uid142_rrx_uid28_fpSinPiTest_q <= ld_expX_uid119_rrx_uid28_fpSinPiTest_b_to_finalExp_uid142_rrx_uid28_fpSinPiTest_d_replace_mem_q;
WHEN OTHERS => finalExp_uid142_rrx_uid28_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_finalExp_uid142_rrx_uid28_fpSinPiTest_q_to_RRangeRed_uid143_rrx_uid28_fpSinPiTest_b(DELAY,534)@13
ld_finalExp_uid142_rrx_uid28_fpSinPiTest_q_to_RRangeRed_uid143_rrx_uid28_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => finalExp_uid142_rrx_uid28_fpSinPiTest_q, xout => ld_finalExp_uid142_rrx_uid28_fpSinPiTest_q_to_RRangeRed_uid143_rrx_uid28_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_nor(LOGICAL,958)
ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_nor_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q;
ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_nor_b <= ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_sticky_ena_q;
ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_nor_q <= not (ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_nor_a or ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_nor_b);
--ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_mem_top(CONSTANT,815)
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_mem_top_q <= "0111";
--ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_cmp(LOGICAL,816)
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_cmp_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_mem_top_q;
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdmux_q);
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_cmp_q <= "1" when ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_cmp_a = ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_cmp_b else "0";
--ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_cmpReg(REG,817)
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_cmpReg_q <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_sticky_ena(REG,959)
ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_nor_q = "1") THEN
ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_sticky_ena_q <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_enaAnd(LOGICAL,960)
ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_enaAnd_a <= ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_sticky_ena_q;
ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_enaAnd_b <= en;
ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_enaAnd_q <= ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_enaAnd_a and ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_enaAnd_b;
--ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_inputreg(DELAY,948)
ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid120_rrx_uid28_fpSinPiTest_b, xout => ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdcnt(COUNTER,811)
-- every=1, low=0, high=7, step=1, init=1
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdcnt_i <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdcnt_i,3));
--ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdreg(REG,812)
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdreg_q <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdmux(MUX,813)
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdmux_s <= en;
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdmux: PROCESS (ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdmux_s, ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdreg_q, ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdmux_q <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdreg_q;
WHEN "1" => ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdmux_q <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem(DUALMEM,949)
ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_ia <= ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_inputreg_q;
ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_aa <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdreg_q;
ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_ab <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdmux_q;
ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 3,
numwords_a => 8,
width_b => 23,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_iq,
address_a => ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_aa,
data_a => ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_ia
);
ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_q <= ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_iq(22 downto 0);
--ZerosGB_uid139_rrx_uid28_fpSinPiTest(CONSTANT,138)
ZerosGB_uid139_rrx_uid28_fpSinPiTest_q <= "000000000000000000000000000000";
--fracXRExt_uid140_rrx_uid28_fpSinPiTest(BITJOIN,139)@14
fracXRExt_uid140_rrx_uid28_fpSinPiTest_q <= ld_fracX_uid120_rrx_uid28_fpSinPiTest_b_to_fracXRExt_uid140_rrx_uid28_fpSinPiTest_b_replace_mem_q & ZerosGB_uid139_rrx_uid28_fpSinPiTest_q;
--LeftShiftStage174dto0_uid322_normMult_uid135_rrx_uid28_fpSinPiTest(BITSELECT,321)@13
LeftShiftStage174dto0_uid322_normMult_uid135_rrx_uid28_fpSinPiTest_in <= leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_q(74 downto 0);
LeftShiftStage174dto0_uid322_normMult_uid135_rrx_uid28_fpSinPiTest_b <= LeftShiftStage174dto0_uid322_normMult_uid135_rrx_uid28_fpSinPiTest_in(74 downto 0);
--leftShiftStage2Idx1_uid323_normMult_uid135_rrx_uid28_fpSinPiTest(BITJOIN,322)@13
leftShiftStage2Idx1_uid323_normMult_uid135_rrx_uid28_fpSinPiTest_q <= LeftShiftStage174dto0_uid322_normMult_uid135_rrx_uid28_fpSinPiTest_b & GND_q;
--X51dto0_uid306_normMult_uid135_rrx_uid28_fpSinPiTest(BITSELECT,305)@9
X51dto0_uid306_normMult_uid135_rrx_uid28_fpSinPiTest_in <= multFracBits_uid132_rrx_uid28_fpSinPiTest_b(51 downto 0);
X51dto0_uid306_normMult_uid135_rrx_uid28_fpSinPiTest_b <= X51dto0_uid306_normMult_uid135_rrx_uid28_fpSinPiTest_in(51 downto 0);
--ld_X51dto0_uid306_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx3_uid307_normMult_uid135_rrx_uid28_fpSinPiTest_b_inputreg(DELAY,998)
ld_X51dto0_uid306_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx3_uid307_normMult_uid135_rrx_uid28_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 52, depth => 1 )
PORT MAP ( xin => X51dto0_uid306_normMult_uid135_rrx_uid28_fpSinPiTest_b, xout => ld_X51dto0_uid306_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx3_uid307_normMult_uid135_rrx_uid28_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X51dto0_uid306_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx3_uid307_normMult_uid135_rrx_uid28_fpSinPiTest_b(DELAY,691)@9
ld_X51dto0_uid306_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx3_uid307_normMult_uid135_rrx_uid28_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 52, depth => 2 )
PORT MAP ( xin => ld_X51dto0_uid306_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx3_uid307_normMult_uid135_rrx_uid28_fpSinPiTest_b_inputreg_q, xout => ld_X51dto0_uid306_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx3_uid307_normMult_uid135_rrx_uid28_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad24_uid226_alignedZ_uid51_fpSinPiTest(CONSTANT,225)
leftShiftStage1Idx3Pad24_uid226_alignedZ_uid51_fpSinPiTest_q <= "000000000000000000000000";
--leftShiftStage0Idx3_uid307_normMult_uid135_rrx_uid28_fpSinPiTest(BITJOIN,306)@12
leftShiftStage0Idx3_uid307_normMult_uid135_rrx_uid28_fpSinPiTest_q <= ld_X51dto0_uid306_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx3_uid307_normMult_uid135_rrx_uid28_fpSinPiTest_b_q & leftShiftStage1Idx3Pad24_uid226_alignedZ_uid51_fpSinPiTest_q;
--X59dto0_uid303_normMult_uid135_rrx_uid28_fpSinPiTest(BITSELECT,302)@9
X59dto0_uid303_normMult_uid135_rrx_uid28_fpSinPiTest_in <= multFracBits_uid132_rrx_uid28_fpSinPiTest_b(59 downto 0);
X59dto0_uid303_normMult_uid135_rrx_uid28_fpSinPiTest_b <= X59dto0_uid303_normMult_uid135_rrx_uid28_fpSinPiTest_in(59 downto 0);
--ld_X59dto0_uid303_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx2_uid304_normMult_uid135_rrx_uid28_fpSinPiTest_b_inputreg(DELAY,997)
ld_X59dto0_uid303_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx2_uid304_normMult_uid135_rrx_uid28_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 60, depth => 1 )
PORT MAP ( xin => X59dto0_uid303_normMult_uid135_rrx_uid28_fpSinPiTest_b, xout => ld_X59dto0_uid303_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx2_uid304_normMult_uid135_rrx_uid28_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X59dto0_uid303_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx2_uid304_normMult_uid135_rrx_uid28_fpSinPiTest_b(DELAY,689)@9
ld_X59dto0_uid303_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx2_uid304_normMult_uid135_rrx_uid28_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 60, depth => 2 )
PORT MAP ( xin => ld_X59dto0_uid303_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx2_uid304_normMult_uid135_rrx_uid28_fpSinPiTest_b_inputreg_q, xout => ld_X59dto0_uid303_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx2_uid304_normMult_uid135_rrx_uid28_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx2_uid304_normMult_uid135_rrx_uid28_fpSinPiTest(BITJOIN,303)@12
leftShiftStage0Idx2_uid304_normMult_uid135_rrx_uid28_fpSinPiTest_q <= ld_X59dto0_uid303_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx2_uid304_normMult_uid135_rrx_uid28_fpSinPiTest_b_q & zs_uid183_lzcZ_uid50_fpSinPiTest_q;
--X67dto0_uid300_normMult_uid135_rrx_uid28_fpSinPiTest(BITSELECT,299)@9
X67dto0_uid300_normMult_uid135_rrx_uid28_fpSinPiTest_in <= multFracBits_uid132_rrx_uid28_fpSinPiTest_b(67 downto 0);
X67dto0_uid300_normMult_uid135_rrx_uid28_fpSinPiTest_b <= X67dto0_uid300_normMult_uid135_rrx_uid28_fpSinPiTest_in(67 downto 0);
--ld_X67dto0_uid300_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx1_uid301_normMult_uid135_rrx_uid28_fpSinPiTest_b_inputreg(DELAY,996)
ld_X67dto0_uid300_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx1_uid301_normMult_uid135_rrx_uid28_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 68, depth => 1 )
PORT MAP ( xin => X67dto0_uid300_normMult_uid135_rrx_uid28_fpSinPiTest_b, xout => ld_X67dto0_uid300_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx1_uid301_normMult_uid135_rrx_uid28_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X67dto0_uid300_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx1_uid301_normMult_uid135_rrx_uid28_fpSinPiTest_b(DELAY,687)@9
ld_X67dto0_uid300_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx1_uid301_normMult_uid135_rrx_uid28_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 68, depth => 2 )
PORT MAP ( xin => ld_X67dto0_uid300_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx1_uid301_normMult_uid135_rrx_uid28_fpSinPiTest_b_inputreg_q, xout => ld_X67dto0_uid300_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx1_uid301_normMult_uid135_rrx_uid28_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1_uid301_normMult_uid135_rrx_uid28_fpSinPiTest(BITJOIN,300)@12
leftShiftStage0Idx1_uid301_normMult_uid135_rrx_uid28_fpSinPiTest_q <= ld_X67dto0_uid300_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0Idx1_uid301_normMult_uid135_rrx_uid28_fpSinPiTest_b_q & cstAllZWE_uid8_fpSinPiTest_q;
--ld_multFracBits_uid132_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_c_inputreg(DELAY,999)
ld_multFracBits_uid132_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 76, depth => 1 )
PORT MAP ( xin => multFracBits_uid132_rrx_uid28_fpSinPiTest_b, xout => ld_multFracBits_uid132_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_multFracBits_uid132_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_c(DELAY,694)@9
ld_multFracBits_uid132_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 76, depth => 2 )
PORT MAP ( xin => ld_multFracBits_uid132_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_c_inputreg_q, xout => ld_multFracBits_uid132_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStageSel4Dto3_uid308_normMult_uid135_rrx_uid28_fpSinPiTest(BITSELECT,307)@12
leftShiftStageSel4Dto3_uid308_normMult_uid135_rrx_uid28_fpSinPiTest_in <= r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_q;
leftShiftStageSel4Dto3_uid308_normMult_uid135_rrx_uid28_fpSinPiTest_b <= leftShiftStageSel4Dto3_uid308_normMult_uid135_rrx_uid28_fpSinPiTest_in(4 downto 3);
--leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest(MUX,308)@12
leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_s <= leftShiftStageSel4Dto3_uid308_normMult_uid135_rrx_uid28_fpSinPiTest_b;
leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest: PROCESS (leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_s, en, ld_multFracBits_uid132_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_c_q, leftShiftStage0Idx1_uid301_normMult_uid135_rrx_uid28_fpSinPiTest_q, leftShiftStage0Idx2_uid304_normMult_uid135_rrx_uid28_fpSinPiTest_q, leftShiftStage0Idx3_uid307_normMult_uid135_rrx_uid28_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_q <= ld_multFracBits_uid132_rrx_uid28_fpSinPiTest_b_to_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_c_q;
WHEN "01" => leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_q <= leftShiftStage0Idx1_uid301_normMult_uid135_rrx_uid28_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_q <= leftShiftStage0Idx2_uid304_normMult_uid135_rrx_uid28_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_q <= leftShiftStage0Idx3_uid307_normMult_uid135_rrx_uid28_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage069dto0_uid317_normMult_uid135_rrx_uid28_fpSinPiTest(BITSELECT,316)@12
LeftShiftStage069dto0_uid317_normMult_uid135_rrx_uid28_fpSinPiTest_in <= leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_q(69 downto 0);
LeftShiftStage069dto0_uid317_normMult_uid135_rrx_uid28_fpSinPiTest_b <= LeftShiftStage069dto0_uid317_normMult_uid135_rrx_uid28_fpSinPiTest_in(69 downto 0);
--leftShiftStage2Idx3Pad6_uid237_alignedZ_uid51_fpSinPiTest(CONSTANT,236)
leftShiftStage2Idx3Pad6_uid237_alignedZ_uid51_fpSinPiTest_q <= "000000";
--leftShiftStage1Idx3_uid318_normMult_uid135_rrx_uid28_fpSinPiTest(BITJOIN,317)@12
leftShiftStage1Idx3_uid318_normMult_uid135_rrx_uid28_fpSinPiTest_q <= LeftShiftStage069dto0_uid317_normMult_uid135_rrx_uid28_fpSinPiTest_b & leftShiftStage2Idx3Pad6_uid237_alignedZ_uid51_fpSinPiTest_q;
--reg_leftShiftStage1Idx3_uid318_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_5(REG,372)@12
reg_leftShiftStage1Idx3_uid318_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid318_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_5_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid318_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_5_q <= leftShiftStage1Idx3_uid318_normMult_uid135_rrx_uid28_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage071dto0_uid314_normMult_uid135_rrx_uid28_fpSinPiTest(BITSELECT,313)@12
LeftShiftStage071dto0_uid314_normMult_uid135_rrx_uid28_fpSinPiTest_in <= leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_q(71 downto 0);
LeftShiftStage071dto0_uid314_normMult_uid135_rrx_uid28_fpSinPiTest_b <= LeftShiftStage071dto0_uid314_normMult_uid135_rrx_uid28_fpSinPiTest_in(71 downto 0);
--leftShiftStage1Idx2_uid315_normMult_uid135_rrx_uid28_fpSinPiTest(BITJOIN,314)@12
leftShiftStage1Idx2_uid315_normMult_uid135_rrx_uid28_fpSinPiTest_q <= LeftShiftStage071dto0_uid314_normMult_uid135_rrx_uid28_fpSinPiTest_b & leftShiftStage0Idx1Pad4_uid146_fxpX_uid40_fpSinPiTest_q;
--reg_leftShiftStage1Idx2_uid315_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_4(REG,371)@12
reg_leftShiftStage1Idx2_uid315_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid315_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_4_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid315_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_4_q <= leftShiftStage1Idx2_uid315_normMult_uid135_rrx_uid28_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage073dto0_uid311_normMult_uid135_rrx_uid28_fpSinPiTest(BITSELECT,310)@12
LeftShiftStage073dto0_uid311_normMult_uid135_rrx_uid28_fpSinPiTest_in <= leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_q(73 downto 0);
LeftShiftStage073dto0_uid311_normMult_uid135_rrx_uid28_fpSinPiTest_b <= LeftShiftStage073dto0_uid311_normMult_uid135_rrx_uid28_fpSinPiTest_in(73 downto 0);
--leftShiftStage1Idx1_uid312_normMult_uid135_rrx_uid28_fpSinPiTest(BITJOIN,311)@12
leftShiftStage1Idx1_uid312_normMult_uid135_rrx_uid28_fpSinPiTest_q <= LeftShiftStage073dto0_uid311_normMult_uid135_rrx_uid28_fpSinPiTest_b & leftShiftStage1Idx2Pad2_uid160_fxpX_uid40_fpSinPiTest_q;
--reg_leftShiftStage1Idx1_uid312_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_3(REG,370)@12
reg_leftShiftStage1Idx1_uid312_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid312_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_3_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid312_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_3_q <= leftShiftStage1Idx1_uid312_normMult_uid135_rrx_uid28_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_2(REG,369)@12
reg_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_2_q <= leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid319_normMult_uid135_rrx_uid28_fpSinPiTest(BITSELECT,318)@12
leftShiftStageSel2Dto1_uid319_normMult_uid135_rrx_uid28_fpSinPiTest_in <= r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid319_normMult_uid135_rrx_uid28_fpSinPiTest_b <= leftShiftStageSel2Dto1_uid319_normMult_uid135_rrx_uid28_fpSinPiTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid319_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_1(REG,368)@12
reg_leftShiftStageSel2Dto1_uid319_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid319_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid319_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_1_q <= leftShiftStageSel2Dto1_uid319_normMult_uid135_rrx_uid28_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest(MUX,319)@13
leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_s <= reg_leftShiftStageSel2Dto1_uid319_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_1_q;
leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest: PROCESS (leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_s, en, reg_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_2_q, reg_leftShiftStage1Idx1_uid312_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_3_q, reg_leftShiftStage1Idx2_uid315_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_4_q, reg_leftShiftStage1Idx3_uid318_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_q <= reg_leftShiftStage0_uid309_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_q <= reg_leftShiftStage1Idx1_uid312_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_3_q;
WHEN "10" => leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_q <= reg_leftShiftStage1Idx2_uid315_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_4_q;
WHEN "11" => leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_q <= reg_leftShiftStage1Idx3_uid318_normMult_uid135_rrx_uid28_fpSinPiTest_0_to_leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid324_normMult_uid135_rrx_uid28_fpSinPiTest(BITSELECT,323)@12
leftShiftStageSel0Dto0_uid324_normMult_uid135_rrx_uid28_fpSinPiTest_in <= r_uid296_zCount_uid134_rrx_uid28_fpSinPiTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid324_normMult_uid135_rrx_uid28_fpSinPiTest_b <= leftShiftStageSel0Dto0_uid324_normMult_uid135_rrx_uid28_fpSinPiTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid324_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage2_uid325_normMult_uid135_rrx_uid28_fpSinPiTest_b(DELAY,713)@12
ld_leftShiftStageSel0Dto0_uid324_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage2_uid325_normMult_uid135_rrx_uid28_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid324_normMult_uid135_rrx_uid28_fpSinPiTest_b, xout => ld_leftShiftStageSel0Dto0_uid324_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage2_uid325_normMult_uid135_rrx_uid28_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid325_normMult_uid135_rrx_uid28_fpSinPiTest(MUX,324)@13
leftShiftStage2_uid325_normMult_uid135_rrx_uid28_fpSinPiTest_s <= ld_leftShiftStageSel0Dto0_uid324_normMult_uid135_rrx_uid28_fpSinPiTest_b_to_leftShiftStage2_uid325_normMult_uid135_rrx_uid28_fpSinPiTest_b_q;
leftShiftStage2_uid325_normMult_uid135_rrx_uid28_fpSinPiTest: PROCESS (leftShiftStage2_uid325_normMult_uid135_rrx_uid28_fpSinPiTest_s, en, leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_q, leftShiftStage2Idx1_uid323_normMult_uid135_rrx_uid28_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid325_normMult_uid135_rrx_uid28_fpSinPiTest_s IS
WHEN "0" => leftShiftStage2_uid325_normMult_uid135_rrx_uid28_fpSinPiTest_q <= leftShiftStage1_uid320_normMult_uid135_rrx_uid28_fpSinPiTest_q;
WHEN "1" => leftShiftStage2_uid325_normMult_uid135_rrx_uid28_fpSinPiTest_q <= leftShiftStage2Idx1_uid323_normMult_uid135_rrx_uid28_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid325_normMult_uid135_rrx_uid28_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracCompOut_uid136_rrx_uid28_fpSinPiTest(BITSELECT,135)@13
fracCompOut_uid136_rrx_uid28_fpSinPiTest_in <= leftShiftStage2_uid325_normMult_uid135_rrx_uid28_fpSinPiTest_q(74 downto 0);
fracCompOut_uid136_rrx_uid28_fpSinPiTest_b <= fracCompOut_uid136_rrx_uid28_fpSinPiTest_in(74 downto 22);
--reg_fracCompOut_uid136_rrx_uid28_fpSinPiTest_0_to_finalFrac_uid141_rrx_uid28_fpSinPiTest_2(REG,373)@13
reg_fracCompOut_uid136_rrx_uid28_fpSinPiTest_0_to_finalFrac_uid141_rrx_uid28_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracCompOut_uid136_rrx_uid28_fpSinPiTest_0_to_finalFrac_uid141_rrx_uid28_fpSinPiTest_2_q <= "00000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracCompOut_uid136_rrx_uid28_fpSinPiTest_0_to_finalFrac_uid141_rrx_uid28_fpSinPiTest_2_q <= fracCompOut_uid136_rrx_uid28_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_xBranch_uid124_rrx_uid28_fpSinPiTest_n_to_finalFrac_uid141_rrx_uid28_fpSinPiTest_b(DELAY,527)@1
ld_xBranch_uid124_rrx_uid28_fpSinPiTest_n_to_finalFrac_uid141_rrx_uid28_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => xBranch_uid124_rrx_uid28_fpSinPiTest_n, xout => ld_xBranch_uid124_rrx_uid28_fpSinPiTest_n_to_finalFrac_uid141_rrx_uid28_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalFrac_uid141_rrx_uid28_fpSinPiTest(MUX,140)@14
finalFrac_uid141_rrx_uid28_fpSinPiTest_s <= ld_xBranch_uid124_rrx_uid28_fpSinPiTest_n_to_finalFrac_uid141_rrx_uid28_fpSinPiTest_b_q;
finalFrac_uid141_rrx_uid28_fpSinPiTest: PROCESS (finalFrac_uid141_rrx_uid28_fpSinPiTest_s, en, reg_fracCompOut_uid136_rrx_uid28_fpSinPiTest_0_to_finalFrac_uid141_rrx_uid28_fpSinPiTest_2_q, fracXRExt_uid140_rrx_uid28_fpSinPiTest_q)
BEGIN
CASE finalFrac_uid141_rrx_uid28_fpSinPiTest_s IS
WHEN "0" => finalFrac_uid141_rrx_uid28_fpSinPiTest_q <= reg_fracCompOut_uid136_rrx_uid28_fpSinPiTest_0_to_finalFrac_uid141_rrx_uid28_fpSinPiTest_2_q;
WHEN "1" => finalFrac_uid141_rrx_uid28_fpSinPiTest_q <= fracXRExt_uid140_rrx_uid28_fpSinPiTest_q;
WHEN OTHERS => finalFrac_uid141_rrx_uid28_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--RRangeRed_uid143_rrx_uid28_fpSinPiTest(BITJOIN,142)@14
RRangeRed_uid143_rrx_uid28_fpSinPiTest_q <= GND_q & ld_finalExp_uid142_rrx_uid28_fpSinPiTest_q_to_RRangeRed_uid143_rrx_uid28_fpSinPiTest_b_q & finalFrac_uid141_rrx_uid28_fpSinPiTest_q;
--fracXRR_uid33_fpSinPiTest(BITSELECT,32)@14
fracXRR_uid33_fpSinPiTest_in <= RRangeRed_uid143_rrx_uid28_fpSinPiTest_q(52 downto 0);
fracXRR_uid33_fpSinPiTest_b <= fracXRR_uid33_fpSinPiTest_in(52 downto 0);
--ld_fracXRR_uid33_fpSinPiTest_b_to_oFracXRR_uid36_uid36_fpSinPiTest_a(DELAY,436)@14
ld_fracXRR_uid33_fpSinPiTest_b_to_oFracXRR_uid36_uid36_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => fracXRR_uid33_fpSinPiTest_b, xout => ld_fracXRR_uid33_fpSinPiTest_b_to_oFracXRR_uid36_uid36_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracXRR_uid36_uid36_fpSinPiTest(BITJOIN,35)@15
oFracXRR_uid36_uid36_fpSinPiTest_q <= VCC_q & ld_fracXRR_uid33_fpSinPiTest_b_to_oFracXRR_uid36_uid36_fpSinPiTest_a_q;
--extendedFracX_uid39_fpSinPiTest(BITJOIN,38)@15
extendedFracX_uid39_fpSinPiTest_q <= cstZwShiftP1_uid25_fpSinPiTest_q & oFracXRR_uid36_uid36_fpSinPiTest_q;
--cstBiasMwShiftM2_uid24_fpSinPiTest(CONSTANT,23)
cstBiasMwShiftM2_uid24_fpSinPiTest_q <= "01110000";
--expXRR_uid32_fpSinPiTest(BITSELECT,31)@14
expXRR_uid32_fpSinPiTest_in <= RRangeRed_uid143_rrx_uid28_fpSinPiTest_q(60 downto 0);
expXRR_uid32_fpSinPiTest_b <= expXRR_uid32_fpSinPiTest_in(60 downto 53);
--fxpXShiftValExt_uid37_fpSinPiTest(SUB,36)@14
fxpXShiftValExt_uid37_fpSinPiTest_a <= STD_LOGIC_VECTOR((10 downto 8 => expXRR_uid32_fpSinPiTest_b(7)) & expXRR_uid32_fpSinPiTest_b);
fxpXShiftValExt_uid37_fpSinPiTest_b <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid24_fpSinPiTest_q);
fxpXShiftValExt_uid37_fpSinPiTest_o <= STD_LOGIC_VECTOR(SIGNED(fxpXShiftValExt_uid37_fpSinPiTest_a) - SIGNED(fxpXShiftValExt_uid37_fpSinPiTest_b));
fxpXShiftValExt_uid37_fpSinPiTest_q <= fxpXShiftValExt_uid37_fpSinPiTest_o(9 downto 0);
--fxpXShiftVal_uid38_fpSinPiTest(BITSELECT,37)@14
fxpXShiftVal_uid38_fpSinPiTest_in <= fxpXShiftValExt_uid37_fpSinPiTest_q(3 downto 0);
fxpXShiftVal_uid38_fpSinPiTest_b <= fxpXShiftVal_uid38_fpSinPiTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid155_fxpX_uid40_fpSinPiTest(BITSELECT,154)@14
leftShiftStageSel3Dto2_uid155_fxpX_uid40_fpSinPiTest_in <= fxpXShiftVal_uid38_fpSinPiTest_b;
leftShiftStageSel3Dto2_uid155_fxpX_uid40_fpSinPiTest_b <= leftShiftStageSel3Dto2_uid155_fxpX_uid40_fpSinPiTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid155_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_1(REG,375)@14
reg_leftShiftStageSel3Dto2_uid155_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid155_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid155_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_1_q <= leftShiftStageSel3Dto2_uid155_fxpX_uid40_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest(MUX,155)@15
leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_s <= reg_leftShiftStageSel3Dto2_uid155_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_1_q;
leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest: PROCESS (leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_s, en, extendedFracX_uid39_fpSinPiTest_q, leftShiftStage0Idx1_uid148_fxpX_uid40_fpSinPiTest_q, leftShiftStage0Idx2_uid151_fxpX_uid40_fpSinPiTest_q, leftShiftStage0Idx3_uid154_fxpX_uid40_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_q <= extendedFracX_uid39_fpSinPiTest_q;
WHEN "01" => leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_q <= leftShiftStage0Idx1_uid148_fxpX_uid40_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_q <= leftShiftStage0Idx2_uid151_fxpX_uid40_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_q <= leftShiftStage0Idx3_uid154_fxpX_uid40_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage064dto0_uid164_fxpX_uid40_fpSinPiTest(BITSELECT,163)@15
LeftShiftStage064dto0_uid164_fxpX_uid40_fpSinPiTest_in <= leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_q(64 downto 0);
LeftShiftStage064dto0_uid164_fxpX_uid40_fpSinPiTest_b <= LeftShiftStage064dto0_uid164_fxpX_uid40_fpSinPiTest_in(64 downto 0);
--ld_LeftShiftStage064dto0_uid164_fxpX_uid40_fpSinPiTest_b_to_leftShiftStage1Idx3_uid165_fxpX_uid40_fpSinPiTest_b(DELAY,552)@15
ld_LeftShiftStage064dto0_uid164_fxpX_uid40_fpSinPiTest_b_to_leftShiftStage1Idx3_uid165_fxpX_uid40_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => LeftShiftStage064dto0_uid164_fxpX_uid40_fpSinPiTest_b, xout => ld_LeftShiftStage064dto0_uid164_fxpX_uid40_fpSinPiTest_b_to_leftShiftStage1Idx3_uid165_fxpX_uid40_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid163_fxpX_uid40_fpSinPiTest(CONSTANT,162)
leftShiftStage1Idx3Pad3_uid163_fxpX_uid40_fpSinPiTest_q <= "000";
--leftShiftStage1Idx3_uid165_fxpX_uid40_fpSinPiTest(BITJOIN,164)@16
leftShiftStage1Idx3_uid165_fxpX_uid40_fpSinPiTest_q <= ld_LeftShiftStage064dto0_uid164_fxpX_uid40_fpSinPiTest_b_to_leftShiftStage1Idx3_uid165_fxpX_uid40_fpSinPiTest_b_q & leftShiftStage1Idx3Pad3_uid163_fxpX_uid40_fpSinPiTest_q;
--LeftShiftStage065dto0_uid161_fxpX_uid40_fpSinPiTest(BITSELECT,160)@15
LeftShiftStage065dto0_uid161_fxpX_uid40_fpSinPiTest_in <= leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_q(65 downto 0);
LeftShiftStage065dto0_uid161_fxpX_uid40_fpSinPiTest_b <= LeftShiftStage065dto0_uid161_fxpX_uid40_fpSinPiTest_in(65 downto 0);
--ld_LeftShiftStage065dto0_uid161_fxpX_uid40_fpSinPiTest_b_to_leftShiftStage1Idx2_uid162_fxpX_uid40_fpSinPiTest_b(DELAY,550)@15
ld_LeftShiftStage065dto0_uid161_fxpX_uid40_fpSinPiTest_b_to_leftShiftStage1Idx2_uid162_fxpX_uid40_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 66, depth => 1 )
PORT MAP ( xin => LeftShiftStage065dto0_uid161_fxpX_uid40_fpSinPiTest_b, xout => ld_LeftShiftStage065dto0_uid161_fxpX_uid40_fpSinPiTest_b_to_leftShiftStage1Idx2_uid162_fxpX_uid40_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid162_fxpX_uid40_fpSinPiTest(BITJOIN,161)@16
leftShiftStage1Idx2_uid162_fxpX_uid40_fpSinPiTest_q <= ld_LeftShiftStage065dto0_uid161_fxpX_uid40_fpSinPiTest_b_to_leftShiftStage1Idx2_uid162_fxpX_uid40_fpSinPiTest_b_q & leftShiftStage1Idx2Pad2_uid160_fxpX_uid40_fpSinPiTest_q;
--LeftShiftStage066dto0_uid158_fxpX_uid40_fpSinPiTest(BITSELECT,157)@15
LeftShiftStage066dto0_uid158_fxpX_uid40_fpSinPiTest_in <= leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_q(66 downto 0);
LeftShiftStage066dto0_uid158_fxpX_uid40_fpSinPiTest_b <= LeftShiftStage066dto0_uid158_fxpX_uid40_fpSinPiTest_in(66 downto 0);
--ld_LeftShiftStage066dto0_uid158_fxpX_uid40_fpSinPiTest_b_to_leftShiftStage1Idx1_uid159_fxpX_uid40_fpSinPiTest_b(DELAY,548)@15
ld_LeftShiftStage066dto0_uid158_fxpX_uid40_fpSinPiTest_b_to_leftShiftStage1Idx1_uid159_fxpX_uid40_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 67, depth => 1 )
PORT MAP ( xin => LeftShiftStage066dto0_uid158_fxpX_uid40_fpSinPiTest_b, xout => ld_LeftShiftStage066dto0_uid158_fxpX_uid40_fpSinPiTest_b_to_leftShiftStage1Idx1_uid159_fxpX_uid40_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid159_fxpX_uid40_fpSinPiTest(BITJOIN,158)@16
leftShiftStage1Idx1_uid159_fxpX_uid40_fpSinPiTest_q <= ld_LeftShiftStage066dto0_uid158_fxpX_uid40_fpSinPiTest_b_to_leftShiftStage1Idx1_uid159_fxpX_uid40_fpSinPiTest_b_q & GND_q;
--reg_leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_2(REG,377)@15
reg_leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_2_q <= leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest(BITSELECT,165)@14
leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest_in <= fxpXShiftVal_uid38_fpSinPiTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest_b <= leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest_in(1 downto 0);
--reg_leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_1(REG,376)@14
reg_leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_1_q <= leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_1_q_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_b(DELAY,554)@15
ld_reg_leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_1_q_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_1_q, xout => ld_reg_leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_1_q_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest(MUX,166)@16
leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_s <= ld_reg_leftShiftStageSel1Dto0_uid166_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_1_q_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_b_q;
leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest: PROCESS (leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_s, en, reg_leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_2_q, leftShiftStage1Idx1_uid159_fxpX_uid40_fpSinPiTest_q, leftShiftStage1Idx2_uid162_fxpX_uid40_fpSinPiTest_q, leftShiftStage1Idx3_uid165_fxpX_uid40_fpSinPiTest_q)
BEGIN
CASE leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_q <= reg_leftShiftStage0_uid156_fxpX_uid40_fpSinPiTest_0_to_leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_q <= leftShiftStage1Idx1_uid159_fxpX_uid40_fpSinPiTest_q;
WHEN "10" => leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_q <= leftShiftStage1Idx2_uid162_fxpX_uid40_fpSinPiTest_q;
WHEN "11" => leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_q <= leftShiftStage1Idx3_uid165_fxpX_uid40_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--intXParity_uid41_fpSinPiTest(BITSELECT,40)@16
intXParity_uid41_fpSinPiTest_in <= leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_q;
intXParity_uid41_fpSinPiTest_b <= intXParity_uid41_fpSinPiTest_in(67 downto 67);
--exp_uid9_fpSinPiTest(BITSELECT,8)@0
exp_uid9_fpSinPiTest_in <= a(30 downto 0);
exp_uid9_fpSinPiTest_b <= exp_uid9_fpSinPiTest_in(30 downto 23);
--sinXIsX_uid34_fpSinPiTest(COMPARE,33)@0
sinXIsX_uid34_fpSinPiTest_cin <= GND_q;
sinXIsX_uid34_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid22_fpSinPiTest_q) & '0';
sinXIsX_uid34_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & exp_uid9_fpSinPiTest_b) & sinXIsX_uid34_fpSinPiTest_cin(0);
sinXIsX_uid34_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid34_fpSinPiTest_a) - UNSIGNED(sinXIsX_uid34_fpSinPiTest_b));
sinXIsX_uid34_fpSinPiTest_n(0) <= not sinXIsX_uid34_fpSinPiTest_o(10);
--ld_sinXIsX_uid34_fpSinPiTest_n_to_InvSinXIsX_uid93_fpSinPiTest_a(DELAY,501)@0
ld_sinXIsX_uid34_fpSinPiTest_n_to_InvSinXIsX_uid93_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_n, xout => ld_sinXIsX_uid34_fpSinPiTest_n_to_InvSinXIsX_uid93_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsX_uid93_fpSinPiTest(LOGICAL,92)@16
InvSinXIsX_uid93_fpSinPiTest_a <= ld_sinXIsX_uid34_fpSinPiTest_n_to_InvSinXIsX_uid93_fpSinPiTest_a_q;
InvSinXIsX_uid93_fpSinPiTest_q <= not InvSinXIsX_uid93_fpSinPiTest_a;
--cstBiasMwShiftM2_uid23_fpSinPiTest(CONSTANT,22)
cstBiasMwShiftM2_uid23_fpSinPiTest_q <= "01110001";
--sinXIsXRR_uid35_fpSinPiTest(COMPARE,34)@14
sinXIsXRR_uid35_fpSinPiTest_cin <= GND_q;
sinXIsXRR_uid35_fpSinPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid23_fpSinPiTest_q) & '0';
sinXIsXRR_uid35_fpSinPiTest_b <= STD_LOGIC_VECTOR((10 downto 8 => expXRR_uid32_fpSinPiTest_b(7)) & expXRR_uid32_fpSinPiTest_b) & sinXIsXRR_uid35_fpSinPiTest_cin(0);
sinXIsXRR_uid35_fpSinPiTest_o <= STD_LOGIC_VECTOR(SIGNED(sinXIsXRR_uid35_fpSinPiTest_a) - SIGNED(sinXIsXRR_uid35_fpSinPiTest_b));
sinXIsXRR_uid35_fpSinPiTest_n(0) <= not sinXIsXRR_uid35_fpSinPiTest_o(11);
--ld_sinXIsXRR_uid35_fpSinPiTest_n_to_InvSinXIsXRR_uid94_fpSinPiTest_a(DELAY,502)@14
ld_sinXIsXRR_uid35_fpSinPiTest_n_to_InvSinXIsXRR_uid94_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => sinXIsXRR_uid35_fpSinPiTest_n, xout => ld_sinXIsXRR_uid35_fpSinPiTest_n_to_InvSinXIsXRR_uid94_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsXRR_uid94_fpSinPiTest(LOGICAL,93)@15
InvSinXIsXRR_uid94_fpSinPiTest_a <= ld_sinXIsXRR_uid35_fpSinPiTest_n_to_InvSinXIsXRR_uid94_fpSinPiTest_a_q;
InvSinXIsXRR_uid94_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvSinXIsXRR_uid94_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
InvSinXIsXRR_uid94_fpSinPiTest_q <= not InvSinXIsXRR_uid94_fpSinPiTest_a;
END IF;
END PROCESS;
--signComp_uid95_fpSinPiTest(LOGICAL,94)@16
signComp_uid95_fpSinPiTest_a <= InvSinXIsXRR_uid94_fpSinPiTest_q;
signComp_uid95_fpSinPiTest_b <= InvSinXIsX_uid93_fpSinPiTest_q;
signComp_uid95_fpSinPiTest_c <= intXParity_uid41_fpSinPiTest_b;
signComp_uid95_fpSinPiTest_q <= signComp_uid95_fpSinPiTest_a and signComp_uid95_fpSinPiTest_b and signComp_uid95_fpSinPiTest_c;
--signX_uid31_fpSinPiTest(BITSELECT,30)@0
signX_uid31_fpSinPiTest_in <= a;
signX_uid31_fpSinPiTest_b <= signX_uid31_fpSinPiTest_in(31 downto 31);
--ld_signX_uid31_fpSinPiTest_b_to_signR_uid96_fpSinPiTest_a(DELAY,506)@0
ld_signX_uid31_fpSinPiTest_b_to_signR_uid96_fpSinPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signX_uid31_fpSinPiTest_b, xout => ld_signX_uid31_fpSinPiTest_b_to_signR_uid96_fpSinPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid96_fpSinPiTest(LOGICAL,95)@16
signR_uid96_fpSinPiTest_a <= ld_signX_uid31_fpSinPiTest_b_to_signR_uid96_fpSinPiTest_a_q;
signR_uid96_fpSinPiTest_b <= signComp_uid95_fpSinPiTest_q;
signR_uid96_fpSinPiTest_q <= signR_uid96_fpSinPiTest_a xor signR_uid96_fpSinPiTest_b;
--ld_signR_uid96_fpSinPiTest_q_to_sinXR_uid97_fpSinPiTest_c(DELAY,510)@16
ld_signR_uid96_fpSinPiTest_q_to_sinXR_uid97_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 20 )
PORT MAP ( xin => signR_uid96_fpSinPiTest_q, xout => ld_signR_uid96_fpSinPiTest_q_to_sinXR_uid97_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstAllOWE_uid6_fpSinPiTest(CONSTANT,5)
cstAllOWE_uid6_fpSinPiTest_q <= "11111111";
--ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_nor(LOGICAL,934)
ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_nor_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q;
ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_nor_b <= ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_sticky_ena_q;
ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_nor_q <= not (ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_nor_a or ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_nor_b);
--ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_mem_top(CONSTANT,917)
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_mem_top_q <= "0100001";
--ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_cmp(LOGICAL,918)
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_cmp_a <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_mem_top_q;
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdmux_q);
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_cmp_q <= "1" when ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_cmp_a = ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_cmp_b else "0";
--ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_cmpReg(REG,919)
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_cmpReg_q <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_sticky_ena(REG,935)
ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_nor_q = "1") THEN
ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_sticky_ena_q <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_enaAnd(LOGICAL,936)
ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_enaAnd_a <= ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_sticky_ena_q;
ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_enaAnd_b <= en;
ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_enaAnd_q <= ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_enaAnd_a and ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_enaAnd_b;
--ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_inputreg(DELAY,924)
ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => exp_uid9_fpSinPiTest_b, xout => ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt(COUNTER,913)
-- every=1, low=0, high=33, step=1, init=1
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_i = 32 THEN
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_eq = '1') THEN
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_i <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_i - 33;
ELSE
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_i <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_i,6));
--ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdreg(REG,914)
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdreg_q <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdmux(MUX,915)
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdmux_s <= en;
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdmux: PROCESS (ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdmux_s, ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdreg_q, ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdmux_q <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdreg_q;
WHEN "1" => ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdmux_q <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem(DUALMEM,925)
ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_ia <= ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_inputreg_q;
ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_aa <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdreg_q;
ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_ab <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdmux_q;
ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 34,
width_b => 8,
widthad_b => 6,
numwords_b => 34,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_iq,
address_a => ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_aa,
data_a => ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_ia
);
ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_reset0 <= areset;
ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_q <= ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_iq(7 downto 0);
--ld_sinXIsXRR_uid35_fpSinPiTest_n_to_reg_sinXIsXRR_uid35_fpSinPiTest_2_to_join_uid73_fpSinPiTest_1_a(DELAY,804)@14
ld_sinXIsXRR_uid35_fpSinPiTest_n_to_reg_sinXIsXRR_uid35_fpSinPiTest_2_to_join_uid73_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => sinXIsXRR_uid35_fpSinPiTest_n, xout => ld_sinXIsXRR_uid35_fpSinPiTest_n_to_reg_sinXIsXRR_uid35_fpSinPiTest_2_to_join_uid73_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sinXIsXRR_uid35_fpSinPiTest_2_to_join_uid73_fpSinPiTest_1(REG,409)@33
reg_sinXIsXRR_uid35_fpSinPiTest_2_to_join_uid73_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid35_fpSinPiTest_2_to_join_uid73_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid35_fpSinPiTest_2_to_join_uid73_fpSinPiTest_1_q <= ld_sinXIsXRR_uid35_fpSinPiTest_n_to_reg_sinXIsXRR_uid35_fpSinPiTest_2_to_join_uid73_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_nor(LOGICAL,832)
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_nor_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q;
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_nor_b <= ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_sticky_ena_q;
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_nor_q <= not (ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_nor_a or ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_nor_b);
--ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_mem_top(CONSTANT,828)
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_mem_top_q <= "01100";
--ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_cmp(LOGICAL,829)
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_cmp_a <= ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_mem_top_q;
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdmux_q);
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_cmp_q <= "1" when ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_cmp_a = ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_cmp_b else "0";
--ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_cmpReg(REG,830)
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_cmpReg_q <= ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_sticky_ena(REG,833)
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_nor_q = "1") THEN
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_sticky_ena_q <= ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_enaAnd(LOGICAL,834)
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_enaAnd_a <= ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_sticky_ena_q;
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_enaAnd_b <= en;
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_enaAnd_q <= ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_enaAnd_a and ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_enaAnd_b;
--oFracXRRSmallXRR_uid65_fpSinPiTest(BITSELECT,64)@15
oFracXRRSmallXRR_uid65_fpSinPiTest_in <= oFracXRR_uid36_uid36_fpSinPiTest_q;
oFracXRRSmallXRR_uid65_fpSinPiTest_b <= oFracXRRSmallXRR_uid65_fpSinPiTest_in(53 downto 28);
--ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_inputreg(DELAY,822)
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => oFracXRRSmallXRR_uid65_fpSinPiTest_b, xout => ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt(COUNTER,824)
-- every=1, low=0, high=12, step=1, init=1
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_i = 11 THEN
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_eq = '1') THEN
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_i - 12;
ELSE
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_i <= ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_i,4));
--ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdreg(REG,825)
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdreg_q <= ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdmux(MUX,826)
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdmux_s <= en;
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdmux: PROCESS (ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdmux_s, ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdreg_q, ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdmux_s IS
WHEN "0" => ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdmux_q <= ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdreg_q;
WHEN "1" => ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdmux_q <= ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem(DUALMEM,823)
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_ia <= ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_inputreg_q;
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_aa <= ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdreg_q;
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_ab <= ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_rdmux_q;
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 4,
numwords_a => 13,
width_b => 26,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_iq,
address_a => ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_aa,
data_a => ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_ia
);
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_reset0 <= areset;
ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_q <= ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_iq(25 downto 0);
--y_uid42_fpSinPiTest(BITSELECT,41)@16
y_uid42_fpSinPiTest_in <= leftShiftStage1_uid167_fxpX_uid40_fpSinPiTest_q(66 downto 0);
y_uid42_fpSinPiTest_b <= y_uid42_fpSinPiTest_in(66 downto 1);
--reg_y_uid42_fpSinPiTest_0_to_oneMinusY_uid43_fpSinPiTest_1(REG,379)@16
reg_y_uid42_fpSinPiTest_0_to_oneMinusY_uid43_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid42_fpSinPiTest_0_to_oneMinusY_uid43_fpSinPiTest_1_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid42_fpSinPiTest_0_to_oneMinusY_uid43_fpSinPiTest_1_q <= y_uid42_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--pad_one_uid43_fpSinPiTest(BITJOIN,42)@16
pad_one_uid43_fpSinPiTest_q <= VCC_q & STD_LOGIC_VECTOR((65 downto 1 => GND_q(0)) & GND_q);
--reg_pad_one_uid43_fpSinPiTest_0_to_oneMinusY_uid43_fpSinPiTest_0(REG,378)@16
reg_pad_one_uid43_fpSinPiTest_0_to_oneMinusY_uid43_fpSinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_one_uid43_fpSinPiTest_0_to_oneMinusY_uid43_fpSinPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_one_uid43_fpSinPiTest_0_to_oneMinusY_uid43_fpSinPiTest_0_q <= pad_one_uid43_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--oneMinusY_uid43_fpSinPiTest(SUB,43)@17
oneMinusY_uid43_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_one_uid43_fpSinPiTest_0_to_oneMinusY_uid43_fpSinPiTest_0_q);
oneMinusY_uid43_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid42_fpSinPiTest_0_to_oneMinusY_uid43_fpSinPiTest_1_q);
oneMinusY_uid43_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid43_fpSinPiTest_a) - UNSIGNED(oneMinusY_uid43_fpSinPiTest_b));
oneMinusY_uid43_fpSinPiTest_q <= oneMinusY_uid43_fpSinPiTest_o(67 downto 0);
--oMyBottom_uid46_fpSinPiTest(BITSELECT,45)@17
oMyBottom_uid46_fpSinPiTest_in <= oneMinusY_uid43_fpSinPiTest_q(64 downto 0);
oMyBottom_uid46_fpSinPiTest_b <= oMyBottom_uid46_fpSinPiTest_in(64 downto 0);
--ld_oMyBottom_uid46_fpSinPiTest_b_to_reg_oMyBottom_uid46_fpSinPiTest_0_to_z_uid48_fpSinPiTest_3_a(DELAY,777)@17
ld_oMyBottom_uid46_fpSinPiTest_b_to_reg_oMyBottom_uid46_fpSinPiTest_0_to_z_uid48_fpSinPiTest_3_a : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => oMyBottom_uid46_fpSinPiTest_b, xout => ld_oMyBottom_uid46_fpSinPiTest_b_to_reg_oMyBottom_uid46_fpSinPiTest_0_to_z_uid48_fpSinPiTest_3_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_oMyBottom_uid46_fpSinPiTest_0_to_z_uid48_fpSinPiTest_3(REG,382)@18
reg_oMyBottom_uid46_fpSinPiTest_0_to_z_uid48_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oMyBottom_uid46_fpSinPiTest_0_to_z_uid48_fpSinPiTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oMyBottom_uid46_fpSinPiTest_0_to_z_uid48_fpSinPiTest_3_q <= ld_oMyBottom_uid46_fpSinPiTest_b_to_reg_oMyBottom_uid46_fpSinPiTest_0_to_z_uid48_fpSinPiTest_3_a_q;
END IF;
END IF;
END PROCESS;
--yBottom_uid47_fpSinPiTest(BITSELECT,46)@16
yBottom_uid47_fpSinPiTest_in <= y_uid42_fpSinPiTest_b(64 downto 0);
yBottom_uid47_fpSinPiTest_b <= yBottom_uid47_fpSinPiTest_in(64 downto 0);
--ld_yBottom_uid47_fpSinPiTest_b_to_reg_yBottom_uid47_fpSinPiTest_0_to_z_uid48_fpSinPiTest_2_a(DELAY,776)@16
ld_yBottom_uid47_fpSinPiTest_b_to_reg_yBottom_uid47_fpSinPiTest_0_to_z_uid48_fpSinPiTest_2_a : dspba_delay
GENERIC MAP ( width => 65, depth => 2 )
PORT MAP ( xin => yBottom_uid47_fpSinPiTest_b, xout => ld_yBottom_uid47_fpSinPiTest_b_to_reg_yBottom_uid47_fpSinPiTest_0_to_z_uid48_fpSinPiTest_2_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yBottom_uid47_fpSinPiTest_0_to_z_uid48_fpSinPiTest_2(REG,381)@18
reg_yBottom_uid47_fpSinPiTest_0_to_z_uid48_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yBottom_uid47_fpSinPiTest_0_to_z_uid48_fpSinPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yBottom_uid47_fpSinPiTest_0_to_z_uid48_fpSinPiTest_2_q <= ld_yBottom_uid47_fpSinPiTest_b_to_reg_yBottom_uid47_fpSinPiTest_0_to_z_uid48_fpSinPiTest_2_a_q;
END IF;
END IF;
END PROCESS;
--ld_y_uid42_fpSinPiTest_b_to_cmpYToOneMinusY_uid45_fpSinPiTest_b(DELAY,445)@16
ld_y_uid42_fpSinPiTest_b_to_cmpYToOneMinusY_uid45_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 66, depth => 2 )
PORT MAP ( xin => y_uid42_fpSinPiTest_b, xout => ld_y_uid42_fpSinPiTest_b_to_cmpYToOneMinusY_uid45_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_oneMinusY_uid43_fpSinPiTest_0_to_cmpYToOneMinusY_uid45_fpSinPiTest_0(REG,380)@17
reg_oneMinusY_uid43_fpSinPiTest_0_to_cmpYToOneMinusY_uid45_fpSinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid43_fpSinPiTest_0_to_cmpYToOneMinusY_uid45_fpSinPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid43_fpSinPiTest_0_to_cmpYToOneMinusY_uid45_fpSinPiTest_0_q <= oneMinusY_uid43_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid45_fpSinPiTest(COMPARE,44)@18
cmpYToOneMinusY_uid45_fpSinPiTest_cin <= GND_q;
cmpYToOneMinusY_uid45_fpSinPiTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid43_fpSinPiTest_0_to_cmpYToOneMinusY_uid45_fpSinPiTest_0_q) & '0';
cmpYToOneMinusY_uid45_fpSinPiTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid42_fpSinPiTest_b_to_cmpYToOneMinusY_uid45_fpSinPiTest_b_q) & cmpYToOneMinusY_uid45_fpSinPiTest_cin(0);
cmpYToOneMinusY_uid45_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
cmpYToOneMinusY_uid45_fpSinPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
cmpYToOneMinusY_uid45_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid45_fpSinPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid45_fpSinPiTest_b));
END IF;
END IF;
END PROCESS;
cmpYToOneMinusY_uid45_fpSinPiTest_c(0) <= cmpYToOneMinusY_uid45_fpSinPiTest_o(70);
--z_uid48_fpSinPiTest(MUX,47)@19
z_uid48_fpSinPiTest_s <= cmpYToOneMinusY_uid45_fpSinPiTest_c;
z_uid48_fpSinPiTest: PROCESS (z_uid48_fpSinPiTest_s, en, reg_yBottom_uid47_fpSinPiTest_0_to_z_uid48_fpSinPiTest_2_q, reg_oMyBottom_uid46_fpSinPiTest_0_to_z_uid48_fpSinPiTest_3_q)
BEGIN
CASE z_uid48_fpSinPiTest_s IS
WHEN "0" => z_uid48_fpSinPiTest_q <= reg_yBottom_uid47_fpSinPiTest_0_to_z_uid48_fpSinPiTest_2_q;
WHEN "1" => z_uid48_fpSinPiTest_q <= reg_oMyBottom_uid46_fpSinPiTest_0_to_z_uid48_fpSinPiTest_3_q;
WHEN OTHERS => z_uid48_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--zAddr_uid61_fpSinPiTest(BITSELECT,60)@19
zAddr_uid61_fpSinPiTest_in <= z_uid48_fpSinPiTest_q;
zAddr_uid61_fpSinPiTest_b <= zAddr_uid61_fpSinPiTest_in(64 downto 57);
--reg_zAddr_uid61_fpSinPiTest_0_to_memoryC2_uid252_sinPiZTableGenerator_lutmem_0(REG,398)@19
reg_zAddr_uid61_fpSinPiTest_0_to_memoryC2_uid252_sinPiZTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid61_fpSinPiTest_0_to_memoryC2_uid252_sinPiZTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid61_fpSinPiTest_0_to_memoryC2_uid252_sinPiZTableGenerator_lutmem_0_q <= zAddr_uid61_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid252_sinPiZTableGenerator_lutmem(DUALMEM,348)@20
memoryC2_uid252_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC2_uid252_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC2_uid252_sinPiZTableGenerator_lutmem_ab <= reg_zAddr_uid61_fpSinPiTest_0_to_memoryC2_uid252_sinPiZTableGenerator_lutmem_0_q;
memoryC2_uid252_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sin_s5_memoryC2_uid252_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid252_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid252_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid252_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC2_uid252_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC2_uid252_sinPiZTableGenerator_lutmem_ia
);
memoryC2_uid252_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC2_uid252_sinPiZTableGenerator_lutmem_q <= memoryC2_uid252_sinPiZTableGenerator_lutmem_iq(12 downto 0);
--reg_memoryC2_uid252_sinPiZTableGenerator_lutmem_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_1(REG,400)@22
reg_memoryC2_uid252_sinPiZTableGenerator_lutmem_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid252_sinPiZTableGenerator_lutmem_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid252_sinPiZTableGenerator_lutmem_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_1_q <= memoryC2_uid252_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPPolyEval_uid62_fpSinPiTest(BITSELECT,61)@19
zPPolyEval_uid62_fpSinPiTest_in <= z_uid48_fpSinPiTest_q(56 downto 0);
zPPolyEval_uid62_fpSinPiTest_b <= zPPolyEval_uid62_fpSinPiTest_in(56 downto 39);
--yT1_uid254_sinPiZPolyEval(BITSELECT,253)@19
yT1_uid254_sinPiZPolyEval_in <= zPPolyEval_uid62_fpSinPiTest_b;
yT1_uid254_sinPiZPolyEval_b <= yT1_uid254_sinPiZPolyEval_in(17 downto 5);
--ld_yT1_uid254_sinPiZPolyEval_b_to_reg_yT1_uid254_sinPiZPolyEval_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_0_a_inputreg(DELAY,1013)
ld_yT1_uid254_sinPiZPolyEval_b_to_reg_yT1_uid254_sinPiZPolyEval_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => yT1_uid254_sinPiZPolyEval_b, xout => ld_yT1_uid254_sinPiZPolyEval_b_to_reg_yT1_uid254_sinPiZPolyEval_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid254_sinPiZPolyEval_b_to_reg_yT1_uid254_sinPiZPolyEval_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_0_a(DELAY,794)@19
ld_yT1_uid254_sinPiZPolyEval_b_to_reg_yT1_uid254_sinPiZPolyEval_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_0_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_yT1_uid254_sinPiZPolyEval_b_to_reg_yT1_uid254_sinPiZPolyEval_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_0_a_inputreg_q, xout => ld_yT1_uid254_sinPiZPolyEval_b_to_reg_yT1_uid254_sinPiZPolyEval_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid254_sinPiZPolyEval_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_0(REG,399)@22
reg_yT1_uid254_sinPiZPolyEval_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid254_sinPiZPolyEval_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid254_sinPiZPolyEval_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_0_q <= ld_yT1_uid254_sinPiZPolyEval_b_to_reg_yT1_uid254_sinPiZPolyEval_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid327_pT1_uid255_sinPiZPolyEval(MULT,326)@23
prodXY_uid327_pT1_uid255_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid327_pT1_uid255_sinPiZPolyEval_a),14)) * SIGNED(prodXY_uid327_pT1_uid255_sinPiZPolyEval_b);
prodXY_uid327_pT1_uid255_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid327_pT1_uid255_sinPiZPolyEval_a <= (others => '0');
prodXY_uid327_pT1_uid255_sinPiZPolyEval_b <= (others => '0');
prodXY_uid327_pT1_uid255_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid327_pT1_uid255_sinPiZPolyEval_a <= reg_yT1_uid254_sinPiZPolyEval_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_0_q;
prodXY_uid327_pT1_uid255_sinPiZPolyEval_b <= reg_memoryC2_uid252_sinPiZTableGenerator_lutmem_0_to_prodXY_uid327_pT1_uid255_sinPiZPolyEval_1_q;
prodXY_uid327_pT1_uid255_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid327_pT1_uid255_sinPiZPolyEval_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid327_pT1_uid255_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid327_pT1_uid255_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid327_pT1_uid255_sinPiZPolyEval_q <= prodXY_uid327_pT1_uid255_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid328_pT1_uid255_sinPiZPolyEval(BITSELECT,327)@26
prodXYTruncFR_uid328_pT1_uid255_sinPiZPolyEval_in <= prodXY_uid327_pT1_uid255_sinPiZPolyEval_q;
prodXYTruncFR_uid328_pT1_uid255_sinPiZPolyEval_b <= prodXYTruncFR_uid328_pT1_uid255_sinPiZPolyEval_in(25 downto 12);
--highBBits_uid257_sinPiZPolyEval(BITSELECT,256)@26
highBBits_uid257_sinPiZPolyEval_in <= prodXYTruncFR_uid328_pT1_uid255_sinPiZPolyEval_b;
highBBits_uid257_sinPiZPolyEval_b <= highBBits_uid257_sinPiZPolyEval_in(13 downto 1);
--ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC1_uid250_sinPiZTableGenerator_lutmem_0_a(DELAY,796)@19
ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC1_uid250_sinPiZTableGenerator_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => zAddr_uid61_fpSinPiTest_b, xout => ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC1_uid250_sinPiZTableGenerator_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_zAddr_uid61_fpSinPiTest_0_to_memoryC1_uid250_sinPiZTableGenerator_lutmem_0(REG,401)@22
reg_zAddr_uid61_fpSinPiTest_0_to_memoryC1_uid250_sinPiZTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid61_fpSinPiTest_0_to_memoryC1_uid250_sinPiZTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid61_fpSinPiTest_0_to_memoryC1_uid250_sinPiZTableGenerator_lutmem_0_q <= ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC1_uid250_sinPiZTableGenerator_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid250_sinPiZTableGenerator_lutmem(DUALMEM,347)@23
memoryC1_uid250_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid250_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid250_sinPiZTableGenerator_lutmem_ab <= reg_zAddr_uid61_fpSinPiTest_0_to_memoryC1_uid250_sinPiZTableGenerator_lutmem_0_q;
memoryC1_uid250_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sin_s5_memoryC1_uid250_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid250_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid250_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid250_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC1_uid250_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC1_uid250_sinPiZTableGenerator_lutmem_ia
);
memoryC1_uid250_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid250_sinPiZTableGenerator_lutmem_q <= memoryC1_uid250_sinPiZTableGenerator_lutmem_iq(20 downto 0);
--reg_memoryC1_uid250_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid258_sinPiZPolyEval_0(REG,402)@25
reg_memoryC1_uid250_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid258_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid250_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid258_sinPiZPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid250_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid258_sinPiZPolyEval_0_q <= memoryC1_uid250_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid258_sinPiZPolyEval(ADD,257)@26
sumAHighB_uid258_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid250_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid258_sinPiZPolyEval_0_q(20)) & reg_memoryC1_uid250_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid258_sinPiZPolyEval_0_q);
sumAHighB_uid258_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid257_sinPiZPolyEval_b(12)) & highBBits_uid257_sinPiZPolyEval_b);
sumAHighB_uid258_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid258_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid258_sinPiZPolyEval_b));
sumAHighB_uid258_sinPiZPolyEval_q <= sumAHighB_uid258_sinPiZPolyEval_o(21 downto 0);
--lowRangeB_uid256_sinPiZPolyEval(BITSELECT,255)@26
lowRangeB_uid256_sinPiZPolyEval_in <= prodXYTruncFR_uid328_pT1_uid255_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid256_sinPiZPolyEval_b <= lowRangeB_uid256_sinPiZPolyEval_in(0 downto 0);
--s1_uid256_uid259_sinPiZPolyEval(BITJOIN,258)@26
s1_uid256_uid259_sinPiZPolyEval_q <= sumAHighB_uid258_sinPiZPolyEval_q & lowRangeB_uid256_sinPiZPolyEval_b;
--reg_s1_uid256_uid259_sinPiZPolyEval_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_1(REG,404)@26
reg_s1_uid256_uid259_sinPiZPolyEval_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid256_uid259_sinPiZPolyEval_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid256_uid259_sinPiZPolyEval_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_1_q <= s1_uid256_uid259_sinPiZPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_nor(LOGICAL,1010)
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_nor_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q;
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_nor_b <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_nor_q <= not (ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_nor_a or ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_nor_b);
--ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_mem_top(CONSTANT,1006)
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_mem_top_q <= "0100";
--ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_cmp(LOGICAL,1007)
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_cmp_a <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_mem_top_q;
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdmux_q);
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_cmp_q <= "1" when ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_cmp_a = ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_cmp_b else "0";
--ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_cmpReg(REG,1008)
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_cmpReg_q <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_sticky_ena(REG,1011)
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_nor_q = "1") THEN
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_sticky_ena_q <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_enaAnd(LOGICAL,1012)
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_enaAnd_a <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_sticky_ena_q;
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_enaAnd_b <= en;
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_enaAnd_q <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_enaAnd_a and ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_enaAnd_b;
--reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0(REG,403)@19
reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q <= "000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q <= zPPolyEval_uid62_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_inputreg(DELAY,1000)
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_inputreg : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q, xout => ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt(COUNTER,1002)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_i = 3 THEN
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_i,3));
--ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdreg(REG,1003)
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdreg_q <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdmux(MUX,1004)
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdmux_s <= en;
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdmux_s, ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdreg_q, ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem(DUALMEM,1001)
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_ia <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_inputreg_q;
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_aa <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdreg_q;
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_ab <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdmux_q;
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 18,
widthad_a => 3,
numwords_a => 5,
width_b => 18,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_ia
);
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_q <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_iq(17 downto 0);
--prodXY_uid330_pT2_uid261_sinPiZPolyEval(MULT,329)@27
prodXY_uid330_pT2_uid261_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid330_pT2_uid261_sinPiZPolyEval_a),19)) * SIGNED(prodXY_uid330_pT2_uid261_sinPiZPolyEval_b);
prodXY_uid330_pT2_uid261_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid330_pT2_uid261_sinPiZPolyEval_a <= (others => '0');
prodXY_uid330_pT2_uid261_sinPiZPolyEval_b <= (others => '0');
prodXY_uid330_pT2_uid261_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid330_pT2_uid261_sinPiZPolyEval_a <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_mem_q;
prodXY_uid330_pT2_uid261_sinPiZPolyEval_b <= reg_s1_uid256_uid259_sinPiZPolyEval_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_1_q;
prodXY_uid330_pT2_uid261_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid330_pT2_uid261_sinPiZPolyEval_pr,41));
END IF;
END IF;
END PROCESS;
prodXY_uid330_pT2_uid261_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid330_pT2_uid261_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid330_pT2_uid261_sinPiZPolyEval_q <= prodXY_uid330_pT2_uid261_sinPiZPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid331_pT2_uid261_sinPiZPolyEval(BITSELECT,330)@30
prodXYTruncFR_uid331_pT2_uid261_sinPiZPolyEval_in <= prodXY_uid330_pT2_uid261_sinPiZPolyEval_q;
prodXYTruncFR_uid331_pT2_uid261_sinPiZPolyEval_b <= prodXYTruncFR_uid331_pT2_uid261_sinPiZPolyEval_in(40 downto 17);
--highBBits_uid263_sinPiZPolyEval(BITSELECT,262)@30
highBBits_uid263_sinPiZPolyEval_in <= prodXYTruncFR_uid331_pT2_uid261_sinPiZPolyEval_b;
highBBits_uid263_sinPiZPolyEval_b <= highBBits_uid263_sinPiZPolyEval_in(23 downto 2);
--ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_nor(LOGICAL,1024)
ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_nor_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q;
ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_nor_b <= ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q;
ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_nor_q <= not (ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_nor_a or ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_nor_b);
--ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_sticky_ena(REG,1025)
ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_nor_q = "1") THEN
ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_enaAnd(LOGICAL,1026)
ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_enaAnd_a <= ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q;
ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_enaAnd_b <= en;
ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_enaAnd_q <= ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_enaAnd_a and ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_enaAnd_b;
--ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_inputreg(DELAY,1014)
ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => zAddr_uid61_fpSinPiTest_b, xout => ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem(DUALMEM,1015)
ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia <= ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_inputreg_q;
ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdreg_q;
ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_zPPolyEval_uid62_fpSinPiTest_0_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_0_q_to_prodXY_uid330_pT2_uid261_sinPiZPolyEval_a_replace_rdmux_q;
ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq,
address_a => ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa,
data_a => ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia
);
ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset;
ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_q <= ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0(REG,405)@26
reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_q <= ld_zAddr_uid61_fpSinPiTest_b_to_reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid248_sinPiZTableGenerator_lutmem(DUALMEM,346)@27
memoryC0_uid248_sinPiZTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid248_sinPiZTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid248_sinPiZTableGenerator_lutmem_ab <= reg_zAddr_uid61_fpSinPiTest_0_to_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_q;
memoryC0_uid248_sinPiZTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sin_s5_memoryC0_uid248_sinPiZTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid248_sinPiZTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid248_sinPiZTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid248_sinPiZTableGenerator_lutmem_iq,
address_a => memoryC0_uid248_sinPiZTableGenerator_lutmem_aa,
data_a => memoryC0_uid248_sinPiZTableGenerator_lutmem_ia
);
memoryC0_uid248_sinPiZTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid248_sinPiZTableGenerator_lutmem_q <= memoryC0_uid248_sinPiZTableGenerator_lutmem_iq(29 downto 0);
--reg_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid264_sinPiZPolyEval_0(REG,406)@29
reg_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid264_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid264_sinPiZPolyEval_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid264_sinPiZPolyEval_0_q <= memoryC0_uid248_sinPiZTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid264_sinPiZPolyEval(ADD,263)@30
sumAHighB_uid264_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid264_sinPiZPolyEval_0_q(29)) & reg_memoryC0_uid248_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid264_sinPiZPolyEval_0_q);
sumAHighB_uid264_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid263_sinPiZPolyEval_b(21)) & highBBits_uid263_sinPiZPolyEval_b);
sumAHighB_uid264_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid264_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid264_sinPiZPolyEval_b));
sumAHighB_uid264_sinPiZPolyEval_q <= sumAHighB_uid264_sinPiZPolyEval_o(30 downto 0);
--lowRangeB_uid262_sinPiZPolyEval(BITSELECT,261)@30
lowRangeB_uid262_sinPiZPolyEval_in <= prodXYTruncFR_uid331_pT2_uid261_sinPiZPolyEval_b(1 downto 0);
lowRangeB_uid262_sinPiZPolyEval_b <= lowRangeB_uid262_sinPiZPolyEval_in(1 downto 0);
--s2_uid262_uid265_sinPiZPolyEval(BITJOIN,264)@30
s2_uid262_uid265_sinPiZPolyEval_q <= sumAHighB_uid264_sinPiZPolyEval_q & lowRangeB_uid262_sinPiZPolyEval_b;
--fxpSinRes_uid64_fpSinPiTest(BITSELECT,63)@30
fxpSinRes_uid64_fpSinPiTest_in <= s2_uid262_uid265_sinPiZPolyEval_q(30 downto 0);
fxpSinRes_uid64_fpSinPiTest_b <= fxpSinRes_uid64_fpSinPiTest_in(30 downto 5);
--ld_sinXIsXRR_uid35_fpSinPiTest_n_to_multSecondOperand_uid66_fpSinPiTest_b(DELAY,463)@14
ld_sinXIsXRR_uid35_fpSinPiTest_n_to_multSecondOperand_uid66_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => sinXIsXRR_uid35_fpSinPiTest_n, xout => ld_sinXIsXRR_uid35_fpSinPiTest_n_to_multSecondOperand_uid66_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--multSecondOperand_uid66_fpSinPiTest(MUX,65)@30
multSecondOperand_uid66_fpSinPiTest_s <= ld_sinXIsXRR_uid35_fpSinPiTest_n_to_multSecondOperand_uid66_fpSinPiTest_b_q;
multSecondOperand_uid66_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSecondOperand_uid66_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE multSecondOperand_uid66_fpSinPiTest_s IS
WHEN "0" => multSecondOperand_uid66_fpSinPiTest_q <= fxpSinRes_uid64_fpSinPiTest_b;
WHEN "1" => multSecondOperand_uid66_fpSinPiTest_q <= ld_oFracXRRSmallXRR_uid65_fpSinPiTest_b_to_multSecondOperand_uid66_fpSinPiTest_d_replace_mem_q;
WHEN OTHERS => multSecondOperand_uid66_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_nor(LOGICAL,843)
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_nor_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q;
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_nor_b <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_sticky_ena_q;
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_nor_q <= not (ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_nor_a or ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_nor_b);
--ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_sticky_ena(REG,844)
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_nor_q = "1") THEN
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_sticky_ena_q <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_enaAnd(LOGICAL,845)
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_enaAnd_a <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_sticky_ena_q;
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_enaAnd_b <= en;
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_enaAnd_q <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_enaAnd_a and ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_enaAnd_b;
--cPi_uid52_fpSinPiTest(CONSTANT,51)
cPi_uid52_fpSinPiTest_q <= "11001001000011111101101011";
--LeftShiftStage263dto0_uid243_alignedZ_uid51_fpSinPiTest(BITSELECT,242)@25
LeftShiftStage263dto0_uid243_alignedZ_uid51_fpSinPiTest_in <= leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_q(63 downto 0);
LeftShiftStage263dto0_uid243_alignedZ_uid51_fpSinPiTest_b <= LeftShiftStage263dto0_uid243_alignedZ_uid51_fpSinPiTest_in(63 downto 0);
--leftShiftStage3Idx1_uid244_alignedZ_uid51_fpSinPiTest(BITJOIN,243)@25
leftShiftStage3Idx1_uid244_alignedZ_uid51_fpSinPiTest_q <= LeftShiftStage263dto0_uid243_alignedZ_uid51_fpSinPiTest_b & GND_q;
--leftShiftStage0Idx2_uid216_alignedZ_uid51_fpSinPiTest(CONSTANT,215)
leftShiftStage0Idx2_uid216_alignedZ_uid51_fpSinPiTest_q <= "00000000000000000000000000000000000000000000000000000000000000000";
--ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_nor(LOGICAL,982)
ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_nor_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q;
ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_nor_b <= ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_sticky_ena_q;
ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_nor_q <= not (ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_nor_a or ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_nor_b);
--ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_sticky_ena(REG,983)
ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_nor_q = "1") THEN
ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_sticky_ena_q <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_enaAnd(LOGICAL,984)
ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_enaAnd_a <= ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_sticky_ena_q;
ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_enaAnd_b <= en;
ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_enaAnd_q <= ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_enaAnd_a and ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_enaAnd_b;
--X32dto0_uid214_alignedZ_uid51_fpSinPiTest(BITSELECT,213)@19
X32dto0_uid214_alignedZ_uid51_fpSinPiTest_in <= z_uid48_fpSinPiTest_q(32 downto 0);
X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b <= X32dto0_uid214_alignedZ_uid51_fpSinPiTest_in(32 downto 0);
--ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_inputreg(DELAY,974)
ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b, xout => ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem(DUALMEM,975)
ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_ia <= ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_inputreg_q;
ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_aa <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdreg_q;
ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_ab <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdmux_q;
ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 1,
numwords_a => 2,
width_b => 33,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_iq,
address_a => ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_aa,
data_a => ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_ia
);
ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_q <= ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_iq(32 downto 0);
--zs_uid177_lzcZ_uid50_fpSinPiTest(CONSTANT,176)
zs_uid177_lzcZ_uid50_fpSinPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest(BITJOIN,214)@23
leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_q <= ld_X32dto0_uid214_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_b_replace_mem_q & zs_uid177_lzcZ_uid50_fpSinPiTest_q;
--ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_nor(LOGICAL,993)
ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_nor_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q;
ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_nor_b <= ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_sticky_ena_q;
ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_nor_q <= not (ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_nor_a or ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_nor_b);
--ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_sticky_ena(REG,994)
ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_nor_q = "1") THEN
ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_sticky_ena_q <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_enaAnd(LOGICAL,995)
ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_enaAnd_a <= ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_sticky_ena_q;
ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_enaAnd_b <= en;
ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_enaAnd_q <= ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_enaAnd_a and ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_enaAnd_b;
--ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_inputreg(DELAY,985)
ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => z_uid48_fpSinPiTest_q, xout => ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem(DUALMEM,986)
ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_ia <= ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_inputreg_q;
ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_aa <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdreg_q;
ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_ab <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdmux_q;
ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 65,
widthad_a => 1,
numwords_a => 2,
width_b => 65,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_iq,
address_a => ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_aa,
data_a => ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_ia
);
ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_reset0 <= areset;
ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_q <= ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_iq(64 downto 0);
--zs_uid169_lzcZ_uid50_fpSinPiTest(CONSTANT,168)
zs_uid169_lzcZ_uid50_fpSinPiTest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--rVStage_uid170_lzcZ_uid50_fpSinPiTest(BITSELECT,169)@19
rVStage_uid170_lzcZ_uid50_fpSinPiTest_in <= z_uid48_fpSinPiTest_q;
rVStage_uid170_lzcZ_uid50_fpSinPiTest_b <= rVStage_uid170_lzcZ_uid50_fpSinPiTest_in(64 downto 1);
--vCount_uid171_lzcZ_uid50_fpSinPiTest(LOGICAL,170)@19
vCount_uid171_lzcZ_uid50_fpSinPiTest_a <= rVStage_uid170_lzcZ_uid50_fpSinPiTest_b;
vCount_uid171_lzcZ_uid50_fpSinPiTest_b <= zs_uid169_lzcZ_uid50_fpSinPiTest_q;
vCount_uid171_lzcZ_uid50_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid171_lzcZ_uid50_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid171_lzcZ_uid50_fpSinPiTest_a = vCount_uid171_lzcZ_uid50_fpSinPiTest_b) THEN
vCount_uid171_lzcZ_uid50_fpSinPiTest_q <= "1";
ELSE
vCount_uid171_lzcZ_uid50_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid171_lzcZ_uid50_fpSinPiTest_q_to_r_uid210_lzcZ_uid50_fpSinPiTest_g(DELAY,604)@20
ld_vCount_uid171_lzcZ_uid50_fpSinPiTest_q_to_r_uid210_lzcZ_uid50_fpSinPiTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => vCount_uid171_lzcZ_uid50_fpSinPiTest_q, xout => ld_vCount_uid171_lzcZ_uid50_fpSinPiTest_q_to_r_uid210_lzcZ_uid50_fpSinPiTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid173_lzcZ_uid50_fpSinPiTest(BITSELECT,172)@19
vStage_uid173_lzcZ_uid50_fpSinPiTest_in <= z_uid48_fpSinPiTest_q(0 downto 0);
vStage_uid173_lzcZ_uid50_fpSinPiTest_b <= vStage_uid173_lzcZ_uid50_fpSinPiTest_in(0 downto 0);
--ld_vStage_uid173_lzcZ_uid50_fpSinPiTest_b_to_cStage_uid174_lzcZ_uid50_fpSinPiTest_b(DELAY,562)@19
ld_vStage_uid173_lzcZ_uid50_fpSinPiTest_b_to_cStage_uid174_lzcZ_uid50_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vStage_uid173_lzcZ_uid50_fpSinPiTest_b, xout => ld_vStage_uid173_lzcZ_uid50_fpSinPiTest_b_to_cStage_uid174_lzcZ_uid50_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid172_lzcZ_uid50_fpSinPiTest(CONSTANT,171)
mO_uid172_lzcZ_uid50_fpSinPiTest_q <= "111111111111111111111111111111111111111111111111111111111111111";
--cStage_uid174_lzcZ_uid50_fpSinPiTest(BITJOIN,173)@20
cStage_uid174_lzcZ_uid50_fpSinPiTest_q <= ld_vStage_uid173_lzcZ_uid50_fpSinPiTest_b_to_cStage_uid174_lzcZ_uid50_fpSinPiTest_b_q & mO_uid172_lzcZ_uid50_fpSinPiTest_q;
--ld_rVStage_uid170_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid176_lzcZ_uid50_fpSinPiTest_c(DELAY,564)@19
ld_rVStage_uid170_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid176_lzcZ_uid50_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid170_lzcZ_uid50_fpSinPiTest_b, xout => ld_rVStage_uid170_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid176_lzcZ_uid50_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid176_lzcZ_uid50_fpSinPiTest(MUX,175)@20
vStagei_uid176_lzcZ_uid50_fpSinPiTest_s <= vCount_uid171_lzcZ_uid50_fpSinPiTest_q;
vStagei_uid176_lzcZ_uid50_fpSinPiTest: PROCESS (vStagei_uid176_lzcZ_uid50_fpSinPiTest_s, en, ld_rVStage_uid170_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid176_lzcZ_uid50_fpSinPiTest_c_q, cStage_uid174_lzcZ_uid50_fpSinPiTest_q)
BEGIN
CASE vStagei_uid176_lzcZ_uid50_fpSinPiTest_s IS
WHEN "0" => vStagei_uid176_lzcZ_uid50_fpSinPiTest_q <= ld_rVStage_uid170_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid176_lzcZ_uid50_fpSinPiTest_c_q;
WHEN "1" => vStagei_uid176_lzcZ_uid50_fpSinPiTest_q <= cStage_uid174_lzcZ_uid50_fpSinPiTest_q;
WHEN OTHERS => vStagei_uid176_lzcZ_uid50_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid178_lzcZ_uid50_fpSinPiTest(BITSELECT,177)@20
rVStage_uid178_lzcZ_uid50_fpSinPiTest_in <= vStagei_uid176_lzcZ_uid50_fpSinPiTest_q;
rVStage_uid178_lzcZ_uid50_fpSinPiTest_b <= rVStage_uid178_lzcZ_uid50_fpSinPiTest_in(63 downto 32);
--vCount_uid179_lzcZ_uid50_fpSinPiTest(LOGICAL,178)@20
vCount_uid179_lzcZ_uid50_fpSinPiTest_a <= rVStage_uid178_lzcZ_uid50_fpSinPiTest_b;
vCount_uid179_lzcZ_uid50_fpSinPiTest_b <= zs_uid177_lzcZ_uid50_fpSinPiTest_q;
vCount_uid179_lzcZ_uid50_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid179_lzcZ_uid50_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid179_lzcZ_uid50_fpSinPiTest_a = vCount_uid179_lzcZ_uid50_fpSinPiTest_b) THEN
vCount_uid179_lzcZ_uid50_fpSinPiTest_q <= "1";
ELSE
vCount_uid179_lzcZ_uid50_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--ld_vCount_uid179_lzcZ_uid50_fpSinPiTest_q_to_r_uid210_lzcZ_uid50_fpSinPiTest_f(DELAY,603)@21
ld_vCount_uid179_lzcZ_uid50_fpSinPiTest_q_to_r_uid210_lzcZ_uid50_fpSinPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid179_lzcZ_uid50_fpSinPiTest_q, xout => ld_vCount_uid179_lzcZ_uid50_fpSinPiTest_q_to_r_uid210_lzcZ_uid50_fpSinPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid180_lzcZ_uid50_fpSinPiTest(BITSELECT,179)@20
vStage_uid180_lzcZ_uid50_fpSinPiTest_in <= vStagei_uid176_lzcZ_uid50_fpSinPiTest_q(31 downto 0);
vStage_uid180_lzcZ_uid50_fpSinPiTest_b <= vStage_uid180_lzcZ_uid50_fpSinPiTest_in(31 downto 0);
--ld_vStage_uid180_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid182_lzcZ_uid50_fpSinPiTest_d(DELAY,571)@20
ld_vStage_uid180_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid182_lzcZ_uid50_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => vStage_uid180_lzcZ_uid50_fpSinPiTest_b, xout => ld_vStage_uid180_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid182_lzcZ_uid50_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_rVStage_uid178_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid182_lzcZ_uid50_fpSinPiTest_c(DELAY,570)@20
ld_rVStage_uid178_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid182_lzcZ_uid50_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid178_lzcZ_uid50_fpSinPiTest_b, xout => ld_rVStage_uid178_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid182_lzcZ_uid50_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid182_lzcZ_uid50_fpSinPiTest(MUX,181)@21
vStagei_uid182_lzcZ_uid50_fpSinPiTest_s <= vCount_uid179_lzcZ_uid50_fpSinPiTest_q;
vStagei_uid182_lzcZ_uid50_fpSinPiTest: PROCESS (vStagei_uid182_lzcZ_uid50_fpSinPiTest_s, en, ld_rVStage_uid178_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid182_lzcZ_uid50_fpSinPiTest_c_q, ld_vStage_uid180_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid182_lzcZ_uid50_fpSinPiTest_d_q)
BEGIN
CASE vStagei_uid182_lzcZ_uid50_fpSinPiTest_s IS
WHEN "0" => vStagei_uid182_lzcZ_uid50_fpSinPiTest_q <= ld_rVStage_uid178_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid182_lzcZ_uid50_fpSinPiTest_c_q;
WHEN "1" => vStagei_uid182_lzcZ_uid50_fpSinPiTest_q <= ld_vStage_uid180_lzcZ_uid50_fpSinPiTest_b_to_vStagei_uid182_lzcZ_uid50_fpSinPiTest_d_q;
WHEN OTHERS => vStagei_uid182_lzcZ_uid50_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid184_lzcZ_uid50_fpSinPiTest(BITSELECT,183)@21
rVStage_uid184_lzcZ_uid50_fpSinPiTest_in <= vStagei_uid182_lzcZ_uid50_fpSinPiTest_q;
rVStage_uid184_lzcZ_uid50_fpSinPiTest_b <= rVStage_uid184_lzcZ_uid50_fpSinPiTest_in(31 downto 16);
--vCount_uid185_lzcZ_uid50_fpSinPiTest(LOGICAL,184)@21
vCount_uid185_lzcZ_uid50_fpSinPiTest_a <= rVStage_uid184_lzcZ_uid50_fpSinPiTest_b;
vCount_uid185_lzcZ_uid50_fpSinPiTest_b <= zs_uid183_lzcZ_uid50_fpSinPiTest_q;
vCount_uid185_lzcZ_uid50_fpSinPiTest_q <= "1" when vCount_uid185_lzcZ_uid50_fpSinPiTest_a = vCount_uid185_lzcZ_uid50_fpSinPiTest_b else "0";
--ld_vCount_uid185_lzcZ_uid50_fpSinPiTest_q_to_reg_vCount_uid185_lzcZ_uid50_fpSinPiTest_0_to_r_uid210_lzcZ_uid50_fpSinPiTest_4_a(DELAY,783)@21
ld_vCount_uid185_lzcZ_uid50_fpSinPiTest_q_to_reg_vCount_uid185_lzcZ_uid50_fpSinPiTest_0_to_r_uid210_lzcZ_uid50_fpSinPiTest_4_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid185_lzcZ_uid50_fpSinPiTest_q, xout => ld_vCount_uid185_lzcZ_uid50_fpSinPiTest_q_to_reg_vCount_uid185_lzcZ_uid50_fpSinPiTest_0_to_r_uid210_lzcZ_uid50_fpSinPiTest_4_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid185_lzcZ_uid50_fpSinPiTest_0_to_r_uid210_lzcZ_uid50_fpSinPiTest_4(REG,388)@22
reg_vCount_uid185_lzcZ_uid50_fpSinPiTest_0_to_r_uid210_lzcZ_uid50_fpSinPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid185_lzcZ_uid50_fpSinPiTest_0_to_r_uid210_lzcZ_uid50_fpSinPiTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid185_lzcZ_uid50_fpSinPiTest_0_to_r_uid210_lzcZ_uid50_fpSinPiTest_4_q <= ld_vCount_uid185_lzcZ_uid50_fpSinPiTest_q_to_reg_vCount_uid185_lzcZ_uid50_fpSinPiTest_0_to_r_uid210_lzcZ_uid50_fpSinPiTest_4_a_q;
END IF;
END IF;
END PROCESS;
--vStage_uid186_lzcZ_uid50_fpSinPiTest(BITSELECT,185)@21
vStage_uid186_lzcZ_uid50_fpSinPiTest_in <= vStagei_uid182_lzcZ_uid50_fpSinPiTest_q(15 downto 0);
vStage_uid186_lzcZ_uid50_fpSinPiTest_b <= vStage_uid186_lzcZ_uid50_fpSinPiTest_in(15 downto 0);
--vStagei_uid188_lzcZ_uid50_fpSinPiTest(MUX,187)@21
vStagei_uid188_lzcZ_uid50_fpSinPiTest_s <= vCount_uid185_lzcZ_uid50_fpSinPiTest_q;
vStagei_uid188_lzcZ_uid50_fpSinPiTest: PROCESS (vStagei_uid188_lzcZ_uid50_fpSinPiTest_s, en, rVStage_uid184_lzcZ_uid50_fpSinPiTest_b, vStage_uid186_lzcZ_uid50_fpSinPiTest_b)
BEGIN
CASE vStagei_uid188_lzcZ_uid50_fpSinPiTest_s IS
WHEN "0" => vStagei_uid188_lzcZ_uid50_fpSinPiTest_q <= rVStage_uid184_lzcZ_uid50_fpSinPiTest_b;
WHEN "1" => vStagei_uid188_lzcZ_uid50_fpSinPiTest_q <= vStage_uid186_lzcZ_uid50_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid188_lzcZ_uid50_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid190_lzcZ_uid50_fpSinPiTest(BITSELECT,189)@21
rVStage_uid190_lzcZ_uid50_fpSinPiTest_in <= vStagei_uid188_lzcZ_uid50_fpSinPiTest_q;
rVStage_uid190_lzcZ_uid50_fpSinPiTest_b <= rVStage_uid190_lzcZ_uid50_fpSinPiTest_in(15 downto 8);
--reg_rVStage_uid190_lzcZ_uid50_fpSinPiTest_0_to_vCount_uid191_lzcZ_uid50_fpSinPiTest_1(REG,383)@21
reg_rVStage_uid190_lzcZ_uid50_fpSinPiTest_0_to_vCount_uid191_lzcZ_uid50_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid190_lzcZ_uid50_fpSinPiTest_0_to_vCount_uid191_lzcZ_uid50_fpSinPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid190_lzcZ_uid50_fpSinPiTest_0_to_vCount_uid191_lzcZ_uid50_fpSinPiTest_1_q <= rVStage_uid190_lzcZ_uid50_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid191_lzcZ_uid50_fpSinPiTest(LOGICAL,190)@22
vCount_uid191_lzcZ_uid50_fpSinPiTest_a <= reg_rVStage_uid190_lzcZ_uid50_fpSinPiTest_0_to_vCount_uid191_lzcZ_uid50_fpSinPiTest_1_q;
vCount_uid191_lzcZ_uid50_fpSinPiTest_b <= cstAllZWE_uid8_fpSinPiTest_q;
vCount_uid191_lzcZ_uid50_fpSinPiTest_q <= "1" when vCount_uid191_lzcZ_uid50_fpSinPiTest_a = vCount_uid191_lzcZ_uid50_fpSinPiTest_b else "0";
--ld_vCount_uid191_lzcZ_uid50_fpSinPiTest_q_to_r_uid210_lzcZ_uid50_fpSinPiTest_d(DELAY,601)@22
ld_vCount_uid191_lzcZ_uid50_fpSinPiTest_q_to_r_uid210_lzcZ_uid50_fpSinPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid191_lzcZ_uid50_fpSinPiTest_q, xout => ld_vCount_uid191_lzcZ_uid50_fpSinPiTest_q_to_r_uid210_lzcZ_uid50_fpSinPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid192_lzcZ_uid50_fpSinPiTest(BITSELECT,191)@21
vStage_uid192_lzcZ_uid50_fpSinPiTest_in <= vStagei_uid188_lzcZ_uid50_fpSinPiTest_q(7 downto 0);
vStage_uid192_lzcZ_uid50_fpSinPiTest_b <= vStage_uid192_lzcZ_uid50_fpSinPiTest_in(7 downto 0);
--reg_vStage_uid192_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid194_lzcZ_uid50_fpSinPiTest_3(REG,385)@21
reg_vStage_uid192_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid194_lzcZ_uid50_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid192_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid194_lzcZ_uid50_fpSinPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid192_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid194_lzcZ_uid50_fpSinPiTest_3_q <= vStage_uid192_lzcZ_uid50_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid194_lzcZ_uid50_fpSinPiTest(MUX,193)@22
vStagei_uid194_lzcZ_uid50_fpSinPiTest_s <= vCount_uid191_lzcZ_uid50_fpSinPiTest_q;
vStagei_uid194_lzcZ_uid50_fpSinPiTest: PROCESS (vStagei_uid194_lzcZ_uid50_fpSinPiTest_s, en, reg_rVStage_uid190_lzcZ_uid50_fpSinPiTest_0_to_vCount_uid191_lzcZ_uid50_fpSinPiTest_1_q, reg_vStage_uid192_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid194_lzcZ_uid50_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid194_lzcZ_uid50_fpSinPiTest_s IS
WHEN "0" => vStagei_uid194_lzcZ_uid50_fpSinPiTest_q <= reg_rVStage_uid190_lzcZ_uid50_fpSinPiTest_0_to_vCount_uid191_lzcZ_uid50_fpSinPiTest_1_q;
WHEN "1" => vStagei_uid194_lzcZ_uid50_fpSinPiTest_q <= reg_vStage_uid192_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid194_lzcZ_uid50_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid194_lzcZ_uid50_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid196_lzcZ_uid50_fpSinPiTest(BITSELECT,195)@22
rVStage_uid196_lzcZ_uid50_fpSinPiTest_in <= vStagei_uid194_lzcZ_uid50_fpSinPiTest_q;
rVStage_uid196_lzcZ_uid50_fpSinPiTest_b <= rVStage_uid196_lzcZ_uid50_fpSinPiTest_in(7 downto 4);
--vCount_uid197_lzcZ_uid50_fpSinPiTest(LOGICAL,196)@22
vCount_uid197_lzcZ_uid50_fpSinPiTest_a <= rVStage_uid196_lzcZ_uid50_fpSinPiTest_b;
vCount_uid197_lzcZ_uid50_fpSinPiTest_b <= leftShiftStage0Idx1Pad4_uid146_fxpX_uid40_fpSinPiTest_q;
vCount_uid197_lzcZ_uid50_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCount_uid197_lzcZ_uid50_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
IF (vCount_uid197_lzcZ_uid50_fpSinPiTest_a = vCount_uid197_lzcZ_uid50_fpSinPiTest_b) THEN
vCount_uid197_lzcZ_uid50_fpSinPiTest_q <= "1";
ELSE
vCount_uid197_lzcZ_uid50_fpSinPiTest_q <= "0";
END IF;
END IF;
END IF;
END PROCESS;
--vStage_uid198_lzcZ_uid50_fpSinPiTest(BITSELECT,197)@22
vStage_uid198_lzcZ_uid50_fpSinPiTest_in <= vStagei_uid194_lzcZ_uid50_fpSinPiTest_q(3 downto 0);
vStage_uid198_lzcZ_uid50_fpSinPiTest_b <= vStage_uid198_lzcZ_uid50_fpSinPiTest_in(3 downto 0);
--reg_vStage_uid198_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid200_lzcZ_uid50_fpSinPiTest_3(REG,387)@22
reg_vStage_uid198_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid200_lzcZ_uid50_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid198_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid200_lzcZ_uid50_fpSinPiTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid198_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid200_lzcZ_uid50_fpSinPiTest_3_q <= vStage_uid198_lzcZ_uid50_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid196_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid200_lzcZ_uid50_fpSinPiTest_2(REG,386)@22
reg_rVStage_uid196_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid200_lzcZ_uid50_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid196_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid200_lzcZ_uid50_fpSinPiTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid196_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid200_lzcZ_uid50_fpSinPiTest_2_q <= rVStage_uid196_lzcZ_uid50_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid200_lzcZ_uid50_fpSinPiTest(MUX,199)@23
vStagei_uid200_lzcZ_uid50_fpSinPiTest_s <= vCount_uid197_lzcZ_uid50_fpSinPiTest_q;
vStagei_uid200_lzcZ_uid50_fpSinPiTest: PROCESS (vStagei_uid200_lzcZ_uid50_fpSinPiTest_s, en, reg_rVStage_uid196_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid200_lzcZ_uid50_fpSinPiTest_2_q, reg_vStage_uid198_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid200_lzcZ_uid50_fpSinPiTest_3_q)
BEGIN
CASE vStagei_uid200_lzcZ_uid50_fpSinPiTest_s IS
WHEN "0" => vStagei_uid200_lzcZ_uid50_fpSinPiTest_q <= reg_rVStage_uid196_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid200_lzcZ_uid50_fpSinPiTest_2_q;
WHEN "1" => vStagei_uid200_lzcZ_uid50_fpSinPiTest_q <= reg_vStage_uid198_lzcZ_uid50_fpSinPiTest_0_to_vStagei_uid200_lzcZ_uid50_fpSinPiTest_3_q;
WHEN OTHERS => vStagei_uid200_lzcZ_uid50_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid202_lzcZ_uid50_fpSinPiTest(BITSELECT,201)@23
rVStage_uid202_lzcZ_uid50_fpSinPiTest_in <= vStagei_uid200_lzcZ_uid50_fpSinPiTest_q;
rVStage_uid202_lzcZ_uid50_fpSinPiTest_b <= rVStage_uid202_lzcZ_uid50_fpSinPiTest_in(3 downto 2);
--vCount_uid203_lzcZ_uid50_fpSinPiTest(LOGICAL,202)@23
vCount_uid203_lzcZ_uid50_fpSinPiTest_a <= rVStage_uid202_lzcZ_uid50_fpSinPiTest_b;
vCount_uid203_lzcZ_uid50_fpSinPiTest_b <= leftShiftStage1Idx2Pad2_uid160_fxpX_uid40_fpSinPiTest_q;
vCount_uid203_lzcZ_uid50_fpSinPiTest_q <= "1" when vCount_uid203_lzcZ_uid50_fpSinPiTest_a = vCount_uid203_lzcZ_uid50_fpSinPiTest_b else "0";
--vStage_uid204_lzcZ_uid50_fpSinPiTest(BITSELECT,203)@23
vStage_uid204_lzcZ_uid50_fpSinPiTest_in <= vStagei_uid200_lzcZ_uid50_fpSinPiTest_q(1 downto 0);
vStage_uid204_lzcZ_uid50_fpSinPiTest_b <= vStage_uid204_lzcZ_uid50_fpSinPiTest_in(1 downto 0);
--vStagei_uid206_lzcZ_uid50_fpSinPiTest(MUX,205)@23
vStagei_uid206_lzcZ_uid50_fpSinPiTest_s <= vCount_uid203_lzcZ_uid50_fpSinPiTest_q;
vStagei_uid206_lzcZ_uid50_fpSinPiTest: PROCESS (vStagei_uid206_lzcZ_uid50_fpSinPiTest_s, en, rVStage_uid202_lzcZ_uid50_fpSinPiTest_b, vStage_uid204_lzcZ_uid50_fpSinPiTest_b)
BEGIN
CASE vStagei_uid206_lzcZ_uid50_fpSinPiTest_s IS
WHEN "0" => vStagei_uid206_lzcZ_uid50_fpSinPiTest_q <= rVStage_uid202_lzcZ_uid50_fpSinPiTest_b;
WHEN "1" => vStagei_uid206_lzcZ_uid50_fpSinPiTest_q <= vStage_uid204_lzcZ_uid50_fpSinPiTest_b;
WHEN OTHERS => vStagei_uid206_lzcZ_uid50_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid208_lzcZ_uid50_fpSinPiTest(BITSELECT,207)@23
rVStage_uid208_lzcZ_uid50_fpSinPiTest_in <= vStagei_uid206_lzcZ_uid50_fpSinPiTest_q;
rVStage_uid208_lzcZ_uid50_fpSinPiTest_b <= rVStage_uid208_lzcZ_uid50_fpSinPiTest_in(1 downto 1);
--vCount_uid209_lzcZ_uid50_fpSinPiTest(LOGICAL,208)@23
vCount_uid209_lzcZ_uid50_fpSinPiTest_a <= rVStage_uid208_lzcZ_uid50_fpSinPiTest_b;
vCount_uid209_lzcZ_uid50_fpSinPiTest_b <= GND_q;
vCount_uid209_lzcZ_uid50_fpSinPiTest_q <= "1" when vCount_uid209_lzcZ_uid50_fpSinPiTest_a = vCount_uid209_lzcZ_uid50_fpSinPiTest_b else "0";
--r_uid210_lzcZ_uid50_fpSinPiTest(BITJOIN,209)@23
r_uid210_lzcZ_uid50_fpSinPiTest_q <= ld_vCount_uid171_lzcZ_uid50_fpSinPiTest_q_to_r_uid210_lzcZ_uid50_fpSinPiTest_g_q & ld_vCount_uid179_lzcZ_uid50_fpSinPiTest_q_to_r_uid210_lzcZ_uid50_fpSinPiTest_f_q & reg_vCount_uid185_lzcZ_uid50_fpSinPiTest_0_to_r_uid210_lzcZ_uid50_fpSinPiTest_4_q & ld_vCount_uid191_lzcZ_uid50_fpSinPiTest_q_to_r_uid210_lzcZ_uid50_fpSinPiTest_d_q & vCount_uid197_lzcZ_uid50_fpSinPiTest_q & vCount_uid203_lzcZ_uid50_fpSinPiTest_q & vCount_uid209_lzcZ_uid50_fpSinPiTest_q;
--leftShiftStageSel6Dto5_uid218_alignedZ_uid51_fpSinPiTest(BITSELECT,217)@23
leftShiftStageSel6Dto5_uid218_alignedZ_uid51_fpSinPiTest_in <= r_uid210_lzcZ_uid50_fpSinPiTest_q;
leftShiftStageSel6Dto5_uid218_alignedZ_uid51_fpSinPiTest_b <= leftShiftStageSel6Dto5_uid218_alignedZ_uid51_fpSinPiTest_in(6 downto 5);
--leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest(MUX,218)@23
leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_s <= leftShiftStageSel6Dto5_uid218_alignedZ_uid51_fpSinPiTest_b;
leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest: PROCESS (leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_s, en, ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_q, leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_q, leftShiftStage0Idx2_uid216_alignedZ_uid51_fpSinPiTest_q, leftShiftStage0Idx2_uid216_alignedZ_uid51_fpSinPiTest_q)
BEGIN
CASE leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_s IS
WHEN "00" => leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_q <= ld_z_uid48_fpSinPiTest_q_to_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_q <= leftShiftStage0Idx1_uid215_alignedZ_uid51_fpSinPiTest_q;
WHEN "10" => leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_q <= leftShiftStage0Idx2_uid216_alignedZ_uid51_fpSinPiTest_q;
WHEN "11" => leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_q <= leftShiftStage0Idx2_uid216_alignedZ_uid51_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage040dto0_uid227_alignedZ_uid51_fpSinPiTest(BITSELECT,226)@23
LeftShiftStage040dto0_uid227_alignedZ_uid51_fpSinPiTest_in <= leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_q(40 downto 0);
LeftShiftStage040dto0_uid227_alignedZ_uid51_fpSinPiTest_b <= LeftShiftStage040dto0_uid227_alignedZ_uid51_fpSinPiTest_in(40 downto 0);
--leftShiftStage1Idx3_uid228_alignedZ_uid51_fpSinPiTest(BITJOIN,227)@23
leftShiftStage1Idx3_uid228_alignedZ_uid51_fpSinPiTest_q <= LeftShiftStage040dto0_uid227_alignedZ_uid51_fpSinPiTest_b & leftShiftStage1Idx3Pad24_uid226_alignedZ_uid51_fpSinPiTest_q;
--reg_leftShiftStage1Idx3_uid228_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_5(REG,393)@23
reg_leftShiftStage1Idx3_uid228_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid228_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid228_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_5_q <= leftShiftStage1Idx3_uid228_alignedZ_uid51_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage048dto0_uid224_alignedZ_uid51_fpSinPiTest(BITSELECT,223)@23
LeftShiftStage048dto0_uid224_alignedZ_uid51_fpSinPiTest_in <= leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_q(48 downto 0);
LeftShiftStage048dto0_uid224_alignedZ_uid51_fpSinPiTest_b <= LeftShiftStage048dto0_uid224_alignedZ_uid51_fpSinPiTest_in(48 downto 0);
--leftShiftStage1Idx2_uid225_alignedZ_uid51_fpSinPiTest(BITJOIN,224)@23
leftShiftStage1Idx2_uid225_alignedZ_uid51_fpSinPiTest_q <= LeftShiftStage048dto0_uid224_alignedZ_uid51_fpSinPiTest_b & zs_uid183_lzcZ_uid50_fpSinPiTest_q;
--reg_leftShiftStage1Idx2_uid225_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_4(REG,392)@23
reg_leftShiftStage1Idx2_uid225_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid225_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid225_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_4_q <= leftShiftStage1Idx2_uid225_alignedZ_uid51_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage056dto0_uid221_alignedZ_uid51_fpSinPiTest(BITSELECT,220)@23
LeftShiftStage056dto0_uid221_alignedZ_uid51_fpSinPiTest_in <= leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_q(56 downto 0);
LeftShiftStage056dto0_uid221_alignedZ_uid51_fpSinPiTest_b <= LeftShiftStage056dto0_uid221_alignedZ_uid51_fpSinPiTest_in(56 downto 0);
--leftShiftStage1Idx1_uid222_alignedZ_uid51_fpSinPiTest(BITJOIN,221)@23
leftShiftStage1Idx1_uid222_alignedZ_uid51_fpSinPiTest_q <= LeftShiftStage056dto0_uid221_alignedZ_uid51_fpSinPiTest_b & cstAllZWE_uid8_fpSinPiTest_q;
--reg_leftShiftStage1Idx1_uid222_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_3(REG,391)@23
reg_leftShiftStage1Idx1_uid222_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid222_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid222_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_3_q <= leftShiftStage1Idx1_uid222_alignedZ_uid51_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_2(REG,390)@23
reg_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_2_q <= leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid229_alignedZ_uid51_fpSinPiTest(BITSELECT,228)@23
leftShiftStageSel4Dto3_uid229_alignedZ_uid51_fpSinPiTest_in <= r_uid210_lzcZ_uid50_fpSinPiTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid229_alignedZ_uid51_fpSinPiTest_b <= leftShiftStageSel4Dto3_uid229_alignedZ_uid51_fpSinPiTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid229_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_1(REG,389)@23
reg_leftShiftStageSel4Dto3_uid229_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid229_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid229_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_1_q <= leftShiftStageSel4Dto3_uid229_alignedZ_uid51_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest(MUX,229)@24
leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_s <= reg_leftShiftStageSel4Dto3_uid229_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_1_q;
leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest: PROCESS (leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_s, en, reg_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_2_q, reg_leftShiftStage1Idx1_uid222_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_3_q, reg_leftShiftStage1Idx2_uid225_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_4_q, reg_leftShiftStage1Idx3_uid228_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_5_q)
BEGIN
CASE leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_s IS
WHEN "00" => leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_q <= reg_leftShiftStage0_uid219_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_q <= reg_leftShiftStage1Idx1_uid222_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_3_q;
WHEN "10" => leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_q <= reg_leftShiftStage1Idx2_uid225_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_4_q;
WHEN "11" => leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_q <= reg_leftShiftStage1Idx3_uid228_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_5_q;
WHEN OTHERS => leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid238_alignedZ_uid51_fpSinPiTest(BITSELECT,237)@24
LeftShiftStage158dto0_uid238_alignedZ_uid51_fpSinPiTest_in <= leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_q(58 downto 0);
LeftShiftStage158dto0_uid238_alignedZ_uid51_fpSinPiTest_b <= LeftShiftStage158dto0_uid238_alignedZ_uid51_fpSinPiTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid238_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage2Idx3_uid239_alignedZ_uid51_fpSinPiTest_b(DELAY,628)@24
ld_LeftShiftStage158dto0_uid238_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage2Idx3_uid239_alignedZ_uid51_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid238_alignedZ_uid51_fpSinPiTest_b, xout => ld_LeftShiftStage158dto0_uid238_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage2Idx3_uid239_alignedZ_uid51_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid239_alignedZ_uid51_fpSinPiTest(BITJOIN,238)@25
leftShiftStage2Idx3_uid239_alignedZ_uid51_fpSinPiTest_q <= ld_LeftShiftStage158dto0_uid238_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage2Idx3_uid239_alignedZ_uid51_fpSinPiTest_b_q & leftShiftStage2Idx3Pad6_uid237_alignedZ_uid51_fpSinPiTest_q;
--LeftShiftStage160dto0_uid235_alignedZ_uid51_fpSinPiTest(BITSELECT,234)@24
LeftShiftStage160dto0_uid235_alignedZ_uid51_fpSinPiTest_in <= leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_q(60 downto 0);
LeftShiftStage160dto0_uid235_alignedZ_uid51_fpSinPiTest_b <= LeftShiftStage160dto0_uid235_alignedZ_uid51_fpSinPiTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid235_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage2Idx2_uid236_alignedZ_uid51_fpSinPiTest_b(DELAY,626)@24
ld_LeftShiftStage160dto0_uid235_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage2Idx2_uid236_alignedZ_uid51_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid235_alignedZ_uid51_fpSinPiTest_b, xout => ld_LeftShiftStage160dto0_uid235_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage2Idx2_uid236_alignedZ_uid51_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid236_alignedZ_uid51_fpSinPiTest(BITJOIN,235)@25
leftShiftStage2Idx2_uid236_alignedZ_uid51_fpSinPiTest_q <= ld_LeftShiftStage160dto0_uid235_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage2Idx2_uid236_alignedZ_uid51_fpSinPiTest_b_q & leftShiftStage0Idx1Pad4_uid146_fxpX_uid40_fpSinPiTest_q;
--LeftShiftStage162dto0_uid232_alignedZ_uid51_fpSinPiTest(BITSELECT,231)@24
LeftShiftStage162dto0_uid232_alignedZ_uid51_fpSinPiTest_in <= leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_q(62 downto 0);
LeftShiftStage162dto0_uid232_alignedZ_uid51_fpSinPiTest_b <= LeftShiftStage162dto0_uid232_alignedZ_uid51_fpSinPiTest_in(62 downto 0);
--ld_LeftShiftStage162dto0_uid232_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage2Idx1_uid233_alignedZ_uid51_fpSinPiTest_b(DELAY,624)@24
ld_LeftShiftStage162dto0_uid232_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage2Idx1_uid233_alignedZ_uid51_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage162dto0_uid232_alignedZ_uid51_fpSinPiTest_b, xout => ld_LeftShiftStage162dto0_uid232_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage2Idx1_uid233_alignedZ_uid51_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid233_alignedZ_uid51_fpSinPiTest(BITJOIN,232)@25
leftShiftStage2Idx1_uid233_alignedZ_uid51_fpSinPiTest_q <= ld_LeftShiftStage162dto0_uid232_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage2Idx1_uid233_alignedZ_uid51_fpSinPiTest_b_q & leftShiftStage1Idx2Pad2_uid160_fxpX_uid40_fpSinPiTest_q;
--reg_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_2(REG,395)@24
reg_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_2_q <= leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest(BITSELECT,239)@23
leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_in <= r_uid210_lzcZ_uid50_fpSinPiTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_b <= leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_in(2 downto 1);
--ld_leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_b_to_reg_leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_1_a(DELAY,789)@23
ld_leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_b_to_reg_leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_b, xout => ld_leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_b_to_reg_leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_1(REG,394)@24
reg_leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_1_q <= ld_leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_b_to_reg_leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest(MUX,240)@25
leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_s <= reg_leftShiftStageSel2Dto1_uid240_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_1_q;
leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest: PROCESS (leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_s, en, reg_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_2_q, leftShiftStage2Idx1_uid233_alignedZ_uid51_fpSinPiTest_q, leftShiftStage2Idx2_uid236_alignedZ_uid51_fpSinPiTest_q, leftShiftStage2Idx3_uid239_alignedZ_uid51_fpSinPiTest_q)
BEGIN
CASE leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_s IS
WHEN "00" => leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_q <= reg_leftShiftStage1_uid230_alignedZ_uid51_fpSinPiTest_0_to_leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_2_q;
WHEN "01" => leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_q <= leftShiftStage2Idx1_uid233_alignedZ_uid51_fpSinPiTest_q;
WHEN "10" => leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_q <= leftShiftStage2Idx2_uid236_alignedZ_uid51_fpSinPiTest_q;
WHEN "11" => leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_q <= leftShiftStage2Idx3_uid239_alignedZ_uid51_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid245_alignedZ_uid51_fpSinPiTest(BITSELECT,244)@23
leftShiftStageSel0Dto0_uid245_alignedZ_uid51_fpSinPiTest_in <= r_uid210_lzcZ_uid50_fpSinPiTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid245_alignedZ_uid51_fpSinPiTest_b <= leftShiftStageSel0Dto0_uid245_alignedZ_uid51_fpSinPiTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid245_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage3_uid246_alignedZ_uid51_fpSinPiTest_b(DELAY,638)@23
ld_leftShiftStageSel0Dto0_uid245_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage3_uid246_alignedZ_uid51_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid245_alignedZ_uid51_fpSinPiTest_b, xout => ld_leftShiftStageSel0Dto0_uid245_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage3_uid246_alignedZ_uid51_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid246_alignedZ_uid51_fpSinPiTest(MUX,245)@25
leftShiftStage3_uid246_alignedZ_uid51_fpSinPiTest_s <= ld_leftShiftStageSel0Dto0_uid245_alignedZ_uid51_fpSinPiTest_b_to_leftShiftStage3_uid246_alignedZ_uid51_fpSinPiTest_b_q;
leftShiftStage3_uid246_alignedZ_uid51_fpSinPiTest: PROCESS (leftShiftStage3_uid246_alignedZ_uid51_fpSinPiTest_s, en, leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_q, leftShiftStage3Idx1_uid244_alignedZ_uid51_fpSinPiTest_q)
BEGIN
CASE leftShiftStage3_uid246_alignedZ_uid51_fpSinPiTest_s IS
WHEN "0" => leftShiftStage3_uid246_alignedZ_uid51_fpSinPiTest_q <= leftShiftStage2_uid241_alignedZ_uid51_fpSinPiTest_q;
WHEN "1" => leftShiftStage3_uid246_alignedZ_uid51_fpSinPiTest_q <= leftShiftStage3Idx1_uid244_alignedZ_uid51_fpSinPiTest_q;
WHEN OTHERS => leftShiftStage3_uid246_alignedZ_uid51_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--pHigh_uid53_fpSinPiTest(BITSELECT,52)@25
pHigh_uid53_fpSinPiTest_in <= leftShiftStage3_uid246_alignedZ_uid51_fpSinPiTest_q;
pHigh_uid53_fpSinPiTest_b <= pHigh_uid53_fpSinPiTest_in(64 downto 39);
--reg_pHigh_uid53_fpSinPiTest_0_to_p_uid54_fpSinPiTest_2(REG,397)@25
reg_pHigh_uid53_fpSinPiTest_0_to_p_uid54_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pHigh_uid53_fpSinPiTest_0_to_p_uid54_fpSinPiTest_2_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pHigh_uid53_fpSinPiTest_0_to_p_uid54_fpSinPiTest_2_q <= pHigh_uid53_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--reg_sinXIsXRR_uid35_fpSinPiTest_2_to_p_uid54_fpSinPiTest_1(REG,396)@14
reg_sinXIsXRR_uid35_fpSinPiTest_2_to_p_uid54_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid35_fpSinPiTest_2_to_p_uid54_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid35_fpSinPiTest_2_to_p_uid54_fpSinPiTest_1_q <= sinXIsXRR_uid35_fpSinPiTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_sinXIsXRR_uid35_fpSinPiTest_2_to_p_uid54_fpSinPiTest_1_q_to_p_uid54_fpSinPiTest_b(DELAY,452)@15
ld_reg_sinXIsXRR_uid35_fpSinPiTest_2_to_p_uid54_fpSinPiTest_1_q_to_p_uid54_fpSinPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => reg_sinXIsXRR_uid35_fpSinPiTest_2_to_p_uid54_fpSinPiTest_1_q, xout => ld_reg_sinXIsXRR_uid35_fpSinPiTest_2_to_p_uid54_fpSinPiTest_1_q_to_p_uid54_fpSinPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--p_uid54_fpSinPiTest(MUX,53)@26
p_uid54_fpSinPiTest_s <= ld_reg_sinXIsXRR_uid35_fpSinPiTest_2_to_p_uid54_fpSinPiTest_1_q_to_p_uid54_fpSinPiTest_b_q;
p_uid54_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p_uid54_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE p_uid54_fpSinPiTest_s IS
WHEN "0" => p_uid54_fpSinPiTest_q <= reg_pHigh_uid53_fpSinPiTest_0_to_p_uid54_fpSinPiTest_2_q;
WHEN "1" => p_uid54_fpSinPiTest_q <= cPi_uid52_fpSinPiTest_q;
WHEN OTHERS => p_uid54_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_inputreg(DELAY,835)
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => p_uid54_fpSinPiTest_q, xout => ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem(DUALMEM,836)
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_ia <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_inputreg_q;
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_aa <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdreg_q;
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_ab <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_rdmux_q;
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 1,
numwords_a => 2,
width_b => 26,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_iq,
address_a => ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_aa,
data_a => ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_ia
);
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_reset0 <= areset;
ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_q <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_iq(25 downto 0);
--mul2xSinRes_uid67_fpSinPiTest(MULT,66)@31
mul2xSinRes_uid67_fpSinPiTest_pr <= UNSIGNED(mul2xSinRes_uid67_fpSinPiTest_a) * UNSIGNED(mul2xSinRes_uid67_fpSinPiTest_b);
mul2xSinRes_uid67_fpSinPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid67_fpSinPiTest_a <= (others => '0');
mul2xSinRes_uid67_fpSinPiTest_b <= (others => '0');
mul2xSinRes_uid67_fpSinPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid67_fpSinPiTest_a <= ld_p_uid54_fpSinPiTest_q_to_mul2xSinRes_uid67_fpSinPiTest_a_replace_mem_q;
mul2xSinRes_uid67_fpSinPiTest_b <= multSecondOperand_uid66_fpSinPiTest_q;
mul2xSinRes_uid67_fpSinPiTest_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid67_fpSinPiTest_pr);
END IF;
END IF;
END PROCESS;
mul2xSinRes_uid67_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid67_fpSinPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mul2xSinRes_uid67_fpSinPiTest_q <= mul2xSinRes_uid67_fpSinPiTest_s1;
END IF;
END IF;
END PROCESS;
--normBit_uid68_fpSinPiTest(BITSELECT,67)@34
normBit_uid68_fpSinPiTest_in <= mul2xSinRes_uid67_fpSinPiTest_q;
normBit_uid68_fpSinPiTest_b <= normBit_uid68_fpSinPiTest_in(51 downto 51);
--join_uid73_fpSinPiTest(BITJOIN,72)@34
join_uid73_fpSinPiTest_q <= reg_sinXIsXRR_uid35_fpSinPiTest_2_to_join_uid73_fpSinPiTest_1_q & normBit_uid68_fpSinPiTest_b;
--cstAllZWF_uid7_fpSinPiTest(CONSTANT,6)
cstAllZWF_uid7_fpSinPiTest_q <= "00000000000000000000000";
--rndOp_uid74_uid75_fpSinPiTest(BITJOIN,74)@34
rndOp_uid74_uid75_fpSinPiTest_q <= join_uid73_fpSinPiTest_q & cstAllZWF_uid7_fpSinPiTest_q & VCC_q;
--ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_nor(LOGICAL,856)
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_nor_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q;
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_nor_b <= ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_nor_q <= not (ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_nor_a or ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_nor_b);
--ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_mem_top(CONSTANT,852)
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_mem_top_q <= "0110";
--ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_cmp(LOGICAL,853)
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_cmp_a <= ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_mem_top_q;
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdmux_q);
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_cmp_q <= "1" when ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_cmp_a = ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_cmp_b else "0";
--ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_cmpReg(REG,854)
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_cmpReg_q <= ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_sticky_ena(REG,857)
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_nor_q = "1") THEN
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_sticky_ena_q <= ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_enaAnd(LOGICAL,858)
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_enaAnd_a <= ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_sticky_ena_q;
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_enaAnd_b <= en;
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_enaAnd_q <= ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_enaAnd_a and ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_enaAnd_b;
--ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_nor(LOGICAL,819)
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_nor_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q;
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_nor_b <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_sticky_ena_q;
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_nor_q <= not (ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_nor_a or ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_nor_b);
--ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_sticky_ena(REG,820)
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_nor_q = "1") THEN
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_sticky_ena_q <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_enaAnd(LOGICAL,821)
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_enaAnd_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_sticky_ena_q;
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_enaAnd_b <= en;
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_enaAnd_q <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_enaAnd_a and ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_enaAnd_b;
--ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_inputreg(DELAY,809)
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expXRR_uid32_fpSinPiTest_b, xout => ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem(DUALMEM,810)
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_ia <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_inputreg_q;
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_aa <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdreg_q;
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_ab <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_rdmux_q;
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_iq,
address_a => ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_aa,
data_a => ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_ia
);
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_reset0 <= areset;
ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_q <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_iq(7 downto 0);
--signExtExpXRR_uid57_fpSinPiTest(BITJOIN,56)@24
signExtExpXRR_uid57_fpSinPiTest_q <= GND_q & ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_replace_mem_q;
--reg_r_uid210_lzcZ_uid50_fpSinPiTest_0_to_expHardCase_uid56_fpSinPiTest_1(REG,407)@23
reg_r_uid210_lzcZ_uid50_fpSinPiTest_0_to_expHardCase_uid56_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid210_lzcZ_uid50_fpSinPiTest_0_to_expHardCase_uid56_fpSinPiTest_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid210_lzcZ_uid50_fpSinPiTest_0_to_expHardCase_uid56_fpSinPiTest_1_q <= r_uid210_lzcZ_uid50_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--expHardCase_uid56_fpSinPiTest(SUB,55)@24
expHardCase_uid56_fpSinPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid55_fpSinPiTest_q);
expHardCase_uid56_fpSinPiTest_b <= STD_LOGIC_VECTOR("00" & reg_r_uid210_lzcZ_uid50_fpSinPiTest_0_to_expHardCase_uid56_fpSinPiTest_1_q);
expHardCase_uid56_fpSinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid56_fpSinPiTest_a) - UNSIGNED(expHardCase_uid56_fpSinPiTest_b));
expHardCase_uid56_fpSinPiTest_q <= expHardCase_uid56_fpSinPiTest_o(8 downto 0);
--ld_sinXIsXRR_uid35_fpSinPiTest_n_to_reg_sinXIsXRR_uid35_fpSinPiTest_2_to_expP_uid59_fpSinPiTest_1_a(DELAY,803)@14
ld_sinXIsXRR_uid35_fpSinPiTest_n_to_reg_sinXIsXRR_uid35_fpSinPiTest_2_to_expP_uid59_fpSinPiTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 9 )
PORT MAP ( xin => sinXIsXRR_uid35_fpSinPiTest_n, xout => ld_sinXIsXRR_uid35_fpSinPiTest_n_to_reg_sinXIsXRR_uid35_fpSinPiTest_2_to_expP_uid59_fpSinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sinXIsXRR_uid35_fpSinPiTest_2_to_expP_uid59_fpSinPiTest_1(REG,408)@23
reg_sinXIsXRR_uid35_fpSinPiTest_2_to_expP_uid59_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid35_fpSinPiTest_2_to_expP_uid59_fpSinPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid35_fpSinPiTest_2_to_expP_uid59_fpSinPiTest_1_q <= ld_sinXIsXRR_uid35_fpSinPiTest_n_to_reg_sinXIsXRR_uid35_fpSinPiTest_2_to_expP_uid59_fpSinPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--expP_uid59_fpSinPiTest(MUX,58)@24
expP_uid59_fpSinPiTest_s <= reg_sinXIsXRR_uid35_fpSinPiTest_2_to_expP_uid59_fpSinPiTest_1_q;
expP_uid59_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expP_uid59_fpSinPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expP_uid59_fpSinPiTest_s IS
WHEN "0" => expP_uid59_fpSinPiTest_q <= expHardCase_uid56_fpSinPiTest_q;
WHEN "1" => expP_uid59_fpSinPiTest_q <= signExtExpXRR_uid57_fpSinPiTest_q;
WHEN OTHERS => expP_uid59_fpSinPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_inputreg(DELAY,846)
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => expP_uid59_fpSinPiTest_q, xout => ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt(COUNTER,848)
-- every=1, low=0, high=6, step=1, init=1
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_i = 5 THEN
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_eq = '1') THEN
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_i - 6;
ELSE
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_i <= ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_i,3));
--ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdreg(REG,849)
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdreg_q <= ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdmux(MUX,850)
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdmux_s <= en;
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdmux: PROCESS (ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdmux_s, ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdreg_q, ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdmux_q <= ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem(DUALMEM,847)
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_ia <= ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_inputreg_q;
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_aa <= ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdreg_q;
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_ab <= ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_rdmux_q;
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 9,
widthad_a => 3,
numwords_a => 7,
width_b => 9,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_iq,
address_a => ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_aa,
data_a => ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_ia
);
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_reset0 <= areset;
ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_q <= ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_iq(8 downto 0);
--highRes_uid69_fpSinPiTest(BITSELECT,68)@34
highRes_uid69_fpSinPiTest_in <= mul2xSinRes_uid67_fpSinPiTest_q(50 downto 0);
highRes_uid69_fpSinPiTest_b <= highRes_uid69_fpSinPiTest_in(50 downto 27);
--lowRes_uid70_fpSinPiTest(BITSELECT,69)@34
lowRes_uid70_fpSinPiTest_in <= mul2xSinRes_uid67_fpSinPiTest_q(49 downto 0);
lowRes_uid70_fpSinPiTest_b <= lowRes_uid70_fpSinPiTest_in(49 downto 26);
--fracRCompPreRnd_uid71_fpSinPiTest(MUX,70)@34
fracRCompPreRnd_uid71_fpSinPiTest_s <= normBit_uid68_fpSinPiTest_b;
fracRCompPreRnd_uid71_fpSinPiTest: PROCESS (fracRCompPreRnd_uid71_fpSinPiTest_s, en, lowRes_uid70_fpSinPiTest_b, highRes_uid69_fpSinPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid71_fpSinPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid71_fpSinPiTest_q <= lowRes_uid70_fpSinPiTest_b;
WHEN "1" => fracRCompPreRnd_uid71_fpSinPiTest_q <= highRes_uid69_fpSinPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid71_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest(BITJOIN,71)@34
expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_q <= ld_expP_uid59_fpSinPiTest_q_to_expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_b_replace_mem_q & fracRCompPreRnd_uid71_fpSinPiTest_q;
--expRCompFracRComp_uid76_fpSinPiTest(ADD,75)@34
expRCompFracRComp_uid76_fpSinPiTest_a <= STD_LOGIC_VECTOR((34 downto 33 => expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_q(32)) & expRCompFracRCompPreRnd_uid72_uid72_fpSinPiTest_q);
expRCompFracRComp_uid76_fpSinPiTest_b <= STD_LOGIC_VECTOR('0' & "00000000" & rndOp_uid74_uid75_fpSinPiTest_q);
expRCompFracRComp_uid76_fpSinPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expRCompFracRComp_uid76_fpSinPiTest_a) + SIGNED(expRCompFracRComp_uid76_fpSinPiTest_b));
expRCompFracRComp_uid76_fpSinPiTest_q <= expRCompFracRComp_uid76_fpSinPiTest_o(33 downto 0);
--expRCompE_uid78_fpSinPiTest(BITSELECT,77)@34
expRCompE_uid78_fpSinPiTest_in <= expRCompFracRComp_uid76_fpSinPiTest_q(32 downto 0);
expRCompE_uid78_fpSinPiTest_b <= expRCompE_uid78_fpSinPiTest_in(32 downto 24);
--expRComp_uid79_fpSinPiTest(BITSELECT,78)@34
expRComp_uid79_fpSinPiTest_in <= expRCompE_uid78_fpSinPiTest_b(7 downto 0);
expRComp_uid79_fpSinPiTest_b <= expRComp_uid79_fpSinPiTest_in(7 downto 0);
--reg_expRComp_uid79_fpSinPiTest_0_to_expRPostExc_uid92_fpSinPiTest_2(REG,413)@34
reg_expRComp_uid79_fpSinPiTest_0_to_expRPostExc_uid92_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRComp_uid79_fpSinPiTest_0_to_expRPostExc_uid92_fpSinPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRComp_uid79_fpSinPiTest_0_to_expRPostExc_uid92_fpSinPiTest_2_q <= expRComp_uid79_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_expRComp_uid79_fpSinPiTest_0_to_expRPostExc_uid92_fpSinPiTest_2_q_to_expRPostExc_uid92_fpSinPiTest_c(DELAY,499)@35
ld_reg_expRComp_uid79_fpSinPiTest_0_to_expRPostExc_uid92_fpSinPiTest_2_q_to_expRPostExc_uid92_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => reg_expRComp_uid79_fpSinPiTest_0_to_expRPostExc_uid92_fpSinPiTest_2_q, xout => ld_reg_expRComp_uid79_fpSinPiTest_0_to_expRPostExc_uid92_fpSinPiTest_2_q_to_expRPostExc_uid92_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_nor(LOGICAL,908)
ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_nor_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q;
ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_nor_b <= ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_sticky_ena_q;
ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_nor_q <= not (ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_nor_a or ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_nor_b);
--ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_mem_top(CONSTANT,878)
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_mem_top_q <= "0100000";
--ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmp(LOGICAL,879)
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmp_a <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_mem_top_q;
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdmux_q);
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmp_q <= "1" when ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmp_a = ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmp_b else "0";
--ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmpReg(REG,880)
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmpReg_q <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_sticky_ena(REG,909)
ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_nor_q = "1") THEN
ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_sticky_ena_q <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_enaAnd(LOGICAL,910)
ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_enaAnd_a <= ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_sticky_ena_q;
ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_enaAnd_b <= en;
ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_enaAnd_q <= ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_enaAnd_a and ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_enaAnd_b;
--frac_uid13_fpSinPiTest(BITSELECT,12)@0
frac_uid13_fpSinPiTest_in <= a(22 downto 0);
frac_uid13_fpSinPiTest_b <= frac_uid13_fpSinPiTest_in(22 downto 0);
--fracXIsZero_uid14_fpSinPiTest(LOGICAL,13)@0
fracXIsZero_uid14_fpSinPiTest_a <= frac_uid13_fpSinPiTest_b;
fracXIsZero_uid14_fpSinPiTest_b <= cstAllZWF_uid7_fpSinPiTest_q;
fracXIsZero_uid14_fpSinPiTest_q <= "1" when fracXIsZero_uid14_fpSinPiTest_a = fracXIsZero_uid14_fpSinPiTest_b else "0";
--expXIsMax_uid12_fpSinPiTest(LOGICAL,11)@0
expXIsMax_uid12_fpSinPiTest_a <= exp_uid9_fpSinPiTest_b;
expXIsMax_uid12_fpSinPiTest_b <= cstAllOWE_uid6_fpSinPiTest_q;
expXIsMax_uid12_fpSinPiTest_q <= "1" when expXIsMax_uid12_fpSinPiTest_a = expXIsMax_uid12_fpSinPiTest_b else "0";
--exc_I_uid15_fpSinPiTest(LOGICAL,14)@0
exc_I_uid15_fpSinPiTest_a <= expXIsMax_uid12_fpSinPiTest_q;
exc_I_uid15_fpSinPiTest_b <= fracXIsZero_uid14_fpSinPiTest_q;
exc_I_uid15_fpSinPiTest_q <= exc_I_uid15_fpSinPiTest_a and exc_I_uid15_fpSinPiTest_b;
--InvFracXIsZero_uid16_fpSinPiTest(LOGICAL,15)@0
InvFracXIsZero_uid16_fpSinPiTest_a <= fracXIsZero_uid14_fpSinPiTest_q;
InvFracXIsZero_uid16_fpSinPiTest_q <= not InvFracXIsZero_uid16_fpSinPiTest_a;
--exc_N_uid17_fpSinPiTest(LOGICAL,16)@0
exc_N_uid17_fpSinPiTest_a <= expXIsMax_uid12_fpSinPiTest_q;
exc_N_uid17_fpSinPiTest_b <= InvFracXIsZero_uid16_fpSinPiTest_q;
exc_N_uid17_fpSinPiTest_q <= exc_N_uid17_fpSinPiTest_a and exc_N_uid17_fpSinPiTest_b;
--excRNaN_uid83_fpSinPiTest(LOGICAL,82)@0
excRNaN_uid83_fpSinPiTest_a <= exc_N_uid17_fpSinPiTest_q;
excRNaN_uid83_fpSinPiTest_b <= exc_I_uid15_fpSinPiTest_q;
excRNaN_uid83_fpSinPiTest_q <= excRNaN_uid83_fpSinPiTest_a or excRNaN_uid83_fpSinPiTest_b;
--ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_inputreg(DELAY,898)
ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => excRNaN_uid83_fpSinPiTest_q, xout => ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt(COUNTER,874)
-- every=1, low=0, high=32, step=1, init=1
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_i = 31 THEN
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_eq = '1') THEN
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_i <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_i - 32;
ELSE
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_i <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_i,6));
--ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdreg(REG,875)
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdreg_q <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdmux(MUX,876)
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdmux_s <= en;
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdmux: PROCESS (ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdmux_s, ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdreg_q, ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdmux_q <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdreg_q;
WHEN "1" => ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdmux_q <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem(DUALMEM,899)
ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_ia <= ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_inputreg_q;
ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_aa <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdreg_q;
ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_ab <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdmux_q;
ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_iq,
address_a => ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_aa,
data_a => ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_ia
);
ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_reset0 <= areset;
ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_q <= ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_iq(0 downto 0);
--reg_expRCompE_uid78_fpSinPiTest_0_to_udf_uid80_fpSinPiTest_1(REG,410)@34
reg_expRCompE_uid78_fpSinPiTest_0_to_udf_uid80_fpSinPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRCompE_uid78_fpSinPiTest_0_to_udf_uid80_fpSinPiTest_1_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRCompE_uid78_fpSinPiTest_0_to_udf_uid80_fpSinPiTest_1_q <= expRCompE_uid78_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--udf_uid80_fpSinPiTest(COMPARE,79)@35
udf_uid80_fpSinPiTest_cin <= GND_q;
udf_uid80_fpSinPiTest_a <= STD_LOGIC_VECTOR('0' & "000000000" & GND_q) & '0';
udf_uid80_fpSinPiTest_b <= STD_LOGIC_VECTOR((10 downto 9 => reg_expRCompE_uid78_fpSinPiTest_0_to_udf_uid80_fpSinPiTest_1_q(8)) & reg_expRCompE_uid78_fpSinPiTest_0_to_udf_uid80_fpSinPiTest_1_q) & udf_uid80_fpSinPiTest_cin(0);
udf_uid80_fpSinPiTest_o <= STD_LOGIC_VECTOR(SIGNED(udf_uid80_fpSinPiTest_a) - SIGNED(udf_uid80_fpSinPiTest_b));
udf_uid80_fpSinPiTest_n(0) <= not udf_uid80_fpSinPiTest_o(11);
--ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_nor(LOGICAL,869)
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_nor_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q;
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_nor_b <= ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_sticky_ena_q;
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_nor_q <= not (ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_nor_a or ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_nor_b);
--ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_mem_top(CONSTANT,865)
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_mem_top_q <= "011111";
--ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_cmp(LOGICAL,866)
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_cmp_a <= ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_mem_top_q;
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdmux_q);
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_cmp_q <= "1" when ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_cmp_a = ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_cmp_b else "0";
--ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_cmpReg(REG,867)
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_cmpReg_q <= ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_sticky_ena(REG,870)
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_nor_q = "1") THEN
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_sticky_ena_q <= ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_enaAnd(LOGICAL,871)
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_enaAnd_a <= ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_sticky_ena_q;
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_enaAnd_b <= en;
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_enaAnd_q <= ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_enaAnd_a and ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_enaAnd_b;
--InvExc_N_uid18_fpSinPiTest(LOGICAL,17)@0
InvExc_N_uid18_fpSinPiTest_a <= exc_N_uid17_fpSinPiTest_q;
InvExc_N_uid18_fpSinPiTest_q <= not InvExc_N_uid18_fpSinPiTest_a;
--InvExc_I_uid19_fpSinPiTest(LOGICAL,18)@0
InvExc_I_uid19_fpSinPiTest_a <= exc_I_uid15_fpSinPiTest_q;
InvExc_I_uid19_fpSinPiTest_q <= not InvExc_I_uid19_fpSinPiTest_a;
--expXIsZero_uid10_fpSinPiTest(LOGICAL,9)@0
expXIsZero_uid10_fpSinPiTest_a <= exp_uid9_fpSinPiTest_b;
expXIsZero_uid10_fpSinPiTest_b <= cstAllZWE_uid8_fpSinPiTest_q;
expXIsZero_uid10_fpSinPiTest_q <= "1" when expXIsZero_uid10_fpSinPiTest_a = expXIsZero_uid10_fpSinPiTest_b else "0";
--InvExpXIsZero_uid20_fpSinPiTest(LOGICAL,19)@0
InvExpXIsZero_uid20_fpSinPiTest_a <= expXIsZero_uid10_fpSinPiTest_q;
InvExpXIsZero_uid20_fpSinPiTest_q <= not InvExpXIsZero_uid20_fpSinPiTest_a;
--exc_R_uid21_fpSinPiTest(LOGICAL,20)@0
exc_R_uid21_fpSinPiTest_a <= InvExpXIsZero_uid20_fpSinPiTest_q;
exc_R_uid21_fpSinPiTest_b <= InvExc_I_uid19_fpSinPiTest_q;
exc_R_uid21_fpSinPiTest_c <= InvExc_N_uid18_fpSinPiTest_q;
exc_R_uid21_fpSinPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
exc_R_uid21_fpSinPiTest_q <= (others => '0');
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
exc_R_uid21_fpSinPiTest_q <= exc_R_uid21_fpSinPiTest_a and exc_R_uid21_fpSinPiTest_b and exc_R_uid21_fpSinPiTest_c;
END IF;
END IF;
END PROCESS;
--ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_inputreg(DELAY,859)
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_R_uid21_fpSinPiTest_q, xout => ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdcnt(COUNTER,861)
-- every=1, low=0, high=31, step=1, init=1
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdcnt_i <= ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdcnt_i,5));
--ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdreg(REG,862)
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdreg_q <= ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdmux(MUX,863)
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdmux_s <= en;
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdmux: PROCESS (ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdmux_s, ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdreg_q, ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdmux_q <= ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdreg_q;
WHEN "1" => ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdmux_q <= ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem(DUALMEM,860)
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_ia <= ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_inputreg_q;
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_aa <= ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdreg_q;
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_ab <= ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_rdmux_q;
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 5,
numwords_a => 32,
width_b => 1,
widthad_b => 5,
numwords_b => 32,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_iq,
address_a => ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_aa,
data_a => ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_ia
);
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_reset0 <= areset;
ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_q <= ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_iq(0 downto 0);
--xRegAndUdf_uid81_fpSinPiTest(LOGICAL,80)@35
xRegAndUdf_uid81_fpSinPiTest_a <= ld_exc_R_uid21_fpSinPiTest_q_to_xRegAndUdf_uid81_fpSinPiTest_a_replace_mem_q;
xRegAndUdf_uid81_fpSinPiTest_b <= udf_uid80_fpSinPiTest_n;
xRegAndUdf_uid81_fpSinPiTest_q <= xRegAndUdf_uid81_fpSinPiTest_a and xRegAndUdf_uid81_fpSinPiTest_b;
--ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_nor(LOGICAL,882)
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_nor_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q;
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_nor_b <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_sticky_ena_q;
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_nor_q <= not (ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_nor_a or ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_nor_b);
--ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_sticky_ena(REG,883)
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_nor_q = "1") THEN
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_sticky_ena_q <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_enaAnd(LOGICAL,884)
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_enaAnd_a <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_sticky_ena_q;
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_enaAnd_b <= en;
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_enaAnd_q <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_enaAnd_a and ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_enaAnd_b;
--ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_inputreg(DELAY,872)
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid10_fpSinPiTest_q, xout => ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem(DUALMEM,873)
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_ia <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_inputreg_q;
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_aa <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdreg_q;
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_ab <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdmux_q;
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_iq,
address_a => ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_aa,
data_a => ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_ia
);
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_reset0 <= areset;
ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_q <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_iq(0 downto 0);
--excRZero_uid82_fpSinPiTest(LOGICAL,81)@35
excRZero_uid82_fpSinPiTest_a <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_mem_q;
excRZero_uid82_fpSinPiTest_b <= xRegAndUdf_uid81_fpSinPiTest_q;
excRZero_uid82_fpSinPiTest_q <= excRZero_uid82_fpSinPiTest_a or excRZero_uid82_fpSinPiTest_b;
--ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_nor(LOGICAL,895)
ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_nor_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q;
ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_nor_b <= ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_sticky_ena_q;
ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_nor_q <= not (ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_nor_a or ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_nor_b);
--ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_sticky_ena(REG,896)
ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_nor_q = "1") THEN
ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_sticky_ena_q <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_enaAnd(LOGICAL,897)
ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_enaAnd_a <= ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_sticky_ena_q;
ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_enaAnd_b <= en;
ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_enaAnd_q <= ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_enaAnd_a and ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_enaAnd_b;
--ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_inputreg(DELAY,885)
ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => sinXIsX_uid34_fpSinPiTest_n, xout => ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem(DUALMEM,886)
ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_ia <= ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_inputreg_q;
ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_aa <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdreg_q;
ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_ab <= ld_expXIsZero_uid10_fpSinPiTest_q_to_excRZero_uid82_fpSinPiTest_a_replace_rdmux_q;
ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 33,
width_b => 1,
widthad_b => 6,
numwords_b => 33,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_iq,
address_a => ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_aa,
data_a => ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_ia
);
ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_reset0 <= areset;
ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_q <= ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_iq(0 downto 0);
--excSelBits_uid84_fpSinPiTest(BITJOIN,83)@35
excSelBits_uid84_fpSinPiTest_q <= ld_excRNaN_uid83_fpSinPiTest_q_to_excSelBits_uid84_fpSinPiTest_c_replace_mem_q & excRZero_uid82_fpSinPiTest_q & ld_sinXIsX_uid34_fpSinPiTest_n_to_excSelBits_uid84_fpSinPiTest_a_replace_mem_q;
--reg_excSelBits_uid84_fpSinPiTest_0_to_excSel_uid85_fpSinPiTest_0(REG,411)@35
reg_excSelBits_uid84_fpSinPiTest_0_to_excSel_uid85_fpSinPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid84_fpSinPiTest_0_to_excSel_uid85_fpSinPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid84_fpSinPiTest_0_to_excSel_uid85_fpSinPiTest_0_q <= excSelBits_uid84_fpSinPiTest_q;
END IF;
END IF;
END PROCESS;
--excSel_uid85_fpSinPiTest(LOOKUP,84)@36
excSel_uid85_fpSinPiTest: PROCESS (reg_excSelBits_uid84_fpSinPiTest_0_to_excSel_uid85_fpSinPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid84_fpSinPiTest_0_to_excSel_uid85_fpSinPiTest_0_q) IS
WHEN "000" => excSel_uid85_fpSinPiTest_q <= "00";
WHEN "001" => excSel_uid85_fpSinPiTest_q <= "01";
WHEN "010" => excSel_uid85_fpSinPiTest_q <= "10";
WHEN "011" => excSel_uid85_fpSinPiTest_q <= "10";
WHEN "100" => excSel_uid85_fpSinPiTest_q <= "11";
WHEN "101" => excSel_uid85_fpSinPiTest_q <= "11";
WHEN "110" => excSel_uid85_fpSinPiTest_q <= "00";
WHEN "111" => excSel_uid85_fpSinPiTest_q <= "00";
WHEN OTHERS =>
excSel_uid85_fpSinPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid92_fpSinPiTest(MUX,91)@36
expRPostExc_uid92_fpSinPiTest_s <= excSel_uid85_fpSinPiTest_q;
expRPostExc_uid92_fpSinPiTest: PROCESS (expRPostExc_uid92_fpSinPiTest_s, en, ld_reg_expRComp_uid79_fpSinPiTest_0_to_expRPostExc_uid92_fpSinPiTest_2_q_to_expRPostExc_uid92_fpSinPiTest_c_q, ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_q, cstAllZWE_uid8_fpSinPiTest_q, cstAllOWE_uid6_fpSinPiTest_q)
BEGIN
CASE expRPostExc_uid92_fpSinPiTest_s IS
WHEN "00" => expRPostExc_uid92_fpSinPiTest_q <= ld_reg_expRComp_uid79_fpSinPiTest_0_to_expRPostExc_uid92_fpSinPiTest_2_q_to_expRPostExc_uid92_fpSinPiTest_c_q;
WHEN "01" => expRPostExc_uid92_fpSinPiTest_q <= ld_exp_uid9_fpSinPiTest_b_to_expRPostExc_uid92_fpSinPiTest_d_replace_mem_q;
WHEN "10" => expRPostExc_uid92_fpSinPiTest_q <= cstAllZWE_uid8_fpSinPiTest_q;
WHEN "11" => expRPostExc_uid92_fpSinPiTest_q <= cstAllOWE_uid6_fpSinPiTest_q;
WHEN OTHERS => expRPostExc_uid92_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracNaN_uid86_fpSinPiTest(CONSTANT,85)
fracNaN_uid86_fpSinPiTest_q <= "00000000000000000000001";
--ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_nor(LOGICAL,921)
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_nor_a <= ld_expXRR_uid32_fpSinPiTest_b_to_signExtExpXRR_uid57_fpSinPiTest_a_notEnable_q;
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_nor_b <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_sticky_ena_q;
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_nor_q <= not (ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_nor_a or ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_nor_b);
--ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_sticky_ena(REG,922)
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_nor_q = "1") THEN
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_sticky_ena_q <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_enaAnd(LOGICAL,923)
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_enaAnd_a <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_sticky_ena_q;
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_enaAnd_b <= en;
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_enaAnd_q <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_enaAnd_a and ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_enaAnd_b;
--ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_inputreg(DELAY,911)
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => frac_uid13_fpSinPiTest_b, xout => ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem(DUALMEM,912)
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_ia <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_inputreg_q;
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_aa <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdreg_q;
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_ab <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_rdmux_q;
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 6,
numwords_a => 34,
width_b => 23,
widthad_b => 6,
numwords_b => 34,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_iq,
address_a => ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_aa,
data_a => ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_ia
);
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_reset0 <= areset;
ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_q <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_iq(22 downto 0);
--fracRComp_uid77_fpSinPiTest(BITSELECT,76)@34
fracRComp_uid77_fpSinPiTest_in <= expRCompFracRComp_uid76_fpSinPiTest_q(23 downto 0);
fracRComp_uid77_fpSinPiTest_b <= fracRComp_uid77_fpSinPiTest_in(23 downto 1);
--reg_fracRComp_uid77_fpSinPiTest_0_to_fracRPostExc_uid88_fpSinPiTest_2(REG,412)@34
reg_fracRComp_uid77_fpSinPiTest_0_to_fracRPostExc_uid88_fpSinPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRComp_uid77_fpSinPiTest_0_to_fracRPostExc_uid88_fpSinPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRComp_uid77_fpSinPiTest_0_to_fracRPostExc_uid88_fpSinPiTest_2_q <= fracRComp_uid77_fpSinPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRComp_uid77_fpSinPiTest_0_to_fracRPostExc_uid88_fpSinPiTest_2_q_to_fracRPostExc_uid88_fpSinPiTest_c(DELAY,496)@35
ld_reg_fracRComp_uid77_fpSinPiTest_0_to_fracRPostExc_uid88_fpSinPiTest_2_q_to_fracRPostExc_uid88_fpSinPiTest_c : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracRComp_uid77_fpSinPiTest_0_to_fracRPostExc_uid88_fpSinPiTest_2_q, xout => ld_reg_fracRComp_uid77_fpSinPiTest_0_to_fracRPostExc_uid88_fpSinPiTest_2_q_to_fracRPostExc_uid88_fpSinPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid88_fpSinPiTest(MUX,87)@36
fracRPostExc_uid88_fpSinPiTest_s <= excSel_uid85_fpSinPiTest_q;
fracRPostExc_uid88_fpSinPiTest: PROCESS (fracRPostExc_uid88_fpSinPiTest_s, en, ld_reg_fracRComp_uid77_fpSinPiTest_0_to_fracRPostExc_uid88_fpSinPiTest_2_q_to_fracRPostExc_uid88_fpSinPiTest_c_q, ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_q, cstAllZWF_uid7_fpSinPiTest_q, fracNaN_uid86_fpSinPiTest_q)
BEGIN
CASE fracRPostExc_uid88_fpSinPiTest_s IS
WHEN "00" => fracRPostExc_uid88_fpSinPiTest_q <= ld_reg_fracRComp_uid77_fpSinPiTest_0_to_fracRPostExc_uid88_fpSinPiTest_2_q_to_fracRPostExc_uid88_fpSinPiTest_c_q;
WHEN "01" => fracRPostExc_uid88_fpSinPiTest_q <= ld_frac_uid13_fpSinPiTest_b_to_fracRPostExc_uid88_fpSinPiTest_d_replace_mem_q;
WHEN "10" => fracRPostExc_uid88_fpSinPiTest_q <= cstAllZWF_uid7_fpSinPiTest_q;
WHEN "11" => fracRPostExc_uid88_fpSinPiTest_q <= fracNaN_uid86_fpSinPiTest_q;
WHEN OTHERS => fracRPostExc_uid88_fpSinPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--sinXR_uid97_fpSinPiTest(BITJOIN,96)@36
sinXR_uid97_fpSinPiTest_q <= ld_signR_uid96_fpSinPiTest_q_to_sinXR_uid97_fpSinPiTest_c_q & expRPostExc_uid92_fpSinPiTest_q & fracRPostExc_uid88_fpSinPiTest_q;
--xOut(GPOUT,4)@36
q <= sinXR_uid97_fpSinPiTest_q;
end normal;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
bin_Dilation_Operation/ip/Dilation/hcc_mulfp3236.vhd
|
10
|
5397
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULFP3236.VHD ***
--*** ***
--*** Function: Single precision multiplier ***
--*** core function ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mulfp3236 IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_mulfp3236;
ARCHITECTURE rtl OF hcc_mulfp3236 IS
constant normtype : integer := 0;
type expfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaman, bbman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aaexp, bbexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal mulout : STD_LOGIC_VECTOR (2*mantissa DOWNTO 1);
signal aaexpff, bbexpff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expff : expfftype;
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal ccsatff, cczipff : STD_LOGIC_VECTOR (2 DOWNTO 1);
component hcc_mul3236b
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
component hcc_mul3236s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- normalization or scale turns it into
-- [S ][1 ][M...M][U..U]
-- [32][31][30..8][7..1]
-- multiplier outputs (result < 2)
-- [S....S][1 ][M*M...][U*U]
-- [64..62][61][60..15][14....1]
-- multiplier outputs (result >= 2)
-- [S....S][1 ][M*M...][U*U.....]
-- [64..63][62][61..16][15.....1]
-- output (if destination not a multiplier)
-- right shift 2
-- [S ][S ][SSS1..XX]
-- [64][64][64....35]
-- result "SSSSS1XXX" if result <2, "SSSS1XXXX" if result >= 2
aaman <= aa(mantissa+10 DOWNTO 11);
bbman <= bb(mantissa+10 DOWNTO 11);
aaexp <= aa(10 DOWNTO 1);
bbexp <= bb(10 DOWNTO 1);
pma: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aaexpff <= "0000000000";
bbexpff <= "0000000000";
FOR k IN 1 TO 2 LOOP
expff(k)(10 DOWNTO 1) <= "0000000000";
END LOOP;
aasatff <= '0';
aazipff <= '0';
bbsatff <= '0';
bbzipff <= '0';
ccsatff <= "00";
cczipff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aasatff <= aasat;
aazipff <= aazip;
bbsatff <= bbsat;
bbzipff <= bbzip;
ccsatff(1) <= aasatff OR bbsatff;
ccsatff(2) <= ccsatff(1);
cczipff(1) <= aazipff OR bbzipff;
cczipff(2) <= cczipff(1);
aaexpff <= aaexp;
bbexpff <= bbexp;
expff(1)(10 DOWNTO 1) <= aaexpff + bbexpff - "0001111111";
FOR k IN 1 TO 10 LOOP
expff(2)(k) <= (expff(1)(k) OR ccsatff(1)) AND NOT(cczipff(1));
END LOOP;
END IF;
END IF;
END PROCESS;
gsa: IF (synthesize = 0) GENERATE
bmult: hcc_mul3236b
GENERIC MAP (width=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aaman,bb=>bbman,
cc=>mulout);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
smult: hcc_mul3236s
GENERIC MAP (width=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aaman,mulbb=>bbman,
mulcc=>mulout);
END GENERATE;
--***************
--*** OUTPUTS ***
--***************
cc<= mulout(2*mantissa) & mulout(2*mantissa) & mulout(2*mantissa DOWNTO mantissa+3) & expff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
Dilation/ip/Dilation/hcc_mulfp3236.vhd
|
10
|
5397
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MULFP3236.VHD ***
--*** ***
--*** Function: Single precision multiplier ***
--*** core function ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mulfp3236 IS
GENERIC (
mantissa : positive := 32; -- 32 or 36
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_mulfp3236;
ARCHITECTURE rtl OF hcc_mulfp3236 IS
constant normtype : integer := 0;
type expfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaman, bbman : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aaexp, bbexp : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal mulout : STD_LOGIC_VECTOR (2*mantissa DOWNTO 1);
signal aaexpff, bbexpff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal expff : expfftype;
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal ccsatff, cczipff : STD_LOGIC_VECTOR (2 DOWNTO 1);
component hcc_mul3236b
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
component hcc_mul3236s
GENERIC (width : positive := 32);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (2*width DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- normalization or scale turns it into
-- [S ][1 ][M...M][U..U]
-- [32][31][30..8][7..1]
-- multiplier outputs (result < 2)
-- [S....S][1 ][M*M...][U*U]
-- [64..62][61][60..15][14....1]
-- multiplier outputs (result >= 2)
-- [S....S][1 ][M*M...][U*U.....]
-- [64..63][62][61..16][15.....1]
-- output (if destination not a multiplier)
-- right shift 2
-- [S ][S ][SSS1..XX]
-- [64][64][64....35]
-- result "SSSSS1XXX" if result <2, "SSSS1XXXX" if result >= 2
aaman <= aa(mantissa+10 DOWNTO 11);
bbman <= bb(mantissa+10 DOWNTO 11);
aaexp <= aa(10 DOWNTO 1);
bbexp <= bb(10 DOWNTO 1);
pma: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aaexpff <= "0000000000";
bbexpff <= "0000000000";
FOR k IN 1 TO 2 LOOP
expff(k)(10 DOWNTO 1) <= "0000000000";
END LOOP;
aasatff <= '0';
aazipff <= '0';
bbsatff <= '0';
bbzipff <= '0';
ccsatff <= "00";
cczipff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aasatff <= aasat;
aazipff <= aazip;
bbsatff <= bbsat;
bbzipff <= bbzip;
ccsatff(1) <= aasatff OR bbsatff;
ccsatff(2) <= ccsatff(1);
cczipff(1) <= aazipff OR bbzipff;
cczipff(2) <= cczipff(1);
aaexpff <= aaexp;
bbexpff <= bbexp;
expff(1)(10 DOWNTO 1) <= aaexpff + bbexpff - "0001111111";
FOR k IN 1 TO 10 LOOP
expff(2)(k) <= (expff(1)(k) OR ccsatff(1)) AND NOT(cczipff(1));
END LOOP;
END IF;
END IF;
END PROCESS;
gsa: IF (synthesize = 0) GENERATE
bmult: hcc_mul3236b
GENERIC MAP (width=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aaman,bb=>bbman,
cc=>mulout);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
smult: hcc_mul3236s
GENERIC MAP (width=>mantissa)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>aaman,mulbb=>bbman,
mulcc=>mulout);
END GENERATE;
--***************
--*** OUTPUTS ***
--***************
cc<= mulout(2*mantissa) & mulout(2*mantissa) & mulout(2*mantissa DOWNTO mantissa+3) & expff(2)(10 DOWNTO 1);
ccsat <= ccsatff(2);
cczip <= cczipff(2);
END rtl;
|
mit
|
Given-Jiang/Dilation_Operation_Altera_OpenCL_DE1-SoC
|
bin_Dilation_Operation/ip/Dilation/fp_tan.vhd
|
10
|
24604
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_TAN1.VHD ***
--*** ***
--*** Function: Single Precision Floating Point ***
--*** Tangent ***
--*** ***
--*** 23/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** NOTES ***
--***************************************************
--*** 1. for very top of range (last 256 mantissa lsbs before pi/2), use seperate ROM, not
--*** calculation
--*** 2. if round up starting when X.49999, errors reduce about 25%, need to tweak this, still getting
--*** all -1 errors with bX.111111111. less errors with less tail bits for smaller exponents (like 122)
--*** more for exponent = 126
ENTITY fp_tan IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
signout : OUT STD_LOGIC;
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1)
);
END fp_tan;
ARCHITECTURE rtl of fp_tan IS
-- input section
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissainff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal argumentff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal topargumentff : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal middleargumentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal tanhighmantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanmiddleff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanhighexponentff : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal tanlowsumff : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal shiftin : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal shiftinbus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal argumentbus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanhighmantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanhighexponent : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal tanmiddle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal deltwo_tailnode : STD_LOGIC_VECTOR (19 DOWNTO 1);
signal tantailnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanlowsumnode : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal tanlowmantissabus : STD_LOGIC_VECTOR (56 DOWNTO 1);
-- numerator section
signal tanlowff : STD_LOGIC_VECTOR (56 DOWNTO 1);
signal numeratorsumff : STD_LOGIC_VECTOR (57 DOWNTO 1);
signal tanlowshift : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal numeratormantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal numeratorexponentff : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal delone_tanhighexponent : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal delthr_tanhighexponent : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal deltwo_tanhighmantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanlowbus : STD_LOGIC_VECTOR (56 DOWNTO 1);
signal numeratorsum : STD_LOGIC_VECTOR (57 DOWNTO 1);
signal numeratorlead, numeratorleadnode : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal numeratormantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal numeratorexponent : STD_LOGIC_VECTOR (5 DOWNTO 1);
-- denominator section
signal lowleadff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal denominatorleadff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal multshiftff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal denominatorproductff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominatorff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominatormantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal inverseexponentff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal lowleadnode : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal multshiftnode : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal denominatorproductbus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominator : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal delone_denominator : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal denominatorlead : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal denominatormantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal delone_tanlowsum : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal lowmantissabus : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal delthr_tanhighmantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multipliernode : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal delfor_tanhighexponent : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal deltwo_lowlead : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal multexponent : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal denominatorexponent : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal inverseexponent : STD_LOGIC_VECTOR (6 DOWNTO 1);
-- divider section
signal tanexponentff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal tanexponentnormff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal tanexponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal tanmantissanormff : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal roundbitff : STD_LOGIC;
signal mantissaoutff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal overff : STD_LOGIC;
signal denominatorinverse : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal del_numeratormantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multiplier_tan : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal tanmantissa : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal tanmantissanorm : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal tanmantissatail : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal overcheck : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal del_inverseexponent : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal del_numeratorexponent : STD_LOGIC_VECTOR (5 DOWNTO 1);
signal tanexponent, tanexponentnorm : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentoutnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal mantissaoutnode : STD_LOGIC_VECTOR (23 DOWNTO 1);
-- small inputs
signal signff : STD_LOGIC_VECTOR (30 DOWNTO 1);
signal small_mantissa : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal small_exponent : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentcheck : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal small_inputff : STD_LOGIC_VECTOR (28 DOWNTO 1);
signal mantissabase : STD_LOGIC_VECTOR (24 DOWNTO 1);
signal exponentbase : STD_LOGIC_VECTOR (8 DOWNTO 1);
component fp_tanlut1
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
exponent : OUT STD_LOGIC_VECTOR (5 DOWNTO 1)
);
end component;
component fp_tanlut2
PORT (
add : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
tanfraction : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_clz36
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_clz36x6
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_rsft36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_rsft56x20
PORT (
inbus : IN STD_LOGIC_VECTOR (56 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (56 DOWNTO 1)
);
end component;
component fp_inv_core
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
-- convert to fixed point
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 23 LOOP
mantissainff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentinff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
argumentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 9 LOOP
topargumentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
middleargumentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
tanhighmantissaff(k) <= '0';
tanmiddleff(k) <= '0';
END LOOP;
FOR k IN 1 TO 5 LOOP
tanhighexponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 5 LOOP
tanlowsumff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
mantissainff <= mantissain;
exponentinff <= exponentin;
argumentff <= argumentbus;
topargumentff <= argumentff(36 DOWNTO 28);
middleargumentff <= argumentff(27 DOWNTO 20);
tanhighmantissaff <= tanhighmantissa;
tanhighexponentff <= tanhighexponent;
tanmiddleff <= tanmiddle;
tanlowsumff <= tanlowsumnode;
END IF;
END IF;
END PROCESS;
shiftin <= 127 - exponentinff;
shiftinbus <= '1' & mantissainff & zerovec(12 DOWNTO 1);
csftin: fp_rsft36
PORT MAP (inbus=>shiftinbus,shift=>shiftin(6 DOWNTO 1),
outbus=>argumentbus);
chtt: fp_tanlut1
PORT MAP (add=>topargumentff,
mantissa=>tanhighmantissa,
exponent=>tanhighexponent);
cltt: fp_tanlut2
PORT MAP (add=>middleargumentff,
tanfraction=>tanmiddle);
-- in level 2, out level 4
dtail: fp_del
GENERIC MAP (width=>19,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>argumentff(19 DOWNTO 1),
cc=>deltwo_tailnode);
tantailnode <= zerovec(8 DOWNTO 1) & deltwo_tailnode & zerovec(9 DOWNTO 1);
tanlowsumnode <= ('0' & tanmiddleff(36 DOWNTO 1)) + ('0' & tantailnode);
tanlowmantissabus <= tanlowsumff & zerovec(19 DOWNTO 1);
--*********************************************
--*** Align two tangent values for addition ***
--*********************************************
padd: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 56 LOOP
tanlowff(k) <= '0';
END LOOP;
FOR k IN 1 TO 57 LOOP
numeratorsumff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
numeratormantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 5 LOOP
numeratorexponentff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
tanlowff <= tanlowbus;
numeratorsumff <= numeratorsum;
numeratormantissaff <= numeratormantissa;
numeratorexponentff <= numeratorexponent;
END IF;
END IF;
END PROCESS;
-- in level 4, out level 5
dhxa: fp_del
GENERIC MAP (width=>5,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>tanhighexponentff,
cc=>delone_tanhighexponent);
-- in level 5, out level 7
dhxb: fp_del
GENERIC MAP (width=>5,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>delone_tanhighexponent,
cc=>delthr_tanhighexponent);
-- in level 4, out level 6
dhm: fp_del
GENERIC MAP (width=>36,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>tanhighmantissaff,
cc=>deltwo_tanhighmantissa);
-- tan high mantissa format 1.XXX, tan low mantissa format 0.XXXXX
-- tan high exponent base is 119 (top of middle range)
tanlowshift <= delone_tanhighexponent;
crsadd: fp_rsft56x20
PORT MAP (inbus=>tanlowmantissabus,
shift=>tanlowshift,
outbus=>tanlowbus);
numeratorsum <= ('0' & deltwo_tanhighmantissa & zerovec(20 DOWNTO 1)) + ('0' & tanlowff);
-- level 8
-- no pipe between clz and shift as only 6 bit shift
-- middle exponent is 119, and 2 overflow bits in numerator sum, so this will
-- cover downto (119+2-6) = 115 exponent
-- below 115 exponent, output mantissa = input mantissa
clznuma: fp_clz36x6
PORT MAP (mantissa=>numeratorsumff(57 DOWNTO 22),
leading=>numeratorlead);
numeratorleadnode <= "000" & numeratorlead(3 DOWNTO 1); -- force [6:4] to 0 to optimize away logic in LSFT
clsnuma: fp_lsft36
PORT MAP (inbus=>numeratorsumff(57 DOWNTO 22),shift=>numeratorleadnode,
outbus=>numeratormantissa);
numeratorexponent <= delthr_tanhighexponent - numeratorlead(5 DOWNTO 1) + 1;
--gnnadd: FOR k IN 1 TO 36 GENERATE
-- numeratormantissa(k) <= (numeratorsumff(k+20) AND NOT(numeratorsumff(57))) OR
-- (numeratorsumff(k+21) AND numeratorsumff(57));
--END GENERATE;
--numeratorexponent <= delthr_tanhighexponent + ("0000" & numeratorsumff(57));
--***************************************************
--*** Align two tangent values for multiplication ***
--***************************************************
pmul: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 6 LOOP
lowleadff(k) <= '0';
denominatorleadff(k) <= '0';
inverseexponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 6 LOOP
multshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
denominatorproductff(k) <= '0';
denominatorff(k) <= '0';
denominatormantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
lowleadff <= lowleadnode;
multshiftff <= multshiftnode;
denominatorproductff <= denominatorproductbus;
denominatorff <= denominator;
denominatorleadff <= denominatorlead;
denominatormantissaff <= denominatormantissa;
inverseexponentff <= inverseexponent;
END IF;
END IF;
END PROCESS;
clzmula: fp_clz36
PORT MAP (mantissa=>tanlowsumff(37 DOWNTO 2),
leading=>lowleadnode);
-- in level 5, out level 6
dlm: fp_del
GENERIC MAP (width=>36,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>tanlowsumff(37 DOWNTO 2),
cc=>delone_tanlowsum);
clsmula: fp_lsft36
PORT MAP (inbus=>delone_tanlowsum,shift=>lowleadff,
outbus=>lowmantissabus);
cma: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>72,
pipes=>3,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>deltwo_tanhighmantissa,
databb=>lowmantissabus,
result=>multipliernode);
-- in level 5, out level 8
dhxc: fp_del
GENERIC MAP (width=>5,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>delone_tanhighexponent,
cc=>delfor_tanhighexponent);
-- in level 6, out level 8
dlla: fp_del
GENERIC MAP (width=>6,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>lowleadff,
cc=>deltwo_lowlead);
-- msb of lowmantissa(37) is at exponent 0 for highmantissa
multexponent <= ('0' & delfor_tanhighexponent);
--multshiftnode <= "001000" - multexponent + 8 - 1 + lowlead;
multshiftnode <= "001111" - multexponent + deltwo_lowlead;
-- '1.0' is at exponent 8 compared to highmantissa
crsmul: fp_rsft36
PORT MAP (inbus=>multipliernode(72 DOWNTO 37),shift=>multshiftff,
outbus=>denominatorproductbus);
denominator <= ('1' & zerovec(35 DOWNTO 1)) - denominatorproductff;
-- in level 11, out level 12
dda: fp_del
GENERIC MAP (width=>36,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, -- use reset to force to ffs here
aa=>denominatorff,
cc=>delone_denominator);
clzmulb: fp_clz36
PORT MAP (mantissa=>denominatorff,
leading=>denominatorlead);
-- denominatormantissa level 12, (denominatormantissaff level 13)
clsmulb: fp_lsft36
PORT MAP (inbus=>delone_denominator,shift=>denominatorleadff,
outbus=>denominatormantissa);
denominatorexponent <= denominatorleadff; -- actually inverse of exponent i.e. 4 => -4, so sign does not have to change after inverting
-- inverseexponentff level 13
inverseexponent <= denominatorexponent - 1;
--****************************
--*** main divider section ***
--****************************
pdiv: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 8 LOOP
tanexponentff(k) <= '0';
tanexponentnormff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 24 LOOP
tanmantissanormff(k) <= '0';
END LOOP;
roundbitff <= '0';
FOR k IN 1 TO 23 LOOP
mantissaoutff(k) <= '0';
END LOOP;
overff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
tanexponentff <= tanexponent;
tanmantissanormff <= tanmantissanorm; -- level 29
tanexponentnormff <= tanexponentnorm; -- level 29
overff <= overcheck(24);
-- round up if 0.4999
roundbitff <= tanmantissanorm(1) OR
(tanmantissatail(9) AND
tanmantissatail(8) AND tanmantissatail(7) AND
tanmantissatail(6) AND tanmantissatail(5) AND
tanmantissatail(4) AND tanmantissatail(3) AND
tanmantissatail(2) AND tanmantissatail(1));
mantissaoutff <= mantissaoutnode; -- level 30
exponentoutff <= exponentoutnode; -- level 30
END IF;
END IF;
END PROCESS;
-- latency 12
-- will give output between 0.5 and 0.99999...
-- will always need to be normalized
-- level 13 in, level 25 out
cinv: fp_inv_core
GENERIC MAP (synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
divisor=>denominatormantissaff,
quotient=>denominatorinverse);
-- level 8 in, level 25 out
dnuma: fp_del
GENERIC MAP (width=>36,pipes=>17)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>numeratormantissaff,
cc=>del_numeratormantissa);
-- level 25 in, level 28 out
cmt: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>72,
pipes=>3,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>del_numeratormantissa,
databb=>denominatorinverse,
result=>multiplier_tan);
tanmantissa <= multiplier_tan(72 DOWNTO 37);
gmna: FOR k IN 1 TO 24 GENERATE
tanmantissanorm(k) <= (tanmantissa(k+9) AND NOT(tanmantissa(35))) OR
(tanmantissa(k+10) AND tanmantissa(35));
END GENERATE;
gmnb: FOR k IN 1 TO 9 GENERATE
tanmantissatail(k) <= (tanmantissa(k) AND NOT(tanmantissa(35))) OR
(tanmantissa(k+1) AND tanmantissa(35));
END GENERATE;
overcheck(1) <= tanmantissanorm(1);
gova: FOR k IN 2 TO 24 GENERATE
overcheck(k) <= overcheck(k-1) AND tanmantissanorm(k);
END GENERATE;
-- level 13 in, level 27 out
ddena: fp_del
GENERIC MAP (width=>6,pipes=>14)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>inverseexponentff,
cc=>del_inverseexponent);
-- level 8 in, level 27 out
dnumb: fp_del
GENERIC MAP (width=>5,pipes=>19)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>numeratorexponentff,
cc=>del_numeratorexponent);
tanexponent <= "01110111" +
(del_numeratorexponent(5) & del_numeratorexponent(5) & del_numeratorexponent(5) & del_numeratorexponent) +
(del_inverseexponent(6) & del_inverseexponent(6) & del_inverseexponent); -- 119 + exponent
tanexponentnorm <= tanexponentff + tanmantissa(35);
--*** handle small inputs ****
dsma: fp_del
GENERIC MAP (width=>23,pipes=>29)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>mantissain,
cc=>small_mantissa);
dsxa: fp_del
GENERIC MAP (width=>8,pipes=>29)
PORT MAP (sysclk=>sysclk,reset=>'0',enable=>enable, -- no resets for memory
aa=>exponentin,
cc=>small_exponent);
exponentcheck <= exponentinff - 115;
psa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 30 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO 28 LOOP
small_inputff(k) <= '0';
END LOOP;
ELSIF(rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff(1) <= signin;
FOR k IN 2 TO 30 LOOP
signff(k) <= signff(k-1);
END LOOP;
small_inputff(1) <= exponentcheck(8);
FOR k IN 2 TO 28 LOOP
small_inputff(k) <= small_inputff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--mantissabase(1) <= (tanmantissanormff(1) AND NOT(small_inputff(28)));
mantissabase(1) <= (roundbitff AND NOT(small_inputff(28)));
gmba: FOR k IN 2 TO 24 GENERATE
mantissabase(k) <= (small_mantissa(k-1) AND small_inputff(28)) OR
(tanmantissanormff(k) AND NOT(small_inputff(28)));
END GENERATE;
gxba: FOR k IN 1 TO 8 GENERATE
exponentbase(k) <= (small_exponent(k) AND small_inputff(28)) OR
(tanexponentnormff(k) AND NOT(small_inputff(28)));
END GENERATE;
mantissaoutnode <= mantissabase(24 DOWNTO 2) + mantissabase(1);
exponentoutnode <= exponentbase + (overff AND NOT(small_inputff(28)));
--***************
--*** OUTPUTS ***
--***************
signout <= signff(30);
mantissaout <= mantissaoutff;
exponentout <= exponentoutff;
END rtl;
|
mit
|
Bjay1435/capstone
|
Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/lib_srl_fifo_v1_0/hdl/src/vhdl/srl_fifo_f.vhd
|
15
|
9375
|
-- srl_fifo_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo_f.vhd
--
-- Description: A small-to-medium depth FIFO. For
-- data storage, the SRL elements native to the
-- target FGPA family are used. If the FIFO depth
-- exceeds the available depth of the SRL elements,
-- then SRLs are cascaded and MUXFN elements are
-- used to select the output of the appropriate SRL stage.
--
-- Features:
-- - Width and depth are arbitrary, but each doubling of
-- depth, starting from the native SRL depth, adds
-- a level of MUXFN. Generally, in performance-oriented
-- applications, the fifo depth may need to be limited to
-- not exceed the SRL cascade depth supported by local
-- fast interconnect or the number of MUXFN levels.
-- However, deeper fifos will correctly build.
-- - Commands: read, write.
-- - Flags: empty and full.
-- - The Addr output is always one less than the current
-- occupancy when the FIFO is non-empty, and is all ones
-- otherwise. Therefore, the value <FIFO_Empty, Addr>--
-- i.e. FIFO_Empty concatenated on the left to Addr--
-- when taken as a signed value, is one less than the
-- current occupancy.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo_f.vhd
-- srl_fifo_rbu_f.vhd
-- proc_common_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: Farrell Ostler
--
-- History:
-- FLO 12/13/05 First Version.
--
-- FLO 04/27/06
-- ^^^^^^
-- C_FAMILY made to default to "nofamily".
-- ~~~~~~
-- FLO 2007-12-12
-- ^^^^^^
-- Using function clog2 now instead of log2 to eliminate superfluous warnings.
-- ~~~~~~
--
-- DET 1/17/2008 v5_0
-- ~~~~~~
-- - Changed proc_common library version to v5_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- predecessor value by # clks: "*_p#"
library ieee;
use ieee.std_logic_1164.all;
library lib_srl_fifo_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
--
entity srl_fifo_f is
generic (
C_DWIDTH : natural;
C_DEPTH : positive := 16;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DWIDTH-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DWIDTH-1);
FIFO_Empty : out std_logic;
FIFO_Full : out std_logic;
Addr : out std_logic_vector(0 to clog2(C_DEPTH)-1)
);
end entity srl_fifo_f;
--
architecture imp of srl_fifo_f is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
constant ZEROES : std_logic_vector(0 to clog2(C_DEPTH)-1) := (others => '0');
begin
I_SRL_FIFO_RBU_F : entity lib_srl_fifo_v1_0_2.srl_fifo_rbu_f
generic map (
C_DWIDTH => C_DWIDTH,
C_DEPTH => C_DEPTH,
C_FAMILY => C_FAMILY
)
port map (
Clk => Clk,
Reset => Reset,
FIFO_Write => FIFO_Write,
Data_In => Data_In,
FIFO_Read => FIFO_Read,
Data_Out => Data_Out,
FIFO_Full => FIFO_Full,
FIFO_Empty => FIFO_Empty,
Addr => Addr,
Num_To_Reread => ZEROES,
Underflow => open,
Overflow => open
);
end architecture imp;
|
mit
|
Bjay1435/capstone
|
Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/lib_srl_fifo_v1_0/hdl/src/vhdl/cntr_incr_decr_addn_f.vhd
|
15
|
10256
|
-- cntr_incr_decr_addn_f - entity / architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005 - 2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: cntr_incr_decr_addn_f.vhd
--
-- Description: This counter can increment, decrement or skip ahead
-- by an arbitrary amount.
--
-- If Reset is active, the value Cnt synchronously resets
-- to all ones. (This reset value, different than the
-- customary reset value of zero, caters to the original
-- application of cntr_incr_decr_addn_f as the address
-- counter for srl_fifo_rbu_f.)
--
-- Otherwise, on each Clk, one is added to Cnt if Incr is
-- asserted and one is subtracted if Decr is asserted. (If
-- both are asserted, then there is no change to Cnt.)
--
-- If Decr is not asserted, then the input value,
-- Nm_to_add, is added. (Simultaneous assertion of Incr
-- would add one more.) If Decr is asserted, then
-- N_to_add, is ignored, i.e., it is possible to decrement
-- by one or add N, but not both, and Decr overrides.
--
-- The value that Cnt will take on at the next clock
-- is available as Cnt_p1.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- cntr_incr_decr_addn_f.vhd
--
-------------------------------------------------------------------------------
--
-- History:
-- FLO 12/30/05 First Version.
--
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- predecessor value by # clks: "*_p#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--
entity cntr_incr_decr_addn_f is
generic (
C_SIZE : natural;
C_FAMILY : string := "nofamily"
);
port (
Clk : in std_logic;
Reset : in std_logic; -- Note: the counter resets to all ones!
Incr : in std_logic;
Decr : in std_logic;
N_to_add : in std_logic_vector(C_SIZE-1 downto 0);
Cnt : out std_logic_vector(C_SIZE-1 downto 0);
Cnt_p1 : out std_logic_vector(C_SIZE-1 downto 0)
);
end entity cntr_incr_decr_addn_f;
---(
library lib_srl_fifo_v1_0_2;
library ieee;
use ieee.numeric_std.UNSIGNED;
use ieee.numeric_std."+";
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
--
architecture imp of cntr_incr_decr_addn_f is
-- constant COUNTER_PRIMS_AVAIL : boolean :=
-- supported(C_FAMILY, (u_MUXCY_L, u_XORCY, u_FDS));
constant COUNTER_PRIMS_AVAIL : boolean := false;
signal cnt_i : std_logic_vector(Cnt'range);
signal cnt_i_p1 : std_logic_vector(Cnt'range);
----------------------------------------------------------------------------
-- Unisim components declared locally for maximum avoidance of default
-- binding and vcomponents version issues.
----------------------------------------------------------------------------
component MUXCY_L
port
(
LO : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
component XORCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
LI : in std_ulogic
);
end component;
component FDS
generic
(
INIT : bit := '1'
);
port
(
Q : out std_ulogic;
C : in std_ulogic;
D : in std_ulogic;
S : in std_ulogic
);
end component;
begin -- architecture imp
---(
INFERRED_GEN : if COUNTER_PRIMS_AVAIL = false generate
--
CNT_I_P1_PROC : process( cnt_i, N_to_add, Decr, Incr
) is
--
function qual_n_to_add(N_to_add : std_logic_vector;
Decr : std_logic
) return UNSIGNED is
variable r: UNSIGNED(N_to_add'range);
begin
for i in r'range loop
r(i) := N_to_add(i) or Decr;
end loop;
return r;
end;
--
function to_singleton_unsigned(s : std_logic) return unsigned is
variable r : unsigned(0 to 0) := (others => s);
begin
return r;
end;
--
begin
cnt_i_p1 <= std_logic_vector( UNSIGNED(cnt_i)
+ qual_n_to_add(N_to_add, Decr)
+ to_singleton_unsigned(Incr)
);
end process;
--
CNT_I_PROC : process(Clk) is
begin
if Clk'event and Clk = '1' then
if Reset = '1' then
cnt_i <= (others => '1');
else
cnt_i <= cnt_i_p1;
end if;
end if;
end process;
--
end generate INFERRED_GEN;
---)
Cnt <= cnt_i;
Cnt_p1 <= cnt_i_p1;
end architecture imp;
---)
|
mit
|
Bjay1435/capstone
|
Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/lib_pkg_v1_0/hdl/src/vhdl/lib_pkg.vhd
|
28
|
16351
|
-- Processor Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: lib_pkg.vhd
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package lib_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type CHAR_TO_INT_TYPE is array (character) of integer;
-- type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-- Type SLV64_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 63);
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer;
function min2 (num1, num2 : integer) return integer;
function Addr_Bits(x,y : std_logic_vector) return integer;
function clog2(x : positive) return natural;
function pad_power2 ( in_num : integer ) return integer;
function pad_4 ( in_num : integer ) return integer;
function log2(x : natural) return integer;
function pwr(x: integer; y: integer) return integer;
function String_To_Int(S : string) return integer;
function itoa (int : integer) return string;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- the RESET_ACTIVE constant should denote the logic level of an active reset
constant RESET_ACTIVE : std_logic := '1';
-- table containing strings representing hex characters for conversion to
-- integers
constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE :=
('0' => 0,
'1' => 1,
'2' => 2,
'3' => 3,
'4' => 4,
'5' => 5,
'6' => 6,
'7' => 7,
'8' => 8,
'9' => 9,
'A'|'a' => 10,
'B'|'b' => 11,
'C'|'c' => 12,
'D'|'d' => 13,
'E'|'e' => 14,
'F'|'f' => 15,
others => -1);
end lib_pkg;
package body lib_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function min2
--
-- This function returns the lesser of two numbers.
-------------------------------------------------------------------------------
function min2 (num1, num2 : integer) return integer is
begin
if num1 <= num2 then
return num1;
else
return num2;
end if;
end function min2;
-------------------------------------------------------------------------------
-- Function Addr_bits
--
-- function to convert an address range (base address and an upper address)
-- into the number of upper address bits needed for decoding a device
-- select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits(x,y : std_logic_vector) return integer is
variable addr_xor : std_logic_vector(x'range);
variable count : integer := 0;
begin
assert x'length = y'length and (x'ascending xnor y'ascending)
report "Addr_Bits: arguments are not the same type"
severity ERROR;
addr_xor := x xor y;
for i in x'range
loop
if addr_xor(i) = '1' then return count;
end if;
count := count + 1;
end loop;
return x'length;
end Addr_Bits;
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
-------------------------------------------------------------------------------
-- Function pad_power2
--
-- This function returns the next power of 2 from the input number. If the
-- input number is a power of 2, this function returns the input number.
--
-- This function is used to round up the number of masters to the next power
-- of 2 if the number of masters is not already a power of 2.
--
-- Input argument 0, which is not a power of two, is accepted and returns 0.
-- Input arguments less than 0 are not allowed.
-------------------------------------------------------------------------------
--
function pad_power2 (in_num : integer ) return integer is
begin
if in_num = 0 then
return 0;
else
return 2**(clog2(in_num));
end if;
end pad_power2;
-------------------------------------------------------------------------------
-- Function pad_4
--
-- This function returns the next multiple of 4 from the input number. If the
-- input number is a multiple of 4, this function returns the input number.
--
-------------------------------------------------------------------------------
--
function pad_4 (in_num : integer ) return integer is
variable out_num : integer;
begin
out_num := (((in_num-1)/4) + 1)*4;
return out_num;
end pad_4;
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
--
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Function pwr -- x**y
-- negative numbers not allowed for y
-------------------------------------------------------------------------------
function pwr(x: integer; y: integer) return integer is
variable z : integer := 1;
begin
if y = 0 then return 1;
else
for i in 1 to y loop
z := z * x;
end loop;
return z;
end if;
end function pwr;
-------------------------------------------------------------------------------
-- Function itoa
--
-- The itoa function converts an integer to a text string.
-- This function is required since `image doesn't work in Synplicity
-- Valid input range is -9999 to 9999
-------------------------------------------------------------------------------
--
function itoa (int : integer) return string is
type table is array (0 to 9) of string (1 to 1);
constant LUT : table :=
("0", "1", "2", "3", "4", "5", "6", "7", "8", "9");
variable str1 : string(1 to 1);
variable str2 : string(1 to 2);
variable str3 : string(1 to 3);
variable str4 : string(1 to 4);
variable str5 : string(1 to 5);
variable abs_int : natural;
variable thousands_place : natural;
variable hundreds_place : natural;
variable tens_place : natural;
variable ones_place : natural;
variable sign : integer;
begin
abs_int := abs(int);
if abs_int > int then sign := -1;
else sign := 1;
end if;
thousands_place := abs_int/1000;
hundreds_place := (abs_int-thousands_place*1000)/100;
tens_place := (abs_int-thousands_place*1000-hundreds_place*100)/10;
ones_place :=
(abs_int-thousands_place*1000-hundreds_place*100-tens_place*10);
if sign>0 then
if thousands_place>0 then
str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) &
LUT(ones_place);
return str4;
elsif hundreds_place>0 then
str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str3;
elsif tens_place>0 then
str2 := LUT(tens_place) & LUT(ones_place);
return str2;
else
str1 := LUT(ones_place);
return str1;
end if;
else
if thousands_place>0 then
str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) &
LUT(tens_place) & LUT(ones_place);
return str5;
elsif hundreds_place>0 then
str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str4;
elsif tens_place>0 then
str3 := "-" & LUT(tens_place) & LUT(ones_place);
return str3;
else
str2 := "-" & LUT(ones_place);
return str2;
end if;
end if;
end itoa;
-----------------------------------------------------------------------------
-- Function String_To_Int
--
-- Converts a string of hex character to an integer
-- accept negative numbers
-----------------------------------------------------------------------------
function String_To_Int(S : String) return Integer is
variable Result : integer := 0;
variable Temp : integer := S'Left;
variable Negative : integer := 1;
begin
for I in S'Left to S'Right loop
if (S(I) = '-') then
Temp := 0;
Negative := -1;
else
Temp := STRHEX_TO_INT_TABLE(S(I));
if (Temp = -1) then
assert false
report "Wrong value in String_To_Int conversion " & S(I)
severity error;
end if;
end if;
Result := Result * 16 + Temp;
end loop;
return (Negative * Result);
end String_To_Int;
end package body lib_pkg;
|
mit
|
Bjay1435/capstone
|
Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_s2mm_sm.vhd
|
1
|
50954
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_sm.vhd
-- Description: This entity contains the S2MM DMA Controller State Machine
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_10;
use axi_dma_v7_1_10.axi_dma_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_sm is
generic (
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Width of Buffer Length, Transferred Bytes, and BTT fields
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1
-- Depth of DataMover command FIFO
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
s2mm_stop : in std_logic ; --
--
-- S2MM Control and Status --
s2mm_run_stop : in std_logic ; --
s2mm_keyhole : in std_logic ; --
s2mm_ftch_idle : in std_logic ; --
s2mm_desc_flush : in std_logic ; --
s2mm_cmnd_idle : out std_logic ; --
s2mm_sts_idle : out std_logic ; --
s2mm_eof_set : out std_logic ; --
s2mm_eof_micro : in std_logic ; --
s2mm_sof_micro : in std_logic ; --
--
-- S2MM Descriptor Fetch Request --
desc_fetch_req : out std_logic ; --
desc_fetch_done : in std_logic ; --
desc_update_done : in std_logic ; --
updt_pending : in std_logic ;
desc_available : in std_logic ; --
--
-- S2MM Status Stream RX Length --
s2mm_rxlength_valid : in std_logic ; --
s2mm_rxlength_clr : out std_logic ; --
s2mm_rxlength : in std_logic_vector --
(C_SG_LENGTH_WIDTH - 1 downto 0) ; --
--
-- DataMover Command --
s2mm_cmnd_wr : out std_logic ; --
s2mm_cmnd_data : out std_logic_vector --
((C_M_AXI_S2MM_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
s2mm_cmnd_pending : in std_logic ; --
--
-- Descriptor Fields --
s2mm_desc_info : in std_logic_vector --
(31 downto 0); --
s2mm_desc_baddress : in std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
s2mm_desc_blength : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0); --
s2mm_desc_blength_v : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0); --
s2mm_desc_blength_s : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) --
);
end axi_dma_s2mm_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Commmand TAG
constant S2MM_CMD_TAG : std_logic_vector(2 downto 0) := (others => '0');
-- DataMover Command Destination Stream Offset
constant S2MM_CMD_DSA : std_logic_vector(5 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant S2MM_CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_S2MM_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_S2MM_ADDR_WIDTH)
:= (others => '0');
-- Queued commands counter width
constant COUNTER_WIDTH : integer := clog2(C_PRMY_CMDFIFO_DEPTH+1);
-- Queued commands zero count
constant ZERO_COUNT : std_logic_vector(COUNTER_WIDTH - 1 downto 0)
:= (others => '0');
-- Zero buffer length error - compare value
constant ZERO_LENGTH : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0)
:= (others => '0');
constant ZERO_BUFFER : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- State Machine Signals
signal desc_fetch_req_cmb : std_logic := '0';
signal write_cmnd_cmb : std_logic := '0';
signal s2mm_rxlength_clr_cmb : std_logic := '0';
signal rxlength : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_rxlength_set : std_logic := '0';
signal blength_grtr_rxlength : std_logic := '0';
signal rxlength_fetched : std_logic := '0';
signal cmnds_queued : std_logic_vector(COUNTER_WIDTH - 1 downto 0) := (others => '0');
signal cmnds_queued_shift : std_logic_vector(C_PRMY_CMDFIFO_DEPTH - 1 downto 0) := (others => '0');
signal count_incr : std_logic := '0';
signal count_decr : std_logic := '0';
signal desc_fetch_done_d1 : std_logic := '0';
signal zero_length_error : std_logic := '0';
signal s2mm_eof_set_i : std_logic := '0';
signal queue_more : std_logic := '0';
signal burst_type : std_logic;
signal eof_micro : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
EN_MICRO_DMA : if C_MICRO_DMA = 1 generate
begin
eof_micro <= s2mm_eof_micro;
end generate EN_MICRO_DMA;
NO_MICRO_DMA : if C_MICRO_DMA = 0 generate
begin
eof_micro <= '0';
end generate NO_MICRO_DMA;
s2mm_eof_set <= s2mm_eof_set_i;
burst_type <= '1' and (not s2mm_keyhole);
-- A 0 s2mm_keyhole means incremental burst
-- a 1 s2mm_keyhole means fixed burst
-------------------------------------------------------------------------------
-- Not using rx length from status stream - (indeterminate length mode)
-------------------------------------------------------------------------------
GEN_SM_FOR_NO_LENGTH : if (C_SG_USE_STSAPP_LENGTH = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_ENABLE_MULTI_CHANNEL = 1) generate
type SG_S2MM_STATE_TYPE is (
IDLE,
FETCH_DESCRIPTOR,
-- EXECUTE_XFER,
WAIT_STATUS
);
signal s2mm_cs : SG_S2MM_STATE_TYPE;
signal s2mm_ns : SG_S2MM_STATE_TYPE;
begin
-- For no status stream or not using length in status app field then eof set is
-- generated from datamover status (see axi_dma_s2mm_cmdsts_if.vhd)
s2mm_eof_set_i <= '0';
-------------------------------------------------------------------------------
-- S2MM Transfer State Machine
-------------------------------------------------------------------------------
S2MM_MACHINE : process(s2mm_cs,
s2mm_run_stop,
desc_available,
desc_fetch_done,
desc_update_done,
s2mm_cmnd_pending,
s2mm_stop,
s2mm_desc_flush,
updt_pending
-- queue_more
)
begin
-- Default signal assignment
desc_fetch_req_cmb <= '0';
write_cmnd_cmb <= '0';
s2mm_cmnd_idle <= '0';
s2mm_ns <= s2mm_cs;
case s2mm_cs is
-------------------------------------------------------------------
when IDLE =>
-- fetch descriptor if desc available, not stopped and running
-- if (updt_pending = '1') then
-- s2mm_ns <= WAIT_STATUS;
if(s2mm_run_stop = '1' and desc_available = '1'
-- and s2mm_stop = '0' and queue_more = '1' and updt_pending = '0')then
and s2mm_stop = '0' and updt_pending = '0')then
if (C_SG_INCLUDE_DESC_QUEUE = 1) then
s2mm_ns <= FETCH_DESCRIPTOR;
desc_fetch_req_cmb <= '1';
else
s2mm_ns <= WAIT_STATUS;
write_cmnd_cmb <= '1';
end if;
else
s2mm_cmnd_idle <= '1';
s2mm_ns <= IDLE;
end if;
-------------------------------------------------------------------
when FETCH_DESCRIPTOR =>
-- exit if error or descriptor flushed
if(s2mm_desc_flush = '1' or s2mm_stop = '1')then
s2mm_ns <= IDLE;
-- wait until fetch complete then execute
-- elsif(desc_fetch_done = '1')then
-- desc_fetch_req_cmb <= '0';
-- s2mm_ns <= EXECUTE_XFER;
elsif (s2mm_cmnd_pending = '0')then
desc_fetch_req_cmb <= '0';
if (updt_pending = '0') then
if(C_SG_INCLUDE_DESC_QUEUE = 1)then
s2mm_ns <= IDLE;
write_cmnd_cmb <= '1';
else
-- coverage off
s2mm_ns <= WAIT_STATUS;
-- coverage on
end if;
end if;
else
s2mm_ns <= FETCH_DESCRIPTOR;
end if;
-------------------------------------------------------------------
-- when EXECUTE_XFER =>
-- -- if error exit
-- if(s2mm_stop = '1')then
-- s2mm_ns <= IDLE;
-- -- Write another command if there is not one already pending
-- elsif(s2mm_cmnd_pending = '0')then
-- if (updt_pending = '0') then
-- write_cmnd_cmb <= '1';
-- end if;
-- if(C_SG_INCLUDE_DESC_QUEUE = 1)then
-- s2mm_ns <= IDLE;
-- else
-- s2mm_ns <= WAIT_STATUS;
-- end if;
-- else
-- s2mm_ns <= EXECUTE_XFER;
-- end if;
-------------------------------------------------------------------
when WAIT_STATUS =>
-- for no Q wait until desc updated
if(desc_update_done = '1' or s2mm_stop = '1')then
s2mm_ns <= IDLE;
else
s2mm_ns <= WAIT_STATUS;
end if;
-------------------------------------------------------------------
-- coverage off
when others =>
s2mm_ns <= IDLE;
-- coverage on
end case;
end process S2MM_MACHINE;
-------------------------------------------------------------------------------
-- Register State Machine Statues
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_cs <= IDLE;
else
s2mm_cs <= s2mm_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- Register State Machine Signalse
-------------------------------------------------------------------------------
-- SM_SIG_REGISTER : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- desc_fetch_req <= '0' ;
-- else
-- if (C_SG_INCLUDE_DESC_QUEUE = 0) then
-- desc_fetch_req <= '1';
-- else
-- desc_fetch_req <= desc_fetch_req_cmb ;
-- end if;
-- end if;
-- end if;
-- end process SM_SIG_REGISTER;
desc_fetch_req <= '1' when (C_SG_INCLUDE_DESC_QUEUE = 0) else
desc_fetch_req_cmb ;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- If Bytes To Transfer (BTT) width less than 23, need to add pad
GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
-- When command by sm, drive command to s2mm_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_cmnd_wr <= '0';
-- s2mm_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
elsif(write_cmnd_cmb = '1')then
s2mm_cmnd_wr <= '1';
-- s2mm_cmnd_data <= s2mm_desc_info
-- & s2mm_desc_blength_v
-- & s2mm_desc_blength_s
-- & S2MM_CMD_RSVD
-- & "0000" -- Cat IOC to CMD TAG
-- & s2mm_desc_baddress
-- & '1' -- Always reset DRE
-- & '0' -- For Indeterminate BTT mode do not set EOF
-- & S2MM_CMD_DSA
-- & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
-- & PAD_VALUE
-- & s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
else
s2mm_cmnd_wr <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
s2mm_cmnd_data <= s2mm_desc_info
& s2mm_desc_blength_v
& s2mm_desc_blength_s
& S2MM_CMD_RSVD
& "00" & eof_micro & eof_micro --00" -- Cat IOC to CMD TAG
& s2mm_desc_baddress
& '1' -- Always reset DRE
& eof_micro --'0' -- For Indeterminate BTT mode do not set EOF
& S2MM_CMD_DSA
& burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
& PAD_VALUE
& s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
end generate GEN_CMD_BTT_LESS_23;
-- If Bytes To Transfer (BTT) width equal 23, no required pad
GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate
begin
-- When command by sm, drive command to s2mm_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_cmnd_wr <= '0';
-- s2mm_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
elsif(write_cmnd_cmb = '1')then
s2mm_cmnd_wr <= '1';
-- s2mm_cmnd_data <= s2mm_desc_info
-- & s2mm_desc_blength_v
-- & s2mm_desc_blength_s
-- & S2MM_CMD_RSVD
-- & "0000" -- Cat IOC to CMD TAG
-- & s2mm_desc_baddress
-- & '1' -- Always reset DRE
-- & '0' -- For indeterminate BTT mode do not set EOF
-- & S2MM_CMD_DSA
-- & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
-- & s2mm_desc_blength;
else
s2mm_cmnd_wr <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
s2mm_cmnd_data <= s2mm_desc_info
& s2mm_desc_blength_v
& s2mm_desc_blength_s
& S2MM_CMD_RSVD
& "00" & eof_micro & eof_micro -- "0000" -- Cat IOC to CMD TAG
& s2mm_desc_baddress
& '1' -- Always reset DRE
& eof_micro -- For indeterminate BTT mode do not set EOF
& S2MM_CMD_DSA
& burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
& s2mm_desc_blength;
end generate GEN_CMD_BTT_EQL_23;
-- Drive unused output to zero
s2mm_rxlength_clr <= '0';
end generate GEN_SM_FOR_NO_LENGTH;
-------------------------------------------------------------------------------
-- Generate state machine and support logic for Using RX Length from Status
-- Stream
-------------------------------------------------------------------------------
-- this would not hold good for MCDMA
GEN_SM_FOR_LENGTH : if (C_SG_USE_STSAPP_LENGTH = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate
type SG_S2MM_STATE_TYPE is (
IDLE,
FETCH_DESCRIPTOR,
GET_RXLENGTH,
CMPR_LENGTH,
EXECUTE_XFER,
WAIT_STATUS
);
signal s2mm_cs : SG_S2MM_STATE_TYPE;
signal s2mm_ns : SG_S2MM_STATE_TYPE;
begin
-------------------------------------------------------------------------------
-- S2MM Transfer State Machine
-------------------------------------------------------------------------------
S2MM_MACHINE : process(s2mm_cs,
s2mm_run_stop,
desc_available,
desc_update_done,
-- desc_fetch_done,
updt_pending,
s2mm_rxlength_valid,
rxlength_fetched,
s2mm_cmnd_pending,
zero_length_error,
s2mm_stop,
s2mm_desc_flush
-- queue_more
)
begin
-- Default signal assignment
desc_fetch_req_cmb <= '0';
s2mm_rxlength_clr_cmb <= '0';
write_cmnd_cmb <= '0';
s2mm_cmnd_idle <= '0';
s2mm_rxlength_set <= '0';
--rxlength_fetched_clr <= '0';
s2mm_ns <= s2mm_cs;
case s2mm_cs is
-------------------------------------------------------------------
when IDLE =>
if(s2mm_run_stop = '1' and desc_available = '1'
-- and s2mm_stop = '0' and queue_more = '1' and updt_pending = '0')then
and s2mm_stop = '0' and updt_pending = '0')then
if (C_SG_INCLUDE_DESC_QUEUE = 0) then
if(rxlength_fetched = '0')then
s2mm_ns <= GET_RXLENGTH;
else
s2mm_ns <= CMPR_LENGTH;
end if;
else
s2mm_ns <= FETCH_DESCRIPTOR;
desc_fetch_req_cmb <= '1';
end if;
else
s2mm_cmnd_idle <= '1';
s2mm_ns <= IDLE; --FETCH_DESCRIPTOR;
end if;
-------------------------------------------------------------------
when FETCH_DESCRIPTOR =>
desc_fetch_req_cmb <= '0';
-- exit if error or descriptor flushed
if(s2mm_desc_flush = '1')then
s2mm_ns <= IDLE;
-- Descriptor fetch complete
else --if(desc_fetch_done = '1')then
-- desc_fetch_req_cmb <= '0';
if(rxlength_fetched = '0')then
s2mm_ns <= GET_RXLENGTH;
else
s2mm_ns <= CMPR_LENGTH;
end if;
-- else
-- desc_fetch_req_cmb <= '1';
end if;
-------------------------------------------------------------------
WHEN GET_RXLENGTH =>
if(s2mm_stop = '1')then
s2mm_ns <= IDLE;
-- Buffer length zero, do not compare lengths, execute
-- command to force datamover to issue interror
elsif(zero_length_error = '1')then
s2mm_ns <= EXECUTE_XFER;
elsif(s2mm_rxlength_valid = '1')then
s2mm_rxlength_set <= '1';
s2mm_rxlength_clr_cmb <= '1';
s2mm_ns <= CMPR_LENGTH;
else
s2mm_ns <= GET_RXLENGTH;
end if;
-------------------------------------------------------------------
WHEN CMPR_LENGTH =>
s2mm_ns <= EXECUTE_XFER;
-------------------------------------------------------------------
when EXECUTE_XFER =>
if(s2mm_stop = '1')then
s2mm_ns <= IDLE;
-- write new command if one is not already pending
elsif(s2mm_cmnd_pending = '0')then
write_cmnd_cmb <= '1';
-- If descriptor queuing enabled then
-- do NOT need to wait for status
if(C_SG_INCLUDE_DESC_QUEUE = 1)then
s2mm_ns <= IDLE;
-- No queuing therefore must wait for
-- status before issuing next command
else
s2mm_ns <= WAIT_STATUS;
end if;
else
s2mm_ns <= EXECUTE_XFER;
end if;
-------------------------------------------------------------------
-- coverage off
when WAIT_STATUS =>
if(desc_update_done = '1' or s2mm_stop = '1')then
s2mm_ns <= IDLE;
else
s2mm_ns <= WAIT_STATUS;
end if;
-- coverage on
-------------------------------------------------------------------
-- coverage off
when others =>
s2mm_ns <= IDLE;
-- coverage on
end case;
end process S2MM_MACHINE;
-------------------------------------------------------------------------------
-- Register state machine states
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_cs <= IDLE;
else
s2mm_cs <= s2mm_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- Register state machine signals
-------------------------------------------------------------------------------
SM_SIG_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_fetch_req <= '0' ;
s2mm_rxlength_clr <= '0' ;
else
if (C_SG_INCLUDE_DESC_QUEUE = 0) then
desc_fetch_req <= '1';
else
desc_fetch_req <= desc_fetch_req_cmb ;
end if;
s2mm_rxlength_clr <= s2mm_rxlength_clr_cmb;
end if;
end if;
end process SM_SIG_REGISTER;
-------------------------------------------------------------------------------
-- Check for a ZERO value in descriptor buffer length. If there is
-- then flag an error and skip waiting for valid rxlength. cmnd will
-- get written to datamover with BTT=0 and datamover will flag dmaint error
-- which will be logged in desc, reset required to clear error
-------------------------------------------------------------------------------
REG_ALIGN_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_fetch_done_d1 <= '0';
else
desc_fetch_done_d1 <= desc_fetch_done;
end if;
end if;
end process REG_ALIGN_DONE;
-------------------------------------------------------------------------------
-- Zero length error detection - for determinate mode, detect early to prevent
-- rxlength calcuation from first taking place. This will force a 0 BTT
-- command to be issued to the datamover causing an internal error.
-------------------------------------------------------------------------------
REG_ZERO_LNGTH_ERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
zero_length_error <= '0';
elsif(desc_fetch_done_d1 = '1'
and s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0) = ZERO_LENGTH)then
zero_length_error <= '1';
end if;
end if;
end process REG_ZERO_LNGTH_ERR;
-------------------------------------------------------------------------------
-- Capture/Hold receive length from status stream. Also decrement length
-- based on if received length is greater than descriptor buffer size. (i.e. is
-- the case where multiple descriptors/buffers are used to describe one packet)
-------------------------------------------------------------------------------
REG_RXLENGTH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
rxlength <= (others => '0');
-- If command register rxlength from status stream fifo
elsif(s2mm_rxlength_set = '1')then
rxlength <= s2mm_rxlength;
-- On command write if current desc buffer size not greater
-- than current rxlength then decrement rxlength in preperations
-- for subsequent commands
elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '0')then
rxlength <= std_logic_vector(unsigned(rxlength(C_SG_LENGTH_WIDTH-1 downto 0))
- unsigned(s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0)));
end if;
end if;
end process REG_RXLENGTH;
-------------------------------------------------------------------------------
-- Calculate if Descriptor Buffer Length is 'Greater Than' or 'Equal To'
-- Received Length value
-------------------------------------------------------------------------------
REG_BLENGTH_GRTR_RXLNGTH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
blength_grtr_rxlength <= '0';
elsif(s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0) >= rxlength)then
blength_grtr_rxlength <= '1';
else
blength_grtr_rxlength <= '0';
end if;
end if;
end process REG_BLENGTH_GRTR_RXLNGTH;
-------------------------------------------------------------------------------
-- On command assert rxlength fetched flag indicating length grabbed from
-- status stream fifo
-------------------------------------------------------------------------------
RXLENGTH_FTCHED_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_eof_set_i = '1')then
rxlength_fetched <= '0';
elsif(s2mm_rxlength_set = '1')then
rxlength_fetched <= '1';
end if;
end if;
end process RXLENGTH_FTCHED_PROCESS;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- If Bytes To Transfer (BTT) width less than 23, need to add pad
GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
-- When command by sm, drive command to s2mm_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_cmnd_wr <= '0';
s2mm_cmnd_data <= (others => '0');
s2mm_eof_set_i <= '0';
-- Current Desc Buffer will NOT hold entire rxlength of data therefore
-- set EOF = based on Desc.EOF and pass buffer length for BTT
elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '0')then
s2mm_cmnd_wr <= '1';
s2mm_cmnd_data <= s2mm_desc_info
& ZERO_BUFFER
& ZERO_BUFFER
& S2MM_CMD_RSVD
-- Command Tag
& '0'
& '0'
& '0' -- Cat. EOF=0 to CMD Tag
& '0' -- Cat. IOC to CMD TAG
-- Command
& s2mm_desc_baddress
& '1' -- Always reset DRE
& '0' -- Not End of Frame
& S2MM_CMD_DSA
& burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
& PAD_VALUE
& s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
s2mm_eof_set_i <= '0';
-- Current Desc Buffer will hold entire rxlength of data therefore
-- set EOF = 1 and pass rxlength for BTT
--
-- Note: change to mode where EOF generates IOC interrupt as
-- opposed to a IOC bit in the descriptor negated need for an
-- EOF and IOC tag. Given time, these two bits could be combined
-- into 1. Associated logic in SG engine would also need to be
-- modified as well as in s2mm_sg_if.
elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '1')then
s2mm_cmnd_wr <= '1';
s2mm_cmnd_data <= s2mm_desc_info
& ZERO_BUFFER
& ZERO_BUFFER
& S2MM_CMD_RSVD
-- Command Tag
& '0'
& '0'
& '1' -- Cat. EOF=1 to CMD Tag
& '1' -- Cat. IOC to CMD TAG
-- Command
& s2mm_desc_baddress
& '1' -- Always reset DRE
& '1' -- Set EOF=1
& S2MM_CMD_DSA
& burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
& PAD_VALUE
& rxlength;
s2mm_eof_set_i <= '1';
else
-- s2mm_cmnd_data <= (others => '0');
s2mm_cmnd_wr <= '0';
s2mm_eof_set_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_CMD_BTT_LESS_23;
-- If Bytes To Transfer (BTT) width equal 23, no required pad
GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate
begin
-- When command by sm, drive command to s2mm_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_cmnd_wr <= '0';
s2mm_cmnd_data <= (others => '0');
s2mm_eof_set_i <= '0';
-- Current Desc Buffer will NOT hold entire rxlength of data therefore
-- set EOF = based on Desc.EOF and pass buffer length for BTT
elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '0')then
s2mm_cmnd_wr <= '1';
s2mm_cmnd_data <= s2mm_desc_info
& ZERO_BUFFER
& ZERO_BUFFER
& S2MM_CMD_RSVD
--& S2MM_CMD_TAG & s2mm_desc_ioc -- Cat IOC to CMD TAG
-- Command Tag
& '0'
& '0'
& '0' -- Cat. EOF='0' to CMD Tag
& '0' -- Cat. IOC='0' to CMD TAG
-- Command
& s2mm_desc_baddress
& '1' -- Always reset DRE
& '0' -- Not End of Frame
& S2MM_CMD_DSA
& burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
& s2mm_desc_blength;
s2mm_eof_set_i <= '0';
-- Current Desc Buffer will hold entire rxlength of data therefore
-- set EOF = 1 and pass rxlength for BTT
--
-- Note: change to mode where EOF generates IOC interrupt as
-- opposed to a IOC bit in the descriptor negated need for an
-- EOF and IOC tag. Given time, these two bits could be combined
-- into 1. Associated logic in SG engine would also need to be
-- modified as well as in s2mm_sg_if.
elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '1')then
s2mm_cmnd_wr <= '1';
s2mm_cmnd_data <= s2mm_desc_info
& ZERO_BUFFER
& ZERO_BUFFER
& S2MM_CMD_RSVD
--& S2MM_CMD_TAG & s2mm_desc_ioc -- Cat IOC to CMD TAG
-- Command Tag
& '0'
& '0'
& '1' -- Cat. EOF='1' to CMD Tag
& '1' -- Cat. IOC='1' to CMD TAG
-- Command
& s2mm_desc_baddress
& '1' -- Always reset DRE
& '1' -- End of Frame
& S2MM_CMD_DSA
& burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
& rxlength;
s2mm_eof_set_i <= '1';
else
-- s2mm_cmnd_data <= (others => '0');
s2mm_cmnd_wr <= '0';
s2mm_eof_set_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_CMD_BTT_EQL_23;
end generate GEN_SM_FOR_LENGTH;
-------------------------------------------------------------------------------
-- Counter for keepting track of pending commands/status in primary datamover
-- Use this to determine if primary datamover for s2mm is Idle.
-------------------------------------------------------------------------------
-- Increment queue count for each command written if not occuring at
-- same time a status from DM being updated to SG engine
count_incr <= '1' when write_cmnd_cmb = '1' and desc_update_done = '0'
else '0';
-- Decrement queue count for each status update to SG engine if not occuring
-- at same time as command being written to DM
count_decr <= '1' when write_cmnd_cmb = '0' and desc_update_done = '1'
else '0';
-- keep track of number queue commands
--CMD2STS_COUNTER : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0' or s2mm_stop = '1')then
-- cmnds_queued <= (others => '0');
-- elsif(count_incr = '1')then
-- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) + 1);
-- elsif(count_decr = '1')then
-- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) - 1);
-- end if;
-- end if;
-- end process CMD2STS_COUNTER;
QUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
begin
CMD2STS_COUNTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_stop = '1')then
cmnds_queued_shift <= (others => '0');
elsif(count_incr = '1')then
cmnds_queued_shift <= cmnds_queued_shift (2 downto 0) & '1';
elsif(count_decr = '1')then
cmnds_queued_shift <= '0' & cmnds_queued_shift (3 downto 1);
end if;
end if;
end process CMD2STS_COUNTER1;
end generate QUEUE_COUNT;
NOQUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
CMD2STS_COUNTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_stop = '1')then
cmnds_queued_shift (0) <= '0';
elsif(count_incr = '1')then
cmnds_queued_shift (0) <= '1';
elsif(count_decr = '1')then
cmnds_queued_shift (0) <= '0';
end if;
end if;
end process CMD2STS_COUNTER1;
end generate NOQUEUE_COUNT;
-- indicate idle when no more queued commands
--s2mm_sts_idle <= '1' when cmnds_queued_shift = "0000"
-- else '0';
s2mm_sts_idle <= not cmnds_queued_shift(0);
-------------------------------------------------------------------------------
-- Queue only the amount of commands that can be queued on descriptor update
-- else lock up can occur. Note datamover command fifo depth is set to number
-- of descriptors to queue.
-------------------------------------------------------------------------------
--QUEUE_MORE_PROCESS : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- queue_more <= '0';
-- elsif(cmnds_queued < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then
-- queue_more <= '1';
-- else
-- queue_more <= '0';
-- end if;
-- end if;
-- end process QUEUE_MORE_PROCESS;
QUEUE_MORE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
queue_more <= '0';
-- elsif(cmnds_queued < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then
-- queue_more <= '1';
else
queue_more <= not (cmnds_queued_shift (C_PRMY_CMDFIFO_DEPTH-1)); --'0';
end if;
end if;
end process QUEUE_MORE_PROCESS;
end implementation;
|
mit
|
mpvanveldhuizen/16-bit-risc
|
vhdl/dat_mem.vhd
|
4
|
866
|
library ieee;
use ieee.std_logic_1164.all;
use IEEE.Numeric_Std.all;
use work.lib.all;
entity dat_mem is
port (DIN, ADD : in std_logic_vector(15 downto 0);
WE, RE, CLK : in std_logic;
DOUT : out std_logic_vector(15 downto 0)
);
end dat_mem;
architecture Logic of dat_mem is
type memT is array (512 downto 0) of std_logic_vector(15 downto 0);
signal mem : memT := (256 => x"0100", 258 => x"0102", others => x"0000");
signal read_address : std_logic_vector(15 downto 0);
begin
process(CLK)
begin
if rising_edge(CLK) then
if WE = '1' then
mem(to_integer(unsigned(ADD))) <= DIN;
end if;
read_address <= ADD;
end if;
end process;
process(RE)
begin
if RE = '1' then
DOUT <= mem(to_integer(unsigned(read_address)));
else
DOUT <= "ZZZZZZZZZZZZZZZZ";
end if;
end process;
end Logic;
|
mit
|
Bjay1435/capstone
|
Geoff/Geoff.ip_user_files/ip/blk_mem_gen_1/blk_mem_gen_1_stub.vhdl
|
2
|
1462
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
-- Date : Mon Dec 5 01:10:10 2016
-- Host : brian-Inspiron-5547 running 64-bit Ubuntu 14.04.5 LTS
-- Command : write_vhdl -force -mode synth_stub
-- /home/brian/545/DMA_single_ram/DMA_single_ram.srcs/sources_1/ip/blk_mem_gen_1/blk_mem_gen_1_stub.vhdl
-- Design : blk_mem_gen_1
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity blk_mem_gen_1 is
Port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 18 downto 0 );
dina : in STD_LOGIC_VECTOR ( 9 downto 0 );
douta : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end blk_mem_gen_1;
architecture stub of blk_mem_gen_1 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[18:0],dina[9:0],douta[9:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_3,Vivado 2016.2";
begin
end;
|
mit
|
Bjay1435/capstone
|
Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_reset.vhd
|
1
|
39339
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_reset.vhd
-- Description: This entity encompasses the reset logic (soft and hard) for
-- distribution to the axi_vdma core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_10;
use axi_dma_v7_1_10.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_reset is
generic(
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_AXI_PRMRY_ACLK_FREQ_HZ : integer := 100000000;
-- Primary clock frequency in hertz
C_AXI_SCNDRY_ACLK_FREQ_HZ : integer := 100000000
-- Secondary clock frequency in hertz
);
port (
-- Clock Sources
m_axi_sg_aclk : in std_logic ; --
axi_prmry_aclk : in std_logic ; --
--
-- Hard Reset --
axi_resetn : in std_logic ; --
--
-- Soft Reset --
soft_reset : in std_logic ; --
soft_reset_clr : out std_logic := '0' ; --
soft_reset_done : in std_logic ; --
--
--
all_idle : in std_logic ; --
stop : in std_logic ; --
halt : out std_logic := '0' ; --
halt_cmplt : in std_logic ; --
--
-- Secondary Reset --
scndry_resetn : out std_logic := '1' ; --
-- AXI Upsizer and Line Buffer --
prmry_resetn : out std_logic := '0' ; --
-- AXI DataMover Primary Reset (Raw) --
dm_prmry_resetn : out std_logic := '1' ; --
-- AXI DataMover Secondary Reset (Raw) --
dm_scndry_resetn : out std_logic := '1' ; --
-- AXI Primary Stream Reset Outputs --
prmry_reset_out_n : out std_logic := '1' ; --
-- AXI Alternat Stream Reset Outputs --
altrnt_reset_out_n : out std_logic := '1' --
);
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of scndry_resetn : signal is "TRUE";
Attribute KEEP of prmry_resetn : signal is "TRUE";
Attribute KEEP of dm_scndry_resetn : signal is "TRUE";
Attribute KEEP of dm_prmry_resetn : signal is "TRUE";
Attribute KEEP of prmry_reset_out_n : signal is "TRUE";
Attribute KEEP of altrnt_reset_out_n : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of scndry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of prmry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of dm_scndry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of dm_prmry_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of prmry_reset_out_n : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of altrnt_reset_out_n: signal is "no";
end axi_dma_reset;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_reset is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Soft Reset Support
signal s_soft_reset_i : std_logic := '0';
signal s_soft_reset_i_d1 : std_logic := '0';
signal s_soft_reset_i_re : std_logic := '0';
signal assert_sftrst_d1 : std_logic := '0';
signal min_assert_sftrst : std_logic := '0';
signal min_assert_sftrst_d1_cdc_tig : std_logic := '0';
--ATTRIBUTE async_reg OF min_assert_sftrst_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF min_assert_sftrst : SIGNAL IS "true";
signal p_min_assert_sftrst : std_logic := '0';
signal sft_rst_dly1 : std_logic := '0';
signal sft_rst_dly2 : std_logic := '0';
signal sft_rst_dly3 : std_logic := '0';
signal sft_rst_dly4 : std_logic := '0';
signal sft_rst_dly5 : std_logic := '0';
signal sft_rst_dly6 : std_logic := '0';
signal sft_rst_dly7 : std_logic := '0';
signal sft_rst_dly8 : std_logic := '0';
signal sft_rst_dly9 : std_logic := '0';
signal sft_rst_dly10 : std_logic := '0';
signal sft_rst_dly11 : std_logic := '0';
signal sft_rst_dly12 : std_logic := '0';
signal sft_rst_dly13 : std_logic := '0';
signal sft_rst_dly14 : std_logic := '0';
signal sft_rst_dly15 : std_logic := '0';
signal sft_rst_dly16 : std_logic := '0';
signal soft_reset_d1 : std_logic := '0';
signal soft_reset_re : std_logic := '0';
-- Soft Reset to Primary clock domain signals
signal p_soft_reset : std_logic := '0';
signal p_soft_reset_d1_cdc_tig : std_logic := '0';
signal p_soft_reset_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF p_soft_reset_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_soft_reset_d2 : SIGNAL IS "true";
signal p_soft_reset_d3 : std_logic := '0';
signal p_soft_reset_re : std_logic := '0';
-- Qualified soft reset in primary clock domain for
-- generating mimimum reset pulse for soft reset
signal p_soft_reset_i : std_logic := '0';
signal p_soft_reset_i_d1 : std_logic := '0';
signal p_soft_reset_i_re : std_logic := '0';
-- Graceful halt control
signal halt_cmplt_d1_cdc_tig : std_logic := '0';
signal s_halt_cmplt : std_logic := '0';
--ATTRIBUTE async_reg OF halt_cmplt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s_halt_cmplt : SIGNAL IS "true";
signal p_halt_d1_cdc_tig : std_logic := '0';
signal p_halt : std_logic := '0';
--ATTRIBUTE async_reg OF p_halt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF p_halt : SIGNAL IS "true";
signal s_halt : std_logic := '0';
-- composite reset (hard and soft)
signal resetn_i : std_logic := '1';
signal scndry_resetn_i : std_logic := '1';
signal axi_resetn_d1_cdc_tig : std_logic := '1';
signal axi_resetn_d2 : std_logic := '1';
--ATTRIBUTE async_reg OF axi_resetn_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF axi_resetn_d2 : SIGNAL IS "true";
signal halt_i : std_logic := '0';
signal p_all_idle : std_logic := '1';
signal p_all_idle_d1_cdc_tig : std_logic := '1';
signal halt_cmplt_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Internal Hard Reset
-- Generate reset on hardware reset or soft reset
-------------------------------------------------------------------------------
resetn_i <= '0' when s_soft_reset_i = '1'
or min_assert_sftrst = '1'
or axi_resetn = '0'
else '1';
-------------------------------------------------------------------------------
-- Minimum Reset Logic for Soft Reset
-------------------------------------------------------------------------------
-- Register to generate rising edge on soft reset and falling edge
-- on reset assertion.
REG_SFTRST_FOR_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
s_soft_reset_i_d1 <= s_soft_reset_i;
assert_sftrst_d1 <= min_assert_sftrst;
-- Register soft reset from DMACR to create
-- rising edge pulse
soft_reset_d1 <= soft_reset;
end if;
end process REG_SFTRST_FOR_RE;
-- rising edge pulse on internal soft reset
s_soft_reset_i_re <= s_soft_reset_i and not s_soft_reset_i_d1;
-- CR605883
-- rising edge pulse on DMACR soft reset
REG_SOFT_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
soft_reset_re <= soft_reset and not soft_reset_d1;
end if;
end process REG_SOFT_RE;
-- falling edge detection on min soft rst to clear soft reset
-- bit in register module
soft_reset_clr <= (not min_assert_sftrst and assert_sftrst_d1)
or (not axi_resetn);
-------------------------------------------------------------------------------
-- Generate Reset for synchronous configuration
-------------------------------------------------------------------------------
GNE_SYNC_RESET : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- On start of soft reset shift pulse through to assert
-- 7 clock later. Used to set minimum 8clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
MIN_PULSE_GEN : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
elsif(all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 8 clocks.
MIN_RESET_ASSERTION : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
min_assert_sftrst <= '1';
elsif(sft_rst_dly7 = '1')then
min_assert_sftrst <= '0';
end if;
end if;
end process MIN_RESET_ASSERTION;
-------------------------------------------------------------------------------
-- Soft Reset Support
-------------------------------------------------------------------------------
-- Generate reset on hardware reset or soft reset if system is idle
-- On soft reset or error
-- mm2s dma controller will idle immediatly
-- sg fetch engine will complete current task and idle (desc's will flush)
-- sg update engine will update all completed descriptors then idle
REG_SOFT_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(soft_reset = '1'
and all_idle = '1' and halt_cmplt = '1')then
s_soft_reset_i <= '1';
elsif(soft_reset_done = '1')then
s_soft_reset_i <= '0';
end if;
end if;
end process REG_SOFT_RESET;
-- Halt datamover on soft_reset or on error. Halt will stay
-- asserted until s_soft_reset_i assertion which occurs when
-- halt is complete or hard reset
REG_DM_HALT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(resetn_i = '0')then
halt_i <= '0';
elsif(soft_reset_re = '1' or stop = '1')then
halt_i <= '1';
end if;
end if;
end process REG_DM_HALT;
halt <= halt_i;
-- AXI Stream reset output
REG_STRM_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
prmry_reset_out_n <= resetn_i and not s_soft_reset_i;
end if;
end process REG_STRM_RESET_OUT;
-- If in Scatter Gather mode and status control stream included
GEN_ALT_RESET_OUT : if C_INCLUDE_SG = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- AXI Stream reset output
REG_ALT_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
altrnt_reset_out_n <= resetn_i and not s_soft_reset_i;
end if;
end process REG_ALT_RESET_OUT;
end generate GEN_ALT_RESET_OUT;
-- If in Simple mode or status control stream excluded
GEN_NO_ALT_RESET_OUT : if C_INCLUDE_SG = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
altrnt_reset_out_n <= '1';
end generate GEN_NO_ALT_RESET_OUT;
-- Registered primary and secondary resets out
REG_RESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
prmry_resetn <= resetn_i;
scndry_resetn <= resetn_i;
end if;
end process REG_RESET_OUT;
-- AXI DataMover Primary Reset (Raw)
dm_prmry_resetn <= resetn_i;
-- AXI DataMover Secondary Reset (Raw)
dm_scndry_resetn <= resetn_i;
end generate GNE_SYNC_RESET;
-------------------------------------------------------------------------------
-- Generate Reset for asynchronous configuration
-------------------------------------------------------------------------------
GEN_ASYNC_RESET : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Primary clock is slower or equal to secondary therefore...
-- For Halt - can simply pass secondary clock version of soft reset
-- rising edge into p_halt assertion
-- For Min Rst Assertion - can simply use secondary logic version of min pulse genator
GEN_PRMRY_GRTR_EQL_SCNDRY : if C_AXI_PRMRY_ACLK_FREQ_HZ >= C_AXI_SCNDRY_ACLK_FREQ_HZ generate
begin
-- CR605883 - Register to provide pure register output for synchronizer
REG_HALT_CONDITIONS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
s_halt <= soft_reset_re or stop;
end if;
end process REG_HALT_CONDITIONS;
-- Halt data mover on soft reset assertion, error (i.e. stop=1) or
-- not running
HALT_PROCESS : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s_halt,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_halt,
scndry_vect_out => open
);
-- HALT_PROCESS : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- --p_halt_d1_cdc_tig <= soft_reset_re or stop; -- CR605883
-- p_halt_d1_cdc_tig <= s_halt; -- CR605883
-- p_halt <= p_halt_d1_cdc_tig;
-- end if;
-- end process HALT_PROCESS;
-- On start of soft reset shift pulse through to assert
-- 7 clock later. Used to set minimum 8clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
-- Adding 5 more flops to make up for 5 stages of Sync flops
MIN_PULSE_GEN : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
sft_rst_dly8 <= '0';
sft_rst_dly9 <= '0';
sft_rst_dly10 <= '0';
sft_rst_dly11 <= '0';
sft_rst_dly12 <= '0';
sft_rst_dly13 <= '0';
sft_rst_dly14 <= '0';
sft_rst_dly15 <= '0';
sft_rst_dly16 <= '0';
elsif(all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
sft_rst_dly8 <= sft_rst_dly7;
sft_rst_dly9 <= sft_rst_dly8;
sft_rst_dly10 <= sft_rst_dly9;
sft_rst_dly11 <= sft_rst_dly10;
sft_rst_dly12 <= sft_rst_dly11;
sft_rst_dly13 <= sft_rst_dly12;
sft_rst_dly14 <= sft_rst_dly13;
sft_rst_dly15 <= sft_rst_dly14;
sft_rst_dly16 <= sft_rst_dly15;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 8 clocks.
MIN_RESET_ASSERTION : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(s_soft_reset_i_re = '1')then
min_assert_sftrst <= '1';
elsif(sft_rst_dly16 = '1')then
min_assert_sftrst <= '0';
end if;
end if;
end process MIN_RESET_ASSERTION;
end generate GEN_PRMRY_GRTR_EQL_SCNDRY;
-- Primary clock is running slower than secondary therefore need to use a primary clock
-- based rising edge version of soft_reset for primary halt assertion
GEN_PRMRY_LESS_SCNDRY : if C_AXI_PRMRY_ACLK_FREQ_HZ < C_AXI_SCNDRY_ACLK_FREQ_HZ generate
signal soft_halt_int : std_logic := '0';
begin
-- Halt data mover on soft reset assertion, error (i.e. stop=1) or
-- not running
soft_halt_int <= p_soft_reset_re or stop;
HALT_PROCESS : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => soft_halt_int,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_halt,
scndry_vect_out => open
);
-- HALT_PROCESS : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- p_halt_d1_cdc_tig <= p_soft_reset_re or stop;
-- p_halt <= p_halt_d1_cdc_tig;
-- end if;
-- end process HALT_PROCESS;
REG_IDLE2PRMRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => all_idle,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_all_idle,
scndry_vect_out => open
);
-- REG_IDLE2PRMRY : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- p_all_idle_d1_cdc_tig <= all_idle;
-- p_all_idle <= p_all_idle_d1_cdc_tig;
-- end if;
-- end process REG_IDLE2PRMRY;
-- On start of soft reset shift pulse through to assert
-- 7 clock later. Used to set minimum 8clk assertion of
-- reset. Shift starts when all is idle and internal reset
-- is asserted.
MIN_PULSE_GEN : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
--if(p_soft_reset_re = '1')then
if(p_soft_reset_i_re = '1')then
sft_rst_dly1 <= '1';
sft_rst_dly2 <= '0';
sft_rst_dly3 <= '0';
sft_rst_dly4 <= '0';
sft_rst_dly5 <= '0';
sft_rst_dly6 <= '0';
sft_rst_dly7 <= '0';
sft_rst_dly8 <= '0';
sft_rst_dly9 <= '0';
sft_rst_dly10 <= '0';
sft_rst_dly11 <= '0';
sft_rst_dly12 <= '0';
sft_rst_dly13 <= '0';
sft_rst_dly14 <= '0';
sft_rst_dly15 <= '0';
sft_rst_dly16 <= '0';
elsif(p_all_idle = '1')then
sft_rst_dly1 <= '0';
sft_rst_dly2 <= sft_rst_dly1;
sft_rst_dly3 <= sft_rst_dly2;
sft_rst_dly4 <= sft_rst_dly3;
sft_rst_dly5 <= sft_rst_dly4;
sft_rst_dly6 <= sft_rst_dly5;
sft_rst_dly7 <= sft_rst_dly6;
sft_rst_dly8 <= sft_rst_dly7;
sft_rst_dly9 <= sft_rst_dly8;
sft_rst_dly10 <= sft_rst_dly9;
sft_rst_dly11 <= sft_rst_dly10;
sft_rst_dly12 <= sft_rst_dly11;
sft_rst_dly13 <= sft_rst_dly12;
sft_rst_dly14 <= sft_rst_dly13;
sft_rst_dly15 <= sft_rst_dly14;
sft_rst_dly16 <= sft_rst_dly15;
end if;
end if;
end process MIN_PULSE_GEN;
-- Drive minimum reset assertion for 8 primary clocks.
MIN_RESET_ASSERTION : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
--if(p_soft_reset_re = '1')then
if(p_soft_reset_i_re = '1')then
p_min_assert_sftrst <= '1';
elsif(sft_rst_dly16 = '1')then
p_min_assert_sftrst <= '0';
end if;
end if;
end process MIN_RESET_ASSERTION;
-- register minimum reset pulse back to secondary domain
REG_MINRST2SCNDRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => p_min_assert_sftrst,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => min_assert_sftrst,
scndry_vect_out => open
);
-- REG_MINRST2SCNDRY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- min_assert_sftrst_d1_cdc_tig <= p_min_assert_sftrst;
-- min_assert_sftrst <= min_assert_sftrst_d1_cdc_tig;
-- end if;
-- end process REG_MINRST2SCNDRY;
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
-- Generate reset on hardware reset or soft reset if system is idle
REG_P_SOFT_RESET : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_soft_reset = '1'
and p_all_idle = '1'
and halt_cmplt = '1')then
p_soft_reset_i <= '1';
else
p_soft_reset_i <= '0';
end if;
end if;
end process REG_P_SOFT_RESET;
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
-- Register qualified soft reset flag for generating rising edge
-- pulse for starting minimum reset pulse
REG_SOFT2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
p_soft_reset_i_d1 <= p_soft_reset_i;
end if;
end process REG_SOFT2PRMRY;
-- CR574188 - fixes issue with soft reset terminating too early
-- for primary slower than secondary clock
-- Generate rising edge pulse on qualified soft reset for min pulse
-- logic.
p_soft_reset_i_re <= p_soft_reset_i and not p_soft_reset_i_d1;
end generate GEN_PRMRY_LESS_SCNDRY;
-- Double register halt complete flag from primary to secondary
-- clock domain.
-- Note: halt complete stays asserted until halt clears therefore
-- only need to double register from fast to slow clock domain.
process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
halt_cmplt_reg <= halt_cmplt;
end if;
end process;
REG_HALT_CMPLT_IN : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => halt_cmplt_reg,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s_halt_cmplt,
scndry_vect_out => open
);
-- REG_HALT_CMPLT_IN : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
--
-- halt_cmplt_d1_cdc_tig <= halt_cmplt;
-- s_halt_cmplt <= halt_cmplt_d1_cdc_tig;
-- end if;
-- end process REG_HALT_CMPLT_IN;
-------------------------------------------------------------------------------
-- Soft Reset Support
-------------------------------------------------------------------------------
-- Generate reset on hardware reset or soft reset if system is idle
REG_SOFT_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(soft_reset = '1'
and all_idle = '1'
and s_halt_cmplt = '1')then
s_soft_reset_i <= '1';
elsif(soft_reset_done = '1')then
s_soft_reset_i <= '0';
end if;
end if;
end process REG_SOFT_RESET;
-- Register soft reset flag into primary domain to correcly
-- halt data mover
REG_SOFT2PRMRY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => soft_reset,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_soft_reset_d2,
scndry_vect_out => open
);
REG_SOFT2PRMRY1 : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- p_soft_reset_d1_cdc_tig <= soft_reset;
-- p_soft_reset_d2 <= p_soft_reset_d1_cdc_tig;
p_soft_reset_d3 <= p_soft_reset_d2;
end if;
end process REG_SOFT2PRMRY1;
-- Generate rising edge pulse for use with p_halt creation
p_soft_reset_re <= p_soft_reset_d2 and not p_soft_reset_d3;
-- used to mask halt reset below
p_soft_reset <= p_soft_reset_d2;
-- Halt datamover on soft_reset or on error. Halt will stay
-- asserted until s_soft_reset_i assertion which occurs when
-- halt is complete or hard reset
REG_DM_HALT : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(axi_resetn_d2 = '0')then
halt_i <= '0';
elsif(p_halt = '1')then
halt_i <= '1';
end if;
end if;
end process REG_DM_HALT;
halt <= halt_i;
-- CR605883 (CDC) Create pure register out for synchronizer
REG_CMB_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
scndry_resetn_i <= resetn_i;
end if;
end process REG_CMB_RESET;
-- Sync to mm2s primary and register resets out
REG_RESET_OUT : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => scndry_resetn_i,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => axi_resetn_d2,
scndry_vect_out => open
);
-- REG_RESET_OUT : process(axi_prmry_aclk)
-- begin
-- if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
-- --axi_resetn_d1_cdc_tig <= resetn_i; -- CR605883
-- axi_resetn_d1_cdc_tig <= scndry_resetn_i;
-- axi_resetn_d2 <= axi_resetn_d1_cdc_tig;
-- end if;
-- end process REG_RESET_OUT;
-- Register resets out to AXI DMA Logic
REG_SRESET_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
scndry_resetn <= resetn_i;
end if;
end process REG_SRESET_OUT;
-- AXI Stream reset output
prmry_reset_out_n <= axi_resetn_d2;
-- If in Scatter Gather mode and status control stream included
GEN_ALT_RESET_OUT : if C_INCLUDE_SG = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- AXI Stream alternate reset output
altrnt_reset_out_n <= axi_resetn_d2;
end generate GEN_ALT_RESET_OUT;
-- If in Simple Mode or status control stream excluded.
GEN_NO_ALT_RESET_OUT : if C_INCLUDE_SG = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
altrnt_reset_out_n <= '1';
end generate GEN_NO_ALT_RESET_OUT;
-- Register primary reset
prmry_resetn <= axi_resetn_d2;
-- AXI DataMover Primary Reset
dm_prmry_resetn <= axi_resetn_d2;
-- AXI DataMover Secondary Reset
dm_scndry_resetn <= resetn_i;
end generate GEN_ASYNC_RESET;
end implementation;
|
mit
|
AlessandroSpallina/CalcolatoriElettronici
|
VHDL/10-12-13/10-12-2013_TEST.vhd
|
2
|
1224
|
-- Copyright (C) 2016 by Spallina Ind.
library ieee;
use ieee.std_logic_1164.all;
entity TESTONE is
end TESTONE;
architecture beh of TESTONE is
component sedici_bit is
port (
din : in std_logic_vector(15 downto 0);
start, clk : in std_logic;
res : out std_logic_vector(15 downto 0);
fine : out std_logic
);
end component;
signal start, clk, fine : std_logic;
signal din, res : std_logic_vector(15 downto 0);
begin
DUT: sedici_bit port map (din, start, clk, res, fine);
process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process;
start <= '1' after 1 ns, '0' after 11 ns,
'1' after 51 ns, '0' after 61 ns,
'1' after 111 ns, '0' after 121 ns,
'1' after 181 ns, '0' after 191 ns;
din <= "00000000000000"&"00" after 11 ns, "0000000000000000" after 21 ns, -- NOT
"00000000000000"&"01" after 61 ns, "0000000000000001" after 71 ns, "0000000000000010" after 81 ns, -- OR
"00000000000000"&"10" after 121 ns, "0000000000000011" after 131 ns, "0000000000000101" after 141 ns, -- ADD
"00000000000000"&"11" after 191 ns, "0000000000000110" after 201 ns, "0000000000011111" after 211 ns; -- MAC
end beh;
|
mit
|
Bjay1435/capstone
|
Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_ftch_q_mngr.vhd
|
1
|
49985
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_queue.vhd
-- Description: This entity is the descriptor fetch queue interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1_3;
use axi_sg_v4_1_3.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_q_mngr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Stream Data width
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_ENABLE_CDMA : integer range 0 to 1 := 0;
C_ACTUAL_ADDR : integer range 32 to 64 := 32;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_mm2s_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
p_reset_n : in std_logic ;
ch2_sg_idle : in std_logic ;
--
-- Channel 1 Control --
ch1_desc_flush : in std_logic ; --
ch1_cyclic : in std_logic ; --
ch1_cntrl_strm_stop : in std_logic ;
ch1_ftch_active : in std_logic ; --
ch1_nxtdesc_wren : out std_logic ; --
ch1_ftch_queue_empty : out std_logic ; --
ch1_ftch_queue_full : out std_logic ; --
ch1_ftch_pause : out std_logic ; --
--
-- Channel 2 Control --
ch2_desc_flush : in std_logic ; --
ch2_cyclic : in std_logic ; --
ch2_ftch_active : in std_logic ; --
ch2_nxtdesc_wren : out std_logic ; --
ch2_ftch_queue_empty : out std_logic ; --
ch2_ftch_queue_full : out std_logic ; --
ch2_ftch_pause : out std_logic ; --
nxtdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
-- DataMover Command --
ftch_cmnd_wr : in std_logic ; --
ftch_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
ftch_stale_desc : out std_logic ; --
--
-- MM2S Stream In from DataMover --
m_axis_mm2s_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_mm2s_tkeep : in std_logic_vector --
((C_M_AXIS_SG_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tlast : in std_logic ; --
m_axis_mm2s_tvalid : in std_logic ; --
m_axis_mm2s_tready : out std_logic ; --
--
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ch1_ftch_aclk : in std_logic ;
m_axis_ch1_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ch1_ftch_tvalid : out std_logic ; --
m_axis_ch1_ftch_tready : in std_logic ; --
m_axis_ch1_ftch_tlast : out std_logic ; --
m_axis_ch1_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ch1_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ch1_ftch_tvalid_new : out std_logic ; --
m_axis_ftch1_desc_available : out std_logic ;
--
m_axis_ch2_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ch2_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ch2_ftch_tdata_mcdma_nxt : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis_ch2_ftch_tvalid_new : out std_logic ; --
m_axis_ftch2_desc_available : out std_logic ;
--
-- Channel 2 AXI Fetch Stream Out --
m_axis_ch2_ftch_aclk : in std_logic ; --
m_axis_ch2_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_ch2_ftch_tvalid : out std_logic ; --
m_axis_ch2_ftch_tready : in std_logic ; --
m_axis_ch2_ftch_tlast : out std_logic ; --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(31 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
(3 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic := '0'; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_ftch_q_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_q_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Determine the maximum word count for use in setting the word counter width
-- Set bit width on max num words to fetch
constant FETCH_COUNT : integer := max2(C_SG_CH1_WORDS_TO_FETCH
,C_SG_CH2_WORDS_TO_FETCH);
-- LOG2 to get width of counter
constant WORDS2FETCH_BITWIDTH : integer := clog2(FETCH_COUNT);
-- Zero value for counter
constant WORD_ZERO : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0)
:= (others => '0');
-- One value for counter
constant WORD_ONE : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(1,WORDS2FETCH_BITWIDTH));
-- Seven value for counter
constant WORD_SEVEN : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(7,WORDS2FETCH_BITWIDTH));
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal m_axis_mm2s_tready_i : std_logic := '0';
signal ch1_ftch_tready : std_logic := '0';
signal ch2_ftch_tready : std_logic := '0';
-- Misc Signals
signal writing_curdesc : std_logic := '0';
signal fetch_word_count : std_logic_vector
(WORDS2FETCH_BITWIDTH-1 downto 0) := (others => '0');
signal msb_curdesc : std_logic_vector(31 downto 0) := (others => '0');
signal lsbnxtdesc_tready : std_logic := '0';
signal msbnxtdesc_tready : std_logic := '0';
signal nxtdesc_tready : std_logic := '0';
signal ch1_writing_curdesc : std_logic := '0';
signal ch2_writing_curdesc : std_logic := '0';
signal m_axis_ch2_ftch_tvalid_1 : std_logic := '0';
-- KAPIL
signal ch_desc_flush : std_logic := '0';
signal m_axis_ch_ftch_tready : std_logic := '0';
signal ch_ftch_queue_empty : std_logic := '0';
signal ch_ftch_queue_full : std_logic := '0';
signal ch_ftch_pause : std_logic := '0';
signal ch_writing_curdesc : std_logic := '0';
signal ch_ftch_tready : std_logic := '0';
signal m_axis_ch_ftch_tdata : std_logic_vector (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_ch_ftch_tvalid : std_logic := '0';
signal m_axis_ch_ftch_tlast : std_logic := '0';
signal data_concat : std_logic_vector (95 downto 0) := (others => '0');
signal data_concat_64 : std_logic_vector (31 downto 0) := (others => '0');
signal data_concat_64_cdma : std_logic_vector (31 downto 0) := (others => '0');
signal data_concat_mcdma : std_logic_vector (63 downto 0) := (others => '0');
signal next_bd : std_logic_vector (31 downto 0) := (others => '0');
signal data_concat_valid, tvalid_new : std_logic;
signal data_concat_tlast, tlast_new : std_logic;
signal counter : std_logic_vector (C_SG_CH1_WORDS_TO_FETCH-1 downto 0);
signal sof_ftch_desc : std_logic;
signal nxtdesc_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal cyclic_enable : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
cyclic_enable <= ch1_cyclic when ch1_ftch_active = '1' else
ch2_cyclic;
nxtdesc <= nxtdesc_int;
TLAST_GEN : if (C_SG_CH1_WORDS_TO_FETCH = 13) generate
-- TLAST is generated when 8th beat is received
tlast_new <= counter (7) and m_axis_mm2s_tvalid;
tvalid_new <= counter (7) and m_axis_mm2s_tvalid;
SOF_CHECK : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (m_axis_mm2s_tvalid = '1' and m_axis_mm2s_tlast = '1'))then
sof_ftch_desc <= '0';
elsif(counter (6) = '1'
and m_axis_mm2s_tready_i = '1' and m_axis_mm2s_tvalid = '1'
and m_axis_mm2s_tdata(27) = '1' )then
sof_ftch_desc <= '1';
end if;
end if;
end process SOF_CHECK;
end generate TLAST_GEN;
NOTLAST_GEN : if (C_SG_CH1_WORDS_TO_FETCH /= 13) generate
sof_ftch_desc <= '0';
CDMA : if C_ENABLE_CDMA = 1 generate
-- For CDMA TLAST is generated when 7th beat is received
-- because last one is not needed
tlast_new <= counter (6) and m_axis_mm2s_tvalid;
tvalid_new <=counter (6) and m_axis_mm2s_tvalid;
end generate CDMA;
NOCDMA : if C_ENABLE_CDMA = 0 generate
-- For DMA tlast is generated with 8th beat
tlast_new <= counter (7) and m_axis_mm2s_tvalid;
tvalid_new <= counter (7) and m_axis_mm2s_tvalid;
end generate NOCDMA;
end generate NOTLAST_GEN;
-- Following shift register keeps track of number of data beats
-- of BD that is being read
DATA_BEAT_REG : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0' or (m_axis_mm2s_tlast = '1' and m_axis_mm2s_tvalid = '1')) then
counter (0) <= '1';
counter (C_SG_CH1_WORDS_TO_FETCH-1 downto 1) <= (others => '0');
Elsif (m_axis_mm2s_tvalid = '1') then
counter (C_SG_CH1_WORDS_TO_FETCH-1 downto 1) <= counter (C_SG_CH1_WORDS_TO_FETCH-2 downto 0);
counter (0) <= '0';
end if;
end if;
end process DATA_BEAT_REG;
-- Registering the Buffer address from BD, 3rd beat
-- Common for DMA, CDMA
DATA_REG1 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (31 downto 0) <= (others => '0');
Elsif (counter (2) = '1') then
data_concat (31 downto 0) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG1;
ADDR_64BIT : if C_ACTUAL_ADDR = 64 generate
begin
DATA_REG1_64 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_64 (31 downto 0) <= (others => '0');
Elsif (counter (3) = '1') then
data_concat_64 (31 downto 0) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG1_64;
end generate ADDR_64BIT;
ADDR_64BIT2 : if C_ACTUAL_ADDR > 32 and C_ACTUAL_ADDR < 64 generate
begin
DATA_REG1_64 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_64 (C_ACTUAL_ADDR-32-1 downto 0) <= (others => '0');
Elsif (counter (3) = '1') then
data_concat_64 (C_ACTUAL_ADDR-32-1 downto 0) <= m_axis_mm2s_tdata (C_ACTUAL_ADDR-32-1 downto 0);
end if;
end if;
end process DATA_REG1_64;
data_concat_64 (31 downto C_ACTUAL_ADDR-32) <= (others => '0');
end generate ADDR_64BIT2;
DMA_REG2 : if C_ENABLE_CDMA = 0 generate
begin
-- For DMA, the 7th beat has the control information
DATA_REG2 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (63 downto 32) <= (others => '0');
Elsif (counter (6) = '1') then
data_concat (63 downto 32) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG2;
end generate DMA_REG2;
CDMA_REG2 : if C_ENABLE_CDMA = 1 generate
begin
-- For CDMA, the 5th beat has the DA information
DATA_REG2 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (63 downto 32) <= (others => '0');
Elsif (counter (4) = '1') then
data_concat (63 downto 32) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG2;
CDMA_ADDR_64BIT : if C_ACTUAL_ADDR = 64 generate
begin
DATA_REG2_64 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_64_cdma (31 downto 0) <= (others => '0');
Elsif (counter (5) = '1') then
data_concat_64_cdma (31 downto 0) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG2_64;
end generate CDMA_ADDR_64BIT;
CDMA_ADDR_64BIT2 : if C_ACTUAL_ADDR > 32 and C_ACTUAL_ADDR < 64 generate
begin
DATA_REG2_64 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_64_cdma (C_ACTUAL_ADDR-32-1 downto 0) <= (others => '0');
Elsif (counter (5) = '1') then
data_concat_64_cdma (C_ACTUAL_ADDR-32-1 downto 0) <= m_axis_mm2s_tdata (C_ACTUAL_ADDR-32-1 downto 0);
end if;
end if;
end process DATA_REG2_64;
data_concat_64_cdma (31 downto C_ACTUAL_ADDR-32) <= (others => '0');
end generate CDMA_ADDR_64BIT2;
end generate CDMA_REG2;
NOFLOP_FOR_QUEUE : if C_SG_CH1_WORDS_TO_FETCH = 8 generate
begin
-- Last beat is directly concatenated and passed to FIFO
-- Masking the CMPLT bit with cyclic_enable
data_concat (95 downto 64) <= (m_axis_mm2s_tdata(31) and (not cyclic_enable)) & m_axis_mm2s_tdata (30 downto 0);
data_concat_valid <= tvalid_new;
data_concat_tlast <= tlast_new;
end generate NOFLOP_FOR_QUEUE;
-- In absence of queuing option the last beat needs to be floped
FLOP_FOR_NOQUEUE : if C_SG_CH1_WORDS_TO_FETCH = 13 generate
begin
NO_FETCH_Q : if C_SG_FTCH_DESC2QUEUE = 0 generate
DATA_REG3 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (95 downto 64) <= (others => '0');
Elsif (counter (7) = '1') then
data_concat (95 downto 64) <= (m_axis_mm2s_tdata(31) and (not cyclic_enable)) & m_axis_mm2s_tdata (30 downto 0);
end if;
end if;
end process DATA_REG3;
end generate NO_FETCH_Q;
FETCH_Q : if C_SG_FTCH_DESC2QUEUE /= 0 generate
DATA_REG3 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (95) <= '0';
Elsif (counter (7) = '1') then
data_concat (95) <= m_axis_mm2s_tdata (31) and (not cyclic_enable);
end if;
end if;
end process DATA_REG3;
data_concat (94 downto 64) <= (others => '0');
end generate FETCH_Q;
DATA_CNTRL : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_valid <= '0';
data_concat_tlast <= '0';
Else
data_concat_valid <= tvalid_new;
data_concat_tlast <= tlast_new;
end if;
end if;
end process DATA_CNTRL;
end generate FLOP_FOR_NOQUEUE;
-- Since the McDMA BD has two more fields to be captured
-- following procedures are needed
NOMCDMA_FTECH : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
data_concat_mcdma <= (others => '0');
end generate NOMCDMA_FTECH;
MCDMA_BD_FETCH : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
DATA_MCDMA_REG1 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_mcdma (31 downto 0) <= (others => '0');
Elsif (counter (4) = '1') then
data_concat_mcdma (31 downto 0) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_MCDMA_REG1;
DATA_MCDMA_REG2 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_mcdma (63 downto 32) <= (others => '0');
Elsif (counter (5) = '1') then
data_concat_mcdma (63 downto 32) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_MCDMA_REG2;
end generate MCDMA_BD_FETCH;
---------------------------------------------------------------------------
-- For 32-bit SG addresses then drive zero on msb
---------------------------------------------------------------------------
GEN_CURDESC_32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
msb_curdesc <= (others => '0');
end generate GEN_CURDESC_32;
---------------------------------------------------------------------------
-- For 64-bit SG addresses then capture upper order adder to msb
---------------------------------------------------------------------------
GEN_CURDESC_64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
CAPTURE_CURADDR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
msb_curdesc <= (others => '0');
elsif(ftch_cmnd_wr = '1')then
msb_curdesc <= ftch_cmnd_data(DATAMOVER_CMD_ADDRMSB_BOFST
+ C_M_AXI_SG_ADDR_WIDTH
downto DATAMOVER_CMD_ADDRMSB_BOFST
+ DATAMOVER_CMD_ADDRLSB_BIT + 1);
end if;
end if;
end process CAPTURE_CURADDR;
end generate GEN_CURDESC_64;
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_LSB_NXTPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
nxtdesc_int(31 downto 0) <= (others => '0');
-- On valid and word count at 0 and channel active capture LSB next pointer
elsif(m_axis_mm2s_tvalid = '1' and counter (0) = '1')then
nxtdesc_int(31 downto 6) <= m_axis_mm2s_tdata (31 downto 6);
-- BD addresses are always 16 word 32-bit aligned
nxtdesc_int(5 downto 0) <= (others => '0');
end if;
end if;
end process REG_LSB_NXTPNTR;
lsbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1'
and counter (0) = '1' --etch_word_count = WORD_ZERO
else '0';
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_NXTDESC : if C_ACTUAL_ADDR = 64 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_NXTPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
nxtdesc_int(63 downto 32) <= (others => '0');
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
-- Capture upper pointer, drive ready to progress DataMover
-- and also write nxtdesc out
elsif(m_axis_mm2s_tvalid = '1' and counter (1) = '1') then -- etch_word_count = WORD_ONE)then
nxtdesc_int(63 downto 32) <= m_axis_mm2s_tdata;
ch1_nxtdesc_wren <= ch1_ftch_active;
ch2_nxtdesc_wren <= ch2_ftch_active;
-- Assert tready/wren for only 1 clock
else
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
end if;
end if;
end process REG_MSB_NXTPNTR;
msbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1'
and counter (1) = '1' --fetch_word_count = WORD_ONE
else '0';
end generate GEN_UPPER_MSB_NXTDESC;
GEN_UPPER_MSB_NXTDESC2 : if C_ACTUAL_ADDR > 32 and C_ACTUAL_ADDR < 64 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_NXTPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
nxtdesc_int(C_ACTUAL_ADDR-1 downto 32) <= (others => '0');
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
-- Capture upper pointer, drive ready to progress DataMover
-- and also write nxtdesc out
elsif(m_axis_mm2s_tvalid = '1' and counter (1) = '1') then -- etch_word_count = WORD_ONE)then
nxtdesc_int(C_ACTUAL_ADDR-1 downto 32) <= m_axis_mm2s_tdata (C_ACTUAL_ADDR-32-1 downto 0);
ch1_nxtdesc_wren <= ch1_ftch_active;
ch2_nxtdesc_wren <= ch2_ftch_active;
-- Assert tready/wren for only 1 clock
else
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
end if;
end if;
end process REG_MSB_NXTPNTR;
nxtdesc_int (63 downto C_ACTUAL_ADDR) <= (others => '0');
msbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1'
and counter (1) = '1' --fetch_word_count = WORD_ONE
else '0';
end generate GEN_UPPER_MSB_NXTDESC2;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_NXTDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_NXTPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
-- Throw away second word but drive ready to progress DataMover
-- and also write nxtdesc out
elsif(m_axis_mm2s_tvalid = '1' and counter (1) = '1') then --fetch_word_count = WORD_ONE)then
ch1_nxtdesc_wren <= ch1_ftch_active;
ch2_nxtdesc_wren <= ch2_ftch_active;
-- Assert for only 1 clock
else
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
end if;
end if;
end process REG_MSB_NXTPNTR;
msbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1'
and counter (1) = '1' --fetch_word_count = WORD_ONE
else '0';
end generate GEN_NO_UPR_MSB_NXTDESC;
-- Drive ready to DataMover for ether lsb or msb capture
nxtdesc_tready <= msbnxtdesc_tready or lsbnxtdesc_tready;
-- Generate logic for checking stale descriptor
GEN_STALE_DESC_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 1 or C_SG_CH2_ENBL_STALE_ERROR = 1 generate
begin
---------------------------------------------------------------------------
-- Examine Completed BIT to determine if stale descriptor fetched
---------------------------------------------------------------------------
CMPLTD_CHECK : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
ftch_stale_desc <= '0';
-- On valid and word count at 0 and channel active capture LSB next pointer
elsif(m_axis_mm2s_tvalid = '1' and counter (7) = '1' --fetch_word_count = WORD_SEVEN
and m_axis_mm2s_tready_i = '1'
and m_axis_mm2s_tdata(DESC_STS_CMPLTD_BIT) = '1' )then
ftch_stale_desc <= '1' and (not cyclic_enable);
else
ftch_stale_desc <= '0';
end if;
end if;
end process CMPLTD_CHECK;
end generate GEN_STALE_DESC_CHECK;
-- No needed logic for checking stale descriptor
GEN_NO_STALE_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 0 and C_SG_CH2_ENBL_STALE_ERROR = 0 generate
begin
ftch_stale_desc <= '0';
end generate GEN_NO_STALE_CHECK;
---------------------------------------------------------------------------
-- SG Queueing therefore pass stream signals to
-- FIFO
---------------------------------------------------------------------------
GEN_QUEUE : if C_SG_FTCH_DESC2QUEUE /= 0 generate
begin
-- Instantiate the queue version
FTCH_QUEUE_I : entity axi_sg_v4_1_3.axi_sg_ftch_queue
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => C_SG_FTCH_DESC2QUEUE ,
C_SG_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_ASYNC => C_ASYNC ,
C_FAMILY => C_FAMILY ,
C_SG2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_INCLUDE_MM2S => C_INCLUDE_CH1,
C_INCLUDE_S2MM => C_INCLUDE_CH2,
C_ENABLE_CDMA => C_ENABLE_CDMA,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_primary_aclk => m_axi_mm2s_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
p_reset_n => p_reset_n ,
ch2_sg_idle => '0' ,
-- Channel Control
desc1_flush => ch1_desc_flush ,
desc2_flush => ch2_desc_flush ,
ch1_cntrl_strm_stop => ch1_cntrl_strm_stop ,
ftch1_active => ch1_ftch_active ,
ftch2_active => ch2_ftch_active ,
ftch1_queue_empty => ch1_ftch_queue_empty ,
ftch2_queue_empty => ch2_ftch_queue_empty ,
ftch1_queue_full => ch1_ftch_queue_full ,
ftch2_queue_full => ch2_ftch_queue_full ,
ftch1_pause => ch1_ftch_pause ,
ftch2_pause => ch2_ftch_pause ,
writing_nxtdesc_in => nxtdesc_tready ,
writing1_curdesc_out => ch1_writing_curdesc ,
writing2_curdesc_out => ch2_writing_curdesc ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
-- MM2S Stream In from DataMover
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
sof_ftch_desc => sof_ftch_desc ,
next_bd => nxtdesc_int ,
data_concat_64 => data_concat_64,
data_concat_64_cdma => data_concat_64_cdma,
data_concat => data_concat,
data_concat_mcdma => data_concat_mcdma,
data_concat_valid => data_concat_valid,
data_concat_tlast => data_concat_tlast,
m_axis1_mm2s_tready => ch1_ftch_tready ,
m_axis2_mm2s_tready => ch2_ftch_tready ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ftch_aclk => m_axi_sg_aclk, --m_axis_ch_ftch_aclk ,
m_axis_ftch1_tdata => m_axis_ch1_ftch_tdata ,
m_axis_ftch1_tvalid => m_axis_ch1_ftch_tvalid ,
m_axis_ftch1_tready => m_axis_ch1_ftch_tready ,
m_axis_ftch1_tlast => m_axis_ch1_ftch_tlast ,
m_axis_ftch1_tdata_new => m_axis_ch1_ftch_tdata_new ,
m_axis_ftch1_tdata_mcdma_new => m_axis_ch1_ftch_tdata_mcdma_new ,
m_axis_ftch1_tvalid_new => m_axis_ch1_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available ,
m_axis_ftch2_tdata_new => m_axis_ch2_ftch_tdata_new ,
m_axis_ftch2_tdata_mcdma_new => m_axis_ch2_ftch_tdata_mcdma_new ,
m_axis_ftch2_tvalid_new => m_axis_ch2_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available ,
m_axis_ftch2_tdata => m_axis_ch2_ftch_tdata ,
m_axis_ftch2_tvalid => m_axis_ch2_ftch_tvalid ,
m_axis_ftch2_tready => m_axis_ch2_ftch_tready ,
m_axis_ftch2_tlast => m_axis_ch2_ftch_tlast ,
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
m_axis_ch2_ftch_tdata_mcdma_nxt <= (others => '0');
end generate GEN_QUEUE;
-- No SG Queueing therefore pass stream signals straight
-- out channel port
-- No SG Queueing therefore pass stream signals straight
-- out channel port
GEN_NO_QUEUE : if C_SG_FTCH_DESC2QUEUE = 0 generate
begin
-- Instantiate the No queue version
NO_FTCH_QUEUE_I : entity axi_sg_v4_1_3.axi_sg_ftch_noqueue
generic map (
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_ASYNC => C_ASYNC ,
C_FAMILY => C_FAMILY ,
C_SG_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_ENABLE_CDMA => C_ENABLE_CDMA,
C_ENABLE_CH1 => C_INCLUDE_CH1
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_primary_aclk => m_axi_mm2s_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
p_reset_n => p_reset_n ,
-- Channel Control
desc_flush => ch1_desc_flush ,
ch1_cntrl_strm_stop => ch1_cntrl_strm_stop ,
ftch_active => ch1_ftch_active ,
ftch_queue_empty => ch1_ftch_queue_empty ,
ftch_queue_full => ch1_ftch_queue_full ,
desc2_flush => ch2_desc_flush ,
ftch2_active => ch2_ftch_active ,
ftch2_queue_empty => ch2_ftch_queue_empty ,
ftch2_queue_full => ch2_ftch_queue_full ,
writing_nxtdesc_in => nxtdesc_tready ,
writing_curdesc_out => ch1_writing_curdesc ,
writing2_curdesc_out => ch2_writing_curdesc ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
-- MM2S Stream In from DataMover
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => ch1_ftch_tready ,
m_axis2_mm2s_tready => ch2_ftch_tready ,
sof_ftch_desc => sof_ftch_desc ,
next_bd => nxtdesc_int ,
data_concat_64 => data_concat_64,
data_concat => data_concat,
data_concat_mcdma => data_concat_mcdma,
data_concat_valid => data_concat_valid,
data_concat_tlast => data_concat_tlast,
-- Channel 1 AXI Fetch Stream Out
m_axis_ftch_tdata => m_axis_ch1_ftch_tdata ,
m_axis_ftch_tvalid => m_axis_ch1_ftch_tvalid ,
m_axis_ftch_tready => m_axis_ch1_ftch_tready ,
m_axis_ftch_tlast => m_axis_ch1_ftch_tlast ,
m_axis_ftch_tdata_new => m_axis_ch1_ftch_tdata_new ,
m_axis_ftch_tdata_mcdma_new => m_axis_ch1_ftch_tdata_mcdma_new ,
m_axis_ftch_tvalid_new => m_axis_ch1_ftch_tvalid_new ,
m_axis_ftch_desc_available => m_axis_ftch1_desc_available ,
m_axis2_ftch_tdata_new => m_axis_ch2_ftch_tdata_new ,
m_axis2_ftch_tdata_mcdma_new => m_axis_ch2_ftch_tdata_mcdma_new ,
m_axis2_ftch_tdata_mcdma_nxt => m_axis_ch2_ftch_tdata_mcdma_nxt ,
m_axis2_ftch_tvalid_new => m_axis_ch2_ftch_tvalid_new ,
m_axis2_ftch_desc_available => m_axis_ftch2_desc_available ,
m_axis2_ftch_tdata => m_axis_ch2_ftch_tdata ,
m_axis2_ftch_tvalid => m_axis_ch2_ftch_tvalid ,
m_axis2_ftch_tready => m_axis_ch2_ftch_tready ,
m_axis2_ftch_tlast => m_axis_ch2_ftch_tlast ,
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
ch1_ftch_pause <= '0';
ch2_ftch_pause <= '0';
end generate GEN_NO_QUEUE;
-------------------------------------------------------------------------------
-- DataMover TREADY MUX
-------------------------------------------------------------------------------
writing_curdesc <= ch1_writing_curdesc or ch2_writing_curdesc or ftch_cmnd_wr;
TREADY_MUX : process(writing_curdesc,
fetch_word_count,
nxtdesc_tready,
-- channel 1 signals
ch1_ftch_active,
ch1_desc_flush,
ch1_ftch_tready,
-- channel 2 signals
ch2_ftch_active,
ch2_desc_flush,
counter(0),
counter(1),
ch2_ftch_tready)
begin
-- If commmanded to flush descriptor then assert ready
-- to datamover until active de-asserts. this allows
-- any commanded fetches to complete.
if( (ch1_desc_flush = '1' and ch1_ftch_active = '1')
or(ch2_desc_flush = '1' and ch2_ftch_active = '1'))then
m_axis_mm2s_tready_i <= '1';
-- NOT ready if cmnd being written because
-- curdesc gets written to queue
elsif(writing_curdesc = '1')then
m_axis_mm2s_tready_i <= '0';
-- First two words drive ready from internal logic
elsif(counter(0) = '1' or counter(1)='1')then
m_axis_mm2s_tready_i <= nxtdesc_tready;
-- Remainder stream words drive ready from channel input
else
m_axis_mm2s_tready_i <= (ch1_ftch_active and ch1_ftch_tready)
or (ch2_ftch_active and ch2_ftch_tready);
end if;
end process TREADY_MUX;
m_axis_mm2s_tready <= m_axis_mm2s_tready_i;
end implementation;
|
mit
|
Bjay1435/capstone
|
Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_s2mm_dre.vhd
|
5
|
89008
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_dre.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_dre.vhd
--
-- Description:
-- This VHDL design implements a 64 bit wide (8 byte lane) function that
-- realigns an arbitrarily aligned input data stream to an arbitrarily aligned
-- output data stream.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_dre_mux8_1_x_n;
use axi_datamover_v5_1_11.axi_datamover_dre_mux4_1_x_n;
use axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_dre is
Generic (
C_DWIDTH : Integer := 64;
-- Sets the native data width of the DRE
C_ALIGN_WIDTH : Integer := 3
-- Sets the width of the alignment control inputs
-- Should be log2(C_DWIDTH)
);
port (
-- Clock and Reset Input ----------------------------------------------
--
dre_clk : In std_logic; --
dre_rst : In std_logic; --
----------------------------------------------------------------------
-- Alignment Control (Independent from Stream Input timing) ----------
--
dre_align_ready : Out std_logic; --
dre_align_valid : In std_logic; --
dre_use_autodest : In std_logic; --
dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
----------------------------------------------------------------------
-- Flush Control (Aligned to input Stream timing) --------------------
--
dre_flush : In std_logic; --
----------------------------------------------------------------------
-- Stream Input Channel ----------------------------------------------
--
dre_in_tstrb : In std_logic_vector((C_DWIDTH/8)-1 downto 0); --
dre_in_tdata : In std_logic_vector(C_DWIDTH-1 downto 0); --
dre_in_tlast : In std_logic; --
dre_in_tvalid : In std_logic; --
dre_in_tready : Out std_logic; --
----------------------------------------------------------------------
-- Stream Output Channel ---------------------------------------------
--
dre_out_tstrb : Out std_logic_vector((C_DWIDTH/8)-1 downto 0); --
dre_out_tdata : Out std_logic_vector(C_DWIDTH-1 downto 0); --
dre_out_tlast : Out std_logic; --
dre_out_tvalid : Out std_logic; --
dre_out_tready : In std_logic --
----------------------------------------------------------------------
);
end entity axi_datamover_s2mm_dre;
architecture implementation of axi_datamover_s2mm_dre is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_start_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the MSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_start_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_start : Integer := 0;
begin
bit_index_start := lane_index*lane_width;
return(bit_index_start);
end function get_start_index;
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_end_index
--
-- Function Description:
-- This function calculates the bus bit index corresponding
-- to the LSB of the Slice lane index input and the Slice width.
--
-------------------------------------------------------------------
function get_end_index (lane_index : integer;
lane_width : integer)
return integer is
Variable bit_index_end : Integer := 0;
begin
bit_index_end := (lane_index*lane_width) + (lane_width-1);
return(bit_index_end);
end function get_end_index;
-- Constants
Constant BYTE_WIDTH : integer := 8; -- bits
Constant DATA_WIDTH_BYTES : integer := C_DWIDTH/BYTE_WIDTH;
Constant SLICE_WIDTH : integer := BYTE_WIDTH+2; -- 8 data bits plus Strobe plus TLAST bit
Constant SLICE_STROBE_INDEX : integer := (BYTE_WIDTH-1)+1;
Constant SLICE_TLAST_INDEX : integer := SLICE_STROBE_INDEX+1;
Constant ZEROED_SLICE : std_logic_vector(SLICE_WIDTH-1 downto 0) := (others => '0');
Constant NUM_BYTE_LANES : integer := C_DWIDTH/BYTE_WIDTH;
Constant ALIGN_VECT_WIDTH : integer := C_ALIGN_WIDTH;
Constant NO_STRB_SET_VALUE : integer := 0;
-- Types
type sig_byte_lane_type is array(DATA_WIDTH_BYTES-1 downto 0) of
std_logic_vector(SLICE_WIDTH-1 downto 0);
-- Signals
signal sig_input_data_reg : sig_byte_lane_type;
signal sig_delay_data_reg : sig_byte_lane_type;
signal sig_output_data_reg : sig_byte_lane_type;
signal sig_pass_mux_bus : sig_byte_lane_type;
signal sig_delay_mux_bus : sig_byte_lane_type;
signal sig_final_mux_bus : sig_byte_lane_type;
Signal sig_dre_strb_out_i : std_logic_vector(DATA_WIDTH_BYTES-1 downto 0) := (others => '0');
Signal sig_dre_data_out_i : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
Signal sig_dest_align_i : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_dre_flush_i : std_logic := '0';
Signal sig_pipeline_halt : std_logic := '0';
Signal sig_dre_tvalid_i : std_logic := '0';
Signal sig_input_accept : std_logic := '0';
Signal sig_tlast_enables : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
signal sig_final_mux_has_tlast : std_logic := '0';
signal sig_tlast_out : std_logic := '0';
Signal sig_tlast_strobes : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
Signal sig_next_auto_dest : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_current_dest_align : std_logic_vector(ALIGN_VECT_WIDTH-1 downto 0) := (others => '0');
Signal sig_last_written_strb : std_logic_vector(NUM_BYTE_LANES-1 downto 0) := (others => '0');
Signal sig_auto_flush : std_logic := '0';
Signal sig_flush_db1 : std_logic := '0';
Signal sig_flush_db2 : std_logic := '0';
signal sig_flush_db1_complete : std_logic := '0';
signal sig_flush_db2_complete : std_logic := '0';
signal sig_output_xfer : std_logic := '0';
signal sig_advance_pipe_data : std_logic := '0';
Signal sig_flush_reg : std_logic := '0';
Signal sig_input_flush_stall : std_logic := '0';
Signal sig_cntl_accept : std_logic := '0';
Signal sig_dre_halted : std_logic := '0';
begin --(architecture implementation)
-- Misc port assignments
dre_align_ready <= sig_dre_halted or
sig_flush_db2_complete ;
dre_in_tready <= sig_input_accept ;
dre_out_tstrb <= sig_dre_strb_out_i ;
dre_out_tdata <= sig_dre_data_out_i ;
dre_out_tvalid <= sig_dre_tvalid_i ;
dre_out_tlast <= sig_tlast_out ;
-- Internal logic
sig_cntl_accept <= dre_align_valid and
(sig_dre_halted or
sig_flush_db2_complete);
sig_pipeline_halt <= sig_dre_halted or
(sig_dre_tvalid_i and
not(dre_out_tready));
sig_output_xfer <= sig_dre_tvalid_i and
dre_out_tready;
sig_advance_pipe_data <= (dre_in_tvalid or
sig_dre_flush_i) and
not(sig_pipeline_halt);
sig_dre_flush_i <= sig_auto_flush ;
sig_input_accept <= dre_in_tvalid and
not(sig_pipeline_halt) and
not(sig_input_flush_stall);
sig_flush_db1_complete <= sig_flush_db1 and
not(sig_pipeline_halt);
sig_flush_db2_complete <= sig_flush_db2 and
not(sig_pipeline_halt);
sig_auto_flush <= sig_flush_db1 or
sig_flush_db2;
sig_input_flush_stall <= sig_auto_flush; -- commanded flush needed for concatonation
sig_last_written_strb <= sig_dre_strb_out_i;
------------------------------------------------------------------------------------
-- DRE Halted logic
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DRE_HALTED_FLOP
--
-- Process Description:
-- Implements a flop for the Halted state flag. All DRE
-- operation is halted until a new alignment control is
-- loaded. The DRE automatically goes into halted state
-- at reset and at completion of a flush operation.
--
-------------------------------------------------------------
IMP_DRE_HALTED_FLOP : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or
(sig_flush_db2_complete = '1' and
dre_align_valid = '0'))then
sig_dre_halted <= '1'; -- default to halted state
elsif (sig_cntl_accept = '1') then
sig_dre_halted <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_DRE_HALTED_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_FLUSH_IN
--
-- Process Description:
-- Input Register for the flush command
--
-------------------------------------------------------------
REG_FLUSH_IN : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or
sig_flush_db2 = '1') then
sig_flush_reg <= '0';
elsif (sig_input_accept = '1') then
sig_flush_reg <= dre_flush;
else
null; -- hold current state
end if;
end if;
end process REG_FLUSH_IN;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_FINAL_MUX_TLAST_OR
--
-- Process Description:
-- Look at all associated tlast bits in the Final Mux output
-- and detirmine if any are set.
--
--
-------------------------------------------------------------
DO_FINAL_MUX_TLAST_OR : process (sig_final_mux_bus)
Variable lvar_finalmux_or : std_logic_vector(NUM_BYTE_LANES-1 downto 0);
begin
lvar_finalmux_or(0) := sig_final_mux_bus(0)(SLICE_TLAST_INDEX);
for tlast_index in 1 to NUM_BYTE_LANES-1 loop
lvar_finalmux_or(tlast_index) :=
lvar_finalmux_or(tlast_index-1) or
sig_final_mux_bus(tlast_index)(SLICE_TLAST_INDEX);
end loop;
sig_final_mux_has_tlast <= lvar_finalmux_or(NUM_BYTE_LANES-1);
end process DO_FINAL_MUX_TLAST_OR;
------------------------------------------------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_FLUSH_DB1
--
-- Process Description:
-- Creates the first sequential flag indicating that the DRE needs to flush out
-- current contents before allowing any new inputs. This is
-- triggered by the receipt of the TLAST.
--
-------------------------------------------------------------
GEN_FLUSH_DB1 : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
If (dre_rst = '1' or
sig_flush_db2_complete = '1') Then
sig_flush_db1 <= '0';
Elsif (sig_input_accept = '1') Then
sig_flush_db1 <= dre_flush or dre_in_tlast;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_FLUSH_DB1;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_FLUSH_DB2
--
-- Process Description:
-- Creates a second sequential flag indicating that the DRE
-- is flushing out current contents. This is
-- triggered by the assertion of the first sequential flush
-- flag.
--
-------------------------------------------------------------
GEN_FLUSH_DB2 : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
If (dre_rst = '1' or
sig_flush_db2_complete = '1') Then
sig_flush_db2 <= '0';
elsif (sig_pipeline_halt = '0') then
sig_flush_db2 <= sig_flush_db1;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_FLUSH_DB2;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CALC_DEST_STRB_ALIGN
--
-- Process Description:
-- This process calculates the byte lane position of the
-- left-most STRB that is unasserted on the DRE output STRB bus.
-- The resulting value is used as the Destination Alignment
-- Vector for the DRE.
--
-------------------------------------------------------------
CALC_DEST_STRB_ALIGN : process (sig_last_written_strb)
Variable lvar_last_strb_hole_position : Integer range 0 to NUM_BYTE_LANES;
Variable lvar_strb_hole_detected : Boolean;
Variable lvar_first_strb_assert_found : Boolean;
Variable lvar_loop_count : integer range 0 to NUM_BYTE_LANES;
Begin
lvar_loop_count := NUM_BYTE_LANES;
lvar_last_strb_hole_position := 0;
lvar_strb_hole_detected := FALSE;
lvar_first_strb_assert_found := FALSE;
-- Search through the output STRB bus starting with the MSByte
while (lvar_loop_count > 0) loop
If (sig_last_written_strb(lvar_loop_count-1) = '0' and
lvar_first_strb_assert_found = FALSE) Then
lvar_strb_hole_detected := TRUE;
lvar_last_strb_hole_position := lvar_loop_count-1;
Elsif (sig_last_written_strb(lvar_loop_count-1) = '1') Then
lvar_first_strb_assert_found := true;
else
null; -- do nothing
End if;
lvar_loop_count := lvar_loop_count - 1;
End loop;
-- now assign the encoder output value to the bit position of the last Strobe encountered
If (lvar_strb_hole_detected) Then
sig_current_dest_align <= STD_LOGIC_VECTOR(TO_UNSIGNED(lvar_last_strb_hole_position, ALIGN_VECT_WIDTH));
else
sig_current_dest_align <= STD_LOGIC_VECTOR(TO_UNSIGNED(NO_STRB_SET_VALUE, ALIGN_VECT_WIDTH));
End if;
end process CALC_DEST_STRB_ALIGN;
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
-- For Generate
--
-- Label: FORMAT_OUTPUT_DATA_STRB
--
-- For Generate Description:
-- Connect the output Data and Strobe ports to the appropriate
-- bits in the sig_output_data_reg.
--
------------------------------------------------------------
FORMAT_OUTPUT_DATA_STRB : for byte_lane_index in 0 to NUM_BYTE_LANES-1 generate
begin
sig_dre_data_out_i(get_end_index(byte_lane_index, BYTE_WIDTH) downto
get_start_index(byte_lane_index, BYTE_WIDTH)) <=
sig_output_data_reg(byte_lane_index)(BYTE_WIDTH-1 downto 0);
sig_dre_strb_out_i(byte_lane_index) <=
sig_output_data_reg(byte_lane_index)(SLICE_WIDTH-2);
end generate FORMAT_OUTPUT_DATA_STRB;
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
---------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_INPUT_REG
--
-- For Generate Description:
--
-- Implements a programble number of input register slices.
--
--
------------------------------------------------------------
GEN_INPUT_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_INPUTREG_SLICE
--
-- Process Description:
-- Implement a single register slice for the Input Register.
--
-------------------------------------------------------------
DO_INPUTREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or
sig_flush_db1_complete = '1' or -- clear on reset or if
(dre_in_tvalid = '1' and
sig_pipeline_halt = '0' and -- the pipe is being advanced and
dre_in_tstrb(slice_index) = '0')) then -- no new valid data id being loaded
sig_input_data_reg(slice_index) <= ZEROED_SLICE;
elsif (dre_in_tstrb(slice_index) = '1' and
sig_input_accept = '1') then
sig_input_data_reg(slice_index) <= sig_tlast_enables(slice_index) &
dre_in_tstrb(slice_index) &
dre_in_tdata((slice_index*8)+7 downto slice_index*8);
else
null; -- don't change state
end if;
end if;
end process DO_INPUTREG_SLICE;
end generate GEN_INPUT_REG;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_DELAY_REG
--
-- For Generate Description:
--
-- Implements a programble number of output register slices
--
--
------------------------------------------------------------
GEN_DELAY_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DELAYREG_SLICE
--
-- Process Description:
-- Implement a single register slice
--
-------------------------------------------------------------
DO_DELAYREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or -- clear on reset or if
(sig_advance_pipe_data = '1' and -- the pipe is being advanced and
sig_delay_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '0')) then -- no new valid data id being loaded
sig_delay_data_reg(slice_index) <= ZEROED_SLICE;
elsif (sig_delay_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '1' and
sig_advance_pipe_data = '1') then
sig_delay_data_reg(slice_index) <= sig_delay_mux_bus(slice_index);
else
null; -- don't change state
end if;
end if;
end process DO_DELAYREG_SLICE;
end generate GEN_DELAY_REG;
------------------------------------------------------------
-- For Generate
--
-- Label: GEN_OUTPUT_REG
--
-- For Generate Description:
--
-- Implements a programble number of output register slices
--
--
------------------------------------------------------------
GEN_OUTPUT_REG : for slice_index in 0 to NUM_BYTE_LANES-1 generate
begin
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_OUTREG_SLICE
--
-- Process Description:
-- Implement a single register slice
--
-------------------------------------------------------------
DO_OUTREG_SLICE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1' or -- clear on reset or if
(sig_output_xfer = '1' and -- the output is being transfered and
sig_final_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '0')) then -- no new valid data id being loaded
sig_output_data_reg(slice_index) <= ZEROED_SLICE;
elsif (sig_final_mux_bus(slice_index)(SLICE_STROBE_INDEX) = '1' and
sig_advance_pipe_data = '1') then
sig_output_data_reg(slice_index) <= sig_final_mux_bus(slice_index);
else
null; -- don't change state
end if;
end if;
end process DO_OUTREG_SLICE;
end generate GEN_OUTPUT_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_TVALID
--
-- Process Description:
-- This sync process generates the Write request for the
-- destination interface.
--
-------------------------------------------------------------
GEN_TVALID : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_dre_tvalid_i <= '0';
elsif (sig_advance_pipe_data = '1') then
sig_dre_tvalid_i <= sig_final_mux_bus(NUM_BYTE_LANES-1)(SLICE_STROBE_INDEX) or -- MS Strobe is set or
sig_final_mux_has_tlast; -- the Last data beat of a packet
Elsif (dre_out_tready = '1' and -- a completed write but no
sig_dre_tvalid_i = '1') Then -- new input data so clear
-- until more input data shows up
sig_dre_tvalid_i <= '0';
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_TVALID;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: GEN_TLAST_OUT
--
-- Process Description:
-- This sync process generates the TLAST output for the
-- destination interface.
--
-------------------------------------------------------------
GEN_TLAST_OUT : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_tlast_out <= '0';
elsif (sig_advance_pipe_data = '1') then
sig_tlast_out <= sig_final_mux_has_tlast;
Elsif (dre_out_tready = '1' and -- a completed transfer
sig_dre_tvalid_i = '1') Then -- so clear tlast
sig_tlast_out <= '0';
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process GEN_TLAST_OUT;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_64
--
-- If Generate Description:
-- Support Logic and Mux Farm for 64-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_64 : if (C_DWIDTH = 64) generate
Signal s_case_i_64 : Integer range 0 to 7 := 0;
signal sig_cntl_state_64 : std_logic_vector(5 downto 0) := (others => '0');
Signal sig_shift_case_i : std_logic_vector(2 downto 0) := (others => '0');
Signal sig_shift_case_reg : std_logic_vector(2 downto 0) := (others => '0');
Signal sig_final_mux_sel : std_logic_vector(7 downto 0) := (others => '0');
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_8
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_8 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(7 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "00000000";
elsif (sig_tlast_strobes(7) = '1') then
sig_tlast_enables <= "10000000";
elsif (sig_tlast_strobes(6) = '1') then
sig_tlast_enables <= "01000000";
elsif (sig_tlast_strobes(5) = '1') then
sig_tlast_enables <= "00100000";
elsif (sig_tlast_strobes(4) = '1') then
sig_tlast_enables <= "00010000";
elsif (sig_tlast_strobes(3) = '1') then
sig_tlast_enables <= "00001000";
elsif (sig_tlast_strobes(2) = '1') then
sig_tlast_enables <= "00000100";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "00000010";
else
sig_tlast_enables <= "00000001";
end if;
end process FIND_MS_STRB_SET_8;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to sld_logic_vector
--sig_shift_case_i <= CONV_STD_LOGIC_VECTOR(s_case_i_64, 3);
sig_shift_case_i <= STD_LOGIC_VECTOR(TO_UNSIGNED(s_case_i_64, 3));
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_64
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_64 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_64)
begin
sig_cntl_state_64 <= dre_src_align & sig_dest_align_i;
case sig_cntl_state_64 is
when "000000" =>
s_case_i_64 <= 0;
when "000001" =>
s_case_i_64 <= 7;
when "000010" =>
s_case_i_64 <= 6;
when "000011" =>
s_case_i_64 <= 5;
when "000100" =>
s_case_i_64 <= 4;
when "000101" =>
s_case_i_64 <= 3;
when "000110" =>
s_case_i_64 <= 2;
when "000111" =>
s_case_i_64 <= 1;
when "001000" =>
s_case_i_64 <= 1;
when "001001" =>
s_case_i_64 <= 0;
when "001010" =>
s_case_i_64 <= 7;
when "001011" =>
s_case_i_64 <= 6;
when "001100" =>
s_case_i_64 <= 5;
when "001101" =>
s_case_i_64 <= 4;
when "001110" =>
s_case_i_64 <= 3;
when "001111" =>
s_case_i_64 <= 2;
when "010000" =>
s_case_i_64 <= 2;
when "010001" =>
s_case_i_64 <= 1;
when "010010" =>
s_case_i_64 <= 0;
when "010011" =>
s_case_i_64 <= 7;
when "010100" =>
s_case_i_64 <= 6;
when "010101" =>
s_case_i_64 <= 5;
when "010110" =>
s_case_i_64 <= 4;
when "010111" =>
s_case_i_64 <= 3;
when "011000" =>
s_case_i_64 <= 3;
when "011001" =>
s_case_i_64 <= 2;
when "011010" =>
s_case_i_64 <= 1;
when "011011" =>
s_case_i_64 <= 0;
when "011100" =>
s_case_i_64 <= 7;
when "011101" =>
s_case_i_64 <= 6;
when "011110" =>
s_case_i_64 <= 5;
when "011111" =>
s_case_i_64 <= 4;
when "100000" =>
s_case_i_64 <= 4;
when "100001" =>
s_case_i_64 <= 3;
when "100010" =>
s_case_i_64 <= 2;
when "100011" =>
s_case_i_64 <= 1;
when "100100" =>
s_case_i_64 <= 0;
when "100101" =>
s_case_i_64 <= 7;
when "100110" =>
s_case_i_64 <= 6;
when "100111" =>
s_case_i_64 <= 5;
when "101000" =>
s_case_i_64 <= 5;
when "101001" =>
s_case_i_64 <= 4;
when "101010" =>
s_case_i_64 <= 3;
when "101011" =>
s_case_i_64 <= 2;
when "101100" =>
s_case_i_64 <= 1;
when "101101" =>
s_case_i_64 <= 0;
when "101110" =>
s_case_i_64 <= 7;
when "101111" =>
s_case_i_64 <= 6;
when "110000" =>
s_case_i_64 <= 6;
when "110001" =>
s_case_i_64 <= 5;
when "110010" =>
s_case_i_64 <= 4;
when "110011" =>
s_case_i_64 <= 3;
when "110100" =>
s_case_i_64 <= 2;
when "110101" =>
s_case_i_64 <= 1;
when "110110" =>
s_case_i_64 <= 0;
when "110111" =>
s_case_i_64 <= 7;
when "111000" =>
s_case_i_64 <= 7;
when "111001" =>
s_case_i_64 <= 6;
when "111010" =>
s_case_i_64 <= 5;
when "111011" =>
s_case_i_64 <= 4;
when "111100" =>
s_case_i_64 <= 3;
when "111101" =>
s_case_i_64 <= 2;
when "111110" =>
s_case_i_64 <= 1;
when "111111" =>
s_case_i_64 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_64;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= (others => '0');
elsif (sig_cntl_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(1),
I1 => sig_input_data_reg(0),
Y => sig_pass_mux_bus(1)
);
-- Pass Mux Byte 2 (4-1 x8 Mux)
I_MUX4_1_PASS_B2 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(2) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
Y => sig_pass_mux_bus(2)
);
-- Pass Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_PASS_B3 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(3) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
Y => sig_pass_mux_bus(3)
);
-- Pass Mux Byte 4 (8-1 x8 Mux)
I_MUX8_1_PASS_B4 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(4) ,
I1 => ZEROED_SLICE ,
I2 => ZEROED_SLICE ,
I3 => ZEROED_SLICE ,
I4 => sig_input_data_reg(0) ,
I5 => sig_input_data_reg(1) ,
I6 => sig_input_data_reg(2) ,
I7 => sig_input_data_reg(3) ,
Y => sig_pass_mux_bus(4)
);
-- Pass Mux Byte 5 (8-1 x8 Mux)
I_MUX8_1_PASS_B5 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(5) ,
I1 => ZEROED_SLICE ,
I2 => ZEROED_SLICE ,
I3 => sig_input_data_reg(0) ,
I4 => sig_input_data_reg(1) ,
I5 => sig_input_data_reg(2) ,
I6 => sig_input_data_reg(3) ,
I7 => sig_input_data_reg(4) ,
Y => sig_pass_mux_bus(5)
);
-- Pass Mux Byte 6 (8-1 x8 Mux)
I_MUX8_1_PASS_B6 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(6) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
I4 => sig_input_data_reg(2) ,
I5 => sig_input_data_reg(3) ,
I6 => sig_input_data_reg(4) ,
I7 => sig_input_data_reg(5) ,
Y => sig_pass_mux_bus(6)
);
-- Pass Mux Byte 7 (8-1 x8 Mux)
I_MUX8_1_PASS_B7 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => sig_input_data_reg(7) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
I4 => sig_input_data_reg(3) ,
I5 => sig_input_data_reg(4) ,
I6 => sig_input_data_reg(5) ,
I7 => sig_input_data_reg(6) ,
Y => sig_pass_mux_bus(7)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Byte 0 (8-1 x8 Mux)
I_MUX8_1_DLY_B0 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0) ,
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(1) ,
I2 => sig_input_data_reg(2) ,
I3 => sig_input_data_reg(3) ,
I4 => sig_input_data_reg(4) ,
I5 => sig_input_data_reg(5) ,
I6 => sig_input_data_reg(6) ,
I7 => sig_input_data_reg(7) ,
Y => sig_delay_mux_bus(0)
);
-- Delay Mux Byte 1 (8-1 x8 Mux)
I_MUX8_1_DLY_B1 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(2) ,
I2 => sig_input_data_reg(3) ,
I3 => sig_input_data_reg(4) ,
I4 => sig_input_data_reg(5) ,
I5 => sig_input_data_reg(6) ,
I6 => sig_input_data_reg(7) ,
I7 => ZEROED_SLICE ,
Y => sig_delay_mux_bus(1)
);
-- Delay Mux Byte 2 (8-1 x8 Mux)
I_MUX8_1_DLY_B2 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux8_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(2 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(3) ,
I2 => sig_input_data_reg(4) ,
I3 => sig_input_data_reg(5) ,
I4 => sig_input_data_reg(6) ,
I5 => sig_input_data_reg(7) ,
I6 => ZEROED_SLICE ,
I7 => ZEROED_SLICE ,
Y => sig_delay_mux_bus(2)
);
-- Delay Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_DLY_B3 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(7) ,
I1 => sig_input_data_reg(4) ,
I2 => sig_input_data_reg(5) ,
I3 => sig_input_data_reg(6) ,
Y => sig_delay_mux_bus(3)
);
-- Delay Mux Byte 4 (4-1 x8 Mux)
I_MUX4_1_DLY_B4 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(5) ,
I2 => sig_input_data_reg(6) ,
I3 => sig_input_data_reg(7) ,
Y => sig_delay_mux_bus(4)
);
-- Delay Mux Byte 5 (2-1 x8 Mux)
I_MUX2_1_DLY_B5 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH -- : Integer := 8
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(7),
I1 => sig_input_data_reg(6),
Y => sig_delay_mux_bus(5)
);
-- Delay Mux Byte 6 (Wire)
sig_delay_mux_bus(6) <= sig_input_data_reg(7);
-- Delay Mux Byte 7 (Zeroed)
sig_delay_mux_bus(7) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Byte 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(0) <= '0';
when "001" =>
sig_final_mux_sel(0) <= '1';
when "010" =>
sig_final_mux_sel(0) <= '1';
when "011" =>
sig_final_mux_sel(0) <= '1';
when "100" =>
sig_final_mux_sel(0) <= '1';
when "101" =>
sig_final_mux_sel(0) <= '1';
when "110" =>
sig_final_mux_sel(0) <= '1';
when "111" =>
sig_final_mux_sel(0) <= '1';
when others =>
sig_final_mux_sel(0) <= '0';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_input_data_reg(0),
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Byte 1 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B1_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 1 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B1_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(1) <= '0';
when "001" =>
sig_final_mux_sel(1) <= '1';
when "010" =>
sig_final_mux_sel(1) <= '1';
when "011" =>
sig_final_mux_sel(1) <= '1';
when "100" =>
sig_final_mux_sel(1) <= '1';
when "101" =>
sig_final_mux_sel(1) <= '1';
when "110" =>
sig_final_mux_sel(1) <= '1';
when "111" =>
sig_final_mux_sel(1) <= '0';
when others =>
sig_final_mux_sel(1) <= '0';
end case;
end process MUX2_1_FINAL_B1_CNTL;
I_MUX2_1_FINAL_B1 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(1) ,
I0 => sig_pass_mux_bus(1) ,
I1 => sig_delay_data_reg(1),
Y => sig_final_mux_bus(1)
);
-- Final Mux Byte 2 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B2_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 2 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B2_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(2) <= '0';
when "001" =>
sig_final_mux_sel(2) <= '1';
when "010" =>
sig_final_mux_sel(2) <= '1';
when "011" =>
sig_final_mux_sel(2) <= '1';
when "100" =>
sig_final_mux_sel(2) <= '1';
when "101" =>
sig_final_mux_sel(2) <= '1';
when "110" =>
sig_final_mux_sel(2) <= '0';
when "111" =>
sig_final_mux_sel(2) <= '0';
when others =>
sig_final_mux_sel(2) <= '0';
end case;
end process MUX2_1_FINAL_B2_CNTL;
I_MUX2_1_FINAL_B2 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(2) ,
I0 => sig_pass_mux_bus(2) ,
I1 => sig_delay_data_reg(2),
Y => sig_final_mux_bus(2)
);
-- Final Mux Byte 3 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B3_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 3 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B3_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(3) <= '0';
when "001" =>
sig_final_mux_sel(3) <= '1';
when "010" =>
sig_final_mux_sel(3) <= '1';
when "011" =>
sig_final_mux_sel(3) <= '1';
when "100" =>
sig_final_mux_sel(3) <= '1';
when "101" =>
sig_final_mux_sel(3) <= '0';
when "110" =>
sig_final_mux_sel(3) <= '0';
when "111" =>
sig_final_mux_sel(3) <= '0';
when others =>
sig_final_mux_sel(3) <= '0';
end case;
end process MUX2_1_FINAL_B3_CNTL;
I_MUX2_1_FINAL_B3 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(3) ,
I0 => sig_pass_mux_bus(3) ,
I1 => sig_delay_data_reg(3),
Y => sig_final_mux_bus(3)
);
-- Final Mux Byte 4 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B4_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 4 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B4_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(4) <= '0';
when "001" =>
sig_final_mux_sel(4) <= '1';
when "010" =>
sig_final_mux_sel(4) <= '1';
when "011" =>
sig_final_mux_sel(4) <= '1';
when "100" =>
sig_final_mux_sel(4) <= '0';
when "101" =>
sig_final_mux_sel(4) <= '0';
when "110" =>
sig_final_mux_sel(4) <= '0';
when "111" =>
sig_final_mux_sel(4) <= '0';
when others =>
sig_final_mux_sel(4) <= '0';
end case;
end process MUX2_1_FINAL_B4_CNTL;
I_MUX2_1_FINAL_B4 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(4) ,
I0 => sig_pass_mux_bus(4) ,
I1 => sig_delay_data_reg(4),
Y => sig_final_mux_bus(4)
);
-- Final Mux Byte 5 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B5_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 5 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B5_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(5) <= '0';
when "001" =>
sig_final_mux_sel(5) <= '1';
when "010" =>
sig_final_mux_sel(5) <= '1';
when "011" =>
sig_final_mux_sel(5) <= '0';
when "100" =>
sig_final_mux_sel(5) <= '0';
when "101" =>
sig_final_mux_sel(5) <= '0';
when "110" =>
sig_final_mux_sel(5) <= '0';
when "111" =>
sig_final_mux_sel(5) <= '0';
when others =>
sig_final_mux_sel(5) <= '0';
end case;
end process MUX2_1_FINAL_B5_CNTL;
I_MUX2_1_FINAL_B5 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(5) ,
I0 => sig_pass_mux_bus(5) ,
I1 => sig_delay_data_reg(5),
Y => sig_final_mux_bus(5)
);
-- Final Mux Byte 6 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B6_CNTL
--
-- Process Description:
-- This process generates the Select Control for Byte 6 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B6_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "000" =>
sig_final_mux_sel(6) <= '0';
when "001" =>
sig_final_mux_sel(6) <= '1';
when "010" =>
sig_final_mux_sel(6) <= '0';
when "011" =>
sig_final_mux_sel(6) <= '0';
when "100" =>
sig_final_mux_sel(6) <= '0';
when "101" =>
sig_final_mux_sel(6) <= '0';
when "110" =>
sig_final_mux_sel(6) <= '0';
when "111" =>
sig_final_mux_sel(6) <= '0';
when others =>
sig_final_mux_sel(6) <= '0';
end case;
end process MUX2_1_FINAL_B6_CNTL;
I_MUX2_1_FINAL_B6 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(6) ,
I0 => sig_pass_mux_bus(6) ,
I1 => sig_delay_data_reg(6),
Y => sig_final_mux_bus(6)
);
-- Final Mux Byte 7 (wire)
sig_final_mux_sel(7) <= '0';
sig_final_mux_bus(7) <= sig_pass_mux_bus(7);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_64;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_32
--
-- If Generate Description:
-- Support Logic and Mux Farm for 32-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_32 : if (C_DWIDTH = 32) generate
Signal s_case_i_32 : Integer range 0 to 3 := 0;
signal sig_cntl_state_32 : std_logic_vector(3 downto 0) := (others => '0');
Signal sig_shift_case_i : std_logic_vector(1 downto 0) := (others => '0');
Signal sig_shift_case_reg : std_logic_vector(1 downto 0) := (others => '0');
Signal sig_final_mux_sel : std_logic_vector(3 downto 0) := (others => '0');
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_4
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_4 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(3 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "0000";
elsif (sig_tlast_strobes(3) = '1') then
sig_tlast_enables <= "1000";
elsif (sig_tlast_strobes(2) = '1') then
sig_tlast_enables <= "0100";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "0010";
else
sig_tlast_enables <= "0001";
end if;
end process FIND_MS_STRB_SET_4;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to sld_logic_vector
--sig_shift_case_i <= CONV_STD_LOGIC_VECTOR(s_case_i_32, 2);
sig_shift_case_i <= STD_LOGIC_VECTOR(TO_UNSIGNED(s_case_i_32, 2));
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_32
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_32 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_32)
begin
sig_cntl_state_32 <= dre_src_align(1 downto 0) & sig_dest_align_i(1 downto 0);
case sig_cntl_state_32 is
when "0000" =>
s_case_i_32 <= 0;
when "0001" =>
s_case_i_32 <= 3;
when "0010" =>
s_case_i_32 <= 2;
when "0011" =>
s_case_i_32 <= 1;
when "0100" =>
s_case_i_32 <= 1;
when "0101" =>
s_case_i_32 <= 0;
when "0110" =>
s_case_i_32 <= 3;
when "0111" =>
s_case_i_32 <= 2;
when "1000" =>
s_case_i_32 <= 2;
when "1001" =>
s_case_i_32 <= 1;
when "1010" =>
s_case_i_32 <= 0;
when "1011" =>
s_case_i_32 <= 3;
when "1100" =>
s_case_i_32 <= 3;
when "1101" =>
s_case_i_32 <= 2;
when "1110" =>
s_case_i_32 <= 1;
when "1111" =>
s_case_i_32 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_32;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= (others => '0');
elsif (sig_cntl_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(1),
I1 => sig_input_data_reg(0),
Y => sig_pass_mux_bus(1)
);
-- Pass Mux Byte 2 (4-1 x8 Mux)
I_MUX4_1_PASS_B2 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(2) ,
I1 => ZEROED_SLICE ,
I2 => sig_input_data_reg(0) ,
I3 => sig_input_data_reg(1) ,
Y => sig_pass_mux_bus(2)
);
-- Pass Mux Byte 3 (4-1 x8 Mux)
I_MUX4_1_PASS_B3 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => sig_input_data_reg(3) ,
I1 => sig_input_data_reg(0) ,
I2 => sig_input_data_reg(1) ,
I3 => sig_input_data_reg(2) ,
Y => sig_pass_mux_bus(3)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Byte 0 (4-1 x8 Mux)
I_MUX4_1_DLY_B4 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux4_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(1 downto 0),
I0 => ZEROED_SLICE ,
I1 => sig_input_data_reg(1) ,
I2 => sig_input_data_reg(2) ,
I3 => sig_input_data_reg(3) ,
Y => sig_delay_mux_bus(0)
);
-- Delay Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_DLY_B5 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg(0),
I0 => sig_input_data_reg(3),
I1 => sig_input_data_reg(2),
Y => sig_delay_mux_bus(1)
);
-- Delay Mux Byte 2 (Wire)
sig_delay_mux_bus(2) <= sig_input_data_reg(3);
-- Delay Mux Byte 3 (Zeroed)
sig_delay_mux_bus(3) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Slice 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(0) <= '0';
when "01" =>
sig_final_mux_sel(0) <= '1';
when "10" =>
sig_final_mux_sel(0) <= '1';
when "11" =>
sig_final_mux_sel(0) <= '1';
when others =>
sig_final_mux_sel(0) <= '0';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_pass_mux_bus(0) ,
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Slice 1 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B1_CNTL
--
-- Process Description:
-- This process generates the Select Control for slice 1 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B1_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(1) <= '0';
when "01" =>
sig_final_mux_sel(1) <= '1';
when "10" =>
sig_final_mux_sel(1) <= '1';
when "11" =>
sig_final_mux_sel(1) <= '0';
when others =>
sig_final_mux_sel(1) <= '0';
end case;
end process MUX2_1_FINAL_B1_CNTL;
I_MUX2_1_FINAL_B1 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(1) ,
I0 => sig_pass_mux_bus(1) ,
I1 => sig_delay_data_reg(1),
Y => sig_final_mux_bus(1)
);
-- Final Mux Slice 2 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B2_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 2 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B2_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when "00" =>
sig_final_mux_sel(2) <= '0';
when "01" =>
sig_final_mux_sel(2) <= '1';
when "10" =>
sig_final_mux_sel(2) <= '0';
when "11" =>
sig_final_mux_sel(2) <= '0';
when others =>
sig_final_mux_sel(2) <= '0';
end case;
end process MUX2_1_FINAL_B2_CNTL;
I_MUX2_1_FINAL_B2 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(2) ,
I0 => sig_pass_mux_bus(2) ,
I1 => sig_delay_data_reg(2),
Y => sig_final_mux_bus(2)
);
-- Final Mux Slice 3 (wire)
sig_final_mux_sel(3) <= '0';
sig_final_mux_bus(3) <= sig_pass_mux_bus(3);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_32;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MUXFARM_16
--
-- If Generate Description:
-- Support Logic and Mux Farm for 16-bit data path case
--
--
------------------------------------------------------------
GEN_MUXFARM_16 : if (C_DWIDTH = 16) generate
Signal s_case_i_16 : Integer range 0 to 1 := 0;
signal sig_cntl_state_16 : std_logic_vector(1 downto 0) := (others => '0');
Signal sig_shift_case_i : std_logic := '0';
Signal sig_shift_case_reg : std_logic := '0';
Signal sig_final_mux_sel : std_logic_vector(1 downto 0) := (others => '0');
begin
-------------------------------------------------------------
-- Combinational Process
--
-- Label: FIND_MS_STRB_SET_2
--
-- Process Description:
-- This process finds the most significant asserted strobe
-- position. This position is used to enable the input flop
-- for TLAST that is associated with that byte position. The
-- TLAST can then flow through the DRE pipe with the last
-- valid byte of data.
--
-------------------------------------------------------------
FIND_MS_STRB_SET_2 : process (dre_in_tlast,
dre_in_tstrb,
sig_tlast_strobes)
begin
sig_tlast_strobes <= dre_in_tstrb(1 downto 0); -- makes case choice locally static
if (dre_in_tlast = '0') then
sig_tlast_enables <= "00";
elsif (sig_tlast_strobes(1) = '1') then
sig_tlast_enables <= "10";
else
sig_tlast_enables <= "01";
end if;
end process FIND_MS_STRB_SET_2;
---------------------------------------------------------------------------------
-- Shift Case logic
-- The new auto-destination alignment is based on the last
-- strobe alignment written into the output register.
sig_next_auto_dest <= sig_current_dest_align;
-- Select the destination alignment to use
sig_dest_align_i <= sig_next_auto_dest
When (dre_use_autodest = '1')
Else dre_dest_align;
-- Convert shift case to std_logic
sig_shift_case_i <= '1'
When s_case_i_16 = 1
Else '0';
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_SHIFT_CASE_16
--
-- Process Description:
-- Implements the DRE Control State Calculator
--
-------------------------------------------------------------
DO_SHIFT_CASE_16 : process (dre_src_align ,
sig_dest_align_i,
sig_cntl_state_16)
begin
sig_cntl_state_16 <= dre_src_align(0) & sig_dest_align_i(0);
case sig_cntl_state_16 is
when "00" =>
s_case_i_16 <= 0;
when "01" =>
s_case_i_16 <= 1;
when "10" =>
s_case_i_16 <= 1;
when "11" =>
s_case_i_16 <= 0;
when others =>
NULL;
end case;
end process DO_SHIFT_CASE_16;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SHIFT_CASE
--
-- Process Description:
-- This process registers the Shift Case output from the
-- Shift Case Generator. This will be used to control the
-- select inputs of the Shift Muxes for the duration of the
-- data transfer session. If Pass Through is requested, then
-- Shift Case 0 is forced regardless of source and destination
-- alignment values.
--
-------------------------------------------------------------
REG_SHIFT_CASE : process (dre_clk)
begin
if (dre_clk'event and dre_clk = '1') then
if (dre_rst = '1') then
sig_shift_case_reg <= '0';
elsif (sig_cntl_accept = '1') then
sig_shift_case_reg <= sig_shift_case_i;
else
null; -- hold state
end if;
-- else
-- null;
end if;
end process REG_SHIFT_CASE;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start PASS Mux Farm Design-------------------------------------------------
-- Pass Mux Byte 0 (wire)
-- This is a wire so.....
sig_pass_mux_bus(0) <= sig_input_data_reg(0);
-- Pass Mux Byte 1 (2-1 x8 Mux)
I_MUX2_1_PASS_B1 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_shift_case_reg,
I0 => sig_input_data_reg(1),
I1 => sig_input_data_reg(0),
Y => sig_pass_mux_bus(1)
);
-- End PASS Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Delay Mux Farm Design-------------------------------------------------
-- Delay Mux Slice 0 (Wire)
sig_delay_mux_bus(0) <= sig_input_data_reg(1);
-- Delay Mux Slice 1 (Zeroed)
sig_delay_mux_bus(1) <= ZEROED_SLICE;
-- End Delay Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Start Final Mux Farm Design-------------------------------------------------
-- Final Mux Slice 0 (2-1 x8 Mux)
-------------------------------------------------------------
-- Combinational Process
--
-- Label: MUX2_1_FINAL_B0_CNTL
--
-- Process Description:
-- This process generates the Select Control for Slice 0 of
-- the Final 2-1 Mux of the DRE.
--
-------------------------------------------------------------
MUX2_1_FINAL_B0_CNTL : process (sig_shift_case_reg)
begin
case sig_shift_case_reg is
when '0' =>
sig_final_mux_sel(0) <= '0';
when others =>
sig_final_mux_sel(0) <= '1';
end case;
end process MUX2_1_FINAL_B0_CNTL;
I_MUX2_1_FINAL_B0 : entity axi_datamover_v5_1_11.axi_datamover_dre_mux2_1_x_n
generic map(
C_WIDTH => SLICE_WIDTH
)
port map(
Sel => sig_final_mux_sel(0) ,
I0 => sig_pass_mux_bus(0) ,
I1 => sig_delay_data_reg(0),
Y => sig_final_mux_bus(0)
);
-- Final Mux Slice 1 (wire)
sig_final_mux_sel(1) <= '0';
sig_final_mux_bus(1) <= sig_pass_mux_bus(1);
-- End Final Mux Farm Design---------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
end generate GEN_MUXFARM_16;
end implementation;
|
mit
|
Bjay1435/capstone
|
Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_ftch_noqueue.vhd
|
1
|
24940
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_noqueue.vhd
-- Description: This entity is the no queue version
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1_3;
use axi_sg_v4_1_3.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_noqueue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Stream Data Width
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
C_ASYNC : integer range 0 to 1 := 0;
C_SG_WORDS_TO_FETCH : integer range 8 to 13 := 8;
C_ENABLE_CDMA : integer range 0 to 1 := 0;
C_ENABLE_CH1 : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_primary_aclk : in std_logic ;
m_axi_sg_aresetn : in std_logic ; --
p_reset_n : in std_logic ;
--
-- Channel Control --
desc_flush : in std_logic ; --
ch1_cntrl_strm_stop : in std_logic ;
ftch_active : in std_logic ; --
ftch_queue_empty : out std_logic ; --
ftch_queue_full : out std_logic ; --
sof_ftch_desc : in std_logic ;
desc2_flush : in std_logic ; --
ftch2_active : in std_logic ; --
ftch2_queue_empty : out std_logic ; --
ftch2_queue_full : out std_logic ; --
--
writing_nxtdesc_in : in std_logic ; --
writing_curdesc_out : out std_logic ; --
writing2_curdesc_out : out std_logic ; --
-- DataMover Command --
ftch_cmnd_wr : in std_logic ; --
ftch_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- MM2S Stream In from DataMover --
m_axis_mm2s_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_mm2s_tlast : in std_logic ; --
m_axis_mm2s_tvalid : in std_logic ; --
m_axis_mm2s_tready : out std_logic ; --
m_axis2_mm2s_tready : out std_logic ; --
data_concat : in std_logic_vector --
(95 downto 0) ; --
data_concat_64 : in std_logic_vector --
(31 downto 0) ; --
data_concat_mcdma : in std_logic_vector --
(63 downto 0) ; --
next_bd : in std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
data_concat_tlast : in std_logic ; --
data_concat_valid : in std_logic ; --
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_ftch_tvalid : out std_logic ; --
m_axis_ftch_tready : in std_logic ; --
m_axis_ftch_tlast : out std_logic ; --
m_axis_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ftch_tvalid_new : out std_logic ; --
m_axis_ftch_desc_available : out std_logic ;
m_axis2_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis2_ftch_tvalid : out std_logic ; --
m_axis2_ftch_tready : in std_logic ; --
m_axis2_ftch_tlast : out std_logic ; --
m_axis2_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis2_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis2_ftch_tdata_mcdma_nxt : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis2_ftch_tvalid_new : out std_logic ; --
m_axis2_ftch_desc_available : out std_logic ;
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(31 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
(3 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic := '0'; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_ftch_noqueue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_noqueue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel 1 internal signals
signal curdesc_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_tvalid : std_logic := '0';
signal ftch_tvalid : std_logic := '0';
signal ftch_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ftch_tlast : std_logic := '0';
signal ftch_tready : std_logic := '0';
-- Misc Signals
signal writing_curdesc : std_logic := '0';
signal writing_nxtdesc : std_logic := '0';
signal msb_curdesc : std_logic_vector(31 downto 0) := (others => '0');
signal ftch_tdata_new_64 : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
signal writing_lsb : std_logic := '0';
signal writing_msb : std_logic := '0';
signal ftch_active_int : std_logic := '0';
signal ftch_tvalid_mult : std_logic := '0';
signal ftch_tdata_mult : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ftch_tlast_mult : std_logic := '0';
signal counter : std_logic_vector (3 downto 0) := (others => '0');
signal wr_cntl : std_logic := '0';
signal ftch_tdata_new : std_logic_vector (96+31*C_ENABLE_CDMA downto 0);
signal queue_wren, queue_rden : std_logic := '0';
signal queue_din : std_logic_vector (32 downto 0);
signal queue_dout : std_logic_vector (32 downto 0);
signal queue_empty, queue_full : std_logic := '0';
signal sof_ftch_desc_del, sof_ftch_desc_pulse : std_logic := '0';
signal sof_ftch_desc_del1 : std_logic := '0';
signal queue_sinit : std_logic := '0';
signal data_concat_mcdma_nxt : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal current_bd : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
queue_sinit <= not m_axi_sg_aresetn;
ftch_active_int <= ftch_active or ftch2_active;
ftch_tdata_new (64 downto 0) <= data_concat (95) & data_concat (63 downto 0);-- when (ftch_active = '1') else (others =>'0');
ftch_tdata_new (96 downto 65) <= current_bd (31 downto 0);
ADDR641 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
ftch_tdata_new_64 <= data_concat_64 & current_bd (C_M_AXI_SG_ADDR_WIDTH-1 downto 32);
end generate ADDR641;
---------------------------------------------------------------------------
-- Write current descriptor to FIFO or out channel port
---------------------------------------------------------------------------
NXT_BD_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
NEXT_BD_S2MM : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
data_concat_mcdma_nxt <= (others => '0');
elsif (ftch2_active = '1') then
data_concat_mcdma_nxt <= next_bd;
end if;
end if;
end process NEXT_BD_S2MM;
end generate NXT_BD_MCDMA;
WRITE_CURDESC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
current_bd <= (others => '0');
--
-- -- Write LSB Address on command write
elsif(ftch_cmnd_wr = '1' and ftch_active_int = '1')then
current_bd <= ftch_cmnd_data((C_M_AXI_SG_ADDR_WIDTH-32)+DATAMOVER_CMD_ADDRMSB_BOFST
+ DATAMOVER_CMD_ADDRLSB_BIT
downto DATAMOVER_CMD_ADDRLSB_BIT);
end if;
end if;
end process WRITE_CURDESC_PROCESS;
GEN_MULT_CHANNEL : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
ftch_tvalid_mult <= m_axis_mm2s_tvalid;
ftch_tdata_mult <= m_axis_mm2s_tdata;
ftch_tlast_mult <= m_axis_mm2s_tlast;
wr_cntl <= m_axis_mm2s_tvalid;
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= "0000";
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
end generate GEN_MULT_CHANNEL;
GEN_NOMULT_CHANNEL : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
ftch_tvalid_mult <= '0'; --m_axis_mm2s_tvalid;
ftch_tdata_mult <= (others => '0'); --m_axis_mm2s_tdata;
ftch_tlast_mult <= '0'; --m_axis_mm2s_tlast;
CONTROL_STREAM : if C_SG_WORDS_TO_FETCH = 13 and C_ENABLE_CH1 = 1 generate
begin
SOF_DEL_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sof_ftch_desc_del <= '0';
else
sof_ftch_desc_del <= sof_ftch_desc;
end if;
end if;
end process SOF_DEL_PROCESS;
SOF_DEL1_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or m_axis_mm2s_tlast = '1')then
sof_ftch_desc_del1 <= '0';
elsif (m_axis_mm2s_tvalid = '1') then
sof_ftch_desc_del1 <= sof_ftch_desc;
end if;
end if;
end process SOF_DEL1_PROCESS;
sof_ftch_desc_pulse <= sof_ftch_desc and (not sof_ftch_desc_del1);
queue_wren <= not queue_full
and sof_ftch_desc
and m_axis_mm2s_tvalid
and ftch_active;
queue_rden <= not queue_empty
and m_axis_mm2s_cntrl_tready;
queue_din(C_M_AXIS_SG_TDATA_WIDTH) <= m_axis_mm2s_tlast;
queue_din(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) <= x"A0000000" when (sof_ftch_desc_pulse = '1') else m_axis_mm2s_tdata;
I_MM2S_CNTRL_STREAM : entity axi_sg_v4_1_3.axi_sg_cntrl_strm
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_ASYNC ,
C_PRMY_CMDFIFO_DEPTH => 16, --FETCH_QUEUE_DEPTH ,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Secondary clock / reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Primary clock / reset
axi_prmry_aclk => m_axi_primary_aclk ,
p_reset_n => p_reset_n ,
-- MM2S Error
mm2s_stop => ch1_cntrl_strm_stop ,
-- Control Stream input
cntrlstrm_fifo_wren => queue_wren ,
cntrlstrm_fifo_full => queue_full ,
cntrlstrm_fifo_din => queue_din ,
-- Memory Map to Stream Control Stream Interface
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
end generate CONTROL_STREAM;
NO_CONTROL_STREAM : if C_SG_WORDS_TO_FETCH /= 13 or C_ENABLE_CH1 = 0 generate
begin
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= "0000";
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
end generate NO_CONTROL_STREAM;
end generate GEN_NOMULT_CHANNEL;
---------------------------------------------------------------------------
-- Map internal stream to external
---------------------------------------------------------------------------
ftch_tready <= (m_axis_ftch_tready and ftch_active) or
(m_axis2_ftch_tready and ftch2_active);
ADDR64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
m_axis_ftch_tdata_new <= ftch_tdata_new_64 & ftch_tdata_new;
end generate ADDR64;
ADDR32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
m_axis_ftch_tdata_new <= ftch_tdata_new;
end generate ADDR32;
m_axis_ftch_tdata_mcdma_new <= data_concat_mcdma;
m_axis_ftch_tvalid_new <= data_concat_valid and ftch_active;
m_axis_ftch_desc_available <= data_concat_tlast and ftch_active;
REG_FOR_STS_CNTRL : if C_SG_WORDS_TO_FETCH = 13 generate
begin
LATCH_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis2_ftch_tvalid_new <= '0';
m_axis2_ftch_desc_available <= '0';
else
m_axis2_ftch_tvalid_new <= data_concat_valid and ftch2_active;
m_axis2_ftch_desc_available <= data_concat_valid and ftch2_active;
end if;
end if;
end process LATCH_PROCESS;
LATCH2_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
m_axis2_ftch_tdata_new <= (others => '0');
elsif (data_concat_valid = '1' and ftch2_active = '1') then
m_axis2_ftch_tdata_new <= ftch_tdata_new;
end if;
end if;
end process LATCH2_PROCESS;
end generate REG_FOR_STS_CNTRL;
NO_REG_FOR_STS_CNTRL : if C_SG_WORDS_TO_FETCH /= 13 generate
begin
ADDR64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
m_axis2_ftch_tdata_new <= ftch_tdata_new_64 & ftch_tdata_new;
end generate ADDR64;
ADDR32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
m_axis2_ftch_tdata_new <= ftch_tdata_new;
end generate ADDR32;
m_axis2_ftch_tvalid_new <= data_concat_valid and ftch2_active;
m_axis2_ftch_desc_available <= data_concat_valid and ftch2_active;
m_axis2_ftch_tdata_mcdma_new <= data_concat_mcdma;
m_axis2_ftch_tdata_mcdma_nxt <= data_concat_mcdma_nxt;
end generate NO_REG_FOR_STS_CNTRL;
m_axis_mm2s_tready <= ftch_tready;
m_axis2_mm2s_tready <= ftch_tready;
---------------------------------------------------------------------------
-- generate psuedo empty flag for Idle generation
---------------------------------------------------------------------------
Q_EMPTY_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk='1')then
if(m_axi_sg_aresetn = '0' or desc_flush = '1')then
ftch_queue_empty <= '1';
-- Else on valid and ready modify empty flag
elsif(ftch_tvalid = '1' and m_axis_ftch_tready = '1' and ftch_active = '1')then
-- On last mark as empty
if(ftch_tlast = '1' )then
ftch_queue_empty <= '1';
-- Otherwise mark as not empty
else
ftch_queue_empty <= '0';
end if;
end if;
end if;
end process Q_EMPTY_PROCESS;
Q2_EMPTY_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk='1')then
if(m_axi_sg_aresetn = '0' or desc2_flush = '1')then
ftch2_queue_empty <= '1';
-- Else on valid and ready modify empty flag
elsif(ftch_tvalid = '1' and m_axis2_ftch_tready = '1' and ftch2_active = '1')then
-- On last mark as empty
if(ftch_tlast = '1' )then
ftch2_queue_empty <= '1';
-- Otherwise mark as not empty
else
ftch2_queue_empty <= '0';
end if;
end if;
end if;
end process Q2_EMPTY_PROCESS;
-- do not need to indicate full to axi_sg_ftch_sm. Only
-- needed for queue case to allow other channel to be serviced
-- if it had queue room
ftch_queue_full <= '0';
ftch2_queue_full <= '0';
-- If writing curdesc out then flag for proper mux selection
writing_curdesc <= curdesc_tvalid;
-- Map intnal signal to port
writing_curdesc_out <= writing_curdesc and ftch_active;
writing2_curdesc_out <= writing_curdesc and ftch2_active;
-- Map port to internal signal
writing_nxtdesc <= writing_nxtdesc_in;
end implementation;
|
mit
|
mpvanveldhuizen/16-bit-risc
|
vhdl/reg8.vhd
|
4
|
428
|
-- REG8
-- 8 bit register file
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity reg8 is
port(D: in std_logic_vector(7 downto 0);
EN: in std_logic;
CLK: in std_logic;
Q: out std_logic_vector(7 downto 0)
);
end reg8;
architecture logic of reg8 is
begin
process(CLK, EN)
begin
if (CLK'event and CLK = '1') and EN = '1' then
Q <= D;
end if;
end process;
end logic;
|
mit
|
Bjay1435/capstone
|
Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_rddata_cntl.vhd
|
5
|
75297
|
-------------------------------------------------------------------------------
-- axi_datamover_rddata_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_rddata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Read Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_11;
use axi_datamover_v5_1_11.axi_datamover_rdmux;
-------------------------------------------------------------------------------
entity axi_datamover_rddata_cntl is
generic (
C_INCLUDE_DRE : Integer range 0 to 1 := 0;
-- Indicates if the DRE interface is used
C_ALIGN_WIDTH : Integer range 1 to 3 := 3;
-- Sets the width of the DRE Alignment controls
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Mux read data from a wider AXI4 Read
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1;
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------
-- Soft Shutdown internal interface -----------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
-----------------------------------------------------------------------
-- External Address Pipelining Contol support -------------------------
--
mm2s_rd_xfer_cmplt : out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single read data transfer on the AXI4 Read Data Channel. --
-- This signal escentially echos the assertion of rlast received --
-- from the AXI4. --
-----------------------------------------------------------------------
-- AXI Read Data Channel I/O ---------------------------------------------
--
mm2s_rdata : In std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- AXI Read data input --
--
mm2s_rresp : In std_logic_vector(1 downto 0); --
-- AXI Read response input --
--
mm2s_rlast : In std_logic; --
-- AXI Read LAST input --
--
mm2s_rvalid : In std_logic; --
-- AXI Read VALID input --
--
mm2s_rready : Out std_logic; --
-- AXI Read data READY output --
--------------------------------------------------------------------------
-- MM2S DRE Control -------------------------------------------------------------
--
mm2s_dre_new_align : Out std_logic; --
-- Active high signal indicating new DRE aligment required --
--
mm2s_dre_use_autodest : Out std_logic; --
-- Active high signal indicating to the DRE to use an auto- --
-- calculated desination alignment based on the last transfer --
--
mm2s_dre_src_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the byte lane of the first valid data byte --
-- being sent to the DRE --
--
mm2s_dre_dest_align : Out std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- Bit field indicating the desired byte lane of the first valid data byte --
-- to be output by the DRE --
--
mm2s_dre_flush : Out std_logic; --
-- Active high signal indicating to the DRE to flush the current --
-- contents to the output register in preparation of a new alignment --
-- that will be comming on the next transfer input --
---------------------------------------------------------------------------------
-- AXI Master Stream Channel------------------------------------------------------
--
mm2s_strm_wvalid : Out std_logic; --
-- AXI Stream VALID Output --
--
mm2s_strm_wready : In Std_logic; --
-- AXI Stream READY input --
--
mm2s_strm_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data output --
--
mm2s_strm_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB output --
--
mm2s_strm_wlast : Out std_logic; --
-- AXI Stream LAST output --
---------------------------------------------------------------------------------
-- MM2S Store and Forward Supplimental Control --------------------------------
-- This output is time aligned and qualified with the AXI Master Stream Channel--
--
mm2s_data2sf_cmd_cmplt : out std_logic; --
--
---------------------------------------------------------------------------------
-- Command Calculator Interface -------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the read data --
-- mux (only used if Stream data width is 8 or 16 bits). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The indication to the Data Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address Channel --
--
mstr2data_dre_src_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The source (input) alignment for the DRE --
--
mstr2data_dre_dest_align : In std_logic_vector(C_ALIGN_WIDTH-1 downto 0); --
-- The destinstion (output) alignment for the DRE --
---------------------------------------------------------------------------------
-- Address Controller Interface -------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
---------------------------------------------------------------------------------
-- Data Controller General Halted Status ----------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
---------------------------------------------------------------------------------
-- Output Stream Skid Buffer Halt control ---------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
---------------------------------------------------------------------------------
-- Read Status Controller Interface ------------------------------------------------
--
data2rsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The propagated command tag from the Command Calculator --
--
data2rsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a propagated calculation error from the Command Calculator --
--
data2rsc_okay : Out std_logic ; --
-- Indication that the AXI Read transfer completed with OK status --
--
data2rsc_decerr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with decode error status --
--
data2rsc_slverr : Out std_logic ; --
-- Indication that the AXI Read transfer completed with slave error status --
--
data2rsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a parent command --
-- pulled from the command FIFO --
--
rsc2data_ready : in std_logic; --
-- Handshake bit from the Read Status Controller Module indicating --
-- that the it is ready to accept a new Read status transfer --
--
data2rsc_valid : Out std_logic ; --
-- Handshake bit output to the Read Status Controller Module --
-- indicating that the Data Controller has valid tag and status --
-- indicators to transfer --
--
rsc2mstr_halt_pipe : In std_logic --
-- Status Flag indicating the Status Controller needs to stall the command --
-- execution pipe due to a Status flow issue or internal error. Generally --
-- this will occur if the Status FIFO is not being serviced fast enough to --
-- keep ahead of the command execution. --
------------------------------------------------------------------------------------
);
end entity axi_datamover_rddata_cntl;
architecture implementation of axi_datamover_rddata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant OKAY : std_logic_vector(1 downto 0) := "00";
Constant EXOKAY : std_logic_vector(1 downto 0) := "01";
Constant SLVERR : std_logic_vector(1 downto 0) := "10";
Constant DECERR : std_logic_vector(1 downto 0) := "11";
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant SOF_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant DRE_ALIGN_WIDTH : integer := C_ALIGN_WIDTH;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
SOF_WIDTH + -- SOF Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Calc error flag
CMD_CMPLT_WIDTH + -- Sequential command flag
CALC_ERR_WIDTH + -- Command Complete Flag
DRE_ALIGN_WIDTH + -- DRE Source Align width
DRE_ALIGN_WIDTH ; -- DRE Dest Align width
-- Caution, the INDEX calculations are order dependent so don't rearrange
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant SOF_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := SOF_STRT_INDEX + SOF_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX + SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX + CMD_CMPLT_WIDTH;
Constant DRE_SRC_STRT_INDEX : integer := CALC_ERR_STRT_INDEX + CALC_ERR_WIDTH;
Constant DRE_DEST_STRT_INDEX : integer := DRE_SRC_STRT_INDEX + DRE_ALIGN_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
--Constant ADDR_POSTED_CNTR_WIDTH : integer := 5; -- allows up to 32 entry address queue
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_good_dbeat : std_logic := '0';
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_data2mmap_ready : std_logic := '0';
signal sig_mmap2data_valid : std_logic := '0';
signal sig_mmap2data_last : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_decerr : std_logic := '0';
signal sig_slverr : std_logic := '0';
signal sig_coelsc_okay_reg : std_logic := '0';
signal sig_coelsc_interr_reg : std_logic := '0';
signal sig_coelsc_decerr_reg : std_logic := '0';
signal sig_coelsc_slverr_reg : std_logic := '0';
signal sig_coelsc_cmd_cmplt_reg : std_logic := '0';
signal sig_coelsc_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_coelsc_reg : std_logic := '0';
signal sig_push_coelsc_reg : std_logic := '0';
signal sig_coelsc_reg_empty : std_logic := '0';
signal sig_coelsc_reg_full : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_cmd_cmplt_last_dbeat : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_next_dre_src_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_next_dre_dest_align_reg : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_no_posted_cmds : std_logic := '0';
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0);
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0);
signal sig_fifo_next_sadddr_lsb : std_logic_vector(SADDR_LSB_WIDTH-1 downto 0);
signal sig_fifo_next_len : std_logic_vector(LEN_WIDTH-1 downto 0);
signal sig_fifo_next_strt_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_last_strb : std_logic_vector(STRB_WIDTH-1 downto 0);
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_dre_src_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_dre_dest_align : std_logic_vector(C_ALIGN_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_advance_pipe : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_rd_xfer_cmplt : std_logic := '0';
begin --(architecture implementation)
-- AXI MMap Data Channel Port assignments
mm2s_rready <= sig_data2mmap_ready;
sig_mmap2data_valid <= mm2s_rvalid ;
sig_mmap2data_last <= mm2s_rlast ;
-- Read Status Block interface
data2rsc_valid <= sig_coelsc_reg_full ;
sig_rsc2data_ready <= rsc2data_ready ;
data2rsc_tag <= sig_coelsc_tag_reg ;
data2rsc_calc_err <= sig_coelsc_interr_reg ;
data2rsc_okay <= sig_coelsc_okay_reg ;
data2rsc_decerr <= sig_coelsc_decerr_reg ;
data2rsc_slverr <= sig_coelsc_slverr_reg ;
data2rsc_cmd_cmplt <= sig_coelsc_cmd_cmplt_reg ;
-- AXI MM2S Stream Channel Port assignments
mm2s_strm_wvalid <= (mm2s_rvalid and
sig_advance_pipe) or
(sig_halt_reg and -- Force tvalid high on a Halt and
sig_dqual_reg_full and -- a transfer is scheduled and
not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
not(sig_calc_error_reg)); -- not a calc error
mm2s_strm_wlast <= (mm2s_rlast and
sig_next_eof_reg) or
(sig_halt_reg and -- Force tvalid high on a Halt and
sig_dqual_reg_full and -- a transfer is scheduled and
not(sig_no_posted_cmds) and -- there are cmds posted to AXi and
not(sig_calc_error_reg)); -- not a calc error;
GEN_MM2S_TKEEP_ENABLE5 : if C_ENABLE_MM2S_TKEEP = 1 generate
begin
-- Generate the Write Strobes for the Stream interface
mm2s_strm_wstrb <= (others => '1')
When (sig_halt_reg = '1') -- Force tstrb high on a Halt
else sig_strt_strb_reg
When (sig_first_dbeat = '1')
Else sig_last_strb_reg
When (sig_last_dbeat = '1')
Else (others => '1');
end generate GEN_MM2S_TKEEP_ENABLE5;
GEN_MM2S_TKEEP_DISABLE5 : if C_ENABLE_MM2S_TKEEP = 0 generate
begin
-- Generate the Write Strobes for the Stream interface
mm2s_strm_wstrb <= (others => '1');
end generate GEN_MM2S_TKEEP_DISABLE5;
-- MM2S Supplimental Controls
mm2s_data2sf_cmd_cmplt <= (mm2s_rlast and
sig_next_cmd_cmplt_reg) or
(sig_halt_reg and
sig_dqual_reg_full and
not(sig_no_posted_cmds) and
not(sig_calc_error_reg));
-- Address Channel Controller synchro pulse input
sig_addr_posted <= addr2data_addr_posted;
-- Request to halt the Address Channel Controller
data2addr_stop_req <= sig_halt_reg;
-- Halted flag to the reset module
data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
sig_no_posted_cmds and
not(sig_calc_error_reg)) or
(sig_halt_reg_dly3 and -- Shutdown after error trap
sig_calc_error_reg);
-- Read Transfer Completed Status output
mm2s_rd_xfer_cmplt <= sig_rd_xfer_cmplt;
-- Internal logic ------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_RD_CMPLT_FLAG
--
-- Process Description:
-- Implements the status flag indicating that a read data
-- transfer has completed. This is an echo of a rlast assertion
-- and a qualified data beat on the AXI4 Read Data Channel
-- inputs.
--
-------------------------------------------------------------
IMP_RD_CMPLT_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_rd_xfer_cmplt <= '0';
else
sig_rd_xfer_cmplt <= sig_mmap2data_last and
sig_good_mmap_dbeat;
end if;
end if;
end process IMP_RD_CMPLT_FLAG;
-- General flag for advancing the MMap Read and the Stream
-- data pipelines
sig_advance_pipe <= sig_addr_chan_rdy and
sig_dqual_rdy and
not(sig_coelsc_reg_full) and -- new status back-pressure term
not(sig_calc_error_reg);
-- test for Kevin's status throttle case
sig_data2mmap_ready <= (mm2s_strm_wready or
sig_halt_reg) and -- Ignore the Stream ready on a Halt request
sig_advance_pipe;
sig_good_mmap_dbeat <= sig_data2mmap_ready and
sig_mmap2data_valid;
sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
sig_mmap2data_last;
sig_get_next_dqual <= sig_last_mmap_dbeat;
------------------------------------------------------------
-- Instance: I_READ_MUX
--
-- Description:
-- Instance of the MM2S Read Data Channel Read Mux
--
------------------------------------------------------------
I_READ_MUX : entity axi_datamover_v5_1_11.axi_datamover_rdmux
generic map (
C_SEL_ADDR_WIDTH => C_SEL_ADDR_WIDTH ,
C_MMAP_DWIDTH => C_MMAP_DWIDTH ,
C_STREAM_DWIDTH => C_STREAM_DWIDTH
)
port map (
mmap_read_data_in => mm2s_rdata ,
mux_data_out => mm2s_strm_wdata ,
mstr2data_saddr_lsb => sig_addr_lsb_reg
);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_LAST_DBEAT
--
-- Process Description:
-- This implements a FLOP that creates a pulse
-- indicating the LAST signal for an incoming read data channel
-- has been received. Note that it is possible to have back to
-- back LAST databeats.
--
-------------------------------------------------------------
REG_LAST_DBEAT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_last_mmap_dbeat_reg <= '0';
else
sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
end if;
end if;
end process REG_LAST_DBEAT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Omits the input data control FIFO if the requested FIFO
-- depth is 1. The Data Qualifier Register serves as a
-- 1 deep FIFO by itself.
--
------------------------------------------------------------
GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
begin
-- Command Calculator Handshake output
data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
-- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(rsc2mstr_halt_pipe) and -- The Rd Status Controller is not stalling
-- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- pre 13.1 -- no calculation error being propagated
sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
sig_fifo_next_tag <= mstr2data_tag ;
sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
sig_fifo_next_len <= mstr2data_len ;
sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
sig_fifo_next_last_strb <= mstr2data_last_strb ;
sig_fifo_next_drr <= mstr2data_drr ;
sig_fifo_next_eof <= mstr2data_eof ;
sig_fifo_next_sequential <= mstr2data_sequential ;
sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
sig_fifo_next_calc_error <= mstr2data_calc_error ;
sig_fifo_next_dre_src_align <= mstr2data_dre_src_align ;
sig_fifo_next_dre_dest_align <= mstr2data_dre_dest_align ;
end generate GEN_NO_DATA_CNTL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Includes the input data control FIFO if the requested
-- FIFO depth is more than 1.
--
------------------------------------------------------------
GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
begin
-- Command Calculator Handshake output
data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
sig_fifo_rd_cmd_ready <= sig_push_dqual_reg; -- pop the fifo when dqual reg is pushed
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2data_dre_dest_align &
mstr2data_dre_src_align &
mstr2data_calc_error &
mstr2data_cmd_cmplt &
mstr2data_sequential &
mstr2data_eof &
mstr2data_drr &
mstr2data_last_strb &
mstr2data_strt_strb &
mstr2data_len &
mstr2data_saddr_lsb &
mstr2data_tag ;
-- Rip the output fifo data word
sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
TAG_STRT_INDEX);
sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
SADDR_LSB_STRT_INDEX);
sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
LEN_STRT_INDEX);
sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
STRT_STRB_STRT_INDEX);
sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
LAST_STRB_STRT_INDEX);
sig_fifo_next_drr <= sig_cmd_fifo_data_out(SOF_STRT_INDEX);
sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
sig_fifo_next_dre_src_align <= sig_cmd_fifo_data_out((DRE_SRC_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
DRE_SRC_STRT_INDEX);
sig_fifo_next_dre_dest_align <= sig_cmd_fifo_data_out((DRE_DEST_STRT_INDEX+DRE_ALIGN_WIDTH)-1 downto
DRE_DEST_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DATA_CNTL_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_FIFO : entity axi_datamover_v5_1_11.axi_datamover_fifo
generic map (
C_DWIDTH => DCTL_FIFO_WIDTH ,
C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_DATA_CNTL_FIFO;
-- Data Qualifier Register ------------------------------------
sig_ld_new_cmd <= sig_push_dqual_reg ;
sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0);
sig_dqual_rdy <= sig_dqual_reg_full ;
sig_strt_strb_reg <= sig_next_strt_strb_reg ;
sig_last_strb_reg <= sig_next_last_strb_reg ;
sig_tag_reg <= sig_next_tag_reg ;
sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
sig_calc_error_reg <= sig_next_calc_error_reg ;
-- Flag indicating that there are no posted commands to AXI
sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0;
-- new for no bubbles between child requests
sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
sig_last_dbeat and -- last data beat of transfer
sig_next_sequential_reg;-- next queued command is sequential
-- to the current command
-- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- pre 13.1 sig_dqual_reg_empty) and
-- pre 13.1 sig_fifo_rd_cmd_valid and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- stalling the command execution pipe
sig_push_dqual_reg <= (sig_sequential_push or
sig_dqual_reg_empty) and
sig_fifo_rd_cmd_valid and
sig_aposted_cntr_ready and
not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
not(rsc2mstr_halt_pipe); -- The Rd Status Controller is not
-- stalling the command execution pipe
sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
sig_get_next_dqual and
sig_dqual_reg_full ;
-- new for no bubbles between child requests
sig_clr_dqual_reg <= mmap_reset or
(sig_pop_dqual_reg and
not(sig_push_dqual_reg));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DQUAL_REG
--
-- Process Description:
-- This process implements a register for the Data
-- Control and qualifiers. It operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_DQUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_clr_dqual_reg = '1') then
sig_next_tag_reg <= (others => '0');
sig_next_strt_strb_reg <= (others => '0');
sig_next_last_strb_reg <= (others => '0');
sig_next_eof_reg <= '0';
sig_next_cmd_cmplt_reg <= '0';
sig_next_sequential_reg <= '0';
sig_next_calc_error_reg <= '0';
sig_next_dre_src_align_reg <= (others => '0');
sig_next_dre_dest_align_reg <= (others => '0');
sig_dqual_reg_empty <= '1';
sig_dqual_reg_full <= '0';
elsif (sig_push_dqual_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_strt_strb_reg <= sig_fifo_next_strt_strb ;
sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
sig_next_eof_reg <= sig_fifo_next_eof ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_next_sequential_reg <= sig_fifo_next_sequential ;
sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
sig_next_dre_src_align_reg <= sig_fifo_next_dre_src_align ;
sig_next_dre_dest_align_reg <= sig_fifo_next_dre_dest_align ;
sig_dqual_reg_empty <= '0';
sig_dqual_reg_full <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_DQUAL_REG;
-- Address LS Cntr logic --------------------------
sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_ADDR_LSB_CNTR
--
-- Process Description:
-- Implements the LS Address Counter used for controlling
-- the Read Data Mux during Burst transfers
--
-------------------------------------------------------------
DO_ADDR_LSB_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_dqual_reg = '1' and
sig_push_dqual_reg = '0')) then -- Clear the Counter
sig_ls_addr_cntr <= (others => '0');
elsif (sig_push_dqual_reg = '1') then -- Load the Counter
sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
else
null; -- Hold Current value
end if;
end if;
end process DO_ADDR_LSB_CNTR;
----- Address posted Counter logic --------------------------------
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max);
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a register for the Address
-- Posted FIFO that operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
------- First/Middle/Last Dbeat detirmination -------------------
sig_new_len_eq_0 <= '1'
When (sig_fifo_next_len = LEN_OF_ZERO)
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_FIRST_MID_LAST
--
-- Process Description:
-- Implements the detection of the First/Mid/Last databeat of
-- a transfer.
--
-------------------------------------------------------------
DO_FIRST_MID_LAST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_first_dbeat <= not(sig_new_len_eq_0);
sig_last_dbeat <= sig_new_len_eq_0;
Elsif (sig_dbeat_cntr_eq_1 = '1' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '1';
Elsif (sig_dbeat_cntr_eq_0 = '0' and
sig_dbeat_cntr_eq_1 = '0' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
else
null; -- hols current state
end if;
end if;
end process DO_FIRST_MID_LAST;
------- Data Controller Halted Indication -------------------------------
data2all_dcntlr_halted <= sig_no_posted_cmds and
(sig_calc_error_reg or
rst2data_stop_request);
------- Data Beat counter logic -------------------------------
sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
sig_dbeat_cntr_eq_0 <= '1'
when (sig_dbeat_cntr_int = 0)
Else '0';
sig_dbeat_cntr_eq_1 <= '1'
when (sig_dbeat_cntr_int = 1)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DBEAT_CNTR
--
-- Process Description:
--
--
-------------------------------------------------------------
DO_DBEAT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dbeat_cntr <= (others => '0');
elsif (sig_ld_new_cmd = '1') then
sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
Elsif (sig_good_mmap_dbeat = '1' and
sig_dbeat_cntr_eq_0 = '0') Then
sig_dbeat_cntr <= sig_dbeat_cntr-1;
else
null; -- Hold current state
end if;
end if;
end process DO_DBEAT_CNTR;
------ Read Response Status Logic ------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: LD_NEW_CMD_PULSE
--
-- Process Description:
-- Generate a 1 Clock wide pulse when a new command has been
-- loaded into the Command Register
--
-------------------------------------------------------------
LD_NEW_CMD_PULSE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_ld_new_cmd_reg = '1') then
sig_ld_new_cmd_reg <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_ld_new_cmd_reg <= '1';
else
null; -- hold State
end if;
end if;
end process LD_NEW_CMD_PULSE;
sig_pop_coelsc_reg <= sig_coelsc_reg_full and
sig_rsc2data_ready ;
sig_push_coelsc_reg <= (sig_good_mmap_dbeat and
not(sig_coelsc_reg_full)) or
(sig_ld_new_cmd_reg and
sig_calc_error_reg) ;
sig_cmd_cmplt_last_dbeat <= (sig_cmd_cmplt_reg and sig_mmap2data_last) or
sig_calc_error_reg;
------- Read Response Decode
-- Decode the AXI MMap Read Response
sig_decerr <= '1'
When (mm2s_rresp = DECERR and mm2s_rvalid = '1')
Else '0';
sig_slverr <= '1'
When (mm2s_rresp = SLVERR and mm2s_rvalid = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: RD_RESP_COELESC_REG
--
-- Process Description:
-- Implement the Read error/status coelescing register.
-- Once a bit is set it will remain set until the overall
-- status is written to the Status Controller.
-- Tag bits are just registered at each valid dbeat.
--
-------------------------------------------------------------
STATUS_COELESC_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_coelsc_reg = '1' and -- Added more qualification here for simultaneus
sig_push_coelsc_reg = '0')) then -- push and pop condition per CR590244
sig_coelsc_tag_reg <= (others => '0');
sig_coelsc_cmd_cmplt_reg <= '0';
sig_coelsc_interr_reg <= '0';
sig_coelsc_decerr_reg <= '0';
sig_coelsc_slverr_reg <= '0';
sig_coelsc_okay_reg <= '1'; -- set back to default of "OKAY"
sig_coelsc_reg_full <= '0';
sig_coelsc_reg_empty <= '1';
Elsif (sig_push_coelsc_reg = '1') Then
sig_coelsc_tag_reg <= sig_tag_reg;
sig_coelsc_cmd_cmplt_reg <= sig_cmd_cmplt_last_dbeat;
sig_coelsc_interr_reg <= sig_calc_error_reg or
sig_coelsc_interr_reg;
sig_coelsc_decerr_reg <= sig_decerr or sig_coelsc_decerr_reg;
sig_coelsc_slverr_reg <= sig_slverr or sig_coelsc_slverr_reg;
sig_coelsc_okay_reg <= not(sig_decerr or
sig_slverr or
sig_calc_error_reg );
sig_coelsc_reg_full <= sig_cmd_cmplt_last_dbeat;
sig_coelsc_reg_empty <= not(sig_cmd_cmplt_last_dbeat);
else
null; -- hold current state
end if;
end if;
end process STATUS_COELESC_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DRE
--
-- If Generate Description:
-- Ties off DRE Control signals to logic low when DRE is
-- omitted from the MM2S functionality.
--
--
------------------------------------------------------------
GEN_NO_DRE : if (C_INCLUDE_DRE = 0) generate
begin
mm2s_dre_new_align <= '0';
mm2s_dre_use_autodest <= '0';
mm2s_dre_src_align <= (others => '0');
mm2s_dre_dest_align <= (others => '0');
mm2s_dre_flush <= '0';
end generate GEN_NO_DRE;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_DRE_CNTLS
--
-- If Generate Description:
-- Implements the DRE Control logic when MM2S DRE is enabled.
--
-- - The DRE needs to have forced alignment at a SOF assertion
--
--
------------------------------------------------------------
GEN_INCLUDE_DRE_CNTLS : if (C_INCLUDE_DRE = 1) generate
-- local signals
signal lsig_s_h_dre_autodest : std_logic := '0';
signal lsig_s_h_dre_new_align : std_logic := '0';
begin
mm2s_dre_new_align <= lsig_s_h_dre_new_align;
-- Autodest is asserted on a new parent command and the
-- previous parent command was not delimited with a EOF
mm2s_dre_use_autodest <= lsig_s_h_dre_autodest;
-- Assign the DRE Source and Destination Alignments
-- Only used when mm2s_dre_new_align is asserted
mm2s_dre_src_align <= sig_next_dre_src_align_reg ;
mm2s_dre_dest_align <= sig_next_dre_dest_align_reg;
-- Assert the Flush flag when the MMap Tlast input of the current transfer is
-- asserted and the next transfer is not sequential and not the last
-- transfer of a packet.
mm2s_dre_flush <= mm2s_rlast and
not(sig_next_sequential_reg) and
not(sig_next_eof_reg);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_S_H_NEW_ALIGN
--
-- Process Description:
-- Generates the new alignment command flag to the DRE.
--
-------------------------------------------------------------
IMP_S_H_NEW_ALIGN : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_s_h_dre_new_align <= '0';
Elsif (sig_push_dqual_reg = '1' and
sig_fifo_next_drr = '1') Then
lsig_s_h_dre_new_align <= '1';
elsif (sig_pop_dqual_reg = '1') then
lsig_s_h_dre_new_align <= sig_next_cmd_cmplt_reg and
not(sig_next_sequential_reg) and
not(sig_next_eof_reg);
Elsif (sig_good_mmap_dbeat = '1') Then
lsig_s_h_dre_new_align <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_S_H_NEW_ALIGN;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_S_H_AUTODEST
--
-- Process Description:
-- Generates the control for the DRE indicating whether the
-- DRE destination alignment should be derived from the write
-- strobe stat of the last completed data-beat to the AXI
-- stream output.
--
-------------------------------------------------------------
IMP_S_H_AUTODEST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_s_h_dre_autodest <= '0';
Elsif (sig_push_dqual_reg = '1' and
sig_fifo_next_drr = '1') Then
lsig_s_h_dre_autodest <= '0';
elsif (sig_pop_dqual_reg = '1') then
lsig_s_h_dre_autodest <= sig_next_cmd_cmplt_reg and
not(sig_next_sequential_reg) and
not(sig_next_eof_reg);
Elsif (lsig_s_h_dre_new_align = '1' and
sig_good_mmap_dbeat = '1') Then
lsig_s_h_dre_autodest <= '0';
else
null; -- hold current state
end if;
end if;
end process IMP_S_H_AUTODEST;
end generate GEN_INCLUDE_DRE_CNTLS;
------- Soft Shutdown Logic -------------------------------
-- Assign the output port skid buf control
data2skid_halt <= sig_data2skid_halt;
-- Create a 1 clock wide pulse to tell the output
-- stream skid buffer to shut down its outputs
sig_data2skid_halt <= sig_halt_reg_dly2 and
not(sig_halt_reg_dly3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
|
mit
|
Bjay1435/capstone
|
Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_addr_cntl.vhd
|
5
|
41585
|
----------------------------------------------------------------------------
-- axi_datamover_addr_cntl.vhd
----------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_addr_cntl.vhd
--
-- Description:
-- This file implements the axi_datamover Master Address Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_11;
Use axi_datamover_v5_1_11.axi_datamover_fifo;
-------------------------------------------------------------------------------
entity axi_datamover_addr_cntl is
generic (
C_ADDR_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- sets the depth of the Command Queue FIFO
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Sets the address bus width
C_ADDR_ID : Integer range 0 to 255 := 0;
-- Sets the value to be on the AxID output
C_ADDR_ID_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the AxID output
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Sets the width of the Command Tag field width
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family
);
port (
-- Clock input ---------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------
-- AXI Address Channel I/O --------------------------------------------
addr2axi_aid : out std_logic_vector(C_ADDR_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
addr2axi_aaddr : out std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
addr2axi_alen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
addr2axi_asize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
addr2axi_aburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_acache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_auser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel BURST output --
--
addr2axi_aprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
addr2axi_avalid : out std_logic; --
-- AXI Address Channel VALID output --
--
axi2addr_aready : in std_logic; --
-- AXI Address Channel READY input --
------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- Command Calculation Interface -----------------------------------------
mstr2addr_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2addr_addr : In std_logic_vector(C_ADDR_WIDTH-1 downto 0); --
-- The next command address to put on the AXI MMap ADDR --
--
mstr2addr_len : In std_logic_vector(7 downto 0); --
-- The next command length to put on the AXI MMap LEN --
-- Sized to support 256 data beat bursts --
--
mstr2addr_size : In std_logic_vector(2 downto 0); --
-- The next command size to put on the AXI MMap SIZE --
--
mstr2addr_burst : In std_logic_vector(1 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cache : In std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_user : In std_logic_vector(3 downto 0); --
-- The next command burst type to put on the AXI MMap BURST --
--
mstr2addr_cmd_cmplt : In std_logic; --
-- The indication to the Address Channel that the current --
-- sub-command output is the last one compiled from the --
-- parent command pulled from the Command FIFO --
--
mstr2addr_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2addr_cmd_valid : in std_logic; --
-- The next command valid indication to the Address Channel --
-- Controller for the AXI MMap --
--
addr2mstr_cmd_ready : out std_logic; --
-- Indication to the Command Calculator that the --
-- command is being accepted --
--------------------------------------------------------------------------
-- Halted Indication to Reset Module ------------------------------
addr2rst_stop_cmplt : out std_logic; --
-- Output flag indicating the address controller has stopped --
-- posting commands to the Address Channel due to a stop --
-- request vai the data2addr_stop_req input port --
------------------------------------------------------------------
-- Address Generation Control ---------------------------------------
allow_addr_req : in std_logic; --
-- Input used to enable/stall the posting of address requests. --
-- 0 = stall address request generation. --
-- 1 = Enable Address request geneartion --
--
addr_req_posted : out std_logic; --
-- Indication from the Address Channel Controller to external --
-- User logic that an address has been posted to the --
-- AXI Address Channel. --
---------------------------------------------------------------------
-- Data Channel Interface ---------------------------------------------
addr2data_addr_posted : Out std_logic; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel. --
--
data2addr_data_rdy : In std_logic; --
-- Indication that the Data Channel is ready to send the first --
-- databeat of the next command on the write data channel. --
-- This is used for the "wait for data" feature which keeps the --
-- address controller from issuing a transfer requset until the --
-- corresponding data is ready. This is expected to be held in --
-- the asserted state until the addr2data_addr_posted signal is --
-- asserted. --
--
data2addr_stop_req : In std_logic; --
-- Indication that the Data Channel has encountered an error --
-- or a soft shutdown request and needs the Address Controller --
-- to stop posting commands to the AXI Address channel --
-----------------------------------------------------------------------
-- Status Module Interface ---------------------------------------
addr2stat_calc_error : out std_logic; --
-- Indication to the Status Module that the Addr Cntl FIFO --
-- is loaded with a Calc error --
--
addr2stat_cmd_fifo_empty : out std_logic --
-- Indication to the Status Module that the Addr Cntl FIFO --
-- is empty --
------------------------------------------------------------------
);
end entity axi_datamover_addr_cntl;
architecture implementation of axi_datamover_addr_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Constant Declarations --------------------------------------------
Constant APROT_VALUE : std_logic_vector(2 downto 0) := (others => '0');
--'0' & -- bit 2, Normal Access
--'0' & -- bit 1, Nonsecure Access
--'0'; -- bit 0, Data Access
Constant LEN_WIDTH : integer := 8;
Constant SIZE_WIDTH : integer := 3;
Constant BURST_WIDTH : integer := 2;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant CALC_ERROR_WIDTH : integer := 1;
Constant ADDR_QUAL_WIDTH : integer := C_TAG_WIDTH + -- Cmd Tag field width
C_ADDR_WIDTH + -- Cmd Address field width
LEN_WIDTH + -- Cmd Len field width
SIZE_WIDTH + -- Cmd Size field width
BURST_WIDTH + -- Cmd Burst field width
CMD_CMPLT_WIDTH + -- Cmd Cmplt filed width
CALC_ERROR_WIDTH + -- Cmd Calc Error flag
8; -- Cmd Cache, user fields
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
-- Signal Declarations --------------------------------------------
signal sig_axi_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_axi_alen : std_logic_vector(7 downto 0) := (others => '0');
signal sig_axi_asize : std_logic_vector(2 downto 0) := (others => '0');
signal sig_axi_aburst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_axi_acache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_axi_auser : std_logic_vector(3 downto 0) := (others => '0');
signal sig_axi_avalid : std_logic := '0';
signal sig_axi_aready : std_logic := '0';
signal sig_addr_posted : std_logic := '0';
signal sig_calc_error : std_logic := '0';
signal sig_cmd_fifo_empty : std_logic := '0';
Signal sig_aq_fifo_data_in : std_logic_vector(ADDR_QUAL_WIDTH-1 downto 0) := (others => '0');
Signal sig_aq_fifo_data_out : std_logic_vector(ADDR_QUAL_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_addr : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_fifo_next_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_fifo_next_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_fifo_next_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_fifo_next_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_calc_error : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_addr_reg : std_logic_vector(C_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_next_len_reg : std_logic_vector(7 downto 0) := (others => '0');
signal sig_next_size_reg : std_logic_vector(2 downto 0) := (others => '0');
signal sig_next_burst_reg : std_logic_vector(1 downto 0) := (others => '0');
signal sig_next_cache_reg : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_user_reg : std_logic_vector(3 downto 0) := (others => '0');
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_addr_valid_reg : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_pop_addr_reg : std_logic := '0';
signal sig_push_addr_reg : std_logic := '0';
signal sig_addr_reg_empty : std_logic := '0';
signal sig_addr_reg_full : std_logic := '0';
signal sig_posted_to_axi : std_logic := '0';
-- obsoleted signal sig_set_wfd_flop : std_logic := '0';
-- obsoleted signal sig_clr_wfd_flop : std_logic := '0';
-- obsoleted signal sig_wait_for_data : std_logic := '0';
-- obsoleted signal sig_data2addr_data_rdy_reg : std_logic := '0';
signal sig_allow_addr_req : std_logic := '0';
signal sig_posted_to_axi_2 : std_logic := '0';
signal new_cmd_in : std_logic;
signal first_addr_valid : std_logic;
signal first_addr_valid_del : std_logic;
signal first_addr_int : std_logic_vector (C_ADDR_WIDTH-1 downto 0);
signal last_addr_int : std_logic_vector (C_ADDR_WIDTH-1 downto 0);
signal addr2axi_cache_int : std_logic_vector (7 downto 0);
signal addr2axi_cache_int1 : std_logic_vector (7 downto 0);
signal last_one : std_logic;
signal latch : std_logic;
signal first_one : std_logic;
signal latch_n : std_logic;
signal latch_n_del : std_logic;
signal mstr2addr_cache_info_int : std_logic_vector (7 downto 0);
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_posted_to_axi : signal is "TRUE"; -- definition
Attribute KEEP of sig_posted_to_axi_2 : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_posted_to_axi : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_posted_to_axi_2 : signal is "no";
begin --(architecture implementation)
-- AXI I/O Port assignments
addr2axi_aid <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_ADDR_ID, C_ADDR_ID_WIDTH));
addr2axi_aaddr <= sig_axi_addr ;
addr2axi_alen <= sig_axi_alen ;
addr2axi_asize <= sig_axi_asize ;
addr2axi_aburst <= sig_axi_aburst;
addr2axi_acache <= sig_axi_acache;
addr2axi_auser <= sig_axi_auser;
addr2axi_aprot <= APROT_VALUE ;
addr2axi_avalid <= sig_axi_avalid;
sig_axi_aready <= axi2addr_aready;
-- Command Calculator Handshake output
sig_fifo_wr_cmd_valid <= mstr2addr_cmd_valid ;
addr2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
-- Data Channel Controller synchro pulse output
addr2data_addr_posted <= sig_addr_posted;
-- Status Module Interface outputs
addr2stat_calc_error <= sig_calc_error ;
addr2stat_cmd_fifo_empty <= sig_addr_reg_empty and
sig_cmd_fifo_empty;
-- Flag Indicating the Address Controller has completed a Stop
addr2rst_stop_cmplt <= (data2addr_stop_req and -- normal shutdown case
sig_addr_reg_empty) or
(data2addr_stop_req and -- shutdown after error trap
sig_calc_error);
-- Assign the address posting control and status
sig_allow_addr_req <= allow_addr_req ;
addr_req_posted <= sig_posted_to_axi_2 ;
-- Internal logic ------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ADDR_FIFO
--
-- If Generate Description:
-- Implements the case where the cmd qualifier depth is
-- greater than 1.
--
------------------------------------------------------------
GEN_ADDR_FIFO : if (C_ADDR_FIFO_DEPTH > 1) generate
begin
-- Format the input FIFO data word
sig_aq_fifo_data_in <= mstr2addr_cache &
mstr2addr_user &
mstr2addr_calc_error &
mstr2addr_cmd_cmplt &
mstr2addr_burst &
mstr2addr_size &
mstr2addr_len &
mstr2addr_addr &
mstr2addr_tag ;
-- Rip fields from FIFO output data word
sig_fifo_next_cache <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH + 7)
downto
(C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH + 4)
);
sig_fifo_next_user <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH + 3)
downto
(C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH)
);
sig_fifo_calc_error <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH +
CALC_ERROR_WIDTH)-1);
sig_fifo_next_cmd_cmplt <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH +
CMD_CMPLT_WIDTH)-1);
sig_fifo_next_burst <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH +
BURST_WIDTH)-1
downto
C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH) ;
sig_fifo_next_size <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH +
SIZE_WIDTH)-1
downto
C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH) ;
sig_fifo_next_len <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH +
LEN_WIDTH)-1
downto
C_ADDR_WIDTH +
C_TAG_WIDTH) ;
sig_fifo_next_addr <= sig_aq_fifo_data_out((C_ADDR_WIDTH +
C_TAG_WIDTH)-1
downto
C_TAG_WIDTH) ;
sig_fifo_next_tag <= sig_aq_fifo_data_out(C_TAG_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_ADDR_QUAL_FIFO
--
-- Description:
-- Instance for the Address/Qualifier FIFO
--
------------------------------------------------------------
I_ADDR_QUAL_FIFO : entity axi_datamover_v5_1_11.axi_datamover_fifo
generic map (
C_DWIDTH => ADDR_QUAL_WIDTH ,
C_DEPTH => C_ADDR_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_aq_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_aq_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_ADDR_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_ADDR_FIFO
--
-- If Generate Description:
-- Implements the case where no additional FIFOing is needed
-- on the input command address/qualifiers.
--
------------------------------------------------------------
GEN_NO_ADDR_FIFO : if (C_ADDR_FIFO_DEPTH = 1) generate
begin
-- Bypass FIFO
sig_fifo_next_tag <= mstr2addr_tag ;
sig_fifo_next_addr <= mstr2addr_addr ;
sig_fifo_next_len <= mstr2addr_len ;
sig_fifo_next_size <= mstr2addr_size ;
sig_fifo_next_burst <= mstr2addr_burst ;
sig_fifo_next_cache <= mstr2addr_cache ;
sig_fifo_next_user <= mstr2addr_user ;
sig_fifo_next_cmd_cmplt <= mstr2addr_cmd_cmplt ;
sig_fifo_calc_error <= mstr2addr_calc_error ;
sig_cmd_fifo_empty <= sig_addr_reg_empty ;
sig_fifo_wr_cmd_ready <= sig_fifo_rd_cmd_ready ;
sig_fifo_rd_cmd_valid <= sig_fifo_wr_cmd_valid ;
end generate GEN_NO_ADDR_FIFO;
-- Output Register Logic -------------------------------------------
sig_axi_addr <= sig_next_addr_reg ;
sig_axi_alen <= sig_next_len_reg ;
sig_axi_asize <= sig_next_size_reg ;
sig_axi_aburst <= sig_next_burst_reg ;
sig_axi_acache <= sig_next_cache_reg ;
sig_axi_auser <= sig_next_user_reg ;
sig_axi_avalid <= sig_addr_valid_reg ;
sig_calc_error <= sig_calc_error_reg ;
sig_fifo_rd_cmd_ready <= sig_addr_reg_empty and
sig_allow_addr_req and
-- obsoleted not(sig_wait_for_data) and
not(data2addr_stop_req);
sig_addr_posted <= sig_posted_to_axi ;
-- Internal signals
sig_push_addr_reg <= sig_addr_reg_empty and
sig_fifo_rd_cmd_valid and
sig_allow_addr_req and
-- obsoleted not(sig_wait_for_data) and
not(data2addr_stop_req);
sig_pop_addr_reg <= not(sig_calc_error_reg) and
sig_axi_aready and
sig_addr_reg_full;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_FIFO_REG
--
-- Process Description:
-- This process implements a register for the Address
-- Control FIFO that operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_ADDR_FIFO_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_pop_addr_reg = '1') then
sig_next_tag_reg <= (others => '0') ;
sig_next_addr_reg <= (others => '0') ;
sig_next_len_reg <= (others => '0') ;
sig_next_size_reg <= (others => '0') ;
sig_next_burst_reg <= (others => '0') ;
sig_next_cache_reg <= (others => '0') ;
sig_next_user_reg <= (others => '0') ;
sig_next_cmd_cmplt_reg <= '0' ;
sig_addr_valid_reg <= '0' ;
sig_calc_error_reg <= '0' ;
sig_addr_reg_empty <= '1' ;
sig_addr_reg_full <= '0' ;
elsif (sig_push_addr_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_addr_reg <= sig_fifo_next_addr ;
sig_next_len_reg <= sig_fifo_next_len ;
sig_next_size_reg <= sig_fifo_next_size ;
sig_next_burst_reg <= sig_fifo_next_burst ;
sig_next_cache_reg <= sig_fifo_next_cache ;
sig_next_user_reg <= sig_fifo_next_user ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_addr_valid_reg <= not(sig_fifo_calc_error);
sig_calc_error_reg <= sig_fifo_calc_error ;
sig_addr_reg_empty <= '0' ;
sig_addr_reg_full <= '1' ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_FIFO_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_POSTED_FLAG
--
-- Process Description:
-- This implements a FLOP that creates a 1 clock wide pulse
-- indicating a new address/qualifier set has been posted to
-- the AXI Addres Channel outputs. This is used to synchronize
-- the Data Channel Controller.
--
-------------------------------------------------------------
IMP_POSTED_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_posted_to_axi <= '0';
sig_posted_to_axi_2 <= '0';
elsif (sig_push_addr_reg = '1') then
sig_posted_to_axi <= '1';
sig_posted_to_axi_2 <= '1';
else
sig_posted_to_axi <= '0';
sig_posted_to_axi_2 <= '0';
end if;
end if;
end process IMP_POSTED_FLAG;
-- PROC_CMD_DETECT : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- first_addr_valid_del <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- first_addr_valid_del <= first_addr_valid;
-- end if;
-- end process PROC_CMD_DETECT;
--
-- PROC_ADDR_DET : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- first_addr_valid <= '0';
-- first_addr_int <= (others => '0');
-- last_addr_int <= (others => '0');
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- if (mstr2addr_cmd_valid = '1' and first_addr_valid = '0') then
-- first_addr_valid <= '1';
-- first_addr_int <= mstr2addr_addr;
-- last_addr_int <= last_addr_int;
-- elsif (mstr2addr_cmd_cmplt = '1') then
-- first_addr_valid <= '0';
-- first_addr_int <= first_addr_int;
-- last_addr_int <= mstr2addr_addr;
-- end if;
-- end if;
-- end process PROC_ADDR_DET;
--
-- latch <= first_addr_valid and (not first_addr_valid_del);
-- latch_n <= (not first_addr_valid) and first_addr_valid_del;
--
-- PROC_CACHE1 : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- mstr2addr_cache_info_int <= (others => '0');
-- latch_n_del <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- if (latch_n = '1') then
-- mstr2addr_cache_info_int <= mstr2addr_cache_info;
-- end if;
-- latch_n_del <= latch_n;
-- end if;
-- end process PROC_CACHE1;
--
--
-- PROC_CACHE : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- addr2axi_cache_int1 <= (others => '0');
-- first_one <= '0';
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- first_one <= '0';
---- if (latch = '1' and first_one = '0') then -- first one
-- if (sig_addr_valid_reg = '0' and first_addr_valid = '0') then
-- addr2axi_cache_int1 <= mstr2addr_cache_info;
---- first_one <= '1';
---- elsif (latch_n_del = '1') then
---- addr2axi_cache_int <= mstr2addr_cache_info_int;
-- elsif ((first_addr_int = sig_next_addr_reg) and (sig_addr_valid_reg = '1')) then
-- addr2axi_cache_int1 <= addr2axi_cache_int1; --mstr2addr_cache_info (7 downto 4);
-- elsif ((last_addr_int >= sig_next_addr_reg) and (sig_addr_valid_reg = '1')) then
-- addr2axi_cache_int1 <= addr2axi_cache_int1; --mstr2addr_cache_info (7 downto 4);
-- end if;
-- end if;
-- end process PROC_CACHE;
--
--
-- PROC_CACHE2 : process (primary_aclk)
-- begin
-- if (mmap_reset = '1') then
-- addr2axi_cache_int <= (others => '0');
-- elsif (primary_aclk'event and primary_aclk = '1') then
-- addr2axi_cache_int <= addr2axi_cache_int1;
-- end if;
-- end process PROC_CACHE2;
--
--addr2axi_cache <= addr2axi_cache_int (3 downto 0);
--addr2axi_user <= addr2axi_cache_int (7 downto 4);
--
end implementation;
|
mit
|
Bjay1435/capstone
|
Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_lite_if.vhd
|
1
|
61582
|
-------------------------------------------------------------------------------
-- axi_dma_lite_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_dma_lite_if.vhd
-- Description: This entity is AXI Lite Interface Module for the AXI DMA
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_10;
use axi_dma_v7_1_10.axi_dma_pkg.all;
library lib_pkg_v1_0_2;
library lib_cdc_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_dma_lite_if is
generic(
C_NUM_CE : integer := 8 ;
C_AXI_LITE_IS_ASYNC : integer range 0 to 1 := 0 ;
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 32 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32
);
port (
-- Async clock input
ip2axi_aclk : in std_logic ; --
ip2axi_aresetn : in std_logic ; --
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
s_axi_lite_aclk : in std_logic ; --
s_axi_lite_aresetn : in std_logic ; --
--
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic ; --
s_axi_lite_awready : out std_logic ; --
s_axi_lite_awaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic ; --
s_axi_lite_arready : out std_logic ; --
s_axi_lite_araddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
-- User IP Interface --
axi2ip_wrce : out std_logic_vector --
(C_NUM_CE-1 downto 0) ; --
axi2ip_wrdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
axi2ip_rdce : out std_logic_vector --
(C_NUM_CE-1 downto 0) ; --
axi2ip_rdaddr : out std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
ip2axi_rddata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) --
);
end axi_dma_lite_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_lite_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Register I/F Address offset
constant ADDR_OFFSET : integer := clog2(C_S_AXI_LITE_DATA_WIDTH/8);
-- Register I/F CE number
constant CE_ADDR_SIZE : integer := clog2(C_NUM_CE);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- AXI Lite slave interface signals
signal awvalid : std_logic := '0';
signal awaddr : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal wvalid : std_logic := '0';
signal wdata : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal arvalid : std_logic := '0';
signal araddr : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal awvalid_d1 : std_logic := '0';
signal awvalid_re : std_logic := '0';
signal awready_i : std_logic := '0';
signal wvalid_d1 : std_logic := '0';
signal wvalid_re : std_logic := '0';
signal wready_i : std_logic := '0';
signal bvalid_i : std_logic := '0';
signal wr_addr_cap : std_logic := '0';
signal wr_data_cap : std_logic := '0';
-- AXI to IP interface signals
signal axi2ip_wraddr_i : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_wrdata_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_wren : std_logic := '0';
signal wrce : std_logic_vector(C_NUM_CE-1 downto 0);
signal rdce : std_logic_vector(C_NUM_CE-1 downto 0) := (others => '0');
signal arvalid_d1 : std_logic := '0';
signal arvalid_re : std_logic := '0';
signal arvalid_re_d1 : std_logic := '0';
signal arvalid_i : std_logic := '0';
signal arready_i : std_logic := '0';
signal rvalid : std_logic := '0';
signal axi2ip_rdaddr_i : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s_axi_lite_rvalid_i : std_logic := '0';
signal read_in_progress : std_logic := '0'; -- CR607165
signal rst_rvalid_re : std_logic := '0'; -- CR576999
signal rst_wvalid_re : std_logic := '0'; -- CR576999
signal rdy : std_logic := '0';
signal rdy1 : std_logic := '0';
signal wr_in_progress : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
--*****************************************************************************
--** AXI LITE READ
--*****************************************************************************
s_axi_lite_wready <= wready_i;
s_axi_lite_awready <= awready_i;
s_axi_lite_arready <= arready_i;
s_axi_lite_bvalid <= bvalid_i;
-------------------------------------------------------------------------------
-- Register AXI Inputs
-------------------------------------------------------------------------------
REG_INPUTS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
awvalid <= '0' ;
awaddr <= (others => '0') ;
wvalid <= '0' ;
wdata <= (others => '0') ;
arvalid <= '0' ;
araddr <= (others => '0') ;
else
awvalid <= s_axi_lite_awvalid ;
awaddr <= s_axi_lite_awaddr ;
wvalid <= s_axi_lite_wvalid ;
wdata <= s_axi_lite_wdata ;
arvalid <= s_axi_lite_arvalid ;
araddr <= s_axi_lite_araddr ;
end if;
end if;
end process REG_INPUTS;
-- s_axi_lite_aclk is synchronous to ip clock
GEN_SYNC_WRITE : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
-------------------------------------------------------------------------------
-- Assert Write Adddress Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_AWVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
awvalid_d1 <= '0';
-- awvalid_re <= '0'; -- CR605883
else
awvalid_d1 <= awvalid;
-- awvalid_re <= awvalid and not awvalid_d1; -- CR605883
end if;
end if;
end process REG_AWVALID;
awvalid_re <= awvalid and not awvalid_d1 and (not (wr_in_progress)); -- CR605883
-------------------------------------------------------------------------------
-- Capture assertion of awvalid to indicate that we have captured
-- a valid address
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Assert Write Data Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_WVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wvalid_d1 <= '0';
-- wvalid_re <= '0';
else
wvalid_d1 <= wvalid;
-- wvalid_re <= wvalid and not wvalid_d1; -- CR605883
end if;
end if;
end process REG_WVALID;
wvalid_re <= wvalid and not wvalid_d1; -- CR605883
WRITE_IN_PROGRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wr_in_progress <= '0';
elsif(awvalid_re = '1')then
wr_in_progress <= '1';
end if;
end if;
end process WRITE_IN_PROGRESS;
-- CR605883 (CDC) provide pure register output to synchronizers
--wvalid_re <= wvalid and not wvalid_d1 and not rst_wvalid_re;
-------------------------------------------------------------------------------
-- Capture assertion of wvalid to indicate that we have captured
-- valid data
-------------------------------------------------------------------------------
WRDATA_CAP_FLAG : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rdy = '1')then
wr_data_cap <= '0';
elsif(wvalid_re = '1')then
wr_data_cap <= '1';
end if;
end if;
end process WRDATA_CAP_FLAG;
REG_WREADY : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rdy = '1') then
rdy <= '0';
elsif (wr_data_cap = '1' and wr_addr_cap = '1') then
rdy <= '1';
end if;
wready_i <= rdy;
awready_i <= rdy;
rdy1 <= rdy;
end if;
end process REG_WREADY;
WRADDR_CAP_FLAG : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rdy = '1')then
wr_addr_cap <= '0';
elsif(awvalid_re = '1')then
wr_addr_cap <= '1';
end if;
end if;
end process WRADDR_CAP_FLAG;
-------------------------------------------------------------------------------
-- Capture Write Address
-------------------------------------------------------------------------------
REG_WRITE_ADDRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
-- axi2ip_wraddr_i <= (others => '0');
-- Register address on valid
elsif(awvalid_re = '1')then
-- axi2ip_wraddr_i <= awaddr;
end if;
end if;
end process REG_WRITE_ADDRESS;
-------------------------------------------------------------------------------
-- Capture Write Data
-------------------------------------------------------------------------------
REG_WRITE_DATA : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_wrdata_i <= (others => '0');
-- Register address and assert ready
elsif(wvalid_re = '1')then
axi2ip_wrdata_i <= wdata;
end if;
end if;
end process REG_WRITE_DATA;
-------------------------------------------------------------------------------
-- Must have both a valid address and valid data before updating
-- a register. Note in AXI write address can come before or
-- after AXI write data.
-- axi2ip_wren <= '1' when wr_data_cap = '1' and wr_addr_cap = '1'
-- else '0';
axi2ip_wren <= rdy; -- or rdy1;
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
WRCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
wrce(j) <= axi2ip_wren when s_axi_lite_awaddr
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate WRCE_GEN;
-------------------------------------------------------------------------------
-- register write ce's and data out to axi dma register module
-------------------------------------------------------------------------------
REG_WR_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_wrce <= (others => '0');
-- axi2ip_wrdata <= (others => '0');
else
axi2ip_wrce <= wrce;
-- axi2ip_wrdata <= axi2ip_wrdata_i;
end if;
end if;
end process REG_WR_OUT;
axi2ip_wrdata <= s_axi_lite_wdata;
-------------------------------------------------------------------------------
-- Write Response
-------------------------------------------------------------------------------
s_axi_lite_bresp <= OKAY_RESP;
WRESP_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- If response issued and target indicates ready then
-- clear response
elsif(bvalid_i = '1' and s_axi_lite_bready = '1')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- Issue a resonse on write
elsif(rdy1 = '1')then
bvalid_i <= '1';
rst_wvalid_re <= '1'; -- CR576999
end if;
end if;
end process WRESP_PROCESS;
end generate GEN_SYNC_WRITE;
-- s_axi_lite_aclk is asynchronous to ip clock
GEN_ASYNC_WRITE : if C_AXI_LITE_IS_ASYNC = 1 generate
-- Data support
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
signal ip_wvalid_d1_cdc_to : std_logic := '0';
signal ip_wvalid_d2 : std_logic := '0';
signal ip_wvalid_re : std_logic := '0';
signal wr_wvalid_re_cdc_from : std_logic := '0';
signal wr_data_cdc_from : std_logic_vector -- CR605883
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); -- CR605883
signal wdata_d1_cdc_to : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal wdata_d2 : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_wrdata_cdc_tig : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal ip_data_cap : std_logic := '0';
-- Address support
signal ip_awvalid_d1_cdc_to : std_logic := '0';
signal ip_awvalid_d2 : std_logic := '0';
signal ip_awvalid_re : std_logic := '0';
signal wr_awvalid_re_cdc_from : std_logic := '0';
signal wr_addr_cdc_from : std_logic_vector -- CR605883
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); -- CR605883
signal awaddr_d1_cdc_tig : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal awaddr_d2 : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ip_addr_cap : std_logic := '0';
-- Bvalid support
signal lite_data_cap_d1 : std_logic := '0';
signal lite_data_cap_d2 : std_logic := '0';
signal lite_addr_cap_d1 : std_logic := '0';
signal lite_addr_cap_d2 : std_logic := '0';
signal lite_axi2ip_wren : std_logic := '0';
signal awvalid_cdc_from : std_logic := '0';
signal awvalid_cdc_to : std_logic := '0';
signal awvalid_to : std_logic := '0';
signal awvalid_to2 : std_logic := '0';
--ATTRIBUTE async_reg OF awvalid_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF awvalid_to : SIGNAL IS "true";
signal wvalid_cdc_from : std_logic := '0';
signal wvalid_cdc_to : std_logic := '0';
signal wvalid_to : std_logic := '0';
signal wvalid_to2 : std_logic := '0';
--ATTRIBUTE async_reg OF wvalid_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF wvalid_to : SIGNAL IS "true";
signal rdy_cdc_to : std_logic := '0';
signal rdy_cdc_from : std_logic := '0';
signal rdy_to : std_logic := '0';
signal rdy_to2 : std_logic := '0';
signal rdy_to2_cdc_from : std_logic := '0';
signal rdy_out : std_logic := '0';
--ATTRIBUTE async_reg OF rdy_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF rdy_to : SIGNAL IS "true";
Attribute KEEP of rdy_to2_cdc_from : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of rdy_to2_cdc_from : signal is "no";
signal rdy_back_cdc_to : std_logic := '0';
signal rdy_back_to : std_logic :='0';
--ATTRIBUTE async_reg OF rdy_back_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF rdy_back_to : SIGNAL IS "true";
signal rdy_back : std_logic := '0';
signal rdy_shut : std_logic := '0';
begin
REG_AWVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
awvalid_d1 <= '0';
else
awvalid_d1 <= awvalid;
end if;
end if;
end process REG_AWVALID;
awvalid_re <= awvalid and not awvalid_d1 and (not (wr_in_progress)); -- CR605883
-------------------------------------------------------------------------------
-- Capture assertion of awvalid to indicate that we have captured
-- a valid address
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Assert Write Data Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_WVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wvalid_d1 <= '0';
else
wvalid_d1 <= wvalid;
end if;
end if;
end process REG_WVALID;
wvalid_re <= wvalid and not wvalid_d1; -- CR605883
--*************************************************************************
--** Write Address Support
--*************************************************************************
AWVLD_CDC_FROM : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
awvalid_cdc_from <= '0';
elsif(awvalid_re = '1')then
awvalid_cdc_from <= '1';
end if;
end if;
end process AWVLD_CDC_FROM;
AWVLD_CDC_TO : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => awvalid_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => awvalid_to,
scndry_vect_out => open
);
-- AWVLD_CDC_TO : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- awvalid_cdc_to <= awvalid_cdc_from;
-- awvalid_to <= awvalid_cdc_to;
-- end if;
-- end process AWVLD_CDC_TO;
AWVLD_CDC_TO2 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
awvalid_to2 <= '0';
else
awvalid_to2 <= awvalid_to;
end if;
end if;
end process AWVLD_CDC_TO2;
ip_awvalid_re <= awvalid_to and (not awvalid_to2);
WVLD_CDC_FROM : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wvalid_cdc_from <= '0';
elsif(wvalid_re = '1')then
wvalid_cdc_from <= '1';
end if;
end if;
end process WVLD_CDC_FROM;
WVLD_CDC_TO : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => wvalid_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => wvalid_to,
scndry_vect_out => open
);
-- WVLD_CDC_TO : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- wvalid_cdc_to <= wvalid_cdc_from;
-- wvalid_to <= wvalid_cdc_to;
-- end if;
-- end process WVLD_CDC_TO;
WVLD_CDC_TO2 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
wvalid_to2 <= '0';
else
wvalid_to2 <= wvalid_to;
end if;
end if;
end process WVLD_CDC_TO2;
ip_wvalid_re <= wvalid_to and (not wvalid_to2);
REG_WADDR_TO_IPCLK : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH,
C_MTBF_STAGES => 1
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => s_axi_lite_awaddr,
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => awaddr_d1_cdc_tig
);
REG_WADDR_TO_IPCLK1 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_S_AXI_LITE_DATA_WIDTH,
C_MTBF_STAGES => 1
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => s_axi_lite_wdata,
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => axi2ip_wrdata_cdc_tig
);
-- Double register address in
-- REG_WADDR_TO_IPCLK : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- if(ip2axi_aresetn = '0')then
-- awaddr_d1_cdc_tig <= (others => '0');
-- -- axi2ip_wraddr_i <= (others => '0');
-- axi2ip_wrdata_cdc_tig <= (others => '0');
-- else
-- awaddr_d1_cdc_tig <= s_axi_lite_awaddr;
-- axi2ip_wrdata_cdc_tig <= s_axi_lite_wdata;
-- -- axi2ip_wraddr_i <= awaddr_d1_cdc_tig; -- CR605883
-- end if;
-- end if;
-- end process REG_WADDR_TO_IPCLK;
-- Flag that address has been captured
REG_IP_ADDR_CAP : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1')then
ip_addr_cap <= '0';
elsif(ip_awvalid_re = '1')then
ip_addr_cap <= '1';
end if;
end if;
end process REG_IP_ADDR_CAP;
REG_WREADY : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1') then -- or rdy = '1') then
rdy <= '0';
elsif (ip_data_cap = '1' and ip_addr_cap = '1') then
rdy <= '1';
end if;
end if;
end process REG_WREADY;
REG3_WREADY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => rdy_to2_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => rdy_back_to,
scndry_vect_out => open
);
-- REG3_WREADY : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- rdy_back_cdc_to <= rdy_to2_cdc_from;
-- rdy_back_to <= rdy_back_cdc_to;
-- end if;
-- end process REG3_WREADY;
REG3_WREADY2 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0') then
rdy_back <= '0';
else
rdy_back <= rdy_back_to;
end if;
end if;
end process REG3_WREADY2;
rdy_shut <= rdy_back_to and (not rdy_back);
REG1_WREADY : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1') then
rdy_cdc_from <= '0';
elsif (rdy = '1') then
rdy_cdc_from <= '1';
end if;
end if;
end process REG1_WREADY;
REG2_WREADY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => ip2axi_aclk,
prmry_resetn => '0',
prmry_in => rdy_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => rdy_to,
scndry_vect_out => open
);
-- REG2_WREADY : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- rdy_cdc_to <= rdy_cdc_from;
-- rdy_to <= rdy_cdc_to;
-- end if;
-- end process REG2_WREADY;
REG2_WREADY2 : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0') then
rdy_to2 <= '0';
rdy_to2_cdc_from <= '0';
else
rdy_to2 <= rdy_to;
rdy_to2_cdc_from <= rdy_to;
end if;
end if;
end process REG2_WREADY2;
rdy_out <= not (rdy_to) and rdy_to2;
wready_i <= rdy_out;
awready_i <= rdy_out;
--*************************************************************************
--** Write Data Support
--*************************************************************************
-------------------------------------------------------------------------------
-- Capture write data
-------------------------------------------------------------------------------
-- WRDATA_S_H : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(s_axi_lite_aresetn = '0')then
-- wr_data_cdc_from <= (others => '0');
-- elsif(wvalid_re = '1')then
-- wr_data_cdc_from <= wdata;
-- end if;
-- end if;
-- end process WRDATA_S_H;
-- Flag that data has been captured
REG_IP_DATA_CAP : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1')then
ip_data_cap <= '0';
elsif(ip_wvalid_re = '1')then
ip_data_cap <= '1';
end if;
end if;
end process REG_IP_DATA_CAP;
-- Must have both a valid address and valid data before updating
-- a register. Note in AXI write address can come before or
-- after AXI write data.
axi2ip_wren <= rdy;
-- axi2ip_wren <= '1' when ip_data_cap = '1' and ip_addr_cap = '1'
-- else '0';
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
WRCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
wrce(j) <= axi2ip_wren when awaddr_d1_cdc_tig
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate WRCE_GEN;
-------------------------------------------------------------------------------
-- register write ce's and data out to axi dma register module
-------------------------------------------------------------------------------
REG_WR_OUT : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
axi2ip_wrce <= (others => '0');
else
axi2ip_wrce <= wrce;
end if;
end if;
end process REG_WR_OUT;
axi2ip_wrdata <= axi2ip_wrdata_cdc_tig; --s_axi_lite_wdata;
--*************************************************************************
--** Write Response Support
--*************************************************************************
-- Minimum of 2 IP clocks for addr and data capture, therefore delaying
-- Lite clock addr and data capture by 2 Lite clocks will guarenttee bvalid
-- responce occurs after write data acutally written.
-- REG_ALIGN_CAP : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(s_axi_lite_aresetn = '0')then
-- lite_data_cap_d1 <= '0';
-- lite_data_cap_d2 <= '0';
-- lite_addr_cap_d1 <= '0';
-- lite_addr_cap_d2 <= '0';
-- else
-- lite_data_cap_d1 <= rdy; --wr_data_cap;
-- lite_data_cap_d2 <= lite_data_cap_d1;
-- lite_addr_cap_d1 <= rdy; --wr_addr_cap;
-- lite_addr_cap_d2 <= lite_addr_cap_d1;
-- end if;
-- end if;
-- end process REG_ALIGN_CAP;
-- Pseudo write enable used simply to assert bvalid
-- lite_axi2ip_wren <= rdy; --'1' when wr_data_cap = '1' and wr_addr_cap = '1'
-- else '0';
WRESP_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- If response issued and target indicates ready then
-- clear response
elsif(bvalid_i = '1' and s_axi_lite_bready = '1')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- Issue a resonse on write
elsif(rdy_out = '1')then
-- elsif(lite_axi2ip_wren = '1')then
bvalid_i <= '1';
rst_wvalid_re <= '1'; -- CR576999
end if;
end if;
end process WRESP_PROCESS;
s_axi_lite_bresp <= OKAY_RESP;
end generate GEN_ASYNC_WRITE;
--*****************************************************************************
--** AXI LITE READ
--*****************************************************************************
-------------------------------------------------------------------------------
-- Assert Read Adddress Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_ARVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_rvalid_re = '1')then
arvalid_d1 <= '0';
else
arvalid_d1 <= arvalid;
end if;
end if;
end process REG_ARVALID;
arvalid_re <= arvalid and not arvalid_d1
and not rst_rvalid_re and not read_in_progress; -- CR607165
-- register for proper alignment
REG_ARREADY : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arready_i <= '0';
else
arready_i <= arvalid_re;
end if;
end if;
end process REG_ARREADY;
-- Always respond 'okay' axi lite read
s_axi_lite_rresp <= OKAY_RESP;
s_axi_lite_rvalid <= s_axi_lite_rvalid_i;
-- s_axi_lite_aclk is synchronous to ip clock
GEN_SYNC_READ : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
read_in_progress <= '0'; --Not used for sync mode (CR607165)
-------------------------------------------------------------------------------
-- Capture Read Address
-------------------------------------------------------------------------------
REG_READ_ADDRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_rdaddr_i <= (others => '0');
-- Register address on valid
elsif(arvalid_re = '1')then
axi2ip_rdaddr_i <= araddr;
end if;
end if;
end process REG_READ_ADDRESS;
-------------------------------------------------------------------------------
-- Generate RdCE based on address match to address bar
-------------------------------------------------------------------------------
RDCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
rdce(j) <= arvalid_re_d1
when axi2ip_rdaddr_i((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate RDCE_GEN;
-------------------------------------------------------------------------------
-- Register out to IP
-------------------------------------------------------------------------------
REG_RDCNTRL_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
--axi2ip_rdce <= (others => '0');
axi2ip_rdaddr <= (others => '0');
else
--axi2ip_rdce <= rdce;
axi2ip_rdaddr <= axi2ip_rdaddr_i;
end if;
end if;
end process REG_RDCNTRL_OUT;
-- Sample and hold rdce value until rvalid assertion
REG_RDCE_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_rvalid_re = '1')then
axi2ip_rdce <= (others => '0');
elsif(arvalid_re_d1 = '1')then
axi2ip_rdce <= rdce;
end if;
end if;
end process REG_RDCE_OUT;
-- Register for proper alignment
REG_RVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arvalid_re_d1 <= '0';
rvalid <= '0';
else
arvalid_re_d1 <= arvalid_re;
rvalid <= arvalid_re_d1;
end if;
end if;
end process REG_RVALID;
-------------------------------------------------------------------------------
-- Drive read data and read data valid out on capture of valid address.
-------------------------------------------------------------------------------
REG_RD_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If rvalid driving out to target and target indicates ready
-- then de-assert rvalid. (structure guarentees min 1 clock of rvalid)
elsif(s_axi_lite_rvalid_i = '1' and s_axi_lite_rready = '1')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If read cycle then assert rvalid and rdata out to target
elsif(rvalid = '1')then
s_axi_lite_rdata <= ip2axi_rddata;
s_axi_lite_rvalid_i <= '1';
rst_rvalid_re <= '1'; -- CR576999
end if;
end if;
end process REG_RD_OUT;
end generate GEN_SYNC_READ;
-- s_axi_lite_aclk is asynchronous to ip clock
GEN_ASYNC_READ : if C_AXI_LITE_IS_ASYNC = 1 generate
ATTRIBUTE async_reg : STRING;
signal ip_arvalid_d1_cdc_tig : std_logic := '0';
signal ip_arvalid_d2 : std_logic := '0';
signal ip_arvalid_d3 : std_logic := '0';
signal ip_arvalid_re : std_logic := '0';
signal araddr_d1_cdc_tig : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) :=(others => '0');
signal araddr_d2 : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) :=(others => '0');
signal araddr_d3 : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) :=(others => '0');
signal lite_rdata_cdc_from : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
signal lite_rdata_d1_cdc_to : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
signal lite_rdata_d2 : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
--ATTRIBUTE async_reg OF ip_arvalid_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF ip_arvalid_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF araddr_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF araddr_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF lite_rdata_d1_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF lite_rdata_d2 : SIGNAL IS "true";
signal p_pulse_s_h : std_logic := '0';
signal p_pulse_s_h_clr : std_logic := '0';
signal s_pulse_d1 : std_logic := '0';
signal s_pulse_d2 : std_logic := '0';
signal s_pulse_d3 : std_logic := '0';
signal s_pulse_re : std_logic := '0';
signal p_pulse_re_d1 : std_logic := '0';
signal p_pulse_re_d2 : std_logic := '0';
signal p_pulse_re_d3 : std_logic := '0';
signal arready_d1 : std_logic := '0'; -- CR605883
signal arready_d2 : std_logic := '0'; -- CR605883
signal arready_d3 : std_logic := '0'; -- CR605883
signal arready_d4 : std_logic := '0'; -- CR605883
signal arready_d5 : std_logic := '0'; -- CR605883
signal arready_d6 : std_logic := '0'; -- CR605883
signal arready_d7 : std_logic := '0'; -- CR605883
signal arready_d8 : std_logic := '0'; -- CR605883
signal arready_d9 : std_logic := '0'; -- CR605883
signal arready_d10 : std_logic := '0'; -- CR605883
signal arready_d11 : std_logic := '0'; -- CR605883
signal arready_d12 : std_logic := '0'; -- CR605883
begin
-- CR607165
-- Flag to prevent overlapping reads
RD_PROGRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_rvalid_re = '1')then
read_in_progress <= '0';
elsif(arvalid_re = '1')then
read_in_progress <= '1';
end if;
end if;
end process RD_PROGRESS;
-- Double register address in
REG_RADDR_TO_IPCLK : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => s_axi_lite_araddr,
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => araddr_d3
);
-- REG_RADDR_TO_IPCLK : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- if(ip2axi_aresetn = '0')then
-- araddr_d1_cdc_tig <= (others => '0');
-- araddr_d2 <= (others => '0');
-- araddr_d3 <= (others => '0');
-- else
-- araddr_d1_cdc_tig <= s_axi_lite_araddr;
-- araddr_d2 <= araddr_d1_cdc_tig;
-- araddr_d3 <= araddr_d2;
-- end if;
-- end if;
-- end process REG_RADDR_TO_IPCLK;
-- Latch and hold read address
REG_ARADDR_PROCESS : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
axi2ip_rdaddr_i <= (others => '0');
elsif(ip_arvalid_re = '1')then
axi2ip_rdaddr_i <= araddr_d3;
end if;
end if;
end process REG_ARADDR_PROCESS;
axi2ip_rdaddr <= axi2ip_rdaddr_i;
-- Register awready into IP clock domain. awready
-- is a 1 axi_lite clock delay of the rising edge of
-- arvalid. This provides a signal that asserts when
-- araddr is known to be stable.
REG_ARVALID_TO_IPCLK : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => arready_i,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => ip_arvalid_d2,
scndry_vect_out => open
);
REG_ARVALID_TO_IPCLK1 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
-- ip_arvalid_d1_cdc_tig <= '0';
-- ip_arvalid_d2 <= '0';
ip_arvalid_d3 <= '0';
else
-- ip_arvalid_d1_cdc_tig <= arready_i;
-- ip_arvalid_d2 <= ip_arvalid_d1_cdc_tig;
ip_arvalid_d3 <= ip_arvalid_d2;
end if;
end if;
end process REG_ARVALID_TO_IPCLK1;
ip_arvalid_re <= ip_arvalid_d2 and not ip_arvalid_d3;
-------------------------------------------------------------------------------
-- Generate Read CE's
-------------------------------------------------------------------------------
RDCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
rdce(j) <= ip_arvalid_re
when araddr_d3((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate RDCE_GEN;
-------------------------------------------------------------------------------
-- Register RDCE and RD Data out to IP
-------------------------------------------------------------------------------
REG_RDCNTRL_OUT : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
axi2ip_rdce <= (others => '0');
elsif(ip_arvalid_re = '1')then
axi2ip_rdce <= rdce;
else
axi2ip_rdce <= (others => '0');
end if;
end if;
end process REG_RDCNTRL_OUT;
-- Generate sample and hold pulse to capture read data from IP
REG_RVALID : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
rvalid <= '0';
else
rvalid <= ip_arvalid_re;
end if;
end if;
end process REG_RVALID;
-------------------------------------------------------------------------------
-- Sample and hold read data from IP
-------------------------------------------------------------------------------
S_H_READ_DATA : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
lite_rdata_cdc_from <= (others => '0');
-- If read cycle then assert rvalid and rdata out to target
elsif(rvalid = '1')then
lite_rdata_cdc_from <= ip2axi_rddata;
end if;
end if;
end process S_H_READ_DATA;
-- Cross read data to axi_lite clock domain
REG_DATA2LITE_CLOCK : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => ip2axi_aclk,
prmry_resetn => '0',
prmry_in => '0', --lite_rdata_cdc_from,
prmry_vect_in => lite_rdata_cdc_from,
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => open, --lite_rdata_d2,
scndry_vect_out => lite_rdata_d2
);
-- REG_DATA2LITE_CLOCK : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(s_axi_lite_aresetn = '0')then
-- lite_rdata_d1_cdc_to <= (others => '0');
-- lite_rdata_d2 <= (others => '0');
-- else
-- lite_rdata_d1_cdc_to <= lite_rdata_cdc_from;
-- lite_rdata_d2 <= lite_rdata_d1_cdc_to;
-- end if;
-- end if;
-- end process REG_DATA2LITE_CLOCK;
-- CR605883 (CDC) modified to remove
-- Because axi_lite_aclk must be less than or equal to ip2axi_aclk
-- then read data will appear a maximum 6 clocks from assertion
-- of arready.
REG_ALIGN_RDATA_LATCH : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arready_d1 <= '0';
arready_d2 <= '0';
arready_d3 <= '0';
arready_d4 <= '0';
arready_d5 <= '0';
arready_d6 <= '0';
arready_d7 <= '0';
arready_d8 <= '0';
arready_d9 <= '0';
arready_d10 <= '0';
arready_d11 <= '0';
arready_d12 <= '0';
else
arready_d1 <= arready_i;
arready_d2 <= arready_d1;
arready_d3 <= arready_d2;
arready_d4 <= arready_d3;
arready_d5 <= arready_d4;
arready_d6 <= arready_d5;
arready_d7 <= arready_d6;
arready_d8 <= arready_d7;
arready_d9 <= arready_d8;
arready_d10 <= arready_d9;
arready_d11 <= arready_d10;
arready_d12 <= arready_d11;
end if;
end if;
end process REG_ALIGN_RDATA_LATCH;
-------------------------------------------------------------------------------
-- Drive read data and read data valid out on capture of valid address.
-------------------------------------------------------------------------------
REG_RD_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If rvalid driving out to target and target indicates ready
-- then de-assert rvalid. (structure guarentees min 1 clock of rvalid)
elsif(s_axi_lite_rvalid_i = '1' and s_axi_lite_rready = '1')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If read cycle then assert rvalid and rdata out to target
-- CR605883
--elsif(s_pulse_re = '1')then
elsif(arready_d12 = '1')then
s_axi_lite_rdata <= lite_rdata_d2;
s_axi_lite_rvalid_i <= '1';
rst_rvalid_re <= '1'; -- CR576999
end if;
end if;
end process REG_RD_OUT;
end generate GEN_ASYNC_READ;
end implementation;
|
mit
|
mpvanveldhuizen/16-bit-risc
|
vhdl/inctwo.vhd
|
4
|
302
|
library ieee;
use ieee.std_logic_1164.all;
use work.lib.all;
entity inctwo is
port (DIN : in std_logic_vector(15 downto 0);
DOUT : out std_logic_vector(15 downto 0));
end inctwo;
architecture Logic of inctwo is
begin
ADD_COMP : add16 port map(DIN,"0000000000000010",DOUT);
end Logic;
|
mit
|
AlessandroSpallina/CalcolatoriElettronici
|
VHDL/04-03-14/04-03-14_TEST.vhd
|
2
|
1463
|
-- Copyright (C) 2016 by Spallina Ind.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity TEST is
end TEST;
architecture BEH of TEST is
component gianni is
port (
op : in std_logic_vector(1 downto 0);
din : in std_logic_vector(31 downto 0);
nw, clk : in std_logic;
res : out std_logic_vector(31 downto 0);
ready : out std_logic
);
end component;
signal op : std_logic_vector(1 downto 0);
signal din : std_logic_vector(31 downto 0);
signal nw, clk : std_logic;
signal res : std_logic_vector(31 downto 0);
signal ready : std_logic;
begin
DUT: gianni port map (op, din, nw, clk, res, ready);
process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process;
nw <= '1' after 1 ns, '0' after 11 ns,
'1' after 51 ns, '0' after 61 ns,
'1' after 101 ns, '0' after 111 ns,
'1' after 161 ns, '0' after 171 ns;
op <= "01" after 11 ns, -- OP "01" aka OR
"10" after 61 ns, -- OP "10" aka SLT
"00" after 111 ns, -- OP "00" aka ADD
"11" after 171 ns; -- OP "11" aka MUL
din <= conv_std_logic_vector(5, 32) after 11 ns, conv_std_logic_vector(3, 32) after 21 ns,
conv_std_logic_vector(2, 32) after 61 ns, conv_std_logic_vector(7, 32) after 71 ns,
conv_std_logic_vector(4, 32) after 111 ns, conv_std_logic_vector(9, 32) after 121 ns,
conv_std_logic_vector(1, 32) after 171 ns, conv_std_logic_vector(10, 32) after 181 ns;
end BEH;
|
mit
|
xiadz/oscilloscope
|
src/trace_pixgen.vhd
|
1
|
6938
|
----------------------------------------------------------------------------------
-- Author: Osowski Marcin
-- Create Date: 20:16:43 05/22/2011
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types.all;
entity trace_pixgen is
port (
nrst : in std_logic;
clk108 : in std_logic;
segment : in integer range 0 to 15;
segment_change : in std_logic;
subsegment : in integer range 0 to 3;
subsegment_change : in std_logic;
line : in integer range 0 to 15;
line_change : in std_logic;
column : in integer range 0 to 1279;
column_change : in std_logic;
page_change : in std_logic;
active_pixgen_source : in PIXGEN_SOURCE_T;
currently_read_screen_segment : in natural range 0 to 13;
currently_read_screen_column : in natural range 0 to 1279;
time_resolution : in integer range 0 to 15;
is_reading_active : in std_logic;
doutb : in std_logic_vector (8 downto 0);
addrb : out std_logic_vector (12 downto 0);
vout : out std_logic_vector (7 downto 0)
);
end trace_pixgen;
architecture behavioral of trace_pixgen is
signal position_div_3 : integer range 0 to 5973;
signal position_mod_3 : integer range 0 to 2;
signal delayed_active_pixgen_source : PIXGEN_SOURCE_T;
signal delayed_subsegment : integer range 0 to 3;
signal delayed_position_mod_3 : integer range 0 to 2;
signal delayed_line : integer range 0 to 15;
signal position_div_3_on_beginning_segment : integer range 0 to 5973;
signal position_mod_3_on_beginning_segment : integer range 0 to 2;
signal currently_inside_reading_zone : std_logic;
begin
-- Computing current position
process (nrst, clk108, position_mod_3, position_div_3) is
variable incremented_position_div_3 : integer range 0 to 5973;
variable incremented_position_mod_3 : integer range 0 to 2;
begin
if position_mod_3 = 2 then
incremented_position_div_3 := position_div_3 + 1;
incremented_position_mod_3 := 0;
else
incremented_position_div_3 := position_div_3;
incremented_position_mod_3 := position_mod_3 + 1;
end if;
if nrst = '0' then
position_div_3 <= 0;
position_mod_3 <= 0;
currently_inside_reading_zone <= '0';
elsif rising_edge (clk108) then
if currently_read_screen_segment = 0 and currently_read_screen_column = 0 then
currently_inside_reading_zone <= '0';
else
if time_resolution >= 10 or is_reading_active = '0' then
if segment = currently_read_screen_segment and
column - currently_read_screen_column < 6 and
column - currently_read_screen_column >= 0 then
currently_inside_reading_zone <= '1';
else
currently_inside_reading_zone <= '0';
end if;
elsif time_resolution >= 7 then
if segment = currently_read_screen_segment then
currently_inside_reading_zone <= '1';
else
currently_inside_reading_zone <= '0';
end if;
else
currently_inside_reading_zone <= '0';
end if;
end if;
if active_pixgen_source = TRACE_PIXGEN_T then
if page_change = '1' then
position_div_3 <= 0;
position_mod_3 <= 0;
position_div_3_on_beginning_segment <= 0;
position_mod_3_on_beginning_segment <= 0;
elsif segment_change = '1' then
position_div_3 <= incremented_position_div_3;
position_mod_3 <= incremented_position_mod_3;
position_div_3_on_beginning_segment <= incremented_position_div_3;
position_mod_3_on_beginning_segment <= incremented_position_mod_3;
elsif line_change = '1' then
position_div_3 <= position_div_3_on_beginning_segment;
position_mod_3 <= position_mod_3_on_beginning_segment;
else
position_div_3 <= incremented_position_div_3;
position_mod_3 <= incremented_position_mod_3;
end if;
end if;
end if;
end process;
addrb <= std_logic_vector (to_unsigned (position_div_3, 13));
delayed_active_pixgen_source <= active_pixgen_source when rising_edge (clk108);
delayed_subsegment <= subsegment when rising_edge (clk108);
delayed_position_mod_3 <= position_mod_3 when rising_edge (clk108);
delayed_line <= line when rising_edge (clk108);
process (nrst, delayed_active_pixgen_source, delayed_subsegment, delayed_position_mod_3, delayed_line, currently_inside_reading_zone) is
begin
if nrst = '0' or delayed_active_pixgen_source /= TRACE_PIXGEN_T then
vout <= "00000000";
else
if currently_inside_reading_zone = '1' then
vout <= "10010010";
elsif delayed_subsegment = 0 then
-- red
if delayed_line = 15 then
vout <= "11100000";
elsif doutb (3 * delayed_position_mod_3) = '1' then
vout <= "11100000";
else
vout <= "00000000";
end if;
elsif delayed_subsegment = 1 then
-- green
if delayed_line = 15 then
vout <= "00011100";
elsif doutb (3 * delayed_position_mod_3 + 1) = '1' then
vout <= "00011100";
else
vout <= "00000000";
end if;
elsif delayed_subsegment = 2 then
-- blue
if delayed_line = 15 then
vout <= "00000011";
elsif doutb (3 * delayed_position_mod_3 + 2) = '1' then
vout <= "00000011";
else
vout <= "00000000";
end if;
else
vout <= "00000000";
end if;
end if;
end process;
end behavioral;
|
mit
|
xiadz/oscilloscope
|
src/tests/test_types.vhd
|
1
|
741
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE work.types.all;
ENTITY test_types IS
END test_types;
ARCHITECTURE behavior OF test_types IS
signal tested_num : integer range 0 to 127;
signal tested_num2 : integer range 0 to 127;
signal tested_short_char : short_character;
BEGIN
stim_proc: process
begin
for i in 0 to 127 loop
tested_num <= i;
tested_short_char <= character_conv_table (i);
wait for 1 ns;
tested_num2 <= short_character'pos (tested_short_char);
wait for 1 ns;
assert tested_num = tested_num2;
assert tested_short_char = short_character'val (i);
end loop;
wait;
end process;
END;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
bin_Gaussian_Filter/ip/Gaussian_Filter/fp_arccospi_s5.vhd
|
10
|
713163
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_arccospi_s5
-- VHDL created on Thu Feb 28 17:21:22 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_arccospi_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_arccospi_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstBiasM2_uid6_fpArccosPiTest_q : std_logic_vector (7 downto 0);
signal ooPi_uid9_fpArccosPiTest_q : std_logic_vector (23 downto 0);
signal cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid20_acosX_uid8_fpArccosPiTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid22_acosX_uid8_fpArccosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid23_acosX_uid8_fpArccosPiTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwFMwShift_uid24_acosX_uid8_fpArccosPiTest_q : std_logic_vector (8 downto 0);
signal cstBiasP1_uid26_acosX_uid8_fpArccosPiTest_q : std_logic_vector (7 downto 0);
signal shiftOutVal_uid54_acosX_uid8_fpArccosPiTest_q : std_logic_vector (5 downto 0);
signal cst01pWShift_uid57_acosX_uid8_fpArccosPiTest_q : std_logic_vector (12 downto 0);
signal pi_uid94_acosX_uid8_fpArccosPiTest_q : std_logic_vector (27 downto 0);
signal path1NegCaseFrac_uid100_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0);
signal path1NegCaseFrac_uid100_acosX_uid8_fpArccosPiTest_q : std_logic_vector (22 downto 0);
signal pi2_uid111_acosX_uid8_fpArccosPiTest_q : std_logic_vector (26 downto 0);
signal fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q : std_logic_vector(1 downto 0);
signal InvExc_N_uid163_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid163_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid164_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid164_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid165_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid165_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal expSum_uid183_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(8 downto 0);
signal expSum_uid183_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(8 downto 0);
signal expSum_uid183_rAcosPi_uid13_fpArccosPiTest_o : std_logic_vector (8 downto 0);
signal expSum_uid183_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (8 downto 0);
signal biasInc_uid184_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (9 downto 0);
signal expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(11 downto 0);
signal expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(11 downto 0);
signal expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_o : std_logic_vector (11 downto 0);
signal expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (10 downto 0);
signal prod_uid186_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector (23 downto 0);
signal prod_uid186_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (23 downto 0);
signal prod_uid186_rAcosPi_uid13_fpArccosPiTest_s1 : std_logic_vector (47 downto 0);
signal prod_uid186_rAcosPi_uid13_fpArccosPiTest_pr : UNSIGNED (47 downto 0);
signal prod_uid186_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (47 downto 0);
signal roundBitDetectionConstant_uid201_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (2 downto 0);
signal excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0Idx1Pad16_uid246_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (15 downto 0);
signal rightShiftStage0Idx2Pad32_uid249_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0);
signal rightShiftStage0Idx3_uid251_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx1Pad4_uid255_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (3 downto 0);
signal rightShiftStage1Idx3Pad12_uid261_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (11 downto 0);
signal rightShiftStage2Idx2Pad2_uid269_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (1 downto 0);
signal rightShiftStage2Idx3Pad3_uid272_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (2 downto 0);
signal maxCountVal_uid320_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (5 downto 0);
signal vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0);
signal vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (5 downto 0);
signal expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid343_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid343_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0);
signal expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector (7 downto 0);
signal negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0Idx3_uid386_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3Pad6_uid396_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q : std_logic_vector (5 downto 0);
signal expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid460_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid460_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(8 downto 0);
signal expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(8 downto 0);
signal expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o : std_logic_vector (8 downto 0);
signal expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (8 downto 0);
signal expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(11 downto 0);
signal expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(11 downto 0);
signal expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o : std_logic_vector (11 downto 0);
signal expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (10 downto 0);
signal prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector (23 downto 0);
signal prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (23 downto 0);
signal prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s1 : std_logic_vector (47 downto 0);
signal prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_pr : UNSIGNED (47 downto 0);
signal prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (47 downto 0);
signal signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid519_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid519_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_b : std_logic_vector (20 downto 0);
signal prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_s1 : std_logic_vector (35 downto 0);
signal prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_pr : SIGNED (36 downto 0);
signal prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_q : std_logic_vector (35 downto 0);
signal prodXY_uid588_pT1_uid554_arccosXO2PolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid588_pT1_uid554_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid588_pT1_uid554_arccosXO2PolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid588_pT1_uid554_arccosXO2PolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid588_pT1_uid554_arccosXO2PolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid591_pT2_uid560_arccosXO2PolyEval_b : std_logic_vector (23 downto 0);
signal prodXY_uid591_pT2_uid560_arccosXO2PolyEval_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid591_pT2_uid560_arccosXO2PolyEval_pr : SIGNED (39 downto 0);
signal prodXY_uid591_pT2_uid560_arccosXO2PolyEval_q : std_logic_vector (38 downto 0);
signal prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_a : std_logic_vector (11 downto 0);
signal prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_pr : SIGNED (24 downto 0);
signal prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_q : std_logic_vector (23 downto 0);
signal prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_a : std_logic_vector (15 downto 0);
signal prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_b : std_logic_vector (22 downto 0);
signal prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_s1 : std_logic_vector (38 downto 0);
signal prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_pr : SIGNED (39 downto 0);
signal prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_q : std_logic_vector (38 downto 0);
signal memoryC0_uid406_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid406_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid406_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid406_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid406_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid406_arcsinXO2XTabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid407_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid407_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (18 downto 0);
signal memoryC1_uid407_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid407_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid407_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (18 downto 0);
signal memoryC1_uid407_arcsinXO2XTabGen_lutmem_q : std_logic_vector (18 downto 0);
signal memoryC2_uid408_arcsinXO2XTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid408_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid408_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid408_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid408_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid408_arcsinXO2XTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal memoryC0_uid550_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid550_arccosXO2TabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid550_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid550_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid550_arccosXO2TabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid550_arccosXO2TabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid551_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid551_arccosXO2TabGen_lutmem_ia : std_logic_vector (21 downto 0);
signal memoryC1_uid551_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid551_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid551_arccosXO2TabGen_lutmem_iq : std_logic_vector (21 downto 0);
signal memoryC1_uid551_arccosXO2TabGen_lutmem_q : std_logic_vector (21 downto 0);
signal memoryC2_uid552_arccosXO2TabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid552_arccosXO2TabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid552_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid552_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid552_arccosXO2TabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid552_arccosXO2TabGen_lutmem_q : std_logic_vector (11 downto 0);
signal memoryC0_uid566_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC0_uid566_sqrtTableGenerator_lutmem_ia : std_logic_vector (28 downto 0);
signal memoryC0_uid566_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid566_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid566_sqrtTableGenerator_lutmem_iq : std_logic_vector (28 downto 0);
signal memoryC0_uid566_sqrtTableGenerator_lutmem_q : std_logic_vector (28 downto 0);
signal memoryC1_uid567_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC1_uid567_sqrtTableGenerator_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid567_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid567_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid567_sqrtTableGenerator_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid567_sqrtTableGenerator_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid568_sqrtTableGenerator_lutmem_reset0 : std_logic;
signal memoryC2_uid568_sqrtTableGenerator_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid568_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid568_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid568_sqrtTableGenerator_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid568_sqrtTableGenerator_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excSelBits_uid137_acosX_uid8_fpArccosPiTest_0_to_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx1_uid256_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx2_uid259_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_4_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStage1Idx3_uid262_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_5_q : std_logic_vector (36 downto 0);
signal reg_rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_pad_o_uid27_uid63_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_0_q : std_logic_vector (35 downto 0);
signal reg_y_uid61_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (31 downto 0);
signal reg_l_uid65_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid282_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid289_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (3 downto 0);
signal reg_vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (34 downto 0);
signal reg_cStage_uid303_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (34 downto 0);
signal reg_vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (5 downto 0);
signal reg_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_0_to_fpL_uid70_acosX_uid8_fpArccosPiTest_0_q : std_logic_vector (22 downto 0);
signal reg_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (22 downto 0);
signal reg_fracSelIn_uid366_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_q : std_logic_vector (3 downto 0);
signal reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid568_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid569_sqrtPolynomialEvaluator_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid568_sqrtTableGenerator_lutmem_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_1_q : std_logic_vector (11 downto 0);
signal reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_q : std_logic_vector (15 downto 0);
signal reg_s1_uid571_uid574_sqrtPolynomialEvaluator_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_1_q : std_logic_vector (22 downto 0);
signal reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_q : std_logic_vector (7 downto 0);
signal reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx1_uid382_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx2_uid385_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx1_uid391_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx2_uid394_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage1Idx3_uid397_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_5_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid409_arcsinXO2XPolyEval_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid411_uid414_arcsinXO2XPolyEval_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_1_q : std_logic_vector (20 downto 0);
signal reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (22 downto 0);
signal reg_SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (22 downto 0);
signal reg_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_add_one_fracY_uid428_uid429_uid429_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (23 downto 0);
signal reg_expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (7 downto 0);
signal reg_expFracPreRound_uid483_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q : std_logic_vector (34 downto 0);
signal reg_roundBitAndNormalizationOp_uid485_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (11 downto 0);
signal reg_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (22 downto 0);
signal reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx1_uid526_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStage0Idx2_uid529_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_4_q : std_logic_vector (23 downto 0);
signal reg_rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_pad_fxpArcsinL_uid94_uid95_acosX_uid8_fpArccosPiTest_0_to_path1NegCase_uid95_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (26 downto 0);
signal reg_path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_0_to_path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid552_arccosXO2TabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid552_arccosXO2TabGen_lutmem_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid555_uid558_arccosXO2PolyEval_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_1_q : std_logic_vector (23 downto 0);
signal reg_pad_pi2_uid111_uid112_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_0_q : std_logic_vector (27 downto 0);
signal reg_fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (26 downto 0);
signal reg_Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (22 downto 0);
signal reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (22 downto 0);
signal reg_Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid140_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_add_one_fracX_uid147_uid148_uid148_rAcosPi_uid13_fpArccosPiTest_0_to_prod_uid186_rAcosPi_uid13_fpArccosPiTest_0_q : std_logic_vector (23 downto 0);
signal reg_expFracPreRound_uid204_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_0_q : std_logic_vector (34 downto 0);
signal reg_roundBitAndNormalizationOp_uid206_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_1_q : std_logic_vector (25 downto 0);
signal reg_expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_0_to_expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_1_q : std_logic_vector (11 downto 0);
signal reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_0_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_2_q : std_logic_vector (0 downto 0);
signal reg_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_0_to_excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_0_q : std_logic_vector (2 downto 0);
signal reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3_q : std_logic_vector (22 downto 0);
signal reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3_q : std_logic_vector (7 downto 0);
signal ld_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q_to_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (23 downto 0);
signal ld_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_c_q : std_logic_vector (31 downto 0);
signal ld_path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest_b_to_path2PosCaseFP_uid123_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path2ResFP_uid125_acosX_uid8_fpArccosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q_to_fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_b_q : std_logic_vector (1 downto 0);
signal ld_expX_uid143_rAcosPi_uid13_fpArccosPiTest_b_to_expSum_uid183_rAcosPi_uid13_fpArccosPiTest_a_q : std_logic_vector (7 downto 0);
signal ld_expSum_uid183_rAcosPi_uid13_fpArccosPiTest_q_to_expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_a_q : std_logic_vector (8 downto 0);
signal ld_signX_uid145_rAcosPi_uid13_fpArccosPiTest_b_to_signR_uid211_rAcosPi_uid13_fpArccosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_q_to_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_2_q_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_1_q_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_q_to_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3_q_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_d_q : std_logic_vector (22 downto 0);
signal ld_signR_uid211_rAcosPi_uid13_fpArccosPiTest_q_to_signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_q_to_R_uid242_rAcosPi_uid13_fpArccosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_c_q : std_logic_vector (5 downto 0);
signal ld_expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (22 downto 0);
signal ld_InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_join_uid365_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q : std_logic_vector (1 downto 0);
signal ld_negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (8 downto 0);
signal ld_reg_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d_q : std_logic_vector (22 downto 0);
signal ld_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid567_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid567_sqrtTableGenerator_lutmem_a_q : std_logic_vector (7 downto 0);
signal ld_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_b_to_reg_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_0_to_fpL_uid70_acosX_uid8_fpArccosPiTest_0_a_q : std_logic_vector (22 downto 0);
signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_to_reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_a_q : std_logic_vector (7 downto 0);
signal ld_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_to_reg_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_yT1_uid553_arccosXO2PolyEval_b_to_reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_a_q : std_logic_vector (11 downto 0);
signal ld_mAddr_uid107_acosX_uid8_fpArccosPiTest_b_to_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_q_to_reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_2_a_q : std_logic_vector (0 downto 0);
signal ld_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_b_to_reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3_a_q : std_logic_vector (7 downto 0);
signal ld_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q_to_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_a_inputreg_q : std_logic_vector (23 downto 0);
signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_sticky_ena_q : signal is true;
signal ld_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_c_inputreg_q : std_logic_vector (31 downto 0);
signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_reset0 : std_logic;
signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_eq : std_logic;
signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_sticky_ena_q : signal is true;
signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_reset0 : std_logic;
signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_sticky_ena_q : signal is true;
signal ld_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_sticky_ena_q : signal is true;
signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_eq : std_logic;
signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q : signal is true;
signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_reset0 : std_logic;
signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ia : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_iq : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_q : std_logic_vector (23 downto 0);
signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q : signal is true;
signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_reset0 : std_logic;
signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_sticky_ena_q : signal is true;
signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_sticky_ena_q : signal is true;
signal ld_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid567_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid567_sqrtTableGenerator_lutmem_a_outputreg_q : std_logic_vector (7 downto 0);
signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_inputreg_q : std_logic_vector (15 downto 0);
signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 : std_logic;
signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_ia : std_logic_vector (15 downto 0);
signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_iq : std_logic_vector (15 downto 0);
signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_q : std_logic_vector (15 downto 0);
signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_sticky_ena_q : signal is true;
signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid553_arccosXO2PolyEval_b_to_reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_a_inputreg_q : std_logic_vector (11 downto 0);
signal ld_mAddr_uid107_acosX_uid8_fpArccosPiTest_b_to_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_reset0 : std_logic;
signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_eq : std_logic;
signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q : signal is true;
signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_reset0 : std_logic;
signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q : signal is true;
signal pad_o_uid27_uid63_acosX_uid8_fpArccosPiTest_q : std_logic_vector (35 downto 0);
signal pad_pi2_uid111_uid112_acosX_uid8_fpArccosPiTest_q : std_logic_vector (27 downto 0);
signal expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(14 downto 0);
signal expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(14 downto 0);
signal expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_o : std_logic_vector (14 downto 0);
signal expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_cin : std_logic_vector (0 downto 0);
signal expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_n : std_logic_vector (0 downto 0);
signal expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(14 downto 0);
signal expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(14 downto 0);
signal expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_o : std_logic_vector (14 downto 0);
signal expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_cin : std_logic_vector (0 downto 0);
signal expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_n : std_logic_vector (0 downto 0);
signal vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a : std_logic_vector(8 downto 0);
signal vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector(8 downto 0);
signal vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_o : std_logic_vector (8 downto 0);
signal vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_cin : std_logic_vector (0 downto 0);
signal vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_c : std_logic_vector (0 downto 0);
signal expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(14 downto 0);
signal expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(14 downto 0);
signal expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o : std_logic_vector (14 downto 0);
signal expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_cin : std_logic_vector (0 downto 0);
signal expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_n : std_logic_vector (0 downto 0);
signal expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(14 downto 0);
signal expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(14 downto 0);
signal expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o : std_logic_vector (14 downto 0);
signal expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_cin : std_logic_vector (0 downto 0);
signal expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_n : std_logic_vector (0 downto 0);
signal path2PosCaseFP_uid123_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0);
signal excSelBits_uid137_acosX_uid8_fpArccosPiTest_q : std_logic_vector (2 downto 0);
signal InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal expX_uid15_acosX_uid8_fpArccosPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid15_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid16_acosX_uid8_fpArccosPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid16_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0);
signal singX_uid17_acosX_uid8_fpArccosPiTest_in : std_logic_vector (31 downto 0);
signal singX_uid17_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid33_acosX_uid8_fpArccosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid33_acosX_uid8_fpArccosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid33_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid35_acosX_uid8_fpArccosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid35_acosX_uid8_fpArccosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid35_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid37_acosX_uid8_fpArccosPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid37_acosX_uid8_fpArccosPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid37_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid38_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid38_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid38_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal expGT0_uid45_acosX_uid8_fpArccosPiTest_a : std_logic_vector(10 downto 0);
signal expGT0_uid45_acosX_uid8_fpArccosPiTest_b : std_logic_vector(10 downto 0);
signal expGT0_uid45_acosX_uid8_fpArccosPiTest_o : std_logic_vector (10 downto 0);
signal expGT0_uid45_acosX_uid8_fpArccosPiTest_cin : std_logic_vector (0 downto 0);
signal expGT0_uid45_acosX_uid8_fpArccosPiTest_c : std_logic_vector (0 downto 0);
signal expEQ0_uid46_acosX_uid8_fpArccosPiTest_a : std_logic_vector(7 downto 0);
signal expEQ0_uid46_acosX_uid8_fpArccosPiTest_b : std_logic_vector(7 downto 0);
signal expEQ0_uid46_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid47_acosX_uid8_fpArccosPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid47_acosX_uid8_fpArccosPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid47_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal shiftValue_uid52_acosX_uid8_fpArccosPiTest_a : std_logic_vector(11 downto 0);
signal shiftValue_uid52_acosX_uid8_fpArccosPiTest_b : std_logic_vector(11 downto 0);
signal shiftValue_uid52_acosX_uid8_fpArccosPiTest_o : std_logic_vector (11 downto 0);
signal shiftValue_uid52_acosX_uid8_fpArccosPiTest_cin : std_logic_vector (0 downto 0);
signal shiftValue_uid52_acosX_uid8_fpArccosPiTest_n : std_logic_vector (0 downto 0);
signal shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_a : std_logic_vector(8 downto 0);
signal shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_b : std_logic_vector(8 downto 0);
signal shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_o : std_logic_vector (8 downto 0);
signal shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_q : std_logic_vector (8 downto 0);
signal oMy_uid63_acosX_uid8_fpArccosPiTest_a : std_logic_vector(36 downto 0);
signal oMy_uid63_acosX_uid8_fpArccosPiTest_b : std_logic_vector(36 downto 0);
signal oMy_uid63_acosX_uid8_fpArccosPiTest_o : std_logic_vector (36 downto 0);
signal oMy_uid63_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0);
signal expL_uid67_acosX_uid8_fpArccosPiTest_a : std_logic_vector(8 downto 0);
signal expL_uid67_acosX_uid8_fpArccosPiTest_b : std_logic_vector(8 downto 0);
signal expL_uid67_acosX_uid8_fpArccosPiTest_o : std_logic_vector (8 downto 0);
signal expL_uid67_acosX_uid8_fpArccosPiTest_q : std_logic_vector (8 downto 0);
signal srVal_uid76_acosX_uid8_fpArccosPiTest_a : std_logic_vector(8 downto 0);
signal srVal_uid76_acosX_uid8_fpArccosPiTest_b : std_logic_vector(8 downto 0);
signal srVal_uid76_acosX_uid8_fpArccosPiTest_o : std_logic_vector (8 downto 0);
signal srVal_uid76_acosX_uid8_fpArccosPiTest_q : std_logic_vector (8 downto 0);
signal path1NegCase_uid95_acosX_uid8_fpArccosPiTest_a : std_logic_vector(28 downto 0);
signal path1NegCase_uid95_acosX_uid8_fpArccosPiTest_b : std_logic_vector(28 downto 0);
signal path1NegCase_uid95_acosX_uid8_fpArccosPiTest_o : std_logic_vector (28 downto 0);
signal path1NegCase_uid95_acosX_uid8_fpArccosPiTest_q : std_logic_vector (28 downto 0);
signal path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_a : std_logic_vector(8 downto 0);
signal path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_b : std_logic_vector(8 downto 0);
signal path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_o : std_logic_vector (8 downto 0);
signal path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_q : std_logic_vector (8 downto 0);
signal path2Diff_uid112_acosX_uid8_fpArccosPiTest_a : std_logic_vector(28 downto 0);
signal path2Diff_uid112_acosX_uid8_fpArccosPiTest_b : std_logic_vector(28 downto 0);
signal path2Diff_uid112_acosX_uid8_fpArccosPiTest_o : std_logic_vector (28 downto 0);
signal path2Diff_uid112_acosX_uid8_fpArccosPiTest_q : std_logic_vector (28 downto 0);
signal expRCalc_uid134_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0);
signal expRCalc_uid134_acosX_uid8_fpArccosPiTest_q : std_logic_vector (7 downto 0);
signal outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q : std_logic_vector(1 downto 0);
signal expRPostExc_uid140_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid140_acosX_uid8_fpArccosPiTest_q : std_logic_vector (7 downto 0);
signal exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_o : std_logic_vector (36 downto 0);
signal expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (35 downto 0);
signal excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_c : std_logic_vector(0 downto 0);
signal excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_c : std_logic_vector(0 downto 0);
signal excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_d : std_logic_vector(0 downto 0);
signal excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_c : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_c : std_logic_vector(0 downto 0);
signal excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_d : std_logic_vector(0 downto 0);
signal excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid227_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid227_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid227_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0);
signal vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0);
signal vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0);
signal vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0);
signal fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(8 downto 0);
signal expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(8 downto 0);
signal expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_o : std_logic_vector (8 downto 0);
signal expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector (8 downto 0);
signal expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(8 downto 0);
signal expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(8 downto 0);
signal expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_o : std_logic_vector (8 downto 0);
signal expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector (8 downto 0);
signal inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal minInf_uid363_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal minInf_uid363_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal minInf_uid363_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(1 downto 0);
signal expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0);
signal expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(36 downto 0);
signal expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o : std_logic_vector (36 downto 0);
signal expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (35 downto 0);
signal excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c : std_logic_vector(0 downto 0);
signal excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c : std_logic_vector(0 downto 0);
signal excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d : std_logic_vector(0 downto 0);
signal excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c : std_logic_vector(0 downto 0);
signal ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c : std_logic_vector(0 downto 0);
signal excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d : std_logic_vector(0 downto 0);
signal excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid505_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid505_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYI_uid505_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid506_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid506_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal ZeroTimesInf_uid506_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(1 downto 0);
signal fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (22 downto 0);
signal expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (7 downto 0);
signal signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0);
signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_enaAnd_q : std_logic_vector(0 downto 0);
signal fracOOPi_uid10_fpArccosPiTest_in : std_logic_vector (22 downto 0);
signal fracOOPi_uid10_fpArccosPiTest_b : std_logic_vector (22 downto 0);
signal piF_uid128_acosX_uid8_fpArccosPiTest_in : std_logic_vector (26 downto 0);
signal piF_uid128_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0);
signal fracRCalc_uid131_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0);
signal fracRCalc_uid131_acosX_uid8_fpArccosPiTest_q : std_logic_vector (22 downto 0);
signal normalizeBit_uid187_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (47 downto 0);
signal normalizeBit_uid187_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (0 downto 0);
signal fracRPostNormHigh_uid189_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (46 downto 0);
signal fracRPostNormHigh_uid189_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (23 downto 0);
signal fracRPostNormLow_uid190_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (45 downto 0);
signal fracRPostNormLow_uid190_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (23 downto 0);
signal stickyRange_uid192_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (21 downto 0);
signal stickyRange_uid192_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (21 downto 0);
signal Prod22_uid193_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (22 downto 0);
signal Prod22_uid193_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (0 downto 0);
signal normalizeBit_uid466_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (47 downto 0);
signal normalizeBit_uid466_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0);
signal fracRPostNormHigh_uid468_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (46 downto 0);
signal fracRPostNormHigh_uid468_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (23 downto 0);
signal fracRPostNormLow_uid469_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (45 downto 0);
signal fracRPostNormLow_uid469_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (23 downto 0);
signal stickyRange_uid471_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (21 downto 0);
signal stickyRange_uid471_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (21 downto 0);
signal Prod22_uid472_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (22 downto 0);
signal Prod22_uid472_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0);
signal prodXYTruncFR_uid583_pT1_uid410_arcsinXO2XPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid583_pT1_uid410_arcsinXO2XPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid586_pT2_uid416_arcsinXO2XPolyEval_in : std_logic_vector (35 downto 0);
signal prodXYTruncFR_uid586_pT2_uid416_arcsinXO2XPolyEval_b : std_logic_vector (21 downto 0);
signal prodXYTruncFR_uid589_pT1_uid554_arccosXO2PolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid589_pT1_uid554_arccosXO2PolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid592_pT2_uid560_arccosXO2PolyEval_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid592_pT2_uid560_arccosXO2PolyEval_b : std_logic_vector (24 downto 0);
signal prodXYTruncFR_uid595_pT1_uid570_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid595_pT1_uid570_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid598_pT2_uid576_sqrtPolynomialEvaluator_in : std_logic_vector (38 downto 0);
signal prodXYTruncFR_uid598_pT2_uid576_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0);
signal sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_in : std_logic_vector (15 downto 0);
signal sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b : std_logic_vector (14 downto 0);
signal fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_q : std_logic_vector (22 downto 0);
signal concExc_uid229_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (2 downto 0);
signal R_uid242_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (31 downto 0);
signal FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in : std_logic_vector (15 downto 0);
signal FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector (15 downto 0);
signal concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (2 downto 0);
signal R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0);
signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_nor_a : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_nor_b : std_logic_vector(0 downto 0);
signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_nor_q : std_logic_vector(0 downto 0);
signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_nor_a : std_logic_vector(0 downto 0);
signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_nor_b : std_logic_vector(0 downto 0);
signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_nor_q : std_logic_vector(0 downto 0);
signal oFracX_uid51_uid51_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0);
signal InvExpXIsZero_uid43_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid43_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid39_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid39_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid42_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid42_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid48_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid48_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid55_acosX_uid8_fpArccosPiTest_in : std_logic_vector (5 downto 0);
signal fxpShifterBits_uid55_acosX_uid8_fpArccosPiTest_b : std_logic_vector (5 downto 0);
signal l_uid65_acosX_uid8_fpArccosPiTest_in : std_logic_vector (34 downto 0);
signal l_uid65_acosX_uid8_fpArccosPiTest_b : std_logic_vector (34 downto 0);
signal expLRange_uid69_acosX_uid8_fpArccosPiTest_in : std_logic_vector (7 downto 0);
signal expLRange_uid69_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0);
signal srValRange_uid77_acosX_uid8_fpArccosPiTest_in : std_logic_vector (4 downto 0);
signal srValRange_uid77_acosX_uid8_fpArccosPiTest_b : std_logic_vector (4 downto 0);
signal path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_in : std_logic_vector (27 downto 0);
signal path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0);
signal path1NegCaseFracHigh_uid98_acosX_uid8_fpArccosPiTest_in : std_logic_vector (26 downto 0);
signal path1NegCaseFracHigh_uid98_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0);
signal path1NegCaseFracLow_uid99_acosX_uid8_fpArccosPiTest_in : std_logic_vector (25 downto 0);
signal path1NegCaseFracLow_uid99_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0);
signal path1NegCaseExpRange_uid102_acosX_uid8_fpArccosPiTest_in : std_logic_vector (7 downto 0);
signal path1NegCaseExpRange_uid102_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0);
signal normBit_uid114_acosX_uid8_fpArccosPiTest_in : std_logic_vector (27 downto 0);
signal normBit_uid114_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0);
signal path2NegCaseFPFrac_uid115_acosX_uid8_fpArccosPiTest_in : std_logic_vector (26 downto 0);
signal path2NegCaseFPFrac_uid115_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0);
signal path2NegCaseFPFrac_uid118_acosX_uid8_fpArccosPiTest_in : std_logic_vector (25 downto 0);
signal path2NegCaseFPFrac_uid118_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0);
signal sR_uid141_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0);
signal fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (23 downto 0);
signal fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (22 downto 0);
signal expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (35 downto 0);
signal expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (11 downto 0);
signal InvExcRNaN_uid240_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal InvExcRNaN_uid240_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage136dto1_uid265_fxpX_uid59_acosX_uid8_fpArccosPiTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto1_uid265_fxpX_uid59_acosX_uid8_fpArccosPiTest_b : std_logic_vector (35 downto 0);
signal RightShiftStage136dto2_uid268_fxpX_uid59_acosX_uid8_fpArccosPiTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto2_uid268_fxpX_uid59_acosX_uid8_fpArccosPiTest_b : std_logic_vector (34 downto 0);
signal RightShiftStage136dto3_uid271_fxpX_uid59_acosX_uid8_fpArccosPiTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage136dto3_uid271_fxpX_uid59_acosX_uid8_fpArccosPiTest_b : std_logic_vector (33 downto 0);
signal rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid288_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (18 downto 0);
signal vStage_uid288_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (18 downto 0);
signal rVStage_uid292_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid292_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid295_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (26 downto 0);
signal vStage_uid295_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (26 downto 0);
signal rVStage_uid306_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid306_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid309_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (32 downto 0);
signal vStage_uid309_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (32 downto 0);
signal InvFracXIsZero_uid339_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid339_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid342_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid342_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal expREven_uid347_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in : std_logic_vector (8 downto 0);
signal expREven_uid347_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0);
signal expROdd_uid350_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in : std_logic_vector (8 downto 0);
signal expROdd_uid350_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0);
signal RightShiftStage123dto1_uid400_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage123dto1_uid400_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0);
signal InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid440_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid440_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid443_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid443_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid456_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid456_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid459_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid459_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0);
signal fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0);
signal expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (35 downto 0);
signal expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (11 downto 0);
signal RightShiftStage023dto2_uid533_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto2_uid533_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b : std_logic_vector (21 downto 0);
signal RightShiftStage023dto4_uid536_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto4_uid536_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b : std_logic_vector (19 downto 0);
signal RightShiftStage023dto6_uid539_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto6_uid539_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b : std_logic_vector (17 downto 0);
signal fpOOPi_uid11_fpArccosPiTest_q : std_logic_vector (31 downto 0);
signal fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (23 downto 0);
signal extraStickyBit_uid194_rAcosPi_uid13_fpArccosPiTest_s : std_logic_vector (0 downto 0);
signal extraStickyBit_uid194_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (0 downto 0);
signal stickyExtendedRange_uid195_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (22 downto 0);
signal fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0);
signal extraStickyBit_uid473_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0);
signal extraStickyBit_uid473_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (0 downto 0);
signal stickyExtendedRange_uid474_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (22 downto 0);
signal lowRangeB_uid411_arcsinXO2XPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid411_arcsinXO2XPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid412_arcsinXO2XPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid412_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid417_arcsinXO2XPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid417_arcsinXO2XPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid418_arcsinXO2XPolyEval_in : std_logic_vector (21 downto 0);
signal highBBits_uid418_arcsinXO2XPolyEval_b : std_logic_vector (19 downto 0);
signal lowRangeB_uid555_arccosXO2PolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid555_arccosXO2PolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid556_arccosXO2PolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid556_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid561_arccosXO2PolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid561_arccosXO2PolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid562_arccosXO2PolyEval_in : std_logic_vector (24 downto 0);
signal highBBits_uid562_arccosXO2PolyEval_b : std_logic_vector (22 downto 0);
signal lowRangeB_uid571_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid571_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0);
signal highBBits_uid572_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0);
signal highBBits_uid572_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid577_sqrtPolynomialEvaluator_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid577_sqrtPolynomialEvaluator_b : std_logic_vector (1 downto 0);
signal highBBits_uid578_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0);
signal highBBits_uid578_sqrtPolynomialEvaluator_b : std_logic_vector (21 downto 0);
signal yT1_uid409_arcsinXO2XPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid409_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0);
signal yT1_uid569_sqrtPolynomialEvaluator_in : std_logic_vector (15 downto 0);
signal yT1_uid569_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0);
signal ArcsinL22dto0_uid88_acosX_uid8_fpArccosPiTest_in : std_logic_vector (22 downto 0);
signal ArcsinL22dto0_uid88_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0);
signal ArcsinL30dto23_uid90_acosX_uid8_fpArccosPiTest_in : std_logic_vector (30 downto 0);
signal ArcsinL30dto23_uid90_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0);
signal oFracXExt_uid58_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0);
signal exc_N_uid40_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid40_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid40_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid49_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid49_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal expXZFracNotZero_uid49_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal shiftValue_uid56_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0);
signal shiftValue_uid56_acosX_uid8_fpArccosPiTest_q : std_logic_vector (5 downto 0);
signal rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid281_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (2 downto 0);
signal vStage_uid281_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (2 downto 0);
signal fpL_uid70_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0);
signal rightShiftStageSel4Dto3_uid387_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid387_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0);
signal path1NegCaseUR_uid103_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFPL_uid116_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFPS_uid119_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0);
signal expX_uid143_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid143_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (7 downto 0);
signal signX_uid145_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid145_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (0 downto 0);
signal fracX_uid147_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid147_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (22 downto 0);
signal expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (7 downto 0);
signal expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (7 downto 0);
signal rightShiftStage2Idx1_uid267_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage2Idx2_uid270_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage2Idx3_uid273_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0);
signal cStage_uid289_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0);
signal vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal cStage_uid296_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0);
signal vCount_uid307_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid307_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid307_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal cStage_uid310_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0);
signal exc_N_uid340_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid340_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid340_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1_uid402_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0);
signal exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid457_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid457_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid457_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (7 downto 0);
signal expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1_uid535_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx2_uid538_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3_uid541_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0);
signal expY_uid144_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (30 downto 0);
signal expY_uid144_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (7 downto 0);
signal signY_uid146_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (31 downto 0);
signal signY_uid146_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (0 downto 0);
signal fracY_uid149_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (22 downto 0);
signal fracY_uid149_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (22 downto 0);
signal FracRPostNorm1dto0_uid199_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (1 downto 0);
signal FracRPostNorm1dto0_uid199_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (1 downto 0);
signal expFracPreRound_uid204_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (34 downto 0);
signal stickyRangeComparator_uid197_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid197_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid197_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal FracRPostNorm1dto0_uid478_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (1 downto 0);
signal FracRPostNorm1dto0_uid478_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (1 downto 0);
signal expFracPreRound_uid483_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0);
signal stickyRangeComparator_uid476_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid476_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(22 downto 0);
signal stickyRangeComparator_uid476_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid413_arcsinXO2XPolyEval_a : std_logic_vector(19 downto 0);
signal sumAHighB_uid413_arcsinXO2XPolyEval_b : std_logic_vector(19 downto 0);
signal sumAHighB_uid413_arcsinXO2XPolyEval_o : std_logic_vector (19 downto 0);
signal sumAHighB_uid413_arcsinXO2XPolyEval_q : std_logic_vector (19 downto 0);
signal sumAHighB_uid419_arcsinXO2XPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid419_arcsinXO2XPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid419_arcsinXO2XPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid419_arcsinXO2XPolyEval_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid557_arccosXO2PolyEval_a : std_logic_vector(22 downto 0);
signal sumAHighB_uid557_arccosXO2PolyEval_b : std_logic_vector(22 downto 0);
signal sumAHighB_uid557_arccosXO2PolyEval_o : std_logic_vector (22 downto 0);
signal sumAHighB_uid557_arccosXO2PolyEval_q : std_logic_vector (22 downto 0);
signal sumAHighB_uid563_arccosXO2PolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid563_arccosXO2PolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid563_arccosXO2PolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid563_arccosXO2PolyEval_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid573_sqrtPolynomialEvaluator_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid573_sqrtPolynomialEvaluator_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid573_sqrtPolynomialEvaluator_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid573_sqrtPolynomialEvaluator_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid579_sqrtPolynomialEvaluator_a : std_logic_vector(29 downto 0);
signal sumAHighB_uid579_sqrtPolynomialEvaluator_b : std_logic_vector(29 downto 0);
signal sumAHighB_uid579_sqrtPolynomialEvaluator_o : std_logic_vector (29 downto 0);
signal sumAHighB_uid579_sqrtPolynomialEvaluator_q : std_logic_vector (29 downto 0);
signal oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0);
signal srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_a : std_logic_vector(8 downto 0);
signal srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_b : std_logic_vector(8 downto 0);
signal srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_o : std_logic_vector (8 downto 0);
signal srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_q : std_logic_vector (8 downto 0);
signal X36dto16_uid245_fxpX_uid59_acosX_uid8_fpArccosPiTest_in : std_logic_vector (36 downto 0);
signal X36dto16_uid245_fxpX_uid59_acosX_uid8_fpArccosPiTest_b : std_logic_vector (20 downto 0);
signal X36dto32_uid248_fxpX_uid59_acosX_uid8_fpArccosPiTest_in : std_logic_vector (36 downto 0);
signal X36dto32_uid248_fxpX_uid59_acosX_uid8_fpArccosPiTest_b : std_logic_vector (4 downto 0);
signal InvExc_N_uid41_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid41_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid50_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid50_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal inputOutOfRange_uid50_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal rightShiftStageSel5Dto4_uid252_fxpX_uid59_acosX_uid8_fpArccosPiTest_in : std_logic_vector (5 downto 0);
signal rightShiftStageSel5Dto4_uid252_fxpX_uid59_acosX_uid8_fpArccosPiTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_in : std_logic_vector (3 downto 0);
signal rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_in : std_logic_vector (1 downto 0);
signal rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_b : std_logic_vector (1 downto 0);
signal cStage_uid282_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0);
signal expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in : std_logic_vector (30 downto 0);
signal expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0);
signal fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in : std_logic_vector (22 downto 0);
signal fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0);
signal signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0);
signal rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0);
signal path1ResFP_uid105_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0);
signal path1ResFP_uid105_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0);
signal path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0);
signal path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0);
signal expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid157_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid157_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid157_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal add_one_fracX_uid147_uid148_uid148_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (23 downto 0);
signal fracXIsZero_uid159_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid159_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid159_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0);
signal vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0);
signal vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0);
signal InvExc_N_uid341_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid341_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0);
signal InvExc_N_uid458_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid458_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0);
signal expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid173_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid173_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid173_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal signR_uid211_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid211_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid211_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal add_one_fracY_uid149_uid150_uid150_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (23 downto 0);
signal fracXIsZero_uid175_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid175_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid175_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal sticky_uid198_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal sticky_uid198_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal sticky_uid477_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal sticky_uid477_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal s1_uid411_uid414_arcsinXO2XPolyEval_q : std_logic_vector (20 downto 0);
signal s2_uid417_uid420_arcsinXO2XPolyEval_q : std_logic_vector (32 downto 0);
signal s1_uid555_uid558_arccosXO2PolyEval_q : std_logic_vector (23 downto 0);
signal s2_uid561_uid564_arccosXO2PolyEval_q : std_logic_vector (32 downto 0);
signal s1_uid571_uid574_sqrtPolynomialEvaluator_q : std_logic_vector (22 downto 0);
signal s2_uid577_uid580_sqrtPolynomialEvaluator_q : std_logic_vector (31 downto 0);
signal X23dto8_uid524_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0);
signal X23dto8_uid524_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b : std_logic_vector (15 downto 0);
signal X23dto16_uid527_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0);
signal X23dto16_uid527_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0);
signal srValArcsinLRange_uid92_acosX_uid8_fpArccosPiTest_in : std_logic_vector (4 downto 0);
signal srValArcsinLRange_uid92_acosX_uid8_fpArccosPiTest_b : std_logic_vector (4 downto 0);
signal rightShiftStage0Idx1_uid247_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage0Idx2_uid250_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0);
signal exc_R_uid44_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid44_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid44_acosX_uid8_fpArccosPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid44_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid135_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid135_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal xRegAndOutOfRange_uid135_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0);
signal rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0);
signal expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal expX0_uid351_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in : std_logic_vector (0 downto 0);
signal expX0_uid351_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0);
signal fracXAddr_uid355_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in : std_logic_vector (22 downto 0);
signal fracXAddr_uid355_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector (6 downto 0);
signal InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage023dto2_uid389_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto2_uid389_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b : std_logic_vector (21 downto 0);
signal RightShiftStage023dto4_uid392_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto4_uid392_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b : std_logic_vector (19 downto 0);
signal RightShiftStage023dto6_uid395_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage023dto6_uid395_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b : std_logic_vector (17 downto 0);
signal Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_in : std_logic_vector (22 downto 0);
signal Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0);
signal Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_in : std_logic_vector (30 downto 0);
signal Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0);
signal path2ResFP_uid125_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0);
signal path2ResFP_uid125_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0);
signal exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid161_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid161_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal inputIsMax_uid60_acosX_uid8_fpArccosPiTest_in : std_logic_vector (36 downto 0);
signal inputIsMax_uid60_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0);
signal y_uid61_acosX_uid8_fpArccosPiTest_in : std_logic_vector (35 downto 0);
signal y_uid61_acosX_uid8_fpArccosPiTest_b : std_logic_vector (34 downto 0);
signal rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid302_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (30 downto 0);
signal vStage_uid302_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (30 downto 0);
signal rVStage_uid313_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (34 downto 0);
signal rVStage_uid313_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0);
signal vStage_uid316_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (33 downto 0);
signal vStage_uid316_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (33 downto 0);
signal exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal sAddr_uid80_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0);
signal sAddr_uid80_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0);
signal exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage123dto1_uid544_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0);
signal RightShiftStage123dto1_uid544_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0);
signal InvExpXIsZero_uid181_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid181_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid177_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid177_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal lrs_uid200_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (2 downto 0);
signal lrs_uid479_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (2 downto 0);
signal fxpArcSinXO2XRes_uid83_acosX_uid8_fpArccosPiTest_in : std_logic_vector (30 downto 0);
signal fxpArcSinXO2XRes_uid83_acosX_uid8_fpArccosPiTest_b : std_logic_vector (25 downto 0);
signal fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_in : std_logic_vector (30 downto 0);
signal fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_b : std_logic_vector (26 downto 0);
signal fracR_uid359_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in : std_logic_vector (28 downto 0);
signal fracR_uid359_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0);
signal rightShiftStage0Idx1_uid526_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0Idx2_uid529_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0);
signal rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in : std_logic_vector (4 downto 0);
signal rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in : std_logic_vector (2 downto 0);
signal rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b : std_logic_vector (1 downto 0);
signal rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in : std_logic_vector (0 downto 0);
signal rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0);
signal excRNaN_uid136_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid136_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid136_acosX_uid8_fpArccosPiTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid136_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal RightShiftStage036dto4_uid254_fxpX_uid59_acosX_uid8_fpArccosPiTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto4_uid254_fxpX_uid59_acosX_uid8_fpArccosPiTest_b : std_logic_vector (32 downto 0);
signal RightShiftStage036dto8_uid257_fxpX_uid59_acosX_uid8_fpArccosPiTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto8_uid257_fxpX_uid59_acosX_uid8_fpArccosPiTest_b : std_logic_vector (28 downto 0);
signal RightShiftStage036dto12_uid260_fxpX_uid59_acosX_uid8_fpArccosPiTest_in : std_logic_vector (36 downto 0);
signal RightShiftStage036dto12_uid260_fxpX_uid59_acosX_uid8_fpArccosPiTest_b : std_logic_vector (24 downto 0);
signal expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector (7 downto 0);
signal rightShiftStage1Idx1_uid391_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx2_uid394_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage1Idx3_uid397_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0);
signal Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_in : std_logic_vector (22 downto 0);
signal Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0);
signal Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_in : std_logic_vector (30 downto 0);
signal Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0);
signal exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal firstPath_uid62_acosX_uid8_fpArccosPiTest_in : std_logic_vector (34 downto 0);
signal firstPath_uid62_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0);
signal mAddr_uid107_acosX_uid8_fpArccosPiTest_in : std_logic_vector (34 downto 0);
signal mAddr_uid107_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0);
signal mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_in : std_logic_vector (26 downto 0);
signal mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_b : std_logic_vector (14 downto 0);
signal cStage_uid303_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0);
signal vCount_uid314_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid314_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid314_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal cStage_uid317_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0);
signal minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2Idx1_uid546_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0);
signal InvExc_I_uid180_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid180_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal roundBitDetectionPattern_uid202_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid202_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid202_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal roundBitDetectionPattern_uid481_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid481_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(2 downto 0);
signal roundBitDetectionPattern_uid481_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal fxpArcsinXO2XResWFRange_uid84_acosX_uid8_fpArccosPiTest_in : std_logic_vector (24 downto 0);
signal fxpArcsinXO2XResWFRange_uid84_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0);
signal path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest_in : std_logic_vector (25 downto 0);
signal path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0);
signal fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector (22 downto 0);
signal rightShiftStage1Idx1_uid256_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx2_uid259_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0);
signal rightShiftStage1Idx3_uid262_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0);
signal pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q : std_logic_vector (2 downto 0);
signal yT1_uid553_arccosXO2PolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid553_arccosXO2PolyEval_b : std_logic_vector (11 downto 0);
signal vStagei_uid318_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid318_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0);
signal vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (5 downto 0);
signal excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_c : std_logic_vector(0 downto 0);
signal excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0);
signal rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0);
signal InvExc_N_uid179_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid179_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal roundBit_uid203_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal roundBit_uid203_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal roundBit_uid482_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal roundBit_uid482_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal fpArcsinXO2XRes_uid85_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0);
signal RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0);
signal fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_in : std_logic_vector (33 downto 0);
signal fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0);
signal join_uid365_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector (2 downto 0);
signal pad_fxpArcsinL_uid94_uid95_acosX_uid8_fpArccosPiTest_q : std_logic_vector (26 downto 0);
signal exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_c : std_logic_vector(0 downto 0);
signal exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal roundBitAndNormalizationOp_uid206_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (25 downto 0);
signal roundBitAndNormalizationOp_uid485_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (25 downto 0);
signal expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (30 downto 0);
signal expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0);
signal signY_uid425_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (31 downto 0);
signal signY_uid425_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0);
signal fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (22 downto 0);
signal fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0);
signal SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_in : std_logic_vector (22 downto 0);
signal SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0);
signal SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_in : std_logic_vector (30 downto 0);
signal SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0);
signal signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (31 downto 0);
signal signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0);
signal fracSelIn_uid366_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector (3 downto 0);
signal excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0);
signal excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0);
signal add_one_fracY_uid428_uid429_uid429_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0);
signal oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0);
signal X23dto8_uid380_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0);
signal X23dto8_uid380_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b : std_logic_vector (15 downto 0);
signal X23dto16_uid383_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0);
signal X23dto16_uid383_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0);
signal rightShiftStage0Idx1_uid382_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0);
signal rightShiftStage0Idx2_uid385_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0);
begin
--xIn(GPIN,3)@0
--cstAllZWF_uid19_acosX_uid8_fpArccosPiTest(CONSTANT,18)
cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q <= "00000000000000000000000";
--GND(CONSTANT,0)
GND_q <= "0";
--cstAllOWE_uid18_acosX_uid8_fpArccosPiTest(CONSTANT,17)
cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q <= "11111111";
--cstBiasP1_uid26_acosX_uid8_fpArccosPiTest(CONSTANT,25)
cstBiasP1_uid26_acosX_uid8_fpArccosPiTest_q <= "10000000";
--ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable(LOGICAL,1457)
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_a <= en;
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q <= not ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_a;
--ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_nor(LOGICAL,1626)
ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q;
ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_nor_b <= ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q;
ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_nor_q <= not (ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_nor_a or ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_nor_b);
--ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_mem_top(CONSTANT,1609)
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_mem_top_q <= "011001";
--ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmp(LOGICAL,1610)
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmp_a <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_mem_top_q;
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux_q);
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmp_q <= "1" when ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmp_a = ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmp_b else "0";
--ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmpReg(REG,1611)
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmpReg_q <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_sticky_ena(REG,1627)
ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_nor_q = "1") THEN
ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_enaAnd(LOGICAL,1628)
ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_enaAnd_a <= ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q;
ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_enaAnd_b <= en;
ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_enaAnd_q <= ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_enaAnd_a and ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_enaAnd_b;
--rightShiftStage2Idx3Pad3_uid272_fxpX_uid59_acosX_uid8_fpArccosPiTest(CONSTANT,271)
rightShiftStage2Idx3Pad3_uid272_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= "000";
--RightShiftStage136dto3_uid271_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITSELECT,270)@1
RightShiftStage136dto3_uid271_fxpX_uid59_acosX_uid8_fpArccosPiTest_in <= rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_q;
RightShiftStage136dto3_uid271_fxpX_uid59_acosX_uid8_fpArccosPiTest_b <= RightShiftStage136dto3_uid271_fxpX_uid59_acosX_uid8_fpArccosPiTest_in(36 downto 3);
--rightShiftStage2Idx3_uid273_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITJOIN,272)@1
rightShiftStage2Idx3_uid273_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage2Idx3Pad3_uid272_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & RightShiftStage136dto3_uid271_fxpX_uid59_acosX_uid8_fpArccosPiTest_b;
--rightShiftStage2Idx2Pad2_uid269_fxpX_uid59_acosX_uid8_fpArccosPiTest(CONSTANT,268)
rightShiftStage2Idx2Pad2_uid269_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= "00";
--RightShiftStage136dto2_uid268_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITSELECT,267)@1
RightShiftStage136dto2_uid268_fxpX_uid59_acosX_uid8_fpArccosPiTest_in <= rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_q;
RightShiftStage136dto2_uid268_fxpX_uid59_acosX_uid8_fpArccosPiTest_b <= RightShiftStage136dto2_uid268_fxpX_uid59_acosX_uid8_fpArccosPiTest_in(36 downto 2);
--rightShiftStage2Idx2_uid270_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITJOIN,269)@1
rightShiftStage2Idx2_uid270_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage2Idx2Pad2_uid269_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & RightShiftStage136dto2_uid268_fxpX_uid59_acosX_uid8_fpArccosPiTest_b;
--RightShiftStage136dto1_uid265_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITSELECT,264)@1
RightShiftStage136dto1_uid265_fxpX_uid59_acosX_uid8_fpArccosPiTest_in <= rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_q;
RightShiftStage136dto1_uid265_fxpX_uid59_acosX_uid8_fpArccosPiTest_b <= RightShiftStage136dto1_uid265_fxpX_uid59_acosX_uid8_fpArccosPiTest_in(36 downto 1);
--rightShiftStage2Idx1_uid267_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITJOIN,266)@1
rightShiftStage2Idx1_uid267_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= GND_q & RightShiftStage136dto1_uid265_fxpX_uid59_acosX_uid8_fpArccosPiTest_b;
--rightShiftStage1Idx3Pad12_uid261_fxpX_uid59_acosX_uid8_fpArccosPiTest(CONSTANT,260)
rightShiftStage1Idx3Pad12_uid261_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= "000000000000";
--rightShiftStage0Idx3_uid251_fxpX_uid59_acosX_uid8_fpArccosPiTest(CONSTANT,250)
rightShiftStage0Idx3_uid251_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= "0000000000000000000000000000000000000";
--rightShiftStage0Idx2Pad32_uid249_fxpX_uid59_acosX_uid8_fpArccosPiTest(CONSTANT,248)
rightShiftStage0Idx2Pad32_uid249_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= "00000000000000000000000000000000";
--X36dto32_uid248_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITSELECT,247)@0
X36dto32_uid248_fxpX_uid59_acosX_uid8_fpArccosPiTest_in <= oFracXExt_uid58_acosX_uid8_fpArccosPiTest_q;
X36dto32_uid248_fxpX_uid59_acosX_uid8_fpArccosPiTest_b <= X36dto32_uid248_fxpX_uid59_acosX_uid8_fpArccosPiTest_in(36 downto 32);
--rightShiftStage0Idx2_uid250_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITJOIN,249)@0
rightShiftStage0Idx2_uid250_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage0Idx2Pad32_uid249_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & X36dto32_uid248_fxpX_uid59_acosX_uid8_fpArccosPiTest_b;
--rightShiftStage0Idx1Pad16_uid246_fxpX_uid59_acosX_uid8_fpArccosPiTest(CONSTANT,245)
rightShiftStage0Idx1Pad16_uid246_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= "0000000000000000";
--X36dto16_uid245_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITSELECT,244)@0
X36dto16_uid245_fxpX_uid59_acosX_uid8_fpArccosPiTest_in <= oFracXExt_uid58_acosX_uid8_fpArccosPiTest_q;
X36dto16_uid245_fxpX_uid59_acosX_uid8_fpArccosPiTest_b <= X36dto16_uid245_fxpX_uid59_acosX_uid8_fpArccosPiTest_in(36 downto 16);
--rightShiftStage0Idx1_uid247_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITJOIN,246)@0
rightShiftStage0Idx1_uid247_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage0Idx1Pad16_uid246_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & X36dto16_uid245_fxpX_uid59_acosX_uid8_fpArccosPiTest_b;
--fracX_uid16_acosX_uid8_fpArccosPiTest(BITSELECT,15)@0
fracX_uid16_acosX_uid8_fpArccosPiTest_in <= a(22 downto 0);
fracX_uid16_acosX_uid8_fpArccosPiTest_b <= fracX_uid16_acosX_uid8_fpArccosPiTest_in(22 downto 0);
--oFracX_uid51_uid51_acosX_uid8_fpArccosPiTest(BITJOIN,50)@0
oFracX_uid51_uid51_acosX_uid8_fpArccosPiTest_q <= VCC_q & fracX_uid16_acosX_uid8_fpArccosPiTest_b;
--cst01pWShift_uid57_acosX_uid8_fpArccosPiTest(CONSTANT,56)
cst01pWShift_uid57_acosX_uid8_fpArccosPiTest_q <= "0000000000000";
--oFracXExt_uid58_acosX_uid8_fpArccosPiTest(BITJOIN,57)@0
oFracXExt_uid58_acosX_uid8_fpArccosPiTest_q <= oFracX_uid51_uid51_acosX_uid8_fpArccosPiTest_q & cst01pWShift_uid57_acosX_uid8_fpArccosPiTest_q;
--shiftOutVal_uid54_acosX_uid8_fpArccosPiTest(CONSTANT,53)
shiftOutVal_uid54_acosX_uid8_fpArccosPiTest_q <= "100100";
--expX_uid15_acosX_uid8_fpArccosPiTest(BITSELECT,14)@0
expX_uid15_acosX_uid8_fpArccosPiTest_in <= a(30 downto 0);
expX_uid15_acosX_uid8_fpArccosPiTest_b <= expX_uid15_acosX_uid8_fpArccosPiTest_in(30 downto 23);
--cstBias_uid22_acosX_uid8_fpArccosPiTest(CONSTANT,21)
cstBias_uid22_acosX_uid8_fpArccosPiTest_q <= "01111111";
--shiftValuePre_uid53_acosX_uid8_fpArccosPiTest(SUB,52)@0
shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid22_acosX_uid8_fpArccosPiTest_q);
shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("0" & expX_uid15_acosX_uid8_fpArccosPiTest_b);
shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_a) - UNSIGNED(shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_b));
shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_q <= shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_o(8 downto 0);
--fxpShifterBits_uid55_acosX_uid8_fpArccosPiTest(BITSELECT,54)@0
fxpShifterBits_uid55_acosX_uid8_fpArccosPiTest_in <= shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_q(5 downto 0);
fxpShifterBits_uid55_acosX_uid8_fpArccosPiTest_b <= fxpShifterBits_uid55_acosX_uid8_fpArccosPiTest_in(5 downto 0);
--cstBiasMwFMwShift_uid24_acosX_uid8_fpArccosPiTest(CONSTANT,23)
cstBiasMwFMwShift_uid24_acosX_uid8_fpArccosPiTest_q <= "001011100";
--shiftValue_uid52_acosX_uid8_fpArccosPiTest(COMPARE,51)@0
shiftValue_uid52_acosX_uid8_fpArccosPiTest_cin <= GND_q;
shiftValue_uid52_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR((10 downto 9 => cstBiasMwFMwShift_uid24_acosX_uid8_fpArccosPiTest_q(8)) & cstBiasMwFMwShift_uid24_acosX_uid8_fpArccosPiTest_q) & '0';
shiftValue_uid52_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR('0' & "00" & expX_uid15_acosX_uid8_fpArccosPiTest_b) & shiftValue_uid52_acosX_uid8_fpArccosPiTest_cin(0);
shiftValue_uid52_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(shiftValue_uid52_acosX_uid8_fpArccosPiTest_a) - SIGNED(shiftValue_uid52_acosX_uid8_fpArccosPiTest_b));
shiftValue_uid52_acosX_uid8_fpArccosPiTest_n(0) <= not shiftValue_uid52_acosX_uid8_fpArccosPiTest_o(11);
--shiftValue_uid56_acosX_uid8_fpArccosPiTest(MUX,55)@0
shiftValue_uid56_acosX_uid8_fpArccosPiTest_s <= shiftValue_uid52_acosX_uid8_fpArccosPiTest_n;
shiftValue_uid56_acosX_uid8_fpArccosPiTest: PROCESS (shiftValue_uid56_acosX_uid8_fpArccosPiTest_s, en, fxpShifterBits_uid55_acosX_uid8_fpArccosPiTest_b, shiftOutVal_uid54_acosX_uid8_fpArccosPiTest_q)
BEGIN
CASE shiftValue_uid56_acosX_uid8_fpArccosPiTest_s IS
WHEN "0" => shiftValue_uid56_acosX_uid8_fpArccosPiTest_q <= fxpShifterBits_uid55_acosX_uid8_fpArccosPiTest_b;
WHEN "1" => shiftValue_uid56_acosX_uid8_fpArccosPiTest_q <= shiftOutVal_uid54_acosX_uid8_fpArccosPiTest_q;
WHEN OTHERS => shiftValue_uid56_acosX_uid8_fpArccosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel5Dto4_uid252_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITSELECT,251)@0
rightShiftStageSel5Dto4_uid252_fxpX_uid59_acosX_uid8_fpArccosPiTest_in <= shiftValue_uid56_acosX_uid8_fpArccosPiTest_q;
rightShiftStageSel5Dto4_uid252_fxpX_uid59_acosX_uid8_fpArccosPiTest_b <= rightShiftStageSel5Dto4_uid252_fxpX_uid59_acosX_uid8_fpArccosPiTest_in(5 downto 4);
--rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest(MUX,252)@0
rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_s <= rightShiftStageSel5Dto4_uid252_fxpX_uid59_acosX_uid8_fpArccosPiTest_b;
rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest: PROCESS (rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_s, en, oFracXExt_uid58_acosX_uid8_fpArccosPiTest_q, rightShiftStage0Idx1_uid247_fxpX_uid59_acosX_uid8_fpArccosPiTest_q, rightShiftStage0Idx2_uid250_fxpX_uid59_acosX_uid8_fpArccosPiTest_q, rightShiftStage0Idx3_uid251_fxpX_uid59_acosX_uid8_fpArccosPiTest_q)
BEGIN
CASE rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_s IS
WHEN "00" => rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= oFracXExt_uid58_acosX_uid8_fpArccosPiTest_q;
WHEN "01" => rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage0Idx1_uid247_fxpX_uid59_acosX_uid8_fpArccosPiTest_q;
WHEN "10" => rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage0Idx2_uid250_fxpX_uid59_acosX_uid8_fpArccosPiTest_q;
WHEN "11" => rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage0Idx3_uid251_fxpX_uid59_acosX_uid8_fpArccosPiTest_q;
WHEN OTHERS => rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage036dto12_uid260_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITSELECT,259)@0
RightShiftStage036dto12_uid260_fxpX_uid59_acosX_uid8_fpArccosPiTest_in <= rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_q;
RightShiftStage036dto12_uid260_fxpX_uid59_acosX_uid8_fpArccosPiTest_b <= RightShiftStage036dto12_uid260_fxpX_uid59_acosX_uid8_fpArccosPiTest_in(36 downto 12);
--rightShiftStage1Idx3_uid262_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITJOIN,261)@0
rightShiftStage1Idx3_uid262_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1Idx3Pad12_uid261_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & RightShiftStage036dto12_uid260_fxpX_uid59_acosX_uid8_fpArccosPiTest_b;
--reg_rightShiftStage1Idx3_uid262_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_5(REG,613)@0
reg_rightShiftStage1Idx3_uid262_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx3_uid262_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_5_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx3_uid262_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_5_q <= rightShiftStage1Idx3_uid262_fxpX_uid59_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage036dto8_uid257_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITSELECT,256)@0
RightShiftStage036dto8_uid257_fxpX_uid59_acosX_uid8_fpArccosPiTest_in <= rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_q;
RightShiftStage036dto8_uid257_fxpX_uid59_acosX_uid8_fpArccosPiTest_b <= RightShiftStage036dto8_uid257_fxpX_uid59_acosX_uid8_fpArccosPiTest_in(36 downto 8);
--rightShiftStage1Idx2_uid259_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITJOIN,258)@0
rightShiftStage1Idx2_uid259_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q & RightShiftStage036dto8_uid257_fxpX_uid59_acosX_uid8_fpArccosPiTest_b;
--reg_rightShiftStage1Idx2_uid259_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_4(REG,612)@0
reg_rightShiftStage1Idx2_uid259_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx2_uid259_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_4_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx2_uid259_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_4_q <= rightShiftStage1Idx2_uid259_fxpX_uid59_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStage1Idx1Pad4_uid255_fxpX_uid59_acosX_uid8_fpArccosPiTest(CONSTANT,254)
rightShiftStage1Idx1Pad4_uid255_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= "0000";
--RightShiftStage036dto4_uid254_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITSELECT,253)@0
RightShiftStage036dto4_uid254_fxpX_uid59_acosX_uid8_fpArccosPiTest_in <= rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_q;
RightShiftStage036dto4_uid254_fxpX_uid59_acosX_uid8_fpArccosPiTest_b <= RightShiftStage036dto4_uid254_fxpX_uid59_acosX_uid8_fpArccosPiTest_in(36 downto 4);
--rightShiftStage1Idx1_uid256_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITJOIN,255)@0
rightShiftStage1Idx1_uid256_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1Idx1Pad4_uid255_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & RightShiftStage036dto4_uid254_fxpX_uid59_acosX_uid8_fpArccosPiTest_b;
--reg_rightShiftStage1Idx1_uid256_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_3(REG,611)@0
reg_rightShiftStage1Idx1_uid256_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx1_uid256_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_3_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx1_uid256_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_3_q <= rightShiftStage1Idx1_uid256_fxpX_uid59_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_2(REG,610)@0
reg_rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_2_q <= "0000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_2_q <= rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITSELECT,262)@0
rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_in <= shiftValue_uid56_acosX_uid8_fpArccosPiTest_q(3 downto 0);
rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_b <= rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_in(3 downto 2);
--reg_rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_1(REG,609)@0
reg_rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_1_q <= rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest(MUX,263)@1
rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_s <= reg_rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_1_q;
rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest: PROCESS (rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_s, en, reg_rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_2_q, reg_rightShiftStage1Idx1_uid256_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_3_q, reg_rightShiftStage1Idx2_uid259_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_4_q, reg_rightShiftStage1Idx3_uid262_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_5_q)
BEGIN
CASE rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_s IS
WHEN "00" => rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_2_q;
WHEN "01" => rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage1Idx1_uid256_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_3_q;
WHEN "10" => rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage1Idx2_uid259_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_4_q;
WHEN "11" => rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage1Idx3_uid262_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_5_q;
WHEN OTHERS => rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITSELECT,273)@0
rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_in <= shiftValue_uid56_acosX_uid8_fpArccosPiTest_q(1 downto 0);
rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_b <= rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_in(1 downto 0);
--reg_rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_1(REG,614)@0
reg_rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_1_q <= rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest(MUX,274)@1
rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_s <= reg_rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_1_q;
rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest: PROCESS (rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_s, en, rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_q, rightShiftStage2Idx1_uid267_fxpX_uid59_acosX_uid8_fpArccosPiTest_q, rightShiftStage2Idx2_uid270_fxpX_uid59_acosX_uid8_fpArccosPiTest_q, rightShiftStage2Idx3_uid273_fxpX_uid59_acosX_uid8_fpArccosPiTest_q)
BEGIN
CASE rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_s IS
WHEN "00" => rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_q;
WHEN "01" => rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage2Idx1_uid267_fxpX_uid59_acosX_uid8_fpArccosPiTest_q;
WHEN "10" => rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage2Idx2_uid270_fxpX_uid59_acosX_uid8_fpArccosPiTest_q;
WHEN "11" => rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage2Idx3_uid273_fxpX_uid59_acosX_uid8_fpArccosPiTest_q;
WHEN OTHERS => rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid61_acosX_uid8_fpArccosPiTest(BITSELECT,60)@1
y_uid61_acosX_uid8_fpArccosPiTest_in <= rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_q(35 downto 0);
y_uid61_acosX_uid8_fpArccosPiTest_b <= y_uid61_acosX_uid8_fpArccosPiTest_in(35 downto 1);
--mAddr_uid107_acosX_uid8_fpArccosPiTest(BITSELECT,106)@1
mAddr_uid107_acosX_uid8_fpArccosPiTest_in <= y_uid61_acosX_uid8_fpArccosPiTest_b;
mAddr_uid107_acosX_uid8_fpArccosPiTest_b <= mAddr_uid107_acosX_uid8_fpArccosPiTest_in(34 downto 27);
--reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid552_arccosXO2TabGen_lutmem_0(REG,688)@1
reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid552_arccosXO2TabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid552_arccosXO2TabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid552_arccosXO2TabGen_lutmem_0_q <= mAddr_uid107_acosX_uid8_fpArccosPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid552_arccosXO2TabGen_lutmem(DUALMEM,604)@2
memoryC2_uid552_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC2_uid552_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC2_uid552_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC2_uid552_arccosXO2TabGen_lutmem_ab <= reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid552_arccosXO2TabGen_lutmem_0_q;
memoryC2_uid552_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccospi_s5_memoryC2_uid552_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid552_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid552_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid552_arccosXO2TabGen_lutmem_iq,
address_a => memoryC2_uid552_arccosXO2TabGen_lutmem_aa,
data_a => memoryC2_uid552_arccosXO2TabGen_lutmem_ia
);
memoryC2_uid552_arccosXO2TabGen_lutmem_q <= memoryC2_uid552_arccosXO2TabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid552_arccosXO2TabGen_lutmem_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_1(REG,690)@4
reg_memoryC2_uid552_arccosXO2TabGen_lutmem_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid552_arccosXO2TabGen_lutmem_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid552_arccosXO2TabGen_lutmem_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_1_q <= memoryC2_uid552_arccosXO2TabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--mPPolyEval_uid108_acosX_uid8_fpArccosPiTest(BITSELECT,107)@1
mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_in <= y_uid61_acosX_uid8_fpArccosPiTest_b(26 downto 0);
mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_b <= mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_in(26 downto 12);
--yT1_uid553_arccosXO2PolyEval(BITSELECT,552)@1
yT1_uid553_arccosXO2PolyEval_in <= mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_b;
yT1_uid553_arccosXO2PolyEval_b <= yT1_uid553_arccosXO2PolyEval_in(14 downto 3);
--ld_yT1_uid553_arccosXO2PolyEval_b_to_reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_a_inputreg(DELAY,1601)
ld_yT1_uid553_arccosXO2PolyEval_b_to_reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 12, depth => 1 )
PORT MAP ( xin => yT1_uid553_arccosXO2PolyEval_b, xout => ld_yT1_uid553_arccosXO2PolyEval_b_to_reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid553_arccosXO2PolyEval_b_to_reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_a(DELAY,1420)@1
ld_yT1_uid553_arccosXO2PolyEval_b_to_reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_a : dspba_delay
GENERIC MAP ( width => 12, depth => 2 )
PORT MAP ( xin => ld_yT1_uid553_arccosXO2PolyEval_b_to_reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_a_inputreg_q, xout => ld_yT1_uid553_arccosXO2PolyEval_b_to_reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0(REG,689)@4
reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_q <= ld_yT1_uid553_arccosXO2PolyEval_b_to_reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid588_pT1_uid554_arccosXO2PolyEval(MULT,587)@5
prodXY_uid588_pT1_uid554_arccosXO2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid588_pT1_uid554_arccosXO2PolyEval_a),13)) * SIGNED(prodXY_uid588_pT1_uid554_arccosXO2PolyEval_b);
prodXY_uid588_pT1_uid554_arccosXO2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid588_pT1_uid554_arccosXO2PolyEval_a <= (others => '0');
prodXY_uid588_pT1_uid554_arccosXO2PolyEval_b <= (others => '0');
prodXY_uid588_pT1_uid554_arccosXO2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid588_pT1_uid554_arccosXO2PolyEval_a <= reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_q;
prodXY_uid588_pT1_uid554_arccosXO2PolyEval_b <= reg_memoryC2_uid552_arccosXO2TabGen_lutmem_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_1_q;
prodXY_uid588_pT1_uid554_arccosXO2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid588_pT1_uid554_arccosXO2PolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid588_pT1_uid554_arccosXO2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid588_pT1_uid554_arccosXO2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid588_pT1_uid554_arccosXO2PolyEval_q <= prodXY_uid588_pT1_uid554_arccosXO2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid589_pT1_uid554_arccosXO2PolyEval(BITSELECT,588)@8
prodXYTruncFR_uid589_pT1_uid554_arccosXO2PolyEval_in <= prodXY_uid588_pT1_uid554_arccosXO2PolyEval_q;
prodXYTruncFR_uid589_pT1_uid554_arccosXO2PolyEval_b <= prodXYTruncFR_uid589_pT1_uid554_arccosXO2PolyEval_in(23 downto 11);
--highBBits_uid556_arccosXO2PolyEval(BITSELECT,555)@8
highBBits_uid556_arccosXO2PolyEval_in <= prodXYTruncFR_uid589_pT1_uid554_arccosXO2PolyEval_b;
highBBits_uid556_arccosXO2PolyEval_b <= highBBits_uid556_arccosXO2PolyEval_in(12 downto 1);
--ld_mAddr_uid107_acosX_uid8_fpArccosPiTest_b_to_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_a_inputreg(DELAY,1602)
ld_mAddr_uid107_acosX_uid8_fpArccosPiTest_b_to_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => mAddr_uid107_acosX_uid8_fpArccosPiTest_b, xout => ld_mAddr_uid107_acosX_uid8_fpArccosPiTest_b_to_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_mAddr_uid107_acosX_uid8_fpArccosPiTest_b_to_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_a(DELAY,1422)@1
ld_mAddr_uid107_acosX_uid8_fpArccosPiTest_b_to_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => ld_mAddr_uid107_acosX_uid8_fpArccosPiTest_b_to_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_a_inputreg_q, xout => ld_mAddr_uid107_acosX_uid8_fpArccosPiTest_b_to_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0(REG,691)@5
reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_q <= ld_mAddr_uid107_acosX_uid8_fpArccosPiTest_b_to_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid551_arccosXO2TabGen_lutmem(DUALMEM,603)@6
memoryC1_uid551_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC1_uid551_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC1_uid551_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC1_uid551_arccosXO2TabGen_lutmem_ab <= reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_q;
memoryC1_uid551_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 22,
widthad_a => 8,
numwords_a => 256,
width_b => 22,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccospi_s5_memoryC1_uid551_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid551_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid551_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid551_arccosXO2TabGen_lutmem_iq,
address_a => memoryC1_uid551_arccosXO2TabGen_lutmem_aa,
data_a => memoryC1_uid551_arccosXO2TabGen_lutmem_ia
);
memoryC1_uid551_arccosXO2TabGen_lutmem_q <= memoryC1_uid551_arccosXO2TabGen_lutmem_iq(21 downto 0);
--sumAHighB_uid557_arccosXO2PolyEval(ADD,556)@8
sumAHighB_uid557_arccosXO2PolyEval_a <= STD_LOGIC_VECTOR((22 downto 22 => memoryC1_uid551_arccosXO2TabGen_lutmem_q(21)) & memoryC1_uid551_arccosXO2TabGen_lutmem_q);
sumAHighB_uid557_arccosXO2PolyEval_b <= STD_LOGIC_VECTOR((22 downto 12 => highBBits_uid556_arccosXO2PolyEval_b(11)) & highBBits_uid556_arccosXO2PolyEval_b);
sumAHighB_uid557_arccosXO2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid557_arccosXO2PolyEval_a) + SIGNED(sumAHighB_uid557_arccosXO2PolyEval_b));
sumAHighB_uid557_arccosXO2PolyEval_q <= sumAHighB_uid557_arccosXO2PolyEval_o(22 downto 0);
--lowRangeB_uid555_arccosXO2PolyEval(BITSELECT,554)@8
lowRangeB_uid555_arccosXO2PolyEval_in <= prodXYTruncFR_uid589_pT1_uid554_arccosXO2PolyEval_b(0 downto 0);
lowRangeB_uid555_arccosXO2PolyEval_b <= lowRangeB_uid555_arccosXO2PolyEval_in(0 downto 0);
--s1_uid555_uid558_arccosXO2PolyEval(BITJOIN,557)@8
s1_uid555_uid558_arccosXO2PolyEval_q <= sumAHighB_uid557_arccosXO2PolyEval_q & lowRangeB_uid555_arccosXO2PolyEval_b;
--reg_s1_uid555_uid558_arccosXO2PolyEval_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_1(REG,693)@8
reg_s1_uid555_uid558_arccosXO2PolyEval_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid555_uid558_arccosXO2PolyEval_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid555_uid558_arccosXO2PolyEval_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_1_q <= s1_uid555_uid558_arccosXO2PolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_nor(LOGICAL,1535)
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q;
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_nor_b <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_sticky_ena_q;
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_nor_q <= not (ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_nor_a or ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_nor_b);
--ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_mem_top(CONSTANT,1531)
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_mem_top_q <= "0101";
--ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmp(LOGICAL,1532)
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmp_a <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_mem_top_q;
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_q);
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmp_q <= "1" when ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmp_a = ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmp_b else "0";
--ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmpReg(REG,1533)
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmpReg_q <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_sticky_ena(REG,1536)
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_nor_q = "1") THEN
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_sticky_ena_q <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_enaAnd(LOGICAL,1537)
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_enaAnd_a <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_sticky_ena_q;
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_enaAnd_b <= en;
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_enaAnd_q <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_enaAnd_a and ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_enaAnd_b;
--reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0(REG,692)@1
reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q <= mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt(COUNTER,1527)
-- every=1, low=0, high=5, step=1, init=1
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_i = 4 THEN
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_eq = '1') THEN
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_i <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_i - 5;
ELSE
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_i <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_i,3));
--ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdreg(REG,1528)
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdreg_q <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux(MUX,1529)
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_s <= en;
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux: PROCESS (ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_s, ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdreg_q, ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_q <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdreg_q;
WHEN "1" => ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_q <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem(DUALMEM,1526)
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_reset0 <= areset;
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_ia <= reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q;
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_aa <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdreg_q;
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_ab <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_q;
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 6,
width_b => 15,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_iq,
address_a => ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_aa,
data_a => ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_ia
);
ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_q <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_iq(14 downto 0);
--prodXY_uid591_pT2_uid560_arccosXO2PolyEval(MULT,590)@9
prodXY_uid591_pT2_uid560_arccosXO2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a),16)) * SIGNED(prodXY_uid591_pT2_uid560_arccosXO2PolyEval_b);
prodXY_uid591_pT2_uid560_arccosXO2PolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a <= (others => '0');
prodXY_uid591_pT2_uid560_arccosXO2PolyEval_b <= (others => '0');
prodXY_uid591_pT2_uid560_arccosXO2PolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_q;
prodXY_uid591_pT2_uid560_arccosXO2PolyEval_b <= reg_s1_uid555_uid558_arccosXO2PolyEval_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_1_q;
prodXY_uid591_pT2_uid560_arccosXO2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid591_pT2_uid560_arccosXO2PolyEval_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid591_pT2_uid560_arccosXO2PolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid591_pT2_uid560_arccosXO2PolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid591_pT2_uid560_arccosXO2PolyEval_q <= prodXY_uid591_pT2_uid560_arccosXO2PolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid592_pT2_uid560_arccosXO2PolyEval(BITSELECT,591)@12
prodXYTruncFR_uid592_pT2_uid560_arccosXO2PolyEval_in <= prodXY_uid591_pT2_uid560_arccosXO2PolyEval_q;
prodXYTruncFR_uid592_pT2_uid560_arccosXO2PolyEval_b <= prodXYTruncFR_uid592_pT2_uid560_arccosXO2PolyEval_in(38 downto 14);
--highBBits_uid562_arccosXO2PolyEval(BITSELECT,561)@12
highBBits_uid562_arccosXO2PolyEval_in <= prodXYTruncFR_uid592_pT2_uid560_arccosXO2PolyEval_b;
highBBits_uid562_arccosXO2PolyEval_b <= highBBits_uid562_arccosXO2PolyEval_in(24 downto 2);
--ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_nor(LOGICAL,1548)
ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q;
ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_nor_b <= ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_sticky_ena_q;
ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_nor_q <= not (ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_nor_a or ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_nor_b);
--ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_sticky_ena(REG,1549)
ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_nor_q = "1") THEN
ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_sticky_ena_q <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_enaAnd(LOGICAL,1550)
ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_enaAnd_a <= ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_sticky_ena_q;
ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_enaAnd_b <= en;
ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_enaAnd_q <= ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_enaAnd_a and ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_enaAnd_b;
--ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem(DUALMEM,1539)
ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_ia <= reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid552_arccosXO2TabGen_lutmem_0_q;
ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_aa <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdreg_q;
ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_ab <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_q;
ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_iq,
address_a => ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_aa,
data_a => ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_ia
);
ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_q <= ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_iq(7 downto 0);
--ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_outputreg(DELAY,1538)
ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_q, xout => ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC0_uid550_arccosXO2TabGen_lutmem(DUALMEM,602)@10
memoryC0_uid550_arccosXO2TabGen_lutmem_reset0 <= areset;
memoryC0_uid550_arccosXO2TabGen_lutmem_ia <= (others => '0');
memoryC0_uid550_arccosXO2TabGen_lutmem_aa <= (others => '0');
memoryC0_uid550_arccosXO2TabGen_lutmem_ab <= ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_outputreg_q;
memoryC0_uid550_arccosXO2TabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccospi_s5_memoryC0_uid550_arccosXO2TabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid550_arccosXO2TabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid550_arccosXO2TabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid550_arccosXO2TabGen_lutmem_iq,
address_a => memoryC0_uid550_arccosXO2TabGen_lutmem_aa,
data_a => memoryC0_uid550_arccosXO2TabGen_lutmem_ia
);
memoryC0_uid550_arccosXO2TabGen_lutmem_q <= memoryC0_uid550_arccosXO2TabGen_lutmem_iq(29 downto 0);
--sumAHighB_uid563_arccosXO2PolyEval(ADD,562)@12
sumAHighB_uid563_arccosXO2PolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => memoryC0_uid550_arccosXO2TabGen_lutmem_q(29)) & memoryC0_uid550_arccosXO2TabGen_lutmem_q);
sumAHighB_uid563_arccosXO2PolyEval_b <= STD_LOGIC_VECTOR((30 downto 23 => highBBits_uid562_arccosXO2PolyEval_b(22)) & highBBits_uid562_arccosXO2PolyEval_b);
sumAHighB_uid563_arccosXO2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid563_arccosXO2PolyEval_a) + SIGNED(sumAHighB_uid563_arccosXO2PolyEval_b));
sumAHighB_uid563_arccosXO2PolyEval_q <= sumAHighB_uid563_arccosXO2PolyEval_o(30 downto 0);
--lowRangeB_uid561_arccosXO2PolyEval(BITSELECT,560)@12
lowRangeB_uid561_arccosXO2PolyEval_in <= prodXYTruncFR_uid592_pT2_uid560_arccosXO2PolyEval_b(1 downto 0);
lowRangeB_uid561_arccosXO2PolyEval_b <= lowRangeB_uid561_arccosXO2PolyEval_in(1 downto 0);
--s2_uid561_uid564_arccosXO2PolyEval(BITJOIN,563)@12
s2_uid561_uid564_arccosXO2PolyEval_q <= sumAHighB_uid563_arccosXO2PolyEval_q & lowRangeB_uid561_arccosXO2PolyEval_b;
--fxpArccosX_uid110_acosX_uid8_fpArccosPiTest(BITSELECT,109)@12
fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_in <= s2_uid561_uid564_arccosXO2PolyEval_q(30 downto 0);
fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_b <= fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_in(30 downto 4);
--reg_fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_1(REG,696)@12
reg_fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_1_q <= fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_b;
END IF;
END IF;
END PROCESS;
--pi2_uid111_acosX_uid8_fpArccosPiTest(CONSTANT,110)
pi2_uid111_acosX_uid8_fpArccosPiTest_q <= "110010010000111111011010101";
--pad_pi2_uid111_uid112_acosX_uid8_fpArccosPiTest(BITJOIN,111)@12
pad_pi2_uid111_uid112_acosX_uid8_fpArccosPiTest_q <= pi2_uid111_acosX_uid8_fpArccosPiTest_q & GND_q;
--reg_pad_pi2_uid111_uid112_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_0(REG,695)@12
reg_pad_pi2_uid111_uid112_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_pi2_uid111_uid112_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_0_q <= "0000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_pi2_uid111_uid112_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_0_q <= pad_pi2_uid111_uid112_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--path2Diff_uid112_acosX_uid8_fpArccosPiTest(SUB,112)@13
path2Diff_uid112_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_pi2_uid111_uid112_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_0_q);
path2Diff_uid112_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_1_q);
path2Diff_uid112_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2Diff_uid112_acosX_uid8_fpArccosPiTest_a) - UNSIGNED(path2Diff_uid112_acosX_uid8_fpArccosPiTest_b));
path2Diff_uid112_acosX_uid8_fpArccosPiTest_q <= path2Diff_uid112_acosX_uid8_fpArccosPiTest_o(28 downto 0);
--path2NegCaseFPFrac_uid115_acosX_uid8_fpArccosPiTest(BITSELECT,114)@13
path2NegCaseFPFrac_uid115_acosX_uid8_fpArccosPiTest_in <= path2Diff_uid112_acosX_uid8_fpArccosPiTest_q(26 downto 0);
path2NegCaseFPFrac_uid115_acosX_uid8_fpArccosPiTest_b <= path2NegCaseFPFrac_uid115_acosX_uid8_fpArccosPiTest_in(26 downto 4);
--path2NegCaseFPL_uid116_acosX_uid8_fpArccosPiTest(BITJOIN,115)@13
path2NegCaseFPL_uid116_acosX_uid8_fpArccosPiTest_q <= GND_q & cstBiasP1_uid26_acosX_uid8_fpArccosPiTest_q & path2NegCaseFPFrac_uid115_acosX_uid8_fpArccosPiTest_b;
--path2NegCaseFPFrac_uid118_acosX_uid8_fpArccosPiTest(BITSELECT,117)@13
path2NegCaseFPFrac_uid118_acosX_uid8_fpArccosPiTest_in <= path2Diff_uid112_acosX_uid8_fpArccosPiTest_q(25 downto 0);
path2NegCaseFPFrac_uid118_acosX_uid8_fpArccosPiTest_b <= path2NegCaseFPFrac_uid118_acosX_uid8_fpArccosPiTest_in(25 downto 3);
--path2NegCaseFPS_uid119_acosX_uid8_fpArccosPiTest(BITJOIN,118)@13
path2NegCaseFPS_uid119_acosX_uid8_fpArccosPiTest_q <= GND_q & cstBias_uid22_acosX_uid8_fpArccosPiTest_q & path2NegCaseFPFrac_uid118_acosX_uid8_fpArccosPiTest_b;
--normBit_uid114_acosX_uid8_fpArccosPiTest(BITSELECT,113)@13
normBit_uid114_acosX_uid8_fpArccosPiTest_in <= path2Diff_uid112_acosX_uid8_fpArccosPiTest_q(27 downto 0);
normBit_uid114_acosX_uid8_fpArccosPiTest_b <= normBit_uid114_acosX_uid8_fpArccosPiTest_in(27 downto 27);
--path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest(MUX,120)@13
path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest_s <= normBit_uid114_acosX_uid8_fpArccosPiTest_b;
path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest: PROCESS (path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest_s, en, path2NegCaseFPS_uid119_acosX_uid8_fpArccosPiTest_q, path2NegCaseFPL_uid116_acosX_uid8_fpArccosPiTest_q)
BEGIN
CASE path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest_s IS
WHEN "0" => path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest_q <= path2NegCaseFPS_uid119_acosX_uid8_fpArccosPiTest_q;
WHEN "1" => path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest_q <= path2NegCaseFPL_uid116_acosX_uid8_fpArccosPiTest_q;
WHEN OTHERS => path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest(BITSELECT,121)@12
path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest_in <= fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_b(25 downto 0);
path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest_b <= path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest_in(25 downto 3);
--ld_path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest_b_to_path2PosCaseFP_uid123_acosX_uid8_fpArccosPiTest_a(DELAY,806)@12
ld_path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest_b_to_path2PosCaseFP_uid123_acosX_uid8_fpArccosPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest_b, xout => ld_path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest_b_to_path2PosCaseFP_uid123_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--path2PosCaseFP_uid123_acosX_uid8_fpArccosPiTest(BITJOIN,122)@13
path2PosCaseFP_uid123_acosX_uid8_fpArccosPiTest_q <= GND_q & cstBias_uid22_acosX_uid8_fpArccosPiTest_q & ld_path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest_b_to_path2PosCaseFP_uid123_acosX_uid8_fpArccosPiTest_a_q;
--singX_uid17_acosX_uid8_fpArccosPiTest(BITSELECT,16)@0
singX_uid17_acosX_uid8_fpArccosPiTest_in <= a;
singX_uid17_acosX_uid8_fpArccosPiTest_b <= singX_uid17_acosX_uid8_fpArccosPiTest_in(31 downto 31);
--ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path2ResFP_uid125_acosX_uid8_fpArccosPiTest_b(DELAY,807)@0
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path2ResFP_uid125_acosX_uid8_fpArccosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => singX_uid17_acosX_uid8_fpArccosPiTest_b, xout => ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path2ResFP_uid125_acosX_uid8_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--path2ResFP_uid125_acosX_uid8_fpArccosPiTest(MUX,124)@13
path2ResFP_uid125_acosX_uid8_fpArccosPiTest_s <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path2ResFP_uid125_acosX_uid8_fpArccosPiTest_b_q;
path2ResFP_uid125_acosX_uid8_fpArccosPiTest: PROCESS (path2ResFP_uid125_acosX_uid8_fpArccosPiTest_s, en, path2PosCaseFP_uid123_acosX_uid8_fpArccosPiTest_q, path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest_q)
BEGIN
CASE path2ResFP_uid125_acosX_uid8_fpArccosPiTest_s IS
WHEN "0" => path2ResFP_uid125_acosX_uid8_fpArccosPiTest_q <= path2PosCaseFP_uid123_acosX_uid8_fpArccosPiTest_q;
WHEN "1" => path2ResFP_uid125_acosX_uid8_fpArccosPiTest_q <= path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest_q;
WHEN OTHERS => path2ResFP_uid125_acosX_uid8_fpArccosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest(BITSELECT,131)@13
Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_in <= path2ResFP_uid125_acosX_uid8_fpArccosPiTest_q(30 downto 0);
Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b <= Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_in(30 downto 23);
--ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_inputreg(DELAY,1616)
ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b, xout => ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt(COUNTER,1605)
-- every=1, low=0, high=25, step=1, init=1
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_i = 24 THEN
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_eq <= '1';
ELSE
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_eq = '1') THEN
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_i <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_i - 25;
ELSE
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_i <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_i,5));
--ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdreg(REG,1606)
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdreg_q <= "00000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdreg_q <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux(MUX,1607)
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux_s <= en;
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux: PROCESS (ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux_s, ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdreg_q, ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_q)
BEGIN
CASE ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux_s IS
WHEN "0" => ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux_q <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdreg_q;
WHEN "1" => ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux_q <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_q;
WHEN OTHERS => ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem(DUALMEM,1617)
ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_reset0 <= areset;
ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ia <= ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_inputreg_q;
ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_aa <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdreg_q;
ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ab <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux_q;
ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 5,
numwords_a => 26,
width_b => 8,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_iq,
address_a => ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_aa,
data_a => ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ia
);
ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_q <= ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_iq(7 downto 0);
--reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3(REG,700)@41
reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_q <= ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage123dto1_uid544_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITSELECT,543)@39
RightShiftStage123dto1_uid544_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in <= rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q;
RightShiftStage123dto1_uid544_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b <= RightShiftStage123dto1_uid544_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in(23 downto 1);
--rightShiftStage2Idx1_uid546_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITJOIN,545)@39
rightShiftStage2Idx1_uid546_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= GND_q & RightShiftStage123dto1_uid544_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b;
--rightShiftStage1Idx3Pad6_uid396_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(CONSTANT,395)
rightShiftStage1Idx3Pad6_uid396_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= "000000";
--RightShiftStage023dto6_uid539_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITSELECT,538)@39
RightShiftStage023dto6_uid539_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in <= rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q;
RightShiftStage023dto6_uid539_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b <= RightShiftStage023dto6_uid539_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in(23 downto 6);
--rightShiftStage1Idx3_uid541_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITJOIN,540)@39
rightShiftStage1Idx3_uid541_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1Idx3Pad6_uid396_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q & RightShiftStage023dto6_uid539_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b;
--RightShiftStage023dto4_uid536_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITSELECT,535)@39
RightShiftStage023dto4_uid536_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in <= rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q;
RightShiftStage023dto4_uid536_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b <= RightShiftStage023dto4_uid536_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in(23 downto 4);
--rightShiftStage1Idx2_uid538_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITJOIN,537)@39
rightShiftStage1Idx2_uid538_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1Idx1Pad4_uid255_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & RightShiftStage023dto4_uid536_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b;
--RightShiftStage023dto2_uid533_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITSELECT,532)@39
RightShiftStage023dto2_uid533_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in <= rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q;
RightShiftStage023dto2_uid533_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b <= RightShiftStage023dto2_uid533_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in(23 downto 2);
--rightShiftStage1Idx1_uid535_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITJOIN,534)@39
rightShiftStage1Idx1_uid535_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= rightShiftStage2Idx2Pad2_uid269_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & RightShiftStage023dto2_uid533_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b;
--rightShiftStage0Idx3_uid386_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(CONSTANT,385)
rightShiftStage0Idx3_uid386_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= "000000000000000000000000";
--maxCountVal_uid320_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(CONSTANT,319)
maxCountVal_uid320_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= "100011";
--reg_y_uid61_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_1(REG,616)@1
reg_y_uid61_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid61_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_1_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid61_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_1_q <= y_uid61_acosX_uid8_fpArccosPiTest_b;
END IF;
END IF;
END PROCESS;
--pad_o_uid27_uid63_acosX_uid8_fpArccosPiTest(BITJOIN,62)@1
pad_o_uid27_uid63_acosX_uid8_fpArccosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((34 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid27_uid63_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_0(REG,615)@1
reg_pad_o_uid27_uid63_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid27_uid63_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_0_q <= "000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_o_uid27_uid63_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_0_q <= pad_o_uid27_uid63_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--oMy_uid63_acosX_uid8_fpArccosPiTest(SUB,63)@2
oMy_uid63_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid27_uid63_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_0_q);
oMy_uid63_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid61_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_1_q);
oMy_uid63_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMy_uid63_acosX_uid8_fpArccosPiTest_a) - UNSIGNED(oMy_uid63_acosX_uid8_fpArccosPiTest_b));
oMy_uid63_acosX_uid8_fpArccosPiTest_q <= oMy_uid63_acosX_uid8_fpArccosPiTest_o(36 downto 0);
--l_uid65_acosX_uid8_fpArccosPiTest(BITSELECT,64)@2
l_uid65_acosX_uid8_fpArccosPiTest_in <= oMy_uid63_acosX_uid8_fpArccosPiTest_q(34 downto 0);
l_uid65_acosX_uid8_fpArccosPiTest_b <= l_uid65_acosX_uid8_fpArccosPiTest_in(34 downto 0);
--rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,277)@2
rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= l_uid65_acosX_uid8_fpArccosPiTest_b;
rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(34 downto 3);
--reg_rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1(REG,617)@2
reg_rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q <= rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(LOGICAL,278)@3
vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a <= reg_rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q;
vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= rightShiftStage0Idx2Pad32_uid249_fxpX_uid59_acosX_uid8_fpArccosPiTest_q;
vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= "1" when vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a = vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b else "0";
--ld_vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_f(DELAY,1040)@3
ld_vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q, xout => ld_vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid281_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,280)@2
vStage_uid281_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= l_uid65_acosX_uid8_fpArccosPiTest_b(2 downto 0);
vStage_uid281_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= vStage_uid281_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(2 downto 0);
--cStage_uid282_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITJOIN,281)@2
cStage_uid282_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= vStage_uid281_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b & rightShiftStage0Idx2Pad32_uid249_fxpX_uid59_acosX_uid8_fpArccosPiTest_q;
--reg_cStage_uid282_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3(REG,619)@2
reg_cStage_uid282_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid282_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid282_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q <= cStage_uid282_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_l_uid65_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2(REG,618)@2
reg_l_uid65_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_l_uid65_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_l_uid65_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q <= l_uid65_acosX_uid8_fpArccosPiTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(MUX,282)@3
vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s <= vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q;
vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest: PROCESS (vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s, en, reg_l_uid65_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q, reg_cStage_uid282_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q)
BEGIN
CASE vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s IS
WHEN "0" => vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= reg_l_uid65_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q;
WHEN "1" => vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= reg_cStage_uid282_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q;
WHEN OTHERS => vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,284)@3
rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q;
rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(34 downto 19);
--reg_rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1(REG,620)@3
reg_rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q <= rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(LOGICAL,285)@4
vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a <= reg_rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q;
vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= rightShiftStage0Idx1Pad16_uid246_fxpX_uid59_acosX_uid8_fpArccosPiTest_q;
vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= "1" when vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a = vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b else "0";
--ld_vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_e(DELAY,1039)@4
ld_vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q, xout => ld_vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid288_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,287)@3
vStage_uid288_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q(18 downto 0);
vStage_uid288_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= vStage_uid288_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(18 downto 0);
--cStage_uid289_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITJOIN,288)@3
cStage_uid289_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= vStage_uid288_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b & rightShiftStage0Idx1Pad16_uid246_fxpX_uid59_acosX_uid8_fpArccosPiTest_q;
--reg_cStage_uid289_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3(REG,622)@3
reg_cStage_uid289_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid289_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid289_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q <= cStage_uid289_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2(REG,621)@3
reg_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q <= vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(MUX,289)@4
vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s <= vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q;
vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest: PROCESS (vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s, en, reg_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q, reg_cStage_uid289_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q)
BEGIN
CASE vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s IS
WHEN "0" => vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= reg_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q;
WHEN "1" => vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= reg_cStage_uid289_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q;
WHEN OTHERS => vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid292_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,291)@4
rVStage_uid292_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q;
rVStage_uid292_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= rVStage_uid292_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(34 downto 27);
--vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(LOGICAL,292)@4
vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a <= rVStage_uid292_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b;
vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q;
vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= "1" when vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a = vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b else "0";
--reg_vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3(REG,626)@4
reg_vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q <= vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStage_uid295_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,294)@4
vStage_uid295_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q(26 downto 0);
vStage_uid295_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= vStage_uid295_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(26 downto 0);
--cStage_uid296_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITJOIN,295)@4
cStage_uid296_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= vStage_uid295_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b & cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q;
--vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(MUX,296)@4
vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s <= vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q;
vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest: PROCESS (vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s, en, vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q, cStage_uid296_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q)
BEGIN
CASE vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s IS
WHEN "0" => vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q;
WHEN "1" => vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= cStage_uid296_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q;
WHEN OTHERS => vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,298)@4
rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q;
rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(34 downto 31);
--reg_rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1(REG,623)@4
reg_rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q <= rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(LOGICAL,299)@5
vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a <= reg_rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q;
vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= rightShiftStage1Idx1Pad4_uid255_fxpX_uid59_acosX_uid8_fpArccosPiTest_q;
vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= "1" when vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a = vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b else "0";
--vStage_uid302_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,301)@4
vStage_uid302_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q(30 downto 0);
vStage_uid302_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= vStage_uid302_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(30 downto 0);
--cStage_uid303_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITJOIN,302)@4
cStage_uid303_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= vStage_uid302_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b & rightShiftStage1Idx1Pad4_uid255_fxpX_uid59_acosX_uid8_fpArccosPiTest_q;
--reg_cStage_uid303_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3(REG,625)@4
reg_cStage_uid303_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cStage_uid303_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cStage_uid303_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q <= cStage_uid303_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2(REG,624)@4
reg_vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q <= vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(MUX,303)@5
vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s <= vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q;
vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest: PROCESS (vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s, en, reg_vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q, reg_cStage_uid303_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q)
BEGIN
CASE vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s IS
WHEN "0" => vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= reg_vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q;
WHEN "1" => vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= reg_cStage_uid303_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q;
WHEN OTHERS => vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid306_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,305)@5
rVStage_uid306_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q;
rVStage_uid306_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= rVStage_uid306_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(34 downto 33);
--vCount_uid307_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(LOGICAL,306)@5
vCount_uid307_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a <= rVStage_uid306_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b;
vCount_uid307_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= rightShiftStage2Idx2Pad2_uid269_fxpX_uid59_acosX_uid8_fpArccosPiTest_q;
vCount_uid307_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= "1" when vCount_uid307_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a = vCount_uid307_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b else "0";
--vStage_uid309_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,308)@5
vStage_uid309_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q(32 downto 0);
vStage_uid309_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= vStage_uid309_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(32 downto 0);
--cStage_uid310_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITJOIN,309)@5
cStage_uid310_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= vStage_uid309_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b & rightShiftStage2Idx2Pad2_uid269_fxpX_uid59_acosX_uid8_fpArccosPiTest_q;
--vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(MUX,310)@5
vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s <= vCount_uid307_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q;
vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest: PROCESS (vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s, en, vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q, cStage_uid310_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q)
BEGIN
CASE vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s IS
WHEN "0" => vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q;
WHEN "1" => vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= cStage_uid310_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q;
WHEN OTHERS => vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid313_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,312)@5
rVStage_uid313_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q;
rVStage_uid313_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= rVStage_uid313_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(34 downto 34);
--vCount_uid314_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(LOGICAL,313)@5
vCount_uid314_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a <= rVStage_uid313_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b;
vCount_uid314_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= GND_q;
vCount_uid314_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= "1" when vCount_uid314_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a = vCount_uid314_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b else "0";
--vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITJOIN,318)@5
vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= ld_vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_f_q & ld_vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_e_q & reg_vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q & vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q & vCount_uid307_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q & vCount_uid314_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q;
--ld_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_c(DELAY,1043)@5
ld_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_c : dspba_delay
GENERIC MAP ( width => 6, depth => 1 )
PORT MAP ( xin => vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q, xout => ld_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1(REG,627)@5
reg_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q <= vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(COMPARE,320)@6
vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_cin <= GND_q;
vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("00" & maxCountVal_uid320_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q) & '0';
vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q) & vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_cin(0);
vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a) - UNSIGNED(vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b));
vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_c(0) <= vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_o(8);
--vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(MUX,322)@6
vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s <= vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_c;
vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s IS
WHEN "0" => vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= ld_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_c_q;
WHEN "1" => vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= maxCountVal_uid320_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q;
WHEN OTHERS => vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--cstBiasM2_uid6_fpArccosPiTest(CONSTANT,5)
cstBiasM2_uid6_fpArccosPiTest_q <= "01111101";
--expL_uid67_acosX_uid8_fpArccosPiTest(SUB,66)@7
expL_uid67_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM2_uid6_fpArccosPiTest_q);
expL_uid67_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("000" & vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q);
expL_uid67_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expL_uid67_acosX_uid8_fpArccosPiTest_a) - UNSIGNED(expL_uid67_acosX_uid8_fpArccosPiTest_b));
expL_uid67_acosX_uid8_fpArccosPiTest_q <= expL_uid67_acosX_uid8_fpArccosPiTest_o(8 downto 0);
--expLRange_uid69_acosX_uid8_fpArccosPiTest(BITSELECT,68)@7
expLRange_uid69_acosX_uid8_fpArccosPiTest_in <= expL_uid67_acosX_uid8_fpArccosPiTest_q(7 downto 0);
expLRange_uid69_acosX_uid8_fpArccosPiTest_b <= expLRange_uid69_acosX_uid8_fpArccosPiTest_in(7 downto 0);
--vStage_uid316_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,315)@5
vStage_uid316_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q(33 downto 0);
vStage_uid316_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= vStage_uid316_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(33 downto 0);
--cStage_uid317_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITJOIN,316)@5
cStage_uid317_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= vStage_uid316_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b & GND_q;
--vStagei_uid318_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(MUX,317)@5
vStagei_uid318_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s <= vCount_uid314_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q;
vStagei_uid318_fpLOut1_uid66_acosX_uid8_fpArccosPiTest: PROCESS (vStagei_uid318_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s, en, vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q, cStage_uid317_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q)
BEGIN
CASE vStagei_uid318_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s IS
WHEN "0" => vStagei_uid318_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q;
WHEN "1" => vStagei_uid318_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= cStage_uid317_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q;
WHEN OTHERS => vStagei_uid318_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest(BITSELECT,67)@5
fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_in <= vStagei_uid318_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q(33 downto 0);
fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_b <= fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_in(33 downto 11);
--ld_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_b_to_reg_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_0_to_fpL_uid70_acosX_uid8_fpArccosPiTest_0_a(DELAY,1359)@5
ld_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_b_to_reg_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_0_to_fpL_uid70_acosX_uid8_fpArccosPiTest_0_a : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_b, xout => ld_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_b_to_reg_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_0_to_fpL_uid70_acosX_uid8_fpArccosPiTest_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_0_to_fpL_uid70_acosX_uid8_fpArccosPiTest_0(REG,628)@6
reg_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_0_to_fpL_uid70_acosX_uid8_fpArccosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_0_to_fpL_uid70_acosX_uid8_fpArccosPiTest_0_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_0_to_fpL_uid70_acosX_uid8_fpArccosPiTest_0_q <= ld_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_b_to_reg_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_0_to_fpL_uid70_acosX_uid8_fpArccosPiTest_0_a_q;
END IF;
END IF;
END PROCESS;
--fpL_uid70_acosX_uid8_fpArccosPiTest(BITJOIN,69)@7
fpL_uid70_acosX_uid8_fpArccosPiTest_q <= GND_q & expLRange_uid69_acosX_uid8_fpArccosPiTest_b & reg_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_0_to_fpL_uid70_acosX_uid8_fpArccosPiTest_0_q;
--signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITSELECT,327)@7
signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in <= fpL_uid70_acosX_uid8_fpArccosPiTest_q;
signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in(31 downto 31);
--expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITSELECT,325)@7
expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in <= fpL_uid70_acosX_uid8_fpArccosPiTest_q(30 downto 0);
expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in(30 downto 23);
--expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,332)@7
expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b;
expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q;
expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "1" when expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a = expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b else "0";
--negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,375)@7
negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q;
negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b;
negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a and negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b;
END IF;
END PROCESS;
--ld_negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_c(DELAY,1099)@8
ld_negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q, xout => ld_negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_nor(LOGICAL,1499)
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q;
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_nor_b <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_sticky_ena_q;
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_nor_q <= not (ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_nor_a or ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_nor_b);
--ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_mem_top(CONSTANT,1495)
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_mem_top_q <= "0110";
--ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmp(LOGICAL,1496)
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmp_a <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_mem_top_q;
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q);
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmp_q <= "1" when ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmp_a = ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmp_b else "0";
--ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmpReg(REG,1497)
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmpReg_q <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_sticky_ena(REG,1500)
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_nor_q = "1") THEN
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_sticky_ena_q <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_enaAnd(LOGICAL,1501)
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_enaAnd_a <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_sticky_ena_q;
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_enaAnd_b <= en;
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_enaAnd_q <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_enaAnd_a and ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_enaAnd_b;
--cstBiasM1_uid23_acosX_uid8_fpArccosPiTest(CONSTANT,22)
cstBiasM1_uid23_acosX_uid8_fpArccosPiTest_q <= "01111110";
--reg_expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0(REG,638)@7
reg_expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_q <= expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b;
END IF;
END IF;
END PROCESS;
--expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(ADD,348)@8
expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_q);
expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_acosX_uid8_fpArccosPiTest_q);
expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a) + UNSIGNED(expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b));
expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_o(8 downto 0);
--expROdd_uid350_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITSELECT,349)@8
expROdd_uid350_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in <= expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q;
expROdd_uid350_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= expROdd_uid350_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in(8 downto 1);
--expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(ADD,345)@8
expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_q);
expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid22_acosX_uid8_fpArccosPiTest_q);
expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a) + UNSIGNED(expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b));
expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_o(8 downto 0);
--expREven_uid347_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITSELECT,346)@8
expREven_uid347_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in <= expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q;
expREven_uid347_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= expREven_uid347_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in(8 downto 1);
--expX0_uid351_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITSELECT,350)@7
expX0_uid351_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in <= expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b(0 downto 0);
expX0_uid351_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= expX0_uid351_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in(0 downto 0);
--expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,351)@7
expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= expX0_uid351_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b;
expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= not expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a;
--ld_expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b(DELAY,1067)@7
ld_expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q, xout => ld_expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(MUX,352)@8
expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_s <= ld_expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q;
expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_s IS
WHEN "0" => expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= expREven_uid347_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b;
WHEN "1" => expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= expROdd_uid350_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b;
WHEN OTHERS => expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b(DELAY,1079)@7
ld_signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b, xout => ld_signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid341_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,340)@8
InvExc_N_uid341_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= exc_N_uid340_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q;
InvExc_N_uid341_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= not InvExc_N_uid341_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a;
--fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITSELECT,326)@7
fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in <= fpL_uid70_acosX_uid8_fpArccosPiTest_q(22 downto 0);
fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in(22 downto 0);
--reg_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_1(REG,629)@7
reg_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_1_q <= fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,336)@8
fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= reg_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_1_q;
fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q;
fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "1" when fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a = fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b else "0";
--expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,334)@7
expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b;
expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q;
expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
IF (expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a = expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b) THEN
expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "1";
ELSE
expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "0";
END IF;
END IF;
END PROCESS;
--exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,337)@8
exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q;
exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q;
exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a and exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b;
--InvExc_I_uid342_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,341)@8
InvExc_I_uid342_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q;
InvExc_I_uid342_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= not InvExc_I_uid342_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a;
--InvExpXIsZero_uid343_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,342)@7
InvExpXIsZero_uid343_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q;
InvExpXIsZero_uid343_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExpXIsZero_uid343_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExpXIsZero_uid343_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= not InvExpXIsZero_uid343_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a;
END IF;
END PROCESS;
--exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,343)@8
exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= InvExpXIsZero_uid343_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q;
exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= InvExc_I_uid342_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q;
exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_c <= InvExc_N_uid341_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q;
exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a and exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b and exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_c;
--minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,361)@8
minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q;
minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= ld_signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q;
minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a and minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b;
--minInf_uid363_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,362)@8
minInf_uid363_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q;
minInf_uid363_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= ld_signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q;
minInf_uid363_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= minInf_uid363_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a and minInf_uid363_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b;
--InvFracXIsZero_uid339_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,338)@8
InvFracXIsZero_uid339_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q;
InvFracXIsZero_uid339_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= not InvFracXIsZero_uid339_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a;
--exc_N_uid340_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,339)@8
exc_N_uid340_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q;
exc_N_uid340_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= InvFracXIsZero_uid339_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q;
exc_N_uid340_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= exc_N_uid340_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a and exc_N_uid340_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b;
--excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,363)@8
excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= exc_N_uid340_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q;
excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= minInf_uid363_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q;
excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_c <= minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q;
excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a or excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b or excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_c;
--InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,359)@7
InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b;
InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= not InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a;
--ld_InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b(DELAY,1077)@7
ld_InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q, xout => ld_InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,360)@8
inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q;
inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= ld_InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q;
inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a and inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b;
--ld_expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_join_uid365_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a(DELAY,1085)@7
ld_expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_join_uid365_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q, xout => ld_expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_join_uid365_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--join_uid365_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITJOIN,364)@8
join_uid365_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q & inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q & ld_expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_join_uid365_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a_q;
--fracSelIn_uid366_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITJOIN,365)@8
fracSelIn_uid366_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= ld_signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q & join_uid365_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q;
--reg_fracSelIn_uid366_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0(REG,630)@8
reg_fracSelIn_uid366_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracSelIn_uid366_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracSelIn_uid366_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_q <= fracSelIn_uid366_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOOKUP,366)@9
fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest: PROCESS (reg_fracSelIn_uid366_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_fracSelIn_uid366_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_q) IS
WHEN "0000" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "01";
WHEN "0001" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "00";
WHEN "0010" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "10";
WHEN "0011" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "00";
WHEN "0100" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "11";
WHEN "0101" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "00";
WHEN "0110" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "10";
WHEN "0111" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "00";
WHEN "1000" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "11";
WHEN "1001" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "00";
WHEN "1010" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "11";
WHEN "1011" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "11";
WHEN "1100" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "11";
WHEN "1101" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "11";
WHEN "1110" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "11";
WHEN "1111" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "11";
WHEN OTHERS =>
fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(MUX,370)@9
expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_s <= fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q;
expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest: PROCESS (expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_s, en, cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q, expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q, cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q, cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q)
BEGIN
CASE expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_s IS
WHEN "00" => expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q;
WHEN "01" => expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q;
WHEN "10" => expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q;
WHEN "11" => expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q;
WHEN OTHERS => expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_inputreg(DELAY,1489)
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q, xout => ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt(COUNTER,1491)
-- every=1, low=0, high=6, step=1, init=1
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i = 5 THEN
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i - 6;
ELSE
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdreg(REG,1492)
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux(MUX,1493)
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux_s, ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q, ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem(DUALMEM,1490)
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_ia <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_inputreg_q;
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_aa <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q;
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_ab <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q;
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 7,
width_b => 8,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_ia
);
ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_q <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid20_acosX_uid8_fpArccosPiTest(CONSTANT,19)
cstNaNWF_uid20_acosX_uid8_fpArccosPiTest_q <= "00000000000000000000001";
--fracXAddr_uid355_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITSELECT,354)@7
fracXAddr_uid355_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in <= fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b;
fracXAddr_uid355_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= fracXAddr_uid355_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in(22 downto 16);
--addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITJOIN,355)@7
addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q & fracXAddr_uid355_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b;
--reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid568_sqrtTableGenerator_lutmem_0(REG,631)@7
reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid568_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid568_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid568_sqrtTableGenerator_lutmem_0_q <= addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid568_sqrtTableGenerator_lutmem(DUALMEM,607)@8
memoryC2_uid568_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC2_uid568_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC2_uid568_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC2_uid568_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid568_sqrtTableGenerator_lutmem_0_q;
memoryC2_uid568_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccospi_s5_memoryC2_uid568_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid568_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid568_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid568_sqrtTableGenerator_lutmem_iq,
address_a => memoryC2_uid568_sqrtTableGenerator_lutmem_aa,
data_a => memoryC2_uid568_sqrtTableGenerator_lutmem_ia
);
memoryC2_uid568_sqrtTableGenerator_lutmem_q <= memoryC2_uid568_sqrtTableGenerator_lutmem_iq(11 downto 0);
--reg_memoryC2_uid568_sqrtTableGenerator_lutmem_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_1(REG,633)@10
reg_memoryC2_uid568_sqrtTableGenerator_lutmem_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid568_sqrtTableGenerator_lutmem_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid568_sqrtTableGenerator_lutmem_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_1_q <= memoryC2_uid568_sqrtTableGenerator_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a_inputreg(DELAY,1488)
ld_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b, xout => ld_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a(DELAY,1073)@7
ld_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a_inputreg_q, xout => ld_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITSELECT,356)@10
FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in <= ld_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a_q(15 downto 0);
FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in(15 downto 0);
--yT1_uid569_sqrtPolynomialEvaluator(BITSELECT,568)@10
yT1_uid569_sqrtPolynomialEvaluator_in <= FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b;
yT1_uid569_sqrtPolynomialEvaluator_b <= yT1_uid569_sqrtPolynomialEvaluator_in(15 downto 4);
--reg_yT1_uid569_sqrtPolynomialEvaluator_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_0(REG,632)@10
reg_yT1_uid569_sqrtPolynomialEvaluator_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid569_sqrtPolynomialEvaluator_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid569_sqrtPolynomialEvaluator_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_0_q <= yT1_uid569_sqrtPolynomialEvaluator_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator(MULT,593)@11
prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_a),13)) * SIGNED(prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_b);
prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_a <= reg_yT1_uid569_sqrtPolynomialEvaluator_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_0_q;
prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_b <= reg_memoryC2_uid568_sqrtTableGenerator_lutmem_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_1_q;
prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_q <= prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid595_pT1_uid570_sqrtPolynomialEvaluator(BITSELECT,594)@14
prodXYTruncFR_uid595_pT1_uid570_sqrtPolynomialEvaluator_in <= prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid595_pT1_uid570_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid595_pT1_uid570_sqrtPolynomialEvaluator_in(23 downto 11);
--highBBits_uid572_sqrtPolynomialEvaluator(BITSELECT,571)@14
highBBits_uid572_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid595_pT1_uid570_sqrtPolynomialEvaluator_b;
highBBits_uid572_sqrtPolynomialEvaluator_b <= highBBits_uid572_sqrtPolynomialEvaluator_in(12 downto 1);
--ld_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid567_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid567_sqrtTableGenerator_lutmem_a(DELAY,1337)@8
ld_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid567_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid567_sqrtTableGenerator_lutmem_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid568_sqrtTableGenerator_lutmem_0_q, xout => ld_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid567_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid567_sqrtTableGenerator_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid567_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid567_sqrtTableGenerator_lutmem_a_outputreg(DELAY,1551)
ld_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid567_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid567_sqrtTableGenerator_lutmem_a_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid567_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid567_sqrtTableGenerator_lutmem_a_q, xout => ld_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid567_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid567_sqrtTableGenerator_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid567_sqrtTableGenerator_lutmem(DUALMEM,606)@12
memoryC1_uid567_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC1_uid567_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC1_uid567_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC1_uid567_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid567_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid567_sqrtTableGenerator_lutmem_a_outputreg_q;
memoryC1_uid567_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccospi_s5_memoryC1_uid567_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid567_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid567_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid567_sqrtTableGenerator_lutmem_iq,
address_a => memoryC1_uid567_sqrtTableGenerator_lutmem_aa,
data_a => memoryC1_uid567_sqrtTableGenerator_lutmem_ia
);
memoryC1_uid567_sqrtTableGenerator_lutmem_q <= memoryC1_uid567_sqrtTableGenerator_lutmem_iq(20 downto 0);
--sumAHighB_uid573_sqrtPolynomialEvaluator(ADD,572)@14
sumAHighB_uid573_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid567_sqrtTableGenerator_lutmem_q(20)) & memoryC1_uid567_sqrtTableGenerator_lutmem_q);
sumAHighB_uid573_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid572_sqrtPolynomialEvaluator_b(11)) & highBBits_uid572_sqrtPolynomialEvaluator_b);
sumAHighB_uid573_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid573_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid573_sqrtPolynomialEvaluator_b));
sumAHighB_uid573_sqrtPolynomialEvaluator_q <= sumAHighB_uid573_sqrtPolynomialEvaluator_o(21 downto 0);
--lowRangeB_uid571_sqrtPolynomialEvaluator(BITSELECT,570)@14
lowRangeB_uid571_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid595_pT1_uid570_sqrtPolynomialEvaluator_b(0 downto 0);
lowRangeB_uid571_sqrtPolynomialEvaluator_b <= lowRangeB_uid571_sqrtPolynomialEvaluator_in(0 downto 0);
--s1_uid571_uid574_sqrtPolynomialEvaluator(BITJOIN,573)@14
s1_uid571_uid574_sqrtPolynomialEvaluator_q <= sumAHighB_uid573_sqrtPolynomialEvaluator_q & lowRangeB_uid571_sqrtPolynomialEvaluator_b;
--reg_s1_uid571_uid574_sqrtPolynomialEvaluator_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_1(REG,636)@14
reg_s1_uid571_uid574_sqrtPolynomialEvaluator_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid571_uid574_sqrtPolynomialEvaluator_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid571_uid574_sqrtPolynomialEvaluator_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_1_q <= s1_uid571_uid574_sqrtPolynomialEvaluator_q;
END IF;
END IF;
END PROCESS;
--ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_nor(LOGICAL,1560)
ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q;
ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_nor_b <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_sticky_ena_q;
ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_nor_q <= not (ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_nor_a or ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_nor_b);
--ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_cmpReg(REG,1558)
ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_sticky_ena(REG,1561)
ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_nor_q = "1") THEN
ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_enaAnd(LOGICAL,1562)
ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_enaAnd_a <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_sticky_ena_q;
ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_enaAnd_b <= en;
ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_enaAnd_q <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_enaAnd_a and ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_enaAnd_b;
--ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_inputreg(DELAY,1552)
ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b, xout => ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt(COUNTER,1554)
-- every=1, low=0, high=1, step=1, init=1
ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i,1));
--ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdreg(REG,1555)
ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux(MUX,1556)
ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux_s <= en;
ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux: PROCESS (ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux_s, ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdreg_q, ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q)
BEGIN
CASE ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux_s IS
WHEN "0" => ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdreg_q;
WHEN "1" => ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem(DUALMEM,1553)
ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 <= areset;
ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_ia <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_inputreg_q;
ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_aa <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdreg_q;
ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_ab <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux_q;
ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 16,
widthad_a => 1,
numwords_a => 2,
width_b => 16,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_iq,
address_a => ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_aa,
data_a => ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_ia
);
ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_q <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_iq(15 downto 0);
--reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0(REG,635)@14
reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_q <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator(MULT,596)@15
prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_a),17)) * SIGNED(prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_b);
prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_a <= (others => '0');
prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_b <= (others => '0');
prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_a <= reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_q;
prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_b <= reg_s1_uid571_uid574_sqrtPolynomialEvaluator_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_1_q;
prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_pr,39));
END IF;
END IF;
END PROCESS;
prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_q <= prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid598_pT2_uid576_sqrtPolynomialEvaluator(BITSELECT,597)@18
prodXYTruncFR_uid598_pT2_uid576_sqrtPolynomialEvaluator_in <= prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_q;
prodXYTruncFR_uid598_pT2_uid576_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid598_pT2_uid576_sqrtPolynomialEvaluator_in(38 downto 15);
--highBBits_uid578_sqrtPolynomialEvaluator(BITSELECT,577)@18
highBBits_uid578_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid598_pT2_uid576_sqrtPolynomialEvaluator_b;
highBBits_uid578_sqrtPolynomialEvaluator_b <= highBBits_uid578_sqrtPolynomialEvaluator_in(23 downto 2);
--ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,1573)
ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q;
ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_sticky_ena_q;
ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_nor_b);
--ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,1574)
ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN
ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,1575)
ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_sticky_ena_q;
ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en;
ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_enaAnd_b;
--ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_inputreg(DELAY,1563)
ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q, xout => ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,1564)
ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_inputreg_q;
ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdreg_q;
ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_q;
ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_iq,
address_a => ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_aa,
data_a => ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_ia
);
ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0(REG,637)@15
reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid566_sqrtTableGenerator_lutmem(DUALMEM,605)@16
memoryC0_uid566_sqrtTableGenerator_lutmem_reset0 <= areset;
memoryC0_uid566_sqrtTableGenerator_lutmem_ia <= (others => '0');
memoryC0_uid566_sqrtTableGenerator_lutmem_aa <= (others => '0');
memoryC0_uid566_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_q;
memoryC0_uid566_sqrtTableGenerator_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 29,
widthad_a => 8,
numwords_a => 256,
width_b => 29,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccospi_s5_memoryC0_uid566_sqrtTableGenerator_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid566_sqrtTableGenerator_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid566_sqrtTableGenerator_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid566_sqrtTableGenerator_lutmem_iq,
address_a => memoryC0_uid566_sqrtTableGenerator_lutmem_aa,
data_a => memoryC0_uid566_sqrtTableGenerator_lutmem_ia
);
memoryC0_uid566_sqrtTableGenerator_lutmem_q <= memoryC0_uid566_sqrtTableGenerator_lutmem_iq(28 downto 0);
--sumAHighB_uid579_sqrtPolynomialEvaluator(ADD,578)@18
sumAHighB_uid579_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid566_sqrtTableGenerator_lutmem_q(28)) & memoryC0_uid566_sqrtTableGenerator_lutmem_q);
sumAHighB_uid579_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid578_sqrtPolynomialEvaluator_b(21)) & highBBits_uid578_sqrtPolynomialEvaluator_b);
sumAHighB_uid579_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid579_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid579_sqrtPolynomialEvaluator_b));
sumAHighB_uid579_sqrtPolynomialEvaluator_q <= sumAHighB_uid579_sqrtPolynomialEvaluator_o(29 downto 0);
--lowRangeB_uid577_sqrtPolynomialEvaluator(BITSELECT,576)@18
lowRangeB_uid577_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid598_pT2_uid576_sqrtPolynomialEvaluator_b(1 downto 0);
lowRangeB_uid577_sqrtPolynomialEvaluator_b <= lowRangeB_uid577_sqrtPolynomialEvaluator_in(1 downto 0);
--s2_uid577_uid580_sqrtPolynomialEvaluator(BITJOIN,579)@18
s2_uid577_uid580_sqrtPolynomialEvaluator_q <= sumAHighB_uid579_sqrtPolynomialEvaluator_q & lowRangeB_uid577_sqrtPolynomialEvaluator_b;
--fracR_uid359_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITSELECT,358)@18
fracR_uid359_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in <= s2_uid577_uid580_sqrtPolynomialEvaluator_q(28 downto 0);
fracR_uid359_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= fracR_uid359_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in(28 downto 6);
--ld_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b(DELAY,1093)@9
ld_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 9 )
PORT MAP ( xin => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q, xout => ld_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(MUX,374)@18
fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_s <= ld_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q;
fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest: PROCESS (fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_s, en, cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q, fracR_uid359_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b, cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q, cstNaNWF_uid20_acosX_uid8_fpArccosPiTest_q)
BEGIN
CASE fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_s IS
WHEN "00" => fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q;
WHEN "01" => fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= fracR_uid359_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b;
WHEN "10" => fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q;
WHEN "11" => fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= cstNaNWF_uid20_acosX_uid8_fpArccosPiTest_q;
WHEN OTHERS => fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITJOIN,376)@18
RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= ld_negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_c_q & ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_q & fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q;
--SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest(BITSELECT,72)@18
SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_in <= RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q(22 downto 0);
SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_b <= SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_in(22 downto 0);
--reg_SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1(REG,662)@18
reg_SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,437)@19
fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= reg_SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q;
fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q;
fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "1" when fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a = fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b else "0";
--ld_fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b(DELAY,1149)@19
ld_fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest(BITSELECT,74)@18
SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_in <= RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q(30 downto 0);
SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_b <= SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_in(30 downto 23);
--reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1(REG,640)@18
reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_b;
END IF;
END IF;
END PROCESS;
--expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,435)@19
expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q;
expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q;
expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "1" when expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a = expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b else "0";
--ld_expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1148)@19
ld_expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,438)@31
exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q;
exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= ld_fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q;
exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b;
--reg_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2(REG,675)@31
reg_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q <= exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage123dto1_uid400_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITSELECT,399)@20
RightShiftStage123dto1_uid400_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in <= rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q;
RightShiftStage123dto1_uid400_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b <= RightShiftStage123dto1_uid400_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in(23 downto 1);
--rightShiftStage2Idx1_uid402_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITJOIN,401)@20
rightShiftStage2Idx1_uid402_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= GND_q & RightShiftStage123dto1_uid400_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b;
--oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest(BITJOIN,73)@18
oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_q <= VCC_q & SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_b;
--X23dto16_uid383_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITSELECT,382)@18
X23dto16_uid383_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in <= oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_q;
X23dto16_uid383_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b <= X23dto16_uid383_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in(23 downto 16);
--rightShiftStage0Idx2_uid385_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITJOIN,384)@18
rightShiftStage0Idx2_uid385_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= rightShiftStage0Idx1Pad16_uid246_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & X23dto16_uid383_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b;
--reg_rightShiftStage0Idx2_uid385_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4(REG,644)@18
reg_rightShiftStage0Idx2_uid385_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid385_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid385_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4_q <= rightShiftStage0Idx2_uid385_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--X23dto8_uid380_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITSELECT,379)@18
X23dto8_uid380_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in <= oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_q;
X23dto8_uid380_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b <= X23dto8_uid380_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in(23 downto 8);
--rightShiftStage0Idx1_uid382_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITJOIN,381)@18
rightShiftStage0Idx1_uid382_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q & X23dto8_uid380_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b;
--reg_rightShiftStage0Idx1_uid382_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3(REG,643)@18
reg_rightShiftStage0Idx1_uid382_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid382_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid382_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3_q <= rightShiftStage0Idx1_uid382_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2(REG,642)@18
reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2_q <= oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--srVal_uid76_acosX_uid8_fpArccosPiTest(SUB,75)@19
srVal_uid76_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_acosX_uid8_fpArccosPiTest_q);
srVal_uid76_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("0" & reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q);
srVal_uid76_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(srVal_uid76_acosX_uid8_fpArccosPiTest_a) - UNSIGNED(srVal_uid76_acosX_uid8_fpArccosPiTest_b));
srVal_uid76_acosX_uid8_fpArccosPiTest_q <= srVal_uid76_acosX_uid8_fpArccosPiTest_o(8 downto 0);
--srValRange_uid77_acosX_uid8_fpArccosPiTest(BITSELECT,76)@19
srValRange_uid77_acosX_uid8_fpArccosPiTest_in <= srVal_uid76_acosX_uid8_fpArccosPiTest_q(4 downto 0);
srValRange_uid77_acosX_uid8_fpArccosPiTest_b <= srValRange_uid77_acosX_uid8_fpArccosPiTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid387_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITSELECT,386)@19
rightShiftStageSel4Dto3_uid387_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in <= srValRange_uid77_acosX_uid8_fpArccosPiTest_b;
rightShiftStageSel4Dto3_uid387_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b <= rightShiftStageSel4Dto3_uid387_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in(4 downto 3);
--rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(MUX,387)@19
rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s <= rightShiftStageSel4Dto3_uid387_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b;
rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest: PROCESS (rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s, en, reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2_q, reg_rightShiftStage0Idx1_uid382_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3_q, reg_rightShiftStage0Idx2_uid385_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4_q, rightShiftStage0Idx3_uid386_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q)
BEGIN
CASE rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s IS
WHEN "00" => rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2_q;
WHEN "01" => rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage0Idx1_uid382_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3_q;
WHEN "10" => rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage0Idx2_uid385_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4_q;
WHEN "11" => rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= rightShiftStage0Idx3_uid386_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q;
WHEN OTHERS => rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--RightShiftStage023dto6_uid395_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITSELECT,394)@19
RightShiftStage023dto6_uid395_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in <= rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q;
RightShiftStage023dto6_uid395_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b <= RightShiftStage023dto6_uid395_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in(23 downto 6);
--rightShiftStage1Idx3_uid397_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITJOIN,396)@19
rightShiftStage1Idx3_uid397_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1Idx3Pad6_uid396_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q & RightShiftStage023dto6_uid395_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b;
--reg_rightShiftStage1Idx3_uid397_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_5(REG,649)@19
reg_rightShiftStage1Idx3_uid397_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx3_uid397_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_5_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx3_uid397_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_5_q <= rightShiftStage1Idx3_uid397_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage023dto4_uid392_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITSELECT,391)@19
RightShiftStage023dto4_uid392_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in <= rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q;
RightShiftStage023dto4_uid392_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b <= RightShiftStage023dto4_uid392_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in(23 downto 4);
--rightShiftStage1Idx2_uid394_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITJOIN,393)@19
rightShiftStage1Idx2_uid394_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1Idx1Pad4_uid255_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & RightShiftStage023dto4_uid392_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b;
--reg_rightShiftStage1Idx2_uid394_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4(REG,648)@19
reg_rightShiftStage1Idx2_uid394_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx2_uid394_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx2_uid394_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4_q <= rightShiftStage1Idx2_uid394_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--RightShiftStage023dto2_uid389_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITSELECT,388)@19
RightShiftStage023dto2_uid389_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in <= rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q;
RightShiftStage023dto2_uid389_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b <= RightShiftStage023dto2_uid389_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in(23 downto 2);
--rightShiftStage1Idx1_uid391_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITJOIN,390)@19
rightShiftStage1Idx1_uid391_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= rightShiftStage2Idx2Pad2_uid269_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & RightShiftStage023dto2_uid389_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b;
--reg_rightShiftStage1Idx1_uid391_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3(REG,647)@19
reg_rightShiftStage1Idx1_uid391_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage1Idx1_uid391_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage1Idx1_uid391_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3_q <= rightShiftStage1Idx1_uid391_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2(REG,646)@19
reg_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2_q <= rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITSELECT,397)@19
rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in <= srValRange_uid77_acosX_uid8_fpArccosPiTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b <= rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1(REG,645)@19
reg_rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1_q <= rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(MUX,398)@20
rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s <= reg_rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1_q;
rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest: PROCESS (rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s, en, reg_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2_q, reg_rightShiftStage1Idx1_uid391_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3_q, reg_rightShiftStage1Idx2_uid394_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4_q, reg_rightShiftStage1Idx3_uid397_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_5_q)
BEGIN
CASE rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s IS
WHEN "00" => rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2_q;
WHEN "01" => rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage1Idx1_uid391_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3_q;
WHEN "10" => rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage1Idx2_uid394_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4_q;
WHEN "11" => rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage1Idx3_uid397_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_5_q;
WHEN OTHERS => rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITSELECT,402)@19
rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in <= srValRange_uid77_acosX_uid8_fpArccosPiTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b <= rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1(REG,650)@19
reg_rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1_q <= rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(MUX,403)@20
rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s <= reg_rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1_q;
rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest: PROCESS (rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s, en, rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q, rightShiftStage2Idx1_uid402_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q)
BEGIN
CASE rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s IS
WHEN "0" => rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q;
WHEN "1" => rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= rightShiftStage2Idx1_uid402_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q;
WHEN OTHERS => rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--sAddr_uid80_acosX_uid8_fpArccosPiTest(BITSELECT,79)@20
sAddr_uid80_acosX_uid8_fpArccosPiTest_in <= rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q;
sAddr_uid80_acosX_uid8_fpArccosPiTest_b <= sAddr_uid80_acosX_uid8_fpArccosPiTest_in(23 downto 16);
--reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0(REG,651)@20
reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0_q <= sAddr_uid80_acosX_uid8_fpArccosPiTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid408_arcsinXO2XTabGen_lutmem(DUALMEM,601)@21
memoryC2_uid408_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC2_uid408_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC2_uid408_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC2_uid408_arcsinXO2XTabGen_lutmem_ab <= reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0_q;
memoryC2_uid408_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 8,
numwords_a => 256,
width_b => 12,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccospi_s5_memoryC2_uid408_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid408_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid408_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid408_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC2_uid408_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC2_uid408_arcsinXO2XTabGen_lutmem_ia
);
memoryC2_uid408_arcsinXO2XTabGen_lutmem_q <= memoryC2_uid408_arcsinXO2XTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_1(REG,653)@23
reg_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_1_q <= memoryC2_uid408_arcsinXO2XTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q_to_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_a_inputreg(DELAY,1448)
ld_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q_to_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 24, depth => 1 )
PORT MAP ( xin => rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q, xout => ld_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q_to_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q_to_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_a(DELAY,768)@20
ld_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q_to_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_a : dspba_delay
GENERIC MAP ( width => 24, depth => 2 )
PORT MAP ( xin => ld_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q_to_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_a_inputreg_q, xout => ld_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q_to_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--sPPolyEval_uid81_acosX_uid8_fpArccosPiTest(BITSELECT,80)@23
sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_in <= ld_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q_to_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_a_q(15 downto 0);
sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b <= sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_in(15 downto 1);
--yT1_uid409_arcsinXO2XPolyEval(BITSELECT,408)@23
yT1_uid409_arcsinXO2XPolyEval_in <= sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b;
yT1_uid409_arcsinXO2XPolyEval_b <= yT1_uid409_arcsinXO2XPolyEval_in(14 downto 3);
--reg_yT1_uid409_arcsinXO2XPolyEval_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_0(REG,652)@23
reg_yT1_uid409_arcsinXO2XPolyEval_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid409_arcsinXO2XPolyEval_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid409_arcsinXO2XPolyEval_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_0_q <= yT1_uid409_arcsinXO2XPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval(MULT,581)@24
prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_a),13)) * SIGNED(prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_b);
prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_a <= (others => '0');
prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_b <= (others => '0');
prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_a <= reg_yT1_uid409_arcsinXO2XPolyEval_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_0_q;
prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_b <= reg_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_1_q;
prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_q <= prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid583_pT1_uid410_arcsinXO2XPolyEval(BITSELECT,582)@27
prodXYTruncFR_uid583_pT1_uid410_arcsinXO2XPolyEval_in <= prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_q;
prodXYTruncFR_uid583_pT1_uid410_arcsinXO2XPolyEval_b <= prodXYTruncFR_uid583_pT1_uid410_arcsinXO2XPolyEval_in(23 downto 11);
--highBBits_uid412_arcsinXO2XPolyEval(BITSELECT,411)@27
highBBits_uid412_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid583_pT1_uid410_arcsinXO2XPolyEval_b;
highBBits_uid412_arcsinXO2XPolyEval_b <= highBBits_uid412_arcsinXO2XPolyEval_in(12 downto 1);
--ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_a_inputreg(DELAY,1576)
ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => sAddr_uid80_acosX_uid8_fpArccosPiTest_b, xout => ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_a(DELAY,1385)@20
ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_a_inputreg_q, xout => ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0(REG,654)@24
reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_q <= ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid407_arcsinXO2XTabGen_lutmem(DUALMEM,600)@25
memoryC1_uid407_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC1_uid407_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC1_uid407_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC1_uid407_arcsinXO2XTabGen_lutmem_ab <= reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_q;
memoryC1_uid407_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 19,
widthad_a => 8,
numwords_a => 256,
width_b => 19,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccospi_s5_memoryC1_uid407_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid407_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid407_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid407_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC1_uid407_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC1_uid407_arcsinXO2XTabGen_lutmem_ia
);
memoryC1_uid407_arcsinXO2XTabGen_lutmem_q <= memoryC1_uid407_arcsinXO2XTabGen_lutmem_iq(18 downto 0);
--sumAHighB_uid413_arcsinXO2XPolyEval(ADD,412)@27
sumAHighB_uid413_arcsinXO2XPolyEval_a <= STD_LOGIC_VECTOR((19 downto 19 => memoryC1_uid407_arcsinXO2XTabGen_lutmem_q(18)) & memoryC1_uid407_arcsinXO2XTabGen_lutmem_q);
sumAHighB_uid413_arcsinXO2XPolyEval_b <= STD_LOGIC_VECTOR((19 downto 12 => highBBits_uid412_arcsinXO2XPolyEval_b(11)) & highBBits_uid412_arcsinXO2XPolyEval_b);
sumAHighB_uid413_arcsinXO2XPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid413_arcsinXO2XPolyEval_a) + SIGNED(sumAHighB_uid413_arcsinXO2XPolyEval_b));
sumAHighB_uid413_arcsinXO2XPolyEval_q <= sumAHighB_uid413_arcsinXO2XPolyEval_o(19 downto 0);
--lowRangeB_uid411_arcsinXO2XPolyEval(BITSELECT,410)@27
lowRangeB_uid411_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid583_pT1_uid410_arcsinXO2XPolyEval_b(0 downto 0);
lowRangeB_uid411_arcsinXO2XPolyEval_b <= lowRangeB_uid411_arcsinXO2XPolyEval_in(0 downto 0);
--s1_uid411_uid414_arcsinXO2XPolyEval(BITJOIN,413)@27
s1_uid411_uid414_arcsinXO2XPolyEval_q <= sumAHighB_uid413_arcsinXO2XPolyEval_q & lowRangeB_uid411_arcsinXO2XPolyEval_b;
--reg_s1_uid411_uid414_arcsinXO2XPolyEval_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_1(REG,656)@27
reg_s1_uid411_uid414_arcsinXO2XPolyEval_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid411_uid414_arcsinXO2XPolyEval_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_1_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid411_uid414_arcsinXO2XPolyEval_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_1_q <= s1_uid411_uid414_arcsinXO2XPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_nor(LOGICAL,1585)
ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q;
ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_nor_b <= ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_sticky_ena_q;
ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_nor_q <= not (ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_nor_a or ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_nor_b);
--ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_sticky_ena(REG,1586)
ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_nor_q = "1") THEN
ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_sticky_ena_q <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_enaAnd(LOGICAL,1587)
ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_enaAnd_a <= ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_sticky_ena_q;
ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_enaAnd_b <= en;
ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_enaAnd_q <= ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_enaAnd_a and ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_enaAnd_b;
--ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_inputreg(DELAY,1577)
ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b, xout => ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem(DUALMEM,1578)
ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_reset0 <= areset;
ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_ia <= ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_inputreg_q;
ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_aa <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdreg_q;
ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_ab <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux_q;
ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_iq,
address_a => ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_aa,
data_a => ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_ia
);
ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_q <= ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0(REG,655)@27
reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_q <= ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval(MULT,584)@28
prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_a),16)) * SIGNED(prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_b);
prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_a <= (others => '0');
prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_b <= (others => '0');
prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_a <= reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_q;
prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_b <= reg_s1_uid411_uid414_arcsinXO2XPolyEval_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_1_q;
prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_pr,36));
END IF;
END IF;
END PROCESS;
prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_q <= prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid586_pT2_uid416_arcsinXO2XPolyEval(BITSELECT,585)@31
prodXYTruncFR_uid586_pT2_uid416_arcsinXO2XPolyEval_in <= prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_q;
prodXYTruncFR_uid586_pT2_uid416_arcsinXO2XPolyEval_b <= prodXYTruncFR_uid586_pT2_uid416_arcsinXO2XPolyEval_in(35 downto 14);
--highBBits_uid418_arcsinXO2XPolyEval(BITSELECT,417)@31
highBBits_uid418_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid586_pT2_uid416_arcsinXO2XPolyEval_b;
highBBits_uid418_arcsinXO2XPolyEval_b <= highBBits_uid418_arcsinXO2XPolyEval_in(21 downto 2);
--ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_nor(LOGICAL,1598)
ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q;
ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_nor_b <= ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q;
ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_nor_q <= not (ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_nor_a or ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_nor_b);
--ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_sticky_ena(REG,1599)
ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_nor_q = "1") THEN
ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_enaAnd(LOGICAL,1600)
ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a <= ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q;
ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b <= en;
ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q <= ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a and ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b;
--ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem(DUALMEM,1589)
ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0 <= areset;
ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia <= ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_a_inputreg_q;
ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdreg_q;
ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_q;
ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 6,
width_b => 8,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq,
address_a => ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa,
data_a => ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia
);
ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q <= ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0(REG,657)@28
reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_q <= ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid406_arcsinXO2XTabGen_lutmem(DUALMEM,599)@29
memoryC0_uid406_arcsinXO2XTabGen_lutmem_reset0 <= areset;
memoryC0_uid406_arcsinXO2XTabGen_lutmem_ia <= (others => '0');
memoryC0_uid406_arcsinXO2XTabGen_lutmem_aa <= (others => '0');
memoryC0_uid406_arcsinXO2XTabGen_lutmem_ab <= reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_q;
memoryC0_uid406_arcsinXO2XTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_arccospi_s5_memoryC0_uid406_arcsinXO2XTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid406_arcsinXO2XTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid406_arcsinXO2XTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid406_arcsinXO2XTabGen_lutmem_iq,
address_a => memoryC0_uid406_arcsinXO2XTabGen_lutmem_aa,
data_a => memoryC0_uid406_arcsinXO2XTabGen_lutmem_ia
);
memoryC0_uid406_arcsinXO2XTabGen_lutmem_q <= memoryC0_uid406_arcsinXO2XTabGen_lutmem_iq(29 downto 0);
--sumAHighB_uid419_arcsinXO2XPolyEval(ADD,418)@31
sumAHighB_uid419_arcsinXO2XPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => memoryC0_uid406_arcsinXO2XTabGen_lutmem_q(29)) & memoryC0_uid406_arcsinXO2XTabGen_lutmem_q);
sumAHighB_uid419_arcsinXO2XPolyEval_b <= STD_LOGIC_VECTOR((30 downto 20 => highBBits_uid418_arcsinXO2XPolyEval_b(19)) & highBBits_uid418_arcsinXO2XPolyEval_b);
sumAHighB_uid419_arcsinXO2XPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid419_arcsinXO2XPolyEval_a) + SIGNED(sumAHighB_uid419_arcsinXO2XPolyEval_b));
sumAHighB_uid419_arcsinXO2XPolyEval_q <= sumAHighB_uid419_arcsinXO2XPolyEval_o(30 downto 0);
--lowRangeB_uid417_arcsinXO2XPolyEval(BITSELECT,416)@31
lowRangeB_uid417_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid586_pT2_uid416_arcsinXO2XPolyEval_b(1 downto 0);
lowRangeB_uid417_arcsinXO2XPolyEval_b <= lowRangeB_uid417_arcsinXO2XPolyEval_in(1 downto 0);
--s2_uid417_uid420_arcsinXO2XPolyEval(BITJOIN,419)@31
s2_uid417_uid420_arcsinXO2XPolyEval_q <= sumAHighB_uid419_arcsinXO2XPolyEval_q & lowRangeB_uid417_arcsinXO2XPolyEval_b;
--fxpArcSinXO2XRes_uid83_acosX_uid8_fpArccosPiTest(BITSELECT,82)@31
fxpArcSinXO2XRes_uid83_acosX_uid8_fpArccosPiTest_in <= s2_uid417_uid420_arcsinXO2XPolyEval_q(30 downto 0);
fxpArcSinXO2XRes_uid83_acosX_uid8_fpArccosPiTest_b <= fxpArcSinXO2XRes_uid83_acosX_uid8_fpArccosPiTest_in(30 downto 5);
--fxpArcsinXO2XResWFRange_uid84_acosX_uid8_fpArccosPiTest(BITSELECT,83)@31
fxpArcsinXO2XResWFRange_uid84_acosX_uid8_fpArccosPiTest_in <= fxpArcSinXO2XRes_uid83_acosX_uid8_fpArccosPiTest_b(24 downto 0);
fxpArcsinXO2XResWFRange_uid84_acosX_uid8_fpArccosPiTest_b <= fxpArcsinXO2XResWFRange_uid84_acosX_uid8_fpArccosPiTest_in(24 downto 2);
--fpArcsinXO2XRes_uid85_acosX_uid8_fpArccosPiTest(BITJOIN,84)@31
fpArcsinXO2XRes_uid85_acosX_uid8_fpArccosPiTest_q <= GND_q & cstBiasP1_uid26_acosX_uid8_fpArccosPiTest_q & fxpArcsinXO2XResWFRange_uid84_acosX_uid8_fpArccosPiTest_b;
--expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,422)@31
expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= fpArcsinXO2XRes_uid85_acosX_uid8_fpArccosPiTest_q(30 downto 0);
expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(30 downto 23);
--expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,449)@31
expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b;
expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q;
expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "1" when expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a = expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b else "0";
--reg_expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2(REG,659)@31
reg_expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q <= expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,503)@32
excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= reg_expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q;
excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= reg_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q;
excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b;
--fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,427)@31
fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= fpArcsinXO2XRes_uid85_acosX_uid8_fpArccosPiTest_q(22 downto 0);
fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(22 downto 0);
--reg_fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1(REG,660)@31
reg_fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b;
END IF;
END IF;
END PROCESS;
--fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,453)@32
fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= reg_fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q;
fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q;
fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "1" when fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a = fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b else "0";
--expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,451)@31
expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b;
expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q;
expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
IF (expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a = expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b) THEN
expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "1";
ELSE
expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "0";
END IF;
END IF;
END PROCESS;
--exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,454)@32
exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b;
--expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,433)@19
expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q;
expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q;
expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "1" when expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a = expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b else "0";
--ld_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1212)@19
ld_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYI_uid505_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,504)@32
excXZAndExcYI_uid505_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q;
excXZAndExcYI_uid505_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
excXZAndExcYI_uid505_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excXZAndExcYI_uid505_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and excXZAndExcYI_uid505_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b;
--ZeroTimesInf_uid506_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,505)@32
ZeroTimesInf_uid506_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= excXZAndExcYI_uid505_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
ZeroTimesInf_uid506_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
ZeroTimesInf_uid506_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= ZeroTimesInf_uid506_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a or ZeroTimesInf_uid506_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b;
--InvFracXIsZero_uid456_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,455)@32
InvFracXIsZero_uid456_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
InvFracXIsZero_uid456_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= not InvFracXIsZero_uid456_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a;
--exc_N_uid457_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,456)@32
exc_N_uid457_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
exc_N_uid457_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= InvFracXIsZero_uid456_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
exc_N_uid457_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= exc_N_uid457_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and exc_N_uid457_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b;
--InvFracXIsZero_uid440_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,439)@19
InvFracXIsZero_uid440_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
InvFracXIsZero_uid440_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= not InvFracXIsZero_uid440_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a;
--exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,440)@19
exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= InvFracXIsZero_uid440_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b;
--ld_exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1242)@19
ld_exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,506)@32
excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q;
excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= exc_N_uid457_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c <= ZeroTimesInf_uid506_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a or excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b or excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c;
--InvExcRNaN_uid519_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,518)@32
InvExcRNaN_uid519_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
InvExcRNaN_uid519_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExcRNaN_uid519_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExcRNaN_uid519_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= not InvExcRNaN_uid519_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a;
END IF;
END PROCESS;
--signY_uid425_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,424)@31
signY_uid425_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= fpArcsinXO2XRes_uid85_acosX_uid8_fpArccosPiTest_q;
signY_uid425_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= signY_uid425_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(31 downto 31);
--signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,423)@18
signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q;
signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(31 downto 31);
--ld_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_to_reg_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_a(DELAY,1410)@18
ld_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_to_reg_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b, xout => ld_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_to_reg_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1(REG,679)@30
reg_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= ld_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_to_reg_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_a_q;
END IF;
END IF;
END PROCESS;
--signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,489)@31
signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= reg_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q;
signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= signY_uid425_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b;
signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a xor signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b;
END IF;
END PROCESS;
--ld_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1254)@32
ld_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,519)@33
signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q;
signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= InvExcRNaN_uid519_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b;
--ld_signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c(DELAY,1258)@33
ld_signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--add_one_fracY_uid428_uid429_uid429_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITJOIN,428)@31
add_one_fracY_uid428_uid429_uid429_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= VCC_q & fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b;
--reg_add_one_fracY_uid428_uid429_uid429_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1(REG,666)@31
reg_add_one_fracY_uid428_uid429_uid429_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracY_uid428_uid429_uid429_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracY_uid428_uid429_uid429_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= add_one_fracY_uid428_uid429_uid429_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor(LOGICAL,1523)
ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q;
ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_b <= ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q;
ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_q <= not (ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_a or ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_b);
--ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_mem_top(CONSTANT,1507)
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_mem_top_q <= "01011";
--ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmp(LOGICAL,1508)
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmp_a <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_mem_top_q;
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q);
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmp_q <= "1" when ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmp_a = ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmp_b else "0";
--ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmpReg(REG,1509)
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmpReg_q <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena(REG,1524)
ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_q = "1") THEN
ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd(LOGICAL,1525)
ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_a <= ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q;
ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_b <= en;
ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_q <= ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_a and ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_b;
--ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt(COUNTER,1503)
-- every=1, low=0, high=11, step=1, init=1
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i = 10 THEN
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_eq = '1') THEN
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i - 11;
ELSE
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i,4));
--ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdreg(REG,1504)
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux(MUX,1505)
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux_s <= en;
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux: PROCESS (ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux_s, ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q, ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q;
WHEN "1" => ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem(DUALMEM,1514)
ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_reset0 <= areset;
ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ia <= reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2_q;
ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_aa <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q;
ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ab <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q;
ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 24,
widthad_a => 4,
numwords_a => 12,
width_b => 24,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_iq,
address_a => ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_aa,
data_a => ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ia
);
ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_q <= ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_iq(23 downto 0);
--prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest(MULT,464)@32
prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_pr <= UNSIGNED(prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a) * UNSIGNED(prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b);
prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= (others => '0');
prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= (others => '0');
prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_q;
prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= reg_add_one_fracY_uid428_uid429_uid429_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q;
prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s1 <= STD_LOGIC_VECTOR(prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_pr);
END IF;
END IF;
END PROCESS;
prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s1;
END IF;
END IF;
END PROCESS;
--normalizeBit_uid466_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,465)@35
normalizeBit_uid466_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
normalizeBit_uid466_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= normalizeBit_uid466_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(47 downto 47);
--roundBitDetectionConstant_uid201_rAcosPi_uid13_fpArccosPiTest(CONSTANT,200)
roundBitDetectionConstant_uid201_rAcosPi_uid13_fpArccosPiTest_q <= "010";
--fracRPostNormHigh_uid468_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,467)@35
fracRPostNormHigh_uid468_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q(46 downto 0);
fracRPostNormHigh_uid468_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= fracRPostNormHigh_uid468_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(46 downto 23);
--fracRPostNormLow_uid469_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,468)@35
fracRPostNormLow_uid469_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q(45 downto 0);
fracRPostNormLow_uid469_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= fracRPostNormLow_uid469_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(45 downto 22);
--fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest(MUX,469)@35
fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s <= normalizeBit_uid466_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b;
fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s, en, fracRPostNormLow_uid469_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b, fracRPostNormHigh_uid468_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b)
BEGIN
CASE fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s IS
WHEN "0" => fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= fracRPostNormLow_uid469_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b;
WHEN "1" => fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= fracRPostNormHigh_uid468_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b;
WHEN OTHERS => fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--FracRPostNorm1dto0_uid478_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,477)@35
FracRPostNorm1dto0_uid478_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q(1 downto 0);
FracRPostNorm1dto0_uid478_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= FracRPostNorm1dto0_uid478_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(1 downto 0);
--Prod22_uid472_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,471)@35
Prod22_uid472_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q(22 downto 0);
Prod22_uid472_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= Prod22_uid472_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(22 downto 22);
--extraStickyBit_uid473_arcsinL_uid87_acosX_uid8_fpArccosPiTest(MUX,472)@35
extraStickyBit_uid473_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s <= normalizeBit_uid466_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b;
extraStickyBit_uid473_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (extraStickyBit_uid473_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s, en, GND_q, Prod22_uid472_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b)
BEGIN
CASE extraStickyBit_uid473_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s IS
WHEN "0" => extraStickyBit_uid473_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= GND_q;
WHEN "1" => extraStickyBit_uid473_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= Prod22_uid472_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b;
WHEN OTHERS => extraStickyBit_uid473_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--stickyRange_uid471_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,470)@35
stickyRange_uid471_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q(21 downto 0);
stickyRange_uid471_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= stickyRange_uid471_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(21 downto 0);
--stickyExtendedRange_uid474_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITJOIN,473)@35
stickyExtendedRange_uid474_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= extraStickyBit_uid473_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q & stickyRange_uid471_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b;
--stickyRangeComparator_uid476_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,475)@35
stickyRangeComparator_uid476_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= stickyExtendedRange_uid474_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
stickyRangeComparator_uid476_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q;
stickyRangeComparator_uid476_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "1" when stickyRangeComparator_uid476_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a = stickyRangeComparator_uid476_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b else "0";
--sticky_uid477_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,476)@35
sticky_uid477_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= stickyRangeComparator_uid476_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
sticky_uid477_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= not sticky_uid477_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a;
--lrs_uid479_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITJOIN,478)@35
lrs_uid479_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= FracRPostNorm1dto0_uid478_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b & sticky_uid477_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
--roundBitDetectionPattern_uid481_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,480)@35
roundBitDetectionPattern_uid481_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= lrs_uid479_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
roundBitDetectionPattern_uid481_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= roundBitDetectionConstant_uid201_rAcosPi_uid13_fpArccosPiTest_q;
roundBitDetectionPattern_uid481_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "1" when roundBitDetectionPattern_uid481_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a = roundBitDetectionPattern_uid481_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b else "0";
--roundBit_uid482_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,481)@35
roundBit_uid482_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= roundBitDetectionPattern_uid481_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
roundBit_uid482_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= not roundBit_uid482_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a;
--roundBitAndNormalizationOp_uid485_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITJOIN,484)@35
roundBitAndNormalizationOp_uid485_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= GND_q & normalizeBit_uid466_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b & cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q & roundBit_uid482_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
--reg_roundBitAndNormalizationOp_uid485_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1(REG,670)@35
reg_roundBitAndNormalizationOp_uid485_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_roundBitAndNormalizationOp_uid485_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_roundBitAndNormalizationOp_uid485_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= roundBitAndNormalizationOp_uid485_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--biasInc_uid184_rAcosPi_uid13_fpArccosPiTest(CONSTANT,183)
biasInc_uid184_rAcosPi_uid13_fpArccosPiTest_q <= "0001111111";
--reg_expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1(REG,668)@31
reg_expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor(LOGICAL,1511)
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q;
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_b <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q;
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_q <= not (ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_a or ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_b);
--ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena(REG,1512)
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_q = "1") THEN
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd(LOGICAL,1513)
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_a <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q;
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_b <= en;
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_q <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_a and ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_b;
--ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem(DUALMEM,1502)
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_reset0 <= areset;
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ia <= reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q;
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_aa <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q;
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ab <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q;
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 12,
width_b => 8,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_iq,
address_a => ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_aa,
data_a => ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ia
);
ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_q <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_iq(7 downto 0);
--expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest(ADD,461)@32
expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_q);
expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("0" & reg_expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q);
expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a) + UNSIGNED(expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b));
END IF;
END IF;
END PROCESS;
expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o(8 downto 0);
--ld_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1175)@33
ld_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest(SUB,463)@34
expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & ld_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q);
expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid184_rAcosPi_uid13_fpArccosPiTest_q(9)) & biasInc_uid184_rAcosPi_uid13_fpArccosPiTest_q);
expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a) - SIGNED(expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b));
END IF;
END IF;
END PROCESS;
expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o(10 downto 0);
--expFracPreRound_uid483_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITJOIN,482)@35
expFracPreRound_uid483_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q & fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
--reg_expFracPreRound_uid483_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0(REG,669)@35
reg_expFracPreRound_uid483_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRound_uid483_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRound_uid483_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q <= expFracPreRound_uid483_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest(ADD,485)@36
expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR((36 downto 35 => reg_expFracPreRound_uid483_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q(34)) & reg_expFracPreRound_uid483_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q);
expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_roundBitAndNormalizationOp_uid485_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q);
expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a) + SIGNED(expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b));
expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o(35 downto 0);
--expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,487)@36
expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(35 downto 24);
--expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,488)@36
expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b(7 downto 0);
expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(7 downto 0);
--ld_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_to_reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_a(DELAY,1409)@36
ld_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_to_reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_a : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b, xout => ld_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_to_reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3(REG,678)@37
reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q <= ld_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_to_reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_a_q;
END IF;
END IF;
END PROCESS;
--ld_excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c(DELAY,1247)@32
ld_excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1(REG,671)@36
reg_expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b;
END IF;
END IF;
END PROCESS;
--expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest(COMPARE,492)@37
expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_cin <= GND_q;
expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q(11)) & reg_expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q) & '0';
expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR('0' & "00000" & cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q) & expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_cin(0);
expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a) - SIGNED(expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b));
expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_n(0) <= not expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o(14);
--InvExc_N_uid458_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,457)@32
InvExc_N_uid458_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= exc_N_uid457_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
InvExc_N_uid458_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= not InvExc_N_uid458_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a;
--InvExc_I_uid459_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,458)@32
InvExc_I_uid459_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
InvExc_I_uid459_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= not InvExc_I_uid459_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a;
--InvExpXIsZero_uid460_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,459)@31
InvExpXIsZero_uid460_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
InvExpXIsZero_uid460_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExpXIsZero_uid460_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExpXIsZero_uid460_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= not InvExpXIsZero_uid460_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a;
END IF;
END PROCESS;
--exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,460)@32
exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= InvExpXIsZero_uid460_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= InvExc_I_uid459_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c <= InvExc_N_uid458_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b and exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c;
--ld_exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b(DELAY,1217)@32
ld_exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1153)@19
ld_exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,441)@31
InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q;
InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= not InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a;
--InvExc_I_uid443_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,442)@31
InvExc_I_uid443_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
InvExc_I_uid443_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= not InvExc_I_uid443_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a;
--InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,443)@19
InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= not InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a;
--ld_InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1156)@19
ld_InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,444)@31
exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q;
exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= InvExc_I_uid443_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c <= InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b and exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c;
--ld_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1216)@31
ld_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 6 )
PORT MAP ( xin => exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,501)@37
ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q;
ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= ld_exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q;
ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c <= expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_n;
ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b and ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c;
--ld_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1223)@31
ld_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,500)@32
excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= ld_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q;
excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b;
--ld_excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c(DELAY,1234)@32
ld_excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2(REG,664)@31
reg_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q <= exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,499)@32
excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= reg_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q;
excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b;
--ld_excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b(DELAY,1233)@32
ld_excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,498)@32
excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q;
excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b;
--ld_excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1232)@32
ld_excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,502)@37
excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q;
excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= ld_excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q;
excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c <= ld_excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q;
excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d <= ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a or excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b or excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c or excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d;
--expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest(COMPARE,490)@37
expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_cin <= GND_q;
expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR('0' & "000000000000" & GND_q) & '0';
expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q(11)) & reg_expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q) & expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_cin(0);
expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a) - SIGNED(expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b));
expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_n(0) <= not expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o(14);
--excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,496)@37
excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q;
excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= ld_exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q;
excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c <= expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_n;
excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b and excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c;
--excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,495)@32
excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= reg_expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q;
excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= reg_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q;
excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b;
--ld_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c(DELAY,1221)@32
ld_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,494)@32
excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q;
excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b;
--ld_excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b(DELAY,1220)@32
ld_excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1(REG,658)@19
reg_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1210)@20
ld_reg_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 12 )
PORT MAP ( xin => reg_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q, xout => ld_reg_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,493)@32
excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_reg_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q;
excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= reg_expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q;
excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b;
--ld_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1219)@32
ld_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,497)@37
excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q;
excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= ld_excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q;
excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c <= ld_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q;
excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d <= excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a or excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b or excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c or excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d;
--concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITJOIN,507)@37
concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= ld_excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q & excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q & excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
--reg_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0(REG,676)@37
reg_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q <= concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOOKUP,508)@38
excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (reg_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q) IS
WHEN "000" => excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "01";
WHEN "001" => excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "00";
WHEN "010" => excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "10";
WHEN "011" => excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "00";
WHEN "100" => excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "11";
WHEN "101" => excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "00";
WHEN "110" => excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "00";
WHEN "111" => excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "00";
WHEN OTHERS =>
excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest(MUX,517)@38
expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s <= excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s, en, cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q, reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q, cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q, cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q)
BEGIN
CASE expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s IS
WHEN "00" => expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q;
WHEN "01" => expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q;
WHEN "10" => expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q;
WHEN "11" => expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q;
WHEN OTHERS => expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,486)@36
fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q(23 downto 0);
fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(23 downto 1);
--reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3(REG,677)@36
reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q <= fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d(DELAY,1250)@37
ld_reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q, xout => ld_reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest(MUX,512)@38
fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s <= excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s, en, cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q, ld_reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d_q, cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q, cstNaNWF_uid20_acosX_uid8_fpArccosPiTest_q)
BEGIN
CASE fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s IS
WHEN "00" => fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q;
WHEN "01" => fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= ld_reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d_q;
WHEN "10" => fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q;
WHEN "11" => fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= cstNaNWF_uid20_acosX_uid8_fpArccosPiTest_q;
WHEN OTHERS => fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITJOIN,520)@38
R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= ld_signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q & expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q & fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q;
--ArcsinL22dto0_uid88_acosX_uid8_fpArccosPiTest(BITSELECT,87)@38
ArcsinL22dto0_uid88_acosX_uid8_fpArccosPiTest_in <= R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q(22 downto 0);
ArcsinL22dto0_uid88_acosX_uid8_fpArccosPiTest_b <= ArcsinL22dto0_uid88_acosX_uid8_fpArccosPiTest_in(22 downto 0);
--oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest(BITJOIN,88)@38
oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_q <= VCC_q & ArcsinL22dto0_uid88_acosX_uid8_fpArccosPiTest_b;
--X23dto16_uid527_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITSELECT,526)@38
X23dto16_uid527_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in <= oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_q;
X23dto16_uid527_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b <= X23dto16_uid527_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in(23 downto 16);
--rightShiftStage0Idx2_uid529_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITJOIN,528)@38
rightShiftStage0Idx2_uid529_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= rightShiftStage0Idx1Pad16_uid246_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & X23dto16_uid527_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b;
--reg_rightShiftStage0Idx2_uid529_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_4(REG,683)@38
reg_rightShiftStage0Idx2_uid529_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx2_uid529_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_4_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx2_uid529_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_4_q <= rightShiftStage0Idx2_uid529_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--X23dto8_uid524_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITSELECT,523)@38
X23dto8_uid524_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in <= oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_q;
X23dto8_uid524_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b <= X23dto8_uid524_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in(23 downto 8);
--rightShiftStage0Idx1_uid526_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITJOIN,525)@38
rightShiftStage0Idx1_uid526_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q & X23dto8_uid524_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b;
--reg_rightShiftStage0Idx1_uid526_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_3(REG,682)@38
reg_rightShiftStage0Idx1_uid526_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStage0Idx1_uid526_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_3_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStage0Idx1_uid526_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_3_q <= rightShiftStage0Idx1_uid526_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--reg_oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_2(REG,681)@38
reg_oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_2_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_2_q <= oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--ArcsinL30dto23_uid90_acosX_uid8_fpArccosPiTest(BITSELECT,89)@38
ArcsinL30dto23_uid90_acosX_uid8_fpArccosPiTest_in <= R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q(30 downto 0);
ArcsinL30dto23_uid90_acosX_uid8_fpArccosPiTest_b <= ArcsinL30dto23_uid90_acosX_uid8_fpArccosPiTest_in(30 downto 23);
--srValArcsinL_uid91_acosX_uid8_fpArccosPiTest(SUB,90)@38
srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid22_acosX_uid8_fpArccosPiTest_q);
srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("0" & ArcsinL30dto23_uid90_acosX_uid8_fpArccosPiTest_b);
srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_a) - UNSIGNED(srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_b));
srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_q <= srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_o(8 downto 0);
--srValArcsinLRange_uid92_acosX_uid8_fpArccosPiTest(BITSELECT,91)@38
srValArcsinLRange_uid92_acosX_uid8_fpArccosPiTest_in <= srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_q(4 downto 0);
srValArcsinLRange_uid92_acosX_uid8_fpArccosPiTest_b <= srValArcsinLRange_uid92_acosX_uid8_fpArccosPiTest_in(4 downto 0);
--rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITSELECT,530)@38
rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in <= srValArcsinLRange_uid92_acosX_uid8_fpArccosPiTest_b;
rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b <= rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in(4 downto 3);
--reg_rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1(REG,680)@38
reg_rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q <= rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(MUX,531)@39
rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s <= reg_rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q;
rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest: PROCESS (rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s, en, reg_oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_2_q, reg_rightShiftStage0Idx1_uid526_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_3_q, reg_rightShiftStage0Idx2_uid529_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_4_q, rightShiftStage0Idx3_uid386_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q)
BEGIN
CASE rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s IS
WHEN "00" => rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= reg_oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_2_q;
WHEN "01" => rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage0Idx1_uid526_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_3_q;
WHEN "10" => rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage0Idx2_uid529_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_4_q;
WHEN "11" => rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= rightShiftStage0Idx3_uid386_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q;
WHEN OTHERS => rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITSELECT,541)@38
rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in <= srValArcsinLRange_uid92_acosX_uid8_fpArccosPiTest_b(2 downto 0);
rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b <= rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in(2 downto 1);
--reg_rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1(REG,684)@38
reg_rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q <= rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(MUX,542)@39
rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s <= reg_rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q;
rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest: PROCESS (rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s, en, rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q, rightShiftStage1Idx1_uid535_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q, rightShiftStage1Idx2_uid538_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q, rightShiftStage1Idx3_uid541_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q)
BEGIN
CASE rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s IS
WHEN "00" => rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q;
WHEN "01" => rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1Idx1_uid535_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q;
WHEN "10" => rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1Idx2_uid538_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q;
WHEN "11" => rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1Idx3_uid541_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q;
WHEN OTHERS => rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITSELECT,546)@38
rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in <= srValArcsinLRange_uid92_acosX_uid8_fpArccosPiTest_b(0 downto 0);
rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b <= rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in(0 downto 0);
--reg_rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1(REG,685)@38
reg_rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q <= rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b;
END IF;
END IF;
END PROCESS;
--rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(MUX,547)@39
rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s <= reg_rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q;
rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest: PROCESS (rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s, en, rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q, rightShiftStage2Idx1_uid546_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q)
BEGIN
CASE rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s IS
WHEN "0" => rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q;
WHEN "1" => rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= rightShiftStage2Idx1_uid546_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q;
WHEN OTHERS => rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--pad_fxpArcsinL_uid94_uid95_acosX_uid8_fpArccosPiTest(BITJOIN,94)@39
pad_fxpArcsinL_uid94_uid95_acosX_uid8_fpArccosPiTest_q <= rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q & STD_LOGIC_VECTOR((2 downto 1 => GND_q(0)) & GND_q);
--reg_pad_fxpArcsinL_uid94_uid95_acosX_uid8_fpArccosPiTest_0_to_path1NegCase_uid95_acosX_uid8_fpArccosPiTest_1(REG,686)@39
reg_pad_fxpArcsinL_uid94_uid95_acosX_uid8_fpArccosPiTest_0_to_path1NegCase_uid95_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_fxpArcsinL_uid94_uid95_acosX_uid8_fpArccosPiTest_0_to_path1NegCase_uid95_acosX_uid8_fpArccosPiTest_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_fxpArcsinL_uid94_uid95_acosX_uid8_fpArccosPiTest_0_to_path1NegCase_uid95_acosX_uid8_fpArccosPiTest_1_q <= pad_fxpArcsinL_uid94_uid95_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--pi_uid94_acosX_uid8_fpArccosPiTest(CONSTANT,93)
pi_uid94_acosX_uid8_fpArccosPiTest_q <= "1100100100001111110110101010";
--path1NegCase_uid95_acosX_uid8_fpArccosPiTest(SUB,95)@40
path1NegCase_uid95_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & pi_uid94_acosX_uid8_fpArccosPiTest_q);
path1NegCase_uid95_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_pad_fxpArcsinL_uid94_uid95_acosX_uid8_fpArccosPiTest_0_to_path1NegCase_uid95_acosX_uid8_fpArccosPiTest_1_q);
path1NegCase_uid95_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path1NegCase_uid95_acosX_uid8_fpArccosPiTest_a) - UNSIGNED(path1NegCase_uid95_acosX_uid8_fpArccosPiTest_b));
path1NegCase_uid95_acosX_uid8_fpArccosPiTest_q <= path1NegCase_uid95_acosX_uid8_fpArccosPiTest_o(28 downto 0);
--path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest(BITSELECT,96)@40
path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_in <= path1NegCase_uid95_acosX_uid8_fpArccosPiTest_q(27 downto 0);
path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_b <= path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_in(27 downto 27);
--reg_path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_0_to_path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_1(REG,687)@40
reg_path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_0_to_path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_0_to_path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_0_to_path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_1_q <= path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_b;
END IF;
END IF;
END PROCESS;
--path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest(ADD,100)@41
path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid22_acosX_uid8_fpArccosPiTest_q);
path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("00000000" & reg_path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_0_to_path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_1_q);
path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_a) + UNSIGNED(path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_b));
path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_q <= path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_o(8 downto 0);
--path1NegCaseExpRange_uid102_acosX_uid8_fpArccosPiTest(BITSELECT,101)@41
path1NegCaseExpRange_uid102_acosX_uid8_fpArccosPiTest_in <= path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_q(7 downto 0);
path1NegCaseExpRange_uid102_acosX_uid8_fpArccosPiTest_b <= path1NegCaseExpRange_uid102_acosX_uid8_fpArccosPiTest_in(7 downto 0);
--path1NegCaseFracHigh_uid98_acosX_uid8_fpArccosPiTest(BITSELECT,97)@40
path1NegCaseFracHigh_uid98_acosX_uid8_fpArccosPiTest_in <= path1NegCase_uid95_acosX_uid8_fpArccosPiTest_q(26 downto 0);
path1NegCaseFracHigh_uid98_acosX_uid8_fpArccosPiTest_b <= path1NegCaseFracHigh_uid98_acosX_uid8_fpArccosPiTest_in(26 downto 4);
--path1NegCaseFracLow_uid99_acosX_uid8_fpArccosPiTest(BITSELECT,98)@40
path1NegCaseFracLow_uid99_acosX_uid8_fpArccosPiTest_in <= path1NegCase_uid95_acosX_uid8_fpArccosPiTest_q(25 downto 0);
path1NegCaseFracLow_uid99_acosX_uid8_fpArccosPiTest_b <= path1NegCaseFracLow_uid99_acosX_uid8_fpArccosPiTest_in(25 downto 3);
--path1NegCaseFrac_uid100_acosX_uid8_fpArccosPiTest(MUX,99)@40
path1NegCaseFrac_uid100_acosX_uid8_fpArccosPiTest_s <= path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_b;
path1NegCaseFrac_uid100_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
path1NegCaseFrac_uid100_acosX_uid8_fpArccosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE path1NegCaseFrac_uid100_acosX_uid8_fpArccosPiTest_s IS
WHEN "0" => path1NegCaseFrac_uid100_acosX_uid8_fpArccosPiTest_q <= path1NegCaseFracLow_uid99_acosX_uid8_fpArccosPiTest_b;
WHEN "1" => path1NegCaseFrac_uid100_acosX_uid8_fpArccosPiTest_q <= path1NegCaseFracHigh_uid98_acosX_uid8_fpArccosPiTest_b;
WHEN OTHERS => path1NegCaseFrac_uid100_acosX_uid8_fpArccosPiTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--path1NegCaseUR_uid103_acosX_uid8_fpArccosPiTest(BITJOIN,102)@41
path1NegCaseUR_uid103_acosX_uid8_fpArccosPiTest_q <= GND_q & path1NegCaseExpRange_uid102_acosX_uid8_fpArccosPiTest_b & path1NegCaseFrac_uid100_acosX_uid8_fpArccosPiTest_q;
--ld_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_c_inputreg(DELAY,1461)
ld_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_c(DELAY,790)@38
ld_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 2 )
PORT MAP ( xin => ld_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_c_inputreg_q, xout => ld_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_nor(LOGICAL,1458)
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q;
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_nor_b <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_sticky_ena_q;
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_nor_q <= not (ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_nor_a or ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_nor_b);
--ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_mem_top(CONSTANT,1454)
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_mem_top_q <= "0100111";
--ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmp(LOGICAL,1455)
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmp_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_mem_top_q;
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q);
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmp_q <= "1" when ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmp_a = ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmp_b else "0";
--ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmpReg(REG,1456)
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmpReg_q <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_sticky_ena(REG,1459)
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_nor_q = "1") THEN
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_sticky_ena_q <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_enaAnd(LOGICAL,1460)
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_enaAnd_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_sticky_ena_q;
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_enaAnd_b <= en;
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_enaAnd_q <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_enaAnd_a and ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_enaAnd_b;
--ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt(COUNTER,1450)
-- every=1, low=0, high=39, step=1, init=1
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i = 38 THEN
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i - 39;
ELSE
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i,6));
--ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdreg(REG,1451)
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux(MUX,1452)
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux_s <= en;
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux: PROCESS (ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux_s, ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q, ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem(DUALMEM,1449)
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_reset0 <= areset;
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_ia <= singX_uid17_acosX_uid8_fpArccosPiTest_b;
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_aa <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q;
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_ab <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q;
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 40,
width_b => 1,
widthad_b => 6,
numwords_b => 40,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_iq,
address_a => ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_aa,
data_a => ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_ia
);
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_q <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_iq(0 downto 0);
--path1ResFP_uid105_acosX_uid8_fpArccosPiTest(MUX,104)@41
path1ResFP_uid105_acosX_uid8_fpArccosPiTest_s <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_q;
path1ResFP_uid105_acosX_uid8_fpArccosPiTest: PROCESS (path1ResFP_uid105_acosX_uid8_fpArccosPiTest_s, en, ld_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_c_q, path1NegCaseUR_uid103_acosX_uid8_fpArccosPiTest_q)
BEGIN
CASE path1ResFP_uid105_acosX_uid8_fpArccosPiTest_s IS
WHEN "0" => path1ResFP_uid105_acosX_uid8_fpArccosPiTest_q <= ld_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_c_q;
WHEN "1" => path1ResFP_uid105_acosX_uid8_fpArccosPiTest_q <= path1NegCaseUR_uid103_acosX_uid8_fpArccosPiTest_q;
WHEN OTHERS => path1ResFP_uid105_acosX_uid8_fpArccosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest(BITSELECT,132)@41
Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_in <= path1ResFP_uid105_acosX_uid8_fpArccosPiTest_q(30 downto 0);
Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_b <= Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_in(30 downto 23);
--reg_Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_2(REG,699)@41
reg_Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_2_q <= Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_nor(LOGICAL,1472)
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q;
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_nor_b <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_sticky_ena_q;
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_nor_q <= not (ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_nor_a or ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_nor_b);
--ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_mem_top(CONSTANT,1468)
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_mem_top_q <= "0100101";
--ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmp(LOGICAL,1469)
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmp_a <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_mem_top_q;
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q);
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmp_q <= "1" when ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmp_a = ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmp_b else "0";
--ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmpReg(REG,1470)
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmpReg_q <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_sticky_ena(REG,1473)
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_nor_q = "1") THEN
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_sticky_ena_q <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_enaAnd(LOGICAL,1474)
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_enaAnd_a <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_sticky_ena_q;
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_enaAnd_b <= en;
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_enaAnd_q <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_enaAnd_a and ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_enaAnd_b;
--ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_c(DELAY,812)@0
ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => singX_uid17_acosX_uid8_fpArccosPiTest_b, xout => ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--inputIsMax_uid60_acosX_uid8_fpArccosPiTest(BITSELECT,59)@1
inputIsMax_uid60_acosX_uid8_fpArccosPiTest_in <= rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_q;
inputIsMax_uid60_acosX_uid8_fpArccosPiTest_b <= inputIsMax_uid60_acosX_uid8_fpArccosPiTest_in(36 downto 36);
--firstPath_uid62_acosX_uid8_fpArccosPiTest(BITSELECT,61)@1
firstPath_uid62_acosX_uid8_fpArccosPiTest_in <= y_uid61_acosX_uid8_fpArccosPiTest_b;
firstPath_uid62_acosX_uid8_fpArccosPiTest_b <= firstPath_uid62_acosX_uid8_fpArccosPiTest_in(34 downto 34);
--pathSelBits_uid126_acosX_uid8_fpArccosPiTest(BITJOIN,125)@1
pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_c_q & inputIsMax_uid60_acosX_uid8_fpArccosPiTest_b & firstPath_uid62_acosX_uid8_fpArccosPiTest_b;
--ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_inputreg(DELAY,1462)
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q, xout => ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt(COUNTER,1464)
-- every=1, low=0, high=37, step=1, init=1
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i = 36 THEN
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_eq = '1') THEN
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i - 37;
ELSE
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i,6));
--ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdreg(REG,1465)
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux(MUX,1466)
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux_s <= en;
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux: PROCESS (ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux_s, ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q, ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_q)
BEGIN
CASE ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux_s IS
WHEN "0" => ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q;
WHEN "1" => ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem(DUALMEM,1463)
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_reset0 <= areset;
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_ia <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_inputreg_q;
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_aa <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q;
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_ab <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q;
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 6,
numwords_a => 38,
width_b => 3,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_iq,
address_a => ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_aa,
data_a => ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_ia
);
ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_q <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_iq(2 downto 0);
--fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest(LOOKUP,126)@41
fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q <= "01";
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
CASE (ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_q) IS
WHEN "000" => fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q <= "01";
WHEN "001" => fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q <= "00";
WHEN "010" => fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q <= "11";
WHEN "011" => fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q <= "11";
WHEN "100" => fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q <= "01";
WHEN "101" => fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q <= "00";
WHEN "110" => fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q <= "10";
WHEN "111" => fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q <= "10";
WHEN OTHERS =>
fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q <= (others => '-');
END CASE;
END IF;
END PROCESS;
--expRCalc_uid134_acosX_uid8_fpArccosPiTest(MUX,133)@42
expRCalc_uid134_acosX_uid8_fpArccosPiTest_s <= fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q;
expRCalc_uid134_acosX_uid8_fpArccosPiTest: PROCESS (expRCalc_uid134_acosX_uid8_fpArccosPiTest_s, en, reg_Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_2_q, reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_q, cstBiasP1_uid26_acosX_uid8_fpArccosPiTest_q, cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q)
BEGIN
CASE expRCalc_uid134_acosX_uid8_fpArccosPiTest_s IS
WHEN "00" => expRCalc_uid134_acosX_uid8_fpArccosPiTest_q <= reg_Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_2_q;
WHEN "01" => expRCalc_uid134_acosX_uid8_fpArccosPiTest_q <= reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_q;
WHEN "10" => expRCalc_uid134_acosX_uid8_fpArccosPiTest_q <= cstBiasP1_uid26_acosX_uid8_fpArccosPiTest_q;
WHEN "11" => expRCalc_uid134_acosX_uid8_fpArccosPiTest_q <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q;
WHEN OTHERS => expRCalc_uid134_acosX_uid8_fpArccosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstAllZWE_uid21_acosX_uid8_fpArccosPiTest(CONSTANT,20)
cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q <= "00000000";
--ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_nor(LOGICAL,1485)
ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q;
ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_nor_b <= ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_sticky_ena_q;
ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_nor_q <= not (ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_nor_a or ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_nor_b);
--ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_sticky_ena(REG,1486)
ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_nor_q = "1") THEN
ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_sticky_ena_q <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_enaAnd(LOGICAL,1487)
ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_enaAnd_a <= ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_sticky_ena_q;
ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_enaAnd_b <= en;
ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_enaAnd_q <= ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_enaAnd_a and ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_enaAnd_b;
--fracXIsZero_uid47_acosX_uid8_fpArccosPiTest(LOGICAL,46)@0
fracXIsZero_uid47_acosX_uid8_fpArccosPiTest_a <= fracX_uid16_acosX_uid8_fpArccosPiTest_b;
fracXIsZero_uid47_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("0000000000000000000000" & GND_q);
fracXIsZero_uid47_acosX_uid8_fpArccosPiTest_q <= "1" when fracXIsZero_uid47_acosX_uid8_fpArccosPiTest_a = fracXIsZero_uid47_acosX_uid8_fpArccosPiTest_b else "0";
--InvFracXIsZero_uid48_acosX_uid8_fpArccosPiTest(LOGICAL,47)@0
InvFracXIsZero_uid48_acosX_uid8_fpArccosPiTest_a <= fracXIsZero_uid47_acosX_uid8_fpArccosPiTest_q;
InvFracXIsZero_uid48_acosX_uid8_fpArccosPiTest_q <= not InvFracXIsZero_uid48_acosX_uid8_fpArccosPiTest_a;
--expEQ0_uid46_acosX_uid8_fpArccosPiTest(LOGICAL,45)@0
expEQ0_uid46_acosX_uid8_fpArccosPiTest_a <= expX_uid15_acosX_uid8_fpArccosPiTest_b;
expEQ0_uid46_acosX_uid8_fpArccosPiTest_b <= cstBias_uid22_acosX_uid8_fpArccosPiTest_q;
expEQ0_uid46_acosX_uid8_fpArccosPiTest_q <= "1" when expEQ0_uid46_acosX_uid8_fpArccosPiTest_a = expEQ0_uid46_acosX_uid8_fpArccosPiTest_b else "0";
--expXZFracNotZero_uid49_acosX_uid8_fpArccosPiTest(LOGICAL,48)@0
expXZFracNotZero_uid49_acosX_uid8_fpArccosPiTest_a <= expEQ0_uid46_acosX_uid8_fpArccosPiTest_q;
expXZFracNotZero_uid49_acosX_uid8_fpArccosPiTest_b <= InvFracXIsZero_uid48_acosX_uid8_fpArccosPiTest_q;
expXZFracNotZero_uid49_acosX_uid8_fpArccosPiTest_q <= expXZFracNotZero_uid49_acosX_uid8_fpArccosPiTest_a and expXZFracNotZero_uid49_acosX_uid8_fpArccosPiTest_b;
--expGT0_uid45_acosX_uid8_fpArccosPiTest(COMPARE,44)@0
expGT0_uid45_acosX_uid8_fpArccosPiTest_cin <= GND_q;
expGT0_uid45_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBias_uid22_acosX_uid8_fpArccosPiTest_q) & '0';
expGT0_uid45_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid15_acosX_uid8_fpArccosPiTest_b) & expGT0_uid45_acosX_uid8_fpArccosPiTest_cin(0);
expGT0_uid45_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expGT0_uid45_acosX_uid8_fpArccosPiTest_a) - UNSIGNED(expGT0_uid45_acosX_uid8_fpArccosPiTest_b));
expGT0_uid45_acosX_uid8_fpArccosPiTest_c(0) <= expGT0_uid45_acosX_uid8_fpArccosPiTest_o(10);
--inputOutOfRange_uid50_acosX_uid8_fpArccosPiTest(LOGICAL,49)@0
inputOutOfRange_uid50_acosX_uid8_fpArccosPiTest_a <= expGT0_uid45_acosX_uid8_fpArccosPiTest_c;
inputOutOfRange_uid50_acosX_uid8_fpArccosPiTest_b <= expXZFracNotZero_uid49_acosX_uid8_fpArccosPiTest_q;
inputOutOfRange_uid50_acosX_uid8_fpArccosPiTest_q <= inputOutOfRange_uid50_acosX_uid8_fpArccosPiTest_a or inputOutOfRange_uid50_acosX_uid8_fpArccosPiTest_b;
--InvExc_N_uid41_acosX_uid8_fpArccosPiTest(LOGICAL,40)@0
InvExc_N_uid41_acosX_uid8_fpArccosPiTest_a <= exc_N_uid40_acosX_uid8_fpArccosPiTest_q;
InvExc_N_uid41_acosX_uid8_fpArccosPiTest_q <= not InvExc_N_uid41_acosX_uid8_fpArccosPiTest_a;
--InvExc_I_uid42_acosX_uid8_fpArccosPiTest(LOGICAL,41)@0
InvExc_I_uid42_acosX_uid8_fpArccosPiTest_a <= exc_I_uid38_acosX_uid8_fpArccosPiTest_q;
InvExc_I_uid42_acosX_uid8_fpArccosPiTest_q <= not InvExc_I_uid42_acosX_uid8_fpArccosPiTest_a;
--expXIsZero_uid33_acosX_uid8_fpArccosPiTest(LOGICAL,32)@0
expXIsZero_uid33_acosX_uid8_fpArccosPiTest_a <= expX_uid15_acosX_uid8_fpArccosPiTest_b;
expXIsZero_uid33_acosX_uid8_fpArccosPiTest_b <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q;
expXIsZero_uid33_acosX_uid8_fpArccosPiTest_q <= "1" when expXIsZero_uid33_acosX_uid8_fpArccosPiTest_a = expXIsZero_uid33_acosX_uid8_fpArccosPiTest_b else "0";
--InvExpXIsZero_uid43_acosX_uid8_fpArccosPiTest(LOGICAL,42)@0
InvExpXIsZero_uid43_acosX_uid8_fpArccosPiTest_a <= expXIsZero_uid33_acosX_uid8_fpArccosPiTest_q;
InvExpXIsZero_uid43_acosX_uid8_fpArccosPiTest_q <= not InvExpXIsZero_uid43_acosX_uid8_fpArccosPiTest_a;
--exc_R_uid44_acosX_uid8_fpArccosPiTest(LOGICAL,43)@0
exc_R_uid44_acosX_uid8_fpArccosPiTest_a <= InvExpXIsZero_uid43_acosX_uid8_fpArccosPiTest_q;
exc_R_uid44_acosX_uid8_fpArccosPiTest_b <= InvExc_I_uid42_acosX_uid8_fpArccosPiTest_q;
exc_R_uid44_acosX_uid8_fpArccosPiTest_c <= InvExc_N_uid41_acosX_uid8_fpArccosPiTest_q;
exc_R_uid44_acosX_uid8_fpArccosPiTest_q <= exc_R_uid44_acosX_uid8_fpArccosPiTest_a and exc_R_uid44_acosX_uid8_fpArccosPiTest_b and exc_R_uid44_acosX_uid8_fpArccosPiTest_c;
--xRegAndOutOfRange_uid135_acosX_uid8_fpArccosPiTest(LOGICAL,134)@0
xRegAndOutOfRange_uid135_acosX_uid8_fpArccosPiTest_a <= exc_R_uid44_acosX_uid8_fpArccosPiTest_q;
xRegAndOutOfRange_uid135_acosX_uid8_fpArccosPiTest_b <= inputOutOfRange_uid50_acosX_uid8_fpArccosPiTest_q;
xRegAndOutOfRange_uid135_acosX_uid8_fpArccosPiTest_q <= xRegAndOutOfRange_uid135_acosX_uid8_fpArccosPiTest_a and xRegAndOutOfRange_uid135_acosX_uid8_fpArccosPiTest_b;
--fracXIsZero_uid37_acosX_uid8_fpArccosPiTest(LOGICAL,36)@0
fracXIsZero_uid37_acosX_uid8_fpArccosPiTest_a <= fracX_uid16_acosX_uid8_fpArccosPiTest_b;
fracXIsZero_uid37_acosX_uid8_fpArccosPiTest_b <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q;
fracXIsZero_uid37_acosX_uid8_fpArccosPiTest_q <= "1" when fracXIsZero_uid37_acosX_uid8_fpArccosPiTest_a = fracXIsZero_uid37_acosX_uid8_fpArccosPiTest_b else "0";
--expXIsMax_uid35_acosX_uid8_fpArccosPiTest(LOGICAL,34)@0
expXIsMax_uid35_acosX_uid8_fpArccosPiTest_a <= expX_uid15_acosX_uid8_fpArccosPiTest_b;
expXIsMax_uid35_acosX_uid8_fpArccosPiTest_b <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q;
expXIsMax_uid35_acosX_uid8_fpArccosPiTest_q <= "1" when expXIsMax_uid35_acosX_uid8_fpArccosPiTest_a = expXIsMax_uid35_acosX_uid8_fpArccosPiTest_b else "0";
--exc_I_uid38_acosX_uid8_fpArccosPiTest(LOGICAL,37)@0
exc_I_uid38_acosX_uid8_fpArccosPiTest_a <= expXIsMax_uid35_acosX_uid8_fpArccosPiTest_q;
exc_I_uid38_acosX_uid8_fpArccosPiTest_b <= fracXIsZero_uid37_acosX_uid8_fpArccosPiTest_q;
exc_I_uid38_acosX_uid8_fpArccosPiTest_q <= exc_I_uid38_acosX_uid8_fpArccosPiTest_a and exc_I_uid38_acosX_uid8_fpArccosPiTest_b;
--InvFracXIsZero_uid39_acosX_uid8_fpArccosPiTest(LOGICAL,38)@0
InvFracXIsZero_uid39_acosX_uid8_fpArccosPiTest_a <= fracXIsZero_uid37_acosX_uid8_fpArccosPiTest_q;
InvFracXIsZero_uid39_acosX_uid8_fpArccosPiTest_q <= not InvFracXIsZero_uid39_acosX_uid8_fpArccosPiTest_a;
--exc_N_uid40_acosX_uid8_fpArccosPiTest(LOGICAL,39)@0
exc_N_uid40_acosX_uid8_fpArccosPiTest_a <= expXIsMax_uid35_acosX_uid8_fpArccosPiTest_q;
exc_N_uid40_acosX_uid8_fpArccosPiTest_b <= InvFracXIsZero_uid39_acosX_uid8_fpArccosPiTest_q;
exc_N_uid40_acosX_uid8_fpArccosPiTest_q <= exc_N_uid40_acosX_uid8_fpArccosPiTest_a and exc_N_uid40_acosX_uid8_fpArccosPiTest_b;
--excRNaN_uid136_acosX_uid8_fpArccosPiTest(LOGICAL,135)@0
excRNaN_uid136_acosX_uid8_fpArccosPiTest_a <= exc_N_uid40_acosX_uid8_fpArccosPiTest_q;
excRNaN_uid136_acosX_uid8_fpArccosPiTest_b <= exc_I_uid38_acosX_uid8_fpArccosPiTest_q;
excRNaN_uid136_acosX_uid8_fpArccosPiTest_c <= xRegAndOutOfRange_uid135_acosX_uid8_fpArccosPiTest_q;
excRNaN_uid136_acosX_uid8_fpArccosPiTest_q <= excRNaN_uid136_acosX_uid8_fpArccosPiTest_a or excRNaN_uid136_acosX_uid8_fpArccosPiTest_b or excRNaN_uid136_acosX_uid8_fpArccosPiTest_c;
--ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_inputreg(DELAY,1475)
ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => excRNaN_uid136_acosX_uid8_fpArccosPiTest_q, xout => ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem(DUALMEM,1476)
ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_reset0 <= areset;
ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_ia <= ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_inputreg_q;
ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_aa <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q;
ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_ab <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q;
ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 38,
width_b => 1,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_iq,
address_a => ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_aa,
data_a => ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_ia
);
ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_q <= ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_iq(0 downto 0);
--excSelBits_uid137_acosX_uid8_fpArccosPiTest(BITJOIN,136)@40
excSelBits_uid137_acosX_uid8_fpArccosPiTest_q <= ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_q & GND_q & GND_q;
--reg_excSelBits_uid137_acosX_uid8_fpArccosPiTest_0_to_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0(REG,608)@40
reg_excSelBits_uid137_acosX_uid8_fpArccosPiTest_0_to_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBits_uid137_acosX_uid8_fpArccosPiTest_0_to_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBits_uid137_acosX_uid8_fpArccosPiTest_0_to_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0_q <= excSelBits_uid137_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest(LOOKUP,137)@41
outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest: PROCESS (reg_excSelBits_uid137_acosX_uid8_fpArccosPiTest_0_to_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excSelBits_uid137_acosX_uid8_fpArccosPiTest_0_to_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q <= "01";
WHEN "100" => outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q <= "01";
WHEN "110" => outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q <= "01";
WHEN "111" => outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--reg_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid140_acosX_uid8_fpArccosPiTest_1(REG,701)@41
reg_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid140_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid140_acosX_uid8_fpArccosPiTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid140_acosX_uid8_fpArccosPiTest_1_q <= outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--expRPostExc_uid140_acosX_uid8_fpArccosPiTest(MUX,139)@42
expRPostExc_uid140_acosX_uid8_fpArccosPiTest_s <= reg_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid140_acosX_uid8_fpArccosPiTest_1_q;
expRPostExc_uid140_acosX_uid8_fpArccosPiTest: PROCESS (expRPostExc_uid140_acosX_uid8_fpArccosPiTest_s, en, cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q, expRCalc_uid134_acosX_uid8_fpArccosPiTest_q, cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q, cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q)
BEGIN
CASE expRPostExc_uid140_acosX_uid8_fpArccosPiTest_s IS
WHEN "00" => expRPostExc_uid140_acosX_uid8_fpArccosPiTest_q <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q;
WHEN "01" => expRPostExc_uid140_acosX_uid8_fpArccosPiTest_q <= expRCalc_uid134_acosX_uid8_fpArccosPiTest_q;
WHEN "10" => expRPostExc_uid140_acosX_uid8_fpArccosPiTest_q <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q;
WHEN "11" => expRPostExc_uid140_acosX_uid8_fpArccosPiTest_q <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q;
WHEN OTHERS => expRPostExc_uid140_acosX_uid8_fpArccosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--piF_uid128_acosX_uid8_fpArccosPiTest(BITSELECT,127)@42
piF_uid128_acosX_uid8_fpArccosPiTest_in <= pi_uid94_acosX_uid8_fpArccosPiTest_q(26 downto 0);
piF_uid128_acosX_uid8_fpArccosPiTest_b <= piF_uid128_acosX_uid8_fpArccosPiTest_in(26 downto 4);
--ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_nor(LOGICAL,1613)
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q;
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_nor_b <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q;
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_nor_q <= not (ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_nor_a or ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_nor_b);
--ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_sticky_ena(REG,1614)
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_nor_q = "1") THEN
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_enaAnd(LOGICAL,1615)
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_enaAnd_a <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q;
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_enaAnd_b <= en;
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_enaAnd_q <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_enaAnd_a and ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_enaAnd_b;
--Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest(BITSELECT,128)@13
Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_in <= path2ResFP_uid125_acosX_uid8_fpArccosPiTest_q(22 downto 0);
Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b <= Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_in(22 downto 0);
--ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_inputreg(DELAY,1603)
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b, xout => ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem(DUALMEM,1604)
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_reset0 <= areset;
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ia <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_inputreg_q;
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_aa <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdreg_q;
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ab <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux_q;
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 5,
numwords_a => 26,
width_b => 23,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_iq,
address_a => ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_aa,
data_a => ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ia
);
ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_q <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_iq(22 downto 0);
--reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3(REG,698)@41
reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_q <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest(BITSELECT,129)@41
Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_in <= path1ResFP_uid105_acosX_uid8_fpArccosPiTest_q(22 downto 0);
Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_b <= Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_in(22 downto 0);
--reg_Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_2(REG,697)@41
reg_Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_2_q <= Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_b;
END IF;
END IF;
END PROCESS;
--fracRCalc_uid131_acosX_uid8_fpArccosPiTest(MUX,130)@42
fracRCalc_uid131_acosX_uid8_fpArccosPiTest_s <= fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q;
fracRCalc_uid131_acosX_uid8_fpArccosPiTest: PROCESS (fracRCalc_uid131_acosX_uid8_fpArccosPiTest_s, en, reg_Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_2_q, reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_q, piF_uid128_acosX_uid8_fpArccosPiTest_b, cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q)
BEGIN
CASE fracRCalc_uid131_acosX_uid8_fpArccosPiTest_s IS
WHEN "00" => fracRCalc_uid131_acosX_uid8_fpArccosPiTest_q <= reg_Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_2_q;
WHEN "01" => fracRCalc_uid131_acosX_uid8_fpArccosPiTest_q <= reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_q;
WHEN "10" => fracRCalc_uid131_acosX_uid8_fpArccosPiTest_q <= piF_uid128_acosX_uid8_fpArccosPiTest_b;
WHEN "11" => fracRCalc_uid131_acosX_uid8_fpArccosPiTest_q <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q;
WHEN OTHERS => fracRCalc_uid131_acosX_uid8_fpArccosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q_to_fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_b(DELAY,832)@41
ld_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q_to_fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q, xout => ld_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q_to_fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid139_acosX_uid8_fpArccosPiTest(MUX,138)@42
fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_s <= ld_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q_to_fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_b_q;
fracRPostExc_uid139_acosX_uid8_fpArccosPiTest: PROCESS (fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_s, en, cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q, fracRCalc_uid131_acosX_uid8_fpArccosPiTest_q, cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q, cstNaNWF_uid20_acosX_uid8_fpArccosPiTest_q)
BEGIN
CASE fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_s IS
WHEN "00" => fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_q <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q;
WHEN "01" => fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_q <= fracRCalc_uid131_acosX_uid8_fpArccosPiTest_q;
WHEN "10" => fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_q <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q;
WHEN "11" => fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_q <= cstNaNWF_uid20_acosX_uid8_fpArccosPiTest_q;
WHEN OTHERS => fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--sR_uid141_acosX_uid8_fpArccosPiTest(BITJOIN,140)@42
sR_uid141_acosX_uid8_fpArccosPiTest_q <= GND_q & expRPostExc_uid140_acosX_uid8_fpArccosPiTest_q & fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_q;
--fracX_uid147_rAcosPi_uid13_fpArccosPiTest(BITSELECT,146)@42
fracX_uid147_rAcosPi_uid13_fpArccosPiTest_in <= sR_uid141_acosX_uid8_fpArccosPiTest_q(22 downto 0);
fracX_uid147_rAcosPi_uid13_fpArccosPiTest_b <= fracX_uid147_rAcosPi_uid13_fpArccosPiTest_in(22 downto 0);
--fracXIsZero_uid159_rAcosPi_uid13_fpArccosPiTest(LOGICAL,158)@42
fracXIsZero_uid159_rAcosPi_uid13_fpArccosPiTest_a <= fracX_uid147_rAcosPi_uid13_fpArccosPiTest_b;
fracXIsZero_uid159_rAcosPi_uid13_fpArccosPiTest_b <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q;
fracXIsZero_uid159_rAcosPi_uid13_fpArccosPiTest_q <= "1" when fracXIsZero_uid159_rAcosPi_uid13_fpArccosPiTest_a = fracXIsZero_uid159_rAcosPi_uid13_fpArccosPiTest_b else "0";
--expX_uid143_rAcosPi_uid13_fpArccosPiTest(BITSELECT,142)@42
expX_uid143_rAcosPi_uid13_fpArccosPiTest_in <= sR_uid141_acosX_uid8_fpArccosPiTest_q(30 downto 0);
expX_uid143_rAcosPi_uid13_fpArccosPiTest_b <= expX_uid143_rAcosPi_uid13_fpArccosPiTest_in(30 downto 23);
--expXIsMax_uid157_rAcosPi_uid13_fpArccosPiTest(LOGICAL,156)@42
expXIsMax_uid157_rAcosPi_uid13_fpArccosPiTest_a <= expX_uid143_rAcosPi_uid13_fpArccosPiTest_b;
expXIsMax_uid157_rAcosPi_uid13_fpArccosPiTest_b <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q;
expXIsMax_uid157_rAcosPi_uid13_fpArccosPiTest_q <= "1" when expXIsMax_uid157_rAcosPi_uid13_fpArccosPiTest_a = expXIsMax_uid157_rAcosPi_uid13_fpArccosPiTest_b else "0";
--exc_I_uid160_rAcosPi_uid13_fpArccosPiTest(LOGICAL,159)@42
exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_a <= expXIsMax_uid157_rAcosPi_uid13_fpArccosPiTest_q;
exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_b <= fracXIsZero_uid159_rAcosPi_uid13_fpArccosPiTest_q;
exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_q <= exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_a and exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_b;
--ld_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_q_to_reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_2_a(DELAY,1442)@42
ld_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_q_to_reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_2_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_q_to_reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_2_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_2(REG,711)@43
reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_2_q <= ld_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_q_to_reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_2_a_q;
END IF;
END IF;
END PROCESS;
--ooPi_uid9_fpArccosPiTest(CONSTANT,8)
ooPi_uid9_fpArccosPiTest_q <= "101000101111100110000011";
--fracOOPi_uid10_fpArccosPiTest(BITSELECT,9)@43
fracOOPi_uid10_fpArccosPiTest_in <= ooPi_uid9_fpArccosPiTest_q(22 downto 0);
fracOOPi_uid10_fpArccosPiTest_b <= fracOOPi_uid10_fpArccosPiTest_in(22 downto 0);
--fpOOPi_uid11_fpArccosPiTest(BITJOIN,10)@43
fpOOPi_uid11_fpArccosPiTest_q <= GND_q & cstBiasM2_uid6_fpArccosPiTest_q & fracOOPi_uid10_fpArccosPiTest_b;
--expY_uid144_rAcosPi_uid13_fpArccosPiTest(BITSELECT,143)@43
expY_uid144_rAcosPi_uid13_fpArccosPiTest_in <= fpOOPi_uid11_fpArccosPiTest_q(30 downto 0);
expY_uid144_rAcosPi_uid13_fpArccosPiTest_b <= expY_uid144_rAcosPi_uid13_fpArccosPiTest_in(30 downto 23);
--expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest(LOGICAL,170)@43
expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_a <= expY_uid144_rAcosPi_uid13_fpArccosPiTest_b;
expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_b <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q;
expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_q <= "1" when expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_a = expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_b else "0";
--reg_expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_1(REG,710)@43
reg_expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_1_q <= expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest(LOGICAL,224)@44
excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_a <= reg_expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_1_q;
excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_b <= reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_2_q;
excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_q <= excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_a and excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_b;
--fracY_uid149_rAcosPi_uid13_fpArccosPiTest(BITSELECT,148)@43
fracY_uid149_rAcosPi_uid13_fpArccosPiTest_in <= fpOOPi_uid11_fpArccosPiTest_q(22 downto 0);
fracY_uid149_rAcosPi_uid13_fpArccosPiTest_b <= fracY_uid149_rAcosPi_uid13_fpArccosPiTest_in(22 downto 0);
--fracXIsZero_uid175_rAcosPi_uid13_fpArccosPiTest(LOGICAL,174)@43
fracXIsZero_uid175_rAcosPi_uid13_fpArccosPiTest_a <= fracY_uid149_rAcosPi_uid13_fpArccosPiTest_b;
fracXIsZero_uid175_rAcosPi_uid13_fpArccosPiTest_b <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q;
fracXIsZero_uid175_rAcosPi_uid13_fpArccosPiTest_q <= "1" when fracXIsZero_uid175_rAcosPi_uid13_fpArccosPiTest_a = fracXIsZero_uid175_rAcosPi_uid13_fpArccosPiTest_b else "0";
--expXIsMax_uid173_rAcosPi_uid13_fpArccosPiTest(LOGICAL,172)@43
expXIsMax_uid173_rAcosPi_uid13_fpArccosPiTest_a <= expY_uid144_rAcosPi_uid13_fpArccosPiTest_b;
expXIsMax_uid173_rAcosPi_uid13_fpArccosPiTest_b <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q;
expXIsMax_uid173_rAcosPi_uid13_fpArccosPiTest_q <= "1" when expXIsMax_uid173_rAcosPi_uid13_fpArccosPiTest_a = expXIsMax_uid173_rAcosPi_uid13_fpArccosPiTest_b else "0";
--exc_I_uid176_rAcosPi_uid13_fpArccosPiTest(LOGICAL,175)@43
exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_a <= expXIsMax_uid173_rAcosPi_uid13_fpArccosPiTest_q;
exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_b <= fracXIsZero_uid175_rAcosPi_uid13_fpArccosPiTest_q;
exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_q <= exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_a and exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_b;
--expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest(LOGICAL,154)@42
expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_a <= expX_uid143_rAcosPi_uid13_fpArccosPiTest_b;
expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_b <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q;
expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_q <= "1" when expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_a = expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_b else "0";
--ld_expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_q_to_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_a(DELAY,911)@42
ld_expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_q_to_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_q_to_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest(LOGICAL,225)@43
excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest_a <= ld_expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_q_to_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_a_q;
excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest_b <= exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_q;
excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest_q <= excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest_a and excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest_b;
END IF;
END PROCESS;
--ZeroTimesInf_uid227_rAcosPi_uid13_fpArccosPiTest(LOGICAL,226)@44
ZeroTimesInf_uid227_rAcosPi_uid13_fpArccosPiTest_a <= excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest_q;
ZeroTimesInf_uid227_rAcosPi_uid13_fpArccosPiTest_b <= excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_q;
ZeroTimesInf_uid227_rAcosPi_uid13_fpArccosPiTest_q <= ZeroTimesInf_uid227_rAcosPi_uid13_fpArccosPiTest_a or ZeroTimesInf_uid227_rAcosPi_uid13_fpArccosPiTest_b;
--InvFracXIsZero_uid177_rAcosPi_uid13_fpArccosPiTest(LOGICAL,176)@43
InvFracXIsZero_uid177_rAcosPi_uid13_fpArccosPiTest_a <= fracXIsZero_uid175_rAcosPi_uid13_fpArccosPiTest_q;
InvFracXIsZero_uid177_rAcosPi_uid13_fpArccosPiTest_q <= not InvFracXIsZero_uid177_rAcosPi_uid13_fpArccosPiTest_a;
--exc_N_uid178_rAcosPi_uid13_fpArccosPiTest(LOGICAL,177)@43
exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_a <= expXIsMax_uid173_rAcosPi_uid13_fpArccosPiTest_q;
exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_b <= InvFracXIsZero_uid177_rAcosPi_uid13_fpArccosPiTest_q;
exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_q <= exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_a and exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_b;
--reg_exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_2(REG,713)@43
reg_exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_2_q <= exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--InvFracXIsZero_uid161_rAcosPi_uid13_fpArccosPiTest(LOGICAL,160)@42
InvFracXIsZero_uid161_rAcosPi_uid13_fpArccosPiTest_a <= fracXIsZero_uid159_rAcosPi_uid13_fpArccosPiTest_q;
InvFracXIsZero_uid161_rAcosPi_uid13_fpArccosPiTest_q <= not InvFracXIsZero_uid161_rAcosPi_uid13_fpArccosPiTest_a;
--exc_N_uid162_rAcosPi_uid13_fpArccosPiTest(LOGICAL,161)@42
exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_a <= expXIsMax_uid157_rAcosPi_uid13_fpArccosPiTest_q;
exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_b <= InvFracXIsZero_uid161_rAcosPi_uid13_fpArccosPiTest_q;
exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_q <= exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_a and exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_b;
--reg_exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_1(REG,712)@42
reg_exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_1_q <= exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_1_q_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_a(DELAY,943)@43
ld_reg_exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_1_q_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_1_q, xout => ld_reg_exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_1_q_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest(LOGICAL,227)@44
excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_a <= ld_reg_exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_1_q_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_a_q;
excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_b <= reg_exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_2_q;
excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_c <= ZeroTimesInf_uid227_rAcosPi_uid13_fpArccosPiTest_q;
excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_q <= excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_a or excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_b or excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_c;
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvExcRNaN_uid240_rAcosPi_uid13_fpArccosPiTest(LOGICAL,239)@44
InvExcRNaN_uid240_rAcosPi_uid13_fpArccosPiTest_a <= excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_q;
InvExcRNaN_uid240_rAcosPi_uid13_fpArccosPiTest_q <= not InvExcRNaN_uid240_rAcosPi_uid13_fpArccosPiTest_a;
--signY_uid146_rAcosPi_uid13_fpArccosPiTest(BITSELECT,145)@43
signY_uid146_rAcosPi_uid13_fpArccosPiTest_in <= fpOOPi_uid11_fpArccosPiTest_q;
signY_uid146_rAcosPi_uid13_fpArccosPiTest_b <= signY_uid146_rAcosPi_uid13_fpArccosPiTest_in(31 downto 31);
--signX_uid145_rAcosPi_uid13_fpArccosPiTest(BITSELECT,144)@42
signX_uid145_rAcosPi_uid13_fpArccosPiTest_in <= sR_uid141_acosX_uid8_fpArccosPiTest_q;
signX_uid145_rAcosPi_uid13_fpArccosPiTest_b <= signX_uid145_rAcosPi_uid13_fpArccosPiTest_in(31 downto 31);
--ld_signX_uid145_rAcosPi_uid13_fpArccosPiTest_b_to_signR_uid211_rAcosPi_uid13_fpArccosPiTest_a(DELAY,907)@42
ld_signX_uid145_rAcosPi_uid13_fpArccosPiTest_b_to_signR_uid211_rAcosPi_uid13_fpArccosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signX_uid145_rAcosPi_uid13_fpArccosPiTest_b, xout => ld_signX_uid145_rAcosPi_uid13_fpArccosPiTest_b_to_signR_uid211_rAcosPi_uid13_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid211_rAcosPi_uid13_fpArccosPiTest(LOGICAL,210)@43
signR_uid211_rAcosPi_uid13_fpArccosPiTest_a <= ld_signX_uid145_rAcosPi_uid13_fpArccosPiTest_b_to_signR_uid211_rAcosPi_uid13_fpArccosPiTest_a_q;
signR_uid211_rAcosPi_uid13_fpArccosPiTest_b <= signY_uid146_rAcosPi_uid13_fpArccosPiTest_b;
signR_uid211_rAcosPi_uid13_fpArccosPiTest_q <= signR_uid211_rAcosPi_uid13_fpArccosPiTest_a xor signR_uid211_rAcosPi_uid13_fpArccosPiTest_b;
--ld_signR_uid211_rAcosPi_uid13_fpArccosPiTest_q_to_signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_a(DELAY,955)@43
ld_signR_uid211_rAcosPi_uid13_fpArccosPiTest_q_to_signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid211_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_signR_uid211_rAcosPi_uid13_fpArccosPiTest_q_to_signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest(LOGICAL,240)@44
signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_a <= ld_signR_uid211_rAcosPi_uid13_fpArccosPiTest_q_to_signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_a_q;
signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_b <= InvExcRNaN_uid240_rAcosPi_uid13_fpArccosPiTest_q;
signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN
signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_q <= signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_a and signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_b;
END IF;
END PROCESS;
--ld_signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_q_to_R_uid242_rAcosPi_uid13_fpArccosPiTest_c(DELAY,959)@45
ld_signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_q_to_R_uid242_rAcosPi_uid13_fpArccosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_q_to_R_uid242_rAcosPi_uid13_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--add_one_fracY_uid149_uid150_uid150_rAcosPi_uid13_fpArccosPiTest(BITJOIN,149)@43
add_one_fracY_uid149_uid150_uid150_rAcosPi_uid13_fpArccosPiTest_q <= VCC_q & fracY_uid149_rAcosPi_uid13_fpArccosPiTest_b;
--add_one_fracX_uid147_uid148_uid148_rAcosPi_uid13_fpArccosPiTest(BITJOIN,147)@42
add_one_fracX_uid147_uid148_uid148_rAcosPi_uid13_fpArccosPiTest_q <= VCC_q & fracX_uid147_rAcosPi_uid13_fpArccosPiTest_b;
--reg_add_one_fracX_uid147_uid148_uid148_rAcosPi_uid13_fpArccosPiTest_0_to_prod_uid186_rAcosPi_uid13_fpArccosPiTest_0(REG,702)@42
reg_add_one_fracX_uid147_uid148_uid148_rAcosPi_uid13_fpArccosPiTest_0_to_prod_uid186_rAcosPi_uid13_fpArccosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_add_one_fracX_uid147_uid148_uid148_rAcosPi_uid13_fpArccosPiTest_0_to_prod_uid186_rAcosPi_uid13_fpArccosPiTest_0_q <= "000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_add_one_fracX_uid147_uid148_uid148_rAcosPi_uid13_fpArccosPiTest_0_to_prod_uid186_rAcosPi_uid13_fpArccosPiTest_0_q <= add_one_fracX_uid147_uid148_uid148_rAcosPi_uid13_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--prod_uid186_rAcosPi_uid13_fpArccosPiTest(MULT,185)@43
prod_uid186_rAcosPi_uid13_fpArccosPiTest_pr <= UNSIGNED(prod_uid186_rAcosPi_uid13_fpArccosPiTest_a) * UNSIGNED(prod_uid186_rAcosPi_uid13_fpArccosPiTest_b);
prod_uid186_rAcosPi_uid13_fpArccosPiTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid186_rAcosPi_uid13_fpArccosPiTest_a <= (others => '0');
prod_uid186_rAcosPi_uid13_fpArccosPiTest_b <= (others => '0');
prod_uid186_rAcosPi_uid13_fpArccosPiTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid186_rAcosPi_uid13_fpArccosPiTest_a <= reg_add_one_fracX_uid147_uid148_uid148_rAcosPi_uid13_fpArccosPiTest_0_to_prod_uid186_rAcosPi_uid13_fpArccosPiTest_0_q;
prod_uid186_rAcosPi_uid13_fpArccosPiTest_b <= add_one_fracY_uid149_uid150_uid150_rAcosPi_uid13_fpArccosPiTest_q;
prod_uid186_rAcosPi_uid13_fpArccosPiTest_s1 <= STD_LOGIC_VECTOR(prod_uid186_rAcosPi_uid13_fpArccosPiTest_pr);
END IF;
END IF;
END PROCESS;
prod_uid186_rAcosPi_uid13_fpArccosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid186_rAcosPi_uid13_fpArccosPiTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid186_rAcosPi_uid13_fpArccosPiTest_q <= prod_uid186_rAcosPi_uid13_fpArccosPiTest_s1;
END IF;
END IF;
END PROCESS;
--normalizeBit_uid187_rAcosPi_uid13_fpArccosPiTest(BITSELECT,186)@46
normalizeBit_uid187_rAcosPi_uid13_fpArccosPiTest_in <= prod_uid186_rAcosPi_uid13_fpArccosPiTest_q;
normalizeBit_uid187_rAcosPi_uid13_fpArccosPiTest_b <= normalizeBit_uid187_rAcosPi_uid13_fpArccosPiTest_in(47 downto 47);
--fracRPostNormHigh_uid189_rAcosPi_uid13_fpArccosPiTest(BITSELECT,188)@46
fracRPostNormHigh_uid189_rAcosPi_uid13_fpArccosPiTest_in <= prod_uid186_rAcosPi_uid13_fpArccosPiTest_q(46 downto 0);
fracRPostNormHigh_uid189_rAcosPi_uid13_fpArccosPiTest_b <= fracRPostNormHigh_uid189_rAcosPi_uid13_fpArccosPiTest_in(46 downto 23);
--fracRPostNormLow_uid190_rAcosPi_uid13_fpArccosPiTest(BITSELECT,189)@46
fracRPostNormLow_uid190_rAcosPi_uid13_fpArccosPiTest_in <= prod_uid186_rAcosPi_uid13_fpArccosPiTest_q(45 downto 0);
fracRPostNormLow_uid190_rAcosPi_uid13_fpArccosPiTest_b <= fracRPostNormLow_uid190_rAcosPi_uid13_fpArccosPiTest_in(45 downto 22);
--fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest(MUX,190)@46
fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest_s <= normalizeBit_uid187_rAcosPi_uid13_fpArccosPiTest_b;
fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest: PROCESS (fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest_s, en, fracRPostNormLow_uid190_rAcosPi_uid13_fpArccosPiTest_b, fracRPostNormHigh_uid189_rAcosPi_uid13_fpArccosPiTest_b)
BEGIN
CASE fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest_s IS
WHEN "0" => fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest_q <= fracRPostNormLow_uid190_rAcosPi_uid13_fpArccosPiTest_b;
WHEN "1" => fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest_q <= fracRPostNormHigh_uid189_rAcosPi_uid13_fpArccosPiTest_b;
WHEN OTHERS => fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--FracRPostNorm1dto0_uid199_rAcosPi_uid13_fpArccosPiTest(BITSELECT,198)@46
FracRPostNorm1dto0_uid199_rAcosPi_uid13_fpArccosPiTest_in <= fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest_q(1 downto 0);
FracRPostNorm1dto0_uid199_rAcosPi_uid13_fpArccosPiTest_b <= FracRPostNorm1dto0_uid199_rAcosPi_uid13_fpArccosPiTest_in(1 downto 0);
--Prod22_uid193_rAcosPi_uid13_fpArccosPiTest(BITSELECT,192)@46
Prod22_uid193_rAcosPi_uid13_fpArccosPiTest_in <= prod_uid186_rAcosPi_uid13_fpArccosPiTest_q(22 downto 0);
Prod22_uid193_rAcosPi_uid13_fpArccosPiTest_b <= Prod22_uid193_rAcosPi_uid13_fpArccosPiTest_in(22 downto 22);
--extraStickyBit_uid194_rAcosPi_uid13_fpArccosPiTest(MUX,193)@46
extraStickyBit_uid194_rAcosPi_uid13_fpArccosPiTest_s <= normalizeBit_uid187_rAcosPi_uid13_fpArccosPiTest_b;
extraStickyBit_uid194_rAcosPi_uid13_fpArccosPiTest: PROCESS (extraStickyBit_uid194_rAcosPi_uid13_fpArccosPiTest_s, en, GND_q, Prod22_uid193_rAcosPi_uid13_fpArccosPiTest_b)
BEGIN
CASE extraStickyBit_uid194_rAcosPi_uid13_fpArccosPiTest_s IS
WHEN "0" => extraStickyBit_uid194_rAcosPi_uid13_fpArccosPiTest_q <= GND_q;
WHEN "1" => extraStickyBit_uid194_rAcosPi_uid13_fpArccosPiTest_q <= Prod22_uid193_rAcosPi_uid13_fpArccosPiTest_b;
WHEN OTHERS => extraStickyBit_uid194_rAcosPi_uid13_fpArccosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--stickyRange_uid192_rAcosPi_uid13_fpArccosPiTest(BITSELECT,191)@46
stickyRange_uid192_rAcosPi_uid13_fpArccosPiTest_in <= prod_uid186_rAcosPi_uid13_fpArccosPiTest_q(21 downto 0);
stickyRange_uid192_rAcosPi_uid13_fpArccosPiTest_b <= stickyRange_uid192_rAcosPi_uid13_fpArccosPiTest_in(21 downto 0);
--stickyExtendedRange_uid195_rAcosPi_uid13_fpArccosPiTest(BITJOIN,194)@46
stickyExtendedRange_uid195_rAcosPi_uid13_fpArccosPiTest_q <= extraStickyBit_uid194_rAcosPi_uid13_fpArccosPiTest_q & stickyRange_uid192_rAcosPi_uid13_fpArccosPiTest_b;
--stickyRangeComparator_uid197_rAcosPi_uid13_fpArccosPiTest(LOGICAL,196)@46
stickyRangeComparator_uid197_rAcosPi_uid13_fpArccosPiTest_a <= stickyExtendedRange_uid195_rAcosPi_uid13_fpArccosPiTest_q;
stickyRangeComparator_uid197_rAcosPi_uid13_fpArccosPiTest_b <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q;
stickyRangeComparator_uid197_rAcosPi_uid13_fpArccosPiTest_q <= "1" when stickyRangeComparator_uid197_rAcosPi_uid13_fpArccosPiTest_a = stickyRangeComparator_uid197_rAcosPi_uid13_fpArccosPiTest_b else "0";
--sticky_uid198_rAcosPi_uid13_fpArccosPiTest(LOGICAL,197)@46
sticky_uid198_rAcosPi_uid13_fpArccosPiTest_a <= stickyRangeComparator_uid197_rAcosPi_uid13_fpArccosPiTest_q;
sticky_uid198_rAcosPi_uid13_fpArccosPiTest_q <= not sticky_uid198_rAcosPi_uid13_fpArccosPiTest_a;
--lrs_uid200_rAcosPi_uid13_fpArccosPiTest(BITJOIN,199)@46
lrs_uid200_rAcosPi_uid13_fpArccosPiTest_q <= FracRPostNorm1dto0_uid199_rAcosPi_uid13_fpArccosPiTest_b & sticky_uid198_rAcosPi_uid13_fpArccosPiTest_q;
--roundBitDetectionPattern_uid202_rAcosPi_uid13_fpArccosPiTest(LOGICAL,201)@46
roundBitDetectionPattern_uid202_rAcosPi_uid13_fpArccosPiTest_a <= lrs_uid200_rAcosPi_uid13_fpArccosPiTest_q;
roundBitDetectionPattern_uid202_rAcosPi_uid13_fpArccosPiTest_b <= roundBitDetectionConstant_uid201_rAcosPi_uid13_fpArccosPiTest_q;
roundBitDetectionPattern_uid202_rAcosPi_uid13_fpArccosPiTest_q <= "1" when roundBitDetectionPattern_uid202_rAcosPi_uid13_fpArccosPiTest_a = roundBitDetectionPattern_uid202_rAcosPi_uid13_fpArccosPiTest_b else "0";
--roundBit_uid203_rAcosPi_uid13_fpArccosPiTest(LOGICAL,202)@46
roundBit_uid203_rAcosPi_uid13_fpArccosPiTest_a <= roundBitDetectionPattern_uid202_rAcosPi_uid13_fpArccosPiTest_q;
roundBit_uid203_rAcosPi_uid13_fpArccosPiTest_q <= not roundBit_uid203_rAcosPi_uid13_fpArccosPiTest_a;
--roundBitAndNormalizationOp_uid206_rAcosPi_uid13_fpArccosPiTest(BITJOIN,205)@46
roundBitAndNormalizationOp_uid206_rAcosPi_uid13_fpArccosPiTest_q <= GND_q & normalizeBit_uid187_rAcosPi_uid13_fpArccosPiTest_b & cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q & roundBit_uid203_rAcosPi_uid13_fpArccosPiTest_q;
--reg_roundBitAndNormalizationOp_uid206_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_1(REG,704)@46
reg_roundBitAndNormalizationOp_uid206_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_roundBitAndNormalizationOp_uid206_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_roundBitAndNormalizationOp_uid206_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_1_q <= roundBitAndNormalizationOp_uid206_rAcosPi_uid13_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid143_rAcosPi_uid13_fpArccosPiTest_b_to_expSum_uid183_rAcosPi_uid13_fpArccosPiTest_a(DELAY,874)@42
ld_expX_uid143_rAcosPi_uid13_fpArccosPiTest_b_to_expSum_uid183_rAcosPi_uid13_fpArccosPiTest_a : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid143_rAcosPi_uid13_fpArccosPiTest_b, xout => ld_expX_uid143_rAcosPi_uid13_fpArccosPiTest_b_to_expSum_uid183_rAcosPi_uid13_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--expSum_uid183_rAcosPi_uid13_fpArccosPiTest(ADD,182)@43
expSum_uid183_rAcosPi_uid13_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid143_rAcosPi_uid13_fpArccosPiTest_b_to_expSum_uid183_rAcosPi_uid13_fpArccosPiTest_a_q);
expSum_uid183_rAcosPi_uid13_fpArccosPiTest_b <= STD_LOGIC_VECTOR("0" & expY_uid144_rAcosPi_uid13_fpArccosPiTest_b);
expSum_uid183_rAcosPi_uid13_fpArccosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSum_uid183_rAcosPi_uid13_fpArccosPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSum_uid183_rAcosPi_uid13_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid183_rAcosPi_uid13_fpArccosPiTest_a) + UNSIGNED(expSum_uid183_rAcosPi_uid13_fpArccosPiTest_b));
END IF;
END IF;
END PROCESS;
expSum_uid183_rAcosPi_uid13_fpArccosPiTest_q <= expSum_uid183_rAcosPi_uid13_fpArccosPiTest_o(8 downto 0);
--ld_expSum_uid183_rAcosPi_uid13_fpArccosPiTest_q_to_expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_a(DELAY,876)@44
ld_expSum_uid183_rAcosPi_uid13_fpArccosPiTest_q_to_expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_a : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => expSum_uid183_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_expSum_uid183_rAcosPi_uid13_fpArccosPiTest_q_to_expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest(SUB,184)@45
expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & ld_expSum_uid183_rAcosPi_uid13_fpArccosPiTest_q_to_expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_a_q);
expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_b <= STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid184_rAcosPi_uid13_fpArccosPiTest_q(9)) & biasInc_uid184_rAcosPi_uid13_fpArccosPiTest_q);
expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_a) - SIGNED(expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_b));
END IF;
END IF;
END PROCESS;
expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_q <= expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_o(10 downto 0);
--expFracPreRound_uid204_rAcosPi_uid13_fpArccosPiTest(BITJOIN,203)@46
expFracPreRound_uid204_rAcosPi_uid13_fpArccosPiTest_q <= expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_q & fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest_q;
--reg_expFracPreRound_uid204_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_0(REG,703)@46
reg_expFracPreRound_uid204_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRound_uid204_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_0_q <= "00000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expFracPreRound_uid204_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_0_q <= expFracPreRound_uid204_rAcosPi_uid13_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest(ADD,206)@47
expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_a <= STD_LOGIC_VECTOR((36 downto 35 => reg_expFracPreRound_uid204_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_0_q(34)) & reg_expFracPreRound_uid204_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_0_q);
expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_roundBitAndNormalizationOp_uid206_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_1_q);
expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_a) + SIGNED(expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_b));
expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_q <= expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_o(35 downto 0);
--expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest(BITSELECT,208)@47
expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_in <= expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_q;
expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_b <= expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_in(35 downto 24);
--expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest(BITSELECT,209)@47
expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_in <= expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_b(7 downto 0);
expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_b <= expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_in(7 downto 0);
--ld_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_b_to_reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3_a(DELAY,1447)@47
ld_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_b_to_reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3_a : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_b, xout => ld_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_b_to_reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3(REG,716)@48
reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3_q <= ld_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_b_to_reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3_a_q;
END IF;
END IF;
END PROCESS;
--ld_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_q_to_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_c(DELAY,948)@44
ld_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_q_to_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_q_to_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--reg_expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_0_to_expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_1(REG,705)@47
reg_expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_0_to_expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_0_to_expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_0_to_expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_1_q <= expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_b;
END IF;
END IF;
END PROCESS;
--expOvf_uid214_rAcosPi_uid13_fpArccosPiTest(COMPARE,213)@48
expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_cin <= GND_q;
expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_0_to_expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_1_q(11)) & reg_expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_0_to_expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_1_q) & '0';
expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_b <= STD_LOGIC_VECTOR('0' & "00000" & cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q) & expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_cin(0);
expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_a) - SIGNED(expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_b));
expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_n(0) <= not expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_o(14);
--InvExc_N_uid179_rAcosPi_uid13_fpArccosPiTest(LOGICAL,178)@43
InvExc_N_uid179_rAcosPi_uid13_fpArccosPiTest_a <= exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_q;
InvExc_N_uid179_rAcosPi_uid13_fpArccosPiTest_q <= not InvExc_N_uid179_rAcosPi_uid13_fpArccosPiTest_a;
--InvExc_I_uid180_rAcosPi_uid13_fpArccosPiTest(LOGICAL,179)@43
InvExc_I_uid180_rAcosPi_uid13_fpArccosPiTest_a <= exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_q;
InvExc_I_uid180_rAcosPi_uid13_fpArccosPiTest_q <= not InvExc_I_uid180_rAcosPi_uid13_fpArccosPiTest_a;
--InvExpXIsZero_uid181_rAcosPi_uid13_fpArccosPiTest(LOGICAL,180)@43
InvExpXIsZero_uid181_rAcosPi_uid13_fpArccosPiTest_a <= expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_q;
InvExpXIsZero_uid181_rAcosPi_uid13_fpArccosPiTest_q <= not InvExpXIsZero_uid181_rAcosPi_uid13_fpArccosPiTest_a;
--exc_R_uid182_rAcosPi_uid13_fpArccosPiTest(LOGICAL,181)@43
exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_a <= InvExpXIsZero_uid181_rAcosPi_uid13_fpArccosPiTest_q;
exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_b <= InvExc_I_uid180_rAcosPi_uid13_fpArccosPiTest_q;
exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_c <= InvExc_N_uid179_rAcosPi_uid13_fpArccosPiTest_q;
exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_q <= exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_a and exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_b and exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_c;
--ld_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_b(DELAY,918)@43
ld_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid163_rAcosPi_uid13_fpArccosPiTest(LOGICAL,162)@42
InvExc_N_uid163_rAcosPi_uid13_fpArccosPiTest_a <= exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_q;
InvExc_N_uid163_rAcosPi_uid13_fpArccosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExc_N_uid163_rAcosPi_uid13_fpArccosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExc_N_uid163_rAcosPi_uid13_fpArccosPiTest_q <= not InvExc_N_uid163_rAcosPi_uid13_fpArccosPiTest_a;
END IF;
END PROCESS;
--InvExc_I_uid164_rAcosPi_uid13_fpArccosPiTest(LOGICAL,163)@42
InvExc_I_uid164_rAcosPi_uid13_fpArccosPiTest_a <= exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_q;
InvExc_I_uid164_rAcosPi_uid13_fpArccosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExc_I_uid164_rAcosPi_uid13_fpArccosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExc_I_uid164_rAcosPi_uid13_fpArccosPiTest_q <= not InvExc_I_uid164_rAcosPi_uid13_fpArccosPiTest_a;
END IF;
END PROCESS;
--InvExpXIsZero_uid165_rAcosPi_uid13_fpArccosPiTest(LOGICAL,164)@42
InvExpXIsZero_uid165_rAcosPi_uid13_fpArccosPiTest_a <= expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_q;
InvExpXIsZero_uid165_rAcosPi_uid13_fpArccosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
InvExpXIsZero_uid165_rAcosPi_uid13_fpArccosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN
InvExpXIsZero_uid165_rAcosPi_uid13_fpArccosPiTest_q <= not InvExpXIsZero_uid165_rAcosPi_uid13_fpArccosPiTest_a;
END IF;
END PROCESS;
--exc_R_uid166_rAcosPi_uid13_fpArccosPiTest(LOGICAL,165)@43
exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_a <= InvExpXIsZero_uid165_rAcosPi_uid13_fpArccosPiTest_q;
exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_b <= InvExc_I_uid164_rAcosPi_uid13_fpArccosPiTest_q;
exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_c <= InvExc_N_uid163_rAcosPi_uid13_fpArccosPiTest_q;
exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_q <= exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_a and exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_b and exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_c;
--ld_exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_a(DELAY,917)@43
ld_exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest(LOGICAL,222)@48
ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_a <= ld_exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_a_q;
ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_b <= ld_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_b_q;
ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_c <= expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_n;
ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_q <= ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_a and ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_b and ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_c;
--reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_1(REG,706)@42
reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_1_q <= exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_2_q_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_b(DELAY,929)@43
ld_reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_2_q_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_1_q, xout => ld_reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_2_q_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_0_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_1(REG,707)@43
reg_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_0_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_0_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_0_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_1_q <= exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest(LOGICAL,221)@44
excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_a <= reg_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_0_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_1_q;
excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_b <= ld_reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_2_q_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_b_q;
excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_q <= excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_a and excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_b;
--ld_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_c(DELAY,935)@44
ld_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest(LOGICAL,220)@43
excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_a <= exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_q;
excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_b <= exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_q;
excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_q <= excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_a and excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_b;
--ld_excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_b(DELAY,934)@43
ld_excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest(LOGICAL,219)@43
excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_a <= reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_1_q;
excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_b <= exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_q;
excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_q <= excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_a and excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_b;
--ld_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_a(DELAY,933)@43
ld_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRInf_uid224_rAcosPi_uid13_fpArccosPiTest(LOGICAL,223)@48
excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_a <= ld_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_a_q;
excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_b <= ld_excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_b_q;
excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_c <= ld_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_c_q;
excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_d <= ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_q;
excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_q <= excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_a or excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_b or excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_c or excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_d;
--expUdf_uid212_rAcosPi_uid13_fpArccosPiTest(COMPARE,211)@48
expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_cin <= GND_q;
expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_a <= STD_LOGIC_VECTOR('0' & "000000000000" & GND_q) & '0';
expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_b <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_0_to_expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_1_q(11)) & reg_expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_0_to_expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_1_q) & expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_cin(0);
expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_a) - SIGNED(expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_b));
expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_n(0) <= not expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_o(14);
--excZC3_uid218_rAcosPi_uid13_fpArccosPiTest(LOGICAL,217)@48
excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_a <= ld_exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_a_q;
excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_b <= ld_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_b_q;
excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_c <= expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_n;
excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_q <= excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_a and excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_b and excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_c;
--excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest(LOGICAL,216)@43
excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_a <= expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_q;
excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_b <= exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_q;
excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_q <= excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_a and excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_b;
--ld_excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_c(DELAY,922)@43
ld_excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest(LOGICAL,215)@43
excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_a <= ld_expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_q_to_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_a_q;
excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_b <= exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_q;
excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_q <= excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_a and excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_b;
--ld_excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_b(DELAY,921)@43
ld_excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest(LOGICAL,214)@43
excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_a <= ld_expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_q_to_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_a_q;
excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_b <= expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_q;
excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_q <= excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_a and excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_b;
--ld_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_a(DELAY,920)@43
ld_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 5 )
PORT MAP ( xin => excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRZero_uid219_rAcosPi_uid13_fpArccosPiTest(LOGICAL,218)@48
excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_a <= ld_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_a_q;
excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_b <= ld_excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_b_q;
excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_c <= ld_excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_c_q;
excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_d <= excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_q;
excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_q <= excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_a or excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_b or excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_c or excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_d;
--concExc_uid229_rAcosPi_uid13_fpArccosPiTest(BITJOIN,228)@48
concExc_uid229_rAcosPi_uid13_fpArccosPiTest_q <= ld_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_q_to_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_c_q & excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_q & excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_q;
--reg_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_0_to_excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_0(REG,714)@48
reg_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_0_to_excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_0_to_excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_0_to_excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_0_q <= concExc_uid229_rAcosPi_uid13_fpArccosPiTest_q;
END IF;
END IF;
END PROCESS;
--excREnc_uid230_rAcosPi_uid13_fpArccosPiTest(LOOKUP,229)@49
excREnc_uid230_rAcosPi_uid13_fpArccosPiTest: PROCESS (reg_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_0_to_excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_0_to_excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_0_q) IS
WHEN "000" => excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q <= "01";
WHEN "001" => excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q <= "00";
WHEN "010" => excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q <= "10";
WHEN "011" => excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q <= "00";
WHEN "100" => excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q <= "11";
WHEN "101" => excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q <= "00";
WHEN "110" => excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q <= "00";
WHEN "111" => excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q <= "00";
WHEN OTHERS =>
excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest(MUX,238)@49
expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_s <= excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q;
expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest: PROCESS (expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_s, en, cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q, reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3_q, cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q, cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q)
BEGIN
CASE expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_s IS
WHEN "00" => expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_q <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q;
WHEN "01" => expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_q <= reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3_q;
WHEN "10" => expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_q <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q;
WHEN "11" => expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_q <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q;
WHEN OTHERS => expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest(BITSELECT,207)@47
fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_in <= expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_q(23 downto 0);
fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_b <= fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_in(23 downto 1);
--reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3(REG,715)@47
reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3_q <= fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3_q_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_d(DELAY,951)@48
ld_reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3_q_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_d : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3_q, xout => ld_reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3_q_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_d_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest(MUX,233)@49
fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_s <= excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q;
fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest: PROCESS (fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_s, en, cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q, ld_reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3_q_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_d_q, cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q, cstNaNWF_uid20_acosX_uid8_fpArccosPiTest_q)
BEGIN
CASE fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_s IS
WHEN "00" => fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_q <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q;
WHEN "01" => fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_q <= ld_reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3_q_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_d_q;
WHEN "10" => fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_q <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q;
WHEN "11" => fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_q <= cstNaNWF_uid20_acosX_uid8_fpArccosPiTest_q;
WHEN OTHERS => fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid242_rAcosPi_uid13_fpArccosPiTest(BITJOIN,241)@49
R_uid242_rAcosPi_uid13_fpArccosPiTest_q <= ld_signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_q_to_R_uid242_rAcosPi_uid13_fpArccosPiTest_c_q & expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_q & fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_q;
--xOut(GPOUT,4)@49
q <= R_uid242_rAcosPi_uid13_fpArccosPiTest_q;
end normal;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
bin_Gaussian_Filter/ip/Gaussian_Filter/dp_invsqr.vhd
|
10
|
10246
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION INVERSE SQUARE ROOT ***
--*** TOP LEVEL ***
--*** ***
--*** DP_INVSQR.VHD ***
--*** ***
--*** Function: IEEE754 DP Inverse Square Root ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 11/08/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** ***
--*** Stratix II ***
--*** Latency = 32 + 2*Speed ***
--*** Speed = 0 : 32 ***
--*** Speed = 1 : 34 ***
--*** ***
--*** Stratix III/IV ***
--*** Latency = 31 + Speed ***
--*** Speed = 0 : 31 ***
--*** Speed = 1 : 32 ***
--*** ***
--***************************************************
ENTITY dp_invsqr IS
GENERIC (
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
doublespeed : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin: IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC
);
END dp_invsqr;
ARCHITECTURE rtl OF dp_invsqr IS
constant manwidth : positive := 52;
constant expwidth : positive := 11;
constant coredepth : positive := 31+2*doublespeed - device*(1+doublespeed);
type expfftype IS ARRAY (coredepth+1 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (coredepth+1 DOWNTO 1);
signal correctff : STD_LOGIC_VECTOR (3 DOWNTO 1); -- SPR 383712
signal expff : expfftype;
signal radicand : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal oddexponent : STD_LOGIC;
signal invroot : STD_LOGIC_VECTOR (54 DOWNTO 1);
--signal invroottest : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal offset : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
-- conditions
signal nanmanff, nanexpff : STD_LOGIC_VECTOR (coredepth-1 DOWNTO 1);
signal zeroexpff, zeromanff : STD_LOGIC_VECTOR (coredepth-2 DOWNTO 1);
signal expinzero, expinmax : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal maninzero : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal expzero, expmax, manzero : STD_LOGIC;
signal infinityconditionff, nanconditionff, expzeroff : STD_LOGIC;
signal correct_powers_of_two : STD_LOGIC; -- SPR 383712
component dp_invsqr_core IS
GENERIC (
doublespeed : integer := 0; -- 0/1
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
odd : IN STD_LOGIC;
invroot : OUT STD_LOGIC_VECTOR (54 DOWNTO 1)
);
end component;
BEGIN
gzva: FOR k IN 1 TO manwidth GENERATE
zerovec(k) <= '0';
END GENERATE;
gxoa: FOR k IN 1 TO expwidth-1 GENERATE
offset(k) <= '1';
END GENERATE;
offset(expwidth) <= '0';
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO manwidth LOOP
maninff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
expinff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth+1 LOOP
signff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth+1 LOOP
FOR j IN 1 TO expwidth LOOP
expff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO manwidth LOOP
manff(k) <= '0';
END LOOP;
correctff <= "000"; -- SPR 383712
ELSIF (rising_edge(sysclk)) THEN
maninff <= mantissain;
expinff <= exponentin;
signff(1) <= signin;
FOR k IN 2 TO coredepth+1 LOOP
signff(k) <= signff(k-1);
END LOOP;
expff(1)(expwidth DOWNTO 1) <= exponentin;
expff(2)(expwidth DOWNTO 1) <= expff(1)(expwidth DOWNTO 1) - offset;
expff(3)(expwidth DOWNTO 1) <= expff(2)(expwidth) & expff(2)(expwidth DOWNTO 2);
expff(4)(expwidth DOWNTO 1) <= offset - expff(3)(expwidth DOWNTO 1);
expff(5)(expwidth DOWNTO 1) <= expff(4)(expwidth DOWNTO 1) - 1 + correctff(3);
FOR k IN 6 TO coredepth LOOP
expff(k)(expwidth DOWNTO 1) <= expff(k-1)(expwidth DOWNTO 1);
END LOOP;
FOR k IN 1 TO expwidth LOOP
expff(coredepth+1)(k) <= (expff(coredepth)(k) AND zeroexpff(coredepth-2)) OR nanexpff(coredepth-2);
END LOOP;
-- SPR 383712
correctff(1) <= correct_powers_of_two;
correctff(2) <= correctff(1);
correctff(3) <= correctff(2);
FOR k IN 1 TO manwidth LOOP
manff(k) <= (invroot(k+1) AND zeromanff(coredepth-2)) OR nanmanff(coredepth-2);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** CONDITIONS ***
--*******************
pcc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO coredepth-1 LOOP
nanmanff(k) <= '0';
nanexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO coredepth-2 LOOP
zeroexpff(k) <= '0';
zeromanff(k) <= '0';
END LOOP;
infinityconditionff <= '0';
nanconditionff <= '0';
expzeroff <= '0';
ELSIF (rising_edge(sysclk)) THEN
infinityconditionff <= manzero AND expmax;
nanconditionff <= signff(1) OR expzero OR (expmax AND manzero);
expzeroff <= expzero;
nanmanff(1) <= nanconditionff; -- level 3
nanexpff(1) <= nanconditionff OR infinityconditionff; -- also max exp when infinity
FOR k IN 2 TO coredepth-1 LOOP
nanmanff(k) <= nanmanff(k-1);
nanexpff(k) <= nanexpff(k-1);
END LOOP;
zeromanff(1) <= NOT(expzeroff) AND NOT(infinityconditionff); -- level 3
zeroexpff(1) <= NOT(expzeroff); -- level 3
FOR k IN 2 TO coredepth-2 LOOP
zeromanff(k) <= zeromanff(k-1);
zeroexpff(k) <= zeroexpff(k-1);
END LOOP;
END IF;
END PROCESS;
--*******************
--*** SQUARE ROOT ***
--*******************
radicand <= '1' & mantissain & '0';
-- sub 1023, so 1023 (odd) = 2^0 => even
oddexponent <= NOT(exponentin(1));
-- does not require rounding, output of core rounded already, LSB always 0
isqr: dp_invsqr_core
GENERIC MAP (doublespeed=>doublespeed,doubleaccuracy=>doubleaccuracy,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radicand=>radicand,odd=>oddexponent,
invroot=>invroot);
--*********************
--*** SPECIAL CASES ***
--*********************
-- 1. if negative input, invalid operation, NAN
-- 2. 0 in, invalid operation, NAN
-- 3. infinity in, invalid operation, infinity out
-- 4. NAN in, invalid operation, NAN
-- '1' if 0
expinzero(1) <= expinff(1);
gxza: FOR k IN 2 TO expwidth GENERATE
expinzero(k) <= expinzero(k-1) OR expinff(k);
END GENERATE;
expzero <= NOT(expinzero(expwidth)); -- '0' when zero
-- '1' if nan or infinity
expinmax(1) <= expinff(1);
gxia: FOR k IN 2 TO expwidth GENERATE
expinmax(k) <= expinmax(k-1) AND expinff(k);
END GENERATE;
expmax <= expinmax(expwidth); -- '1' when true
-- '1' if zero or infinity
maninzero(1) <= maninff(1);
gmza: FOR k IN 2 TO manwidth GENERATE
maninzero(k) <= maninzero(k-1) OR maninff(k);
END GENERATE;
manzero <= NOT(maninzero(manwidth));
-- 09/03/11 ML
-- if mantissa is 0 and exponent is odd (...123,125,127,129,131...) then dont subtract 1 from offset corrected exponent
-- '1' is subtracted as any value, no matter how small, in the mantissa will reduce the inverse below the mirrored exponent (around 127)
-- if the exponent is odd (with mantissa 0) the value is a power of 2 (...0.25,0.5,1,2,4...) and the mirrored exponent is correct
-- if the exponent is even (with mantissa 0), the inverse square root will have a non zero mantissa and can be handled normally
correct_powers_of_two <= manzero AND expinff(1); -- SPR 383712
--***************
--*** OUTPUTS ***
--***************
signout <= signff(coredepth+1);
exponentout <= expff(coredepth+1)(expwidth DOWNTO 1);
mantissaout <= manff;
-----------------------------------------------
nanout <= nanmanff(coredepth-1);
invalidout <= nanmanff(coredepth-1);
END rtl;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
bin_Gaussian_Filter/ip/Gaussian_Filter/hcc_castltoy.vhd
|
10
|
2035
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTLTOY.VHD ***
--*** ***
--*** Function: Cast Long to Internal Double ***
--*** Format ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castltoy IS
GENERIC (
unsigned : integer := 0 -- 0 = signed, 1 = unsigned
);
PORT (
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (77 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_castltoy;
ARCHITECTURE rtl OF hcc_castltoy IS
signal fit : STD_LOGIC;
signal exponentfit, exponentnofit : STD_LOGIC_VECTOR (10 DOWNTO 1);
BEGIN
gxa: IF (unsigned = 0) GENERATE
cc(77 DOWNTO 73) <= aa(32) & aa(32) & aa(32) & aa(32) & aa(32);
END GENERATE;
gxb: IF (unsigned = 1) GENERATE
cc(77 DOWNTO 73) <= "00000";
END GENERATE;
cc(72 DOWNTO 41) <= aa;
gza: FOR k IN 14 TO 40 GENERATE
cc(k) <= '0';
END GENERATE;
cc(13 DOWNTO 1) <= conv_std_logic_vector (1054,13); -- account for 31bit right shift
ccsat <= '0';
cczip <= '0';
END rtl;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
bin_Gaussian_Filter/ip/Gaussian_Filter/hcc_alufp1_dot_sv.vhd
|
10
|
12467
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_ALUFP1_DOT.VHD ***
--*** ***
--*** Function: Single Precision Floating Point ***
--*** Adder (Signed Magnitude for first level ***
--*** Vector Optimized Structure) ***
--*** ***
--*** 15/10/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--*** TBD - what if exponents negative ***
ENTITY hcc_alufp1_dot IS
GENERIC (
mantissa : positive := 32;
shiftspeed : integer := 0;
outputpipe : integer := 1; -- 0 = no pipe, 1 = pipe (for this function only - input, not output pipes affected)
addsub_resetval : std_logic
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
addsub : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip, aanan : IN STD_LOGIC;
bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
bbsat, bbzip, bbnan : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip, ccnan : OUT STD_LOGIC
);
END hcc_alufp1_dot;
ARCHITECTURE rtl OF hcc_alufp1_dot IS
type exponentbasefftype IS ARRAY (3+shiftspeed DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1);
-- input registers and nodes
signal aasignff, bbsignff : STD_LOGIC;
signal aamantissaff, bbmantissaff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aaexponentff, bbexponentff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC;
signal aananff, bbnanff : STD_LOGIC;
signal addsubff : STD_LOGIC;
signal aasignnode, bbsignnode : STD_LOGIC;
signal aamantissanode, bbmantissanode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aaexponentnode, bbexponentnode : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aasatnode, aazipnode, bbsatnode, bbzipnode : STD_LOGIC;
signal aanannode, bbnannode : STD_LOGIC;
signal addsubnode : STD_LOGIC;
signal mantissaleftff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal mantissarightff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal mantissaleftdelayff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal exponentshiftff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal exponentbaseff : exponentbasefftype;
signal invertleftff, invertrightff : STD_LOGIC_VECTOR (2+shiftspeed DOWNTO 1);
signal shiftcheckff, shiftcheckdelayff : STD_LOGIC;
signal aluleftff, alurightff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal aluff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal ccsatff, cczipff, ccnanff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1);
signal mantissaleftnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal zeroaluright : STD_LOGIC;
signal aluleftnode, alurightnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
signal alucarrybitnode : STD_LOGIC;
signal subexponentone, subexponenttwo : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal switch : STD_LOGIC;
signal shiftcheck : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal shiftcheckbit : STD_LOGIC;
signal shiftbusnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_rsftpipe32
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftpipe36
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_rsftcomb32
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_rsftcomb36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pin: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
aasignff <= '0';
bbsignff <= '0';
FOR k IN 1 TO mantissa LOOP
aamantissaff(k) <= '0';
bbmantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
aaexponentff(k) <= '0';
bbexponentff(k) <= '0';
END LOOP;
aasatff <= '0';
bbsatff <= '0';
aazipff <= '0';
bbzipff <= '0';
aananff <= '0';
bbnanff <= '0';
addsubff <= addsub_resetval;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aasignff <= aa(mantissa+10);
bbsignff <= bb(mantissa+10);
aamantissaff <= '0'& aa(mantissa+9 DOWNTO 11);
bbmantissaff <= '0'& bb(mantissa+9 DOWNTO 11);
aaexponentff <= aa(10 DOWNTO 1);
bbexponentff <= bb(10 DOWNTO 1);
aasatff <= aasat;
bbsatff <= bbsat;
aazipff <= aazip;
bbzipff <= bbzip;
aananff <= aanan;
bbnanff <= bbnan;
addsubff <= addsub;
END IF;
END IF;
END PROCESS;
gina: IF (outputpipe = 1) GENERATE
aasignnode <= aasignff;
aamantissanode <= aamantissaff;
aaexponentnode <= aaexponentff;
bbsignnode <= bbsignff;
bbmantissanode <= bbmantissaff;
bbexponentnode <= bbexponentff;
aasatnode <= aasatff;
bbsatnode <= bbsatff;
aazipnode <= aazipff;
bbzipnode <= bbzipff;
aanannode <= aananff;
bbnannode <= bbnanff;
addsubnode <= addsubff;
END GENERATE;
ginb: IF (outputpipe = 0) GENERATE
aasignnode <= aa(mantissa+10);
bbsignnode <= bb(mantissa+10);
aamantissanode <= '0'& aa(mantissa+9 DOWNTO 11);
bbmantissanode <= '0'& bb(mantissa+9 DOWNTO 11);
aaexponentnode <= aa(10 DOWNTO 1);
bbexponentnode <= bb(10 DOWNTO 1);
aasatnode <= aasat;
bbsatnode <= bbsat;
aazipnode <= aazip;
bbzipnode <= bbzip;
aanannode <= aanan;
bbnannode <= bbnan;
addsubnode <= addsub;
END GENERATE;
paa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO mantissa LOOP
mantissaleftff(k) <= '0';
mantissarightff(k) <= '0';
mantissaleftdelayff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
exponentshiftff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
FOR j IN 1 TO 10 LOOP
exponentbaseff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO 2+shiftspeed LOOP
invertleftff(k) <= '0';
invertrightff(k) <= '0';
END LOOP;
shiftcheckff <= '0';
shiftcheckdelayff <= '0';
FOR k IN 1 TO mantissa LOOP
aluleftff(k) <= '0';
alurightff(k) <= '0';
aluff(k) <= '0';
END LOOP;
FOR k IN 1 TO 3+shiftspeed LOOP
ccsatff(k) <= '0';
cczipff(k) <= '0';
ccnanff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO mantissa LOOP
mantissaleftff(k) <= (aamantissanode(k) AND NOT(switch)) OR (bbmantissanode(k) AND switch);
mantissarightff(k) <= (bbmantissanode(k) AND NOT(switch)) OR (aamantissanode(k) AND switch);
END LOOP;
-- only use if shiftspeed = 1
mantissaleftdelayff <= mantissaleftff;
FOR k IN 1 TO 10 LOOP
exponentshiftff(k) <= (subexponentone(k) AND NOT(switch)) OR (subexponenttwo(k) AND switch);
END LOOP;
FOR k IN 1 TO 10 LOOP
exponentbaseff(1)(k) <= (aaexponentnode(k) AND NOT(switch)) OR (bbexponentnode(k) AND switch);
END LOOP;
FOR k IN 2 TO 3+shiftspeed LOOP
exponentbaseff(k)(10 DOWNTO 1) <= exponentbaseff(k-1)(10 DOWNTO 1);
END LOOP;
invertleftff(1) <= ((aasignnode AND NOT(switch)) OR (bbsignnode AND switch)) XOR (addsubnode AND switch);
invertrightff(1) <= ((bbsignnode AND NOT(switch)) OR (aasignnode AND switch)) XOR (addsubnode AND NOT(switch));
FOR k IN 2 TO 2+shiftspeed LOOP
invertleftff(k) <= invertleftff(k-1);
invertrightff(k) <= invertrightff(k-1);
END LOOP;
shiftcheckff <= shiftcheckbit;
shiftcheckdelayff <= shiftcheckff;
aluleftff <= mantissaleftnode;
alurightff <= shiftbusnode;
aluff <= aluleftnode + alurightnode + alucarrybitnode;
ccsatff(1) <= aasatnode OR bbsatnode;
cczipff(1) <= aazipnode AND bbzipnode;
-- add/sub infinity is invalid OP, NAN out
ccnanff(1) <= aanannode OR bbnannode OR aasatnode OR bbsatnode;
FOR k IN 2 TO 3+shiftspeed LOOP
ccsatff(k) <= ccsatff(k-1);
cczipff(k) <= cczipff(k-1);
ccnanff(k) <= ccnanff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
gmsa: IF (shiftspeed = 0) GENERATE
mantissaleftnode <= mantissaleftff;
zeroaluright <= shiftcheckff;
END GENERATE;
gmsb: IF (shiftspeed = 1) GENERATE
mantissaleftnode <= mantissaleftdelayff;
zeroaluright <= shiftcheckdelayff;
END GENERATE;
gma: FOR k IN 1 TO mantissa GENERATE
aluleftnode(k) <= aluleftff(k) XOR invertleftff(2+shiftspeed);
alurightnode(k) <= (alurightff(k) XOR invertrightff(2+shiftspeed)) AND NOT(zeroaluright);
END GENERATE;
-- carrybit into ALU only if larger value is negated
alucarrybitnode <= invertleftff(2+shiftspeed);
subexponentone <= aaexponentnode(10 DOWNTO 1) - bbexponentnode(10 DOWNTO 1);
subexponenttwo <= bbexponentnode(10 DOWNTO 1) - aaexponentnode(10 DOWNTO 1);
switch <= subexponentone(10);
gsa: IF (mantissa = 32) GENERATE
-- 31 ok, 32 not
shiftcheck <= "0000000000";
-- if '1', then zero right bus
shiftcheckbit <= exponentshiftff(10) OR exponentshiftff(9) OR exponentshiftff(8) OR
exponentshiftff(7) OR exponentshiftff(6);
gsb: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb32
PORT MAP (inbus=>mantissarightff,shift=>exponentshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsc: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>mantissarightff,shift=>exponentshiftff(5 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
gsd: IF (mantissa = 36) GENERATE
-- 35 ok, 36 not
shiftcheck <= exponentshiftff - "0000100100";
-- if '1', then zero right bus
shiftcheckbit <= NOT(shiftcheck(10));
gse: IF (shiftspeed = 0) GENERATE
shiftone: hcc_rsftcomb36
PORT MAP (inbus=>mantissarightff,shift=>exponentshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
gsf: IF (shiftspeed = 1) GENERATE
shifttwo: hcc_rsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>mantissarightff,shift=>exponentshiftff(6 DOWNTO 1),
outbus=>shiftbusnode);
END GENERATE;
END GENERATE;
--*** OUTPUT ***
cc <= aluff & exponentbaseff(3+shiftspeed)(10 DOWNTO 1);
ccsat <= ccsatff(3+shiftspeed);
cczip <= cczipff(3+shiftspeed);
ccnan <= ccnanff(3+shiftspeed);
END rtl;
|
mit
|
Reiuiji/ECE368-Lab
|
Lab 3/VGA Part 2/mux8to1.vhd
|
12
|
1166
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Mux 8 to 1
-- Project Name: VGA Toplevel
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Select one bit from a byte
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MUX8to1 is
Port ( SEL : in STD_LOGIC_VECTOR (2 downto 0);
DATA : in STD_LOGIC_VECTOR (7 downto 0);
OUTPUT : out STD_LOGIC);
end MUX8to1;
architecture Behavioral of MUX8to1 is
signal SEL1 : STD_LOGIC_VECTOR (2 downto 0);
begin
SEL1<=SEL-2;
with SEL1 SELect
OUTPUT<= DATA(7) when "000" ,
DATA(6) when "001" ,
DATA(5) when "010" ,
DATA(4) when "011" ,
DATA(3) when "100" ,
DATA(2) when "101" ,
DATA(1) when "110" ,
DATA(0) when "111" ,
'0' when others;
end Behavioral;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
Gaussian_Filter/ip/Gaussian_Filter/fp_div_lut1.vhd
|
10
|
35988
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_DIV_LUT1.VHD ***
--*** ***
--*** Function: Look Up Table - Inverse ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_div_lut1 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
END fp_div_lut1;
ARCHITECTURE rtl OF fp_div_lut1 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "000000000" => data <= conv_std_logic_vector(2044,11);
WHEN "000000001" => data <= conv_std_logic_vector(2036,11);
WHEN "000000010" => data <= conv_std_logic_vector(2028,11);
WHEN "000000011" => data <= conv_std_logic_vector(2020,11);
WHEN "000000100" => data <= conv_std_logic_vector(2012,11);
WHEN "000000101" => data <= conv_std_logic_vector(2005,11);
WHEN "000000110" => data <= conv_std_logic_vector(1997,11);
WHEN "000000111" => data <= conv_std_logic_vector(1989,11);
WHEN "000001000" => data <= conv_std_logic_vector(1982,11);
WHEN "000001001" => data <= conv_std_logic_vector(1974,11);
WHEN "000001010" => data <= conv_std_logic_vector(1967,11);
WHEN "000001011" => data <= conv_std_logic_vector(1959,11);
WHEN "000001100" => data <= conv_std_logic_vector(1952,11);
WHEN "000001101" => data <= conv_std_logic_vector(1944,11);
WHEN "000001110" => data <= conv_std_logic_vector(1937,11);
WHEN "000001111" => data <= conv_std_logic_vector(1929,11);
WHEN "000010000" => data <= conv_std_logic_vector(1922,11);
WHEN "000010001" => data <= conv_std_logic_vector(1915,11);
WHEN "000010010" => data <= conv_std_logic_vector(1908,11);
WHEN "000010011" => data <= conv_std_logic_vector(1900,11);
WHEN "000010100" => data <= conv_std_logic_vector(1893,11);
WHEN "000010101" => data <= conv_std_logic_vector(1886,11);
WHEN "000010110" => data <= conv_std_logic_vector(1879,11);
WHEN "000010111" => data <= conv_std_logic_vector(1872,11);
WHEN "000011000" => data <= conv_std_logic_vector(1865,11);
WHEN "000011001" => data <= conv_std_logic_vector(1858,11);
WHEN "000011010" => data <= conv_std_logic_vector(1851,11);
WHEN "000011011" => data <= conv_std_logic_vector(1845,11);
WHEN "000011100" => data <= conv_std_logic_vector(1838,11);
WHEN "000011101" => data <= conv_std_logic_vector(1831,11);
WHEN "000011110" => data <= conv_std_logic_vector(1824,11);
WHEN "000011111" => data <= conv_std_logic_vector(1817,11);
WHEN "000100000" => data <= conv_std_logic_vector(1811,11);
WHEN "000100001" => data <= conv_std_logic_vector(1804,11);
WHEN "000100010" => data <= conv_std_logic_vector(1798,11);
WHEN "000100011" => data <= conv_std_logic_vector(1791,11);
WHEN "000100100" => data <= conv_std_logic_vector(1785,11);
WHEN "000100101" => data <= conv_std_logic_vector(1778,11);
WHEN "000100110" => data <= conv_std_logic_vector(1772,11);
WHEN "000100111" => data <= conv_std_logic_vector(1765,11);
WHEN "000101000" => data <= conv_std_logic_vector(1759,11);
WHEN "000101001" => data <= conv_std_logic_vector(1752,11);
WHEN "000101010" => data <= conv_std_logic_vector(1746,11);
WHEN "000101011" => data <= conv_std_logic_vector(1740,11);
WHEN "000101100" => data <= conv_std_logic_vector(1734,11);
WHEN "000101101" => data <= conv_std_logic_vector(1727,11);
WHEN "000101110" => data <= conv_std_logic_vector(1721,11);
WHEN "000101111" => data <= conv_std_logic_vector(1715,11);
WHEN "000110000" => data <= conv_std_logic_vector(1709,11);
WHEN "000110001" => data <= conv_std_logic_vector(1703,11);
WHEN "000110010" => data <= conv_std_logic_vector(1697,11);
WHEN "000110011" => data <= conv_std_logic_vector(1691,11);
WHEN "000110100" => data <= conv_std_logic_vector(1685,11);
WHEN "000110101" => data <= conv_std_logic_vector(1679,11);
WHEN "000110110" => data <= conv_std_logic_vector(1673,11);
WHEN "000110111" => data <= conv_std_logic_vector(1667,11);
WHEN "000111000" => data <= conv_std_logic_vector(1661,11);
WHEN "000111001" => data <= conv_std_logic_vector(1655,11);
WHEN "000111010" => data <= conv_std_logic_vector(1650,11);
WHEN "000111011" => data <= conv_std_logic_vector(1644,11);
WHEN "000111100" => data <= conv_std_logic_vector(1638,11);
WHEN "000111101" => data <= conv_std_logic_vector(1632,11);
WHEN "000111110" => data <= conv_std_logic_vector(1627,11);
WHEN "000111111" => data <= conv_std_logic_vector(1621,11);
WHEN "001000000" => data <= conv_std_logic_vector(1615,11);
WHEN "001000001" => data <= conv_std_logic_vector(1610,11);
WHEN "001000010" => data <= conv_std_logic_vector(1604,11);
WHEN "001000011" => data <= conv_std_logic_vector(1599,11);
WHEN "001000100" => data <= conv_std_logic_vector(1593,11);
WHEN "001000101" => data <= conv_std_logic_vector(1588,11);
WHEN "001000110" => data <= conv_std_logic_vector(1582,11);
WHEN "001000111" => data <= conv_std_logic_vector(1577,11);
WHEN "001001000" => data <= conv_std_logic_vector(1571,11);
WHEN "001001001" => data <= conv_std_logic_vector(1566,11);
WHEN "001001010" => data <= conv_std_logic_vector(1561,11);
WHEN "001001011" => data <= conv_std_logic_vector(1555,11);
WHEN "001001100" => data <= conv_std_logic_vector(1550,11);
WHEN "001001101" => data <= conv_std_logic_vector(1545,11);
WHEN "001001110" => data <= conv_std_logic_vector(1540,11);
WHEN "001001111" => data <= conv_std_logic_vector(1534,11);
WHEN "001010000" => data <= conv_std_logic_vector(1529,11);
WHEN "001010001" => data <= conv_std_logic_vector(1524,11);
WHEN "001010010" => data <= conv_std_logic_vector(1519,11);
WHEN "001010011" => data <= conv_std_logic_vector(1514,11);
WHEN "001010100" => data <= conv_std_logic_vector(1509,11);
WHEN "001010101" => data <= conv_std_logic_vector(1504,11);
WHEN "001010110" => data <= conv_std_logic_vector(1499,11);
WHEN "001010111" => data <= conv_std_logic_vector(1494,11);
WHEN "001011000" => data <= conv_std_logic_vector(1489,11);
WHEN "001011001" => data <= conv_std_logic_vector(1484,11);
WHEN "001011010" => data <= conv_std_logic_vector(1479,11);
WHEN "001011011" => data <= conv_std_logic_vector(1474,11);
WHEN "001011100" => data <= conv_std_logic_vector(1469,11);
WHEN "001011101" => data <= conv_std_logic_vector(1464,11);
WHEN "001011110" => data <= conv_std_logic_vector(1460,11);
WHEN "001011111" => data <= conv_std_logic_vector(1455,11);
WHEN "001100000" => data <= conv_std_logic_vector(1450,11);
WHEN "001100001" => data <= conv_std_logic_vector(1445,11);
WHEN "001100010" => data <= conv_std_logic_vector(1440,11);
WHEN "001100011" => data <= conv_std_logic_vector(1436,11);
WHEN "001100100" => data <= conv_std_logic_vector(1431,11);
WHEN "001100101" => data <= conv_std_logic_vector(1426,11);
WHEN "001100110" => data <= conv_std_logic_vector(1422,11);
WHEN "001100111" => data <= conv_std_logic_vector(1417,11);
WHEN "001101000" => data <= conv_std_logic_vector(1413,11);
WHEN "001101001" => data <= conv_std_logic_vector(1408,11);
WHEN "001101010" => data <= conv_std_logic_vector(1403,11);
WHEN "001101011" => data <= conv_std_logic_vector(1399,11);
WHEN "001101100" => data <= conv_std_logic_vector(1394,11);
WHEN "001101101" => data <= conv_std_logic_vector(1390,11);
WHEN "001101110" => data <= conv_std_logic_vector(1385,11);
WHEN "001101111" => data <= conv_std_logic_vector(1381,11);
WHEN "001110000" => data <= conv_std_logic_vector(1377,11);
WHEN "001110001" => data <= conv_std_logic_vector(1372,11);
WHEN "001110010" => data <= conv_std_logic_vector(1368,11);
WHEN "001110011" => data <= conv_std_logic_vector(1363,11);
WHEN "001110100" => data <= conv_std_logic_vector(1359,11);
WHEN "001110101" => data <= conv_std_logic_vector(1355,11);
WHEN "001110110" => data <= conv_std_logic_vector(1351,11);
WHEN "001110111" => data <= conv_std_logic_vector(1346,11);
WHEN "001111000" => data <= conv_std_logic_vector(1342,11);
WHEN "001111001" => data <= conv_std_logic_vector(1338,11);
WHEN "001111010" => data <= conv_std_logic_vector(1334,11);
WHEN "001111011" => data <= conv_std_logic_vector(1329,11);
WHEN "001111100" => data <= conv_std_logic_vector(1325,11);
WHEN "001111101" => data <= conv_std_logic_vector(1321,11);
WHEN "001111110" => data <= conv_std_logic_vector(1317,11);
WHEN "001111111" => data <= conv_std_logic_vector(1313,11);
WHEN "010000000" => data <= conv_std_logic_vector(1309,11);
WHEN "010000001" => data <= conv_std_logic_vector(1305,11);
WHEN "010000010" => data <= conv_std_logic_vector(1301,11);
WHEN "010000011" => data <= conv_std_logic_vector(1297,11);
WHEN "010000100" => data <= conv_std_logic_vector(1292,11);
WHEN "010000101" => data <= conv_std_logic_vector(1288,11);
WHEN "010000110" => data <= conv_std_logic_vector(1284,11);
WHEN "010000111" => data <= conv_std_logic_vector(1281,11);
WHEN "010001000" => data <= conv_std_logic_vector(1277,11);
WHEN "010001001" => data <= conv_std_logic_vector(1273,11);
WHEN "010001010" => data <= conv_std_logic_vector(1269,11);
WHEN "010001011" => data <= conv_std_logic_vector(1265,11);
WHEN "010001100" => data <= conv_std_logic_vector(1261,11);
WHEN "010001101" => data <= conv_std_logic_vector(1257,11);
WHEN "010001110" => data <= conv_std_logic_vector(1253,11);
WHEN "010001111" => data <= conv_std_logic_vector(1249,11);
WHEN "010010000" => data <= conv_std_logic_vector(1246,11);
WHEN "010010001" => data <= conv_std_logic_vector(1242,11);
WHEN "010010010" => data <= conv_std_logic_vector(1238,11);
WHEN "010010011" => data <= conv_std_logic_vector(1234,11);
WHEN "010010100" => data <= conv_std_logic_vector(1231,11);
WHEN "010010101" => data <= conv_std_logic_vector(1227,11);
WHEN "010010110" => data <= conv_std_logic_vector(1223,11);
WHEN "010010111" => data <= conv_std_logic_vector(1220,11);
WHEN "010011000" => data <= conv_std_logic_vector(1216,11);
WHEN "010011001" => data <= conv_std_logic_vector(1212,11);
WHEN "010011010" => data <= conv_std_logic_vector(1209,11);
WHEN "010011011" => data <= conv_std_logic_vector(1205,11);
WHEN "010011100" => data <= conv_std_logic_vector(1201,11);
WHEN "010011101" => data <= conv_std_logic_vector(1198,11);
WHEN "010011110" => data <= conv_std_logic_vector(1194,11);
WHEN "010011111" => data <= conv_std_logic_vector(1191,11);
WHEN "010100000" => data <= conv_std_logic_vector(1187,11);
WHEN "010100001" => data <= conv_std_logic_vector(1184,11);
WHEN "010100010" => data <= conv_std_logic_vector(1180,11);
WHEN "010100011" => data <= conv_std_logic_vector(1177,11);
WHEN "010100100" => data <= conv_std_logic_vector(1173,11);
WHEN "010100101" => data <= conv_std_logic_vector(1170,11);
WHEN "010100110" => data <= conv_std_logic_vector(1166,11);
WHEN "010100111" => data <= conv_std_logic_vector(1163,11);
WHEN "010101000" => data <= conv_std_logic_vector(1159,11);
WHEN "010101001" => data <= conv_std_logic_vector(1156,11);
WHEN "010101010" => data <= conv_std_logic_vector(1153,11);
WHEN "010101011" => data <= conv_std_logic_vector(1149,11);
WHEN "010101100" => data <= conv_std_logic_vector(1146,11);
WHEN "010101101" => data <= conv_std_logic_vector(1142,11);
WHEN "010101110" => data <= conv_std_logic_vector(1139,11);
WHEN "010101111" => data <= conv_std_logic_vector(1136,11);
WHEN "010110000" => data <= conv_std_logic_vector(1133,11);
WHEN "010110001" => data <= conv_std_logic_vector(1129,11);
WHEN "010110010" => data <= conv_std_logic_vector(1126,11);
WHEN "010110011" => data <= conv_std_logic_vector(1123,11);
WHEN "010110100" => data <= conv_std_logic_vector(1120,11);
WHEN "010110101" => data <= conv_std_logic_vector(1116,11);
WHEN "010110110" => data <= conv_std_logic_vector(1113,11);
WHEN "010110111" => data <= conv_std_logic_vector(1110,11);
WHEN "010111000" => data <= conv_std_logic_vector(1107,11);
WHEN "010111001" => data <= conv_std_logic_vector(1104,11);
WHEN "010111010" => data <= conv_std_logic_vector(1100,11);
WHEN "010111011" => data <= conv_std_logic_vector(1097,11);
WHEN "010111100" => data <= conv_std_logic_vector(1094,11);
WHEN "010111101" => data <= conv_std_logic_vector(1091,11);
WHEN "010111110" => data <= conv_std_logic_vector(1088,11);
WHEN "010111111" => data <= conv_std_logic_vector(1085,11);
WHEN "011000000" => data <= conv_std_logic_vector(1082,11);
WHEN "011000001" => data <= conv_std_logic_vector(1079,11);
WHEN "011000010" => data <= conv_std_logic_vector(1076,11);
WHEN "011000011" => data <= conv_std_logic_vector(1073,11);
WHEN "011000100" => data <= conv_std_logic_vector(1070,11);
WHEN "011000101" => data <= conv_std_logic_vector(1067,11);
WHEN "011000110" => data <= conv_std_logic_vector(1064,11);
WHEN "011000111" => data <= conv_std_logic_vector(1061,11);
WHEN "011001000" => data <= conv_std_logic_vector(1058,11);
WHEN "011001001" => data <= conv_std_logic_vector(1055,11);
WHEN "011001010" => data <= conv_std_logic_vector(1052,11);
WHEN "011001011" => data <= conv_std_logic_vector(1049,11);
WHEN "011001100" => data <= conv_std_logic_vector(1046,11);
WHEN "011001101" => data <= conv_std_logic_vector(1043,11);
WHEN "011001110" => data <= conv_std_logic_vector(1040,11);
WHEN "011001111" => data <= conv_std_logic_vector(1037,11);
WHEN "011010000" => data <= conv_std_logic_vector(1034,11);
WHEN "011010001" => data <= conv_std_logic_vector(1031,11);
WHEN "011010010" => data <= conv_std_logic_vector(1028,11);
WHEN "011010011" => data <= conv_std_logic_vector(1026,11);
WHEN "011010100" => data <= conv_std_logic_vector(1023,11);
WHEN "011010101" => data <= conv_std_logic_vector(1020,11);
WHEN "011010110" => data <= conv_std_logic_vector(1017,11);
WHEN "011010111" => data <= conv_std_logic_vector(1014,11);
WHEN "011011000" => data <= conv_std_logic_vector(1012,11);
WHEN "011011001" => data <= conv_std_logic_vector(1009,11);
WHEN "011011010" => data <= conv_std_logic_vector(1006,11);
WHEN "011011011" => data <= conv_std_logic_vector(1003,11);
WHEN "011011100" => data <= conv_std_logic_vector(1001,11);
WHEN "011011101" => data <= conv_std_logic_vector(998,11);
WHEN "011011110" => data <= conv_std_logic_vector(995,11);
WHEN "011011111" => data <= conv_std_logic_vector(992,11);
WHEN "011100000" => data <= conv_std_logic_vector(990,11);
WHEN "011100001" => data <= conv_std_logic_vector(987,11);
WHEN "011100010" => data <= conv_std_logic_vector(984,11);
WHEN "011100011" => data <= conv_std_logic_vector(982,11);
WHEN "011100100" => data <= conv_std_logic_vector(979,11);
WHEN "011100101" => data <= conv_std_logic_vector(976,11);
WHEN "011100110" => data <= conv_std_logic_vector(974,11);
WHEN "011100111" => data <= conv_std_logic_vector(971,11);
WHEN "011101000" => data <= conv_std_logic_vector(969,11);
WHEN "011101001" => data <= conv_std_logic_vector(966,11);
WHEN "011101010" => data <= conv_std_logic_vector(963,11);
WHEN "011101011" => data <= conv_std_logic_vector(961,11);
WHEN "011101100" => data <= conv_std_logic_vector(958,11);
WHEN "011101101" => data <= conv_std_logic_vector(956,11);
WHEN "011101110" => data <= conv_std_logic_vector(953,11);
WHEN "011101111" => data <= conv_std_logic_vector(951,11);
WHEN "011110000" => data <= conv_std_logic_vector(948,11);
WHEN "011110001" => data <= conv_std_logic_vector(946,11);
WHEN "011110010" => data <= conv_std_logic_vector(943,11);
WHEN "011110011" => data <= conv_std_logic_vector(941,11);
WHEN "011110100" => data <= conv_std_logic_vector(938,11);
WHEN "011110101" => data <= conv_std_logic_vector(936,11);
WHEN "011110110" => data <= conv_std_logic_vector(933,11);
WHEN "011110111" => data <= conv_std_logic_vector(931,11);
WHEN "011111000" => data <= conv_std_logic_vector(928,11);
WHEN "011111001" => data <= conv_std_logic_vector(926,11);
WHEN "011111010" => data <= conv_std_logic_vector(923,11);
WHEN "011111011" => data <= conv_std_logic_vector(921,11);
WHEN "011111100" => data <= conv_std_logic_vector(919,11);
WHEN "011111101" => data <= conv_std_logic_vector(916,11);
WHEN "011111110" => data <= conv_std_logic_vector(914,11);
WHEN "011111111" => data <= conv_std_logic_vector(911,11);
WHEN "100000000" => data <= conv_std_logic_vector(909,11);
WHEN "100000001" => data <= conv_std_logic_vector(907,11);
WHEN "100000010" => data <= conv_std_logic_vector(904,11);
WHEN "100000011" => data <= conv_std_logic_vector(902,11);
WHEN "100000100" => data <= conv_std_logic_vector(900,11);
WHEN "100000101" => data <= conv_std_logic_vector(897,11);
WHEN "100000110" => data <= conv_std_logic_vector(895,11);
WHEN "100000111" => data <= conv_std_logic_vector(893,11);
WHEN "100001000" => data <= conv_std_logic_vector(890,11);
WHEN "100001001" => data <= conv_std_logic_vector(888,11);
WHEN "100001010" => data <= conv_std_logic_vector(886,11);
WHEN "100001011" => data <= conv_std_logic_vector(884,11);
WHEN "100001100" => data <= conv_std_logic_vector(881,11);
WHEN "100001101" => data <= conv_std_logic_vector(879,11);
WHEN "100001110" => data <= conv_std_logic_vector(877,11);
WHEN "100001111" => data <= conv_std_logic_vector(875,11);
WHEN "100010000" => data <= conv_std_logic_vector(872,11);
WHEN "100010001" => data <= conv_std_logic_vector(870,11);
WHEN "100010010" => data <= conv_std_logic_vector(868,11);
WHEN "100010011" => data <= conv_std_logic_vector(866,11);
WHEN "100010100" => data <= conv_std_logic_vector(864,11);
WHEN "100010101" => data <= conv_std_logic_vector(861,11);
WHEN "100010110" => data <= conv_std_logic_vector(859,11);
WHEN "100010111" => data <= conv_std_logic_vector(857,11);
WHEN "100011000" => data <= conv_std_logic_vector(855,11);
WHEN "100011001" => data <= conv_std_logic_vector(853,11);
WHEN "100011010" => data <= conv_std_logic_vector(851,11);
WHEN "100011011" => data <= conv_std_logic_vector(848,11);
WHEN "100011100" => data <= conv_std_logic_vector(846,11);
WHEN "100011101" => data <= conv_std_logic_vector(844,11);
WHEN "100011110" => data <= conv_std_logic_vector(842,11);
WHEN "100011111" => data <= conv_std_logic_vector(840,11);
WHEN "100100000" => data <= conv_std_logic_vector(838,11);
WHEN "100100001" => data <= conv_std_logic_vector(836,11);
WHEN "100100010" => data <= conv_std_logic_vector(834,11);
WHEN "100100011" => data <= conv_std_logic_vector(832,11);
WHEN "100100100" => data <= conv_std_logic_vector(830,11);
WHEN "100100101" => data <= conv_std_logic_vector(827,11);
WHEN "100100110" => data <= conv_std_logic_vector(825,11);
WHEN "100100111" => data <= conv_std_logic_vector(823,11);
WHEN "100101000" => data <= conv_std_logic_vector(821,11);
WHEN "100101001" => data <= conv_std_logic_vector(819,11);
WHEN "100101010" => data <= conv_std_logic_vector(817,11);
WHEN "100101011" => data <= conv_std_logic_vector(815,11);
WHEN "100101100" => data <= conv_std_logic_vector(813,11);
WHEN "100101101" => data <= conv_std_logic_vector(811,11);
WHEN "100101110" => data <= conv_std_logic_vector(809,11);
WHEN "100101111" => data <= conv_std_logic_vector(807,11);
WHEN "100110000" => data <= conv_std_logic_vector(805,11);
WHEN "100110001" => data <= conv_std_logic_vector(803,11);
WHEN "100110010" => data <= conv_std_logic_vector(801,11);
WHEN "100110011" => data <= conv_std_logic_vector(799,11);
WHEN "100110100" => data <= conv_std_logic_vector(797,11);
WHEN "100110101" => data <= conv_std_logic_vector(796,11);
WHEN "100110110" => data <= conv_std_logic_vector(794,11);
WHEN "100110111" => data <= conv_std_logic_vector(792,11);
WHEN "100111000" => data <= conv_std_logic_vector(790,11);
WHEN "100111001" => data <= conv_std_logic_vector(788,11);
WHEN "100111010" => data <= conv_std_logic_vector(786,11);
WHEN "100111011" => data <= conv_std_logic_vector(784,11);
WHEN "100111100" => data <= conv_std_logic_vector(782,11);
WHEN "100111101" => data <= conv_std_logic_vector(780,11);
WHEN "100111110" => data <= conv_std_logic_vector(778,11);
WHEN "100111111" => data <= conv_std_logic_vector(777,11);
WHEN "101000000" => data <= conv_std_logic_vector(775,11);
WHEN "101000001" => data <= conv_std_logic_vector(773,11);
WHEN "101000010" => data <= conv_std_logic_vector(771,11);
WHEN "101000011" => data <= conv_std_logic_vector(769,11);
WHEN "101000100" => data <= conv_std_logic_vector(767,11);
WHEN "101000101" => data <= conv_std_logic_vector(765,11);
WHEN "101000110" => data <= conv_std_logic_vector(764,11);
WHEN "101000111" => data <= conv_std_logic_vector(762,11);
WHEN "101001000" => data <= conv_std_logic_vector(760,11);
WHEN "101001001" => data <= conv_std_logic_vector(758,11);
WHEN "101001010" => data <= conv_std_logic_vector(756,11);
WHEN "101001011" => data <= conv_std_logic_vector(755,11);
WHEN "101001100" => data <= conv_std_logic_vector(753,11);
WHEN "101001101" => data <= conv_std_logic_vector(751,11);
WHEN "101001110" => data <= conv_std_logic_vector(749,11);
WHEN "101001111" => data <= conv_std_logic_vector(747,11);
WHEN "101010000" => data <= conv_std_logic_vector(746,11);
WHEN "101010001" => data <= conv_std_logic_vector(744,11);
WHEN "101010010" => data <= conv_std_logic_vector(742,11);
WHEN "101010011" => data <= conv_std_logic_vector(740,11);
WHEN "101010100" => data <= conv_std_logic_vector(739,11);
WHEN "101010101" => data <= conv_std_logic_vector(737,11);
WHEN "101010110" => data <= conv_std_logic_vector(735,11);
WHEN "101010111" => data <= conv_std_logic_vector(734,11);
WHEN "101011000" => data <= conv_std_logic_vector(732,11);
WHEN "101011001" => data <= conv_std_logic_vector(730,11);
WHEN "101011010" => data <= conv_std_logic_vector(728,11);
WHEN "101011011" => data <= conv_std_logic_vector(727,11);
WHEN "101011100" => data <= conv_std_logic_vector(725,11);
WHEN "101011101" => data <= conv_std_logic_vector(723,11);
WHEN "101011110" => data <= conv_std_logic_vector(722,11);
WHEN "101011111" => data <= conv_std_logic_vector(720,11);
WHEN "101100000" => data <= conv_std_logic_vector(718,11);
WHEN "101100001" => data <= conv_std_logic_vector(717,11);
WHEN "101100010" => data <= conv_std_logic_vector(715,11);
WHEN "101100011" => data <= conv_std_logic_vector(713,11);
WHEN "101100100" => data <= conv_std_logic_vector(712,11);
WHEN "101100101" => data <= conv_std_logic_vector(710,11);
WHEN "101100110" => data <= conv_std_logic_vector(708,11);
WHEN "101100111" => data <= conv_std_logic_vector(707,11);
WHEN "101101000" => data <= conv_std_logic_vector(705,11);
WHEN "101101001" => data <= conv_std_logic_vector(704,11);
WHEN "101101010" => data <= conv_std_logic_vector(702,11);
WHEN "101101011" => data <= conv_std_logic_vector(700,11);
WHEN "101101100" => data <= conv_std_logic_vector(699,11);
WHEN "101101101" => data <= conv_std_logic_vector(697,11);
WHEN "101101110" => data <= conv_std_logic_vector(696,11);
WHEN "101101111" => data <= conv_std_logic_vector(694,11);
WHEN "101110000" => data <= conv_std_logic_vector(692,11);
WHEN "101110001" => data <= conv_std_logic_vector(691,11);
WHEN "101110010" => data <= conv_std_logic_vector(689,11);
WHEN "101110011" => data <= conv_std_logic_vector(688,11);
WHEN "101110100" => data <= conv_std_logic_vector(686,11);
WHEN "101110101" => data <= conv_std_logic_vector(685,11);
WHEN "101110110" => data <= conv_std_logic_vector(683,11);
WHEN "101110111" => data <= conv_std_logic_vector(682,11);
WHEN "101111000" => data <= conv_std_logic_vector(680,11);
WHEN "101111001" => data <= conv_std_logic_vector(679,11);
WHEN "101111010" => data <= conv_std_logic_vector(677,11);
WHEN "101111011" => data <= conv_std_logic_vector(676,11);
WHEN "101111100" => data <= conv_std_logic_vector(674,11);
WHEN "101111101" => data <= conv_std_logic_vector(672,11);
WHEN "101111110" => data <= conv_std_logic_vector(671,11);
WHEN "101111111" => data <= conv_std_logic_vector(669,11);
WHEN "110000000" => data <= conv_std_logic_vector(668,11);
WHEN "110000001" => data <= conv_std_logic_vector(667,11);
WHEN "110000010" => data <= conv_std_logic_vector(665,11);
WHEN "110000011" => data <= conv_std_logic_vector(664,11);
WHEN "110000100" => data <= conv_std_logic_vector(662,11);
WHEN "110000101" => data <= conv_std_logic_vector(661,11);
WHEN "110000110" => data <= conv_std_logic_vector(659,11);
WHEN "110000111" => data <= conv_std_logic_vector(658,11);
WHEN "110001000" => data <= conv_std_logic_vector(656,11);
WHEN "110001001" => data <= conv_std_logic_vector(655,11);
WHEN "110001010" => data <= conv_std_logic_vector(653,11);
WHEN "110001011" => data <= conv_std_logic_vector(652,11);
WHEN "110001100" => data <= conv_std_logic_vector(650,11);
WHEN "110001101" => data <= conv_std_logic_vector(649,11);
WHEN "110001110" => data <= conv_std_logic_vector(648,11);
WHEN "110001111" => data <= conv_std_logic_vector(646,11);
WHEN "110010000" => data <= conv_std_logic_vector(645,11);
WHEN "110010001" => data <= conv_std_logic_vector(643,11);
WHEN "110010010" => data <= conv_std_logic_vector(642,11);
WHEN "110010011" => data <= conv_std_logic_vector(641,11);
WHEN "110010100" => data <= conv_std_logic_vector(639,11);
WHEN "110010101" => data <= conv_std_logic_vector(638,11);
WHEN "110010110" => data <= conv_std_logic_vector(636,11);
WHEN "110010111" => data <= conv_std_logic_vector(635,11);
WHEN "110011000" => data <= conv_std_logic_vector(634,11);
WHEN "110011001" => data <= conv_std_logic_vector(632,11);
WHEN "110011010" => data <= conv_std_logic_vector(631,11);
WHEN "110011011" => data <= conv_std_logic_vector(630,11);
WHEN "110011100" => data <= conv_std_logic_vector(628,11);
WHEN "110011101" => data <= conv_std_logic_vector(627,11);
WHEN "110011110" => data <= conv_std_logic_vector(625,11);
WHEN "110011111" => data <= conv_std_logic_vector(624,11);
WHEN "110100000" => data <= conv_std_logic_vector(623,11);
WHEN "110100001" => data <= conv_std_logic_vector(621,11);
WHEN "110100010" => data <= conv_std_logic_vector(620,11);
WHEN "110100011" => data <= conv_std_logic_vector(619,11);
WHEN "110100100" => data <= conv_std_logic_vector(617,11);
WHEN "110100101" => data <= conv_std_logic_vector(616,11);
WHEN "110100110" => data <= conv_std_logic_vector(615,11);
WHEN "110100111" => data <= conv_std_logic_vector(613,11);
WHEN "110101000" => data <= conv_std_logic_vector(612,11);
WHEN "110101001" => data <= conv_std_logic_vector(611,11);
WHEN "110101010" => data <= conv_std_logic_vector(610,11);
WHEN "110101011" => data <= conv_std_logic_vector(608,11);
WHEN "110101100" => data <= conv_std_logic_vector(607,11);
WHEN "110101101" => data <= conv_std_logic_vector(606,11);
WHEN "110101110" => data <= conv_std_logic_vector(604,11);
WHEN "110101111" => data <= conv_std_logic_vector(603,11);
WHEN "110110000" => data <= conv_std_logic_vector(602,11);
WHEN "110110001" => data <= conv_std_logic_vector(601,11);
WHEN "110110010" => data <= conv_std_logic_vector(599,11);
WHEN "110110011" => data <= conv_std_logic_vector(598,11);
WHEN "110110100" => data <= conv_std_logic_vector(597,11);
WHEN "110110101" => data <= conv_std_logic_vector(595,11);
WHEN "110110110" => data <= conv_std_logic_vector(594,11);
WHEN "110110111" => data <= conv_std_logic_vector(593,11);
WHEN "110111000" => data <= conv_std_logic_vector(592,11);
WHEN "110111001" => data <= conv_std_logic_vector(591,11);
WHEN "110111010" => data <= conv_std_logic_vector(589,11);
WHEN "110111011" => data <= conv_std_logic_vector(588,11);
WHEN "110111100" => data <= conv_std_logic_vector(587,11);
WHEN "110111101" => data <= conv_std_logic_vector(586,11);
WHEN "110111110" => data <= conv_std_logic_vector(584,11);
WHEN "110111111" => data <= conv_std_logic_vector(583,11);
WHEN "111000000" => data <= conv_std_logic_vector(582,11);
WHEN "111000001" => data <= conv_std_logic_vector(581,11);
WHEN "111000010" => data <= conv_std_logic_vector(580,11);
WHEN "111000011" => data <= conv_std_logic_vector(578,11);
WHEN "111000100" => data <= conv_std_logic_vector(577,11);
WHEN "111000101" => data <= conv_std_logic_vector(576,11);
WHEN "111000110" => data <= conv_std_logic_vector(575,11);
WHEN "111000111" => data <= conv_std_logic_vector(574,11);
WHEN "111001000" => data <= conv_std_logic_vector(572,11);
WHEN "111001001" => data <= conv_std_logic_vector(571,11);
WHEN "111001010" => data <= conv_std_logic_vector(570,11);
WHEN "111001011" => data <= conv_std_logic_vector(569,11);
WHEN "111001100" => data <= conv_std_logic_vector(568,11);
WHEN "111001101" => data <= conv_std_logic_vector(566,11);
WHEN "111001110" => data <= conv_std_logic_vector(565,11);
WHEN "111001111" => data <= conv_std_logic_vector(564,11);
WHEN "111010000" => data <= conv_std_logic_vector(563,11);
WHEN "111010001" => data <= conv_std_logic_vector(562,11);
WHEN "111010010" => data <= conv_std_logic_vector(561,11);
WHEN "111010011" => data <= conv_std_logic_vector(560,11);
WHEN "111010100" => data <= conv_std_logic_vector(558,11);
WHEN "111010101" => data <= conv_std_logic_vector(557,11);
WHEN "111010110" => data <= conv_std_logic_vector(556,11);
WHEN "111010111" => data <= conv_std_logic_vector(555,11);
WHEN "111011000" => data <= conv_std_logic_vector(554,11);
WHEN "111011001" => data <= conv_std_logic_vector(553,11);
WHEN "111011010" => data <= conv_std_logic_vector(552,11);
WHEN "111011011" => data <= conv_std_logic_vector(551,11);
WHEN "111011100" => data <= conv_std_logic_vector(549,11);
WHEN "111011101" => data <= conv_std_logic_vector(548,11);
WHEN "111011110" => data <= conv_std_logic_vector(547,11);
WHEN "111011111" => data <= conv_std_logic_vector(546,11);
WHEN "111100000" => data <= conv_std_logic_vector(545,11);
WHEN "111100001" => data <= conv_std_logic_vector(544,11);
WHEN "111100010" => data <= conv_std_logic_vector(543,11);
WHEN "111100011" => data <= conv_std_logic_vector(542,11);
WHEN "111100100" => data <= conv_std_logic_vector(541,11);
WHEN "111100101" => data <= conv_std_logic_vector(540,11);
WHEN "111100110" => data <= conv_std_logic_vector(538,11);
WHEN "111100111" => data <= conv_std_logic_vector(537,11);
WHEN "111101000" => data <= conv_std_logic_vector(536,11);
WHEN "111101001" => data <= conv_std_logic_vector(535,11);
WHEN "111101010" => data <= conv_std_logic_vector(534,11);
WHEN "111101011" => data <= conv_std_logic_vector(533,11);
WHEN "111101100" => data <= conv_std_logic_vector(532,11);
WHEN "111101101" => data <= conv_std_logic_vector(531,11);
WHEN "111101110" => data <= conv_std_logic_vector(530,11);
WHEN "111101111" => data <= conv_std_logic_vector(529,11);
WHEN "111110000" => data <= conv_std_logic_vector(528,11);
WHEN "111110001" => data <= conv_std_logic_vector(527,11);
WHEN "111110010" => data <= conv_std_logic_vector(526,11);
WHEN "111110011" => data <= conv_std_logic_vector(525,11);
WHEN "111110100" => data <= conv_std_logic_vector(524,11);
WHEN "111110101" => data <= conv_std_logic_vector(523,11);
WHEN "111110110" => data <= conv_std_logic_vector(522,11);
WHEN "111110111" => data <= conv_std_logic_vector(521,11);
WHEN "111111000" => data <= conv_std_logic_vector(520,11);
WHEN "111111001" => data <= conv_std_logic_vector(519,11);
WHEN "111111010" => data <= conv_std_logic_vector(518,11);
WHEN "111111011" => data <= conv_std_logic_vector(517,11);
WHEN "111111100" => data <= conv_std_logic_vector(516,11);
WHEN "111111101" => data <= conv_std_logic_vector(515,11);
WHEN "111111110" => data <= conv_std_logic_vector(514,11);
WHEN "111111111" => data <= conv_std_logic_vector(513,11);
WHEN others => data <= conv_std_logic_vector(0,11);
END CASE;
END PROCESS;
END rtl;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
bin_Gaussian_Filter/ip/Gaussian_Filter/fp_cos.vhd
|
10
|
12425
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_COS1.VHD ***
--*** ***
--*** Function: Single Precision COS Core ***
--*** ***
--*** 10/01/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. Input < 0.5 radians, take sin(pi/2-input)***
--*** 2. latency = depth + range_depth (11) + 6 ***
--*** (1 less than sin) ***
--***************************************************
ENTITY fp_cos IS
GENERIC (
device : integer := 0;
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_cos;
ARCHITECTURE rtl of fp_cos IS
constant cordic_width : positive := width;
constant cordic_depth : positive := depth;
constant range_depth : positive := 11;
signal piovertwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
-- range reduction
signal circle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal negcircle : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrantsign, quadrantselect : STD_LOGIC;
signal positive_quadrant, negative_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fraction_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal one_term : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal quadrant : STD_LOGIC_VECTOR (34 DOWNTO 1);
-- circle to radians mult
signal radiansnode : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal indexcheck : STD_LOGIC_VECTOR (16 DOWNTO 1);
signal indexbit : STD_LOGIC;
signal signinff : STD_LOGIC_VECTOR (range_depth DOWNTO 1);
signal selectoutputff : STD_LOGIC_VECTOR (range_depth+cordic_depth+5 DOWNTO 1);
signal signcalcff : STD_LOGIC_VECTOR (cordic_depth+6 DOWNTO 1);
signal quadrant_sumff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal select_sincosff : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal fixed_sincos : STD_LOGIC_VECTOR (cordic_width DOWNTO 1);
signal fixed_sincosnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal fixed_sincosff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal countnode : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal mantissanormnode : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissanormff : STD_LOGIC_VECTOR (23 DOWNTO 1);
signal exponentnormnode : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal exponentnormff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal overflownode : STD_LOGIC_VECTOR (24 DOWNTO 1);
component fp_range1
GENERIC (device : integer);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
circle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1);
negcircle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_cordic_m1
GENERIC (
width : positive := 36;
depth : positive := 20;
indexpoint : positive := 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1]
indexbit : IN STD_LOGIC;
sincosbit : IN STD_LOGIC;
sincos : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_clz36 IS
PORT (
mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component fp_lsft36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- pi/2 = 1.57
piovertwo <= x"c90fdaa22";
zerovec <= x"000000000";
--*** RANGE REDUCTION ***
crr: fp_range1
GENERIC MAP(device=>device)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
signin=>signin,exponentin=>exponentin,mantissain=>mantissain,
circle=>circle,negcircle=>negcircle);
quadrantsign <= (NOT(circle(36)) AND circle(35)) OR
(circle(36) AND NOT(circle(35))); -- cos negative in quadrants 2&3
quadrantselect <= circle(35); -- cos (1-x) in quadants 2&4
gra: FOR k IN 1 TO 34 GENERATE
quadrant(k) <= (circle(k) AND NOT(quadrantselect)) OR
(negcircle(k) AND quadrantselect);
END GENERATE;
-- if quadrant >0.5 (when quadrant(34) = 1), use quadrant, else use 1-quadrant, and take sin rather than cos
-- do this to maximize input value, not output value
positive_quadrant <= '0' & quadrant & '0';
gnqa: FOR k IN 1 TO 36 GENERATE
negative_quadrant(k) <= NOT(positive_quadrant(k));
fraction_quadrant(k) <= (positive_quadrant(k) AND quadrant(34)) OR
(negative_quadrant(k) AND NOT(quadrant(34)));
END GENERATE;
one_term <= NOT(quadrant(34)) & zerovec(35 DOWNTO 1); -- 0 if positive quadrant
pfa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO range_depth LOOP
signinff(k) <= '0';
END LOOP;
FOR k IN 1 TO cordic_depth+6 LOOP
signcalcff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
quadrant_sumff(k) <= '0';
END LOOP;
FOR k IN 1 TO 4 LOOP
select_sincosff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signinff(1) <= signin;
FOR k IN 2 TO range_depth LOOP
signinff(k) <= signinff(k-1);
END LOOP;
-- level range_depth+1 to range_depth+cordic_depth+6
signcalcff(1) <= quadrantsign;
FOR k IN 2 TO cordic_depth+6 LOOP
signcalcff(k) <= signcalcff(k-1);
END LOOP;
-- range 0-0.9999
quadrant_sumff <= one_term + fraction_quadrant + quadrant(34); -- level range_depth+1
-- level range depth+1 to range_depth+4
select_sincosff(1) <= NOT(quadrant(34));
FOR k IN 2 TO 4 LOOP
select_sincosff(k) <= select_sincosff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
-- levels range_depth+2,3,4
cmul: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>cordic_width,
pipes=>3,synthesize=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>quadrant_sumff,databb=>piovertwo,
result=>radiansnode);
indexcheck(1) <= radiansnode(cordic_width-1);
gica: FOR k IN 2 TO 16 GENERATE
indexcheck(k) <= indexcheck(k-1) OR radiansnode(cordic_width-k);
END GENERATE;
-- for safety, give an extra bit of space
indexbit <= NOT(indexcheck(indexpoint+1));
ccc: fp_cordic_m1
GENERIC MAP (width=>cordic_width,depth=>cordic_depth,indexpoint=>indexpoint)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radians=>radiansnode,
indexbit=>indexbit,
sincosbit=>select_sincosff(4),
sincos=>fixed_sincos);
gfxa: IF (width < 36) GENERATE
fixed_sincosnode <= fixed_sincos & zerovec(36-width DOWNTO 1);
END GENERATE;
gfxb: IF (width = 36) GENERATE
fixed_sincosnode <= fixed_sincos;
END GENERATE;
clz: fp_clz36
PORT MAP (mantissa=>fixed_sincosnode,leading=>countnode);
sft: fp_lsft36
PORT MAP (inbus=>fixed_sincosff,shift=>countff,
outbus=>mantissanormnode);
-- maximum sin or cos = 1.0 = 1.0e127 single precision
-- 1e128 - 1 (leading one) gives correct number
exponentnormnode <= "10000000" - ("00" & countff);
overflownode(1) <= mantissanormnode(12);
gova: FOR k IN 2 TO 24 GENERATE
overflownode(k) <= mantissanormnode(k+11) AND overflownode(k-1);
END GENERATE;
-- OUTPUT
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
fixed_sincosff(k) <= '0';
END LOOP;
countff <= "000000";
FOR k IN 1 TO 23 LOOP
mantissanormff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentnormff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
fixed_sincosff <= fixed_sincosnode; -- level range_depth+cordic_depth+5
countff <= countnode; -- level range_depth+4+cordic_depth+5
-- level range_depth+cordic_depth+6
mantissanormff <= mantissanormnode(35 DOWNTO 13) + mantissanormnode(12);
exponentnormff <= exponentnormnode(8 DOWNTO 1) + overflownode(24);
END IF;
END IF;
END PROCESS;
mantissaout <= mantissanormff;
exponentout <= exponentnormff;
signout <= signcalcff(cordic_depth+6);
END rtl;
|
mit
|
Reiuiji/ECE368-Lab
|
Lab 2/ALU/alu_mux.vhd
|
12
|
2229
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_MUX
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Mux unit
-- Output what ALU operation requested
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU_Mux is
Port ( OP : in STD_LOGIC_VECTOR (3 downto 0);
ARITH : in STD_LOGIC_VECTOR (7 downto 0);
LOGIC : in STD_LOGIC_VECTOR (7 downto 0);
SHIFT : in STD_LOGIC_VECTOR (7 downto 0);
MEMORY : in STD_LOGIC_VECTOR (7 downto 0);
CCR_ARITH : in STD_LOGIC_VECTOR (3 downto 0);
CCR_LOGIC : in STD_LOGIC_VECTOR (3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR (7 downto 0);
CCR_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end ALU_Mux;
architecture Combinational of ALU_Mux is
begin
with OP select
ALU_OUT <=
ARITH when "0000", -- ADD
ARITH when "0001", -- SUB
LOGIC when "0010", -- AND
LOGIC when "0011", -- OR
LOGIC when "0100", -- CMP
ARITH when "0101", -- ADDI
LOGIC when "0110", -- ANDI
SHIFT when "0111", -- SL
SHIFT when "1000", -- SR
MEMORY when "1001", -- LW
MEMORY when OTHERS; -- SW
with OP select
CCR_OUT <=
CCR_ARITH when "0000", -- ADD
CCR_ARITH when "0001", -- SUB
CCR_LOGIC when "0010", -- AND
CCR_LOGIC when "0011", -- OR
CCR_LOGIC when "0100", -- CMP
CCR_ARITH when "0101", -- ADDI
CCR_LOGIC when "0110", -- ANDI
"0000" when OTHERS; -- All flags cleared for other LOGIC operations
end Combinational;
|
mit
|
Reiuiji/ECE368-Lab
|
Lab 2/ALU/alu_logic_unit.vhd
|
12
|
1560
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Logic_Unit
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Logic Unit
-- Operations - AND, OR, CMP, ANDI
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Logic_Unit is
Port ( A : in STD_LOGIC_VECTOR (7 downto 0);
B : in STD_LOGIC_VECTOR (7 downto 0);
OP : in STD_LOGIC_VECTOR (2 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
RESULT : out STD_LOGIC_VECTOR (7 downto 0));
end Logic_Unit;
architecture Combinational of Logic_Unit is
signal cmp: STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
begin
with OP select
RESULT <=
A and B when "010", -- AND REG A, REG B
A or B when "011", -- OR REG A, REG B
x"00" when "100", -- CMP REG A, REG B
A and B when OTHERS;-- ANDI REG A, IMMED
--Compare Operation
cmp(3) <= '1' when a<b else '0'; -- N when s<r
cmp(2) <= '1' when a=b else '0'; -- Z when s=r
-- Choose CCR output
with OP select
ccr <=
cmp when "100",
"0000" when OTHERS;
end Combinational;
|
mit
|
Reiuiji/ECE368-Lab
|
Lab 3/Keyboard/misc/we_delay.vhd
|
1
|
948
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Keycode to Ascii
-- Project Name: Keyboard Controller
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Delay the Write Enable Line
-- Delay the Write Line to allow the ascii bus
-- to propagate through before able to read.
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity WE_DELAY is
Port ( WE_IN_1 : in STD_LOGIC;
WE_IN_2 : in STD_LOGIC;
WE_OUT_1 : out STD_LOGIC;
WE_OUT_2 : out STD_LOGIC);
end WE_DELAY;
architecture delay of WE_DELAY is
begin
WE_OUT_1 <= transport WE_IN_1 after 10 ns;
WE_OUT_2 <= transport WE_IN_2 after 10 ns;
end delay;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
bin_Gaussian_Filter/ip/Gaussian_Filter/FPSinCosXDPS4f375_safe_path.vhd
|
10
|
427
|
-- safe_path for FPSinCosXDPS4f375 given rtl dir is . (quartus)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
PACKAGE FPSinCosXDPS4f375_safe_path is
FUNCTION safe_path( path: string ) RETURN string;
END FPSinCosXDPS4f375_safe_path;
PACKAGE body FPSinCosXDPS4f375_safe_path IS
FUNCTION safe_path( path: string )
RETURN string IS
BEGIN
return string'("./") & path;
END FUNCTION safe_path;
END FPSinCosXDPS4f375_safe_path;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
Gaussian_Filter/ip/Gaussian_Filter/dp_floatfix.vhd
|
10
|
12529
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CONVERSION - TOP LEVEL ***
--*** ***
--*** DP_FLOATFIX.VHD ***
--*** ***
--*** Function: Convert Floating Point to Fixed ***
--*** Point Number ***
--*** ***
--*** 07/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** LATENCY : ***
--*** speed = 0 : 3 ***
--*** speed = 1 : 5 ***
--***************************************************
--***************************************************
--*** OUTPUT FORMAT - UNSIGNED ***
--*** maximum number is (2^decimal)-1, else ***
--*** saturate. if input negative, zero output ***
--*** OUTPUT FORMAT - SIGNED ***
--*** maximum number is (2^decimal-1)-1, else ***
--*** saturate ***
--***************************************************
ENTITY dp_floatfix IS
GENERIC (
unsigned : integer := 1; -- unsigned = 0, signed = 1
decimal : integer := 14;
fractional : integer := 6;
precision : integer := 0; -- single = 0, double = 1
speed : integer := 0 -- low speed = 0, high speed = 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
sign : IN STD_LOGIC;
exponent : IN STD_LOGIC_VECTOR (8+3*precision DOWNTO 1);
mantissa : IN STD_LOGIC_VECTOR (23+29*precision DOWNTO 1);
fixed_number : OUT STD_LOGIC_VECTOR (decimal+fractional DOWNTO 1)
);
END dp_floatfix;
ARCHITECTURE rtl of dp_floatfix IS
constant fixed_width : positive := decimal + fractional;
constant mantissa_width : positive := 23 + 29*precision;
constant exponent_width : positive := 8 + 3*precision;
constant exponent_base_number : positive := 127+896*precision;
-- input stage
signal zerovec : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal exponent_base_node : STD_LOGIC_VECTOR (exponent_width+1 DOWNTO 1);
signal saturate_check : STD_LOGIC_VECTOR (exponent_width+1 DOWNTO 1);
signal saturate_output, zero_output : STD_LOGIC;
signal saturate_apply, zero_apply : STD_LOGIC;
signal sign_apply : STD_LOGIC;
signal signed_mantissa_node : STD_LOGIC_VECTOR (mantissa_width+2 DOWNTO 1);
signal signed_mantissa_comp : STD_LOGIC_VECTOR (mantissa_width+2 DOWNTO 1);
signal signed_mantissa : STD_LOGIC_VECTOR (mantissa_width+2 DOWNTO 1);
signal input_vector : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal negexponent : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
signal expbase, negexpbase : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
signal leftshift, rightshift : STD_LOGIC_VECTOR (exponent_width DOWNTO 1);
-- shift stage
signal leftbus, rightbus : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal shiftbus, shiftbusff : STD_LOGIC_VECTOR (fixed_width DOWNTO 1);
signal select_bit : STD_LOGIC;
-- output stage
signal fixed_numberff : STD_LOGIC_VECTOR (fixed_width DOWNTO 1);
component dp_addpipe IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component dp_lsft64x64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1)
);
end component;
component dp_lsftpipe64x64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1)
);
end component;
component dp_rsft64x64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1)
);
end component;
component dp_rsftpipe64x64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1)
);
end component;
component fp_delbit IS
GENERIC (
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC;
cc : OUT STD_LOGIC
);
end component;
BEGIN
gera : IF NOT((unsigned = 0) OR
(unsigned = 1)) GENERATE
assert false report "unsigned must be 0 or 1" severity error;
END GENERATE;
gerb : IF NOT((precision = 0) OR
(precision = 1)) GENERATE
assert false report "precision must be 0 (single precision) or 1 (double precision)" severity error;
END GENERATE;
gerc : IF NOT((speed = 0) OR
(speed = 1)) GENERATE
assert false report "speed must be 0 or 1" severity error;
END GENERATE;
gerd : IF (decimal < 2) GENERATE
assert false report "decimal must be greater than 2" severity error;
END GENERATE;
gere : IF (fixed_width > 64) GENERATE
assert false report "maximum fixed point precision must be 64 or less" severity error;
END GENERATE;
gza: FOR k IN 1 TO 116 GENERATE
zerovec(k) <= '0';
END GENERATE;
--*** LEVEL 1-2 ***
-- level 1 if speed = 0
-- level 2 if speed = 1
-- check for zero and saturate conditions
exponent_base_node <= conv_std_logic_vector(exponent_base_number,exponent_width+1);
gzsa: IF (unsigned = 0) GENERATE
saturate_check <= exponent - exponent_base_node - decimal;
-- '1' when condition true
saturate_output <= NOT(saturate_check(exponent_width+1));
zero_output <= sign;
END GENERATE;
gzsb: IF (unsigned = 1) GENERATE
saturate_check <= exponent - exponent_base_node - decimal + 1;
-- '1' when condition true
saturate_output <= NOT(saturate_check(exponent_width+1));
zero_output <= '0';
dss: fp_delbit
GENERIC MAP (pipes=>2+2*speed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>sign,
cc=>sign_apply);
END GENERATE;
ds: fp_delbit
GENERIC MAP (pipes=>2+2*speed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>saturate_output,
cc=>saturate_apply);
dz: fp_delbit
GENERIC MAP (pipes=>2+2*speed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>zero_output,
cc=>zero_apply);
signed_mantissa_node <= "01" & mantissa;
gsma: FOR k IN 1 TO mantissa_width+2 GENERATE
signed_mantissa_comp(k) <= signed_mantissa_node(k) XOR sign;
END GENERATE;
addtop: dp_addpipe
GENERIC MAP (width=>mantissa_width+2,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>signed_mantissa_comp,bb=>zerovec(mantissa_width+2 DOWNTO 1),
carryin=>sign,
cc=>signed_mantissa);
giva: FOR k IN 116-decimal+3 TO 116 GENERATE
input_vector(k) <= signed_mantissa(mantissa_width+2);
END GENERATE;
input_vector(116-decimal+2 DOWNTO 116-decimal-mantissa_width+1) <= signed_mantissa;
givb: IF (116-decimal-mantissa_width+1 > 1) GENERATE
input_vector(116-decimal-mantissa_width DOWNTO 1) <= zerovec(116-decimal-mantissa_width DOWNTO 1);
END GENERATE;
gcxa: FOR k IN 1 TO exponent_width GENERATE
negexponent(k) <= NOT(exponent(k));
END GENERATE;
gcxb: FOR k IN 1 TO exponent_width-1 GENERATE
expbase(k) <= '1';
negexpbase(k) <= '0';
END GENERATE;
expbase(exponent_width) <= '0';
negexpbase(exponent_width) <= '1';
sublx: dp_addpipe
GENERIC MAP (width=>exponent_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>exponent,bb=>negexpbase,
carryin=>'1',
cc=>leftshift);
subrx: dp_addpipe
GENERIC MAP (width=>exponent_width,pipes=>speed+1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>negexponent,bb=>expbase,
carryin=>'1',
cc=>rightshift);
--*** LEVEL 2-4 (shiftbusff) ***
-- level 2 if speed = 0
-- level 4 if speed = 1
gsfa: IF (speed = 0) GENERATE
clsc: dp_lsft64x64
PORT MAP (inbus=>input_vector,shift=>leftshift(6 DOWNTO 1),
outbus=>leftbus);
crsc: dp_rsft64x64
PORT MAP (inbus=>input_vector,shift=>rightshift(6 DOWNTO 1),
outbus=>rightbus);
select_bit <= leftshift(exponent_width);
END GENERATE;
gsfb: IF (speed = 1) GENERATE
clsp: dp_lsftpipe64x64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>input_vector,shift=>leftshift(6 DOWNTO 1),
outbus=>leftbus);
crsp: dp_rsftpipe64x64
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>input_vector,shift=>rightshift(6 DOWNTO 1),
outbus=>rightbus);
db: fp_delbit
GENERIC MAP (pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>leftshift(exponent_width),
cc=>select_bit);
END GENERATE;
gsba: FOR k IN 1 TO fixed_width GENERATE
shiftbus(k) <= (leftbus(116-fixed_width+k) AND NOT(select_bit)) OR
(rightbus(116-fixed_width+k) AND select_bit);
END GENERATE;
psa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO fixed_width LOOP
shiftbusff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftbusff <= shiftbus;
END IF;
END IF;
END PROCESS;
--*** LEVEL 3-5 ***
-- level 3 if speed = 0
-- level 5 if speed = 1
gou: IF (unsigned = 0) GENERATE
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO fixed_width LOOP
fixed_numberff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO fixed_width LOOP
fixed_numberff(k) <= (shiftbusff(k) AND NOT(zero_apply)) OR saturate_apply;
END LOOP;
END IF;
END IF;
END PROCESS;
END GENERATE;
gos: IF (unsigned = 1) GENERATE
pos: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO fixed_width LOOP
fixed_numberff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
FOR k IN 1 TO fixed_width-1 LOOP
fixed_numberff(k) <= (shiftbusff(k) AND NOT(zero_apply) AND
NOT(saturate_apply AND sign_apply)) OR
(saturate_apply AND NOT(sign_apply));
END LOOP;
fixed_numberff(fixed_width) <= (shiftbusff(fixed_width) AND NOT(zero_apply) AND
NOT(saturate_apply AND NOT(sign_apply))) OR
(saturate_apply AND sign_apply);
END IF;
END IF;
END PROCESS;
END GENERATE;
fixed_number <= fixed_numberff;
END rtl;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
Gaussian_Filter/ip/Gaussian_Filter/fp_divrnd.vhd
|
10
|
6587
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION DIVIDER - OUTPUT STAGE ***
--*** ***
--*** FP_DIVRND.VHD ***
--*** ***
--*** Function: Output Stage, Rounding ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 2 ***
--***************************************************
ENTITY fp_divrnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentdiv : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
mantissadiv : IN STD_LOGIC_VECTOR (24 DOWNTO 1); -- includes roundbit
nanin : IN STD_LOGIC;
dividebyzeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
END fp_divrnd;
ARCHITECTURE rtl OF fp_divrnd IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal dividebyzeroff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal overflowbitff : STD_LOGIC;
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal infinitygen : STD_LOGIC_VECTOR (expwidth+1 DOWNTO 1);
signal zerogen : STD_LOGIC_VECTOR (expwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
signal setmanzeroff, setmanmaxff : STD_LOGIC;
signal setexpzeroff, setexpmaxff : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= "00";
nanff <= "00";
dividebyzeroff <= "00";
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
overflowbitff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
signff(1) <= signin;
signff(2) <= signff(1);
nanff(1) <= nanin;
nanff(2) <= nanff(1);
dividebyzeroff(1) <= dividebyzeroin;
dividebyzeroff(2) <= dividebyzeroff(1);
roundmantissaff <= mantissadiv(manwidth+1 DOWNTO 2) + (zerovec & mantissadiv(1));
overflowbitff <= manoverflow(manwidth+1);
-- nan takes precedence (set max)
-- nan takes precedence (set max)
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND setmanzero) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= exponentdiv(expwidth+2 DOWNTO 1);
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND setexpzero) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & overflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissadiv(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissadiv(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- infinity if exponent >= 255
infinitygen(1) <= exponentnode(1);
gia: FOR k IN 2 TO expwidth GENERATE
infinitygen(k) <= infinitygen(k-1) AND exponentnode(k);
END GENERATE;
infinitygen(expwidth+1) <= infinitygen(expwidth) OR
(exponentnode(expwidth+1) AND
NOT(exponentnode(expwidth+2))); -- ;1' if infinity
-- zero if exponent <= 0
zerogen(1) <= exponentnode(1);
gza: FOR k IN 2 TO expwidth GENERATE
zerogen(k) <= zerogen(k-1) OR exponentnode(k);
END GENERATE;
zerogen(expwidth+1) <= zerogen(expwidth) AND
NOT(exponentnode(expwidth+2)); -- '0' if zero
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(infinitygen(expwidth+1)) AND zerogen(expwidth+1) AND NOT(dividebyzeroff(1));
-- setmantissa to "11..11" when nan
setmanmax <= nanff(1);
-- set exponent to 0 when zero condition
setexpzero <= zerogen(expwidth+1);
-- set exponent to "11..11" when nan, infinity, or divide by 0
setexpmax <= nanff(1) OR infinitygen(expwidth+1) OR dividebyzeroff(1);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(2);
mantissaout <= mantissaff;
exponentout <= exponenttwoff(expwidth DOWNTO 1);
-----------------------------------------------
nanout <= nanff(2);
invalidout <= nanff(2);
dividebyzeroout <= dividebyzeroff(2);
END rtl;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
bin_Gaussian_Filter/ip/Gaussian_Filter/fp_divrnd.vhd
|
10
|
6587
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** SINGLE PRECISION DIVIDER - OUTPUT STAGE ***
--*** ***
--*** FP_DIVRND.VHD ***
--*** ***
--*** Function: Output Stage, Rounding ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: Latency = 2 ***
--***************************************************
ENTITY fp_divrnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentdiv : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
mantissadiv : IN STD_LOGIC_VECTOR (24 DOWNTO 1); -- includes roundbit
nanin : IN STD_LOGIC;
dividebyzeroin : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
invalidout : OUT STD_LOGIC;
dividebyzeroout : OUT STD_LOGIC
);
END fp_divrnd;
ARCHITECTURE rtl OF fp_divrnd IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal dividebyzeroff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal overflowbitff : STD_LOGIC;
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal infinitygen : STD_LOGIC_VECTOR (expwidth+1 DOWNTO 1);
signal zerogen : STD_LOGIC_VECTOR (expwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
signal setmanzeroff, setmanmaxff : STD_LOGIC;
signal setexpzeroff, setexpmaxff : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= "00";
nanff <= "00";
dividebyzeroff <= "00";
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
overflowbitff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
signff(1) <= signin;
signff(2) <= signff(1);
nanff(1) <= nanin;
nanff(2) <= nanff(1);
dividebyzeroff(1) <= dividebyzeroin;
dividebyzeroff(2) <= dividebyzeroff(1);
roundmantissaff <= mantissadiv(manwidth+1 DOWNTO 2) + (zerovec & mantissadiv(1));
overflowbitff <= manoverflow(manwidth+1);
-- nan takes precedence (set max)
-- nan takes precedence (set max)
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND setmanzero) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= exponentdiv(expwidth+2 DOWNTO 1);
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND setexpzero) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & overflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissadiv(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissadiv(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- infinity if exponent >= 255
infinitygen(1) <= exponentnode(1);
gia: FOR k IN 2 TO expwidth GENERATE
infinitygen(k) <= infinitygen(k-1) AND exponentnode(k);
END GENERATE;
infinitygen(expwidth+1) <= infinitygen(expwidth) OR
(exponentnode(expwidth+1) AND
NOT(exponentnode(expwidth+2))); -- ;1' if infinity
-- zero if exponent <= 0
zerogen(1) <= exponentnode(1);
gza: FOR k IN 2 TO expwidth GENERATE
zerogen(k) <= zerogen(k-1) OR exponentnode(k);
END GENERATE;
zerogen(expwidth+1) <= zerogen(expwidth) AND
NOT(exponentnode(expwidth+2)); -- '0' if zero
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(infinitygen(expwidth+1)) AND zerogen(expwidth+1) AND NOT(dividebyzeroff(1));
-- setmantissa to "11..11" when nan
setmanmax <= nanff(1);
-- set exponent to 0 when zero condition
setexpzero <= zerogen(expwidth+1);
-- set exponent to "11..11" when nan, infinity, or divide by 0
setexpmax <= nanff(1) OR infinitygen(expwidth+1) OR dividebyzeroff(1);
--***************
--*** OUTPUTS ***
--***************
signout <= signff(2);
mantissaout <= mantissaff;
exponentout <= exponenttwoff(expwidth DOWNTO 1);
-----------------------------------------------
nanout <= nanff(2);
invalidout <= nanff(2);
dividebyzeroout <= dividebyzeroff(2);
END rtl;
|
mit
|
Reiuiji/ECE368-Lab
|
Lab 3/VGA Part 1/clk40MHz.vhd
|
4
|
2233
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Pixel CLK
-- Project Name: VGA
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Pixel Clock
-- Output a 40Mhz clock for a vga controller
-- 100 Mhz to 40 Mhz
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity CLK_40MHZ is
port(CLK_IN: in std_logic;
CLK_OUT: inout std_logic);
end CLK_40MHZ;
architecture Behavioral of CLK_40MHZ is
component CLKDLL
generic (CLKDV_DIVIDE : real := 2.5;--2.0; -- (1.5, 2.0, 2.5,
-- 3.0, 4.0, 5.0, 8.0, 16.0)
DUTY_CYCLE_CORRECTION : Boolean := TRUE; -- (TRUE, FALSE)
STARTUP_WAIT : boolean := FALSE); -- (TRUE, FALSE)
port(CLK0 : out STD_ULOGIC;
CLK180 : out STD_ULOGIC;
CLK270 : out STD_ULOGIC;
CLK2X : out STD_ULOGIC;
CLK90 : out STD_ULOGIC;
CLKDV : out STD_ULOGIC;
LOCKED : out STD_ULOGIC;
CLKFB : in STD_ULOGIC;
CLKIN : in STD_ULOGIC;
RST : in STD_ULOGIC);
end component;
attribute CLKDV_DIVIDE : real;
attribute DUTY_CYCLE_CORRECTION : boolean;
attribute STARTUP_WAIT : boolean;
signal CLK_D: std_logic;
begin
CLKDLL_inst : CLKDLL
port map (
CLK0 => open, -- 0 degree DLL CLK ouptput
CLK180 => open, -- 180 degree DLL CLK output
CLK270 => open, -- 270 degree DLL CLK output
CLK2X => CLK_D, -- 2X DLL CLK output
CLK90 => open, -- 90 degree DLL CLK output
CLKDV => CLK_OUT, -- Divided DLL CLK out (CLKDV_DIVIDE)
LOCKED => open, -- DLL LOCK status output
CLKFB => CLK_D, -- DLL clock feedback
CLKIN => CLK_IN, -- Clock input (from IBUFG, BUFG or DLL)
RST => '0' -- DLL asynchronous reset input
);
end Behavioral;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
Gaussian_Filter/ip/Gaussian_Filter/hcc_sgnpstn.vhd
|
20
|
4235
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_SGNPSTN.VHD ***
--*** ***
--*** Function: Leading 0/1s for a small signed ***
--*** number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_sgnpstn IS
GENERIC (offset : integer := 0;
width : positive := 5);
PORT (
signbit : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END hcc_sgnpstn;
ARCHITECTURE rtl OF hcc_sgnpstn IS
signal pluspos, minuspos : STD_LOGIC_VECTOR (width DOWNTO 1);
BEGIN
paa: PROCESS (inbus)
BEGIN
CASE inbus IS
WHEN "0000" => pluspos <= conv_std_logic_vector (0,width);
WHEN "0001" => pluspos <= conv_std_logic_vector (offset+3,width);
WHEN "0010" => pluspos <= conv_std_logic_vector (offset+2,width);
WHEN "0011" => pluspos <= conv_std_logic_vector (offset+2,width);
WHEN "0100" => pluspos <= conv_std_logic_vector (offset+1,width);
WHEN "0101" => pluspos <= conv_std_logic_vector (offset+1,width);
WHEN "0110" => pluspos <= conv_std_logic_vector (offset+1,width);
WHEN "0111" => pluspos <= conv_std_logic_vector (offset+1,width);
WHEN "1000" => pluspos <= conv_std_logic_vector (offset,width);
WHEN "1001" => pluspos <= conv_std_logic_vector (offset,width);
WHEN "1010" => pluspos <= conv_std_logic_vector (offset,width);
WHEN "1011" => pluspos <= conv_std_logic_vector (offset,width);
WHEN "1100" => pluspos <= conv_std_logic_vector (offset,width);
WHEN "1101" => pluspos <= conv_std_logic_vector (offset,width);
WHEN "1110" => pluspos <= conv_std_logic_vector (offset,width);
WHEN "1111" => pluspos <= conv_std_logic_vector (offset,width);
WHEN others => pluspos <= conv_std_logic_vector (0,width);
END CASE;
CASE inbus IS
WHEN "0000" => minuspos <= conv_std_logic_vector (offset,width);
WHEN "0001" => minuspos <= conv_std_logic_vector (offset,width);
WHEN "0010" => minuspos <= conv_std_logic_vector (offset,width);
WHEN "0011" => minuspos <= conv_std_logic_vector (offset,width);
WHEN "0100" => minuspos <= conv_std_logic_vector (offset,width);
WHEN "0101" => minuspos <= conv_std_logic_vector (offset,width);
WHEN "0110" => minuspos <= conv_std_logic_vector (offset,width);
WHEN "0111" => minuspos <= conv_std_logic_vector (offset,width);
WHEN "1000" => minuspos <= conv_std_logic_vector (offset+1,width);
WHEN "1001" => minuspos <= conv_std_logic_vector (offset+1,width);
WHEN "1010" => minuspos <= conv_std_logic_vector (offset+1,width);
WHEN "1011" => minuspos <= conv_std_logic_vector (offset+1,width);
WHEN "1100" => minuspos <= conv_std_logic_vector (offset+2,width);
WHEN "1101" => minuspos <= conv_std_logic_vector (offset+2,width);
WHEN "1110" => minuspos <= conv_std_logic_vector (offset+3,width);
WHEN "1111" => minuspos <= conv_std_logic_vector (0,width);
WHEN others => minuspos <= conv_std_logic_vector (0,width);
END CASE;
END PROCESS;
gaa: FOR k IN 1 TO width GENERATE
position(k) <= (pluspos(k) AND NOT(signbit)) OR (minuspos(k) AND signbit);
END GENERATE;
END rtl;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
bin_Gaussian_Filter/ip/Gaussian_Filter/fp_fxmul.vhd
|
10
|
10945
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_FXMUL.VHD ***
--*** ***
--*** Function: Parameterized Fixed Point ***
--*** Multiplier ***
--*** (behavioral and synthesizable support) ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 15/01/08 - change 54x18 to >54 outputs ***
--*** 23/04/09 - change 54x54 to SII & SIII ***
--*** versions with both 8&9(10) multipliers ***
--*** ***
--***************************************************
--***************************************************
--*** valid supported cores ***
--*** ***
--*** 1: SII/SIII, 18-36 bit inputs, ***
--*** any output width, 2 pipes ***
--*** 2: SII/SIII, 18-36 bit inputs, ***
--*** any output width, 3 pipes ***
--*** 3: SII/SIII 54x18 inputs, ***
--*** up to 72 bit output, 3 or 4 pipes ***
--*** 4: SII 54x54 inputs, 72 bit outputs, ***
--*** 8 or 9 multiplier core 5 or 6 pipes ***
--*** 5: SIII/IV 54x54 inputs, 72 bit outputs, ***
--*** 8 or 9 (10) multiplier core 4 pipes ***
--*** ***
--***************************************************
ENTITY fp_fxmul IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
END fp_fxmul;
ARCHITECTURE rtl OF fp_fxmul IS
component fp_mul2s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT
(
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_mul3s
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36
);
PORT
(
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_mul5418s
GENERIC (
widthcc : positive := 36;
pipes : positive := 3 --3/4
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (18 DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_mul54us_3xs
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (72 DOWNTO 1)
);
end component;
component fp_mul54us_28s
GENERIC (latency : positive := 5);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (72 DOWNTO 1)
);
end component;
component fp_mul54us_29s
GENERIC (latency : positive := 5);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (72 DOWNTO 1)
);
end component;
component fp_mul54us_38s
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (72 DOWNTO 1)
);
end component;
component fp_mul54usb
GENERIC (
latency : positive := 5; -- 4/5/6
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
prune : integer := 0 -- 0 = pruned multiplier, 1 = normal multiplier
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (72 DOWNTO 1)
);
end component;
component fp_mul7218s
GENERIC (
widthcc : positive := 36;
pipes : positive := 3 --3/4
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (72 DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (18 DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
BEGIN
gone: IF ((widthaa < 37) AND
(widthbb < 37) AND
(widthcc <= (widthaa + widthbb)) AND
(pipes = 2)) GENERATE
mulone: fp_mul2s
GENERIC MAP (widthaa=>widthaa,widthbb=>widthbb,widthcc=>widthcc)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb,
result=>result);
END GENERATE;
gtwo: IF ((widthaa < 37) AND
(widthbb < 37) AND
(widthcc <= (widthaa + widthbb)) AND
(pipes = 3)) GENERATE
multwo: fp_mul3s
GENERIC MAP (widthaa=>widthaa,widthbb=>widthbb,widthcc=>widthcc)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb,
result=>result);
END GENERATE;
gthr: IF ((widthaa = 54) AND
(widthbb = 18) AND
(widthcc < 73) AND
((pipes = 3) OR (pipes = 4))) GENERATE
multhr: fp_mul5418s
GENERIC MAP (widthcc=>widthcc,pipes=>pipes)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb,
result=>result);
END GENERATE;
gforone: IF ((widthaa = 54) AND
(widthbb = 54) AND
(widthcc = 72) AND
(accuracy = 1) AND
(device = 1) AND
(synthesize = 1)) GENERATE
mulforone: fp_mul54us_3xs
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>dataaa,mulbb=>databb,
mulcc=>result);
END GENERATE;
gfortwo: IF ((widthaa = 54) AND
(widthbb = 54) AND
(widthcc = 72) AND
(accuracy = 0) AND
(device = 1) AND
(synthesize = 1)) GENERATE
mulfortwo: fp_mul54us_38s
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>dataaa,mulbb=>databb,
mulcc=>result);
END GENERATE;
gforthr: IF ((widthaa = 54) AND
(widthbb = 54) AND
(widthcc = 72) AND
(accuracy = 0) AND
(device = 0) AND
(synthesize = 1) AND
((pipes = 5) OR (pipes = 6))) GENERATE
mulforthr: fp_mul54us_28s
GENERIC MAP (latency=>pipes)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>dataaa,mulbb=>databb,
mulcc=>result);
END GENERATE;
gforfor: IF ((widthaa = 54) AND
(widthbb = 54) AND
(widthcc = 72) AND
(accuracy = 1) AND
(device = 0) AND
(synthesize = 1) AND
((pipes = 5) OR (pipes = 6))) GENERATE
mulforfor: fp_mul54us_29s
GENERIC MAP (latency=>pipes)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
mulaa=>dataaa,mulbb=>databb,
mulcc=>result);
END GENERATE;
gforfiv: IF ((widthaa = 54) AND
(widthbb = 54) AND
(widthcc = 72) AND
(synthesize = 0)) GENERATE
mulforfiv: fp_mul54usb
GENERIC MAP (latency=>pipes,device=>device,prune=>accuracy)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>dataaa,bb=>databb,
cc=>result);
END GENERATE;
gfiv: IF ((widthaa = 72) AND
(widthbb = 18) AND
(widthcc < 90) AND
((pipes = 3) OR (pipes = 4))) GENERATE
multhr: fp_mul7218s
GENERIC MAP (widthcc=>widthcc,pipes=>pipes)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb,
result=>result);
END GENERATE;
END rtl;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
Gaussian_Filter/ip/Gaussian_Filter/fp_invsqr_est.vhd
|
10
|
6478
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_INVSQR_EST.VHD ***
--*** ***
--*** Function: Estimates 18 Bit Inverse Root ***
--*** ***
--*** Used by both single and double inverse ***
--*** square root cores ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. Inverse square root of 18 bit header ***
--*** (not including leading '1') ***
--*** 2. Uses 20 bit precision tables - 18 bits ***
--*** drops a bit occasionally ***
--***************************************************
ENTITY fp_invsqr_est IS
GENERIC (synthesize : integer := 0); -- 0 = behavioral, 1 = syntheziable
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (19 DOWNTO 1);
invroot : OUT STD_LOGIC_VECTOR (18 DOWNTO 1)
);
END fp_invsqr_est;
ARCHITECTURE rtl OF fp_invsqr_est IS
type smalldelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (9 DOWNTO 1);
type largedelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (20 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal one, two : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal oneaddff, zipaddff : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal twodelff : smalldelfftype;
signal onelut, onelutff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal ziplut, ziplutff : STD_LOGIC_VECTOR (20 DOWNTO 1);
signal ziplutdelff : largedelfftype;
signal onetwo : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal invrootff : STD_LOGIC_VECTOR (20 DOWNTO 1);
component fp_invsqr_lut1 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
end component;
component fp_invsqr_lut0 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (20 DOWNTO 1)
);
end component;
component fp_fxmul IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 9 GENERATE
zerovec(k) <= '0';
END GENERATE;
one <= radicand(18 DOWNTO 10);
two <= radicand(9 DOWNTO 1);
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 9 LOOP
oneaddff(k) <= '0';
zipaddff(k) <= '0';
END LOOP;
FOR k IN 1 TO 2 LOOP
FOR j IN 1 TO 9 LOOP
twodelff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO 11 LOOP
onelutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 20 LOOP
ziplutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 2 LOOP
FOR j IN 1 TO 20 LOOP
ziplutdelff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO 18 LOOP
invrootff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
oneaddff <= one;
zipaddff <= one;
twodelff(1)(9 DOWNTO 1) <= two;
twodelff(2)(9 DOWNTO 1) <= twodelff(1)(9 DOWNTO 1);
onelutff <= onelut;
ziplutff <= ziplut;
ziplutdelff(1)(20 DOWNTO 1) <= ziplutff;
ziplutdelff(2)(20 DOWNTO 1) <= ziplutdelff(1)(20 DOWNTO 1);
invrootff <= ziplutdelff(2)(20 DOWNTO 1) - (zerovec(9 DOWNTO 1) & onetwo);
END IF;
END IF;
END PROCESS;
upper: fp_invsqr_lut1 PORT MAP (add=>oneaddff,data=>onelut);
lower: fp_invsqr_lut0 PORT MAP (add=>zipaddff,data=>ziplut);
mulcore: fp_fxmul
GENERIC MAP (widthaa=>11,widthbb=>9,widthcc=>11,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>onelutff,databb=>twodelff(2)(9 DOWNTO 1),
result=>onetwo);
--**************
--*** OUTPUT ***
--**************
invroot <= invrootff(20 DOWNTO 3);
END rtl;
|
mit
|
ou-cse-378/vhdl-tetris
|
opcodes.vhd
|
1
|
3275
|
--Name:Brad McMahon
--File:Opcodes.vhd
--Date:
--Description:Opcode constants
--CSE 378
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
package opcodes is
subtype opcode is std_logic_vector(15 downto 0);
-- Register instructions --WHYP WORDS
constant nop: opcode := X"0000"; -- NOP
constant dup: opcode := X"0001"; -- DUP
constant swap: opcode := X"0002"; -- SWAP
constant drop: opcode := X"0003"; -- DROP
constant over: opcode := X"0004"; -- OVER
constant rot: opcode := X"0005"; -- ROT
constant mrot: opcode := X"0006"; -- -ROT
constant nip: opcode := X"0007"; -- NIP
constant tuck: opcode := X"0008"; -- TUCK
constant rot_drop: opcode := X"0009"; -- ROT_DROP
constant rot_drop_swap: opcode := X"000A"; -- ROT_DROP_SWAP
-- Function unit instructions
constant plus: opcode := X"0010"; -- +
constant minus: opcode := X"0011"; -- -
constant plus1: opcode := X"0012"; -- 1+
constant minus1: opcode := X"0013"; -- 1-
constant invert: opcode := X"0014"; -- INVERT
constant andd: opcode := X"0015"; -- AND
constant orr: opcode := X"0016"; -- OR
constant xorr: opcode := X"0017"; -- XOR
constant twotimes: opcode := X"0018"; -- 2*
constant u2slash: opcode := X"0019"; -- U2/
constant twoslash: opcode := X"001A"; -- 2/
constant rshift: opcode := X"001B"; -- RSHIFT
constant lshift: opcode := X"001C"; -- LSHIFT
constant ones: opcode := X"0020"; -- TRUE
constant zeros: opcode := X"0021"; -- FALSE
constant zeroequal: opcode := X"0022"; -- 0=
constant zeroless: opcode := X"0023"; -- 0<
constant zerogreat: opcode := X"0f23"; -- 0>
constant ugt: opcode := X"0024"; -- U>
constant ult: opcode := X"0025"; -- U<
constant eq: opcode := X"0026"; -- =
constant ugte: opcode := X"0027"; -- U>=
constant ulte: opcode := X"0028"; -- U<=
constant neq: opcode := X"0029"; -- <>
constant gt: opcode := X"002A"; -- >
constant lt: opcode := X"002B"; -- <
constant gte: opcode := X"002C"; -- >=
constant lte: opcode := X"002D"; -- <=
-- I/O instructions
constant sfetch: opcode := X"0037"; -- S@
constant digstore: opcode := X"0038"; -- DIG!
constant scorefetch: opcode := X"0040"; -- score@
constant destrofetch: opcode := X"0041"; -- destrofetch
constant ClearLines: opcode := X"0042"; -- ClearLines
-- Transfer instructions
constant lit: opcode := X"0100"; -- LIT
constant jmp: opcode := X"0101"; -- AGAIN, ELSE
constant jz: opcode := X"0102"; -- IF, UNTIL
constant jb4HI: opcode := X"010D"; -- waitB4
constant jb4LO: opcode := X"0109";
-- Return Stack and I/O instructions
constant tor: opcode := X"0030";
constant rfrom: opcode := X"0031";
constant rfetch: opcode := X"0032";
constant rfromdrop: opcode := X"0033";
constant ldstore: opcode := X"0039";
-- Transfer Instructions
constant drjne: opcode :=X"0103";
constant call: opcode :=X"0104";
constant ret: opcode :=X"0105";
end opcodes;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
bin_Gaussian_Filter/ip/Gaussian_Filter/fp_exprnd.vhd
|
10
|
7830
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_EXPRND.VHD ***
--*** ***
--*** Function: FP Exponent Output Block - ***
--*** Rounded ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_exprnd IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaexp : IN STD_LOGIC_VECTOR (24 DOWNTO 1); -- includes roundbit
nanin : IN STD_LOGIC;
rangeerror : IN STD_LOGIC;
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1);
--------------------------------------------------
nanout : OUT STD_LOGIC;
overflowout : OUT STD_LOGIC;
underflowout : OUT STD_LOGIC
);
END fp_exprnd;
ARCHITECTURE rtl OF fp_exprnd IS
constant expwidth : positive := 8;
constant manwidth : positive := 23;
type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1);
signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal rangeerrorff : STD_LOGIC;
signal overflownode, underflownode : STD_LOGIC;
signal overflowff, underflowff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal manoverflowbitff : STD_LOGIC;
signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1);
signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1);
signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1);
signal infinitygen : STD_LOGIC_VECTOR (expwidth+1 DOWNTO 1);
signal zerogen : STD_LOGIC_VECTOR (expwidth+1 DOWNTO 1);
signal setmanzero, setmanmax : STD_LOGIC;
signal setexpzero, setexpmax : STD_LOGIC;
BEGIN
gzv: FOR k IN 1 TO manwidth-1 GENERATE
zerovec(k) <= '0';
END GENERATE;
pra: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
nanff <= "00";
rangeerrorff <= '0';
overflowff <= "00";
underflowff <= "00";
manoverflowbitff <= '0';
FOR k IN 1 TO manwidth LOOP
roundmantissaff(k) <= '0';
mantissaff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth+2 LOOP
exponentoneff(k) <= '0';
END LOOP;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF(enable = '1') THEN
nanff(1) <= nanin;
nanff(2) <= nanff(1);
rangeerrorff <= rangeerror;
overflowff(1) <= overflownode;
overflowff(2) <= overflowff(1);
underflowff(1) <= underflownode;
underflowff(2) <= underflowff(1);
manoverflowbitff <= manoverflow(manwidth+1);
roundmantissaff <= mantissaexp(manwidth+1 DOWNTO 2) + (zerovec & mantissaexp(1));
-- nan takes precedence (set max)
-- nan takes precedence (set max)
FOR k IN 1 TO manwidth LOOP
mantissaff(k) <= (roundmantissaff(k) AND setmanzero) OR setmanmax;
END LOOP;
exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentexp;
FOR k IN 1 TO expwidth LOOP
exponenttwoff(k) <= (exponentnode(k) AND setexpzero) OR setexpmax;
END LOOP;
END IF;
END IF;
END PROCESS;
exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) +
(zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff);
--*********************************
--*** PREDICT MANTISSA OVERFLOW ***
--*********************************
manoverflow(1) <= mantissaexp(1);
gmoa: FOR k IN 2 TO manwidth+1 GENERATE
manoverflow(k) <= manoverflow(k-1) AND mantissaexp(k);
END GENERATE;
--**********************************
--*** CHECK GENERATED CONDITIONS ***
--**********************************
-- infinity if exponent == 255
infinitygen(1) <= exponentnode(1);
gia: FOR k IN 2 TO expwidth GENERATE
infinitygen(k) <= infinitygen(k-1) AND exponentnode(k);
END GENERATE;
infinitygen(expwidth+1) <= infinitygen(expwidth) OR
(exponentnode(expwidth+1) AND
NOT(exponentnode(expwidth+2))); -- '1' if infinity
-- zero if exponent == 0
zerogen(1) <= exponentnode(1);
gza: FOR k IN 2 TO expwidth GENERATE
zerogen(k) <= zerogen(k-1) OR exponentnode(k);
END GENERATE;
zerogen(expwidth+1) <= zerogen(expwidth) AND
NOT(exponentnode(expwidth+2)); -- '0' if zero
-- trap any other overflow errors
-- when sign = 0 and rangeerror = 1, overflow
-- when sign = 1 and rangeerror = 1, underflow
overflownode <= NOT(signin) AND rangeerror;
underflownode <= signin AND rangeerror;
-- set mantissa to 0 when infinity or zero condition
setmanzero <= NOT(infinitygen(expwidth+1)) AND zerogen(expwidth+1) AND NOT(rangeerrorff);
-- setmantissa to "11..11" when nan
setmanmax <= nanin;
-- set exponent to 0 when zero condition
setexpzero <= zerogen(expwidth+1);
-- set exponent to "11..11" when nan, infinity, or divide by 0
setexpmax <= nanin OR infinitygen(expwidth+1) OR rangeerrorff;
--***************
--*** OUTPUTS ***
--***************
signout <= '0';
mantissaout <= mantissaff;
exponentout <= exponenttwoff;
-----------------------------------------------
nanout <= nanff(2);
overflowout <= overflowff(2);
underflowout <= underflowff(2);
END rtl;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
bin_Gaussian_Filter/ip/Gaussian_Filter/dp_ln_core.vhd
|
10
|
21706
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION LOG(e) - CORE ***
--*** ***
--*** DP_LN_CORE.VHD ***
--*** ***
--*** Function: Double Precision LOG (LN) Core ***
--*** ***
--*** 18/02/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 24/04/09 - SIII/SIV multiplier support ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** SII/SIII/SIV Latency = 26 + 7*doublespeed ***
--*** no 54x54 multipliers ***
--***************************************************
ENTITY dp_ln_core IS
GENERIC (
doublespeed : integer := 0; -- 0/1
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
ccman : OUT STD_LOGIC_VECTOR (53 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
ccsgn : OUT STD_LOGIC;
zeroout : OUT STD_LOGIC
);
END dp_ln_core;
ARCHITECTURE rtl OF dp_ln_core IS
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
--*** INPUT BLOCK ***
signal aamanff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal aaexpff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal aaexpabsff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal aaexppos, aaexpneg : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal aaexpabs : STD_LOGIC_VECTOR (10 DOWNTO 1);
--*** TABLES ***
signal lutpowaddff : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal lutoneaddff, luttwoaddff : STD_LOGIC_VECTOR (9 DOWNTO 1);
signal lutpowmanff, lutonemanff, luttwomanff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal lutpowexpff, lutoneexpff, luttwoexpff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal lutoneinvff : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal luttwoinvff : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal lutpowmannode, lutonemannode, luttwomannode : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal lutpowexpnode, lutoneexpnode, luttwoexpnode : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal lutoneinvnode : STD_LOGIC_VECTOR (12 DOWNTO 1);
signal luttwoinvnode : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal aanum, aanumdel : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal invonenum : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal mulonenode : STD_LOGIC_VECTOR (65 DOWNTO 1);
signal mulonenormff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal mulonenumdel : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal multwonode : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal multwonormff : STD_LOGIC_VECTOR (71 DOWNTO 1);
--*** SERIES ***
signal squaredterm : STD_LOGIC_VECTOR (48 DOWNTO 1);
signal onethird : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal scaledterm, scaledtermdel : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal cubedterm : STD_LOGIC_VECTOR (32 DOWNTO 1);
signal xtermdel : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal oneterm, twoterm, thrterm : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal oneplustwoterm : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal seriesterm : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal mantissaseries : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentseries : STD_LOGIC_VECTOR (11 DOWNTO 1);
--*** ADD LOGS ***
signal zeropow, zeroone, zerotwo : STD_LOGIC;
signal mantissapowernode : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal mantissapower : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentpower : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal numberone, numberonedel : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal mantissaone : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentone : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal mantissaaddone : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentaddone : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal mantissatwo : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponenttwo : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal numbertwo, numbertwodel : STD_LOGIC_VECTOR (75 DOWNTO 1);
signal mantissaaddtwo : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentaddtwo : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal numberthr, numberthrdel : STD_LOGIC_VECTOR (75 DOWNTO 1);
signal mantissasum : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal mantissasumabs : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentsum : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal mantissanorm : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exponentnorm : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeronorm : STD_LOGIC;
signal signff : STD_LOGIC_VECTOR (25+7*doublespeed DOWNTO 1);
component dp_lnlutpow
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
end component;
component dp_lnlut9
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
inv : OUT STD_LOGIC_VECTOR (12 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
end component;
component dp_lnlut18
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
inv : OUT STD_LOGIC_VECTOR (18 DOWNTO 1);
logman : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
logexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component dp_fxadd
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component dp_fxsub
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component dp_lnadd
GENERIC (
speed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aaman : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
aaexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
bbman : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
bbexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
ccman : OUT STD_LOGIC_VECTOR (64 DOWNTO 1);
ccexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1)
);
end component;
component dp_lnnorm
GENERIC (
speed : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inman : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
inexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
outman : OUT STD_LOGIC_VECTOR (64 DOWNTO 1);
outexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
zero : OUT STD_LOGIC
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
--*******************
--*** INPUT BLOCK ***
--*******************
ppin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
aamanff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
aaexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO 10 LOOP
aaexpabsff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aamanff <= aaman; -- level 1
aaexpff <= aaexp; -- level 1
aaexpabsff <= aaexpabs; -- level 2
END IF;
END IF;
END PROCESS;
aaexppos <= ('0' & aaexpff) - "001111111111";
aaexpneg <= "001111111111" - ('0' & aaexpff);
gaba: FOR k IN 1 TO 10 GENERATE
aaexpabs(k) <= (aaexppos(k) AND NOT(aaexppos(12))) OR (aaexpneg(k) AND aaexppos(12));
END GENERATE;
--******************************************
--*** RANGE REDUCTION THROUGH LUT SERIES ***
--******************************************
plut: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 10 LOOP
lutpowaddff(k) <= '0';
END LOOP;
FOR k IN 1 TO 9 LOOP
lutoneaddff(k) <= '0';
luttwoaddff(k) <= '0';
END LOOP;
FOR k IN 1 TO 52 LOOP
lutpowmanff(k) <= '0';
lutonemanff(k) <= '0';
luttwomanff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
lutpowexpff(k) <= '0';
lutoneexpff(k) <= '0';
luttwoexpff(k) <= '0';
END LOOP;
FOR k IN 1 TO 12 LOOP
lutoneinvff(k) <= '0';
END LOOP;
FOR k IN 1 TO 18 LOOP
luttwoinvff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
lutpowaddff <= aaexpabsff; -- level 3
lutoneaddff <= aamanff(52 DOWNTO 44); -- level 2
luttwoaddff <= mulonenormff(55 DOWNTO 47); -- level 8+speed
lutpowmanff <= lutpowmannode; -- level 4
lutpowexpff <= lutpowexpnode; -- level 4
lutoneinvff <= lutoneinvnode; -- level 3
lutonemanff <= lutonemannode; -- level 3
lutoneexpff <= lutoneexpnode; -- level 3
luttwoinvff <= luttwoinvnode; -- level 9+speed
luttwomanff <= luttwomannode; -- level 9+speed
luttwoexpff <= luttwoexpnode; -- level 9+speed
END IF;
END IF;
END PROCESS;
lutpow: dp_lnlutpow
PORT MAP (add=>lutpowaddff,
logman=>lutpowmannode,logexp=>lutpowexpnode);
lutone: dp_lnlut9
PORT MAP (add=>lutoneaddff,
inv=>lutoneinvnode,logman=>lutonemannode,logexp=>lutoneexpnode);
luttwo: dp_lnlut18
PORT MAP (add=>luttwoaddff,
inv=>luttwoinvnode,logman=>luttwomannode,logexp=>luttwoexpnode);
aanum <= '1' & aamanff & '0';
-- level 1 in, level 3 out
delone: fp_del
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aanum,cc=>aanumdel);
invonenum <= lutoneinvff & "000000";
--mulone <= aanum * invone; -- 53*12 = 65
-- level 3 in, level 6+doublespeed out
mulone: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>18,widthcc=>65,
pipes=>3+doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>aanumdel,databb=>invonenum,
result=>mulonenode);
--multwo <= mulonenorm(64 DOWNTO 11) * invtwo; -- 54x18=72
-- level 7+speed in, level 9+speed out
deltwo: fp_del
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>mulonenormff(64 DOWNTO 11),cc=>mulonenumdel);
-- level 9+doublespeed in, level 12+2*doublespeed out
multwo: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>18,widthcc=>72,
pipes=>3+doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>mulonenumdel,databb=>luttwoinvff,
result=>multwonode);
pmna: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
mulonenormff(k) <= '0';
END LOOP;
FOR k IN 1 TO 71 LOOP
multwonormff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
-- normalize in case input is 1.000000 and inv is 0.5
-- level 7+speed
FOR k IN 1 TO 64 LOOP
mulonenormff(k) <= (mulonenode(k+1) AND mulonenode(65)) OR
(mulonenode(k) AND NOT(mulonenode(65)));
END LOOP;
-- level 13+2*speed
FOR k IN 1 TO 71 LOOP
multwonormff(k) <= (multwonode(k+1) AND multwonode(72)) OR
(multwonode(k) AND NOT(multwonode(72)));
END LOOP;
END IF;
END IF;
END PROCESS;
--************************************
--*** TAYLOR SERIES OF SMALL RANGE ***
--************************************
-- taylor series expansion of subrange (36 bits)
-- x - x*x/2
-- 16 leading bits, so x*x 16 bits down, +1 bit for 1/2
-- 36 lower bits in multwo(54:19)
--square <= multwonorm(54 DOWNTO 19) * multwonorm(54 DOWNTO 19);
-- level 13+2*doublespeed in, 16+2*doublespeed out
multhr: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>48,
pipes=>3,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multwonormff(54 DOWNTO 19),databb=>multwonormff(54 DOWNTO 19),
result=>squaredterm);
onethird <= "010101010101010101";
-- level 13+2*doublespeed in, level 15+2*doublespeed out
mulfor: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>18,
pipes=>2,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multwonormff(54 DOWNTO 37),databb=>onethird,
result=>scaledterm);
--level 15+2*doublespeed in, level 16+2*doublespeed out
delthr: fp_del
GENERIC MAP (width=>18,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>scaledterm,cc=>scaledtermdel);
-- level 16+2*doublespeed in, level 18+2*doublespeed out
mulfiv: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>32,
pipes=>2,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>squaredterm(48 DOWNTO 31),databb=>scaledtermdel,
result=>cubedterm);
--level 13+2*doublespeed in, level 16+2*doublespeed out
delfor: fp_del
GENERIC MAP (width=>54,pipes=>3)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>multwonormff(54 DOWNTO 1),cc=>xtermdel);
-- level 16+2*doublespeed
oneterm <= xtermdel & zerovec(10 DOWNTO 1);
twoterm <= zerovec(17 DOWNTO 1) & squaredterm(48 DOWNTO 2); -- x*x/2
-- level 18+2*doublespeed
thrterm <= zerovec(32 DOWNTO 1) & cubedterm;
--level 16+2*doublespeed in, level 18+2*doublespeed out
tayone: dp_fxsub
GENERIC MAP (width=>64,pipes=>2,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>oneterm,bb=>twoterm,borrowin=>'1',
cc=>oneplustwoterm);
--level 18+2*doublespeed in, level 19+3*doublespeed out
taytwo: dp_fxadd
GENERIC MAP (width=>64,pipes=>1+doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>oneplustwoterm,bb=>thrterm,carryin=>'0',
cc=>seriesterm);
--mantissaseries <= seriesterm;
mantissaseries <= '0' & seriesterm(64 DOWNTO 2);
exponentseries <= conv_std_logic_vector (1006,11);
--18x18
--cubed <= square(72 DOWNTO 55) * multwonorm(54 DOWNTO 37);
--cubedscale <= cubed(36 DOWNTO 19) * onethird;
--**************************
--*** ADD ALL LOGARITHMS ***
--**************************
zeropow <= lutpowexpff(11) OR lutpowexpff(10) OR lutpowexpff(9) OR
lutpowexpff(8) OR lutpowexpff(7) OR lutpowexpff(6) OR
lutpowexpff(5) OR lutpowexpff(4) OR lutpowexpff(3) OR
lutpowexpff(2) OR lutpowexpff(1);
-- level 4
--mantissapower <= zeropow & lutpowmanff & zerovec(11 DOWNTO 1);
--mantissapower <= '0' & zeropow & lutpowmanff & zerovec(10 DOWNTO 1);
mantissapowernode <= '0' & zeropow & lutpowmanff & zerovec(10 DOWNTO 1);
gmpz: FOR k IN 1 TO 64 GENERATE
mantissapower(k) <= mantissapowernode(k) XOR signff(3);
END GENERATE;
exponentpower <= lutpowexpff;
zeroone <= lutoneexpff(11) OR lutoneexpff(10) OR lutoneexpff(9) OR
lutoneexpff(8) OR lutoneexpff(7) OR lutoneexpff(6) OR
lutoneexpff(5) OR lutoneexpff(4) OR lutoneexpff(3) OR
lutoneexpff(2) OR lutoneexpff(1);
-- level 3
numberone <= zeroone & lutonemanff & lutoneexpff;
-- level 3 in, level 4 out
delfiv: fp_del
GENERIC MAP (width=>64,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numberone,cc=>numberonedel);
--mantissaone <= numberonedel(64 DOWNTO 12) & zerovec(11 DOWNTO 1);
mantissaone <= '0' & numberonedel(64 DOWNTO 12) & zerovec(10 DOWNTO 1);
exponentone <= numberonedel(11 DOWNTO 1);
-- level 4 in, level 10 out
addone: dp_lnadd
GENERIC MAP (speed=>1,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aaman=>mantissapower,aaexp=>exponentpower,
bbman=>mantissaone,bbexp=>exponentone,
ccman=>mantissaaddone,ccexp=>exponentaddone);
zerotwo <= luttwoexpff(11) OR luttwoexpff(10) OR luttwoexpff(9) OR
luttwoexpff(8) OR luttwoexpff(7) OR luttwoexpff(6) OR
luttwoexpff(5) OR luttwoexpff(4) OR luttwoexpff(3) OR
luttwoexpff(2) OR luttwoexpff(1);
-- level 9+doublespeed
--mantissatwo <= zerotwo & luttwomanff & zerovec(11 DOWNTO 1);
mantissatwo <= '0' & zerotwo & luttwomanff & zerovec(10 DOWNTO 1);
exponenttwo <= luttwoexpff;
numbertwo <= mantissatwo & exponenttwo;
gasa: IF (doublespeed = 0) GENERATE
delsix: fp_del
GENERIC MAP (width=>75,pipes=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numbertwo,cc=>numbertwodel);
END GENERATE;
gasb: IF (doublespeed = 1) GENERATE
numbertwodel <= numbertwo;
END GENERATE;
-- level 10 in, level 16 out
addtwo: dp_lnadd
GENERIC MAP (speed=>1,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aaman=>mantissaaddone,aaexp=>exponentaddone,
bbman=>numbertwodel(75 DOWNTO 12),bbexp=>numbertwodel(11 DOWNTO 1),
ccman=>mantissaaddtwo,ccexp=>exponentaddtwo);
numberthr <= mantissaaddtwo & exponentaddtwo;
-- level 16 in, level 19+3*doublespeed out
delsev: fp_del
GENERIC MAP (width=>75,pipes=>3+3*doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>numberthr,cc=>numberthrdel);
-- level 19+3*doublespeed in, level 23+5*doublespeed out
addthr: dp_lnadd
GENERIC MAP (speed=>doublespeed,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aaman=>mantissaseries,aaexp=>exponentseries,
bbman=>numberthrdel(75 DOWNTO 12),bbexp=>numberthrdel(11 DOWNTO 1),
ccman=>mantissasum,ccexp=>exponentsum);
gmsa: FOR k IN 1 TO 64 GENERATE
mantissasumabs(k) <= mantissasum(k) XOR signff(22+5*doublespeed);
END GENERATE;
-- level 23+5*doublespeed in, level 26+7*doublespeed out
norm: dp_lnnorm
GENERIC MAP (speed=>doublespeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inman=>mantissasumabs,inexp=>exponentsum,
outman=>mantissanorm,outexp=>exponentnorm,
zero=>zeronorm);
psgna: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 25+7*doublespeed LOOP
signff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
signff(1) <= aaexppos(12);
FOR k IN 2 TO 25+7*doublespeed LOOP
signff(k) <= signff(k-1);
END LOOP;
END IF;
END PROCESS;
--***************
--*** OUTPUTS ***
--***************
ccman <= mantissanorm(63 DOWNTO 11);
ccexp <= exponentnorm;
ccsgn <= signff(25+7*doublespeed);
zeroout <= zeronorm;
END rtl;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
Gaussian_Filter/ip/Gaussian_Filter/fp_cordic_atan1.vhd
|
10
|
5033
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_CORDIC_ATAN1.VHD ***
--*** ***
--*** Function: ATAN Values Table for SIN and ***
--*** COS CORDIC Core ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_cordic_atan1 IS
GENERIC (start : positive := 32;
width : positive := 32;
indexpoint : positive := 1);
PORT (
indexbit : IN STD_LOGIC;
arctan : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_cordic_atan1;
ARCHITECTURE sft OF fp_cordic_atan1 IS
type atantype IS ARRAY (48 DOWNTO 1) OF STD_LOGIC_VECTOR (48 DOWNTO 1);
signal atannum : atantype;
BEGIN
-- "00" + 46 bits
atannum(1)(48 DOWNTO 1) <= x"3243F6A8885A";
atannum(2)(48 DOWNTO 1) <= x"1DAC670561BB";
atannum(3)(48 DOWNTO 1) <= x"0FADBAFC9640";
atannum(4)(48 DOWNTO 1) <= x"07F56EA6AB0C";
atannum(5)(48 DOWNTO 1) <= x"03FEAB76E5A0";
atannum(6)(48 DOWNTO 1) <= x"01FFD55BBA97";
atannum(7)(48 DOWNTO 1) <= x"00FFFAAADDDC";
atannum(8)(48 DOWNTO 1) <= x"007FFF5556EF";
atannum(9)(48 DOWNTO 1) <= x"003FFFEAAAB7";
atannum(10)(48 DOWNTO 1) <= x"001FFFFD5556";
atannum(11)(48 DOWNTO 1) <= x"000FFFFFAAAB";
atannum(12)(48 DOWNTO 1) <= x"0007FFFFF555";
atannum(13)(48 DOWNTO 1) <= x"0003FFFFFEAB";
atannum(14)(48 DOWNTO 1) <= x"0001FFFFFFD5";
atannum(15)(48 DOWNTO 1) <= x"0000FFFFFFFB";
atannum(16)(48 DOWNTO 1) <= x"00007FFFFFFF";
atannum(17)(48 DOWNTO 1) <= x"000040000000";
atannum(18)(48 DOWNTO 1) <= x"000020000000";
atannum(19)(48 DOWNTO 1) <= x"000010000000";
atannum(20)(48 DOWNTO 1) <= x"000008000000";
atannum(21)(48 DOWNTO 1) <= x"000004000000";
atannum(22)(48 DOWNTO 1) <= x"000002000000";
atannum(23)(48 DOWNTO 1) <= x"000001000000";
atannum(24)(48 DOWNTO 1) <= x"000000800000";
atannum(25)(48 DOWNTO 1) <= x"000000400000";
atannum(26)(48 DOWNTO 1) <= x"000000200000";
atannum(27)(48 DOWNTO 1) <= x"000000100000";
atannum(28)(48 DOWNTO 1) <= x"000000080000";
atannum(29)(48 DOWNTO 1) <= x"000000040000";
atannum(30)(48 DOWNTO 1) <= x"000000020000";
atannum(31)(48 DOWNTO 1) <= x"000000010000";
atannum(32)(48 DOWNTO 1) <= x"000000008000";
atannum(33)(48 DOWNTO 1) <= x"000000004000";
atannum(34)(48 DOWNTO 1) <= x"000000002000";
atannum(35)(48 DOWNTO 1) <= x"000000001000";
atannum(36)(48 DOWNTO 1) <= x"000000000800";
atannum(37)(48 DOWNTO 1) <= x"000000000400";
atannum(38)(48 DOWNTO 1) <= x"000000000200";
atannum(39)(48 DOWNTO 1) <= x"000000000100";
atannum(40)(48 DOWNTO 1) <= x"000000000080";
atannum(41)(48 DOWNTO 1) <= x"000000000040";
atannum(42)(48 DOWNTO 1) <= x"000000000020";
atannum(43)(48 DOWNTO 1) <= x"000000000010";
atannum(44)(48 DOWNTO 1) <= x"000000000008";
atannum(45)(48 DOWNTO 1) <= x"000000000004";
atannum(46)(48 DOWNTO 1) <= x"000000000002";
atannum(47)(48 DOWNTO 1) <= x"000000000001";
atannum(48)(48 DOWNTO 1) <= x"000000000000";
pca: PROCESS (indexbit)
BEGIN
CASE indexbit IS
WHEN '0' => arctan <= atannum(start)(48 DOWNTO 49-width);
WHEN '1' => arctan <= atannum(start+indexpoint)(48-indexpoint DOWNTO 49-indexpoint-width);
WHEN others => arctan <= atannum(48)(width DOWNTO 1);
END CASE;
END PROCESS;
END sft;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
Gaussian_Filter/ip/Gaussian_Filter/hcc_castxtoy.vhd
|
10
|
2116
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTXTOY.VHD ***
--*** ***
--*** Function: Cast Internal Single to ***
--*** Internal Double ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castxtoy IS
GENERIC (
target : integer := 1; -- 1(internal), 0 (multiplier, divider)
mantissa : positive := 32
);
PORT (
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aasat, aazip : STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
END hcc_castxtoy;
ARCHITECTURE rtl OF hcc_castxtoy IS
signal exponentadjust : STD_LOGIC_VECTOR (13 DOWNTO 1);
BEGIN
-- x : 32/36 signed mantissa, 10 bit exponent
-- y : (internal) 64 signed mantissa, 13 bit exponent
exponentadjust <= conv_std_logic_vector (896,13);
cc(67+10*target DOWNTO 68+10*target-mantissa) <= aa(mantissa+10 DOWNTO 11);
gxa: FOR k IN 14 TO 67+10*target-mantissa GENERATE
cc(k) <= aa(11);
END GENERATE;
cc(13 DOWNTO 1) <= ("000" & aa(10 DOWNTO 1)) + exponentadjust;
ccsat <= aasat;
cczip <= aazip;
END rtl;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
bin_Gaussian_Filter/ip/Gaussian_Filter/fp_mul23x56.vhd
|
10
|
6888
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
LIBRARY altera_mf;
USE altera_mf.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_MUL23X56.VHD ***
--*** ***
--*** Function: Fixed Point Multiplier ***
--*** ***
--*** 23 and 56 bit inputs, 4 pipes ***
--*** ***
--*** 07/01/10 ML ***
--*** ***
--*** (c) 2010 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_mul23x56 IS
GENERIC (device : integer := 0);
PORT
(
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (56 DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (79 DOWNTO 1)
);
END fp_mul23x56;
ARCHITECTURE SYN OF fp_mul23x56 IS
constant AW : integer := 23;
constant BW : integer := 56;
constant RW : integer := AW+BW;
-- use 27-bit multipliers on SV/AV/CV,
-- use 36-bit multipliers on SIII/SIV
-- split multiplication into two equal parts on other architectures
function chooseMaxMulWidth(device : integer) return integer is
begin
if (device = 2) then
return 27;
elsif (device = 1) then
return 36;
else
return 28;
end if;
end function;
constant MAXMULWIDTH : integer := chooseMaxMulWidth(device);
constant use_2_multipliers : boolean := BW <= 2 * MAXMULWIDTH;
constant use_3_multipliers : boolean := not use_2_multipliers;
component fp_mul2s
GENERIC (
widthaa : positive;
widthbb : positive;
widthcc : positive
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR(widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR(widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR(widthcc DOWNTO 1)
);
end component;
component fp_mul3s
GENERIC (
widthaa : positive;
widthbb : positive;
widthcc : positive
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
signal zerovec : STD_LOGIC_VECTOR(MAXMULWIDTH DOWNTO 1);
BEGIN
zerovec <= (others => '0');
gen2mul: IF use_2_multipliers GENERATE
constant BLW : integer := MAXMULWIDTH;
constant BHW : integer := BW - BLW;
signal multiplier_low : STD_LOGIC_VECTOR(BLW+AW DOWNTO 1);
signal multiplier_high : STD_LOGIC_VECTOR(BHW+AW DOWNTO 1);
signal adderff : STD_LOGIC_VECTOR(RW DOWNTO 1);
BEGIN
ml: fp_mul3s
GENERIC MAP (widthaa=>AW,widthbb=>BLW,widthcc=>BLW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BLW DOWNTO 1),
result=>multiplier_low);
mh: fp_mul3s
GENERIC MAP (widthaa=>AW,widthbb=>BHW,widthcc=>BHW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BHW+BLW DOWNTO BLW+1),
result=>multiplier_high);
pad: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
adderff <= (others => '0');
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
adderff <= (zerovec(RW-(BLW+AW) DOWNTO 1) & multiplier_low) +
(multiplier_high & zerovec(RW-(BHW+AW) DOWNTO 1));
END IF;
END IF;
END PROCESS;
result <= adderff;
END GENERATE;
gen3mul: IF use_3_multipliers GENERATE
constant BLW : integer := MAXMULWIDTH;
constant BHW : integer := MAXMULWIDTH;
constant BTW : integer := BW - BLW - BHW;
signal multiplier_low : STD_LOGIC_VECTOR(BLW+AW DOWNTO 1);
signal multiplier_high : STD_LOGIC_VECTOR(BHW+AW DOWNTO 1);
signal multiplier_top : STD_LOGIC_VECTOR(BTW+AW DOWNTO 1);
signal adderff0 : STD_LOGIC_VECTOR (RW DOWNTO 1);
signal adderff1 : STD_LOGIC_VECTOR (RW DOWNTO 1);
BEGIN
ml: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BLW,widthcc=>BLW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BLW DOWNTO 1),
result=>multiplier_low);
mh: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BHW,widthcc=>BHW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BHW+BLW DOWNTO BLW+1),
result=>multiplier_high);
mt: fp_mul2s
GENERIC MAP (widthaa=>AW,widthbb=>BTW,widthcc=>BTW+AW)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>dataaa,databb=>databb(BTW+BHW+BLW DOWNTO BHW+BLW+1),
result=>multiplier_top);
pad: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
adderff0 <= (others => '0');
adderff1 <= (others => '0');
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
adderff0 <= (multiplier_top & zerovec(RW-(BTW+AW)-(BLW+AW) DOWNTO 1) & multiplier_low) +
(zerovec(RW-(BHW+AW)-BLW DOWNTO 1) & multiplier_high & zerovec(BLW DOWNTO 1));
adderff1 <= adderff0;
END IF;
END IF;
END PROCESS;
result <= adderff1;
END GENERATE;
END SYN;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
Gaussian_Filter/ip/Gaussian_Filter/hcc_cntsgn32_sv.vhd
|
20
|
5981
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTSGN32.VHD ***
--*** ***
--*** Function: Count leading bits in a signed ***
--*** 32 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntsgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntsgn32;
ARCHITECTURE rtl OF hcc_cntsgn32 IS
type positiontype IS ARRAY (8 DOWNTO 1) OF STD_LOGIC_VECTOR (5 DOWNTO 1);
signal possec, negsec, sec, sel : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal position : positiontype;
component hcc_sgnpstn
GENERIC (offset : integer := 0;
width : positive := 5);
PORT (
signbit : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (4 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- for double 64 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [64][63..60][59][58..7][6..4][321] - NB underflow less than overflow
-- find first leading '1' in inexact portion for 32 bit positive number
possec(1) <= frac(31) OR frac(30) OR frac(29) OR frac(28);
possec(2) <= frac(27) OR frac(26) OR frac(25) OR frac(24);
possec(3) <= frac(23) OR frac(22) OR frac(21) OR frac(20);
possec(4) <= frac(19) OR frac(18) OR frac(17) OR frac(16);
possec(5) <= frac(15) OR frac(14) OR frac(13) OR frac(12);
possec(6) <= frac(11) OR frac(10) OR frac(9) OR frac(8);
possec(7) <= frac(7) OR frac(6) OR frac(5) OR frac(4);
possec(8) <= frac(3) OR frac(2) OR frac(1);
-- find first leading '0' in inexact portion for 32 bit negative number
negsec(1) <= frac(31) AND frac(30) AND frac(29) AND frac(28);
negsec(2) <= frac(27) AND frac(26) AND frac(25) AND frac(24);
negsec(3) <= frac(23) AND frac(22) AND frac(21) AND frac(20);
negsec(4) <= frac(19) AND frac(18) AND frac(17) AND frac(16);
negsec(5) <= frac(15) AND frac(14) AND frac(13) AND frac(12);
negsec(6) <= frac(11) AND frac(10) AND frac(9) AND frac(8);
negsec(7) <= frac(7) AND frac(6) AND frac(5) AND frac(4);
negsec(8) <= frac(3) AND frac(2) AND frac(1);
gaa: FOR k IN 1 TO 8 GENERATE
sec(k) <= (possec(k) AND NOT(frac(32))) OR (NOT(negsec(k)) AND frac(32));
END GENERATE;
sel(1) <= sec(1);
sel(2) <= sec(2) AND NOT(sec(1));
sel(3) <= sec(3) AND NOT(sec(2)) AND NOT(sec(1));
sel(4) <= sec(4) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(5) <= sec(5) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(6) <= sec(6) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(7) <= sec(7) AND NOT(sec(6)) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND
NOT(sec(2)) AND NOT(sec(1));
sel(8) <= sec(8) AND NOT(sec(7)) AND NOT(sec(6)) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND
NOT(sec(2)) AND NOT(sec(1));
pone: hcc_sgnpstn
GENERIC MAP (offset=>0,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(31 DOWNTO 28),
position=>position(1)(5 DOWNTO 1));
ptwo: hcc_sgnpstn
GENERIC MAP (offset=>4,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(27 DOWNTO 24),
position=>position(2)(5 DOWNTO 1));
pthr: hcc_sgnpstn
GENERIC MAP (offset=>8,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(23 DOWNTO 20),
position=>position(3)(5 DOWNTO 1));
pfor: hcc_sgnpstn
GENERIC MAP (offset=>12,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(19 DOWNTO 16),
position=>position(4)(5 DOWNTO 1));
pfiv: hcc_sgnpstn
GENERIC MAP (offset=>16,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(15 DOWNTO 12),
position=>position(5)(5 DOWNTO 1));
psix: hcc_sgnpstn
GENERIC MAP (offset=>20,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(11 DOWNTO 8),
position=>position(6)(5 DOWNTO 1));
psev: hcc_sgnpstn
GENERIC MAP (offset=>24,width=>5)
PORT MAP (signbit=>frac(32),inbus=>frac(7 DOWNTO 4),
position=>position(7)(5 DOWNTO 1));
pegt: hcc_sgnpstn
GENERIC MAP (offset=>28,width=>5)
PORT MAP (signbit=>frac(32),inbus=>lastfrac,
position=>position(8)(5 DOWNTO 1));
lastfrac <= frac(3 DOWNTO 1) & frac(32);
gmc: FOR k IN 1 TO 5 GENERATE
count(k) <= (position(1)(k) AND sel(1)) OR
(position(2)(k) AND sel(2)) OR
(position(3)(k) AND sel(3)) OR
(position(4)(k) AND sel(4)) OR
(position(5)(k) AND sel(5)) OR
(position(6)(k) AND sel(6)) OR
(position(7)(k) AND sel(7)) OR
(position(8)(k) AND sel(8));
END GENERATE;
count(6) <= '0';
END rtl;
|
mit
|
Reiuiji/ECE368-Lab
|
Lab 2/ALU/load_store_unit.vhd
|
11
|
1366
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Logic_Unit
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Load/Store Unit
-- Operations - Load/Store to a register
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Load_Store_Unit is
Port ( CLK : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (7 downto 0);
IMMED : in STD_LOGIC_VECTOR (7 downto 0);
OP : in STD_LOGIC_VECTOR (3 downto 0);
RESULT : out STD_LOGIC_VECTOR (7 downto 0));
end Load_Store_Unit;
architecture Behavioral of Load_Store_Unit is
signal reg : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal w_en : std_logic := '0';-- '1' = write, '0' = read
begin
w_en <= '1' when OP="1010" else '0';
process(CLK)
begin
if (CLK'event and CLK='1') then
if (w_en = '1') then
reg <= A;
end if;
end if;
end process;
RESULT <= reg;
end Behavioral;
|
mit
|
Reiuiji/ECE368-Lab
|
Lab 2/Counter/counter.vhd
|
1
|
1390
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2014
-- Module Name: counter
-- Project Name: CLOCK COUNTER
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Counter
-- Will increase the counter(output) ever time
-- the clock does a rising action
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
Port ( CLK : in STD_LOGIC;
DIRECTION : in STD_LOGIC;
RST : in STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (7 downto 0));
end counter;
architecture Behavioral of counter is
signal count : std_logic_vector(0 to 7) := "00000000";
begin
process (CLK, RST)
begin
if (RST = '1') then
count <= "00000000";
elsif (CLK'event and CLK = '1') then
if DIRECTION = '1' then
count <= count + 1;
else
count <= count - 1;
end if;
end if;
end process;
COUNT_OUT <= count;
end Behavioral;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
bin_Gaussian_Filter/ip/Gaussian_Filter/dp_neg.vhd
|
10
|
3079
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** DP_NEG.VHD ***
--*** ***
--*** Function: Single Precision Negative Value ***
--*** ***
--*** Created 12/09/09 ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_neg IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
signin : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1);
signout : OUT STD_LOGIC;
exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1);
mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1);
satout, zeroout, nanout : OUT STD_LOGIC
);
END dp_neg;
ARCHITECTURE rtl OF dp_neg IS
signal signff : STD_LOGIC;
signal exponentff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal mantissaff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal expnode : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expzerochk, expmaxchk : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal expzero, expmax : STD_LOGIC;
signal manzerochk : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal manzero, mannonzero : STD_LOGIC;
BEGIN
pin: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
signff <= '0';
FOR k IN 1 TO 11 LOOP
exponentff(k) <= '0';
END LOOP;
FOR k IN 1 TO 52 LOOP
mantissaff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
signff <= NOT(signin);
exponentff <= exponentin;
mantissaff <= mantissain;
END IF;
END IF;
END PROCESS;
expzerochk(1) <= exponentff(1);
expmaxchk(1) <= exponentff(1);
gxa: FOR k IN 2 TO 11 GENERATE
expzerochk(k) <= expzerochk(k-1) OR exponentff(k);
expmaxchk(k) <= expmaxchk(k-1) AND exponentff(k);
END GENERATE;
expzero <= NOT(expzerochk(11));
expmax <= expmaxchk(11);
manzerochk(1) <= mantissaff(1);
gma: FOR k IN 2 TO 52 GENERATE
manzerochk(k) <= manzerochk(k-1) OR mantissaff(k);
END GENERATE;
manzero <= NOT(manzerochk(52));
mannonzero <= manzerochk(52);
signout <= signff;
exponentout <= exponentff;
mantissaout <= mantissaff;
satout <= expmax AND manzero;
zeroout <= expzero;
nanout <= expmax AND mannonzero;
END rtl;
|
mit
|
Reiuiji/ECE368-Lab
|
Lab 4/VGA_Debug/vga_driver.vhd
|
10
|
3053
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2016
-- Module Name: VGA Toplevel
-- Project Name: VGA Toplevel
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Toplevel of the VGA Unit
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
entity VGA_Driver is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
--Data INPUT
DATA_CLK : in STD_LOGIC;
DATA_WE : in STD_LOGIC;
DATA_ADR : in STD_LOGIC_VECTOR (11 downto 0);
DATA : in STD_LOGIC_VECTOR (7 downto 0);
--VGA OUTPUT
HSYNC : out STD_LOGIC;
VSYNC : out STD_LOGIC;
VGARED : out STD_LOGIC_VECTOR (2 downto 0);
VGAGRN : out STD_LOGIC_VECTOR (2 downto 0);
VGABLU : out STD_LOGIC_VECTOR (1 downto 0));
end VGA_Driver;
architecture Structural of VGA_Driver is
signal PCLK : STD_LOGIC;
signal vcount : STD_LOGIC_VECTOR(9 downto 0):= (OTHERS => '0');
signal hcount : STD_LOGIC_VECTOR(9 downto 0):= (OTHERS => '0');
signal blank : STD_LOGIC := '0';
signal MUX8to1_OUT : STD_LOGIC := '0';
signal BUF_ADR : STD_LOGIC_VECTOR(11 downto 0):= (OTHERS => '0');
signal BUF_OUT : STD_LOGIC_VECTOR(7 downto 0):= (OTHERS => '0');
signal FR_ADR : STD_LOGIC_VECTOR(10 downto 0):= (OTHERS => '0');
signal FR_DATA: STD_LOGIC_VECTOR(7 downto 0):= (OTHERS => '0');
signal VGA_ADR : STD_LOGIC_VECTOR(12 downto 0):= (OTHERS => '0');
begin
VGA_ADR <= vcount(8 downto 4)*X"50" + hcount(9 downto 3);
BUF_ADR <= VGA_ADR(11 downto 0);
FR_ADR <= BUF_OUT(6 downto 0) & vcount(3 downto 0);
U1: entity work.CLK_25MHZ
port map( CLK_IN => CLK,
CLK_OUT => PCLK);
U2: entity work.vga_controller
port map( RST => RST,
PIXEL_CLK => PCLK,
HS => HSYNC,
VS => VSYNC,
HCOUNT => hcount,
VCOUNT => vcount,
BLANK => blank);
U3: entity work.RGB
port map( VALUE => MUX8to1_OUT,
BLANK => blank,
RED => VGARED,
GRN => VGAGRN,
BLU => VGABLU);
U4: entity work.MUX8to1
port map( SEL => hcount(2 downto 0),
DATA => FR_DATA,
OUTPUT => MUX8to1_OUT);
U5: entity work.FONT_ROM
port map( CLK => CLK,
ADDR => FR_ADR,
DATA => FR_DATA);
U6: entity work.VGA_BUFFER_RAM
port map( CLKA => DATA_CLK,
WEA(0)=> DATA_WE,
ADDRA => DATA_ADR,
DINA => DATA,
CLKB => CLK,
ADDRB => BUF_ADR,
DOUTB => BUF_OUT);
end Structural;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
bin_Gaussian_Filter/ip/Gaussian_Filter/hcc_cntusgn32.vhd
|
20
|
4321
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CNTUSGN32.VHD ***
--*** ***
--*** Function: Count leading bits in an ***
--*** unsigned 32 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_cntusgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
END hcc_cntusgn32;
ARCHITECTURE rtl OF hcc_cntusgn32 IS
type positiontype IS ARRAY (6 DOWNTO 1) OF STD_LOGIC_VECTOR (6 DOWNTO 1);
signal sec, sel : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal lastfrac : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal position : positiontype;
component hcc_usgnpos IS
GENERIC (start : integer := 10);
PORT (
ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
BEGIN
-- for single 32 bit mantissa
-- [S ][O....O][1 ][M...M][RGS]
-- [32][31..28][27][26..4][321] - NB underflow can run into RGS
-- for single 36 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [36][35..32][31][30..8][7..4][321]
-- for double 64 bit mantissa
-- [S ][O....O][1 ][M...M][O..O][RGS]
-- [64][63..60][59][58..7][6..4][321] - NB underflow less than overflow
-- find first leading '1' in inexact portion for 32 bit positive number
sec(1) <= frac(31) OR frac(30) OR frac(29) OR frac(28) OR frac(27) OR frac(26);
sec(2) <= frac(25) OR frac(24) OR frac(23) OR frac(22) OR frac(21) OR frac(20);
sec(3) <= frac(19) OR frac(18) OR frac(17) OR frac(16) OR frac(15) OR frac(14);
sec(4) <= frac(13) OR frac(12) OR frac(11) OR frac(10) OR frac(9) OR frac(8);
sec(5) <= frac(7) OR frac(6) OR frac(5) OR frac(4) OR frac(3) OR frac(2);
sec(6) <= frac(1);
sel(1) <= sec(1);
sel(2) <= sec(2) AND NOT(sec(1));
sel(3) <= sec(3) AND NOT(sec(2)) AND NOT(sec(1));
sel(4) <= sec(4) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(5) <= sec(5) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
sel(6) <= sec(6) AND NOT(sec(5)) AND NOT(sec(4)) AND NOT(sec(3)) AND NOT(sec(2)) AND NOT(sec(1));
pone: hcc_usgnpos
GENERIC MAP (start=>0)
PORT MAP (ingroup=>frac(31 DOWNTO 26),
position=>position(1)(6 DOWNTO 1));
ptwo: hcc_usgnpos
GENERIC MAP (start=>6)
PORT MAP (ingroup=>frac(25 DOWNTO 20),
position=>position(2)(6 DOWNTO 1));
pthr: hcc_usgnpos
GENERIC MAP (start=>12)
PORT MAP (ingroup=>frac(19 DOWNTO 14),
position=>position(3)(6 DOWNTO 1));
pfor: hcc_usgnpos
GENERIC MAP (start=>18)
PORT MAP (ingroup=>frac(13 DOWNTO 8),
position=>position(4)(6 DOWNTO 1));
pfiv: hcc_usgnpos
GENERIC MAP (start=>24)
PORT MAP (ingroup=>frac(7 DOWNTO 2),
position=>position(5)(6 DOWNTO 1));
psix: hcc_usgnpos
GENERIC MAP (start=>30)
PORT MAP (ingroup=>lastfrac,
position=>position(6)(6 DOWNTO 1));
lastfrac <= frac(1) & "00000";
gmc: FOR k IN 1 TO 6 GENERATE
count(k) <= (position(1)(k) AND sel(1)) OR
(position(2)(k) AND sel(2)) OR
(position(3)(k) AND sel(3)) OR
(position(4)(k) AND sel(4)) OR
(position(5)(k) AND sel(5)) OR
(position(6)(k) AND sel(6));
END GENERATE;
END rtl;
|
mit
|
Reiuiji/ECE368-Lab
|
Examples/Templates/VHDL-Template-Structural.vhd
|
1
|
1663
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Class: ECE 368 Digital Design
-- Engineer: [Engineer 1]
-- [Engineer 2]
--
-- Create Date: [Date]
-- Module Name: [Module Name]
-- Project Name: [Project Name]
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
--
-- Description:
-- [Insert Description]
--
-- Notes:
-- [Insert Notes]
--
-- Revision:
-- [Insert Revision]
--
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity [Name]_TopLevel_design is
PORT (
CLOCK : in STD_LOGIC;
[IN_Port0] : in STD_LOGIC;
[IN_Port1] : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
[OUT_Port0] : out STD_LOGIC;
[OUT_Port1] : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
);
end [Name]_TopLevel_design;
architecture Structural of [Name]_TopLevel_design is
signal [IN_Port0] : in STD_LOGIC;
signal [IN_Port1] : in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0);
signal [OUT_Port0] : out STD_LOGIC;
signal [OUT_Port1] : out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0)
begin
[OUT_PORT] <= [DATA_OUT];
----- Structural Components: -----
-- [Name] UNIT
[Name]_Unit : entity work.Unit_File
port map (
--COMPONENT SIGNAL
CLOCK => CLOCK,
[IN_Port0] => [IN_Port0],
[IN_Port1] => [IN_Port1],
[OUT_Port0] => [OUT_Port0],
[OUT_Port1] => [OUT_Port1]
);
end Structural;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
Gaussian_Filter/ip/Gaussian_Filter/fp_exp_s5.vhd
|
10
|
3109
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_exp_s5
-- VHDL created on Tue Mar 12 11:36:13 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.hcc_package_cmd.all;
use work.math_package_cmd.all;
use work.fpc_library_package_cmd.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_exp_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_exp_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal fpExpTest_reset : std_logic;
signal fpExpTest_q : std_logic_vector (31 downto 0);
-- synopsys translate off
signal fpExpTest_q_real : REAL;
-- synopsys translate on
begin
--GND(CONSTANT,0)
--VCC(CONSTANT,1)
--xIn(GPIN,3)@0
--fpExpTest(FLOATEXP,2)@0
fpExpTest_reset <= areset;
fpExpTest_inst : fp_exp_sIEEE_2_sIEEE
PORT MAP (
clk_en => '1',
clock => clk,
reset => fpExpTest_reset,
dataa => a,
result => fpExpTest_q
);
-- synopsys translate off
fpExpTest_q_real <= sIEEE_2_real(fpExpTest_q);
-- synopsys translate on
--xOut(GPOUT,4)@16
q <= fpExpTest_q;
end normal;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
Gaussian_Filter/ip/Gaussian_Filter/fp_lsft23.vhd
|
10
|
4244
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_LSFT23.VHD ***
--*** ***
--*** Function: 23 bit Left Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_lsft23 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (23 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (23 DOWNTO 1)
);
END fp_lsft23;
ARCHITECTURE sft OF fp_lsft23 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (23 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
gaa: FOR k IN 4 TO 23 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
gbb: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
gbc: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
gbd: FOR k IN 13 TO 23 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5)));
END GENERATE;
gcb: FOR k IN 17 TO 23 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(5))) OR
(levtwo(k-16) AND shift(5));
END GENERATE;
outbus <= levthr;
END sft;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
bin_Gaussian_Filter/ip/Gaussian_Filter/fp_rsft78.vhd
|
10
|
3744
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_RSFT78.VHD ***
--*** ***
--*** Function: 78 bit Arithmetic Right Shift ***
--*** ***
--*** 22/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_rsft78 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (78 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (78 DOWNTO 1)
);
END fp_rsft78;
ARCHITECTURE rtl of fp_rsft78 IS
signal levzip, levone, levtwo : STD_LOGIC_VECTOR (78 DOWNTO 1);
signal levthr, levfor, levfiv : STD_LOGIC_VECTOR (78 DOWNTO 1);
signal levsix : STD_LOGIC_VECTOR (78 DOWNTO 1);
BEGIN
levzip <= inbus;
gaa: FOR k IN 1 TO 77 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(1))) OR (levzip(k+1) AND shift(1));
END GENERATE;
levone(78) <= levzip(78) AND NOT(shift(1));
gba: FOR k IN 1 TO 76 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(2))) OR (levone(k+2) AND shift(2));
END GENERATE;
levtwo(77) <= levone(77) AND NOT(shift(2));
levtwo(78) <= levone(78) AND NOT(shift(2));
gca: FOR k IN 1 TO 74 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(3))) OR (levtwo(k+4) AND shift(3));
END GENERATE;
gcb: FOR k IN 75 TO 78 GENERATE
levthr(k) <= levtwo(k) AND NOT(shift(3));
END GENERATE;
gda: FOR k IN 1 TO 70 GENERATE
levfor(k) <= (levthr(k) AND NOT(shift(4))) OR (levthr(k+8) AND shift(4));
END GENERATE;
gdb: FOR k IN 71 TO 78 GENERATE
levfor(k) <= levthr(k) AND NOT(shift(4));
END GENERATE;
gea: FOR k IN 1 TO 62 GENERATE
levfiv(k) <= (levfor(k) AND NOT(shift(5))) OR (levfor(k+16) AND shift(5));
END GENERATE;
geb: FOR k IN 63 TO 78 GENERATE
levfiv(k) <= levfor(k) AND NOT(shift(5));
END GENERATE;
gfa: FOR k IN 1 TO 46 GENERATE
levsix(k) <= (levfiv(k) AND NOT(shift(6))) OR (levfiv(k+32) AND shift(6));
END GENERATE;
gfb: FOR k IN 47 TO 78 GENERATE
levsix(k) <= levfiv(k) AND NOT(shift(6));
END GENERATE;
outbus <= levsix;
END;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
Gaussian_Filter/ip/Gaussian_Filter/fp_sincos_s5.vhd
|
10
|
671358
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_sincos_s5
-- VHDL created on Wed Mar 27 09:55:14 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_sincos_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
s : out std_logic_vector(31 downto 0);
c : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_sincos_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid8_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBias_uid22_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasM1_uid23_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShift_uid24_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid25_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstBiasMwShiftM2_uid26_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cstZwShiftP1_uid27_fpSinCosXTest_q : std_logic_vector (13 downto 0);
signal cstNaNwF_uid32_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal cstZmwFRRPwSM1_uid52_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal cPi_uid71_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal p_uid73_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal p_uid73_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal expPSin_uid76_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal expPSin_uid76_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal multSinOp2_uid91_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal multSinOp2_uid91_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_a : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal mulSin_uid92_fpSinCosXTest_s1 : std_logic_vector (51 downto 0);
signal mulSin_uid92_fpSinCosXTest_pr : UNSIGNED (51 downto 0);
signal mulSin_uid92_fpSinCosXTest_q : std_logic_vector (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_a : std_logic_vector (25 downto 0);
signal mulCos_uid105_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal mulCos_uid105_fpSinCosXTest_s1 : std_logic_vector (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_pr : UNSIGNED (51 downto 0);
signal mulCos_uid105_fpSinCosXTest_q : std_logic_vector (51 downto 0);
signal excSelSin_uid119_fpSinCosXTest_q : std_logic_vector(1 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRSinFull_uid133_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expSelectorCos_uid145_fpSinCosXTest_q : std_logic_vector(1 downto 0);
signal signRCond2_uid152_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_d : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRCond2_uid152_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_d : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal signRCond1_uid157_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q : std_logic_vector (29 downto 0);
signal leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (11 downto 0);
signal leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal zs_uid236_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(63 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal mO_uid239_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (62 downto 0);
signal zs_uid244_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal zs_uid250_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (5 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(63 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(63 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i : std_logic_vector(0 downto 0);
signal vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (47 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a : std_logic_vector (12 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr : SIGNED (26 downto 0);
signal prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q : std_logic_vector (25 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a : std_logic_vector (14 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b : std_logic_vector (22 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr : SIGNED (38 downto 0);
signal prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q : std_logic_vector (37 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a : std_logic_vector (12 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 : std_logic_vector (25 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr : SIGNED (26 downto 0);
signal prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q : std_logic_vector (25 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a : std_logic_vector (14 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b : std_logic_vector (22 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr : SIGNED (38 downto 0);
signal prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q : std_logic_vector (37 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0 : std_logic;
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0 : std_logic;
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa : std_logic_vector (7 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab : std_logic_vector (7 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq : std_logic_vector (39 downto 0);
signal rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q : std_logic_vector (39 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr : UNSIGNED (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a : std_logic_vector(81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b : std_logic_vector(81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o : std_logic_vector (81 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q : std_logic_vector (81 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC0_uid394_tableGensinPiZ_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid394_tableGensinPiZ_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC1_uid396_tableGensinPiZ_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid396_tableGensinPiZ_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_reset0 : std_logic;
signal memoryC2_uid398_tableGensinPiZ_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid398_tableGensinPiZ_lutmem_q : std_logic_vector (12 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC0_uid400_tableGencosPiZ_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid400_tableGencosPiZ_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC1_uid402_tableGencosPiZ_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid402_tableGencosPiZ_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_reset0 : std_logic;
signal memoryC2_uid404_tableGencosPiZ_lutmem_ia : std_logic_vector (12 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_aa : std_logic_vector (7 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_ab : std_logic_vector (7 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_iq : std_logic_vector (12 downto 0);
signal memoryC2_uid404_tableGencosPiZ_lutmem_q : std_logic_vector (12 downto 0);
signal reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q : std_logic_vector (2 downto 0);
signal reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q : std_logic_vector (39 downto 0);
signal reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (39 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q : std_logic_vector (26 downto 0);
signal reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (15 downto 0);
signal reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (1 downto 0);
signal reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (1 downto 0);
signal reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q : std_logic_vector (77 downto 0);
signal reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (77 downto 0);
signal reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q : std_logic_vector (67 downto 0);
signal reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q : std_logic_vector (67 downto 0);
signal reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q : std_logic_vector (66 downto 0);
signal reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q : std_logic_vector (65 downto 0);
signal reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q : std_logic_vector (67 downto 0);
signal reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q : std_logic_vector (25 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q : std_logic_vector (12 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q : std_logic_vector (20 downto 0);
signal reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q : std_logic_vector (22 downto 0);
signal reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q : std_logic_vector (29 downto 0);
signal reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q : std_logic_vector (6 downto 0);
signal reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q : std_logic_vector (0 downto 0);
signal reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q : std_logic_vector (3 downto 0);
signal reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q : std_logic_vector (3 downto 0);
signal reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q : std_logic_vector (0 downto 0);
signal reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q : std_logic_vector (64 downto 0);
signal reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q : std_logic_vector (64 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q : std_logic_vector (12 downto 0);
signal reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q : std_logic_vector (12 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q : std_logic_vector (20 downto 0);
signal reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q : std_logic_vector (22 downto 0);
signal reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q : std_logic_vector (7 downto 0);
signal reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q : std_logic_vector (29 downto 0);
signal reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q : std_logic_vector (25 downto 0);
signal reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q : std_logic_vector (25 downto 0);
signal reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q : std_logic_vector (6 downto 0);
signal reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q : std_logic_vector (7 downto 0);
signal reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q : std_logic_vector (1 downto 0);
signal reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q : std_logic_vector (22 downto 0);
signal reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q : std_logic_vector (3 downto 0);
signal reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q : std_logic_vector (7 downto 0);
signal reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q : std_logic_vector (0 downto 0);
signal reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q : std_logic_vector (0 downto 0);
signal ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q : std_logic_vector (52 downto 0);
signal ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q : std_logic_vector (65 downto 0);
signal ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q : std_logic_vector (67 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q : std_logic_vector (0 downto 0);
signal ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q : std_logic_vector (0 downto 0);
signal ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (7 downto 0);
signal ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (66 downto 0);
signal ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (65 downto 0);
signal ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q : std_logic_vector (64 downto 0);
signal ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q : std_logic_vector (63 downto 0);
signal ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (58 downto 0);
signal ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q : std_logic_vector (63 downto 0);
signal ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q : std_logic_vector (31 downto 0);
signal ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q : std_logic_vector (31 downto 0);
signal ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (62 downto 0);
signal ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (60 downto 0);
signal ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (58 downto 0);
signal ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q : std_logic_vector (0 downto 0);
signal ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q : std_logic_vector (0 downto 0);
signal ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (76 downto 0);
signal ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (75 downto 0);
signal ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q : std_logic_vector (74 downto 0);
signal ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q : std_logic_vector (12 downto 0);
signal ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q : std_logic_vector (53 downto 0);
signal ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q : std_logic_vector (1 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q : std_logic_vector (12 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q : std_logic_vector (0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0 : std_logic;
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q : signal is true;
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q : std_logic_vector (6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0 : std_logic;
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q : std_logic_vector (31 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q : signal is true;
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (22 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0 : std_logic;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq : std_logic;
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q : std_logic_vector (4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q : signal is true;
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q : std_logic_vector (64 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q : std_logic_vector (32 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q : std_logic_vector (64 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (61 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (45 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 : std_logic;
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q : std_logic_vector (29 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q : signal is true;
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0 : std_logic;
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q : std_logic_vector (77 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q : signal is true;
signal ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0 : std_logic;
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq : std_logic;
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q : signal is true;
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0 : std_logic;
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q : std_logic_vector (2 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q : signal is true;
signal ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q : std_logic_vector (12 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0 : std_logic;
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0 : std_logic;
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q : signal is true;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0 : std_logic;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq : std_logic;
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q : std_logic_vector (2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q : signal is true;
signal sinXIsXRR_uid41_fpSinCosXTest_a : std_logic_vector(11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_b : std_logic_vector(11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_o : std_logic_vector (11 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal sinXIsXRR_uid41_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_a : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_b : std_logic_vector(11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_o : std_logic_vector (11 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOneXRR_uid42_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal yIsZero_uid51_fpSinCosXTest_a : std_logic_vector(65 downto 0);
signal yIsZero_uid51_fpSinCosXTest_b : std_logic_vector(65 downto 0);
signal yIsZero_uid51_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal pad_one_uid55_fpSinCosXTest_q : std_logic_vector (66 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_a : std_logic_vector(70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_b : std_logic_vector(70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_o : std_logic_vector (70 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal cmpYToOneMinusY_uid57_fpSinCosXTest_c : std_logic_vector (0 downto 0);
signal leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal InvCmpYToOneMinusY_uid61_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCmpYToOneMinusY_uid61_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid127_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsX_uid127_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvSinXIsXRR_uid128_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvSinXIsXRR_uid128_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_I_uid131_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_I_uid131_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvExc_N_uid132_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvExc_N_uid132_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid136_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOneXRR_uid136_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvCosXONe_uid149_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvCosXONe_uid149_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvYIsZero_uid151_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvYIsZero_uid151_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal InvIntXParity_uid155_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvIntXParity_uid155_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal oFracXRR_uid43_uid43_fpSinCosXTest_q : std_logic_vector (53 downto 0);
signal half_uid53_fpSinCosXTest_q : std_logic_vector (65 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q : std_logic_vector (1 downto 0);
signal exp_uid9_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal exp_uid9_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal frac_uid13_fpSinCosXTest_in : std_logic_vector (22 downto 0);
signal frac_uid13_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal signX_uid37_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal signX_uid37_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal expFracX_uid166_px_uid33_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal expFracX_uid166_px_uid33_fpSinCosXTest_b : std_logic_vector (30 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid10_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid12_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid14_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid15_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal sinXIsX_uid40_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal fxpXShiftValExt_uid45_fpSinCosXTest_q : std_logic_vector (9 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_a : std_logic_vector(65 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_b : std_logic_vector(65 downto 0);
signal yIsHalf_uid54_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_a : std_logic_vector(67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_b : std_logic_vector(67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_o : std_logic_vector (67 downto 0);
signal oneMinusY_uid55_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal zSin_uid60_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal zSin_uid60_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal zCos_uid64_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal zCos_uid64_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal expSinHC_uid74_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expSinHC_uid74_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expHardCase_uid78_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal excRNaN_uid117_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid117_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid117_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracRPostExcSin_uid122_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExcSin_uid122_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExcSin_uid126_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExcSin_uid126_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal yHalfCosXNotOne_uid138_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal rZOrOne_uid140_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fracRPostExcCos_uid142_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal fracRPostExcCos_uid142_fpSinCosXTest_q : std_logic_vector (22 downto 0);
signal expRPostExcCos_uid147_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal expRPostExcCos_uid147_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal cosXONe_uid148_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal cosXONe_uid148_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal cosXONe_uid148_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCos_uid158_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signRCosFull_uid161_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal finalExp_uid209_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal finalExp_uid209_rrx_uid34_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(7 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(7 downto 0);
signal vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(31 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(31 downto 0);
signal vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (7 downto 0);
signal vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal extendedFracX_uid47_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal normBitSin_uid93_fpSinCosXTest_in : std_logic_vector (51 downto 0);
signal normBitSin_uid93_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal fracRSinPreRndHigh_uid95_fpSinCosXTest_in : std_logic_vector (50 downto 0);
signal fracRSinPreRndHigh_uid95_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracRSinPreRndLow_uid96_fpSinCosXTest_in : std_logic_vector (49 downto 0);
signal fracRSinPreRndLow_uid96_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal normBitCos_uid106_fpSinCosXTest_in : std_logic_vector (51 downto 0);
signal normBitCos_uid106_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal fracRCosPreRndHigh_uid108_fpSinCosXTest_in : std_logic_vector (50 downto 0);
signal fracRCosPreRndHigh_uid108_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracRCosPreRndLow_uid109_fpSinCosXTest_in : std_logic_vector (49 downto 0);
signal fracRCosPreRndLow_uid109_fpSinCosXTest_b : std_logic_vector (23 downto 0);
signal fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q : std_logic_vector (52 downto 0);
signal leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in : std_logic_vector (25 downto 0);
signal prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b : std_logic_vector (13 downto 0);
signal prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b : std_logic_vector (23 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int : std_logic_vector (80 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q : std_logic_vector (80 downto 0);
signal os_uid196_rrx_uid34_fpSinCosXTest_q : std_logic_vector (79 downto 0);
signal leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal join_uid99_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal join_uid141_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal zSinYBottom_uid59_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal zSinYBottom_uid59_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal zSinOMyBottom_uid58_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal zSinOMyBottom_uid58_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal excSelBitsSin_uid118_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal fpSin_uid134_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal join_uid143_fpSinCosXTest_q : std_logic_vector (2 downto 0);
signal fpCos_uid162_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (63 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int : std_logic_vector (107 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q : std_logic_vector (107 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a : std_logic_vector(6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b : std_logic_vector(6 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal fracX_uid187_rrx_uid34_fpSinCosXTest_in : std_logic_vector (22 downto 0);
signal fracX_uid187_rrx_uid34_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a : std_logic_vector(4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b : std_logic_vector(4 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b : std_logic_vector(0 downto 0);
signal ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a : std_logic_vector(2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b : std_logic_vector(2 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q : std_logic_vector(0 downto 0);
signal oFracXRRSmallXRR_uid90_fpSinCosXTest_in : std_logic_vector (53 downto 0);
signal oFracXRRSmallXRR_uid90_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal R_uid167_px_uid33_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal InvFracXIsZero_uid16_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid16_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal fxpXShiftVal_uid46_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal fxpXShiftVal_uid46_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal addr_uid81_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal addr_uid81_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal zPsinPiZ_uid84_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal zPsinPiZ_uid84_fpSinCosXTest_b : std_logic_vector (14 downto 0);
signal rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (32 downto 0);
signal addr_uid83_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal addr_uid83_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal zPcosPiZ_uid87_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal zPcosPiZ_uid87_fpSinCosXTest_b : std_logic_vector (14 downto 0);
signal rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (32 downto 0);
signal X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (32 downto 0);
signal expSinHCR_uid75_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expSinHCR_uid75_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal expPCos_uid79_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expPCos_uid79_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (66 downto 0);
signal LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (66 downto 0);
signal LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (65 downto 0);
signal LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (64 downto 0);
signal rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (58 downto 0);
signal rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (60 downto 0);
signal LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (58 downto 0);
signal LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (58 downto 0);
signal rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (3 downto 0);
signal rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (76 downto 0);
signal LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (76 downto 0);
signal LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (75 downto 0);
signal LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (75 downto 0);
signal LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (74 downto 0);
signal X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (59 downto 0);
signal X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (59 downto 0);
signal X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (55 downto 0);
signal X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (55 downto 0);
signal fracRSinPreRnd_uid97_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal fracRSinPreRnd_uid97_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal fracRCosPreRnd_uid110_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal fracRCosPreRnd_uid110_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal cosRndOp_uid112_uid113_fpSinCosXTest_q : std_logic_vector (24 downto 0);
signal rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal lowRangeB_uid408_polyEvalsinPiZ_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid408_polyEvalsinPiZ_b : std_logic_vector (0 downto 0);
signal highBBits_uid409_polyEvalsinPiZ_in : std_logic_vector (13 downto 0);
signal highBBits_uid409_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid414_polyEvalsinPiZ_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid414_polyEvalsinPiZ_b : std_logic_vector (1 downto 0);
signal highBBits_uid415_polyEvalsinPiZ_in : std_logic_vector (23 downto 0);
signal highBBits_uid415_polyEvalsinPiZ_b : std_logic_vector (21 downto 0);
signal lowRangeB_uid421_polyEvalcosPiZ_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid421_polyEvalcosPiZ_b : std_logic_vector (0 downto 0);
signal highBBits_uid422_polyEvalcosPiZ_in : std_logic_vector (13 downto 0);
signal highBBits_uid422_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal lowRangeB_uid427_polyEvalcosPiZ_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid427_polyEvalcosPiZ_b : std_logic_vector (1 downto 0);
signal highBBits_uid428_polyEvalcosPiZ_in : std_logic_vector (23 downto 0);
signal highBBits_uid428_polyEvalcosPiZ_b : std_logic_vector (21 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in : std_logic_vector (53 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in : std_logic_vector (80 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b : std_logic_vector (26 downto 0);
signal fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in : std_logic_vector (76 downto 0);
signal fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b : std_logic_vector (52 downto 0);
signal intXParity_uid49_fpSinCosXTest_in : std_logic_vector (67 downto 0);
signal intXParity_uid49_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal y_uid50_fpSinCosXTest_in : std_logic_vector (66 downto 0);
signal y_uid50_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal sinRndOp_uid100_uid101_fpSinCosXTest_q : std_logic_vector (25 downto 0);
signal LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (63 downto 0);
signal expSelBitsCos_uid144_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a : std_logic_vector(108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b : std_logic_vector(108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o : std_logic_vector (108 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q : std_logic_vector (108 downto 0);
signal oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q : std_logic_vector (23 downto 0);
signal expX_uid186_rrx_uid34_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal expX_uid186_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal exc_N_uid17_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid17_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal yT1_uid406_polyEvalsinPiZ_in : std_logic_vector (14 downto 0);
signal yT1_uid406_polyEvalsinPiZ_b : std_logic_vector (12 downto 0);
signal yT1_uid419_polyEvalcosPiZ_in : std_logic_vector (14 downto 0);
signal yT1_uid419_polyEvalcosPiZ_b : std_logic_vector (12 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(15 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(15 downto 0);
signal vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (15 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(1 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(1 downto 0);
signal vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (1 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(3 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(3 downto 0);
signal vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (3 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q : std_logic_vector (67 downto 0);
signal expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q : std_logic_vector (31 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_a : std_logic_vector(32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_b : std_logic_vector(32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_o : std_logic_vector (32 downto 0);
signal expFracRCos_uid114_fpSinCosXTest_q : std_logic_vector (32 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid410_polyEvalsinPiZ_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid416_polyEvalsinPiZ_q : std_logic_vector (30 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid423_polyEvalcosPiZ_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid429_polyEvalcosPiZ_q : std_logic_vector (30 downto 0);
signal finalFrac_uid208_rrx_uid34_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal finalFrac_uid208_rrx_uid34_fpSinCosXTest_q : std_logic_vector (52 downto 0);
signal signComp_uid129_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_c : std_logic_vector(0 downto 0);
signal signComp_uid129_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_a : std_logic_vector(32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_b : std_logic_vector(32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_o : std_logic_vector (32 downto 0);
signal expFracRSin_uid102_fpSinCosXTest_q : std_logic_vector (32 downto 0);
signal leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal multFracBits_uid199_rrx_uid34_fpSinCosXTest_in : std_logic_vector (77 downto 0);
signal multFracBits_uid199_rrx_uid34_fpSinCosXTest_b : std_logic_vector (77 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in : std_logic_vector (26 downto 0);
signal prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b : std_logic_vector (26 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_a : std_logic_vector(10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_b : std_logic_vector(10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_o : std_logic_vector (10 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_cin : std_logic_vector (0 downto 0);
signal xBranch_uid191_rrx_uid34_fpSinCosXTest_n : std_logic_vector (0 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q : std_logic_vector (5 downto 0);
signal fracRCompCos_uid115_fpSinCosXTest_in : std_logic_vector (23 downto 0);
signal fracRCompCos_uid115_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal expRCompSin_uid116_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal expRCompSin_uid116_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal s1_uid408_uid411_polyEvalsinPiZ_q : std_logic_vector (22 downto 0);
signal s2_uid414_uid417_polyEvalsinPiZ_q : std_logic_vector (32 downto 0);
signal s1_uid421_uid424_polyEvalcosPiZ_q : std_logic_vector (22 downto 0);
signal s2_uid427_uid430_polyEvalcosPiZ_q : std_logic_vector (32 downto 0);
signal RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q : std_logic_vector (61 downto 0);
signal signR_uid130_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal signR_uid130_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal signR_uid130_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal fracRCompSin_uid103_fpSinCosXTest_in : std_logic_vector (23 downto 0);
signal fracRCompSin_uid103_fpSinCosXTest_b : std_logic_vector (22 downto 0);
signal expRCompSin_uid104_fpSinCosXTest_in : std_logic_vector (31 downto 0);
signal expRCompSin_uid104_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in : std_logic_vector (77 downto 0);
signal multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b : std_logic_vector (31 downto 0);
signal X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (61 downto 0);
signal X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (61 downto 0);
signal X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (45 downto 0);
signal X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (45 downto 0);
signal X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (29 downto 0);
signal X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (29 downto 0);
signal expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b : std_logic_vector(0 downto 0);
signal vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector(0 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a : std_logic_vector(8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b : std_logic_vector(8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o : std_logic_vector (8 downto 0);
signal expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q : std_logic_vector (8 downto 0);
signal leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (5 downto 0);
signal leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (3 downto 0);
signal leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (1 downto 0);
signal leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal polyEvalSigsinPiZ_uid86_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal polyEvalSigsinPiZ_uid86_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal polyEvalSigcosPiZ_uid89_fpSinCosXTest_in : std_logic_vector (30 downto 0);
signal polyEvalSigcosPiZ_uid89_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal expXRR_uid38_fpSinCosXTest_in : std_logic_vector (60 downto 0);
signal expXRR_uid38_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal fracXRR_uid39_fpSinCosXTest_in : std_logic_vector (52 downto 0);
signal fracXRR_uid39_fpSinCosXTest_b : std_logic_vector (52 downto 0);
signal pHigh_uid72_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal pHigh_uid72_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal pCos_uid77_fpSinCosXTest_in : std_logic_vector (64 downto 0);
signal pCos_uid77_fpSinCosXTest_b : std_logic_vector (25 downto 0);
signal r_uid277_lzcZSin_uid66_fpSinCosXTest_q : std_logic_vector (6 downto 0);
signal r_uid356_lzcZCos_uid69_fpSinCosXTest_q : std_logic_vector (6 downto 0);
signal expCompOut_uid205_rrx_uid34_fpSinCosXTest_in : std_logic_vector (7 downto 0);
signal expCompOut_uid205_rrx_uid34_fpSinCosXTest_b : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (0 downto 0);
signal LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (73 downto 0);
signal LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (73 downto 0);
signal LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (69 downto 0);
signal LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (69 downto 0);
signal LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in : std_logic_vector (65 downto 0);
signal LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b : std_logic_vector (65 downto 0);
signal leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q : std_logic_vector (77 downto 0);
signal LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (56 downto 0);
signal LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (48 downto 0);
signal LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (48 downto 0);
signal LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in : std_logic_vector (40 downto 0);
signal LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b : std_logic_vector (40 downto 0);
signal LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (56 downto 0);
signal LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (48 downto 0);
signal LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (48 downto 0);
signal LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in : std_logic_vector (40 downto 0);
signal LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b : std_logic_vector (40 downto 0);
signal leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
signal leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q : std_logic_vector (64 downto 0);
begin
--xIn(GPIN,3)@0
--GND(CONSTANT,0)
GND_q <= "0";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable(LOGICAL,1282)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q <= not ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_a;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor(LOGICAL,1422)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q <= not (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_a or ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_b);
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top(CONSTANT,1418)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q <= "01011";
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp(LOGICAL,1419)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_mem_top_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q <= "1" when ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_a = ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_b else "0";
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg(REG,1420)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena(REG,1423)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_nor_q = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd(LOGICAL,1424)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_sticky_ena_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b <= en;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_a and ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_b;
--expFracX_uid166_px_uid33_fpSinCosXTest(BITSELECT,165)@0
expFracX_uid166_px_uid33_fpSinCosXTest_in <= a(30 downto 0);
expFracX_uid166_px_uid33_fpSinCosXTest_b <= expFracX_uid166_px_uid33_fpSinCosXTest_in(30 downto 0);
--R_uid167_px_uid33_fpSinCosXTest(BITJOIN,166)@0
R_uid167_px_uid33_fpSinCosXTest_q <= GND_q & expFracX_uid166_px_uid33_fpSinCosXTest_b;
--expX_uid186_rrx_uid34_fpSinCosXTest(BITSELECT,185)@0
expX_uid186_rrx_uid34_fpSinCosXTest_in <= R_uid167_px_uid33_fpSinCosXTest_q(30 downto 0);
expX_uid186_rrx_uid34_fpSinCosXTest_b <= expX_uid186_rrx_uid34_fpSinCosXTest_in(30 downto 23);
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg(DELAY,1412)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expX_uid186_rrx_uid34_fpSinCosXTest_b, xout => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt(COUNTER,1414)
-- every=1, low=0, high=11, step=1, init=1
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i = 10 THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i - 11;
ELSE
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg(REG,1415)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux(MUX,1416)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem(DUALMEM,1413)
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_inputreg_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdreg_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_rdmux_q;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 12,
width_b => 8,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_ia
);
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--zs_uid244_lzcZSin_uid66_fpSinCosXTest(CONSTANT,243)
zs_uid244_lzcZSin_uid66_fpSinCosXTest_q <= "00000000000000000000000000000000";
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor(LOGICAL,1396)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q <= not (ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_a or ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_b);
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg(REG,1318)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena(REG,1397)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_nor_q = "1") THEN
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd(LOGICAL,1398)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_sticky_ena_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b <= en;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_a and ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_b;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg(DELAY,1388)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => R_uid167_px_uid33_fpSinCosXTest_q, xout => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt(COUNTER,1314)
-- every=1, low=0, high=1, step=1, init=1
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_i,1));
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg(REG,1315)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux(MUX,1316)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s <= en;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux: PROCESS (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s, ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q, ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q)
BEGIN
CASE ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_s IS
WHEN "0" => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
WHEN "1" => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdcnt_q;
WHEN OTHERS => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem(DUALMEM,1389)
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_inputreg_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 32,
widthad_a => 1,
numwords_a => 2,
width_b => 32,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq,
address_a => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_aa,
data_a => ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_ia
);
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_reset0 <= areset;
ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_iq(31 downto 0);
--fracX_uid187_rrx_uid34_fpSinCosXTest(BITSELECT,186)@4
fracX_uid187_rrx_uid34_fpSinCosXTest_in <= ld_R_uid167_px_uid33_fpSinCosXTest_q_to_fracX_uid187_rrx_uid34_fpSinCosXTest_a_replace_mem_q(22 downto 0);
fracX_uid187_rrx_uid34_fpSinCosXTest_b <= fracX_uid187_rrx_uid34_fpSinCosXTest_in(22 downto 0);
--oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest(BITJOIN,196)@4
oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q <= VCC_q & fracX_uid187_rrx_uid34_fpSinCosXTest_b;
--prod_uid198_rrx_uid34_fpSinCosXTest_b_0(BITSELECT,518)@4
prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in <= STD_LOGIC_VECTOR("000" & oFracX_uid197_uid197_rrx_uid34_fpSinCosXTest_q);
prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b <= prod_uid198_rrx_uid34_fpSinCosXTest_b_0_in(26 downto 0);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1(REG,539)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q <= prod_uid198_rrx_uid34_fpSinCosXTest_b_0_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShift_uid24_fpSinCosXTest(CONSTANT,23)
cstBiasMwShift_uid24_fpSinCosXTest_q <= "01110011";
--expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest(SUB,191)@0
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expX_uid186_rrx_uid34_fpSinCosXTest_b);
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0" & cstBiasMwShift_uid24_fpSinCosXTest_q);
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_b));
expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q <= expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_o(8 downto 0);
--expXTableAddr_uid193_rrx_uid34_fpSinCosXTest(BITSELECT,192)@0
expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in <= expXTableAddrExt_uid192_rrx_uid34_fpSinCosXTest_q(7 downto 0);
expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b <= expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0(REG,534)@0
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q <= expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem(DUALMEM,514)@1
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia <= (others => '0');
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa <= (others => '0');
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab <= reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q;
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq,
address_a => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_aa,
data_a => rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_ia
);
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_reset0 <= areset;
rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q <= rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1(REG,537)@3
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q <= rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem(DUALMEM,513)@1
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia <= (others => '0');
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa <= (others => '0');
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab <= reg_expXTableAddr_uid193_rrx_uid34_fpSinCosXTest_0_to_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_q;
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 40,
widthad_a => 8,
numwords_a => 140,
width_b => 40,
widthad_b => 8,
numwords_b => 140,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0,
clock0 => clk,
address_b => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ab,
-- data_b => (others => '0'),
q_b => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq,
address_a => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_aa,
data_a => rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_ia
);
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_reset0 <= areset;
rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q <= rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_iq(39 downto 0);
--reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0(REG,536)@3
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q <= "0000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q <= rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_q;
END IF;
END IF;
END PROCESS;
--os_uid196_rrx_uid34_fpSinCosXTest(BITJOIN,195)@4
os_uid196_rrx_uid34_fpSinCosXTest_q <= reg_rrTable_uid195_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_1_q & reg_rrTable_uid194_rrx_uid34_fpSinCosXTest_lutmem_0_to_os_uid196_rrx_uid34_fpSinCosXTest_0_q;
--prod_uid198_rrx_uid34_fpSinCosXTest_a_2(BITSELECT,517)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in <= STD_LOGIC_VECTOR("0" & os_uid196_rrx_uid34_fpSinCosXTest_q);
prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_2_in(80 downto 54);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0(REG,542)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_2_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0(MULT,521)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_2_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_s1;
END IF;
END IF;
END PROCESS;
--ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a(DELAY,1145)@8
ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a : dspba_delay
GENERIC MAP ( width => 54, depth => 1 )
PORT MAP ( xin => prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q, xout => ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset );
--prod_uid198_rrx_uid34_fpSinCosXTest_align_2(BITSHIFT,524)@9
prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int <= ld_prod_uid198_rrx_uid34_fpSinCosXTest_a2_b0_q_to_prod_uid198_rrx_uid34_fpSinCosXTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000";
prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q_int(107 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_a_1(BITSELECT,516)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in <= os_uid196_rrx_uid34_fpSinCosXTest_q(53 downto 0);
prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_1_in(53 downto 27);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0(REG,540)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_1_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0(MULT,520)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_1_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_align_1(BITSHIFT,523)@8
prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int <= prod_uid198_rrx_uid34_fpSinCosXTest_a1_b0_q & "000000000000000000000000000";
prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q_int(80 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_a_0(BITSELECT,515)@4
prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in <= os_uid196_rrx_uid34_fpSinCosXTest_q(26 downto 0);
prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b <= prod_uid198_rrx_uid34_fpSinCosXTest_a_0_in(26 downto 0);
--reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0(REG,538)@4
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a_0_b;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0(MULT,519)@5
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr <= UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a) * UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b);
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b <= (others => '0');
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_a <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_a_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_b <= reg_prod_uid198_rrx_uid34_fpSinCosXTest_b_0_0_to_prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_1_q;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1 <= STD_LOGIC_VECTOR(prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_pr);
END IF;
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_s1;
END IF;
END IF;
END PROCESS;
--prod_uid198_rrx_uid34_fpSinCosXTest_align_0(BITSHIFT,522)@8
prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int <= prod_uid198_rrx_uid34_fpSinCosXTest_a0_b0_q;
prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q_int(53 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0(ADD,525)@8
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a <= STD_LOGIC_VECTOR("0000000000000000000000000000" & prod_uid198_rrx_uid34_fpSinCosXTest_align_0_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b <= STD_LOGIC_VECTOR("0" & prod_uid198_rrx_uid34_fpSinCosXTest_align_1_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_a) + UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_b));
END IF;
END PROCESS;
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_o(81 downto 0);
--prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0(ADD,526)@9
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a <= STD_LOGIC_VECTOR("000000000000000000000000000" & prod_uid198_rrx_uid34_fpSinCosXTest_result_add_0_0_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b <= STD_LOGIC_VECTOR("0" & prod_uid198_rrx_uid34_fpSinCosXTest_align_2_q);
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_a) + UNSIGNED(prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_b));
prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_o(108 downto 0);
--multFracBits_uid199_rrx_uid34_fpSinCosXTest(BITSELECT,198)@9
multFracBits_uid199_rrx_uid34_fpSinCosXTest_in <= prod_uid198_rrx_uid34_fpSinCosXTest_result_add_1_0_q(77 downto 0);
multFracBits_uid199_rrx_uid34_fpSinCosXTest_b <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_in(77 downto 0);
--multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest(BITSELECT,199)@9
multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b;
multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b <= multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_in(77 downto 46);
--reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1(REG,544)@9
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= "00000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,433)@10
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a(DELAY,1178)@10
ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xout => ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5(REG,555)@12
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q <= ld_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_a_q;
END IF;
END IF;
END PROCESS;
--zs_uid250_lzcZSin_uid66_fpSinCosXTest(CONSTANT,249)
zs_uid250_lzcZSin_uid66_fpSinCosXTest_q <= "0000000000000000";
--mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest(CONSTANT,434)
mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "11111111111111111111111111111111";
--vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,436)@10
vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q, mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_multFracBitsTop_uid200_rrx_uid34_fpSinCosXTest_0_to_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= mO_uid435_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,438)@10
rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_in(31 downto 16);
--reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1(REG,546)@10
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q <= rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,439)@11
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4(REG,554)@11
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q <= vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e(DELAY,1081)@12
ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--cstAllZWE_uid8_fpSinCosXTest(CONSTANT,7)
cstAllZWE_uid8_fpSinCosXTest_q <= "00000000";
--vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,440)@10
vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid437_zCount_uid201_rrx_uid34_fpSinCosXTest_q(15 downto 0);
vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_in(15 downto 0);
--reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,548)@10
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "0000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,442)@11
vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q, reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid439_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid441_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,444)@11
rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_in(15 downto 8);
--vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,445)@11
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i <= "1" when vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xin => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d(DELAY,1080)@12
ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xout => ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest(CONSTANT,212)
leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q <= "0000";
--vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,446)@11
vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid443_zCount_uid201_rrx_uid34_fpSinCosXTest_q(7 downto 0);
vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,550)@11
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,549)@11
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,448)@12
vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q, reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid445_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid447_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,450)@12
rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_in(7 downto 4);
--vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,451)@12
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,553)@12
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest(CONSTANT,226)
leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q <= "00";
--vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,452)@12
vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid449_zCount_uid201_rrx_uid34_fpSinCosXTest_q(3 downto 0);
vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_in(3 downto 0);
--vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,454)@12
vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b, vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= rVStage_uid451_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
WHEN "1" => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= vStage_uid453_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,456)@12
rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_in(3 downto 2);
--vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,457)@12
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i <= "1" when vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q, xin => vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,458)@12
vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid455_zCount_uid201_rrx_uid34_fpSinCosXTest_q(1 downto 0);
vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_in(1 downto 0);
--reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3(REG,552)@12
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q <= vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2(REG,551)@12
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q <= rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest(MUX,460)@13
vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s <= vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest: PROCESS (vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s, en, reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q, reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_rVStage_uid457_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vStage_uid459_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest(BITSELECT,462)@13
rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in <= vStagei_uid461_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_in(1 downto 1);
--vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest(LOGICAL,463)@13
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a <= rVStage_uid463_zCount_uid201_rrx_uid34_fpSinCosXTest_b;
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b <= GND_q;
vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= "1" when vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_a = vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_b else "0";
--r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest(BITJOIN,464)@13
r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q <= reg_vCount_uid434_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_5_q & ld_reg_vCount_uid440_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_4_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_e_q & ld_vCount_uid446_zCount_uid201_rrx_uid34_fpSinCosXTest_q_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_d_q & reg_vCount_uid452_zCount_uid201_rrx_uid34_fpSinCosXTest_0_to_r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_2_q & vCount_uid458_zCount_uid201_rrx_uid34_fpSinCosXTest_q & vCount_uid464_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
--cstBiasM1_uid23_fpSinCosXTest(CONSTANT,22)
cstBiasM1_uid23_fpSinCosXTest_q <= "01111110";
--expCompOutExt_uid204_rrx_uid34_fpSinCosXTest(SUB,203)@13
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("000" & r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q);
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_b));
expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q <= expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_o(8 downto 0);
--expCompOut_uid205_rrx_uid34_fpSinCosXTest(BITSELECT,204)@13
expCompOut_uid205_rrx_uid34_fpSinCosXTest_in <= expCompOutExt_uid204_rrx_uid34_fpSinCosXTest_q(7 downto 0);
expCompOut_uid205_rrx_uid34_fpSinCosXTest_b <= expCompOut_uid205_rrx_uid34_fpSinCosXTest_in(7 downto 0);
--reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2(REG,564)@13
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q <= expCompOut_uid205_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--xBranch_uid191_rrx_uid34_fpSinCosXTest(COMPARE,190)@0
xBranch_uid191_rrx_uid34_fpSinCosXTest_cin <= GND_q;
xBranch_uid191_rrx_uid34_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid24_fpSinCosXTest_q) & '0';
xBranch_uid191_rrx_uid34_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & expX_uid186_rrx_uid34_fpSinCosXTest_b) & xBranch_uid191_rrx_uid34_fpSinCosXTest_cin(0);
xBranch_uid191_rrx_uid34_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xBranch_uid191_rrx_uid34_fpSinCosXTest_a) - UNSIGNED(xBranch_uid191_rrx_uid34_fpSinCosXTest_b));
xBranch_uid191_rrx_uid34_fpSinCosXTest_n(0) <= not xBranch_uid191_rrx_uid34_fpSinCosXTest_o(10);
--reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1(REG,563)@0
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q <= xBranch_uid191_rrx_uid34_fpSinCosXTest_n;
END IF;
END IF;
END PROCESS;
--ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b(DELAY,829)@1
ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 13 )
PORT MAP ( xin => reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q, xout => ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalExp_uid209_rrx_uid34_fpSinCosXTest(MUX,208)@14
finalExp_uid209_rrx_uid34_fpSinCosXTest_s <= ld_reg_xBranch_uid191_rrx_uid34_fpSinCosXTest_2_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_1_q_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_b_q;
finalExp_uid209_rrx_uid34_fpSinCosXTest: PROCESS (finalExp_uid209_rrx_uid34_fpSinCosXTest_s, en, reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q, ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q)
BEGIN
CASE finalExp_uid209_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= reg_expCompOut_uid205_rrx_uid34_fpSinCosXTest_0_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_2_q;
WHEN "1" => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= ld_expX_uid186_rrx_uid34_fpSinCosXTest_b_to_finalExp_uid209_rrx_uid34_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => finalExp_uid209_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b(DELAY,833)@14
ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => finalExp_uid209_rrx_uid34_fpSinCosXTest_q, xout => ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1409)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_a or ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top(CONSTANT,1279)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q <= "01000";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp(LOGICAL,1280)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_mem_top_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q <= "1" when ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_a = ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_b else "0";
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg(REG,1281)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1410)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1411)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1399)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => fracX_uid187_rrx_uid34_fpSinCosXTest_b, xout => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt(COUNTER,1275)
-- every=1, low=0, high=8, step=1, init=1
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i = 7 THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i - 8;
ELSE
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg(REG,1276)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux(MUX,1277)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s, ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q, ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1400)
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 4,
numwords_a => 9,
width_b => 23,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(22 downto 0);
--ZerosGB_uid206_rrx_uid34_fpSinCosXTest(CONSTANT,205)
ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q <= "000000000000000000000000000000";
--fracXRExt_uid207_rrx_uid34_fpSinCosXTest(BITJOIN,206)@15
fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q <= ld_fracX_uid187_rrx_uid34_fpSinCosXTest_b_to_fracXRExt_uid207_rrx_uid34_fpSinCosXTest_b_replace_mem_q & ZerosGB_uid206_rrx_uid34_fpSinCosXTest_q;
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1499)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1500)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1501)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,474)@9
X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(29 downto 0);
X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_in(29 downto 0);
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1491)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 30, depth => 1 )
PORT MAP ( xin => X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1492)
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 1,
numwords_a => 2,
width_b => 30,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(29 downto 0);
--leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest(CONSTANT,473)
leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= "000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,475)@13
leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X29dto0_uid475_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & leftShiftStage0Idx3Pad48_uid474_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1488)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1489)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1490)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,471)@9
X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(45 downto 0);
X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_in(45 downto 0);
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1480)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 46, depth => 1 )
PORT MAP ( xin => X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1481)
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 46,
widthad_a => 1,
numwords_a => 2,
width_b => 46,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(45 downto 0);
--leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,472)@13
leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X45dto0_uid472_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor(LOGICAL,1477)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q <= not (ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_a or ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_b);
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena(REG,1478)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_nor_q = "1") THEN
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd(LOGICAL,1479)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_sticky_ena_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b <= en;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_a and ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_b;
--X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,468)@9
X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= multFracBits_uid199_rrx_uid34_fpSinCosXTest_b(61 downto 0);
X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_in(61 downto 0);
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg(DELAY,1469)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 62, depth => 1 )
PORT MAP ( xin => X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem(DUALMEM,1470)
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_inputreg_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 62,
widthad_a => 1,
numwords_a => 2,
width_b => 62,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_ia
);
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_iq(61 downto 0);
--leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,469)@13
leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_X61dto0_uid469_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_b_replace_mem_q & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor(LOGICAL,1510)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q <= not (ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_a or ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_b);
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena(REG,1511)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_nor_q = "1") THEN
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd(LOGICAL,1512)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_sticky_ena_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b <= en;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_a and ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_b;
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg(DELAY,1502)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 78, depth => 1 )
PORT MAP ( xin => multFracBits_uid199_rrx_uid34_fpSinCosXTest_b, xout => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem(DUALMEM,1503)
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_inputreg_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 78,
widthad_a => 1,
numwords_a => 2,
width_b => 78,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_ia
);
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_iq(77 downto 0);
--leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,476)@13
leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q;
leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_in(5 downto 4);
--leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,477)@13
leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= leftShiftStageSel5Dto4_uid477_normMult_uid202_rrx_uid34_fpSinCosXTest_b;
leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_multFracBits_uid199_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx1_uid470_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx2_uid473_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage0Idx3_uid476_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,485)@13
LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(65 downto 0);
LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_in(65 downto 0);
--leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest(CONSTANT,218)
leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q <= "000000000000";
--leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,486)@13
leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage065dto0_uid486_normMult_uid202_rrx_uid34_fpSinCosXTest_b & leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5(REG,560)@13
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,482)@13
LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(69 downto 0);
LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_in(69 downto 0);
--leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,483)@13
leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage069dto0_uid483_normMult_uid202_rrx_uid34_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4(REG,559)@13
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,479)@13
LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q(73 downto 0);
LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_in(73 downto 0);
--leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,480)@13
leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= LeftShiftStage073dto0_uid480_normMult_uid202_rrx_uid34_fpSinCosXTest_b & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3(REG,558)@13
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2(REG,557)@13
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,487)@13
leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q(3 downto 0);
leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1(REG,556)@13
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,488)@14
leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= reg_leftShiftStageSel3Dto2_uid488_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q;
leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage0_uid478_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid481_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid484_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid487_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,496)@14
LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(74 downto 0);
LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_in(74 downto 0);
--ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1112)@14
ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 75, depth => 1 )
PORT MAP ( xin => LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest(CONSTANT,229)
leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q <= "000";
--leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,497)@15
leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage174dto0_uid497_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,493)@14
LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(75 downto 0);
LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_in(75 downto 0);
--ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1110)@14
ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 76, depth => 1 )
PORT MAP ( xin => LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,494)@15
leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage175dto0_uid494_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,490)@14
LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q(76 downto 0);
LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_in(76 downto 0);
--ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b(DELAY,1108)@14
ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 77, depth => 1 )
PORT MAP ( xin => LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest(BITJOIN,491)@15
leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= ld_LeftShiftStage176dto0_uid491_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_b_q & GND_q;
--reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2(REG,562)@14
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q <= leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest(BITSELECT,498)@13
leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in <= r_uid465_zCount_uid201_rrx_uid34_fpSinCosXTest_q(1 downto 0);
leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b <= leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a(DELAY,1184)@13
ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b, xout => ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1(REG,561)@14
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q <= ld_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest(MUX,499)@15
leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s <= reg_leftShiftStageSel1Dto0_uid499_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_1_q;
leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest: PROCESS (leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s, en, reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q, leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= reg_leftShiftStage1_uid489_normMult_uid202_rrx_uid34_fpSinCosXTest_0_to_leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx1_uid492_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx2_uid495_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= leftShiftStage2Idx3_uid498_normMult_uid202_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fracCompOut_uid203_rrx_uid34_fpSinCosXTest(BITSELECT,202)@15
fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in <= leftShiftStage2_uid500_normMult_uid202_rrx_uid34_fpSinCosXTest_q(76 downto 0);
fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b <= fracCompOut_uid203_rrx_uid34_fpSinCosXTest_in(76 downto 24);
--ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b(DELAY,826)@0
ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 15 )
PORT MAP ( xin => xBranch_uid191_rrx_uid34_fpSinCosXTest_n, xout => ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--finalFrac_uid208_rrx_uid34_fpSinCosXTest(MUX,207)@15
finalFrac_uid208_rrx_uid34_fpSinCosXTest_s <= ld_xBranch_uid191_rrx_uid34_fpSinCosXTest_n_to_finalFrac_uid208_rrx_uid34_fpSinCosXTest_b_q;
finalFrac_uid208_rrx_uid34_fpSinCosXTest: PROCESS (finalFrac_uid208_rrx_uid34_fpSinCosXTest_s, en, fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b, fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q)
BEGIN
CASE finalFrac_uid208_rrx_uid34_fpSinCosXTest_s IS
WHEN "0" => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= fracCompOut_uid203_rrx_uid34_fpSinCosXTest_b;
WHEN "1" => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= fracXRExt_uid207_rrx_uid34_fpSinCosXTest_q;
WHEN OTHERS => finalFrac_uid208_rrx_uid34_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--RRangeRed_uid210_rrx_uid34_fpSinCosXTest(BITJOIN,209)@15
RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q <= GND_q & ld_finalExp_uid209_rrx_uid34_fpSinCosXTest_q_to_RRangeRed_uid210_rrx_uid34_fpSinCosXTest_b_q & finalFrac_uid208_rrx_uid34_fpSinCosXTest_q;
--expXRR_uid38_fpSinCosXTest(BITSELECT,37)@15
expXRR_uid38_fpSinCosXTest_in <= RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q(60 downto 0);
expXRR_uid38_fpSinCosXTest_b <= expXRR_uid38_fpSinCosXTest_in(60 downto 53);
--reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1(REG,565)@15
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q <= expXRR_uid38_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--cstBiasMwShiftM2_uid26_fpSinCosXTest(CONSTANT,25)
cstBiasMwShiftM2_uid26_fpSinCosXTest_q <= "01110000";
--cosXIsOneXRR_uid42_fpSinCosXTest(COMPARE,41)@16
cosXIsOneXRR_uid42_fpSinCosXTest_cin <= GND_q;
cosXIsOneXRR_uid42_fpSinCosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid26_fpSinCosXTest_q) & '0';
cosXIsOneXRR_uid42_fpSinCosXTest_b <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q) & cosXIsOneXRR_uid42_fpSinCosXTest_cin(0);
cosXIsOneXRR_uid42_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(cosXIsOneXRR_uid42_fpSinCosXTest_a) - SIGNED(cosXIsOneXRR_uid42_fpSinCosXTest_b));
cosXIsOneXRR_uid42_fpSinCosXTest_n(0) <= not cosXIsOneXRR_uid42_fpSinCosXTest_o(11);
--exp_uid9_fpSinCosXTest(BITSELECT,8)@0
exp_uid9_fpSinCosXTest_in <= a(30 downto 0);
exp_uid9_fpSinCosXTest_b <= exp_uid9_fpSinCosXTest_in(30 downto 23);
--sinXIsX_uid40_fpSinCosXTest(COMPARE,39)@0
sinXIsX_uid40_fpSinCosXTest_cin <= GND_q;
sinXIsX_uid40_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid24_fpSinCosXTest_q) & '0';
sinXIsX_uid40_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & exp_uid9_fpSinCosXTest_b) & sinXIsX_uid40_fpSinCosXTest_cin(0);
sinXIsX_uid40_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(sinXIsX_uid40_fpSinCosXTest_a) - UNSIGNED(sinXIsX_uid40_fpSinCosXTest_b));
sinXIsX_uid40_fpSinCosXTest_n(0) <= not sinXIsX_uid40_fpSinCosXTest_o(10);
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a(DELAY,789)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--cosXONe_uid148_fpSinCosXTest(LOGICAL,147)@16
cosXONe_uid148_fpSinCosXTest_a <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_cosXONe_uid148_fpSinCosXTest_a_q;
cosXONe_uid148_fpSinCosXTest_b <= cosXIsOneXRR_uid42_fpSinCosXTest_n;
cosXONe_uid148_fpSinCosXTest_q <= cosXONe_uid148_fpSinCosXTest_a or cosXONe_uid148_fpSinCosXTest_b;
--ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a(DELAY,791)@16
ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 4 )
PORT MAP ( xin => cosXONe_uid148_fpSinCosXTest_q, xout => ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--InvCosXONe_uid149_fpSinCosXTest(LOGICAL,148)@20
InvCosXONe_uid149_fpSinCosXTest_a <= ld_cosXONe_uid148_fpSinCosXTest_q_to_InvCosXONe_uid149_fpSinCosXTest_a_q;
InvCosXONe_uid149_fpSinCosXTest_q <= not InvCosXONe_uid149_fpSinCosXTest_a;
--cstZwShiftP1_uid27_fpSinCosXTest(CONSTANT,26)
cstZwShiftP1_uid27_fpSinCosXTest_q <= "00000000000000";
--fracXRR_uid39_fpSinCosXTest(BITSELECT,38)@15
fracXRR_uid39_fpSinCosXTest_in <= RRangeRed_uid210_rrx_uid34_fpSinCosXTest_q(52 downto 0);
fracXRR_uid39_fpSinCosXTest_b <= fracXRR_uid39_fpSinCosXTest_in(52 downto 0);
--ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a(DELAY,668)@15
ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 53, depth => 1 )
PORT MAP ( xin => fracXRR_uid39_fpSinCosXTest_b, xout => ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--oFracXRR_uid43_uid43_fpSinCosXTest(BITJOIN,42)@16
oFracXRR_uid43_uid43_fpSinCosXTest_q <= VCC_q & ld_fracXRR_uid39_fpSinCosXTest_b_to_oFracXRR_uid43_uid43_fpSinCosXTest_a_q;
--extendedFracX_uid47_fpSinCosXTest(BITJOIN,46)@16
extendedFracX_uid47_fpSinCosXTest_q <= cstZwShiftP1_uid27_fpSinCosXTest_q & oFracXRR_uid43_uid43_fpSinCosXTest_q;
--X55dto0_uid220_fxpX_uid48_fpSinCosXTest(BITSELECT,219)@16
X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(55 downto 0);
X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b <= X55dto0_uid220_fxpX_uid48_fpSinCosXTest_in(55 downto 0);
--leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest(BITJOIN,220)@16
leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q <= X55dto0_uid220_fxpX_uid48_fpSinCosXTest_b & leftShiftStage0Idx3Pad12_uid219_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5(REG,571)@16
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q <= leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--X59dto0_uid217_fxpX_uid48_fpSinCosXTest(BITSELECT,216)@16
X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(59 downto 0);
X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b <= X59dto0_uid217_fxpX_uid48_fpSinCosXTest_in(59 downto 0);
--leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest(BITJOIN,217)@16
leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q <= X59dto0_uid217_fxpX_uid48_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4(REG,570)@16
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q <= leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--X63dto0_uid214_fxpX_uid48_fpSinCosXTest(BITSELECT,213)@16
X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in <= extendedFracX_uid47_fpSinCosXTest_q(63 downto 0);
X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b <= X63dto0_uid214_fxpX_uid48_fpSinCosXTest_in(63 downto 0);
--leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest(BITJOIN,214)@16
leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q <= X63dto0_uid214_fxpX_uid48_fpSinCosXTest_b & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3(REG,569)@16
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q <= leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2(REG,568)@16
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q <= extendedFracX_uid47_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--fxpXShiftValExt_uid45_fpSinCosXTest(SUB,44)@16
fxpXShiftValExt_uid45_fpSinCosXTest_a <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q);
fxpXShiftValExt_uid45_fpSinCosXTest_b <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid26_fpSinCosXTest_q);
fxpXShiftValExt_uid45_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(fxpXShiftValExt_uid45_fpSinCosXTest_a) - SIGNED(fxpXShiftValExt_uid45_fpSinCosXTest_b));
fxpXShiftValExt_uid45_fpSinCosXTest_q <= fxpXShiftValExt_uid45_fpSinCosXTest_o(9 downto 0);
--fxpXShiftVal_uid46_fpSinCosXTest(BITSELECT,45)@16
fxpXShiftVal_uid46_fpSinCosXTest_in <= fxpXShiftValExt_uid45_fpSinCosXTest_q(3 downto 0);
fxpXShiftVal_uid46_fpSinCosXTest_b <= fxpXShiftVal_uid46_fpSinCosXTest_in(3 downto 0);
--leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest(BITSELECT,221)@16
leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in <= fxpXShiftVal_uid46_fpSinCosXTest_b;
leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b <= leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_in(3 downto 2);
--reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1(REG,567)@16
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q <= leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest(MUX,222)@17
leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s <= reg_leftShiftStageSel3Dto2_uid222_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_1_q;
leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest: PROCESS (leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s, en, reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q, reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q, reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q, reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_extendedFracX_uid47_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx1_uid215_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx2_uid218_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0Idx3_uid221_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest(BITSELECT,230)@17
LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(64 downto 0);
LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_in(64 downto 0);
--ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b(DELAY,851)@17
ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest(BITJOIN,231)@18
leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage064dto0_uid231_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_b_q & leftShiftStage1Idx3Pad3_uid230_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest(BITSELECT,227)@17
LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(65 downto 0);
LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_in(65 downto 0);
--ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b(DELAY,849)@17
ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 66, depth => 1 )
PORT MAP ( xin => LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest(BITJOIN,228)@18
leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage065dto0_uid228_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest(BITSELECT,224)@17
LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q(66 downto 0);
LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b <= LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_in(66 downto 0);
--ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b(DELAY,847)@17
ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 67, depth => 1 )
PORT MAP ( xin => LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b, xout => ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest(BITJOIN,225)@18
leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q <= ld_LeftShiftStage066dto0_uid225_fxpX_uid48_fpSinCosXTest_b_to_leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_b_q & GND_q;
--reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2(REG,573)@17
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q <= leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest(BITSELECT,232)@16
leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in <= fxpXShiftVal_uid46_fpSinCosXTest_b(1 downto 0);
leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b <= leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_in(1 downto 0);
--ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a(DELAY,1195)@16
ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b, xout => ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1(REG,572)@17
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q <= ld_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_b_to_reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest(MUX,233)@18
leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s <= reg_leftShiftStageSel1Dto0_uid233_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_1_q;
leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest: PROCESS (leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s, en, reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q, leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q, leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q, leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= reg_leftShiftStage0_uid223_fxpX_uid48_fpSinCosXTest_0_to_leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx1_uid226_fxpX_uid48_fpSinCosXTest_q;
WHEN "10" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx2_uid229_fxpX_uid48_fpSinCosXTest_q;
WHEN "11" => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= leftShiftStage1Idx3_uid232_fxpX_uid48_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--y_uid50_fpSinCosXTest(BITSELECT,49)@18
y_uid50_fpSinCosXTest_in <= leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q(66 downto 0);
y_uid50_fpSinCosXTest_b <= y_uid50_fpSinCosXTest_in(66 downto 1);
--ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b(DELAY,680)@18
ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 66, depth => 2 )
PORT MAP ( xin => y_uid50_fpSinCosXTest_b, xout => ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1(REG,575)@18
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q <= "000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q <= y_uid50_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--pad_one_uid55_fpSinCosXTest(BITJOIN,54)@18
pad_one_uid55_fpSinCosXTest_q <= VCC_q & STD_LOGIC_VECTOR((65 downto 1 => GND_q(0)) & GND_q);
--reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0(REG,574)@18
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q <= pad_one_uid55_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--oneMinusY_uid55_fpSinCosXTest(SUB,55)@19
oneMinusY_uid55_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_one_uid55_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_0_q);
oneMinusY_uid55_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q);
oneMinusY_uid55_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid55_fpSinCosXTest_a) - UNSIGNED(oneMinusY_uid55_fpSinCosXTest_b));
oneMinusY_uid55_fpSinCosXTest_q <= oneMinusY_uid55_fpSinCosXTest_o(67 downto 0);
--reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0(REG,576)@19
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q <= oneMinusY_uid55_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--cmpYToOneMinusY_uid57_fpSinCosXTest(COMPARE,56)@20
cmpYToOneMinusY_uid57_fpSinCosXTest_cin <= GND_q;
cmpYToOneMinusY_uid57_fpSinCosXTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid55_fpSinCosXTest_0_to_cmpYToOneMinusY_uid57_fpSinCosXTest_0_q) & '0';
cmpYToOneMinusY_uid57_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q) & cmpYToOneMinusY_uid57_fpSinCosXTest_cin(0);
cmpYToOneMinusY_uid57_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid57_fpSinCosXTest_a) - UNSIGNED(cmpYToOneMinusY_uid57_fpSinCosXTest_b));
cmpYToOneMinusY_uid57_fpSinCosXTest_c(0) <= cmpYToOneMinusY_uid57_fpSinCosXTest_o(70);
--InvCmpYToOneMinusY_uid61_fpSinCosXTest(LOGICAL,60)@20
InvCmpYToOneMinusY_uid61_fpSinCosXTest_a <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
InvCmpYToOneMinusY_uid61_fpSinCosXTest_q <= not InvCmpYToOneMinusY_uid61_fpSinCosXTest_a;
--intXParity_uid49_fpSinCosXTest(BITSELECT,48)@18
intXParity_uid49_fpSinCosXTest_in <= leftShiftStage1_uid234_fxpX_uid48_fpSinCosXTest_q;
intXParity_uid49_fpSinCosXTest_b <= intXParity_uid49_fpSinCosXTest_in(67 downto 67);
--ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b(DELAY,794)@18
ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => intXParity_uid49_fpSinCosXTest_b, xout => ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--yIsZero_uid51_fpSinCosXTest(LOGICAL,50)@19
yIsZero_uid51_fpSinCosXTest_a <= reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q;
yIsZero_uid51_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000000000000000000000000000000000" & GND_q);
yIsZero_uid51_fpSinCosXTest_q <= "1" when yIsZero_uid51_fpSinCosXTest_a = yIsZero_uid51_fpSinCosXTest_b else "0";
--ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a(DELAY,792)@19
ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => yIsZero_uid51_fpSinCosXTest_q, xout => ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvYIsZero_uid151_fpSinCosXTest(LOGICAL,150)@20
InvYIsZero_uid151_fpSinCosXTest_a <= ld_yIsZero_uid51_fpSinCosXTest_q_to_InvYIsZero_uid151_fpSinCosXTest_a_q;
InvYIsZero_uid151_fpSinCosXTest_q <= not InvYIsZero_uid151_fpSinCosXTest_a;
--signRCond2_uid152_fpSinCosXTest(LOGICAL,151)@20
signRCond2_uid152_fpSinCosXTest_a <= InvYIsZero_uid151_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_b <= ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q;
signRCond2_uid152_fpSinCosXTest_c <= InvCmpYToOneMinusY_uid61_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_d <= InvCosXONe_uid149_fpSinCosXTest_q;
signRCond2_uid152_fpSinCosXTest_q_i <= signRCond2_uid152_fpSinCosXTest_a and signRCond2_uid152_fpSinCosXTest_b and signRCond2_uid152_fpSinCosXTest_c and signRCond2_uid152_fpSinCosXTest_d;
signRCond2_uid152_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRCond2_uid152_fpSinCosXTest_q, xin => signRCond2_uid152_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--InvIntXParity_uid155_fpSinCosXTest(LOGICAL,154)@20
InvIntXParity_uid155_fpSinCosXTest_a <= ld_intXParity_uid49_fpSinCosXTest_b_to_signRCond2_uid152_fpSinCosXTest_b_q;
InvIntXParity_uid155_fpSinCosXTest_q <= not InvIntXParity_uid155_fpSinCosXTest_a;
--signRCond1_uid157_fpSinCosXTest(LOGICAL,156)@20
signRCond1_uid157_fpSinCosXTest_a <= InvYIsZero_uid151_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_b <= InvIntXParity_uid155_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_c <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
signRCond1_uid157_fpSinCosXTest_d <= InvCosXONe_uid149_fpSinCosXTest_q;
signRCond1_uid157_fpSinCosXTest_q_i <= signRCond1_uid157_fpSinCosXTest_a and signRCond1_uid157_fpSinCosXTest_b and signRCond1_uid157_fpSinCosXTest_c and signRCond1_uid157_fpSinCosXTest_d;
signRCond1_uid157_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRCond1_uid157_fpSinCosXTest_q, xin => signRCond1_uid157_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--signRCos_uid158_fpSinCosXTest(LOGICAL,157)@21
signRCos_uid158_fpSinCosXTest_a <= signRCond1_uid157_fpSinCosXTest_q;
signRCos_uid158_fpSinCosXTest_b <= signRCond2_uid152_fpSinCosXTest_q;
signRCos_uid158_fpSinCosXTest_q <= signRCos_uid158_fpSinCosXTest_a or signRCos_uid158_fpSinCosXTest_b;
--cstAllZWF_uid7_fpSinCosXTest(CONSTANT,6)
cstAllZWF_uid7_fpSinCosXTest_q <= "00000000000000000000000";
--frac_uid13_fpSinCosXTest(BITSELECT,12)@0
frac_uid13_fpSinCosXTest_in <= a(22 downto 0);
frac_uid13_fpSinCosXTest_b <= frac_uid13_fpSinCosXTest_in(22 downto 0);
--fracXIsZero_uid14_fpSinCosXTest(LOGICAL,13)@0
fracXIsZero_uid14_fpSinCosXTest_a <= frac_uid13_fpSinCosXTest_b;
fracXIsZero_uid14_fpSinCosXTest_b <= cstAllZWF_uid7_fpSinCosXTest_q;
fracXIsZero_uid14_fpSinCosXTest_q <= "1" when fracXIsZero_uid14_fpSinCosXTest_a = fracXIsZero_uid14_fpSinCosXTest_b else "0";
--cstAllOWE_uid6_fpSinCosXTest(CONSTANT,5)
cstAllOWE_uid6_fpSinCosXTest_q <= "11111111";
--expXIsMax_uid12_fpSinCosXTest(LOGICAL,11)@0
expXIsMax_uid12_fpSinCosXTest_a <= exp_uid9_fpSinCosXTest_b;
expXIsMax_uid12_fpSinCosXTest_b <= cstAllOWE_uid6_fpSinCosXTest_q;
expXIsMax_uid12_fpSinCosXTest_q <= "1" when expXIsMax_uid12_fpSinCosXTest_a = expXIsMax_uid12_fpSinCosXTest_b else "0";
--exc_I_uid15_fpSinCosXTest(LOGICAL,14)@0
exc_I_uid15_fpSinCosXTest_a <= expXIsMax_uid12_fpSinCosXTest_q;
exc_I_uid15_fpSinCosXTest_b <= fracXIsZero_uid14_fpSinCosXTest_q;
exc_I_uid15_fpSinCosXTest_q <= exc_I_uid15_fpSinCosXTest_a and exc_I_uid15_fpSinCosXTest_b;
--ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a(DELAY,762)@0
ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 20 )
PORT MAP ( xin => exc_I_uid15_fpSinCosXTest_q, xout => ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_I_uid131_fpSinCosXTest(LOGICAL,130)@20
InvExc_I_uid131_fpSinCosXTest_a <= ld_exc_I_uid15_fpSinCosXTest_q_to_InvExc_I_uid131_fpSinCosXTest_a_q;
InvExc_I_uid131_fpSinCosXTest_q <= not InvExc_I_uid131_fpSinCosXTest_a;
--reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2(REG,649)@20
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q <= InvExc_I_uid131_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--InvFracXIsZero_uid16_fpSinCosXTest(LOGICAL,15)@0
InvFracXIsZero_uid16_fpSinCosXTest_a <= fracXIsZero_uid14_fpSinCosXTest_q;
InvFracXIsZero_uid16_fpSinCosXTest_q <= not InvFracXIsZero_uid16_fpSinCosXTest_a;
--exc_N_uid17_fpSinCosXTest(LOGICAL,16)@0
exc_N_uid17_fpSinCosXTest_a <= expXIsMax_uid12_fpSinCosXTest_q;
exc_N_uid17_fpSinCosXTest_b <= InvFracXIsZero_uid16_fpSinCosXTest_q;
exc_N_uid17_fpSinCosXTest_q <= exc_N_uid17_fpSinCosXTest_a and exc_N_uid17_fpSinCosXTest_b;
--ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a(DELAY,763)@0
ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 20 )
PORT MAP ( xin => exc_N_uid17_fpSinCosXTest_q, xout => ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvExc_N_uid132_fpSinCosXTest(LOGICAL,131)@20
InvExc_N_uid132_fpSinCosXTest_a <= ld_exc_N_uid17_fpSinCosXTest_q_to_InvExc_N_uid132_fpSinCosXTest_a_q;
InvExc_N_uid132_fpSinCosXTest_q <= not InvExc_N_uid132_fpSinCosXTest_a;
--reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1(REG,648)@20
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q <= InvExc_N_uid132_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--signRCosFull_uid161_fpSinCosXTest(LOGICAL,160)@21
signRCosFull_uid161_fpSinCosXTest_a <= reg_InvExc_N_uid132_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_1_q;
signRCosFull_uid161_fpSinCosXTest_b <= reg_InvExc_I_uid131_fpSinCosXTest_0_to_signRCosFull_uid161_fpSinCosXTest_2_q;
signRCosFull_uid161_fpSinCosXTest_c <= signRCos_uid158_fpSinCosXTest_q;
signRCosFull_uid161_fpSinCosXTest_q <= signRCosFull_uid161_fpSinCosXTest_a and signRCosFull_uid161_fpSinCosXTest_b and signRCosFull_uid161_fpSinCosXTest_c;
--ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c(DELAY,809)@21
ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRCosFull_uid161_fpSinCosXTest_q, xout => ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--cstBias_uid22_fpSinCosXTest(CONSTANT,21)
cstBias_uid22_fpSinCosXTest_q <= "01111111";
--ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a(DELAY,681)@19
ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 68, depth => 1 )
PORT MAP ( xin => oneMinusY_uid55_fpSinCosXTest_q, xout => ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--zSinOMyBottom_uid58_fpSinCosXTest(BITSELECT,57)@20
zSinOMyBottom_uid58_fpSinCosXTest_in <= ld_oneMinusY_uid55_fpSinCosXTest_q_to_zSinOMyBottom_uid58_fpSinCosXTest_a_q(64 downto 0);
zSinOMyBottom_uid58_fpSinCosXTest_b <= zSinOMyBottom_uid58_fpSinCosXTest_in(64 downto 0);
--reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3(REG,579)@20
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q <= zSinOMyBottom_uid58_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--zSinYBottom_uid59_fpSinCosXTest(BITSELECT,58)@20
zSinYBottom_uid59_fpSinCosXTest_in <= ld_y_uid50_fpSinCosXTest_b_to_cmpYToOneMinusY_uid57_fpSinCosXTest_b_q(64 downto 0);
zSinYBottom_uid59_fpSinCosXTest_b <= zSinYBottom_uid59_fpSinCosXTest_in(64 downto 0);
--reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2(REG,578)@20
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q <= zSinYBottom_uid59_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1(REG,614)@20
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q <= InvCmpYToOneMinusY_uid61_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--zCos_uid64_fpSinCosXTest(MUX,63)@21
zCos_uid64_fpSinCosXTest_s <= reg_InvCmpYToOneMinusY_uid61_fpSinCosXTest_0_to_zCos_uid64_fpSinCosXTest_1_q;
zCos_uid64_fpSinCosXTest: PROCESS (zCos_uid64_fpSinCosXTest_s, en, reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q, reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q)
BEGIN
CASE zCos_uid64_fpSinCosXTest_s IS
WHEN "0" => zCos_uid64_fpSinCosXTest_q <= reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q;
WHEN "1" => zCos_uid64_fpSinCosXTest_q <= reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q;
WHEN OTHERS => zCos_uid64_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--addr_uid83_fpSinCosXTest(BITSELECT,82)@21
addr_uid83_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q;
addr_uid83_fpSinCosXTest_b <= addr_uid83_fpSinCosXTest_in(64 downto 57);
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0(REG,630)@21
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q <= addr_uid83_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid404_tableGencosPiZ_lutmem(DUALMEM,532)@22
memoryC2_uid404_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC2_uid404_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC2_uid404_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC2_uid404_tableGencosPiZ_lutmem_0_q;
memoryC2_uid404_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC2_uid404_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid404_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid404_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid404_tableGencosPiZ_lutmem_iq,
address_a => memoryC2_uid404_tableGencosPiZ_lutmem_aa,
data_a => memoryC2_uid404_tableGencosPiZ_lutmem_ia
);
memoryC2_uid404_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC2_uid404_tableGencosPiZ_lutmem_q <= memoryC2_uid404_tableGencosPiZ_lutmem_iq(12 downto 0);
--reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1(REG,632)@24
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q <= memoryC2_uid404_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPcosPiZ_uid87_fpSinCosXTest(BITSELECT,86)@21
zPcosPiZ_uid87_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(56 downto 0);
zPcosPiZ_uid87_fpSinCosXTest_b <= zPcosPiZ_uid87_fpSinCosXTest_in(56 downto 42);
--yT1_uid419_polyEvalcosPiZ(BITSELECT,418)@21
yT1_uid419_polyEvalcosPiZ_in <= zPcosPiZ_uid87_fpSinCosXTest_b;
yT1_uid419_polyEvalcosPiZ_b <= yT1_uid419_polyEvalcosPiZ_in(14 downto 2);
--reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0(REG,631)@21
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q <= yT1_uid419_polyEvalcosPiZ_b;
END IF;
END IF;
END PROCESS;
--ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg(DELAY,1513)
ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q, xout => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a(DELAY,1125)@22
ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_inputreg_q, xout => ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q, ena => en(0), clk => clk, aclr => areset );
--prodXY_uid508_pT1_uid420_polyEvalcosPiZ(MULT,507)@25
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a),14)) * SIGNED(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b);
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a <= (others => '0');
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b <= (others => '0');
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a <= ld_reg_yT1_uid419_polyEvalcosPiZ_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_0_q_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_a_q;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_b <= reg_memoryC2_uid404_tableGencosPiZ_lutmem_0_to_prodXY_uid508_pT1_uid420_polyEvalcosPiZ_1_q;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid508_pT1_uid420_polyEvalcosPiZ_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid508_pT1_uid420_polyEvalcosPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q <= prodXY_uid508_pT1_uid420_polyEvalcosPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ(BITSELECT,508)@28
prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in <= prodXY_uid508_pT1_uid420_polyEvalcosPiZ_q;
prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_in(25 downto 12);
--highBBits_uid422_polyEvalcosPiZ(BITSELECT,421)@28
highBBits_uid422_polyEvalcosPiZ_in <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b;
highBBits_uid422_polyEvalcosPiZ_b <= highBBits_uid422_polyEvalcosPiZ_in(13 downto 1);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a(DELAY,1256)@21
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addr_uid83_fpSinCosXTest_b, xout => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0(REG,633)@24
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid402_tableGencosPiZ_lutmem(DUALMEM,531)@25
memoryC1_uid402_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC1_uid402_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC1_uid402_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC1_uid402_tableGencosPiZ_lutmem_0_q;
memoryC1_uid402_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC1_uid402_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid402_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid402_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid402_tableGencosPiZ_lutmem_iq,
address_a => memoryC1_uid402_tableGencosPiZ_lutmem_aa,
data_a => memoryC1_uid402_tableGencosPiZ_lutmem_ia
);
memoryC1_uid402_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC1_uid402_tableGencosPiZ_lutmem_q <= memoryC1_uid402_tableGencosPiZ_lutmem_iq(20 downto 0);
--reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0(REG,634)@27
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q <= memoryC1_uid402_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid423_polyEvalcosPiZ(ADD,422)@28
sumAHighB_uid423_polyEvalcosPiZ_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q(20)) & reg_memoryC1_uid402_tableGencosPiZ_lutmem_0_to_sumAHighB_uid423_polyEvalcosPiZ_0_q);
sumAHighB_uid423_polyEvalcosPiZ_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid422_polyEvalcosPiZ_b(12)) & highBBits_uid422_polyEvalcosPiZ_b);
sumAHighB_uid423_polyEvalcosPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid423_polyEvalcosPiZ_a) + SIGNED(sumAHighB_uid423_polyEvalcosPiZ_b));
sumAHighB_uid423_polyEvalcosPiZ_q <= sumAHighB_uid423_polyEvalcosPiZ_o(21 downto 0);
--lowRangeB_uid421_polyEvalcosPiZ(BITSELECT,420)@28
lowRangeB_uid421_polyEvalcosPiZ_in <= prodXYTruncFR_uid509_pT1_uid420_polyEvalcosPiZ_b(0 downto 0);
lowRangeB_uid421_polyEvalcosPiZ_b <= lowRangeB_uid421_polyEvalcosPiZ_in(0 downto 0);
--s1_uid421_uid424_polyEvalcosPiZ(BITJOIN,423)@28
s1_uid421_uid424_polyEvalcosPiZ_q <= sumAHighB_uid423_polyEvalcosPiZ_q & lowRangeB_uid421_polyEvalcosPiZ_b;
--reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1(REG,636)@28
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q <= s1_uid421_uid424_polyEvalcosPiZ_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor(LOGICAL,1524)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q <= not (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_a or ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_b);
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top(CONSTANT,1520)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q <= "0100";
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp(LOGICAL,1521)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_mem_top_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q <= "1" when ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_a = ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_b else "0";
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg(REG,1522)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena(REG,1525)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_nor_q = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd(LOGICAL,1526)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_sticky_ena_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b <= en;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_a and ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_b;
--reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0(REG,635)@21
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q <= zPcosPiZ_uid87_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg(DELAY,1514)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q, xout => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt(COUNTER,1516)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i = 3 THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_eq = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i - 4;
ELSE
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_i,3));
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg(REG,1517)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux(MUX,1518)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s <= en;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux: PROCESS (ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s, ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q, ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_s IS
WHEN "0" => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
WHEN "1" => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem(DUALMEM,1515)
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_inputreg_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq,
address_a => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_aa,
data_a => ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_ia
);
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_reset0 <= areset;
ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_iq(14 downto 0);
--prodXY_uid511_pT2_uid426_polyEvalcosPiZ(MULT,510)@29
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a),16)) * SIGNED(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b);
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a <= (others => '0');
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b <= (others => '0');
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_mem_q;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_b <= reg_s1_uid421_uid424_polyEvalcosPiZ_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_1_q;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid511_pT2_uid426_polyEvalcosPiZ_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid511_pT2_uid426_polyEvalcosPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q <= prodXY_uid511_pT2_uid426_polyEvalcosPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ(BITSELECT,511)@32
prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in <= prodXY_uid511_pT2_uid426_polyEvalcosPiZ_q;
prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_in(37 downto 14);
--highBBits_uid428_polyEvalcosPiZ(BITSELECT,427)@32
highBBits_uid428_polyEvalcosPiZ_in <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b;
highBBits_uid428_polyEvalcosPiZ_b <= highBBits_uid428_polyEvalcosPiZ_in(23 downto 2);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor(LOGICAL,1577)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q <= not (ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_a or ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_b);
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena(REG,1578)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_nor_q = "1") THEN
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd(LOGICAL,1579)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b <= en;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_a and ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_b;
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg(DELAY,1567)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addr_uid83_fpSinCosXTest_b, xout => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem(DUALMEM,1568)
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_inputreg_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq,
address_a => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_aa,
data_a => ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_ia
);
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0(REG,637)@28
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q <= ld_addr_uid83_fpSinCosXTest_b_to_reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid400_tableGencosPiZ_lutmem(DUALMEM,530)@29
memoryC0_uid400_tableGencosPiZ_lutmem_ia <= (others => '0');
memoryC0_uid400_tableGencosPiZ_lutmem_aa <= (others => '0');
memoryC0_uid400_tableGencosPiZ_lutmem_ab <= reg_addr_uid83_fpSinCosXTest_0_to_memoryC0_uid400_tableGencosPiZ_lutmem_0_q;
memoryC0_uid400_tableGencosPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC0_uid400_tableGencosPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid400_tableGencosPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid400_tableGencosPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid400_tableGencosPiZ_lutmem_iq,
address_a => memoryC0_uid400_tableGencosPiZ_lutmem_aa,
data_a => memoryC0_uid400_tableGencosPiZ_lutmem_ia
);
memoryC0_uid400_tableGencosPiZ_lutmem_reset0 <= areset;
memoryC0_uid400_tableGencosPiZ_lutmem_q <= memoryC0_uid400_tableGencosPiZ_lutmem_iq(29 downto 0);
--reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0(REG,638)@31
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q <= memoryC0_uid400_tableGencosPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid429_polyEvalcosPiZ(ADD,428)@32
sumAHighB_uid429_polyEvalcosPiZ_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q(29)) & reg_memoryC0_uid400_tableGencosPiZ_lutmem_0_to_sumAHighB_uid429_polyEvalcosPiZ_0_q);
sumAHighB_uid429_polyEvalcosPiZ_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid428_polyEvalcosPiZ_b(21)) & highBBits_uid428_polyEvalcosPiZ_b);
sumAHighB_uid429_polyEvalcosPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid429_polyEvalcosPiZ_a) + SIGNED(sumAHighB_uid429_polyEvalcosPiZ_b));
sumAHighB_uid429_polyEvalcosPiZ_q <= sumAHighB_uid429_polyEvalcosPiZ_o(30 downto 0);
--lowRangeB_uid427_polyEvalcosPiZ(BITSELECT,426)@32
lowRangeB_uid427_polyEvalcosPiZ_in <= prodXYTruncFR_uid512_pT2_uid426_polyEvalcosPiZ_b(1 downto 0);
lowRangeB_uid427_polyEvalcosPiZ_b <= lowRangeB_uid427_polyEvalcosPiZ_in(1 downto 0);
--s2_uid427_uid430_polyEvalcosPiZ(BITJOIN,429)@32
s2_uid427_uid430_polyEvalcosPiZ_q <= sumAHighB_uid429_polyEvalcosPiZ_q & lowRangeB_uid427_polyEvalcosPiZ_b;
--polyEvalSigcosPiZ_uid89_fpSinCosXTest(BITSELECT,88)@32
polyEvalSigcosPiZ_uid89_fpSinCosXTest_in <= s2_uid427_uid430_polyEvalcosPiZ_q(30 downto 0);
polyEvalSigcosPiZ_uid89_fpSinCosXTest_b <= polyEvalSigcosPiZ_uid89_fpSinCosXTest_in(30 downto 5);
--reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1(REG,640)@32
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q <= polyEvalSigcosPiZ_uid89_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor(LOGICAL,1590)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q <= not (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_a or ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_b);
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top(CONSTANT,1586)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q <= "010";
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp(LOGICAL,1587)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_mem_top_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q <= "1" when ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_a = ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_b else "0";
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg(REG,1588)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena(REG,1591)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_nor_q = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd(LOGICAL,1592)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_sticky_ena_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b <= en;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_a and ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_b;
--LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest(BITSELECT,388)@27
LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q(63 downto 0);
LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_in(63 downto 0);
--leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest(BITJOIN,389)@27
leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage263dto0_uid389_alignedZCos_uid70_fpSinCosXTest_b & GND_q;
--cstZmwFRRPwSM1_uid52_fpSinCosXTest(CONSTANT,51)
cstZmwFRRPwSM1_uid52_fpSinCosXTest_q <= "00000000000000000000000000000000000000000000000000000000000000000";
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor(LOGICAL,1455)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q <= not (ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_a or ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_b);
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena(REG,1456)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_nor_q = "1") THEN
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd(LOGICAL,1457)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b <= en;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_a and ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_b;
--X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest(BITSELECT,359)@21
X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(32 downto 0);
X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b <= X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_in(32 downto 0);
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg(DELAY,1447)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem(DUALMEM,1448)
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_inputreg_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 1,
numwords_a => 2,
width_b => 33,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_ia
);
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_iq(32 downto 0);
--leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest(BITJOIN,360)@25
leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q <= ld_X32dto0_uid360_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor(LOGICAL,1466)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q <= not (ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_a or ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_b);
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena(REG,1467)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_nor_q = "1") THEN
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd(LOGICAL,1468)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_sticky_ena_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b <= en;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_a and ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_b;
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg(DELAY,1458)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => zCos_uid64_fpSinCosXTest_q, xout => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem(DUALMEM,1459)
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_inputreg_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 65,
widthad_a => 1,
numwords_a => 2,
width_b => 65,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_ia
);
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_iq(64 downto 0);
--zs_uid236_lzcZSin_uid66_fpSinCosXTest(CONSTANT,235)
zs_uid236_lzcZSin_uid66_fpSinCosXTest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--rVStage_uid316_lzcZCos_uid69_fpSinCosXTest(BITSELECT,315)@21
rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q;
rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_in(64 downto 1);
--vCount_uid317_lzcZCos_uid69_fpSinCosXTest(LOGICAL,316)@21
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid236_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid317_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid317_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid317_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g(DELAY,985)@22
ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid319_lzcZCos_uid69_fpSinCosXTest(BITSELECT,318)@21
vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in <= zCos_uid64_fpSinCosXTest_q(0 downto 0);
vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid319_lzcZCos_uid69_fpSinCosXTest_in(0 downto 0);
--ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b(DELAY,943)@21
ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--mO_uid239_lzcZSin_uid66_fpSinCosXTest(CONSTANT,238)
mO_uid239_lzcZSin_uid66_fpSinCosXTest_q <= "111111111111111111111111111111111111111111111111111111111111111";
--cStage_uid320_lzcZCos_uid69_fpSinCosXTest(BITJOIN,319)@22
cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q <= ld_vStage_uid319_lzcZCos_uid69_fpSinCosXTest_b_to_cStage_uid320_lzcZCos_uid69_fpSinCosXTest_b_q & mO_uid239_lzcZSin_uid66_fpSinCosXTest_q;
--ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c(DELAY,945)@21
ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid322_lzcZCos_uid69_fpSinCosXTest(MUX,321)@22
vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid322_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s, en, ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q, cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= ld_rVStage_uid316_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= cStage_uid320_lzcZCos_uid69_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid324_lzcZCos_uid69_fpSinCosXTest(BITSELECT,323)@22
rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_in(63 downto 32);
--vCount_uid325_lzcZCos_uid69_fpSinCosXTest(LOGICAL,324)@22
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid325_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid325_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid325_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f(DELAY,984)@23
ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid326_lzcZCos_uid69_fpSinCosXTest(BITSELECT,325)@22
vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid322_lzcZCos_uid69_fpSinCosXTest_q(31 downto 0);
vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid326_lzcZCos_uid69_fpSinCosXTest_in(31 downto 0);
--ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d(DELAY,952)@22
ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c(DELAY,951)@22
ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b, xout => ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid328_lzcZCos_uid69_fpSinCosXTest(MUX,327)@23
vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid328_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s, en, ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q, ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q)
BEGIN
CASE vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= ld_rVStage_uid324_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= ld_vStage_uid326_lzcZCos_uid69_fpSinCosXTest_b_to_vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_d_q;
WHEN OTHERS => vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid330_lzcZCos_uid69_fpSinCosXTest(BITSELECT,329)@23
rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_in(31 downto 16);
--vCount_uid331_lzcZCos_uid69_fpSinCosXTest(LOGICAL,330)@23
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid331_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid331_lzcZCos_uid69_fpSinCosXTest_b else "0";
--reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4(REG,622)@23
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q <= vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e(DELAY,983)@24
ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid332_lzcZCos_uid69_fpSinCosXTest(BITSELECT,331)@23
vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid328_lzcZCos_uid69_fpSinCosXTest_q(15 downto 0);
vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid332_lzcZCos_uid69_fpSinCosXTest_in(15 downto 0);
--vStagei_uid334_lzcZCos_uid69_fpSinCosXTest(MUX,333)@23
vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid331_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid334_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s, en, rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b, vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= rVStage_uid330_lzcZCos_uid69_fpSinCosXTest_b;
WHEN "1" => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= vStage_uid332_lzcZCos_uid69_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid336_lzcZCos_uid69_fpSinCosXTest(BITSELECT,335)@23
rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_in(15 downto 8);
--reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1(REG,617)@23
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q <= rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid337_lzcZCos_uid69_fpSinCosXTest(LOGICAL,336)@24
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a <= reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q;
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid337_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid337_lzcZCos_uid69_fpSinCosXTest_b else "0";
--ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d(DELAY,982)@24
ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q, xout => ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid338_lzcZCos_uid69_fpSinCosXTest(BITSELECT,337)@23
vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid334_lzcZCos_uid69_fpSinCosXTest_q(7 downto 0);
vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid338_lzcZCos_uid69_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3(REG,619)@23
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q <= vStage_uid338_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid340_lzcZCos_uid69_fpSinCosXTest(MUX,339)@24
vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid340_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s, en, reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q, reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= reg_rVStage_uid336_lzcZCos_uid69_fpSinCosXTest_0_to_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= reg_vStage_uid338_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid342_lzcZCos_uid69_fpSinCosXTest(BITSELECT,341)@24
rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_in(7 downto 4);
--vCount_uid343_lzcZCos_uid69_fpSinCosXTest(LOGICAL,342)@24
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i <= "1" when vCount_uid343_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid343_lzcZCos_uid69_fpSinCosXTest_b else "0";
vCount_uid343_lzcZCos_uid69_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q, xin => vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid344_lzcZCos_uid69_fpSinCosXTest(BITSELECT,343)@24
vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid340_lzcZCos_uid69_fpSinCosXTest_q(3 downto 0);
vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid344_lzcZCos_uid69_fpSinCosXTest_in(3 downto 0);
--reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3(REG,621)@24
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q <= vStage_uid344_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2(REG,620)@24
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q <= rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid346_lzcZCos_uid69_fpSinCosXTest(MUX,345)@25
vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid346_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s, en, reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q, reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= reg_rVStage_uid342_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= reg_vStage_uid344_lzcZCos_uid69_fpSinCosXTest_0_to_vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid348_lzcZCos_uid69_fpSinCosXTest(BITSELECT,347)@25
rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_in(3 downto 2);
--vCount_uid349_lzcZCos_uid69_fpSinCosXTest(LOGICAL,348)@25
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid349_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid349_lzcZCos_uid69_fpSinCosXTest_b else "0";
--vStage_uid350_lzcZCos_uid69_fpSinCosXTest(BITSELECT,349)@25
vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid346_lzcZCos_uid69_fpSinCosXTest_q(1 downto 0);
vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b <= vStage_uid350_lzcZCos_uid69_fpSinCosXTest_in(1 downto 0);
--vStagei_uid352_lzcZCos_uid69_fpSinCosXTest(MUX,351)@25
vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s <= vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q;
vStagei_uid352_lzcZCos_uid69_fpSinCosXTest: PROCESS (vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s, en, rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b, vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= rVStage_uid348_lzcZCos_uid69_fpSinCosXTest_b;
WHEN "1" => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= vStage_uid350_lzcZCos_uid69_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid354_lzcZCos_uid69_fpSinCosXTest(BITSELECT,353)@25
rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in <= vStagei_uid352_lzcZCos_uid69_fpSinCosXTest_q;
rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b <= rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_in(1 downto 1);
--vCount_uid355_lzcZCos_uid69_fpSinCosXTest(LOGICAL,354)@25
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a <= rVStage_uid354_lzcZCos_uid69_fpSinCosXTest_b;
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b <= GND_q;
vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q <= "1" when vCount_uid355_lzcZCos_uid69_fpSinCosXTest_a = vCount_uid355_lzcZCos_uid69_fpSinCosXTest_b else "0";
--r_uid356_lzcZCos_uid69_fpSinCosXTest(BITJOIN,355)@25
r_uid356_lzcZCos_uid69_fpSinCosXTest_q <= ld_vCount_uid317_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_g_q & ld_vCount_uid325_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_f_q & ld_reg_vCount_uid331_lzcZCos_uid69_fpSinCosXTest_0_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_4_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_e_q & ld_vCount_uid337_lzcZCos_uid69_fpSinCosXTest_q_to_r_uid356_lzcZCos_uid69_fpSinCosXTest_d_q & vCount_uid343_lzcZCos_uid69_fpSinCosXTest_q & vCount_uid349_lzcZCos_uid69_fpSinCosXTest_q & vCount_uid355_lzcZCos_uid69_fpSinCosXTest_q;
--leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest(BITSELECT,363)@25
leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q;
leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_in(6 downto 5);
--leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest(MUX,364)@25
leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s <= leftShiftStageSel6Dto5_uid364_alignedZCos_uid70_fpSinCosXTest_b;
leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s, en, ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= ld_zCos_uid64_fpSinCosXTest_q_to_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage0Idx1_uid361_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest(BITSELECT,372)@25
LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(40 downto 0);
LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_in(40 downto 0);
--leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest(CONSTANT,292)
leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q <= "000000000000000000000000";
--leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest(BITJOIN,373)@25
leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage040dto0_uid373_alignedZCos_uid70_fpSinCosXTest_b & leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5(REG,627)@25
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest(BITSELECT,369)@25
LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(48 downto 0);
LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_in(48 downto 0);
--leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest(BITJOIN,370)@25
leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage048dto0_uid370_alignedZCos_uid70_fpSinCosXTest_b & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4(REG,626)@25
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest(BITSELECT,366)@25
LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q(56 downto 0);
LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_in(56 downto 0);
--leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest(BITJOIN,367)@25
leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q <= LeftShiftStage056dto0_uid367_alignedZCos_uid70_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3(REG,625)@25
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2(REG,624)@25
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q <= leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest(BITSELECT,374)@25
leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1(REG,623)@25
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q <= leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest(MUX,375)@26
leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s <= reg_leftShiftStageSel4Dto3_uid375_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_1_q;
leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s, en, reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage0_uid365_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid368_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid371_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid374_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest(BITSELECT,383)@26
LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(58 downto 0);
LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1009)@26
ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest(CONSTANT,303)
leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q <= "000000";
--leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest(BITJOIN,384)@27
leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage158dto0_uid384_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q;
--LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest(BITSELECT,380)@26
LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(60 downto 0);
LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1007)@26
ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest(BITJOIN,381)@27
leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage160dto0_uid381_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest(BITSELECT,377)@26
LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q(62 downto 0);
LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b <= LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_in(62 downto 0);
--ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1005)@26
ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest(BITJOIN,378)@27
leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q <= ld_LeftShiftStage162dto0_uid378_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2(REG,629)@26
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q <= leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest(BITSELECT,385)@25
leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1(REG,628)@25
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q <= leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1011)@26
ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q, xout => ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest(MUX,386)@27
leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s <= ld_reg_leftShiftStageSel2Dto1_uid386_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_1_q_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_b_q;
leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s, en, reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= reg_leftShiftStage1_uid376_alignedZCos_uid70_fpSinCosXTest_0_to_leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx1_uid379_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx2_uid382_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2Idx3_uid385_alignedZCos_uid70_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest(BITSELECT,390)@25
leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b <= leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b(DELAY,1019)@25
ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b, xout => ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest(MUX,391)@27
leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s <= ld_leftShiftStageSel0Dto0_uid391_alignedZCos_uid70_fpSinCosXTest_b_to_leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_b_q;
leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest: PROCESS (leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s, en, leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q, leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_s IS
WHEN "0" => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage2_uid387_alignedZCos_uid70_fpSinCosXTest_q;
WHEN "1" => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= leftShiftStage3Idx1_uid390_alignedZCos_uid70_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pCos_uid77_fpSinCosXTest(BITSELECT,76)@27
pCos_uid77_fpSinCosXTest_in <= leftShiftStage3_uid392_alignedZCos_uid70_fpSinCosXTest_q;
pCos_uid77_fpSinCosXTest_b <= pCos_uid77_fpSinCosXTest_in(64 downto 39);
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg(DELAY,1580)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => pCos_uid77_fpSinCosXTest_b, xout => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt(COUNTER,1582)
-- every=1, low=0, high=2, step=1, init=1
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i = 1 THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '1';
ELSE
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_eq = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i - 2;
ELSE
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_i,2));
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg(REG,1583)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux(MUX,1584)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s <= en;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux: PROCESS (ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s, ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q, ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q)
BEGIN
CASE ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_s IS
WHEN "0" => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q;
WHEN "1" => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem(DUALMEM,1581)
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_inputreg_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdreg_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_rdmux_q;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 2,
numwords_a => 3,
width_b => 26,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq,
address_a => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_aa,
data_a => ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_ia
);
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_reset0 <= areset;
ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_iq(25 downto 0);
--reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0(REG,639)@32
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q <= ld_pCos_uid77_fpSinCosXTest_b_to_reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--mulCos_uid105_fpSinCosXTest(MULT,104)@33
mulCos_uid105_fpSinCosXTest_pr <= UNSIGNED(mulCos_uid105_fpSinCosXTest_a) * UNSIGNED(mulCos_uid105_fpSinCosXTest_b);
mulCos_uid105_fpSinCosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulCos_uid105_fpSinCosXTest_a <= (others => '0');
mulCos_uid105_fpSinCosXTest_b <= (others => '0');
mulCos_uid105_fpSinCosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulCos_uid105_fpSinCosXTest_a <= reg_pCos_uid77_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_0_q;
mulCos_uid105_fpSinCosXTest_b <= reg_polyEvalSigcosPiZ_uid89_fpSinCosXTest_0_to_mulCos_uid105_fpSinCosXTest_1_q;
mulCos_uid105_fpSinCosXTest_s1 <= STD_LOGIC_VECTOR(mulCos_uid105_fpSinCosXTest_pr);
END IF;
END IF;
END PROCESS;
mulCos_uid105_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulCos_uid105_fpSinCosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulCos_uid105_fpSinCosXTest_q <= mulCos_uid105_fpSinCosXTest_s1;
END IF;
END IF;
END PROCESS;
--normBitCos_uid106_fpSinCosXTest(BITSELECT,105)@36
normBitCos_uid106_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q;
normBitCos_uid106_fpSinCosXTest_b <= normBitCos_uid106_fpSinCosXTest_in(51 downto 51);
--cosRndOp_uid112_uid113_fpSinCosXTest(BITJOIN,112)@36
cosRndOp_uid112_uid113_fpSinCosXTest_q <= normBitCos_uid106_fpSinCosXTest_b & cstAllZWF_uid7_fpSinCosXTest_q & VCC_q;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor(LOGICAL,1296)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q <= not (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_a or ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_b);
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top(CONSTANT,1292)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q <= "0110";
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp(LOGICAL,1293)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_mem_top_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q <= "1" when ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_a = ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_b else "0";
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg(REG,1294)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena(REG,1297)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_nor_q = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd(LOGICAL,1298)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_sticky_ena_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b <= en;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_a and ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_b;
--reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1(REG,641)@25
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q <= r_uid356_lzcZCos_uid69_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg(DELAY,1286)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q, xout => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt(COUNTER,1288)
-- every=1, low=0, high=6, step=1, init=1
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i = 5 THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i - 6;
ELSE
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_i,3));
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg(REG,1289)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux(MUX,1290)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s <= en;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux: PROCESS (ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s, ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q, ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem(DUALMEM,1287)
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_inputreg_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 7,
width_b => 7,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_ia
);
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_iq(6 downto 0);
--expHardCase_uid78_fpSinCosXTest(SUB,77)@35
expHardCase_uid78_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expHardCase_uid78_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_mem_q);
expHardCase_uid78_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid78_fpSinCosXTest_a) - UNSIGNED(expHardCase_uid78_fpSinCosXTest_b));
expHardCase_uid78_fpSinCosXTest_q <= expHardCase_uid78_fpSinCosXTest_o(8 downto 0);
--expPCos_uid79_fpSinCosXTest(BITSELECT,78)@35
expPCos_uid79_fpSinCosXTest_in <= expHardCase_uid78_fpSinCosXTest_q(7 downto 0);
expPCos_uid79_fpSinCosXTest_b <= expPCos_uid79_fpSinCosXTest_in(7 downto 0);
--reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1(REG,642)@35
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q <= expPCos_uid79_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRCosPreRndHigh_uid108_fpSinCosXTest(BITSELECT,107)@36
fracRCosPreRndHigh_uid108_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q(50 downto 0);
fracRCosPreRndHigh_uid108_fpSinCosXTest_b <= fracRCosPreRndHigh_uid108_fpSinCosXTest_in(50 downto 27);
--fracRCosPreRndLow_uid109_fpSinCosXTest(BITSELECT,108)@36
fracRCosPreRndLow_uid109_fpSinCosXTest_in <= mulCos_uid105_fpSinCosXTest_q(49 downto 0);
fracRCosPreRndLow_uid109_fpSinCosXTest_b <= fracRCosPreRndLow_uid109_fpSinCosXTest_in(49 downto 26);
--fracRCosPreRnd_uid110_fpSinCosXTest(MUX,109)@36
fracRCosPreRnd_uid110_fpSinCosXTest_s <= normBitCos_uid106_fpSinCosXTest_b;
fracRCosPreRnd_uid110_fpSinCosXTest: PROCESS (fracRCosPreRnd_uid110_fpSinCosXTest_s, en, fracRCosPreRndLow_uid109_fpSinCosXTest_b, fracRCosPreRndHigh_uid108_fpSinCosXTest_b)
BEGIN
CASE fracRCosPreRnd_uid110_fpSinCosXTest_s IS
WHEN "0" => fracRCosPreRnd_uid110_fpSinCosXTest_q <= fracRCosPreRndLow_uid109_fpSinCosXTest_b;
WHEN "1" => fracRCosPreRnd_uid110_fpSinCosXTest_q <= fracRCosPreRndHigh_uid108_fpSinCosXTest_b;
WHEN OTHERS => fracRCosPreRnd_uid110_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracRCosPreRnd_uid111_uid111_fpSinCosXTest(BITJOIN,110)@36
expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q <= reg_expPCos_uid79_fpSinCosXTest_0_to_expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_1_q & fracRCosPreRnd_uid110_fpSinCosXTest_q;
--expFracRCos_uid114_fpSinCosXTest(ADD,113)@36
expFracRCos_uid114_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expFracRCosPreRnd_uid111_uid111_fpSinCosXTest_q);
expFracRCos_uid114_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00000000" & cosRndOp_uid112_uid113_fpSinCosXTest_q);
expFracRCos_uid114_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRCos_uid114_fpSinCosXTest_a) + UNSIGNED(expFracRCos_uid114_fpSinCosXTest_b));
expFracRCos_uid114_fpSinCosXTest_q <= expFracRCos_uid114_fpSinCosXTest_o(32 downto 0);
--expRCompSin_uid116_fpSinCosXTest(BITSELECT,115)@36
expRCompSin_uid116_fpSinCosXTest_in <= expFracRCos_uid114_fpSinCosXTest_q(31 downto 0);
expRCompSin_uid116_fpSinCosXTest_b <= expRCompSin_uid116_fpSinCosXTest_in(31 downto 24);
--reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2(REG,646)@36
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q <= expRCompSin_uid116_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor(LOGICAL,1385)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q <= not (ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_a or ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_b);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top(CONSTANT,1305)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q <= "01101";
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp(LOGICAL,1306)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_mem_top_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q <= "1" when ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_a = ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_b else "0";
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg(REG,1307)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena(REG,1386)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_nor_q = "1") THEN
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd(LOGICAL,1387)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_sticky_ena_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b <= en;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_a and ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_b;
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a(DELAY,745)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c(DELAY,783)@16
ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => cosXIsOneXRR_uid42_fpSinCosXTest_n, xout => ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--InvCosXIsOneXRR_uid136_fpSinCosXTest(LOGICAL,135)@16
InvCosXIsOneXRR_uid136_fpSinCosXTest_a <= cosXIsOneXRR_uid42_fpSinCosXTest_n;
InvCosXIsOneXRR_uid136_fpSinCosXTest_q <= not InvCosXIsOneXRR_uid136_fpSinCosXTest_a;
--ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c(DELAY,773)@16
ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => InvCosXIsOneXRR_uid136_fpSinCosXTest_q, xout => ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a(DELAY,755)@0
ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => sinXIsX_uid40_fpSinCosXTest_n, xout => ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsX_uid127_fpSinCosXTest(LOGICAL,126)@18
InvSinXIsX_uid127_fpSinCosXTest_a <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_InvSinXIsX_uid127_fpSinCosXTest_a_q;
InvSinXIsX_uid127_fpSinCosXTest_q <= not InvSinXIsX_uid127_fpSinCosXTest_a;
--ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b(DELAY,772)@18
ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => InvSinXIsX_uid127_fpSinCosXTest_q, xout => ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--half_uid53_fpSinCosXTest(BITJOIN,52)@19
half_uid53_fpSinCosXTest_q <= VCC_q & cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
--yIsHalf_uid54_fpSinCosXTest(LOGICAL,53)@19
yIsHalf_uid54_fpSinCosXTest_a <= reg_y_uid50_fpSinCosXTest_0_to_oneMinusY_uid55_fpSinCosXTest_1_q;
yIsHalf_uid54_fpSinCosXTest_b <= half_uid53_fpSinCosXTest_q;
yIsHalf_uid54_fpSinCosXTest_q <= "1" when yIsHalf_uid54_fpSinCosXTest_a = yIsHalf_uid54_fpSinCosXTest_b else "0";
--yHalfCosXNotOne_uid138_fpSinCosXTest(LOGICAL,137)@19
yHalfCosXNotOne_uid138_fpSinCosXTest_a <= yIsHalf_uid54_fpSinCosXTest_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_b <= ld_InvSinXIsX_uid127_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_b_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_c <= ld_InvCosXIsOneXRR_uid136_fpSinCosXTest_q_to_yHalfCosXNotOne_uid138_fpSinCosXTest_c_q;
yHalfCosXNotOne_uid138_fpSinCosXTest_q <= yHalfCosXNotOne_uid138_fpSinCosXTest_a and yHalfCosXNotOne_uid138_fpSinCosXTest_b and yHalfCosXNotOne_uid138_fpSinCosXTest_c;
--ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b(DELAY,744)@0
ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => exc_I_uid15_fpSinCosXTest_q, xout => ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a(DELAY,743)@0
ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => exc_N_uid17_fpSinCosXTest_q, xout => ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--excRNaN_uid117_fpSinCosXTest(LOGICAL,116)@19
excRNaN_uid117_fpSinCosXTest_a <= ld_exc_N_uid17_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_a_q;
excRNaN_uid117_fpSinCosXTest_b <= ld_exc_I_uid15_fpSinCosXTest_q_to_excRNaN_uid117_fpSinCosXTest_b_q;
excRNaN_uid117_fpSinCosXTest_q <= excRNaN_uid117_fpSinCosXTest_a or excRNaN_uid117_fpSinCosXTest_b;
--join_uid143_fpSinCosXTest(BITJOIN,142)@19
join_uid143_fpSinCosXTest_q <= ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q & yHalfCosXNotOne_uid138_fpSinCosXTest_q & excRNaN_uid117_fpSinCosXTest_q;
--expSelBitsCos_uid144_fpSinCosXTest(BITJOIN,143)@19
expSelBitsCos_uid144_fpSinCosXTest_q <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q & join_uid143_fpSinCosXTest_q;
--reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0(REG,645)@19
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q <= expSelBitsCos_uid144_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--expSelectorCos_uid145_fpSinCosXTest(LOOKUP,144)@20
expSelectorCos_uid145_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expSelectorCos_uid145_fpSinCosXTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_expSelBitsCos_uid144_fpSinCosXTest_0_to_expSelectorCos_uid145_fpSinCosXTest_0_q) IS
WHEN "0000" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "0001" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "0010" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "0011" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "0100" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "0101" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "0110" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "0111" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "1000" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "1001" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "1010" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "1011" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN "1100" => expSelectorCos_uid145_fpSinCosXTest_q <= "01";
WHEN "1101" => expSelectorCos_uid145_fpSinCosXTest_q <= "11";
WHEN "1110" => expSelectorCos_uid145_fpSinCosXTest_q <= "10";
WHEN "1111" => expSelectorCos_uid145_fpSinCosXTest_q <= "00";
WHEN OTHERS =>
expSelectorCos_uid145_fpSinCosXTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg(DELAY,1375)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => expSelectorCos_uid145_fpSinCosXTest_q, xout => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt(COUNTER,1301)
-- every=1, low=0, high=13, step=1, init=1
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i = 12 THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i - 13;
ELSE
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_i,4));
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg(REG,1302)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux(MUX,1303)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s, ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q, ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem(DUALMEM,1376)
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_inputreg_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_ia
);
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_iq(1 downto 0);
--expRPostExcCos_uid147_fpSinCosXTest(MUX,146)@37
expRPostExcCos_uid147_fpSinCosXTest_s <= ld_expSelectorCos_uid145_fpSinCosXTest_q_to_expRPostExcCos_uid147_fpSinCosXTest_b_replace_mem_q;
expRPostExcCos_uid147_fpSinCosXTest: PROCESS (expRPostExcCos_uid147_fpSinCosXTest_s, en, reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q, cstBias_uid22_fpSinCosXTest_q, cstAllZWE_uid8_fpSinCosXTest_q, cstAllOWE_uid6_fpSinCosXTest_q)
BEGIN
CASE expRPostExcCos_uid147_fpSinCosXTest_s IS
WHEN "00" => expRPostExcCos_uid147_fpSinCosXTest_q <= reg_expRCompSin_uid116_fpSinCosXTest_0_to_expRPostExcCos_uid147_fpSinCosXTest_2_q;
WHEN "01" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstBias_uid22_fpSinCosXTest_q;
WHEN "10" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstAllZWE_uid8_fpSinCosXTest_q;
WHEN "11" => expRPostExcCos_uid147_fpSinCosXTest_q <= cstAllOWE_uid6_fpSinCosXTest_q;
WHEN OTHERS => expRPostExcCos_uid147_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--cstNaNwF_uid32_fpSinCosXTest(CONSTANT,31)
cstNaNwF_uid32_fpSinCosXTest_q <= "00000000000000000000001";
--fracRCompCos_uid115_fpSinCosXTest(BITSELECT,114)@36
fracRCompCos_uid115_fpSinCosXTest_in <= expFracRCos_uid114_fpSinCosXTest_q(23 downto 0);
fracRCompCos_uid115_fpSinCosXTest_b <= fracRCompCos_uid115_fpSinCosXTest_in(23 downto 1);
--reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2(REG,644)@36
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q <= fracRCompCos_uid115_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor(LOGICAL,1372)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q <= not (ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_a or ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_b);
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena(REG,1373)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_nor_q = "1") THEN
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd(LOGICAL,1374)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_sticky_ena_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b <= en;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_a and ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_b;
--reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1(REG,613)@19
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q <= excRNaN_uid117_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3(REG,612)@19
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q <= ld_cosXIsOneXRR_uid42_fpSinCosXTest_n_to_join_uid143_fpSinCosXTest_c_q;
END IF;
END IF;
END PROCESS;
--reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2(REG,611)@19
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q <= ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q;
END IF;
END IF;
END PROCESS;
--reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1(REG,610)@19
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q <= yHalfCosXNotOne_uid138_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--rZOrOne_uid140_fpSinCosXTest(LOGICAL,139)@20
rZOrOne_uid140_fpSinCosXTest_a <= reg_yHalfCosXNotOne_uid138_fpSinCosXTest_0_to_rZOrOne_uid140_fpSinCosXTest_1_q;
rZOrOne_uid140_fpSinCosXTest_b <= reg_sinXIsX_uid40_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_2_q;
rZOrOne_uid140_fpSinCosXTest_c <= reg_cosXIsOneXRR_uid42_fpSinCosXTest_2_to_rZOrOne_uid140_fpSinCosXTest_3_q;
rZOrOne_uid140_fpSinCosXTest_q <= rZOrOne_uid140_fpSinCosXTest_a or rZOrOne_uid140_fpSinCosXTest_b or rZOrOne_uid140_fpSinCosXTest_c;
--join_uid141_fpSinCosXTest(BITJOIN,140)@20
join_uid141_fpSinCosXTest_q <= reg_excRNaN_uid117_fpSinCosXTest_0_to_join_uid141_fpSinCosXTest_1_q & rZOrOne_uid140_fpSinCosXTest_q;
--reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1(REG,643)@20
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q <= join_uid141_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg(DELAY,1362)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q, xout => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem(DUALMEM,1363)
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_inputreg_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 4,
numwords_a => 14,
width_b => 2,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_ia
);
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_iq(1 downto 0);
--fracRPostExcCos_uid142_fpSinCosXTest(MUX,141)@37
fracRPostExcCos_uid142_fpSinCosXTest_s <= ld_reg_join_uid141_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_1_q_to_fracRPostExcCos_uid142_fpSinCosXTest_b_replace_mem_q;
fracRPostExcCos_uid142_fpSinCosXTest: PROCESS (fracRPostExcCos_uid142_fpSinCosXTest_s, en, reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q, cstAllZWF_uid7_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q)
BEGIN
CASE fracRPostExcCos_uid142_fpSinCosXTest_s IS
WHEN "00" => fracRPostExcCos_uid142_fpSinCosXTest_q <= reg_fracRCompCos_uid115_fpSinCosXTest_0_to_fracRPostExcCos_uid142_fpSinCosXTest_2_q;
WHEN "01" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstAllZWF_uid7_fpSinCosXTest_q;
WHEN "10" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN "11" => fracRPostExcCos_uid142_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN OTHERS => fracRPostExcCos_uid142_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpCos_uid162_fpSinCosXTest(BITJOIN,161)@37
fpCos_uid162_fpSinCosXTest_q <= ld_signRCosFull_uid161_fpSinCosXTest_q_to_fpCos_uid162_fpSinCosXTest_c_q & expRPostExcCos_uid147_fpSinCosXTest_q & fracRPostExcCos_uid142_fpSinCosXTest_q;
--cstBiasMwShiftM2_uid25_fpSinCosXTest(CONSTANT,24)
cstBiasMwShiftM2_uid25_fpSinCosXTest_q <= "01110001";
--sinXIsXRR_uid41_fpSinCosXTest(COMPARE,40)@16
sinXIsXRR_uid41_fpSinCosXTest_cin <= GND_q;
sinXIsXRR_uid41_fpSinCosXTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid25_fpSinCosXTest_q) & '0';
sinXIsXRR_uid41_fpSinCosXTest_b <= STD_LOGIC_VECTOR((10 downto 8 => reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q(7)) & reg_expXRR_uid38_fpSinCosXTest_0_to_sinXIsXRR_uid41_fpSinCosXTest_1_q) & sinXIsXRR_uid41_fpSinCosXTest_cin(0);
sinXIsXRR_uid41_fpSinCosXTest_o <= STD_LOGIC_VECTOR(SIGNED(sinXIsXRR_uid41_fpSinCosXTest_a) - SIGNED(sinXIsXRR_uid41_fpSinCosXTest_b));
sinXIsXRR_uid41_fpSinCosXTest_n(0) <= not sinXIsXRR_uid41_fpSinCosXTest_o(11);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a(DELAY,756)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--InvSinXIsXRR_uid128_fpSinCosXTest(LOGICAL,127)@18
InvSinXIsXRR_uid128_fpSinCosXTest_a <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_InvSinXIsXRR_uid128_fpSinCosXTest_a_q;
InvSinXIsXRR_uid128_fpSinCosXTest_q <= not InvSinXIsXRR_uid128_fpSinCosXTest_a;
--signComp_uid129_fpSinCosXTest(LOGICAL,128)@18
signComp_uid129_fpSinCosXTest_a <= InvSinXIsXRR_uid128_fpSinCosXTest_q;
signComp_uid129_fpSinCosXTest_b <= InvSinXIsX_uid127_fpSinCosXTest_q;
signComp_uid129_fpSinCosXTest_c <= intXParity_uid49_fpSinCosXTest_b;
signComp_uid129_fpSinCosXTest_q <= signComp_uid129_fpSinCosXTest_a and signComp_uid129_fpSinCosXTest_b and signComp_uid129_fpSinCosXTest_c;
--signX_uid37_fpSinCosXTest(BITSELECT,36)@0
signX_uid37_fpSinCosXTest_in <= a;
signX_uid37_fpSinCosXTest_b <= signX_uid37_fpSinCosXTest_in(31 downto 31);
--ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a(DELAY,760)@0
ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 18 )
PORT MAP ( xin => signX_uid37_fpSinCosXTest_b, xout => ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q, ena => en(0), clk => clk, aclr => areset );
--signR_uid130_fpSinCosXTest(LOGICAL,129)@18
signR_uid130_fpSinCosXTest_a <= ld_signX_uid37_fpSinCosXTest_b_to_signR_uid130_fpSinCosXTest_a_q;
signR_uid130_fpSinCosXTest_b <= signComp_uid129_fpSinCosXTest_q;
signR_uid130_fpSinCosXTest_q <= signR_uid130_fpSinCosXTest_a xor signR_uid130_fpSinCosXTest_b;
--ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c(DELAY,766)@18
ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => signR_uid130_fpSinCosXTest_q, xout => ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--signRSinFull_uid133_fpSinCosXTest(LOGICAL,132)@20
signRSinFull_uid133_fpSinCosXTest_a <= InvExc_N_uid132_fpSinCosXTest_q;
signRSinFull_uid133_fpSinCosXTest_b <= InvExc_I_uid131_fpSinCosXTest_q;
signRSinFull_uid133_fpSinCosXTest_c <= ld_signR_uid130_fpSinCosXTest_q_to_signRSinFull_uid133_fpSinCosXTest_c_q;
signRSinFull_uid133_fpSinCosXTest_q_i <= signRSinFull_uid133_fpSinCosXTest_a and signRSinFull_uid133_fpSinCosXTest_b and signRSinFull_uid133_fpSinCosXTest_c;
signRSinFull_uid133_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => signRSinFull_uid133_fpSinCosXTest_q, xin => signRSinFull_uid133_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c(DELAY,769)@21
ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => signRSinFull_uid133_fpSinCosXTest_q, xout => ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor(LOGICAL,1359)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q <= not (ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_a or ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_b);
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top(CONSTANT,1342)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q <= "0100010";
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp(LOGICAL,1343)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_mem_top_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q <= "1" when ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_a = ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_b else "0";
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg(REG,1344)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena(REG,1360)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_nor_q = "1") THEN
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd(LOGICAL,1361)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_sticky_ena_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b <= en;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_a and ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_b;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg(DELAY,1349)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => exp_uid9_fpSinCosXTest_b, xout => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt(COUNTER,1338)
-- every=1, low=0, high=34, step=1, init=1
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i = 33 THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '1';
ELSE
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq <= '0';
END IF;
IF (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_eq = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i - 34;
ELSE
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_i,6));
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg(REG,1339)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q <= "000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux(MUX,1340)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s <= en;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux: PROCESS (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q)
BEGIN
CASE ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_s IS
WHEN "0" => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
WHEN "1" => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdcnt_q;
WHEN OTHERS => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem(DUALMEM,1350)
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_inputreg_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 35,
width_b => 8,
widthad_b => 6,
numwords_b => 35,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_ia
);
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a(DELAY,1228)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1(REG,605)@35
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor(LOGICAL,1309)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q <= not (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_a or ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_b);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena(REG,1310)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_nor_q = "1") THEN
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd(LOGICAL,1311)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_sticky_ena_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b <= en;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_a and ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_b;
--oFracXRRSmallXRR_uid90_fpSinCosXTest(BITSELECT,89)@16
oFracXRRSmallXRR_uid90_fpSinCosXTest_in <= oFracXRR_uid43_uid43_fpSinCosXTest_q;
oFracXRRSmallXRR_uid90_fpSinCosXTest_b <= oFracXRRSmallXRR_uid90_fpSinCosXTest_in(53 downto 28);
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg(DELAY,1299)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => oFracXRRSmallXRR_uid90_fpSinCosXTest_b, xout => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem(DUALMEM,1300)
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_inputreg_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 4,
numwords_a => 14,
width_b => 26,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_ia
);
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_iq(25 downto 0);
--reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1(REG,577)@20
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q <= cmpYToOneMinusY_uid57_fpSinCosXTest_c;
END IF;
END IF;
END PROCESS;
--zSin_uid60_fpSinCosXTest(MUX,59)@21
zSin_uid60_fpSinCosXTest_s <= reg_cmpYToOneMinusY_uid57_fpSinCosXTest_1_to_zSin_uid60_fpSinCosXTest_1_q;
zSin_uid60_fpSinCosXTest: PROCESS (zSin_uid60_fpSinCosXTest_s, en, reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q, reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q)
BEGIN
CASE zSin_uid60_fpSinCosXTest_s IS
WHEN "0" => zSin_uid60_fpSinCosXTest_q <= reg_zSinYBottom_uid59_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_2_q;
WHEN "1" => zSin_uid60_fpSinCosXTest_q <= reg_zSinOMyBottom_uid58_fpSinCosXTest_0_to_zSin_uid60_fpSinCosXTest_3_q;
WHEN OTHERS => zSin_uid60_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--addr_uid81_fpSinCosXTest(BITSELECT,80)@21
addr_uid81_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q;
addr_uid81_fpSinCosXTest_b <= addr_uid81_fpSinCosXTest_in(64 downto 57);
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0(REG,595)@21
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q <= addr_uid81_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--memoryC2_uid398_tableGensinPiZ_lutmem(DUALMEM,529)@22
memoryC2_uid398_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC2_uid398_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC2_uid398_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC2_uid398_tableGensinPiZ_lutmem_0_q;
memoryC2_uid398_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 13,
widthad_a => 8,
numwords_a => 256,
width_b => 13,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC2_uid398_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid398_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid398_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid398_tableGensinPiZ_lutmem_iq,
address_a => memoryC2_uid398_tableGensinPiZ_lutmem_aa,
data_a => memoryC2_uid398_tableGensinPiZ_lutmem_ia
);
memoryC2_uid398_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC2_uid398_tableGensinPiZ_lutmem_q <= memoryC2_uid398_tableGensinPiZ_lutmem_iq(12 downto 0);
--reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1(REG,597)@24
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q <= memoryC2_uid398_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--zPsinPiZ_uid84_fpSinCosXTest(BITSELECT,83)@21
zPsinPiZ_uid84_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(56 downto 0);
zPsinPiZ_uid84_fpSinCosXTest_b <= zPsinPiZ_uid84_fpSinCosXTest_in(56 downto 42);
--yT1_uid406_polyEvalsinPiZ(BITSELECT,405)@21
yT1_uid406_polyEvalsinPiZ_in <= zPsinPiZ_uid84_fpSinCosXTest_b;
yT1_uid406_polyEvalsinPiZ_b <= yT1_uid406_polyEvalsinPiZ_in(14 downto 2);
--ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg(DELAY,1540)
ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 13, depth => 1 )
PORT MAP ( xin => yT1_uid406_polyEvalsinPiZ_b, xout => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a(DELAY,1219)@21
ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a : dspba_delay
GENERIC MAP ( width => 13, depth => 2 )
PORT MAP ( xin => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_inputreg_q, xout => ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0(REG,596)@24
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q <= "0000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q <= ld_yT1_uid406_polyEvalsinPiZ_b_to_reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_a_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid502_pT1_uid407_polyEvalsinPiZ(MULT,501)@25
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a),14)) * SIGNED(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b);
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a <= (others => '0');
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b <= (others => '0');
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_a <= reg_yT1_uid406_polyEvalsinPiZ_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_0_q;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_b <= reg_memoryC2_uid398_tableGensinPiZ_lutmem_0_to_prodXY_uid502_pT1_uid407_polyEvalsinPiZ_1_q;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid502_pT1_uid407_polyEvalsinPiZ_pr,26));
END IF;
END IF;
END PROCESS;
prodXY_uid502_pT1_uid407_polyEvalsinPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q <= prodXY_uid502_pT1_uid407_polyEvalsinPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ(BITSELECT,502)@28
prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in <= prodXY_uid502_pT1_uid407_polyEvalsinPiZ_q;
prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_in(25 downto 12);
--highBBits_uid409_polyEvalsinPiZ(BITSELECT,408)@28
highBBits_uid409_polyEvalsinPiZ_in <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b;
highBBits_uid409_polyEvalsinPiZ_b <= highBBits_uid409_polyEvalsinPiZ_in(13 downto 1);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a(DELAY,1221)@21
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a : dspba_delay
GENERIC MAP ( width => 8, depth => 3 )
PORT MAP ( xin => addr_uid81_fpSinCosXTest_b, xout => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0(REG,598)@24
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_a_q;
END IF;
END IF;
END PROCESS;
--memoryC1_uid396_tableGensinPiZ_lutmem(DUALMEM,528)@25
memoryC1_uid396_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC1_uid396_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC1_uid396_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC1_uid396_tableGensinPiZ_lutmem_0_q;
memoryC1_uid396_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 8,
numwords_a => 256,
width_b => 21,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC1_uid396_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid396_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid396_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid396_tableGensinPiZ_lutmem_iq,
address_a => memoryC1_uid396_tableGensinPiZ_lutmem_aa,
data_a => memoryC1_uid396_tableGensinPiZ_lutmem_ia
);
memoryC1_uid396_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC1_uid396_tableGensinPiZ_lutmem_q <= memoryC1_uid396_tableGensinPiZ_lutmem_iq(20 downto 0);
--reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0(REG,599)@27
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q <= memoryC1_uid396_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid410_polyEvalsinPiZ(ADD,409)@28
sumAHighB_uid410_polyEvalsinPiZ_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q(20)) & reg_memoryC1_uid396_tableGensinPiZ_lutmem_0_to_sumAHighB_uid410_polyEvalsinPiZ_0_q);
sumAHighB_uid410_polyEvalsinPiZ_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid409_polyEvalsinPiZ_b(12)) & highBBits_uid409_polyEvalsinPiZ_b);
sumAHighB_uid410_polyEvalsinPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid410_polyEvalsinPiZ_a) + SIGNED(sumAHighB_uid410_polyEvalsinPiZ_b));
sumAHighB_uid410_polyEvalsinPiZ_q <= sumAHighB_uid410_polyEvalsinPiZ_o(21 downto 0);
--lowRangeB_uid408_polyEvalsinPiZ(BITSELECT,407)@28
lowRangeB_uid408_polyEvalsinPiZ_in <= prodXYTruncFR_uid503_pT1_uid407_polyEvalsinPiZ_b(0 downto 0);
lowRangeB_uid408_polyEvalsinPiZ_b <= lowRangeB_uid408_polyEvalsinPiZ_in(0 downto 0);
--s1_uid408_uid411_polyEvalsinPiZ(BITJOIN,410)@28
s1_uid408_uid411_polyEvalsinPiZ_q <= sumAHighB_uid410_polyEvalsinPiZ_q & lowRangeB_uid408_polyEvalsinPiZ_b;
--reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1(REG,601)@28
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q <= s1_uid408_uid411_polyEvalsinPiZ_q;
END IF;
END IF;
END PROCESS;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor(LOGICAL,1551)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q <= not (ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_a or ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_b);
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena(REG,1552)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_nor_q = "1") THEN
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd(LOGICAL,1553)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_sticky_ena_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b <= en;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_a and ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_b;
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg(DELAY,1541)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => zPsinPiZ_uid84_fpSinCosXTest_b, xout => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem(DUALMEM,1542)
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_inputreg_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 3,
numwords_a => 5,
width_b => 15,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq,
address_a => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_aa,
data_a => ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_ia
);
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_reset0 <= areset;
ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_iq(14 downto 0);
--reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0(REG,600)@28
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q <= ld_zPsinPiZ_uid84_fpSinCosXTest_b_to_reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid505_pT2_uid413_polyEvalsinPiZ(MULT,504)@29
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr <= signed(resize(UNSIGNED(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a),16)) * SIGNED(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b);
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a <= (others => '0');
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b <= (others => '0');
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_a <= reg_zPsinPiZ_uid84_fpSinCosXTest_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_0_q;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_b <= reg_s1_uid408_uid411_polyEvalsinPiZ_0_to_prodXY_uid505_pT2_uid413_polyEvalsinPiZ_1_q;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid505_pT2_uid413_polyEvalsinPiZ_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid505_pT2_uid413_polyEvalsinPiZ: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q <= prodXY_uid505_pT2_uid413_polyEvalsinPiZ_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ(BITSELECT,505)@32
prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in <= prodXY_uid505_pT2_uid413_polyEvalsinPiZ_q;
prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_in(37 downto 14);
--highBBits_uid415_polyEvalsinPiZ(BITSELECT,414)@32
highBBits_uid415_polyEvalsinPiZ_in <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b;
highBBits_uid415_polyEvalsinPiZ_b <= highBBits_uid415_polyEvalsinPiZ_in(23 downto 2);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor(LOGICAL,1564)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q <= not (ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_a or ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_b);
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena(REG,1565)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_nor_q = "1") THEN
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd(LOGICAL,1566)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_sticky_ena_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b <= en;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_a and ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_b;
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg(DELAY,1554)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => addr_uid81_fpSinCosXTest_b, xout => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem(DUALMEM,1555)
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_inputreg_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdreg_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab <= ld_reg_zPcosPiZ_uid87_fpSinCosXTest_0_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_0_q_to_prodXY_uid511_pT2_uid426_polyEvalcosPiZ_a_replace_rdmux_q;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 5,
width_b => 8,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq,
address_a => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_aa,
data_a => ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_ia
);
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_reset0 <= areset;
ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_iq(7 downto 0);
--reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0(REG,602)@28
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q <= ld_addr_uid81_fpSinCosXTest_b_to_reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--memoryC0_uid394_tableGensinPiZ_lutmem(DUALMEM,527)@29
memoryC0_uid394_tableGensinPiZ_lutmem_ia <= (others => '0');
memoryC0_uid394_tableGensinPiZ_lutmem_aa <= (others => '0');
memoryC0_uid394_tableGensinPiZ_lutmem_ab <= reg_addr_uid81_fpSinCosXTest_0_to_memoryC0_uid394_tableGensinPiZ_lutmem_0_q;
memoryC0_uid394_tableGensinPiZ_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 8,
numwords_a => 256,
width_b => 30,
widthad_b => 8,
numwords_b => 256,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_sincos_s5_memoryC0_uid394_tableGensinPiZ_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid394_tableGensinPiZ_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid394_tableGensinPiZ_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid394_tableGensinPiZ_lutmem_iq,
address_a => memoryC0_uid394_tableGensinPiZ_lutmem_aa,
data_a => memoryC0_uid394_tableGensinPiZ_lutmem_ia
);
memoryC0_uid394_tableGensinPiZ_lutmem_reset0 <= areset;
memoryC0_uid394_tableGensinPiZ_lutmem_q <= memoryC0_uid394_tableGensinPiZ_lutmem_iq(29 downto 0);
--reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0(REG,603)@31
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q <= memoryC0_uid394_tableGensinPiZ_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid416_polyEvalsinPiZ(ADD,415)@32
sumAHighB_uid416_polyEvalsinPiZ_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q(29)) & reg_memoryC0_uid394_tableGensinPiZ_lutmem_0_to_sumAHighB_uid416_polyEvalsinPiZ_0_q);
sumAHighB_uid416_polyEvalsinPiZ_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid415_polyEvalsinPiZ_b(21)) & highBBits_uid415_polyEvalsinPiZ_b);
sumAHighB_uid416_polyEvalsinPiZ_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid416_polyEvalsinPiZ_a) + SIGNED(sumAHighB_uid416_polyEvalsinPiZ_b));
sumAHighB_uid416_polyEvalsinPiZ_q <= sumAHighB_uid416_polyEvalsinPiZ_o(30 downto 0);
--lowRangeB_uid414_polyEvalsinPiZ(BITSELECT,413)@32
lowRangeB_uid414_polyEvalsinPiZ_in <= prodXYTruncFR_uid506_pT2_uid413_polyEvalsinPiZ_b(1 downto 0);
lowRangeB_uid414_polyEvalsinPiZ_b <= lowRangeB_uid414_polyEvalsinPiZ_in(1 downto 0);
--s2_uid414_uid417_polyEvalsinPiZ(BITJOIN,416)@32
s2_uid414_uid417_polyEvalsinPiZ_q <= sumAHighB_uid416_polyEvalsinPiZ_q & lowRangeB_uid414_polyEvalsinPiZ_b;
--polyEvalSigsinPiZ_uid86_fpSinCosXTest(BITSELECT,85)@32
polyEvalSigsinPiZ_uid86_fpSinCosXTest_in <= s2_uid414_uid417_polyEvalsinPiZ_q(30 downto 0);
polyEvalSigsinPiZ_uid86_fpSinCosXTest_b <= polyEvalSigsinPiZ_uid86_fpSinCosXTest_in(30 downto 5);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b(DELAY,708)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 16 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--multSinOp2_uid91_fpSinCosXTest(MUX,90)@32
multSinOp2_uid91_fpSinCosXTest_s <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_multSinOp2_uid91_fpSinCosXTest_b_q;
multSinOp2_uid91_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSinOp2_uid91_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE multSinOp2_uid91_fpSinCosXTest_s IS
WHEN "0" => multSinOp2_uid91_fpSinCosXTest_q <= polyEvalSigsinPiZ_uid86_fpSinCosXTest_b;
WHEN "1" => multSinOp2_uid91_fpSinCosXTest_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => multSinOp2_uid91_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor(LOGICAL,1320)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q <= not (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_a or ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_b);
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena(REG,1321)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_nor_q = "1") THEN
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd(LOGICAL,1322)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_sticky_ena_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b <= en;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_a and ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_b;
--cPi_uid71_fpSinCosXTest(CONSTANT,70)
cPi_uid71_fpSinCosXTest_q <= "11001001000011111101101011";
--LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest(BITSELECT,309)@27
LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q(63 downto 0);
LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_in(63 downto 0);
--leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest(BITJOIN,310)@27
leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage263dto0_uid310_alignedZSin_uid67_fpSinCosXTest_b & GND_q;
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor(LOGICAL,1433)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q <= not (ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_a or ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_b);
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena(REG,1434)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_nor_q = "1") THEN
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd(LOGICAL,1435)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_sticky_ena_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b <= en;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_a and ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_b;
--X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest(BITSELECT,280)@21
X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(32 downto 0);
X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b <= X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_in(32 downto 0);
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg(DELAY,1425)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 33, depth => 1 )
PORT MAP ( xin => X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem(DUALMEM,1426)
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_inputreg_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 33,
widthad_a => 1,
numwords_a => 2,
width_b => 33,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_ia
);
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_iq(32 downto 0);
--leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest(BITJOIN,281)@25
leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q <= ld_X32dto0_uid281_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_b_replace_mem_q & zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor(LOGICAL,1444)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q <= not (ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_a or ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_b);
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena(REG,1445)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_nor_q = "1") THEN
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd(LOGICAL,1446)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_sticky_ena_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b <= en;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_a and ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_b;
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg(DELAY,1436)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 65, depth => 1 )
PORT MAP ( xin => zSin_uid60_fpSinCosXTest_q, xout => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem(DUALMEM,1437)
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_inputreg_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 65,
widthad_a => 1,
numwords_a => 2,
width_b => 65,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq,
address_a => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_aa,
data_a => ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_ia
);
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_reset0 <= areset;
ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_iq(64 downto 0);
--rVStage_uid237_lzcZSin_uid66_fpSinCosXTest(BITSELECT,236)@21
rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q;
rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_in(64 downto 1);
--vCount_uid238_lzcZSin_uid66_fpSinCosXTest(LOGICAL,237)@21
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid236_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid238_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid238_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid238_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g(DELAY,903)@22
ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid240_lzcZSin_uid66_fpSinCosXTest(BITSELECT,239)@21
vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in <= zSin_uid60_fpSinCosXTest_q(0 downto 0);
vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid240_lzcZSin_uid66_fpSinCosXTest_in(0 downto 0);
--ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b(DELAY,861)@21
ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cStage_uid241_lzcZSin_uid66_fpSinCosXTest(BITJOIN,240)@22
cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q <= ld_vStage_uid240_lzcZSin_uid66_fpSinCosXTest_b_to_cStage_uid241_lzcZSin_uid66_fpSinCosXTest_b_q & mO_uid239_lzcZSin_uid66_fpSinCosXTest_q;
--ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c(DELAY,863)@21
ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 64, depth => 1 )
PORT MAP ( xin => rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid243_lzcZSin_uid66_fpSinCosXTest(MUX,242)@22
vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid243_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s, en, ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q, cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q)
BEGIN
CASE vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= ld_rVStage_uid237_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= cStage_uid241_lzcZSin_uid66_fpSinCosXTest_q;
WHEN OTHERS => vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid245_lzcZSin_uid66_fpSinCosXTest(BITSELECT,244)@22
rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_in(63 downto 32);
--vCount_uid246_lzcZSin_uid66_fpSinCosXTest(LOGICAL,245)@22
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid244_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid246_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid246_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid246_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f(DELAY,902)@23
ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid247_lzcZSin_uid66_fpSinCosXTest(BITSELECT,246)@22
vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid243_lzcZSin_uid66_fpSinCosXTest_q(31 downto 0);
vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid247_lzcZSin_uid66_fpSinCosXTest_in(31 downto 0);
--ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d(DELAY,870)@22
ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c(DELAY,869)@22
ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b, xout => ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q, ena => en(0), clk => clk, aclr => areset );
--vStagei_uid249_lzcZSin_uid66_fpSinCosXTest(MUX,248)@23
vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid249_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s, en, ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q, ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q)
BEGIN
CASE vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= ld_rVStage_uid245_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_c_q;
WHEN "1" => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= ld_vStage_uid247_lzcZSin_uid66_fpSinCosXTest_b_to_vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_d_q;
WHEN OTHERS => vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid251_lzcZSin_uid66_fpSinCosXTest(BITSELECT,250)@23
rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_in(31 downto 16);
--vCount_uid252_lzcZSin_uid66_fpSinCosXTest(LOGICAL,251)@23
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b <= zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid252_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid252_lzcZSin_uid66_fpSinCosXTest_b else "0";
--reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4(REG,585)@23
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q <= vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e(DELAY,901)@24
ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q, xout => ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid253_lzcZSin_uid66_fpSinCosXTest(BITSELECT,252)@23
vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid249_lzcZSin_uid66_fpSinCosXTest_q(15 downto 0);
vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid253_lzcZSin_uid66_fpSinCosXTest_in(15 downto 0);
--vStagei_uid255_lzcZSin_uid66_fpSinCosXTest(MUX,254)@23
vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid252_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid255_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s, en, rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b, vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= rVStage_uid251_lzcZSin_uid66_fpSinCosXTest_b;
WHEN "1" => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= vStage_uid253_lzcZSin_uid66_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid257_lzcZSin_uid66_fpSinCosXTest(BITSELECT,256)@23
rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_in(15 downto 8);
--reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1(REG,580)@23
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q <= rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vCount_uid258_lzcZSin_uid66_fpSinCosXTest(LOGICAL,257)@24
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a <= reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q;
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid258_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid258_lzcZSin_uid66_fpSinCosXTest_b else "0";
--ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d(DELAY,900)@24
ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q, xout => ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q, ena => en(0), clk => clk, aclr => areset );
--vStage_uid259_lzcZSin_uid66_fpSinCosXTest(BITSELECT,258)@23
vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid255_lzcZSin_uid66_fpSinCosXTest_q(7 downto 0);
vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid259_lzcZSin_uid66_fpSinCosXTest_in(7 downto 0);
--reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3(REG,582)@23
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q <= vStage_uid259_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid261_lzcZSin_uid66_fpSinCosXTest(MUX,260)@24
vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid261_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s, en, reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q, reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= reg_rVStage_uid257_lzcZSin_uid66_fpSinCosXTest_0_to_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_1_q;
WHEN "1" => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= reg_vStage_uid259_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid263_lzcZSin_uid66_fpSinCosXTest(BITSELECT,262)@24
rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_in(7 downto 4);
--vCount_uid264_lzcZSin_uid66_fpSinCosXTest(LOGICAL,263)@24
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b <= leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i <= "1" when vCount_uid264_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid264_lzcZSin_uid66_fpSinCosXTest_b else "0";
vCount_uid264_lzcZSin_uid66_fpSinCosXTest_delay : dspba_delay
GENERIC MAP (width => 1, depth => 1)
PORT MAP (xout => vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q, xin => vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q_i, clk => clk, ena => en(0), aclr => areset);
--vStage_uid265_lzcZSin_uid66_fpSinCosXTest(BITSELECT,264)@24
vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid261_lzcZSin_uid66_fpSinCosXTest_q(3 downto 0);
vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid265_lzcZSin_uid66_fpSinCosXTest_in(3 downto 0);
--reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3(REG,584)@24
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q <= vStage_uid265_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2(REG,583)@24
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q <= "0000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q <= rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--vStagei_uid267_lzcZSin_uid66_fpSinCosXTest(MUX,266)@25
vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid267_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s, en, reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q, reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q)
BEGIN
CASE vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= reg_rVStage_uid263_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_2_q;
WHEN "1" => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= reg_vStage_uid265_lzcZSin_uid66_fpSinCosXTest_0_to_vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_3_q;
WHEN OTHERS => vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid269_lzcZSin_uid66_fpSinCosXTest(BITSELECT,268)@25
rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_in(3 downto 2);
--vCount_uid270_lzcZSin_uid66_fpSinCosXTest(LOGICAL,269)@25
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b <= leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid270_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid270_lzcZSin_uid66_fpSinCosXTest_b else "0";
--vStage_uid271_lzcZSin_uid66_fpSinCosXTest(BITSELECT,270)@25
vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid267_lzcZSin_uid66_fpSinCosXTest_q(1 downto 0);
vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b <= vStage_uid271_lzcZSin_uid66_fpSinCosXTest_in(1 downto 0);
--vStagei_uid273_lzcZSin_uid66_fpSinCosXTest(MUX,272)@25
vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s <= vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q;
vStagei_uid273_lzcZSin_uid66_fpSinCosXTest: PROCESS (vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s, en, rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b, vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b)
BEGIN
CASE vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_s IS
WHEN "0" => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= rVStage_uid269_lzcZSin_uid66_fpSinCosXTest_b;
WHEN "1" => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= vStage_uid271_lzcZSin_uid66_fpSinCosXTest_b;
WHEN OTHERS => vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid275_lzcZSin_uid66_fpSinCosXTest(BITSELECT,274)@25
rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in <= vStagei_uid273_lzcZSin_uid66_fpSinCosXTest_q;
rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b <= rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_in(1 downto 1);
--vCount_uid276_lzcZSin_uid66_fpSinCosXTest(LOGICAL,275)@25
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a <= rVStage_uid275_lzcZSin_uid66_fpSinCosXTest_b;
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b <= GND_q;
vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q <= "1" when vCount_uid276_lzcZSin_uid66_fpSinCosXTest_a = vCount_uid276_lzcZSin_uid66_fpSinCosXTest_b else "0";
--r_uid277_lzcZSin_uid66_fpSinCosXTest(BITJOIN,276)@25
r_uid277_lzcZSin_uid66_fpSinCosXTest_q <= ld_vCount_uid238_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_g_q & ld_vCount_uid246_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_f_q & ld_reg_vCount_uid252_lzcZSin_uid66_fpSinCosXTest_0_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_4_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_e_q & ld_vCount_uid258_lzcZSin_uid66_fpSinCosXTest_q_to_r_uid277_lzcZSin_uid66_fpSinCosXTest_d_q & vCount_uid264_lzcZSin_uid66_fpSinCosXTest_q & vCount_uid270_lzcZSin_uid66_fpSinCosXTest_q & vCount_uid276_lzcZSin_uid66_fpSinCosXTest_q;
--leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest(BITSELECT,284)@25
leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q;
leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_in(6 downto 5);
--leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest(MUX,285)@25
leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s <= leftShiftStageSel6Dto5_uid285_alignedZSin_uid67_fpSinCosXTest_b;
leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s, en, ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q, leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q, cstZmwFRRPwSM1_uid52_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= ld_zSin_uid60_fpSinCosXTest_q_to_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_c_replace_mem_q;
WHEN "01" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage0Idx1_uid282_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "10" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN "11" => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= cstZmwFRRPwSM1_uid52_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest(BITSELECT,293)@25
LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(40 downto 0);
LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_in(40 downto 0);
--leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest(BITJOIN,294)@25
leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage040dto0_uid294_alignedZSin_uid67_fpSinCosXTest_b & leftShiftStage1Idx3Pad24_uid293_alignedZSin_uid67_fpSinCosXTest_q;
--reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5(REG,590)@25
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q <= leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest(BITSELECT,290)@25
LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(48 downto 0);
LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_in(48 downto 0);
--leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest(BITJOIN,291)@25
leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage048dto0_uid291_alignedZSin_uid67_fpSinCosXTest_b & zs_uid250_lzcZSin_uid66_fpSinCosXTest_q;
--reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4(REG,589)@25
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q <= leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest(BITSELECT,287)@25
LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q(56 downto 0);
LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_in(56 downto 0);
--leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest(BITJOIN,288)@25
leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q <= LeftShiftStage056dto0_uid288_alignedZSin_uid67_fpSinCosXTest_b & cstAllZWE_uid8_fpSinCosXTest_q;
--reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3(REG,588)@25
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q <= leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2(REG,587)@25
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q <= leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest(BITSELECT,295)@25
leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1(REG,586)@25
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q <= leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest(MUX,296)@26
leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s <= reg_leftShiftStageSel4Dto3_uid296_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_1_q;
leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s, en, reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q, reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q, reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q, reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q)
BEGIN
CASE leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage0_uid286_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx1_uid289_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_3_q;
WHEN "10" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx2_uid292_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_4_q;
WHEN "11" => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1Idx3_uid295_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_5_q;
WHEN OTHERS => leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest(BITSELECT,304)@26
LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(58 downto 0);
LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_in(58 downto 0);
--ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b(DELAY,927)@26
ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 59, depth => 1 )
PORT MAP ( xin => LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest(BITJOIN,305)@27
leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage158dto0_uid305_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage2Idx3Pad6_uid304_alignedZSin_uid67_fpSinCosXTest_q;
--LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest(BITSELECT,301)@26
LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(60 downto 0);
LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_in(60 downto 0);
--ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b(DELAY,925)@26
ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 61, depth => 1 )
PORT MAP ( xin => LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest(BITJOIN,302)@27
leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage160dto0_uid302_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage0Idx1Pad4_uid213_fxpX_uid48_fpSinCosXTest_q;
--LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest(BITSELECT,298)@26
LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q(62 downto 0);
LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b <= LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_in(62 downto 0);
--ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b(DELAY,923)@26
ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 63, depth => 1 )
PORT MAP ( xin => LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest(BITJOIN,299)@27
leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q <= ld_LeftShiftStage162dto0_uid299_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_b_q & leftShiftStage1Idx2Pad2_uid227_fxpX_uid48_fpSinCosXTest_q;
--reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2(REG,592)@26
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q <= leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest(BITSELECT,306)@25
leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_in(2 downto 1);
--ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a(DELAY,1214)@25
ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1(REG,591)@26
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q <= ld_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_b_to_reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest(MUX,307)@27
leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s <= reg_leftShiftStageSel2Dto1_uid307_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_1_q;
leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s, en, reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q, leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "00" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= reg_leftShiftStage1_uid297_alignedZSin_uid67_fpSinCosXTest_0_to_leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_2_q;
WHEN "01" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx1_uid300_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "10" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx2_uid303_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "11" => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2Idx3_uid306_alignedZSin_uid67_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest(BITSELECT,311)@25
leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b <= leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b(DELAY,937)@25
ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b, xout => ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest(MUX,312)@27
leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s <= ld_leftShiftStageSel0Dto0_uid312_alignedZSin_uid67_fpSinCosXTest_b_to_leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_b_q;
leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest: PROCESS (leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s, en, leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q, leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q)
BEGIN
CASE leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_s IS
WHEN "0" => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage2_uid308_alignedZSin_uid67_fpSinCosXTest_q;
WHEN "1" => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= leftShiftStage3Idx1_uid311_alignedZSin_uid67_fpSinCosXTest_q;
WHEN OTHERS => leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--pHigh_uid72_fpSinCosXTest(BITSELECT,71)@27
pHigh_uid72_fpSinCosXTest_in <= leftShiftStage3_uid313_alignedZSin_uid67_fpSinCosXTest_q;
pHigh_uid72_fpSinCosXTest_b <= pHigh_uid72_fpSinCosXTest_in(64 downto 39);
--reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2(REG,594)@27
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q <= "00000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q <= pHigh_uid72_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a(DELAY,1216)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q, ena => en(0), clk => clk, aclr => areset );
--reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1(REG,593)@27
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_a_q;
END IF;
END IF;
END PROCESS;
--p_uid73_fpSinCosXTest(MUX,72)@28
p_uid73_fpSinCosXTest_s <= reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_p_uid73_fpSinCosXTest_1_q;
p_uid73_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
p_uid73_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE p_uid73_fpSinCosXTest_s IS
WHEN "0" => p_uid73_fpSinCosXTest_q <= reg_pHigh_uid72_fpSinCosXTest_0_to_p_uid73_fpSinCosXTest_2_q;
WHEN "1" => p_uid73_fpSinCosXTest_q <= cPi_uid71_fpSinCosXTest_q;
WHEN OTHERS => p_uid73_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg(DELAY,1312)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => p_uid73_fpSinCosXTest_q, xout => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem(DUALMEM,1313)
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_inputreg_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdreg_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_rdmux_q;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 1,
numwords_a => 2,
width_b => 26,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq,
address_a => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_aa,
data_a => ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_ia
);
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_reset0 <= areset;
ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_iq(25 downto 0);
--mulSin_uid92_fpSinCosXTest(MULT,91)@33
mulSin_uid92_fpSinCosXTest_pr <= UNSIGNED(mulSin_uid92_fpSinCosXTest_a) * UNSIGNED(mulSin_uid92_fpSinCosXTest_b);
mulSin_uid92_fpSinCosXTest_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulSin_uid92_fpSinCosXTest_a <= (others => '0');
mulSin_uid92_fpSinCosXTest_b <= (others => '0');
mulSin_uid92_fpSinCosXTest_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulSin_uid92_fpSinCosXTest_a <= ld_p_uid73_fpSinCosXTest_q_to_mulSin_uid92_fpSinCosXTest_a_replace_mem_q;
mulSin_uid92_fpSinCosXTest_b <= multSinOp2_uid91_fpSinCosXTest_q;
mulSin_uid92_fpSinCosXTest_s1 <= STD_LOGIC_VECTOR(mulSin_uid92_fpSinCosXTest_pr);
END IF;
END IF;
END PROCESS;
mulSin_uid92_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mulSin_uid92_fpSinCosXTest_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
mulSin_uid92_fpSinCosXTest_q <= mulSin_uid92_fpSinCosXTest_s1;
END IF;
END IF;
END PROCESS;
--normBitSin_uid93_fpSinCosXTest(BITSELECT,92)@36
normBitSin_uid93_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q;
normBitSin_uid93_fpSinCosXTest_b <= normBitSin_uid93_fpSinCosXTest_in(51 downto 51);
--join_uid99_fpSinCosXTest(BITJOIN,98)@36
join_uid99_fpSinCosXTest_q <= reg_sinXIsXRR_uid41_fpSinCosXTest_2_to_join_uid99_fpSinCosXTest_1_q & normBitSin_uid93_fpSinCosXTest_b;
--sinRndOp_uid100_uid101_fpSinCosXTest(BITJOIN,100)@36
sinRndOp_uid100_uid101_fpSinCosXTest_q <= join_uid99_fpSinCosXTest_q & cstAllZWF_uid7_fpSinCosXTest_q & VCC_q;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor(LOGICAL,1333)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q <= not (ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_a or ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_b);
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena(REG,1334)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_nor_q = "1") THEN
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd(LOGICAL,1335)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_sticky_ena_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b <= en;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_a and ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_b;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor(LOGICAL,1283)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q <= not (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_a or ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_b);
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena(REG,1284)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_nor_q = "1") THEN
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd(LOGICAL,1285)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_sticky_ena_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b <= en;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_a and ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_b;
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg(DELAY,1273)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expXRR_uid38_fpSinCosXTest_b, xout => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem(DUALMEM,1274)
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_inputreg_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdreg_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_rdmux_q;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 4,
numwords_a => 9,
width_b => 8,
widthad_b => 4,
numwords_b => 9,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_ia
);
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_iq(7 downto 0);
--reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1(REG,604)@25
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q <= "0000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q <= r_uid277_lzcZSin_uid66_fpSinCosXTest_q;
END IF;
END IF;
END PROCESS;
--expSinHC_uid74_fpSinCosXTest(SUB,73)@26
expSinHC_uid74_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_fpSinCosXTest_q);
expSinHC_uid74_fpSinCosXTest_b <= STD_LOGIC_VECTOR("00" & reg_r_uid277_lzcZSin_uid66_fpSinCosXTest_0_to_expSinHC_uid74_fpSinCosXTest_1_q);
expSinHC_uid74_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSinHC_uid74_fpSinCosXTest_a) - UNSIGNED(expSinHC_uid74_fpSinCosXTest_b));
expSinHC_uid74_fpSinCosXTest_q <= expSinHC_uid74_fpSinCosXTest_o(8 downto 0);
--expSinHCR_uid75_fpSinCosXTest(BITSELECT,74)@26
expSinHCR_uid75_fpSinCosXTest_in <= expSinHC_uid74_fpSinCosXTest_q(7 downto 0);
expSinHCR_uid75_fpSinCosXTest_b <= expSinHCR_uid75_fpSinCosXTest_in(7 downto 0);
--ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b(DELAY,695)@16
ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 10 )
PORT MAP ( xin => sinXIsXRR_uid41_fpSinCosXTest_n, xout => ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--expPSin_uid76_fpSinCosXTest(MUX,75)@26
expPSin_uid76_fpSinCosXTest_s <= ld_sinXIsXRR_uid41_fpSinCosXTest_n_to_expPSin_uid76_fpSinCosXTest_b_q;
expPSin_uid76_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expPSin_uid76_fpSinCosXTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE expPSin_uid76_fpSinCosXTest_s IS
WHEN "0" => expPSin_uid76_fpSinCosXTest_q <= expSinHCR_uid75_fpSinCosXTest_b;
WHEN "1" => expPSin_uid76_fpSinCosXTest_q <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_replace_mem_q;
WHEN OTHERS => expPSin_uid76_fpSinCosXTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg(DELAY,1323)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expPSin_uid76_fpSinCosXTest_q, xout => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem(DUALMEM,1324)
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_inputreg_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdreg_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab <= ld_reg_r_uid356_lzcZCos_uid69_fpSinCosXTest_0_to_expHardCase_uid78_fpSinCosXTest_1_q_to_expHardCase_uid78_fpSinCosXTest_b_replace_rdmux_q;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 7,
width_b => 8,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq,
address_a => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_aa,
data_a => ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_ia
);
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_reset0 <= areset;
ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_iq(7 downto 0);
--fracRSinPreRndHigh_uid95_fpSinCosXTest(BITSELECT,94)@36
fracRSinPreRndHigh_uid95_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q(50 downto 0);
fracRSinPreRndHigh_uid95_fpSinCosXTest_b <= fracRSinPreRndHigh_uid95_fpSinCosXTest_in(50 downto 27);
--fracRSinPreRndLow_uid96_fpSinCosXTest(BITSELECT,95)@36
fracRSinPreRndLow_uid96_fpSinCosXTest_in <= mulSin_uid92_fpSinCosXTest_q(49 downto 0);
fracRSinPreRndLow_uid96_fpSinCosXTest_b <= fracRSinPreRndLow_uid96_fpSinCosXTest_in(49 downto 26);
--fracRSinPreRnd_uid97_fpSinCosXTest(MUX,96)@36
fracRSinPreRnd_uid97_fpSinCosXTest_s <= normBitSin_uid93_fpSinCosXTest_b;
fracRSinPreRnd_uid97_fpSinCosXTest: PROCESS (fracRSinPreRnd_uid97_fpSinCosXTest_s, en, fracRSinPreRndLow_uid96_fpSinCosXTest_b, fracRSinPreRndHigh_uid95_fpSinCosXTest_b)
BEGIN
CASE fracRSinPreRnd_uid97_fpSinCosXTest_s IS
WHEN "0" => fracRSinPreRnd_uid97_fpSinCosXTest_q <= fracRSinPreRndLow_uid96_fpSinCosXTest_b;
WHEN "1" => fracRSinPreRnd_uid97_fpSinCosXTest_q <= fracRSinPreRndHigh_uid95_fpSinCosXTest_b;
WHEN OTHERS => fracRSinPreRnd_uid97_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracRSinPreRnd_uid98_uid98_fpSinCosXTest(BITJOIN,97)@36
expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q <= ld_expPSin_uid76_fpSinCosXTest_q_to_expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_b_replace_mem_q & fracRSinPreRnd_uid97_fpSinCosXTest_q;
--expFracRSin_uid102_fpSinCosXTest(ADD,101)@36
expFracRSin_uid102_fpSinCosXTest_a <= STD_LOGIC_VECTOR("0" & expFracRSinPreRnd_uid98_uid98_fpSinCosXTest_q);
expFracRSin_uid102_fpSinCosXTest_b <= STD_LOGIC_VECTOR("0000000" & sinRndOp_uid100_uid101_fpSinCosXTest_q);
expFracRSin_uid102_fpSinCosXTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRSin_uid102_fpSinCosXTest_a) + UNSIGNED(expFracRSin_uid102_fpSinCosXTest_b));
expFracRSin_uid102_fpSinCosXTest_q <= expFracRSin_uid102_fpSinCosXTest_o(32 downto 0);
--expRCompSin_uid104_fpSinCosXTest(BITSELECT,103)@36
expRCompSin_uid104_fpSinCosXTest_in <= expFracRSin_uid102_fpSinCosXTest_q(31 downto 0);
expRCompSin_uid104_fpSinCosXTest_b <= expRCompSin_uid104_fpSinCosXTest_in(31 downto 24);
--reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2(REG,607)@36
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q <= "00000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q <= expRCompSin_uid104_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor(LOGICAL,1537)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q <= not (ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_a or ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_b);
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena(REG,1538)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_nor_q = "1") THEN
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd(LOGICAL,1539)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_sticky_ena_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b <= en;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_a and ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_b;
--expXIsZero_uid10_fpSinCosXTest(LOGICAL,9)@0
expXIsZero_uid10_fpSinCosXTest_a <= exp_uid9_fpSinCosXTest_b;
expXIsZero_uid10_fpSinCosXTest_b <= cstAllZWE_uid8_fpSinCosXTest_q;
expXIsZero_uid10_fpSinCosXTest_q <= "1" when expXIsZero_uid10_fpSinCosXTest_a = expXIsZero_uid10_fpSinCosXTest_b else "0";
--ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b(DELAY,746)@0
ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 19 )
PORT MAP ( xin => expXIsZero_uid10_fpSinCosXTest_q, xout => ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q, ena => en(0), clk => clk, aclr => areset );
--excSelBitsSin_uid118_fpSinCosXTest(BITJOIN,117)@19
excSelBitsSin_uid118_fpSinCosXTest_q <= excRNaN_uid117_fpSinCosXTest_q & ld_expXIsZero_uid10_fpSinCosXTest_q_to_excSelBitsSin_uid118_fpSinCosXTest_b_q & ld_sinXIsX_uid40_fpSinCosXTest_n_to_excSelBitsSin_uid118_fpSinCosXTest_a_q;
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg(DELAY,1527)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 3, depth => 1 )
PORT MAP ( xin => excSelBitsSin_uid118_fpSinCosXTest_q, xout => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem(DUALMEM,1528)
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_inputreg_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdreg_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab <= ld_oFracXRRSmallXRR_uid90_fpSinCosXTest_b_to_multSinOp2_uid91_fpSinCosXTest_d_replace_rdmux_q;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 3,
widthad_a => 4,
numwords_a => 14,
width_b => 3,
widthad_b => 4,
numwords_b => 14,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq,
address_a => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_aa,
data_a => ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_ia
);
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_reset0 <= areset;
ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_iq(2 downto 0);
--reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0(REG,533)@35
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q <= ld_excSelBitsSin_uid118_fpSinCosXTest_q_to_reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--excSelSin_uid119_fpSinCosXTest(LOOKUP,118)@36
excSelSin_uid119_fpSinCosXTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
excSelSin_uid119_fpSinCosXTest_q <= "00";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
CASE (reg_excSelBitsSin_uid118_fpSinCosXTest_0_to_excSelSin_uid119_fpSinCosXTest_0_q) IS
WHEN "000" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN "001" => excSelSin_uid119_fpSinCosXTest_q <= "01";
WHEN "010" => excSelSin_uid119_fpSinCosXTest_q <= "10";
WHEN "011" => excSelSin_uid119_fpSinCosXTest_q <= "10";
WHEN "100" => excSelSin_uid119_fpSinCosXTest_q <= "11";
WHEN "101" => excSelSin_uid119_fpSinCosXTest_q <= "11";
WHEN "110" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN "111" => excSelSin_uid119_fpSinCosXTest_q <= "00";
WHEN OTHERS =>
excSelSin_uid119_fpSinCosXTest_q <= (others => '-');
END CASE;
END IF;
END IF;
END PROCESS;
--expRPostExcSin_uid126_fpSinCosXTest(MUX,125)@37
expRPostExcSin_uid126_fpSinCosXTest_s <= excSelSin_uid119_fpSinCosXTest_q;
expRPostExcSin_uid126_fpSinCosXTest: PROCESS (expRPostExcSin_uid126_fpSinCosXTest_s, en, reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q, ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q, cstAllZWE_uid8_fpSinCosXTest_q, cstAllOWE_uid6_fpSinCosXTest_q)
BEGIN
CASE expRPostExcSin_uid126_fpSinCosXTest_s IS
WHEN "00" => expRPostExcSin_uid126_fpSinCosXTest_q <= reg_expRCompSin_uid104_fpSinCosXTest_0_to_expRPostExcSin_uid126_fpSinCosXTest_2_q;
WHEN "01" => expRPostExcSin_uid126_fpSinCosXTest_q <= ld_exp_uid9_fpSinCosXTest_b_to_expRPostExcSin_uid126_fpSinCosXTest_d_replace_mem_q;
WHEN "10" => expRPostExcSin_uid126_fpSinCosXTest_q <= cstAllZWE_uid8_fpSinCosXTest_q;
WHEN "11" => expRPostExcSin_uid126_fpSinCosXTest_q <= cstAllOWE_uid6_fpSinCosXTest_q;
WHEN OTHERS => expRPostExcSin_uid126_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor(LOGICAL,1346)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a <= ld_expXRR_uid38_fpSinCosXTest_b_to_expPSin_uid76_fpSinCosXTest_d_notEnable_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q <= not (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_a or ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_b);
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena(REG,1347)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_nor_q = "1") THEN
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd(LOGICAL,1348)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_sticky_ena_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b <= en;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_a and ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_b;
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg(DELAY,1336)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => frac_uid13_fpSinCosXTest_b, xout => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem(DUALMEM,1337)
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_inputreg_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdreg_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_rdmux_q;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 23,
widthad_a => 6,
numwords_a => 35,
width_b => 23,
widthad_b => 6,
numwords_b => 35,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0,
clock1 => clk,
address_b => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq,
address_a => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_aa,
data_a => ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_ia
);
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_reset0 <= areset;
ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_iq(22 downto 0);
--fracRCompSin_uid103_fpSinCosXTest(BITSELECT,102)@36
fracRCompSin_uid103_fpSinCosXTest_in <= expFracRSin_uid102_fpSinCosXTest_q(23 downto 0);
fracRCompSin_uid103_fpSinCosXTest_b <= fracRCompSin_uid103_fpSinCosXTest_in(23 downto 1);
--reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2(REG,606)@36
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q <= fracRCompSin_uid103_fpSinCosXTest_b;
END IF;
END IF;
END PROCESS;
--fracRPostExcSin_uid122_fpSinCosXTest(MUX,121)@37
fracRPostExcSin_uid122_fpSinCosXTest_s <= excSelSin_uid119_fpSinCosXTest_q;
fracRPostExcSin_uid122_fpSinCosXTest: PROCESS (fracRPostExcSin_uid122_fpSinCosXTest_s, en, reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q, ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q, cstAllZWF_uid7_fpSinCosXTest_q, cstNaNwF_uid32_fpSinCosXTest_q)
BEGIN
CASE fracRPostExcSin_uid122_fpSinCosXTest_s IS
WHEN "00" => fracRPostExcSin_uid122_fpSinCosXTest_q <= reg_fracRCompSin_uid103_fpSinCosXTest_0_to_fracRPostExcSin_uid122_fpSinCosXTest_2_q;
WHEN "01" => fracRPostExcSin_uid122_fpSinCosXTest_q <= ld_frac_uid13_fpSinCosXTest_b_to_fracRPostExcSin_uid122_fpSinCosXTest_d_replace_mem_q;
WHEN "10" => fracRPostExcSin_uid122_fpSinCosXTest_q <= cstAllZWF_uid7_fpSinCosXTest_q;
WHEN "11" => fracRPostExcSin_uid122_fpSinCosXTest_q <= cstNaNwF_uid32_fpSinCosXTest_q;
WHEN OTHERS => fracRPostExcSin_uid122_fpSinCosXTest_q <= (others => '0');
END CASE;
END PROCESS;
--fpSin_uid134_fpSinCosXTest(BITJOIN,133)@37
fpSin_uid134_fpSinCosXTest_q <= ld_signRSinFull_uid133_fpSinCosXTest_q_to_fpSin_uid134_fpSinCosXTest_c_q & expRPostExcSin_uid126_fpSinCosXTest_q & fracRPostExcSin_uid122_fpSinCosXTest_q;
--xOut(GPOUT,4)@37
s <= fpSin_uid134_fpSinCosXTest_q;
c <= fpCos_uid162_fpSinCosXTest_q;
end normal;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
bin_Gaussian_Filter/ip/Gaussian_Filter/hcc_mul54uss_8tst.vhd
|
10
|
8877
|
LIBRARY ieee;
LIBRARY work;
LIBRARY lpm;
USE lpm.all;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_MUL54USS_8TST.VHD ***
--*** ***
--*** Function: 6 pipeline stage unsigned 54 ***
--*** bit multiplier (synthesizable) ***
--*** ***
--*** FOR FITTING TESTING ONLY - NOT TESTED ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_mul54uss_8tst IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
mulaa, mulbb : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
mulcc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_mul54uss_8tst;
ARCHITECTURE syn of hcc_mul54uss_8tst IS
signal muloneout : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal multwoout, multhrout : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mulforout, mulfivout : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal vecone, vectwo, vecthr : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal sumone, carone : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal vecfor, vecfiv, vecsix : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal sumtwo, cartwo : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal sumtwoff, cartwoff : STD_LOGIC_VECTOR (38 DOWNTO 1);
signal vecsev, vecegt, vecnin : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumthr, carthr : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal sumthrff, carthrff : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (34 DOWNTO 1);
component altmult_add
GENERIC (
addnsub_multiplier_aclr1 : STRING;
addnsub_multiplier_pipeline_aclr1 : STRING;
addnsub_multiplier_pipeline_register1 : STRING;
addnsub_multiplier_register1 : STRING;
dedicated_multiplier_circuitry : STRING;
input_aclr_a0 : STRING;
input_aclr_b0 : STRING;
input_register_a0 : STRING;
input_register_b0 : STRING;
input_source_a0 : STRING;
input_source_b0 : STRING;
intended_device_family : STRING;
lpm_type : STRING;
multiplier1_direction : STRING;
multiplier_aclr0 : STRING;
multiplier_register0 : STRING;
number_of_multipliers : NATURAL;
output_aclr : STRING;
output_register : STRING;
port_addnsub1 : STRING;
port_signa : STRING;
port_signb : STRING;
representation_a : STRING;
representation_b : STRING;
signed_aclr_a : STRING;
signed_aclr_b : STRING;
signed_pipeline_aclr_a : STRING;
signed_pipeline_aclr_b : STRING;
signed_pipeline_register_a : STRING;
signed_pipeline_register_b : STRING;
signed_register_a : STRING;
signed_register_b : STRING;
width_a : NATURAL;
width_b : NATURAL;
width_result : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (width_a-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (width_b-1 DOWNTO 0);
clock0 : IN STD_LOGIC ;
aclr3 : IN STD_LOGIC ;
ena0 : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (width_result-1 DOWNTO 0)
);
end component;
-- identical component to that above, but fixed at 18x18, latency 2
-- mul18usus generated by Quartus
component hcc_mul18usus
PORT
(
aclr3 : IN STD_LOGIC := '0';
clock0 : IN STD_LOGIC := '1';
dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
datab_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0');
ena0 : IN STD_LOGIC := '1';
result : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
);
end component;
COMPONENT lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_pipeline : NATURAL;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
);
END COMPONENT;
BEGIN
gza: FOR k IN 1 TO 34 GENERATE
zerovec(k) <= '0';
END GENERATE;
mulone : altmult_add
GENERIC MAP (
addnsub_multiplier_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_aclr1 => "ACLR3",
addnsub_multiplier_pipeline_register1 => "CLOCK0",
addnsub_multiplier_register1 => "CLOCK0",
dedicated_multiplier_circuitry => "AUTO",
input_aclr_a0 => "ACLR3",
input_aclr_b0 => "ACLR3",
input_register_a0 => "CLOCK0",
input_register_b0 => "CLOCK0",
input_source_a0 => "DATAA",
input_source_b0 => "DATAB",
intended_device_family => "Stratix II",
lpm_type => "altmult_add",
multiplier1_direction => "ADD",
multiplier_aclr0 => "ACLR3",
multiplier_register0 => "CLOCK0",
number_of_multipliers => 1,
output_aclr => "ACLR3",
output_register => "CLOCK0",
port_addnsub1 => "PORT_UNUSED",
port_signa => "PORT_UNUSED",
port_signb => "PORT_UNUSED",
representation_a => "UNSIGNED",
representation_b => "UNSIGNED",
signed_aclr_a => "ACLR3",
signed_aclr_b => "ACLR3",
signed_pipeline_aclr_a => "ACLR3",
signed_pipeline_aclr_b => "ACLR3",
signed_pipeline_register_a => "CLOCK0",
signed_pipeline_register_b => "CLOCK0",
signed_register_a => "CLOCK0",
signed_register_b => "CLOCK0",
width_a => 36,
width_b => 36,
width_result => 72
)
PORT MAP (
dataa => mulaa(54 DOWNTO 19),
datab => mulbb(54 DOWNTO 19),
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => muloneout
);
-- Blo*C 18*18 = 36, latency = 2
multwo: hcc_mul18usus
PORT MAP (
dataa_0 => mulaa(54 DOWNTO 37),
datab_0 => mulbb(18 DOWNTO 1),
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => multwoout
);
-- Bhi*C 18*18 = 36, latency = 2
multhr: hcc_mul18usus
PORT MAP (
dataa_0 => mulaa(36 DOWNTO 19),
datab_0 => mulbb(18 DOWNTO 1),
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => multhrout
);
-- Alo*D 18*18 = 36, latency = 2
mulfor: hcc_mul18usus
PORT MAP (
dataa_0 => mulbb(54 DOWNTO 37),
datab_0 => mulaa(18 DOWNTO 1),
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulforout
);
-- Ahi*D 18*18 = 36, latency = 2
mulfiv: hcc_mul18usus
PORT MAP (
dataa_0 => mulbb(36 DOWNTO 19),
datab_0 => mulaa(18 DOWNTO 1),
clock0 => sysclk,
aclr3 => reset,
ena0 => enable,
result => mulfivout
);
vecone <= multwoout;
vectwo <= zerovec(18 DOWNTO 1) & multhrout(36 DOWNTO 19);
vecthr <= mulforout;
gca: FOR k IN 1 TO 36 GENERATE
sumone(k) <= vecone(k) XOR vectwo(k) XOR vecthr(k);
carone(k) <= (vecone(k) AND vectwo(k)) OR
(vecone(k) AND vecthr(k)) OR
(vectwo(k) AND vecthr(k));
END GENERATE;
vecfor <= '0' & sumone;
vecfiv <= carone & '0';
vecsix <= zerovec(19 DOWNTO 1) & mulfivout(36 DOWNTO 19);
gcb: FOR k IN 1 TO 37 GENERATE
sumtwo(k) <= vecfor(k) XOR vecfiv(k) XOR vecsix(k);
cartwo(k) <= (vecfor(k) AND vecfiv(k)) OR
(vecfor(k) AND vecsix(k)) OR
(vecfiv(k) AND vecsix(k));
END GENERATE;
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 38 LOOP
sumtwoff(k) <= '0';
cartwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sumtwoff <= '0' & sumtwo;
cartwoff <= cartwo & '0';
END IF;
END IF;
END PROCESS;
vecsev <= zerovec(34 DOWNTO 1) & sumtwoff;
vecegt <= zerovec(34 DOWNTO 1) & cartwoff;
vecnin <= muloneout;
gcc: FOR k IN 1 TO 72 GENERATE
sumthr(k) <= vecsev(k) XOR vecegt(k) XOR vecnin(k);
carthr(k) <= (vecsev(k) AND vecegt(k)) OR
(vecsev(k) AND vecnin(k)) OR
(vecegt(k) AND vecnin(k));
END GENERATE;
pmb: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 72 LOOP
sumthrff(k) <= '0';
carthrff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
sumthrff <= sumthr;
carthrff <= carthr(71 DOWNTO 1) & '0';
END IF;
END IF;
END PROCESS;
-- according to marcel, 2 pipes = 1 pipe in middle, on on output
adder : lpm_add_sub
GENERIC MAP (
lpm_direction => "ADD",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
lpm_pipeline => 2,
lpm_type => "LPM_ADD_SUB",
lpm_width => 64
)
PORT MAP (
dataa => sumthrff(72 DOWNTO 9),
datab => carthrff(72 DOWNTO 9),
clken => enable,
aclr => reset,
clock => sysclk,
result => mulcc
);
END syn;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
bin_Gaussian_Filter/ip/Gaussian_Filter/CosPiDPStratixVf400.vhd
|
10
|
580991
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Debug Version 12.0
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from CosPiDPStratixVf400
-- VHDL created on Wed Sep 05 17:56:14 2012
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
USE work.CosPiDPStratixVf400_safe_path.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
-- Text written from d:/qshell64/p4/ip/aion/src/mip_common/hw_model.cpp:1240
entity CosPiDPStratixVf400 is
port (
xIn_v : in std_logic_vector(0 downto 0);
xIn_c : in std_logic_vector(7 downto 0);
xIn_0 : in std_logic_vector(63 downto 0);
xOut_v : out std_logic_vector(0 downto 0);
xOut_c : out std_logic_vector(7 downto 0);
xOut_0 : out std_logic_vector(63 downto 0);
clk : in std_logic;
areset : in std_logic;
bus_clk : in std_logic;
h_areset : in std_logic
);
end;
architecture normal of CosPiDPStratixVf400 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal GND_q : std_logic_vector (0 downto 0);
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid8_fpCosPiTest_q : std_logic_vector (10 downto 0);
signal cstAllZWF_uid9_fpCosPiTest_q : std_logic_vector (51 downto 0);
signal cstBias_uid10_fpCosPiTest_q : std_logic_vector (10 downto 0);
signal cstBiasM1_uid11_fpCosPiTest_q : std_logic_vector (10 downto 0);
signal cstBiasPwF_uid12_fpCosPiTest_q : std_logic_vector (10 downto 0);
signal biasMwShift_uid13_fpCosPiTest_q : std_logic_vector (10 downto 0);
signal biasMwShiftMO_uid14_fpCosPiTest_q : std_logic_vector (10 downto 0);
signal cst01pWShift_uid15_fpCosPiTest_q : std_logic_vector (27 downto 0);
signal cstZwSwF_uid16_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal cstAllZWE_uid22_fpCosPiTest_q : std_logic_vector (10 downto 0);
signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_a : std_logic_vector(81 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_b : std_logic_vector(81 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_o : std_logic_vector (81 downto 0);
signal oMFxpXFrac_uid49_fpCosPiTest_q : std_logic_vector (81 downto 0);
signal rangeReducedFxPX_uid53_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal rangeReducedFxPX_uid53_fpCosPiTest_q : std_logic_vector (79 downto 0);
signal z_halfMRRFxPXE_uid54_fpCosPiTest_a : std_logic_vector(80 downto 0);
signal z_halfMRRFxPXE_uid54_fpCosPiTest_b : std_logic_vector(80 downto 0);
signal z_halfMRRFxPXE_uid54_fpCosPiTest_o : std_logic_vector (80 downto 0);
signal z_halfMRRFxPXE_uid54_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal xIsInt_uid82_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIsInt_uid82_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIsInt_uid82_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal or_uid87_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal or_uid87_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal or_uid87_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal or_uid87_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal or_uid87_fpCosPiTest_e : std_logic_vector(0 downto 0);
signal or_uid87_fpCosPiTest_f : std_logic_vector(0 downto 0);
signal or_uid87_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracRPostExc1_uid88_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc1_uid88_fpCosPiTest_q : std_logic_vector (51 downto 0);
signal oneFracRPostExc2_uid89_fpCosPiTest_q : std_logic_vector (51 downto 0);
signal expRPostExc1_uid93_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal expRPostExc1_uid93_fpCosPiTest_q : std_logic_vector (10 downto 0);
signal leftShiftStage0Idx1Pad32_uid107_fxpX_uid43_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal leftShiftStage0Idx2Pad64_uid110_fxpX_uid43_fpCosPiTest_q : std_logic_vector (63 downto 0);
signal leftShiftStage0Idx3_uid113_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal leftShiftStage1Idx1Pad8_uid116_fxpX_uid43_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage1Idx2Pad16_uid119_fxpX_uid43_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal leftShiftStage1Idx3Pad24_uid122_fxpX_uid43_fpCosPiTest_q : std_logic_vector (23 downto 0);
signal leftShiftStage2Idx1Pad2_uid127_fxpX_uid43_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal leftShiftStage2Idx2Pad4_uid130_fxpX_uid43_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage2Idx3Pad6_uid133_fxpX_uid43_fpCosPiTest_q : std_logic_vector (5 downto 0);
signal mO_uid147_lzcZ_uid58_fpCosPiTest_q : std_logic_vector (48 downto 0);
signal memoryC3_uid228_sinPiZTableGenerator_q : std_logic_vector(34 downto 0);
signal memoryC4_uid229_sinPiZTableGenerator_q : std_logic_vector(25 downto 0);
signal memoryC5_uid230_sinPiZTableGenerator_q : std_logic_vector(16 downto 0);
signal rndBit_uid245_sinPiZPolyEval_q : std_logic_vector (1 downto 0);
signal rndBit_uid257_sinPiZPolyEval_q : std_logic_vector (2 downto 0);
signal prodXY_uid262_pT1_uid232_sinPiZPolyEval_a : std_logic_vector (16 downto 0);
signal prodXY_uid262_pT1_uid232_sinPiZPolyEval_b : std_logic_vector (16 downto 0);
signal prodXY_uid262_pT1_uid232_sinPiZPolyEval_s1 : std_logic_vector (33 downto 0);
signal prodXY_uid262_pT1_uid232_sinPiZPolyEval_pr : SIGNED (34 downto 0);
signal prodXY_uid262_pT1_uid232_sinPiZPolyEval_q : std_logic_vector (33 downto 0);
signal prodXY_uid265_pT2_uid238_sinPiZPolyEval_a : std_logic_vector (25 downto 0);
signal prodXY_uid265_pT2_uid238_sinPiZPolyEval_b : std_logic_vector (27 downto 0);
signal prodXY_uid265_pT2_uid238_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0);
signal prodXY_uid265_pT2_uid238_sinPiZPolyEval_pr : SIGNED (54 downto 0);
signal prodXY_uid265_pT2_uid238_sinPiZPolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid270_pT3_uid244_sinPiZPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid270_pT3_uid244_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid270_pT3_uid244_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid270_pT3_uid244_sinPiZPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid270_pT3_uid244_sinPiZPolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid287_pT4_uid250_sinPiZPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid287_pT4_uid250_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid287_pT4_uid250_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid287_pT4_uid250_sinPiZPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid287_pT4_uid250_sinPiZPolyEval_q : std_logic_vector (53 downto 0);
signal topProd_uid302_pT5_uid256_sinPiZPolyEval_a : std_logic_vector (26 downto 0);
signal topProd_uid302_pT5_uid256_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal topProd_uid302_pT5_uid256_sinPiZPolyEval_s1 : std_logic_vector (53 downto 0);
signal topProd_uid302_pT5_uid256_sinPiZPolyEval_pr : SIGNED (54 downto 0);
signal topProd_uid302_pT5_uid256_sinPiZPolyEval_q : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a0_b0_a : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a0_b0_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a0_b0_s1 : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a0_b0_pr : UNSIGNED (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a0_b0_q : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a1_b0_a : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a1_b0_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a1_b0_s1 : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a1_b0_pr : UNSIGNED (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a1_b0_q : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a0_b1_a : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a0_b1_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a0_b1_s1 : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a0_b1_pr : UNSIGNED (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a0_b1_q : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a1_b1_a : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a1_b1_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a1_b1_s1 : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a1_b1_pr : UNSIGNED (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a1_b1_q : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_zero_36_q : std_logic_vector (26 downto 0);
type multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(18 downto 0);
signal multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_a : multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_a_type;
type multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(17 downto 0);
signal multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_c : multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_c_type;
type multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(36 downto 0);
signal multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_p : multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_p_type;
type multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_w_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_w : multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_w_type;
type multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_x_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_x : multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_x_type;
type multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_y_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_y : multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_y_type;
type multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_s_type is array(0 to 0) of SIGNED(37 downto 0);
signal multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_s : multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_s_type;
signal multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_s0 : std_logic_vector(36 downto 0);
signal multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_q : std_logic_vector (36 downto 0);
type multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_a : multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_a_type;
type multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_c : multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_c_type;
type multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_p : multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_p_type;
type multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_w : multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_w_type;
type multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_x : multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_x_type;
type multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_y : multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_y_type;
type multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_s : multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_s_type;
signal multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_q : std_logic_vector (54 downto 0);
type multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_a_type is array(0 to 1) of SIGNED(27 downto 0);
signal multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_a : multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_a_type;
type multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_c_type is array(0 to 1) of SIGNED(26 downto 0);
signal multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_c : multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_c_type;
type multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_p_type is array(0 to 1) of SIGNED(54 downto 0);
signal multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_p : multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_p_type;
type multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_w_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_w : multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_w_type;
type multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_x_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_x : multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_x_type;
type multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_y_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_y : multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_y_type;
type multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_s_type is array(0 to 1) of SIGNED(55 downto 0);
signal multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_s : multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_s_type;
signal multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_s0 : std_logic_vector(54 downto 0);
signal multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_q : std_logic_vector (54 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_a : std_logic_vector(90 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_b : std_logic_vector(90 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_o : std_logic_vector (90 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_cin : std_logic_vector (0 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_c : std_logic_vector (0 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_q : std_logic_vector (88 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_a : std_logic_vector(21 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_b : std_logic_vector(21 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_o : std_logic_vector (21 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_cin : std_logic_vector (0 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_q : std_logic_vector (19 downto 0);
signal reg_leftShiftStage3Idx1_uid140_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_3_q : std_logic_vector (80 downto 0);
signal reg_leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_2_q : std_logic_vector (80 downto 0);
signal reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracZero_uid47_fpCosPiTest_0_q : std_logic_vector (79 downto 0);
signal reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracHalf_uid48_fpCosPiTest_0_q : std_logic_vector (79 downto 0);
signal reg_xIsHalf_uid85_fpCosPiTest_0_to_or_uid87_fpCosPiTest_4_q : std_logic_vector (0 downto 0);
signal reg_fxpXFrac_uid45_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_1_q : std_logic_vector (79 downto 0);
signal reg_pad_o_uid17_uid49_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_0_q : std_logic_vector (80 downto 0);
signal reg_pad_half_uid18_uid54_fpCosPiTest_0_to_z_halfMRRFxPXE_uid54_fpCosPiTest_0_q : std_logic_vector (79 downto 0);
signal reg_rVStage_uid153_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid154_lzcZ_uid58_fpCosPiTest_0_q : std_logic_vector (31 downto 0);
signal reg_rVStage_uid159_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid160_lzcZ_uid58_fpCosPiTest_0_q : std_logic_vector (15 downto 0);
signal reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid166_lzcZ_uid58_fpCosPiTest_0_q : std_logic_vector (7 downto 0);
signal reg_vStage_uid167_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_3_q : std_logic_vector (7 downto 0);
signal reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_2_q : std_logic_vector (7 downto 0);
signal reg_leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal reg_leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_1_q : std_logic_vector (0 downto 0);
signal reg_s1_uid233_uid236_sinPiZPolyEval_0_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_1_q : std_logic_vector (27 downto 0);
signal reg_highBBits_uid240_sinPiZPolyEval_0_to_sumAHighB_uid241_sinPiZPolyEval_1_q : std_logic_vector (27 downto 0);
signal reg_yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_9_q : std_logic_vector (17 downto 0);
signal reg_pad_yBottomBits_uid272_uid277_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_6_q : std_logic_vector (17 downto 0);
signal reg_yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_0_to_topProd_uid270_pT3_uid244_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_highBBits_uid281_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0);
signal reg_topProd_uid270_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0);
signal reg_R_uid284_pT3_uid244_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_1_q : std_logic_vector (36 downto 0);
signal reg_cIncludingRoundingBit_uid246_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_0_q : std_logic_vector (44 downto 0);
signal reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid288_uid292_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_highBBits_uid296_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0);
signal reg_topProd_uid287_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0);
signal reg_R_uid299_pT4_uid250_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_1_q : std_logic_vector (45 downto 0);
signal reg_cIncludingRoundingBit_uid252_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_0_q : std_logic_vector (51 downto 0);
signal reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_9_q : std_logic_vector (26 downto 0);
signal reg_pad_yBottomBits_uid303_uid307_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_6_q : std_logic_vector (26 downto 0);
signal reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_1_q : std_logic_vector (26 downto 0);
signal reg_highBBits_uid311_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_1_q : std_logic_vector (28 downto 0);
signal reg_topProd_uid302_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_0_q : std_logic_vector (53 downto 0);
signal reg_R_uid314_pT5_uid256_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_1_q : std_logic_vector (53 downto 0);
signal reg_cIncludingRoundingBit_uid258_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_0_q : std_logic_vector (60 downto 0);
signal reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_1_q : std_logic_vector (26 downto 0);
signal reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_0_q : std_logic_vector (26 downto 0);
signal reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_1_q : std_logic_vector (26 downto 0);
signal reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_0_q : std_logic_vector (26 downto 0);
signal reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_1_q : std_logic_vector (26 downto 0);
signal reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_0_q : std_logic_vector (26 downto 0);
signal reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_1_q : std_logic_vector (26 downto 0);
signal reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_0_q : std_logic_vector (26 downto 0);
signal reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q : std_logic_vector (6 downto 0);
signal reg_expFracPreRnd_uid73_uid73_fpCosPiTest_0_to_expFracComp_uid76_fpCosPiTest_0_q : std_logic_vector (63 downto 0);
signal reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_q : std_logic_vector (1 downto 0);
signal ld_FxpXFrac79_uid46_fpCosPiTest_b_to_rangeReducedFxPX_uid53_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_fxpXFrac_uid45_fpCosPiTest_b_to_rangeReducedFxPX_uid53_fpCosPiTest_c_q : std_logic_vector (79 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_zPPolyEval_uid65_fpCosPiTest_a_q : std_logic_vector (78 downto 0);
signal ld_normBit_uid69_fpCosPiTest_b_to_rndExpUpdate_uid74_uid75_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOne_uid38_fpCosPiTest_c_to_InvCosXIsOne_uid79_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_xEvenInt_uid37_fpCosPiTest_c_to_Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_q_to_xIsInt_uid82_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_cosXIsOne_uid38_fpCosPiTest_c_to_or_uid87_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_fxpXFracHalf_uid48_fpCosPiTest_q_to_or_uid87_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_expXIsZero_uid24_fpCosPiTest_q_to_or_uid87_fpCosPiTest_d_q : std_logic_vector (0 downto 0);
signal ld_Or2ZeroExcRNaN_uid94_fpCosPiTest_q_to_join_uid96_fpCosPiTest_a_q : std_logic_vector (0 downto 0);
signal ld_Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_q_to_signRComp_uid101_fpCosPiTest_c_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest_b_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_b_q : std_logic_vector (0 downto 0);
signal ld_rVStage_uid153_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_c_q : std_logic_vector (31 downto 0);
signal ld_vStage_uid155_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_d_q : std_logic_vector (31 downto 0);
signal ld_rVStage_uid159_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_c_q : std_logic_vector (15 downto 0);
signal ld_vStage_uid161_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_d_q : std_logic_vector (15 downto 0);
signal ld_vCount_uid160_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_e_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid154_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_f_q : std_logic_vector (0 downto 0);
signal ld_vCount_uid146_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_g_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC4_uid229_sinPiZTableGenerator_a_q : std_logic_vector (6 downto 0);
signal ld_lowRangeB_uid239_sinPiZPolyEval_b_to_s2_uid239_uid242_sinPiZPolyEval_a_q : std_logic_vector (0 downto 0);
signal ld_lowRangeB_uid280_pT3_uid244_sinPiZPolyEval_b_to_add0_uid280_uid283_pT3_uid244_sinPiZPolyEval_a_q : std_logic_vector (0 downto 0);
signal ld_yT4_uid249_sinPiZPolyEval_b_to_xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_a_q : std_logic_vector (42 downto 0);
signal ld_reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_1_q_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_b_q : std_logic_vector (26 downto 0);
signal ld_yBottomBits_uid288_pT4_uid250_sinPiZPolyEval_b_to_spad_yBottomBits_uid288_uid290_pT4_uid250_sinPiZPolyEval_a_q : std_logic_vector (17 downto 0);
signal ld_lowRangeB_uid295_pT4_uid250_sinPiZPolyEval_b_to_add0_uid295_uid298_pT4_uid250_sinPiZPolyEval_a_q : std_logic_vector (17 downto 0);
signal ld_reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_1_q_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_b_q : std_logic_vector (26 downto 0);
signal ld_yBottomBits_uid303_pT5_uid256_sinPiZPolyEval_b_to_spad_yBottomBits_uid303_uid305_pT5_uid256_sinPiZPolyEval_a_q : std_logic_vector (24 downto 0);
signal ld_lowRangeB_uid310_pT5_uid256_sinPiZPolyEval_b_to_add0_uid310_uid313_pT5_uid256_sinPiZPolyEval_a_q : std_logic_vector (24 downto 0);
signal ld_mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_a_q : std_logic_vector (19 downto 0);
signal ld_mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_b_q : std_logic_vector (19 downto 0);
signal ld_mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid68_fpCosPiTest_ADD_BitJoin_for_q_a_q : std_logic_vector (88 downto 0);
signal ld_xIn_v_to_xOut_v_outputreg_q : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_reset0 : std_logic;
signal ld_xIn_v_to_xOut_v_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_ir : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_xIn_v_to_xOut_v_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_xIn_v_to_xOut_v_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_xIn_v_to_xOut_v_replace_rdcnt_eq : std_logic;
signal ld_xIn_v_to_xOut_v_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_xIn_v_to_xOut_v_mem_top_q : std_logic_vector (6 downto 0);
signal ld_xIn_v_to_xOut_v_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_xIn_c_to_xOut_c_outputreg_q : std_logic_vector (7 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_reset0 : std_logic;
signal ld_xIn_c_to_xOut_c_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_ir : std_logic_vector (7 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_xIn_c_to_xOut_c_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_inputreg_q : std_logic_vector (78 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_reset0 : std_logic;
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_iq : std_logic_vector (78 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_ia : std_logic_vector (78 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_ir : std_logic_vector (78 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_q : std_logic_vector (78 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_eq : std_logic;
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_wrreg_q : std_logic_vector (4 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_outputreg_q : std_logic_vector (6 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ir : std_logic_vector (6 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_outputreg_q : std_logic_vector (0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0);
signal ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_inputreg_q : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_ir : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_mem_top_q : std_logic_vector (6 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_inputreg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_reset0 : std_logic;
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_ir : std_logic_vector (0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_q : std_logic_vector (0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_eq : std_logic;
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_mem_top_q : std_logic_vector (6 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_iq : std_logic_vector (46 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_ia : std_logic_vector (46 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_ir : std_logic_vector (46 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_q : std_logic_vector (46 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(1 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_i : unsigned(1 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_eq : std_logic;
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (1 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_mem_top_q : std_logic_vector (2 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_reset0 : std_logic;
signal ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_ir : std_logic_vector (14 downto 0);
signal ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_aa : std_logic_vector (1 downto 0);
signal ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_ab : std_logic_vector (1 downto 0);
signal ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_outputreg_q : std_logic_vector (78 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_reset0 : std_logic;
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_iq : std_logic_vector (78 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_ia : std_logic_vector (78 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_ir : std_logic_vector (78 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_q : std_logic_vector (78 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_outputreg_q : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_ir : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_outputreg_q : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_ir : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_outputreg_q : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_ir : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_outputreg_q : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_reset0 : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_iq : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_ia : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_ir : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_q : std_logic_vector (6 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_eq : std_logic;
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(3 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_mem_top_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_outputreg_q : std_logic_vector (25 downto 0);
signal ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (25 downto 0);
signal ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (25 downto 0);
signal ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (25 downto 0);
signal ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (25 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_outputreg_q : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_reset0 : std_logic;
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_ir : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (44 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic;
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_mem_top_q : std_logic_vector (5 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_outputreg_q : std_logic_vector (17 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_reset0 : std_logic;
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_iq : std_logic_vector (17 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_ia : std_logic_vector (17 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_ir : std_logic_vector (17 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_aa : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_ab : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_q : std_logic_vector (17 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_q : std_logic_vector(4 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_i : unsigned(4 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_eq : std_logic;
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdreg_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_mem_top_q : std_logic_vector (5 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_sticky_ena_q : std_logic_vector (0 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_outputreg_q : std_logic_vector (1 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_reset0 : std_logic;
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_ir : std_logic_vector (1 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_aa : std_logic_vector (5 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_ab : std_logic_vector (5 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_q : std_logic_vector(5 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_i : unsigned(5 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_eq : std_logic;
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdreg_q : std_logic_vector (5 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_mem_top_q : std_logic_vector (6 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_sticky_ena_q : std_logic_vector (0 downto 0);
signal pad_o_uid17_uid49_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal pad_half_uid18_uid54_fpCosPiTest_q : std_logic_vector (79 downto 0);
signal spad_yBottomBits_uid288_uid290_pT4_uid250_sinPiZPolyEval_q : std_logic_vector (18 downto 0);
signal pad_yBottomBits_uid288_uid292_pT4_uid250_sinPiZPolyEval_q : std_logic_vector (26 downto 0);
signal spad_yBottomBits_uid303_uid305_pT5_uid256_sinPiZPolyEval_q : std_logic_vector (25 downto 0);
signal pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_q : std_logic_vector (25 downto 0);
signal pad_yBottomBits_uid303_uid307_pT5_uid256_sinPiZPolyEval_q : std_logic_vector (26 downto 0);
signal expHardCase_uid61_fpCosPiTest_a : std_logic_vector(11 downto 0);
signal expHardCase_uid61_fpCosPiTest_b : std_logic_vector(11 downto 0);
signal expHardCase_uid61_fpCosPiTest_o : std_logic_vector (11 downto 0);
signal expHardCase_uid61_fpCosPiTest_q : std_logic_vector (11 downto 0);
signal rndExpUpdate_uid74_uid75_fpCosPiTest_q : std_logic_vector (53 downto 0);
signal expFracComp_uid76_fpCosPiTest_a : std_logic_vector(64 downto 0);
signal expFracComp_uid76_fpCosPiTest_b : std_logic_vector(64 downto 0);
signal expFracComp_uid76_fpCosPiTest_o : std_logic_vector (64 downto 0);
signal expFracComp_uid76_fpCosPiTest_q : std_logic_vector (64 downto 0);
signal fracRPostExc_uid90_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRPostExc_uid90_fpCosPiTest_q : std_logic_vector (51 downto 0);
signal expRPostExc_uid97_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid97_fpCosPiTest_q : std_logic_vector (10 downto 0);
signal leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal memoryC0_uid225_sinPiZTableGenerator_q : std_logic_vector(57 downto 0);
signal memoryC1_uid226_sinPiZTableGenerator_q : std_logic_vector(49 downto 0);
signal memoryC2_uid227_sinPiZTableGenerator_q : std_logic_vector(42 downto 0);
signal sumAHighB_uid241_sinPiZPolyEval_a : std_logic_vector(35 downto 0);
signal sumAHighB_uid241_sinPiZPolyEval_b : std_logic_vector(35 downto 0);
signal sumAHighB_uid241_sinPiZPolyEval_o : std_logic_vector (35 downto 0);
signal sumAHighB_uid241_sinPiZPolyEval_q : std_logic_vector (35 downto 0);
signal ts3_uid247_sinPiZPolyEval_a : std_logic_vector(45 downto 0);
signal ts3_uid247_sinPiZPolyEval_b : std_logic_vector(45 downto 0);
signal ts3_uid247_sinPiZPolyEval_o : std_logic_vector (45 downto 0);
signal ts3_uid247_sinPiZPolyEval_q : std_logic_vector (45 downto 0);
signal ts4_uid253_sinPiZPolyEval_a : std_logic_vector(52 downto 0);
signal ts4_uid253_sinPiZPolyEval_b : std_logic_vector(52 downto 0);
signal ts4_uid253_sinPiZPolyEval_o : std_logic_vector (52 downto 0);
signal ts4_uid253_sinPiZPolyEval_q : std_logic_vector (52 downto 0);
signal ts5_uid259_sinPiZPolyEval_a : std_logic_vector(61 downto 0);
signal ts5_uid259_sinPiZPolyEval_b : std_logic_vector(61 downto 0);
signal ts5_uid259_sinPiZPolyEval_o : std_logic_vector (61 downto 0);
signal ts5_uid259_sinPiZPolyEval_q : std_logic_vector (61 downto 0);
signal sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_q : std_logic_vector (54 downto 0);
signal sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_a : std_logic_vector(54 downto 0);
signal sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_b : std_logic_vector(54 downto 0);
signal sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_o : std_logic_vector (54 downto 0);
signal sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_q : std_logic_vector (54 downto 0);
signal cstHalfwSwFP1_uid19_fpCosPiTest_q : std_logic_vector (79 downto 0);
signal ld_xIn_v_to_xOut_v_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xIn_v_to_xOut_v_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_xIn_v_to_xOut_v_notEnable_a : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_notEnable_q : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (1 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux_q : std_logic_vector (0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (3 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux_q : std_logic_vector (4 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux_q : std_logic_vector (5 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_enaAnd_q : std_logic_vector(0 downto 0);
signal expX_uid6_fpCosPiTest_in : std_logic_vector (62 downto 0);
signal expX_uid6_fpCosPiTest_b : std_logic_vector (10 downto 0);
signal fracX_uid7_fpCosPiTest_in : std_logic_vector (51 downto 0);
signal fracX_uid7_fpCosPiTest_b : std_logic_vector (51 downto 0);
signal expXIsMax_uid26_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal expXIsMax_uid26_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal expXIsMax_uid26_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid28_fpCosPiTest_a : std_logic_vector(51 downto 0);
signal fracXIsZero_uid28_fpCosPiTest_b : std_logic_vector(51 downto 0);
signal fracXIsZero_uid28_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xEvenInt_uid37_fpCosPiTest_a : std_logic_vector(13 downto 0);
signal xEvenInt_uid37_fpCosPiTest_b : std_logic_vector(13 downto 0);
signal xEvenInt_uid37_fpCosPiTest_o : std_logic_vector (13 downto 0);
signal xEvenInt_uid37_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal xEvenInt_uid37_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal cosXIsOne_uid38_fpCosPiTest_a : std_logic_vector(13 downto 0);
signal cosXIsOne_uid38_fpCosPiTest_b : std_logic_vector(13 downto 0);
signal cosXIsOne_uid38_fpCosPiTest_o : std_logic_vector (13 downto 0);
signal cosXIsOne_uid38_fpCosPiTest_cin : std_logic_vector (0 downto 0);
signal cosXIsOne_uid38_fpCosPiTest_c : std_logic_vector (0 downto 0);
signal shiftValFxPX_uid40_fpCosPiTest_a : std_logic_vector(11 downto 0);
signal shiftValFxPX_uid40_fpCosPiTest_b : std_logic_vector(11 downto 0);
signal shiftValFxPX_uid40_fpCosPiTest_o : std_logic_vector (11 downto 0);
signal shiftValFxPX_uid40_fpCosPiTest_q : std_logic_vector (11 downto 0);
signal fxpXFracZero_uid47_fpCosPiTest_a : std_logic_vector(79 downto 0);
signal fxpXFracZero_uid47_fpCosPiTest_b : std_logic_vector(79 downto 0);
signal fxpXFracZero_uid47_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal expXIsZero_uid24_fpCosPiTest_a : std_logic_vector(10 downto 0);
signal expXIsZero_uid24_fpCosPiTest_b : std_logic_vector(10 downto 0);
signal expXIsZero_uid24_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal oMFxpXFrac_uid51_fpCosPiTest_in : std_logic_vector (79 downto 0);
signal oMFxpXFrac_uid51_fpCosPiTest_b : std_logic_vector (79 downto 0);
signal z_uid56_fpCosPiTest_in : std_logic_vector (78 downto 0);
signal z_uid56_fpCosPiTest_b : std_logic_vector (78 downto 0);
signal or_uid95_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal or_uid95_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal or_uid95_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal or_uid95_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid154_lzcZ_uid58_fpCosPiTest_a : std_logic_vector(31 downto 0);
signal vCount_uid154_lzcZ_uid58_fpCosPiTest_b : std_logic_vector(31 downto 0);
signal vCount_uid154_lzcZ_uid58_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal vCount_uid166_lzcZ_uid58_fpCosPiTest_a : std_logic_vector(7 downto 0);
signal vCount_uid166_lzcZ_uid58_fpCosPiTest_b : std_logic_vector(7 downto 0);
signal vCount_uid166_lzcZ_uid58_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid160_lzcZ_uid58_fpCosPiTest_a : std_logic_vector(15 downto 0);
signal vCount_uid160_lzcZ_uid58_fpCosPiTest_b : std_logic_vector(15 downto 0);
signal vCount_uid160_lzcZ_uid58_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal cIncludingRoundingBit_uid246_sinPiZPolyEval_q : std_logic_vector (44 downto 0);
signal cIncludingRoundingBit_uid252_sinPiZPolyEval_q : std_logic_vector (51 downto 0);
signal cIncludingRoundingBit_uid258_sinPiZPolyEval_q : std_logic_vector (60 downto 0);
signal prodXYTruncFR_uid263_pT1_uid232_sinPiZPolyEval_in : std_logic_vector (33 downto 0);
signal prodXYTruncFR_uid263_pT1_uid232_sinPiZPolyEval_b : std_logic_vector (17 downto 0);
signal prodXYTruncFR_uid266_pT2_uid238_sinPiZPolyEval_in : std_logic_vector (53 downto 0);
signal prodXYTruncFR_uid266_pT2_uid238_sinPiZPolyEval_b : std_logic_vector (28 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b0_in : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b0_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b0_in : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b0_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b0_in : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b0_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b0_in : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b0_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b1_in : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b1_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b1_in : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b1_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b1_in : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b1_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b1_in : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b1_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_joined_BJ_1_q : std_logic_vector (107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_joined_BJ_2_q : std_logic_vector (107 downto 0);
signal multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_in : std_logic_vector (36 downto 0);
signal multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_b : std_logic_vector (29 downto 0);
signal multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_b : std_logic_vector (46 downto 0);
signal multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_in : std_logic_vector (54 downto 0);
signal multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_b : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_BitJoin_for_q_q : std_logic_vector (108 downto 0);
signal fxpXFracHalf_uid48_fpCosPiTest_a : std_logic_vector(79 downto 0);
signal fxpXFracHalf_uid48_fpCosPiTest_b : std_logic_vector(79 downto 0);
signal fxpXFracHalf_uid48_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid169_lzcZ_uid58_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid169_lzcZ_uid58_fpCosPiTest_q : std_logic_vector (7 downto 0);
signal leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal zPPolyEval_uid65_fpCosPiTest_in : std_logic_vector (71 downto 0);
signal zPPolyEval_uid65_fpCosPiTest_b : std_logic_vector (44 downto 0);
signal InvCosXIsOne_uid79_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvCosXIsOne_uid79_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvXEvenInt_uid83_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvXEvenInt_uid83_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal xIsHalf_uid85_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal xIsHalf_uid85_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal xIsHalf_uid85_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal xIsHalf_uid85_fpCosPiTest_d : std_logic_vector(0 downto 0);
signal xIsHalf_uid85_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal join_uid96_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal signRComp_uid101_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signRComp_uid101_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signRComp_uid101_fpCosPiTest_c : std_logic_vector(0 downto 0);
signal signRComp_uid101_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid157_lzcZ_uid58_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid157_lzcZ_uid58_fpCosPiTest_q : std_logic_vector (31 downto 0);
signal vStagei_uid163_lzcZ_uid58_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid163_lzcZ_uid58_fpCosPiTest_q : std_logic_vector (15 downto 0);
signal s2_uid239_uid242_sinPiZPolyEval_q : std_logic_vector (36 downto 0);
signal add0_uid280_uid283_pT3_uid244_sinPiZPolyEval_q : std_logic_vector (55 downto 0);
signal xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_in : std_logic_vector (42 downto 0);
signal xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal add0_uid295_uid298_pT4_uid250_sinPiZPolyEval_q : std_logic_vector (72 downto 0);
signal add0_uid310_uid313_pT5_uid256_sinPiZPolyEval_q : std_logic_vector (79 downto 0);
signal ld_xIn_v_to_xOut_v_cmp_a : std_logic_vector(6 downto 0);
signal ld_xIn_v_to_xOut_v_cmp_b : std_logic_vector(6 downto 0);
signal ld_xIn_v_to_xOut_v_cmp_q : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_nor_a : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_nor_b : std_logic_vector(0 downto 0);
signal ld_xIn_v_to_xOut_v_nor_q : std_logic_vector(0 downto 0);
signal alignedZLow_uid60_fpCosPiTest_in : std_logic_vector (78 downto 0);
signal alignedZLow_uid60_fpCosPiTest_b : std_logic_vector (52 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_nor_a : std_logic_vector(0 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_nor_b : std_logic_vector(0 downto 0);
signal ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmp_a : std_logic_vector(6 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmp_b : std_logic_vector(6 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal R_uid104_fpCosPiTest_q : std_logic_vector (63 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmp_a : std_logic_vector(6 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmp_b : std_logic_vector(6 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmp_q : std_logic_vector(0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmp_a : std_logic_vector(2 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmp_b : std_logic_vector(2 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_nor_a : std_logic_vector(0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_nor_b : std_logic_vector(0 downto 0);
signal ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_nor_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_nor_q : std_logic_vector(0 downto 0);
signal yT3_uid243_sinPiZPolyEval_in : std_logic_vector (44 downto 0);
signal yT3_uid243_sinPiZPolyEval_b : std_logic_vector (34 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal yT4_uid249_sinPiZPolyEval_in : std_logic_vector (44 downto 0);
signal yT4_uid249_sinPiZPolyEval_b : std_logic_vector (42 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmp_a : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmp_b : std_logic_vector(4 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_in : std_logic_vector (44 downto 0);
signal xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmp_a : std_logic_vector(5 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmp_b : std_logic_vector(5 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0);
signal ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmp_a : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmp_b : std_logic_vector(5 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_nor_a : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_nor_b : std_logic_vector(0 downto 0);
signal ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_nor_q : std_logic_vector(0 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmp_a : std_logic_vector(6 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmp_b : std_logic_vector(6 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_nor_a : std_logic_vector(0 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_nor_b : std_logic_vector(0 downto 0);
signal ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_nor_q : std_logic_vector(0 downto 0);
signal expP_uid62_fpCosPiTest_in : std_logic_vector (10 downto 0);
signal expP_uid62_fpCosPiTest_b : std_logic_vector (10 downto 0);
signal fracRComp_uid77_fpCosPiTest_in : std_logic_vector (52 downto 0);
signal fracRComp_uid77_fpCosPiTest_b : std_logic_vector (51 downto 0);
signal expRComp_uid78_fpCosPiTest_in : std_logic_vector (63 downto 0);
signal expRComp_uid78_fpCosPiTest_b : std_logic_vector (10 downto 0);
signal FxpX80_uid44_fpCosPiTest_in : std_logic_vector (80 downto 0);
signal FxpX80_uid44_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal fxpXFrac_uid45_fpCosPiTest_in : std_logic_vector (79 downto 0);
signal fxpXFrac_uid45_fpCosPiTest_b : std_logic_vector (79 downto 0);
signal s3_uid248_sinPiZPolyEval_in : std_logic_vector (45 downto 0);
signal s3_uid248_sinPiZPolyEval_b : std_logic_vector (44 downto 0);
signal s4_uid254_sinPiZPolyEval_in : std_logic_vector (52 downto 0);
signal s4_uid254_sinPiZPolyEval_b : std_logic_vector (51 downto 0);
signal s5_uid260_sinPiZPolyEval_in : std_logic_vector (61 downto 0);
signal s5_uid260_sinPiZPolyEval_b : std_logic_vector (60 downto 0);
signal oFracX_uid39_uid39_fpCosPiTest_q : std_logic_vector (52 downto 0);
signal And2ExpXIsMaxFracXIsZero_uid29_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal And2ExpXIsMaxFracXIsZero_uid29_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal And2ExpXIsMaxFracXIsZero_uid29_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid30_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid30_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal fxpShifterBits_uid42_fpCosPiTest_in : std_logic_vector (6 downto 0);
signal fxpShifterBits_uid42_fpCosPiTest_b : std_logic_vector (6 downto 0);
signal And2FxpXFracZeroInvCosXIsOne_uid80_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal And2FxpXFracZeroInvCosXIsOne_uid80_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal And2FxpXFracZeroInvCosXIsOne_uid80_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid34_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid34_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal zAddr_uid64_fpCosPiTest_in : std_logic_vector (78 downto 0);
signal zAddr_uid64_fpCosPiTest_b : std_logic_vector (6 downto 0);
signal rVStage_uid145_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (78 downto 0);
signal rVStage_uid145_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (63 downto 0);
signal vStage_uid148_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (14 downto 0);
signal vStage_uid148_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (14 downto 0);
signal X46dto0_uid189_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (46 downto 0);
signal X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (46 downto 0);
signal lowRangeB_uid233_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid233_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid234_sinPiZPolyEval_in : std_logic_vector (17 downto 0);
signal highBBits_uid234_sinPiZPolyEval_b : std_logic_vector (16 downto 0);
signal lowRangeB_uid239_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid239_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid240_sinPiZPolyEval_in : std_logic_vector (28 downto 0);
signal highBBits_uid240_sinPiZPolyEval_b : std_logic_vector (27 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_joined_BJ_0_q : std_logic_vector (107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_a : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_b : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_c : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_q : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAB_a : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAB_b : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAB_q : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_andBC_a : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_andBC_b : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_andBC_q : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAC_a : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAC_b : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAC_q : std_logic_vector(107 downto 0);
signal lowRangeB_uid280_pT3_uid244_sinPiZPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid280_pT3_uid244_sinPiZPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid281_pT3_uid244_sinPiZPolyEval_in : std_logic_vector (29 downto 0);
signal highBBits_uid281_pT3_uid244_sinPiZPolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid295_pT4_uid250_sinPiZPolyEval_in : std_logic_vector (17 downto 0);
signal lowRangeB_uid295_pT4_uid250_sinPiZPolyEval_b : std_logic_vector (17 downto 0);
signal highBBits_uid296_pT4_uid250_sinPiZPolyEval_in : std_logic_vector (46 downto 0);
signal highBBits_uid296_pT4_uid250_sinPiZPolyEval_b : std_logic_vector (28 downto 0);
signal lowRangeB_uid310_pT5_uid256_sinPiZPolyEval_in : std_logic_vector (24 downto 0);
signal lowRangeB_uid310_pT5_uid256_sinPiZPolyEval_b : std_logic_vector (24 downto 0);
signal highBBits_uid311_pT5_uid256_sinPiZPolyEval_in : std_logic_vector (53 downto 0);
signal highBBits_uid311_pT5_uid256_sinPiZPolyEval_b : std_logic_vector (28 downto 0);
signal normBit_uid69_fpCosPiTest_in : std_logic_vector (106 downto 0);
signal normBit_uid69_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal highRes_uid70_fpCosPiTest_in : std_logic_vector (105 downto 0);
signal highRes_uid70_fpCosPiTest_b : std_logic_vector (52 downto 0);
signal lowRes_uid71_fpCosPiTest_in : std_logic_vector (104 downto 0);
signal lowRes_uid71_fpCosPiTest_b : std_logic_vector (52 downto 0);
signal InvFxpXFracHalf_uid102_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvFxpXFracHalf_uid102_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid171_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal rVStage_uid171_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal vStage_uid173_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal vStage_uid173_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (3 downto 0);
signal LeftShiftStage070dto0_uid198_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (70 downto 0);
signal LeftShiftStage070dto0_uid198_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (70 downto 0);
signal LeftShiftStage062dto0_uid201_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (62 downto 0);
signal LeftShiftStage062dto0_uid201_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (62 downto 0);
signal LeftShiftStage054dto0_uid204_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (54 downto 0);
signal LeftShiftStage054dto0_uid204_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (54 downto 0);
signal yT1_uid231_sinPiZPolyEval_in : std_logic_vector (44 downto 0);
signal yT1_uid231_sinPiZPolyEval_b : std_logic_vector (16 downto 0);
signal yT2_uid237_sinPiZPolyEval_in : std_logic_vector (44 downto 0);
signal yT2_uid237_sinPiZPolyEval_b : std_logic_vector (25 downto 0);
signal xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_in : std_logic_vector (17 downto 0);
signal xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b : std_logic_vector (17 downto 0);
signal signR_uid103_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal signR_uid103_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal signR_uid103_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid159_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal rVStage_uid159_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal vStage_uid161_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal vStage_uid161_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (15 downto 0);
signal rVStage_uid165_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (15 downto 0);
signal rVStage_uid165_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal vStage_uid167_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (7 downto 0);
signal vStage_uid167_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (7 downto 0);
signal yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_in : std_logic_vector (36 downto 0);
signal yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid272_pT3_uid244_sinPiZPolyEval_in : std_logic_vector (9 downto 0);
signal yBottomBits_uid272_pT3_uid244_sinPiZPolyEval_b : std_logic_vector (9 downto 0);
signal yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_in : std_logic_vector (36 downto 0);
signal yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_b : std_logic_vector (17 downto 0);
signal R_uid284_pT3_uid244_sinPiZPolyEval_in : std_logic_vector (54 downto 0);
signal R_uid284_pT3_uid244_sinPiZPolyEval_b : std_logic_vector (36 downto 0);
signal R_uid299_pT4_uid250_sinPiZPolyEval_in : std_logic_vector (71 downto 0);
signal R_uid299_pT4_uid250_sinPiZPolyEval_b : std_logic_vector (45 downto 0);
signal R_uid314_pT5_uid256_sinPiZPolyEval_in : std_logic_vector (78 downto 0);
signal R_uid314_pT5_uid256_sinPiZPolyEval_b : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a_0_in : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a_0_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a_1_in : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_a_1_b : std_logic_vector (26 downto 0);
signal xTop27Bits_uid268_pT3_uid244_sinPiZPolyEval_in : std_logic_vector (34 downto 0);
signal xTop27Bits_uid268_pT3_uid244_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal xTop18Bits_uid271_pT3_uid244_sinPiZPolyEval_in : std_logic_vector (34 downto 0);
signal xTop18Bits_uid271_pT3_uid244_sinPiZPolyEval_b : std_logic_vector (17 downto 0);
signal xBottomBits_uid273_pT3_uid244_sinPiZPolyEval_in : std_logic_vector (7 downto 0);
signal xBottomBits_uid273_pT3_uid244_sinPiZPolyEval_b : std_logic_vector (7 downto 0);
signal xBottomBits_uid289_pT4_uid250_sinPiZPolyEval_in : std_logic_vector (15 downto 0);
signal xBottomBits_uid289_pT4_uid250_sinPiZPolyEval_b : std_logic_vector (15 downto 0);
signal FxpXFrac79_uid46_fpCosPiTest_in : std_logic_vector (79 downto 0);
signal FxpXFrac79_uid46_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_in : std_logic_vector (44 downto 0);
signal yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid288_pT4_uid250_sinPiZPolyEval_in : std_logic_vector (17 downto 0);
signal yBottomBits_uid288_pT4_uid250_sinPiZPolyEval_b : std_logic_vector (17 downto 0);
signal yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_in : std_logic_vector (51 downto 0);
signal yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_b : std_logic_vector (26 downto 0);
signal yBottomBits_uid303_pT5_uid256_sinPiZPolyEval_in : std_logic_vector (24 downto 0);
signal yBottomBits_uid303_pT5_uid256_sinPiZPolyEval_b : std_logic_vector (24 downto 0);
signal fxpSinRes_uid67_fpCosPiTest_in : std_logic_vector (58 downto 0);
signal fxpSinRes_uid67_fpCosPiTest_b : std_logic_vector (53 downto 0);
signal oFracXExt_uid41_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal InvAnd2ExpXIsMaxFracXIsZero_uid33_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvAnd2ExpXIsMaxFracXIsZero_uid33_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal And2ExpXIsMaxInvFracXIsZero_uid31_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal And2ExpXIsMaxInvFracXIsZero_uid31_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal And2ExpXIsMaxInvFracXIsZero_uid31_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStageSel6Dto5_uid114_fxpX_uid43_fpCosPiTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid114_fxpX_uid43_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid125_fxpX_uid43_fpCosPiTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid125_fxpX_uid43_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid136_fxpX_uid43_fpCosPiTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid136_fxpX_uid43_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid35_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid35_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid35_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vCount_uid146_lzcZ_uid58_fpCosPiTest_a : std_logic_vector(63 downto 0);
signal vCount_uid146_lzcZ_uid58_fpCosPiTest_b : std_logic_vector(63 downto 0);
signal vCount_uid146_lzcZ_uid58_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal cStage_uid149_lzcZ_uid58_fpCosPiTest_q : std_logic_vector (63 downto 0);
signal sumAHighB_uid235_sinPiZPolyEval_a : std_logic_vector(26 downto 0);
signal sumAHighB_uid235_sinPiZPolyEval_b : std_logic_vector(26 downto 0);
signal sumAHighB_uid235_sinPiZPolyEval_o : std_logic_vector (26 downto 0);
signal sumAHighB_uid235_sinPiZPolyEval_q : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_BitExpansion_for_a_q : std_logic_vector (108 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_a : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_b : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_c : std_logic_vector(107 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_q : std_logic_vector(107 downto 0);
signal fracRCompPreRnd_uid72_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal fracRCompPreRnd_uid72_fpCosPiTest_q : std_logic_vector (52 downto 0);
signal vCount_uid172_lzcZ_uid58_fpCosPiTest_a : std_logic_vector(3 downto 0);
signal vCount_uid172_lzcZ_uid58_fpCosPiTest_b : std_logic_vector(3 downto 0);
signal vCount_uid172_lzcZ_uid58_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid175_lzcZ_uid58_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid175_lzcZ_uid58_fpCosPiTest_q : std_logic_vector (3 downto 0);
signal leftShiftStage1Idx1_uid199_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal leftShiftStage1Idx2_uid202_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal leftShiftStage1Idx3_uid205_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal spad_yBottomBits_uid272_uid275_pT3_uid244_sinPiZPolyEval_q : std_logic_vector (10 downto 0);
signal pad_xBottomBits_uid273_uid276_pT3_uid244_sinPiZPolyEval_q : std_logic_vector (16 downto 0);
signal pad_xBottomBits_uid289_uid291_pT4_uid250_sinPiZPolyEval_q : std_logic_vector (25 downto 0);
signal Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_b_0_in : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_b_0_b : std_logic_vector (26 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_b_1_in : std_logic_vector (53 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_b_1_b : std_logic_vector (26 downto 0);
signal X48dto0_uid108_fxpX_uid43_fpCosPiTest_in : std_logic_vector (48 downto 0);
signal X48dto0_uid108_fxpX_uid43_fpCosPiTest_b : std_logic_vector (48 downto 0);
signal X16dto0_uid111_fxpX_uid43_fpCosPiTest_in : std_logic_vector (16 downto 0);
signal X16dto0_uid111_fxpX_uid43_fpCosPiTest_b : std_logic_vector (16 downto 0);
signal InvAnd2ExpXIsMaxInvFracXIsZero_uid32_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal InvAnd2ExpXIsMaxInvFracXIsZero_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal excRNaN_uid86_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal excRNaN_uid86_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal excRNaN_uid86_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid151_lzcZ_uid58_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid151_lzcZ_uid58_fpCosPiTest_q : std_logic_vector (63 downto 0);
signal s1_uid233_uid236_sinPiZPolyEval_q : std_logic_vector (27 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_in : std_logic_vector (108 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_b : std_logic_vector (88 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_c : std_logic_vector (19 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_comp_0_out1_lsb_BS_in : std_logic_vector (106 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_comp_0_out1_lsb_BS_b : std_logic_vector (106 downto 0);
signal expFracPreRnd_uid73_uid73_fpCosPiTest_q : std_logic_vector (63 downto 0);
signal rVStage_uid177_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (3 downto 0);
signal rVStage_uid177_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal vStage_uid179_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal vStage_uid179_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal pad_yBottomBits_uid272_uid277_pT3_uid244_sinPiZPolyEval_q : std_logic_vector (17 downto 0);
signal leftShiftStage0Idx1_uid109_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal leftShiftStage0Idx2_uid112_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal Or2ZeroExcRNaN_uid94_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal Or2ZeroExcRNaN_uid94_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal Or2ZeroExcRNaN_uid94_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal rVStage_uid153_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (63 downto 0);
signal rVStage_uid153_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal vStage_uid155_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (31 downto 0);
signal vStage_uid155_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (31 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_comp_0_out1_BJ_q : std_logic_vector (107 downto 0);
signal vCount_uid178_lzcZ_uid58_fpCosPiTest_a : std_logic_vector(1 downto 0);
signal vCount_uid178_lzcZ_uid58_fpCosPiTest_b : std_logic_vector(1 downto 0);
signal vCount_uid178_lzcZ_uid58_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal vStagei_uid181_lzcZ_uid58_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal vStagei_uid181_lzcZ_uid58_fpCosPiTest_q : std_logic_vector (1 downto 0);
signal LeftShiftStage176dto0_uid209_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (76 downto 0);
signal LeftShiftStage176dto0_uid209_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (76 downto 0);
signal LeftShiftStage174dto0_uid212_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid212_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (74 downto 0);
signal LeftShiftStage172dto0_uid215_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (72 downto 0);
signal LeftShiftStage172dto0_uid215_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (72 downto 0);
signal leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_BitExpansion_for_b_q : std_logic_vector (108 downto 0);
signal rVStage_uid183_lzcZ_uid58_fpCosPiTest_in : std_logic_vector (1 downto 0);
signal rVStage_uid183_lzcZ_uid58_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage2Idx1_uid210_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal leftShiftStage2Idx2_uid213_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal leftShiftStage2Idx3_uid216_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal LeftShiftStage072dto0_uid117_fxpX_uid43_fpCosPiTest_in : std_logic_vector (72 downto 0);
signal LeftShiftStage072dto0_uid117_fxpX_uid43_fpCosPiTest_b : std_logic_vector (72 downto 0);
signal LeftShiftStage064dto0_uid120_fxpX_uid43_fpCosPiTest_in : std_logic_vector (64 downto 0);
signal LeftShiftStage064dto0_uid120_fxpX_uid43_fpCosPiTest_b : std_logic_vector (64 downto 0);
signal LeftShiftStage056dto0_uid123_fxpX_uid43_fpCosPiTest_in : std_logic_vector (56 downto 0);
signal LeftShiftStage056dto0_uid123_fxpX_uid43_fpCosPiTest_b : std_logic_vector (56 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_in : std_logic_vector (108 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_b : std_logic_vector (88 downto 0);
signal mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_c : std_logic_vector (19 downto 0);
signal vCount_uid184_lzcZ_uid58_fpCosPiTest_a : std_logic_vector(0 downto 0);
signal vCount_uid184_lzcZ_uid58_fpCosPiTest_b : std_logic_vector(0 downto 0);
signal vCount_uid184_lzcZ_uid58_fpCosPiTest_q : std_logic_vector(0 downto 0);
signal leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal leftShiftStage1Idx1_uid118_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal leftShiftStage1Idx2_uid121_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal leftShiftStage1Idx3_uid124_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal r_uid185_lzcZ_uid58_fpCosPiTest_q : std_logic_vector (6 downto 0);
signal LeftShiftStage277dto0_uid220_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (77 downto 0);
signal LeftShiftStage277dto0_uid220_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (77 downto 0);
signal leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (6 downto 0);
signal leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (4 downto 0);
signal leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (2 downto 0);
signal leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (1 downto 0);
signal leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_in : std_logic_vector (0 downto 0);
signal leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_b : std_logic_vector (0 downto 0);
signal leftShiftStage3Idx1_uid221_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal LeftShiftStage178dto0_uid128_fxpX_uid43_fpCosPiTest_in : std_logic_vector (78 downto 0);
signal LeftShiftStage178dto0_uid128_fxpX_uid43_fpCosPiTest_b : std_logic_vector (78 downto 0);
signal LeftShiftStage176dto0_uid131_fxpX_uid43_fpCosPiTest_in : std_logic_vector (76 downto 0);
signal LeftShiftStage176dto0_uid131_fxpX_uid43_fpCosPiTest_b : std_logic_vector (76 downto 0);
signal LeftShiftStage174dto0_uid134_fxpX_uid43_fpCosPiTest_in : std_logic_vector (74 downto 0);
signal LeftShiftStage174dto0_uid134_fxpX_uid43_fpCosPiTest_b : std_logic_vector (74 downto 0);
signal leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_s : std_logic_vector (0 downto 0);
signal leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q : std_logic_vector (78 downto 0);
signal leftShiftStage2Idx1_uid129_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal leftShiftStage2Idx2_uid132_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal leftShiftStage2Idx3_uid135_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_s : std_logic_vector (1 downto 0);
signal leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
signal LeftShiftStage279dto0_uid139_fxpX_uid43_fpCosPiTest_in : std_logic_vector (79 downto 0);
signal LeftShiftStage279dto0_uid139_fxpX_uid43_fpCosPiTest_b : std_logic_vector (79 downto 0);
signal leftShiftStage3Idx1_uid140_fxpX_uid43_fpCosPiTest_q : std_logic_vector (80 downto 0);
begin
--ld_xIn_v_to_xOut_v_notEnable(LOGICAL,852)
ld_xIn_v_to_xOut_v_notEnable_a <= VCC_q;
ld_xIn_v_to_xOut_v_notEnable_q <= not ld_xIn_v_to_xOut_v_notEnable_a;
--ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_nor(LOGICAL,942)
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_nor_b <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_sticky_ena_q;
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_nor_q <= not (ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_nor_a or ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_nor_b);
--ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_mem_top(CONSTANT,938)
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_mem_top_q <= "0100101";
--ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmp(LOGICAL,939)
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmp_a <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_mem_top_q;
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux_q);
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmp_q <= "1" when ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmp_a = ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmp_b else "0";
--ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmpReg(REG,940)
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmpReg_q <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmp_q;
END IF;
END PROCESS;
--ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_sticky_ena(REG,943)
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_nor_q = "1") THEN
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_sticky_ena_q <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_enaAnd(LOGICAL,944)
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_enaAnd_a <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_sticky_ena_q;
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_enaAnd_b <= VCC_q;
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_enaAnd_q <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_enaAnd_a and ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_enaAnd_b;
--LeftShiftStage174dto0_uid134_fxpX_uid43_fpCosPiTest(BITSELECT,133)@0
LeftShiftStage174dto0_uid134_fxpX_uid43_fpCosPiTest_in <= leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_q(74 downto 0);
LeftShiftStage174dto0_uid134_fxpX_uid43_fpCosPiTest_b <= LeftShiftStage174dto0_uid134_fxpX_uid43_fpCosPiTest_in(74 downto 0);
--leftShiftStage2Idx3Pad6_uid133_fxpX_uid43_fpCosPiTest(CONSTANT,132)
leftShiftStage2Idx3Pad6_uid133_fxpX_uid43_fpCosPiTest_q <= "000000";
--leftShiftStage2Idx3_uid135_fxpX_uid43_fpCosPiTest(BITJOIN,134)@0
leftShiftStage2Idx3_uid135_fxpX_uid43_fpCosPiTest_q <= LeftShiftStage174dto0_uid134_fxpX_uid43_fpCosPiTest_b & leftShiftStage2Idx3Pad6_uid133_fxpX_uid43_fpCosPiTest_q;
--LeftShiftStage176dto0_uid131_fxpX_uid43_fpCosPiTest(BITSELECT,130)@0
LeftShiftStage176dto0_uid131_fxpX_uid43_fpCosPiTest_in <= leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_q(76 downto 0);
LeftShiftStage176dto0_uid131_fxpX_uid43_fpCosPiTest_b <= LeftShiftStage176dto0_uid131_fxpX_uid43_fpCosPiTest_in(76 downto 0);
--leftShiftStage2Idx2Pad4_uid130_fxpX_uid43_fpCosPiTest(CONSTANT,129)
leftShiftStage2Idx2Pad4_uid130_fxpX_uid43_fpCosPiTest_q <= "0000";
--leftShiftStage2Idx2_uid132_fxpX_uid43_fpCosPiTest(BITJOIN,131)@0
leftShiftStage2Idx2_uid132_fxpX_uid43_fpCosPiTest_q <= LeftShiftStage176dto0_uid131_fxpX_uid43_fpCosPiTest_b & leftShiftStage2Idx2Pad4_uid130_fxpX_uid43_fpCosPiTest_q;
--LeftShiftStage178dto0_uid128_fxpX_uid43_fpCosPiTest(BITSELECT,127)@0
LeftShiftStage178dto0_uid128_fxpX_uid43_fpCosPiTest_in <= leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_q(78 downto 0);
LeftShiftStage178dto0_uid128_fxpX_uid43_fpCosPiTest_b <= LeftShiftStage178dto0_uid128_fxpX_uid43_fpCosPiTest_in(78 downto 0);
--leftShiftStage2Idx1Pad2_uid127_fxpX_uid43_fpCosPiTest(CONSTANT,126)
leftShiftStage2Idx1Pad2_uid127_fxpX_uid43_fpCosPiTest_q <= "00";
--leftShiftStage2Idx1_uid129_fxpX_uid43_fpCosPiTest(BITJOIN,128)@0
leftShiftStage2Idx1_uid129_fxpX_uid43_fpCosPiTest_q <= LeftShiftStage178dto0_uid128_fxpX_uid43_fpCosPiTest_b & leftShiftStage2Idx1Pad2_uid127_fxpX_uid43_fpCosPiTest_q;
--LeftShiftStage056dto0_uid123_fxpX_uid43_fpCosPiTest(BITSELECT,122)@0
LeftShiftStage056dto0_uid123_fxpX_uid43_fpCosPiTest_in <= leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_q(56 downto 0);
LeftShiftStage056dto0_uid123_fxpX_uid43_fpCosPiTest_b <= LeftShiftStage056dto0_uid123_fxpX_uid43_fpCosPiTest_in(56 downto 0);
--leftShiftStage1Idx3Pad24_uid122_fxpX_uid43_fpCosPiTest(CONSTANT,121)
leftShiftStage1Idx3Pad24_uid122_fxpX_uid43_fpCosPiTest_q <= "000000000000000000000000";
--leftShiftStage1Idx3_uid124_fxpX_uid43_fpCosPiTest(BITJOIN,123)@0
leftShiftStage1Idx3_uid124_fxpX_uid43_fpCosPiTest_q <= LeftShiftStage056dto0_uid123_fxpX_uid43_fpCosPiTest_b & leftShiftStage1Idx3Pad24_uid122_fxpX_uid43_fpCosPiTest_q;
--LeftShiftStage064dto0_uid120_fxpX_uid43_fpCosPiTest(BITSELECT,119)@0
LeftShiftStage064dto0_uid120_fxpX_uid43_fpCosPiTest_in <= leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_q(64 downto 0);
LeftShiftStage064dto0_uid120_fxpX_uid43_fpCosPiTest_b <= LeftShiftStage064dto0_uid120_fxpX_uid43_fpCosPiTest_in(64 downto 0);
--leftShiftStage1Idx2Pad16_uid119_fxpX_uid43_fpCosPiTest(CONSTANT,118)
leftShiftStage1Idx2Pad16_uid119_fxpX_uid43_fpCosPiTest_q <= "0000000000000000";
--leftShiftStage1Idx2_uid121_fxpX_uid43_fpCosPiTest(BITJOIN,120)@0
leftShiftStage1Idx2_uid121_fxpX_uid43_fpCosPiTest_q <= LeftShiftStage064dto0_uid120_fxpX_uid43_fpCosPiTest_b & leftShiftStage1Idx2Pad16_uid119_fxpX_uid43_fpCosPiTest_q;
--LeftShiftStage072dto0_uid117_fxpX_uid43_fpCosPiTest(BITSELECT,116)@0
LeftShiftStage072dto0_uid117_fxpX_uid43_fpCosPiTest_in <= leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_q(72 downto 0);
LeftShiftStage072dto0_uid117_fxpX_uid43_fpCosPiTest_b <= LeftShiftStage072dto0_uid117_fxpX_uid43_fpCosPiTest_in(72 downto 0);
--leftShiftStage1Idx1Pad8_uid116_fxpX_uid43_fpCosPiTest(CONSTANT,115)
leftShiftStage1Idx1Pad8_uid116_fxpX_uid43_fpCosPiTest_q <= "00000000";
--leftShiftStage1Idx1_uid118_fxpX_uid43_fpCosPiTest(BITJOIN,117)@0
leftShiftStage1Idx1_uid118_fxpX_uid43_fpCosPiTest_q <= LeftShiftStage072dto0_uid117_fxpX_uid43_fpCosPiTest_b & leftShiftStage1Idx1Pad8_uid116_fxpX_uid43_fpCosPiTest_q;
--leftShiftStage0Idx3_uid113_fxpX_uid43_fpCosPiTest(CONSTANT,112)
leftShiftStage0Idx3_uid113_fxpX_uid43_fpCosPiTest_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000";
--X16dto0_uid111_fxpX_uid43_fpCosPiTest(BITSELECT,110)@0
X16dto0_uid111_fxpX_uid43_fpCosPiTest_in <= oFracXExt_uid41_fpCosPiTest_q(16 downto 0);
X16dto0_uid111_fxpX_uid43_fpCosPiTest_b <= X16dto0_uid111_fxpX_uid43_fpCosPiTest_in(16 downto 0);
--leftShiftStage0Idx2Pad64_uid110_fxpX_uid43_fpCosPiTest(CONSTANT,109)
leftShiftStage0Idx2Pad64_uid110_fxpX_uid43_fpCosPiTest_q <= "0000000000000000000000000000000000000000000000000000000000000000";
--leftShiftStage0Idx2_uid112_fxpX_uid43_fpCosPiTest(BITJOIN,111)@0
leftShiftStage0Idx2_uid112_fxpX_uid43_fpCosPiTest_q <= X16dto0_uid111_fxpX_uid43_fpCosPiTest_b & leftShiftStage0Idx2Pad64_uid110_fxpX_uid43_fpCosPiTest_q;
--X48dto0_uid108_fxpX_uid43_fpCosPiTest(BITSELECT,107)@0
X48dto0_uid108_fxpX_uid43_fpCosPiTest_in <= oFracXExt_uid41_fpCosPiTest_q(48 downto 0);
X48dto0_uid108_fxpX_uid43_fpCosPiTest_b <= X48dto0_uid108_fxpX_uid43_fpCosPiTest_in(48 downto 0);
--leftShiftStage0Idx1Pad32_uid107_fxpX_uid43_fpCosPiTest(CONSTANT,106)
leftShiftStage0Idx1Pad32_uid107_fxpX_uid43_fpCosPiTest_q <= "00000000000000000000000000000000";
--leftShiftStage0Idx1_uid109_fxpX_uid43_fpCosPiTest(BITJOIN,108)@0
leftShiftStage0Idx1_uid109_fxpX_uid43_fpCosPiTest_q <= X48dto0_uid108_fxpX_uid43_fpCosPiTest_b & leftShiftStage0Idx1Pad32_uid107_fxpX_uid43_fpCosPiTest_q;
--cst01pWShift_uid15_fpCosPiTest(CONSTANT,14)
cst01pWShift_uid15_fpCosPiTest_q <= "0000000000000000000000000000";
--xIn(PORTIN,3)@0
--fracX_uid7_fpCosPiTest(BITSELECT,6)@0
fracX_uid7_fpCosPiTest_in <= xIn_0(51 downto 0);
fracX_uid7_fpCosPiTest_b <= fracX_uid7_fpCosPiTest_in(51 downto 0);
--oFracX_uid39_uid39_fpCosPiTest(BITJOIN,38)@0
oFracX_uid39_uid39_fpCosPiTest_q <= VCC_q & fracX_uid7_fpCosPiTest_b;
--oFracXExt_uid41_fpCosPiTest(BITJOIN,40)@0
oFracXExt_uid41_fpCosPiTest_q <= cst01pWShift_uid15_fpCosPiTest_q & oFracX_uid39_uid39_fpCosPiTest_q;
--biasMwShiftMO_uid14_fpCosPiTest(CONSTANT,13)
biasMwShiftMO_uid14_fpCosPiTest_q <= "01111100011";
--expX_uid6_fpCosPiTest(BITSELECT,5)@0
expX_uid6_fpCosPiTest_in <= xIn_0(62 downto 0);
expX_uid6_fpCosPiTest_b <= expX_uid6_fpCosPiTest_in(62 downto 52);
--shiftValFxPX_uid40_fpCosPiTest(SUB,39)@0
shiftValFxPX_uid40_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid6_fpCosPiTest_b);
shiftValFxPX_uid40_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & biasMwShiftMO_uid14_fpCosPiTest_q);
shiftValFxPX_uid40_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValFxPX_uid40_fpCosPiTest_a) - UNSIGNED(shiftValFxPX_uid40_fpCosPiTest_b));
shiftValFxPX_uid40_fpCosPiTest_q <= shiftValFxPX_uid40_fpCosPiTest_o(11 downto 0);
--fxpShifterBits_uid42_fpCosPiTest(BITSELECT,41)@0
fxpShifterBits_uid42_fpCosPiTest_in <= shiftValFxPX_uid40_fpCosPiTest_q(6 downto 0);
fxpShifterBits_uid42_fpCosPiTest_b <= fxpShifterBits_uid42_fpCosPiTest_in(6 downto 0);
--leftShiftStageSel6Dto5_uid114_fxpX_uid43_fpCosPiTest(BITSELECT,113)@0
leftShiftStageSel6Dto5_uid114_fxpX_uid43_fpCosPiTest_in <= fxpShifterBits_uid42_fpCosPiTest_b;
leftShiftStageSel6Dto5_uid114_fxpX_uid43_fpCosPiTest_b <= leftShiftStageSel6Dto5_uid114_fxpX_uid43_fpCosPiTest_in(6 downto 5);
--leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest(MUX,114)@0
leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_s <= leftShiftStageSel6Dto5_uid114_fxpX_uid43_fpCosPiTest_b;
leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest: PROCESS (leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_s, oFracXExt_uid41_fpCosPiTest_q, leftShiftStage0Idx1_uid109_fxpX_uid43_fpCosPiTest_q, leftShiftStage0Idx2_uid112_fxpX_uid43_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_q <= oFracXExt_uid41_fpCosPiTest_q;
WHEN "01" => leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_q <= leftShiftStage0Idx1_uid109_fxpX_uid43_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_q <= leftShiftStage0Idx2_uid112_fxpX_uid43_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_q <= leftShiftStage0Idx3_uid113_fxpX_uid43_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel4Dto3_uid125_fxpX_uid43_fpCosPiTest(BITSELECT,124)@0
leftShiftStageSel4Dto3_uid125_fxpX_uid43_fpCosPiTest_in <= fxpShifterBits_uid42_fpCosPiTest_b(4 downto 0);
leftShiftStageSel4Dto3_uid125_fxpX_uid43_fpCosPiTest_b <= leftShiftStageSel4Dto3_uid125_fxpX_uid43_fpCosPiTest_in(4 downto 3);
--leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest(MUX,125)@0
leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_s <= leftShiftStageSel4Dto3_uid125_fxpX_uid43_fpCosPiTest_b;
leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest: PROCESS (leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_s, leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_q, leftShiftStage1Idx1_uid118_fxpX_uid43_fpCosPiTest_q, leftShiftStage1Idx2_uid121_fxpX_uid43_fpCosPiTest_q, leftShiftStage1Idx3_uid124_fxpX_uid43_fpCosPiTest_q)
BEGIN
CASE leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_q <= leftShiftStage0_uid115_fxpX_uid43_fpCosPiTest_q;
WHEN "01" => leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_q <= leftShiftStage1Idx1_uid118_fxpX_uid43_fpCosPiTest_q;
WHEN "10" => leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_q <= leftShiftStage1Idx2_uid121_fxpX_uid43_fpCosPiTest_q;
WHEN "11" => leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_q <= leftShiftStage1Idx3_uid124_fxpX_uid43_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel2Dto1_uid136_fxpX_uid43_fpCosPiTest(BITSELECT,135)@0
leftShiftStageSel2Dto1_uid136_fxpX_uid43_fpCosPiTest_in <= fxpShifterBits_uid42_fpCosPiTest_b(2 downto 0);
leftShiftStageSel2Dto1_uid136_fxpX_uid43_fpCosPiTest_b <= leftShiftStageSel2Dto1_uid136_fxpX_uid43_fpCosPiTest_in(2 downto 1);
--leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest(MUX,136)@0
leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_s <= leftShiftStageSel2Dto1_uid136_fxpX_uid43_fpCosPiTest_b;
leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest: PROCESS (leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_s, leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_q, leftShiftStage2Idx1_uid129_fxpX_uid43_fpCosPiTest_q, leftShiftStage2Idx2_uid132_fxpX_uid43_fpCosPiTest_q, leftShiftStage2Idx3_uid135_fxpX_uid43_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_q <= leftShiftStage1_uid126_fxpX_uid43_fpCosPiTest_q;
WHEN "01" => leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_q <= leftShiftStage2Idx1_uid129_fxpX_uid43_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_q <= leftShiftStage2Idx2_uid132_fxpX_uid43_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_q <= leftShiftStage2Idx3_uid135_fxpX_uid43_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--LeftShiftStage279dto0_uid139_fxpX_uid43_fpCosPiTest(BITSELECT,138)@0
LeftShiftStage279dto0_uid139_fxpX_uid43_fpCosPiTest_in <= leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_q(79 downto 0);
LeftShiftStage279dto0_uid139_fxpX_uid43_fpCosPiTest_b <= LeftShiftStage279dto0_uid139_fxpX_uid43_fpCosPiTest_in(79 downto 0);
--GND(CONSTANT,0)
GND_q <= "0";
--leftShiftStage3Idx1_uid140_fxpX_uid43_fpCosPiTest(BITJOIN,139)@0
leftShiftStage3Idx1_uid140_fxpX_uid43_fpCosPiTest_q <= LeftShiftStage279dto0_uid139_fxpX_uid43_fpCosPiTest_b & GND_q;
--reg_leftShiftStage3Idx1_uid140_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_3(REG,356)@0
reg_leftShiftStage3Idx1_uid140_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage3Idx1_uid140_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_3_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_leftShiftStage3Idx1_uid140_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_3_q <= leftShiftStage3Idx1_uid140_fxpX_uid43_fpCosPiTest_q;
END IF;
END PROCESS;
--reg_leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_2(REG,357)@0
reg_leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_2_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_2_q <= leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_q;
END IF;
END PROCESS;
--leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest(BITSELECT,140)@0
leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest_in <= fxpShifterBits_uid42_fpCosPiTest_b(0 downto 0);
leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest_b <= leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest_in(0 downto 0);
--ld_leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest_b_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_b(DELAY,547)@0
ld_leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest_b_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest_b, xout => ld_leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest_b_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_b_q, clk => clk, aclr => areset );
--leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest(MUX,141)@1
leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_s <= ld_leftShiftStageSel0Dto0_uid141_fxpX_uid43_fpCosPiTest_b_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_b_q;
leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest: PROCESS (leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_s, reg_leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_2_q, reg_leftShiftStage3Idx1_uid140_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_3_q)
BEGIN
CASE leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_s IS
WHEN "0" => leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_q <= reg_leftShiftStage2_uid137_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_2_q;
WHEN "1" => leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_q <= reg_leftShiftStage3Idx1_uid140_fxpX_uid43_fpCosPiTest_0_to_leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_3_q;
WHEN OTHERS => leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--fxpXFrac_uid45_fpCosPiTest(BITSELECT,44)@1
fxpXFrac_uid45_fpCosPiTest_in <= leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_q(79 downto 0);
fxpXFrac_uid45_fpCosPiTest_b <= fxpXFrac_uid45_fpCosPiTest_in(79 downto 0);
--FxpXFrac79_uid46_fpCosPiTest(BITSELECT,45)@1
FxpXFrac79_uid46_fpCosPiTest_in <= fxpXFrac_uid45_fpCosPiTest_b;
FxpXFrac79_uid46_fpCosPiTest_b <= FxpXFrac79_uid46_fpCosPiTest_in(79 downto 79);
--FxpX80_uid44_fpCosPiTest(BITSELECT,43)@1
FxpX80_uid44_fpCosPiTest_in <= leftShiftStage3_uid142_fxpX_uid43_fpCosPiTest_q;
FxpX80_uid44_fpCosPiTest_b <= FxpX80_uid44_fpCosPiTest_in(80 downto 80);
--Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest(LOGICAL,97)@1
Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_a <= FxpX80_uid44_fpCosPiTest_b;
Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_b <= FxpXFrac79_uid46_fpCosPiTest_b;
Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_q <= Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_a xor Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_b;
--ld_Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_q_to_signRComp_uid101_fpCosPiTest_c(DELAY,504)@1
ld_Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_q_to_signRComp_uid101_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_q, xout => ld_Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_q_to_signRComp_uid101_fpCosPiTest_c_q, clk => clk, aclr => areset );
--cstBiasPwF_uid12_fpCosPiTest(CONSTANT,11)
cstBiasPwF_uid12_fpCosPiTest_q <= "10000110011";
--xEvenInt_uid37_fpCosPiTest(COMPARE,36)@0
xEvenInt_uid37_fpCosPiTest_cin <= GND_q;
xEvenInt_uid37_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasPwF_uid12_fpCosPiTest_q) & '0';
xEvenInt_uid37_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid6_fpCosPiTest_b) & xEvenInt_uid37_fpCosPiTest_cin(0);
xEvenInt_uid37_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xEvenInt_uid37_fpCosPiTest_a) - UNSIGNED(xEvenInt_uid37_fpCosPiTest_b));
xEvenInt_uid37_fpCosPiTest_c(0) <= xEvenInt_uid37_fpCosPiTest_o(13);
--ld_xEvenInt_uid37_fpCosPiTest_c_to_Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_a(DELAY,470)@0
ld_xEvenInt_uid37_fpCosPiTest_c_to_Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => xEvenInt_uid37_fpCosPiTest_c, xout => ld_xEvenInt_uid37_fpCosPiTest_c_to_Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_a_q, clk => clk, aclr => areset );
--InvXEvenInt_uid83_fpCosPiTest(LOGICAL,82)@2
InvXEvenInt_uid83_fpCosPiTest_a <= ld_xEvenInt_uid37_fpCosPiTest_c_to_Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_a_q;
InvXEvenInt_uid83_fpCosPiTest_q <= not InvXEvenInt_uid83_fpCosPiTest_a;
--biasMwShift_uid13_fpCosPiTest(CONSTANT,12)
biasMwShift_uid13_fpCosPiTest_q <= "01111100100";
--cosXIsOne_uid38_fpCosPiTest(COMPARE,37)@0
cosXIsOne_uid38_fpCosPiTest_cin <= GND_q;
cosXIsOne_uid38_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid6_fpCosPiTest_b) & '0';
cosXIsOne_uid38_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & biasMwShift_uid13_fpCosPiTest_q) & cosXIsOne_uid38_fpCosPiTest_cin(0);
cosXIsOne_uid38_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cosXIsOne_uid38_fpCosPiTest_a) - UNSIGNED(cosXIsOne_uid38_fpCosPiTest_b));
cosXIsOne_uid38_fpCosPiTest_c(0) <= cosXIsOne_uid38_fpCosPiTest_o(13);
--ld_cosXIsOne_uid38_fpCosPiTest_c_to_InvCosXIsOne_uid79_fpCosPiTest_a(DELAY,467)@0
ld_cosXIsOne_uid38_fpCosPiTest_c_to_InvCosXIsOne_uid79_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => cosXIsOne_uid38_fpCosPiTest_c, xout => ld_cosXIsOne_uid38_fpCosPiTest_c_to_InvCosXIsOne_uid79_fpCosPiTest_a_q, clk => clk, aclr => areset );
--InvCosXIsOne_uid79_fpCosPiTest(LOGICAL,78)@2
InvCosXIsOne_uid79_fpCosPiTest_a <= ld_cosXIsOne_uid38_fpCosPiTest_c_to_InvCosXIsOne_uid79_fpCosPiTest_a_q;
InvCosXIsOne_uid79_fpCosPiTest_q <= not InvCosXIsOne_uid79_fpCosPiTest_a;
--signRComp_uid101_fpCosPiTest(LOGICAL,100)@2
signRComp_uid101_fpCosPiTest_a <= InvCosXIsOne_uid79_fpCosPiTest_q;
signRComp_uid101_fpCosPiTest_b <= InvXEvenInt_uid83_fpCosPiTest_q;
signRComp_uid101_fpCosPiTest_c <= ld_Xor2FxpXParityFxpXHalfParity_uid98_fpCosPiTest_q_to_signRComp_uid101_fpCosPiTest_c_q;
signRComp_uid101_fpCosPiTest_q <= signRComp_uid101_fpCosPiTest_a and signRComp_uid101_fpCosPiTest_b and signRComp_uid101_fpCosPiTest_c;
--cstZwSwF_uid16_fpCosPiTest(CONSTANT,15)
cstZwSwF_uid16_fpCosPiTest_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000000";
--cstHalfwSwFP1_uid19_fpCosPiTest(BITJOIN,18)@2
cstHalfwSwFP1_uid19_fpCosPiTest_q <= VCC_q & cstZwSwF_uid16_fpCosPiTest_q;
--reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracHalf_uid48_fpCosPiTest_0(REG,359)@1
reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracHalf_uid48_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracHalf_uid48_fpCosPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracHalf_uid48_fpCosPiTest_0_q <= fxpXFrac_uid45_fpCosPiTest_b;
END IF;
END PROCESS;
--fxpXFracHalf_uid48_fpCosPiTest(LOGICAL,47)@2
fxpXFracHalf_uid48_fpCosPiTest_a <= reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracHalf_uid48_fpCosPiTest_0_q;
fxpXFracHalf_uid48_fpCosPiTest_b <= cstHalfwSwFP1_uid19_fpCosPiTest_q;
fxpXFracHalf_uid48_fpCosPiTest_q <= "1" when fxpXFracHalf_uid48_fpCosPiTest_a = fxpXFracHalf_uid48_fpCosPiTest_b else "0";
--InvFxpXFracHalf_uid102_fpCosPiTest(LOGICAL,101)@2
InvFxpXFracHalf_uid102_fpCosPiTest_a <= fxpXFracHalf_uid48_fpCosPiTest_q;
InvFxpXFracHalf_uid102_fpCosPiTest_q <= not InvFxpXFracHalf_uid102_fpCosPiTest_a;
--signR_uid103_fpCosPiTest(LOGICAL,102)@2
signR_uid103_fpCosPiTest_a <= InvFxpXFracHalf_uid102_fpCosPiTest_q;
signR_uid103_fpCosPiTest_b <= signRComp_uid101_fpCosPiTest_q;
signR_uid103_fpCosPiTest_q <= signR_uid103_fpCosPiTest_a and signR_uid103_fpCosPiTest_b;
--ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_inputreg(DELAY,932)
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => signR_uid103_fpCosPiTest_q, xout => ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_inputreg_q, clk => clk, aclr => areset );
--ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt(COUNTER,934)
-- every=1, low=0, high=37, step=1, init=1
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_i = 36 THEN
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_eq <= '1';
ELSE
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_eq <= '0';
END IF;
IF (ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_eq = '1') THEN
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_i <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_i - 37;
ELSE
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_i <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_i,6));
--ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdreg(REG,935)
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdreg_q <= "000000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdreg_q <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_q;
END IF;
END PROCESS;
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux(MUX,936)
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux_s <= VCC_q;
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux: PROCESS (ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux_s, ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdreg_q, ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux_q <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdreg_q;
WHEN "1" => ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux_q <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem(DUALMEM,933)
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_reset0 <= areset;
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_ia <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_inputreg_q;
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_aa <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdreg_q;
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_ab <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_rdmux_q;
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 38,
width_b => 1,
widthad_b => 6,
numwords_b => 38,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_iq,
address_a => ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_aa,
data_a => ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_ia
);
ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_q <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_iq(0 downto 0);
--cstBias_uid10_fpCosPiTest(CONSTANT,9)
cstBias_uid10_fpCosPiTest_q <= "01111111111";
--cstAllOWE_uid8_fpCosPiTest(CONSTANT,7)
cstAllOWE_uid8_fpCosPiTest_q <= "11111111111";
--cstAllZWE_uid22_fpCosPiTest(CONSTANT,21)
cstAllZWE_uid22_fpCosPiTest_q <= "00000000000";
--reg_fxpXFrac_uid45_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_1(REG,361)@1
reg_fxpXFrac_uid45_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpXFrac_uid45_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_1_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_fxpXFrac_uid45_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_1_q <= fxpXFrac_uid45_fpCosPiTest_b;
END IF;
END PROCESS;
--pad_o_uid17_uid49_fpCosPiTest(BITJOIN,48)@1
pad_o_uid17_uid49_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((79 downto 1 => GND_q(0)) & GND_q);
--reg_pad_o_uid17_uid49_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_0(REG,362)@1
reg_pad_o_uid17_uid49_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_o_uid17_uid49_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_0_q <= "000000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_pad_o_uid17_uid49_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_0_q <= pad_o_uid17_uid49_fpCosPiTest_q;
END IF;
END PROCESS;
--oMFxpXFrac_uid49_fpCosPiTest(SUB,49)@2
oMFxpXFrac_uid49_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid17_uid49_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_0_q);
oMFxpXFrac_uid49_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_fxpXFrac_uid45_fpCosPiTest_0_to_oMFxpXFrac_uid49_fpCosPiTest_1_q);
oMFxpXFrac_uid49_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
oMFxpXFrac_uid49_fpCosPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
oMFxpXFrac_uid49_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMFxpXFrac_uid49_fpCosPiTest_a) - UNSIGNED(oMFxpXFrac_uid49_fpCosPiTest_b));
END IF;
END PROCESS;
oMFxpXFrac_uid49_fpCosPiTest_q <= oMFxpXFrac_uid49_fpCosPiTest_o(81 downto 0);
--oMFxpXFrac_uid51_fpCosPiTest(BITSELECT,50)@3
oMFxpXFrac_uid51_fpCosPiTest_in <= oMFxpXFrac_uid49_fpCosPiTest_q(79 downto 0);
oMFxpXFrac_uid51_fpCosPiTest_b <= oMFxpXFrac_uid51_fpCosPiTest_in(79 downto 0);
--ld_fxpXFrac_uid45_fpCosPiTest_b_to_rangeReducedFxPX_uid53_fpCosPiTest_c(DELAY,443)@1
ld_fxpXFrac_uid45_fpCosPiTest_b_to_rangeReducedFxPX_uid53_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 80, depth => 2 )
PORT MAP ( xin => fxpXFrac_uid45_fpCosPiTest_b, xout => ld_fxpXFrac_uid45_fpCosPiTest_b_to_rangeReducedFxPX_uid53_fpCosPiTest_c_q, clk => clk, aclr => areset );
--ld_FxpXFrac79_uid46_fpCosPiTest_b_to_rangeReducedFxPX_uid53_fpCosPiTest_b(DELAY,442)@1
ld_FxpXFrac79_uid46_fpCosPiTest_b_to_rangeReducedFxPX_uid53_fpCosPiTest_b : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => FxpXFrac79_uid46_fpCosPiTest_b, xout => ld_FxpXFrac79_uid46_fpCosPiTest_b_to_rangeReducedFxPX_uid53_fpCosPiTest_b_q, clk => clk, aclr => areset );
--rangeReducedFxPX_uid53_fpCosPiTest(MUX,52)@3
rangeReducedFxPX_uid53_fpCosPiTest_s <= ld_FxpXFrac79_uid46_fpCosPiTest_b_to_rangeReducedFxPX_uid53_fpCosPiTest_b_q;
rangeReducedFxPX_uid53_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
rangeReducedFxPX_uid53_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
CASE rangeReducedFxPX_uid53_fpCosPiTest_s IS
WHEN "0" => rangeReducedFxPX_uid53_fpCosPiTest_q <= ld_fxpXFrac_uid45_fpCosPiTest_b_to_rangeReducedFxPX_uid53_fpCosPiTest_c_q;
WHEN "1" => rangeReducedFxPX_uid53_fpCosPiTest_q <= oMFxpXFrac_uid51_fpCosPiTest_b;
WHEN OTHERS => rangeReducedFxPX_uid53_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END PROCESS;
--pad_half_uid18_uid54_fpCosPiTest(BITJOIN,53)@3
pad_half_uid18_uid54_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((78 downto 1 => GND_q(0)) & GND_q);
--reg_pad_half_uid18_uid54_fpCosPiTest_0_to_z_halfMRRFxPXE_uid54_fpCosPiTest_0(REG,363)@3
reg_pad_half_uid18_uid54_fpCosPiTest_0_to_z_halfMRRFxPXE_uid54_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_half_uid18_uid54_fpCosPiTest_0_to_z_halfMRRFxPXE_uid54_fpCosPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_pad_half_uid18_uid54_fpCosPiTest_0_to_z_halfMRRFxPXE_uid54_fpCosPiTest_0_q <= pad_half_uid18_uid54_fpCosPiTest_q;
END IF;
END PROCESS;
--z_halfMRRFxPXE_uid54_fpCosPiTest(SUB,54)@4
z_halfMRRFxPXE_uid54_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_half_uid18_uid54_fpCosPiTest_0_to_z_halfMRRFxPXE_uid54_fpCosPiTest_0_q);
z_halfMRRFxPXE_uid54_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & rangeReducedFxPX_uid53_fpCosPiTest_q);
z_halfMRRFxPXE_uid54_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
z_halfMRRFxPXE_uid54_fpCosPiTest_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
z_halfMRRFxPXE_uid54_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(z_halfMRRFxPXE_uid54_fpCosPiTest_a) - UNSIGNED(z_halfMRRFxPXE_uid54_fpCosPiTest_b));
END IF;
END PROCESS;
z_halfMRRFxPXE_uid54_fpCosPiTest_q <= z_halfMRRFxPXE_uid54_fpCosPiTest_o(80 downto 0);
--z_uid56_fpCosPiTest(BITSELECT,55)@5
z_uid56_fpCosPiTest_in <= z_halfMRRFxPXE_uid54_fpCosPiTest_q(78 downto 0);
z_uid56_fpCosPiTest_b <= z_uid56_fpCosPiTest_in(78 downto 0);
--zAddr_uid64_fpCosPiTest(BITSELECT,63)@5
zAddr_uid64_fpCosPiTest_in <= z_uid56_fpCosPiTest_b;
zAddr_uid64_fpCosPiTest_b <= zAddr_uid64_fpCosPiTest_in(78 downto 72);
--memoryC5_uid230_sinPiZTableGenerator(LOOKUP,229)@5
memoryC5_uid230_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC5_uid230_sinPiZTableGenerator_q <= "11111111101000001";
ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN
CASE (zAddr_uid64_fpCosPiTest_b) IS
WHEN "0000000" => memoryC5_uid230_sinPiZTableGenerator_q <= "11111111101000001";
WHEN "0000001" => memoryC5_uid230_sinPiZTableGenerator_q <= "11111110101101000";
WHEN "0000010" => memoryC5_uid230_sinPiZTableGenerator_q <= "11111101101011101";
WHEN "0000011" => memoryC5_uid230_sinPiZTableGenerator_q <= "11111100110001110";
WHEN "0000100" => memoryC5_uid230_sinPiZTableGenerator_q <= "11111100000000010";
WHEN "0000101" => memoryC5_uid230_sinPiZTableGenerator_q <= "11111011000000000";
WHEN "0000110" => memoryC5_uid230_sinPiZTableGenerator_q <= "11111010001101101";
WHEN "0000111" => memoryC5_uid230_sinPiZTableGenerator_q <= "11111001010010111";
WHEN "0001000" => memoryC5_uid230_sinPiZTableGenerator_q <= "11111000010110010";
WHEN "0001001" => memoryC5_uid230_sinPiZTableGenerator_q <= "11110111100010100";
WHEN "0001010" => memoryC5_uid230_sinPiZTableGenerator_q <= "11110110100011111";
WHEN "0001011" => memoryC5_uid230_sinPiZTableGenerator_q <= "11110101100101101";
WHEN "0001100" => memoryC5_uid230_sinPiZTableGenerator_q <= "11110100101101011";
WHEN "0001101" => memoryC5_uid230_sinPiZTableGenerator_q <= "11110011111011101";
WHEN "0001110" => memoryC5_uid230_sinPiZTableGenerator_q <= "11110010111001010";
WHEN "0001111" => memoryC5_uid230_sinPiZTableGenerator_q <= "11110010001011011";
WHEN "0010000" => memoryC5_uid230_sinPiZTableGenerator_q <= "11110001010101011";
WHEN "0010001" => memoryC5_uid230_sinPiZTableGenerator_q <= "11110000011011001";
WHEN "0010010" => memoryC5_uid230_sinPiZTableGenerator_q <= "11101111011000001";
WHEN "0010011" => memoryC5_uid230_sinPiZTableGenerator_q <= "11101110101001010";
WHEN "0010100" => memoryC5_uid230_sinPiZTableGenerator_q <= "11101101110100110";
WHEN "0010101" => memoryC5_uid230_sinPiZTableGenerator_q <= "11101100111100011";
WHEN "0010110" => memoryC5_uid230_sinPiZTableGenerator_q <= "11101011111111111";
WHEN "0010111" => memoryC5_uid230_sinPiZTableGenerator_q <= "11101011001001010";
WHEN "0011000" => memoryC5_uid230_sinPiZTableGenerator_q <= "11101010010100110";
WHEN "0011001" => memoryC5_uid230_sinPiZTableGenerator_q <= "11101001010011011";
WHEN "0011010" => memoryC5_uid230_sinPiZTableGenerator_q <= "11101000100011100";
WHEN "0011011" => memoryC5_uid230_sinPiZTableGenerator_q <= "11100111101010110";
WHEN "0011100" => memoryC5_uid230_sinPiZTableGenerator_q <= "11100110110111000";
WHEN "0011101" => memoryC5_uid230_sinPiZTableGenerator_q <= "11100101111110010";
WHEN "0011110" => memoryC5_uid230_sinPiZTableGenerator_q <= "11100100111110010";
WHEN "0011111" => memoryC5_uid230_sinPiZTableGenerator_q <= "11100100001010101";
WHEN "0100000" => memoryC5_uid230_sinPiZTableGenerator_q <= "11100011011011111";
WHEN "0100001" => memoryC5_uid230_sinPiZTableGenerator_q <= "11100010011110111";
WHEN "0100010" => memoryC5_uid230_sinPiZTableGenerator_q <= "11100001110001010";
WHEN "0100011" => memoryC5_uid230_sinPiZTableGenerator_q <= "11100000111000100";
WHEN "0100100" => memoryC5_uid230_sinPiZTableGenerator_q <= "11011111111110101";
WHEN "0100101" => memoryC5_uid230_sinPiZTableGenerator_q <= "11011111001010110";
WHEN "0100110" => memoryC5_uid230_sinPiZTableGenerator_q <= "11011110011000111";
WHEN "0100111" => memoryC5_uid230_sinPiZTableGenerator_q <= "11011101101000000";
WHEN "0101000" => memoryC5_uid230_sinPiZTableGenerator_q <= "11011100110000011";
WHEN "0101001" => memoryC5_uid230_sinPiZTableGenerator_q <= "11011011111111001";
WHEN "0101010" => memoryC5_uid230_sinPiZTableGenerator_q <= "11011011000100110";
WHEN "0101011" => memoryC5_uid230_sinPiZTableGenerator_q <= "11011010010101100";
WHEN "0101100" => memoryC5_uid230_sinPiZTableGenerator_q <= "11011001100010010";
WHEN "0101101" => memoryC5_uid230_sinPiZTableGenerator_q <= "11011000101010111";
WHEN "0101110" => memoryC5_uid230_sinPiZTableGenerator_q <= "11010111111101010";
WHEN "0101111" => memoryC5_uid230_sinPiZTableGenerator_q <= "11010111001010000";
WHEN "0110000" => memoryC5_uid230_sinPiZTableGenerator_q <= "11010110011010011";
WHEN "0110001" => memoryC5_uid230_sinPiZTableGenerator_q <= "11010101100101011";
WHEN "0110010" => memoryC5_uid230_sinPiZTableGenerator_q <= "11010100110111110";
WHEN "0110011" => memoryC5_uid230_sinPiZTableGenerator_q <= "11010011111111000";
WHEN "0110100" => memoryC5_uid230_sinPiZTableGenerator_q <= "11010011010110010";
WHEN "0110101" => memoryC5_uid230_sinPiZTableGenerator_q <= "11010010101001110";
WHEN "0110110" => memoryC5_uid230_sinPiZTableGenerator_q <= "11010001110010011";
WHEN "0110111" => memoryC5_uid230_sinPiZTableGenerator_q <= "11010001000111011";
WHEN "0111000" => memoryC5_uid230_sinPiZTableGenerator_q <= "11010000001111011";
WHEN "0111001" => memoryC5_uid230_sinPiZTableGenerator_q <= "11001111011111110";
WHEN "0111010" => memoryC5_uid230_sinPiZTableGenerator_q <= "11001110111001010";
WHEN "0111011" => memoryC5_uid230_sinPiZTableGenerator_q <= "11001110001110111";
WHEN "0111100" => memoryC5_uid230_sinPiZTableGenerator_q <= "11001101011000100";
WHEN "0111101" => memoryC5_uid230_sinPiZTableGenerator_q <= "11001100101010010";
WHEN "0111110" => memoryC5_uid230_sinPiZTableGenerator_q <= "11001100000011111";
WHEN "0111111" => memoryC5_uid230_sinPiZTableGenerator_q <= "11001011010001010";
WHEN "1000000" => memoryC5_uid230_sinPiZTableGenerator_q <= "11001010100111110";
WHEN "1000001" => memoryC5_uid230_sinPiZTableGenerator_q <= "11001001110110010";
WHEN "1000010" => memoryC5_uid230_sinPiZTableGenerator_q <= "11001001010111000";
WHEN "1000011" => memoryC5_uid230_sinPiZTableGenerator_q <= "11001000100111111";
WHEN "1000100" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000111111001100";
WHEN "1000101" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000111010001001";
WHEN "1000110" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000110101010110";
WHEN "1000111" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000110000011101";
WHEN "1001000" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000101001110100";
WHEN "1001001" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000100101111001";
WHEN "1001010" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000011111111010";
WHEN "1001011" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000011011110110";
WHEN "1001100" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000010110001100";
WHEN "1001101" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000010001001000";
WHEN "1001110" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000001101111001";
WHEN "1001111" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000001000000111";
WHEN "1010000" => memoryC5_uid230_sinPiZTableGenerator_q <= "11000000010111001";
WHEN "1010001" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111111110110110";
WHEN "1010010" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111111001111111";
WHEN "1010011" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111110110010100";
WHEN "1010100" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111110001011000";
WHEN "1010101" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111101100010111";
WHEN "1010110" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111101000010010";
WHEN "1010111" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111100100010000";
WHEN "1011000" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111100000111100";
WHEN "1011001" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111011011111111";
WHEN "1011010" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111010111100000";
WHEN "1011011" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111010011110100";
WHEN "1011100" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111010000011100";
WHEN "1011101" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111001011011110";
WHEN "1011110" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111000111111101";
WHEN "1011111" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111000100101011";
WHEN "1100000" => memoryC5_uid230_sinPiZTableGenerator_q <= "10111000001100100";
WHEN "1100001" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110111101101110";
WHEN "1100010" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110111010011000";
WHEN "1100011" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110110110110000";
WHEN "1100100" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110110010011010";
WHEN "1100101" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110110000011110";
WHEN "1100110" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110101100101100";
WHEN "1100111" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110101000101110";
WHEN "1101000" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110100110100000";
WHEN "1101001" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110100100010001";
WHEN "1101010" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110100001000000";
WHEN "1101011" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110011101101110";
WHEN "1101100" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110011011011111";
WHEN "1101101" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110010111000100";
WHEN "1101110" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110010101110011";
WHEN "1101111" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110010001111100";
WHEN "1110000" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110010000001111";
WHEN "1110001" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110001110011001";
WHEN "1110010" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110001010100010";
WHEN "1110011" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110000111111000";
WHEN "1110100" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110000101110110";
WHEN "1110101" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110000101000100";
WHEN "1110110" => memoryC5_uid230_sinPiZTableGenerator_q <= "10110000010100010";
WHEN "1110111" => memoryC5_uid230_sinPiZTableGenerator_q <= "10101111111110011";
WHEN "1111000" => memoryC5_uid230_sinPiZTableGenerator_q <= "10101111110010000";
WHEN "1111001" => memoryC5_uid230_sinPiZTableGenerator_q <= "10101111100110111";
WHEN "1111010" => memoryC5_uid230_sinPiZTableGenerator_q <= "10101111010111000";
WHEN "1111011" => memoryC5_uid230_sinPiZTableGenerator_q <= "10101111000101000";
WHEN "1111100" => memoryC5_uid230_sinPiZTableGenerator_q <= "10101110110110100";
WHEN "1111101" => memoryC5_uid230_sinPiZTableGenerator_q <= "10101110101011010";
WHEN "1111110" => memoryC5_uid230_sinPiZTableGenerator_q <= "10101110100000011";
WHEN "1111111" => memoryC5_uid230_sinPiZTableGenerator_q <= "10101110010001011";
WHEN OTHERS =>
memoryC5_uid230_sinPiZTableGenerator_q <= "11111111101000001";
END CASE;
END IF;
END PROCESS;
--ld_z_uid56_fpCosPiTest_b_to_zPPolyEval_uid65_fpCosPiTest_a(DELAY,452)@5
ld_z_uid56_fpCosPiTest_b_to_zPPolyEval_uid65_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 79, depth => 1 )
PORT MAP ( xin => z_uid56_fpCosPiTest_b, xout => ld_z_uid56_fpCosPiTest_b_to_zPPolyEval_uid65_fpCosPiTest_a_q, clk => clk, aclr => areset );
--zPPolyEval_uid65_fpCosPiTest(BITSELECT,64)@6
zPPolyEval_uid65_fpCosPiTest_in <= ld_z_uid56_fpCosPiTest_b_to_zPPolyEval_uid65_fpCosPiTest_a_q(71 downto 0);
zPPolyEval_uid65_fpCosPiTest_b <= zPPolyEval_uid65_fpCosPiTest_in(71 downto 27);
--yT1_uid231_sinPiZPolyEval(BITSELECT,230)@6
yT1_uid231_sinPiZPolyEval_in <= zPPolyEval_uid65_fpCosPiTest_b;
yT1_uid231_sinPiZPolyEval_b <= yT1_uid231_sinPiZPolyEval_in(44 downto 28);
--prodXY_uid262_pT1_uid232_sinPiZPolyEval(MULT,261)@6
prodXY_uid262_pT1_uid232_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid262_pT1_uid232_sinPiZPolyEval_a),18)) * SIGNED(prodXY_uid262_pT1_uid232_sinPiZPolyEval_b);
prodXY_uid262_pT1_uid232_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid262_pT1_uid232_sinPiZPolyEval_a <= (others => '0');
prodXY_uid262_pT1_uid232_sinPiZPolyEval_b <= (others => '0');
prodXY_uid262_pT1_uid232_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prodXY_uid262_pT1_uid232_sinPiZPolyEval_a <= yT1_uid231_sinPiZPolyEval_b;
prodXY_uid262_pT1_uid232_sinPiZPolyEval_b <= memoryC5_uid230_sinPiZTableGenerator_q;
prodXY_uid262_pT1_uid232_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid262_pT1_uid232_sinPiZPolyEval_pr,34));
END IF;
END PROCESS;
prodXY_uid262_pT1_uid232_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid262_pT1_uid232_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prodXY_uid262_pT1_uid232_sinPiZPolyEval_q <= prodXY_uid262_pT1_uid232_sinPiZPolyEval_s1;
END IF;
END PROCESS;
--prodXYTruncFR_uid263_pT1_uid232_sinPiZPolyEval(BITSELECT,262)@9
prodXYTruncFR_uid263_pT1_uid232_sinPiZPolyEval_in <= prodXY_uid262_pT1_uid232_sinPiZPolyEval_q;
prodXYTruncFR_uid263_pT1_uid232_sinPiZPolyEval_b <= prodXYTruncFR_uid263_pT1_uid232_sinPiZPolyEval_in(33 downto 16);
--highBBits_uid234_sinPiZPolyEval(BITSELECT,233)@9
highBBits_uid234_sinPiZPolyEval_in <= prodXYTruncFR_uid263_pT1_uid232_sinPiZPolyEval_b;
highBBits_uid234_sinPiZPolyEval_b <= highBBits_uid234_sinPiZPolyEval_in(17 downto 1);
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC4_uid229_sinPiZTableGenerator_a(DELAY,638)@5
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC4_uid229_sinPiZTableGenerator_a : dspba_delay
GENERIC MAP ( width => 7, depth => 3 )
PORT MAP ( xin => zAddr_uid64_fpCosPiTest_b, xout => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC4_uid229_sinPiZTableGenerator_a_q, clk => clk, aclr => areset );
--memoryC4_uid229_sinPiZTableGenerator(LOOKUP,228)@8
memoryC4_uid229_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC4_uid229_sinPiZTableGenerator_q <= "01010001100110110001011110";
ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN
CASE (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC4_uid229_sinPiZTableGenerator_a_q) IS
WHEN "0000000" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001100110110001011110";
WHEN "0000001" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001100110011111111100";
WHEN "0000010" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001100101101100110011";
WHEN "0000011" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001100100010011000101";
WHEN "0000100" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001100010010010010110";
WHEN "0000101" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001011111110011000100";
WHEN "0000110" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001011100101011001100";
WHEN "0000111" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001011001000001111000";
WHEN "0001000" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001010100110101100100";
WHEN "0001001" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001010000000010110001";
WHEN "0001010" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001001010101111100100";
WHEN "0001011" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010001000100111000100010";
WHEN "0001100" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010000111110011011110101";
WHEN "0001101" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010000110111011001010101";
WHEN "0001110" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010000101111111000110001";
WHEN "0001111" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010000100111101101111110";
WHEN "0010000" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010000011111000010010110";
WHEN "0010001" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010000010101110100101111";
WHEN "0010010" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010000001100000110110101";
WHEN "0010011" => memoryC4_uid229_sinPiZTableGenerator_q <= "01010000000001101111000000";
WHEN "0010100" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001111110110110101110011";
WHEN "0010101" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001111101011011010111001";
WHEN "0010110" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001111011111011110000110";
WHEN "0010111" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001111010010111100110100";
WHEN "0011000" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001111000101110111111001";
WHEN "0011001" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001110111000010100011101";
WHEN "0011010" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001110101010001000110011";
WHEN "0011011" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001110011011011101100111";
WHEN "0011100" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001110001100001110001111";
WHEN "0011101" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001101111100011110001010";
WHEN "0011110" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001101101100001110100101";
WHEN "0011111" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001101011011011000110110";
WHEN "0100000" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001101001001111111101110";
WHEN "0100001" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001100111000001001001111";
WHEN "0100010" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001100100101101100011001";
WHEN "0100011" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001100010010110001110000";
WHEN "0100100" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001011111111010101110110";
WHEN "0100101" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001011101011010111000111";
WHEN "0100110" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001011010110110110011110";
WHEN "0100111" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001011000001110100011110";
WHEN "0101000" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001010101100010100010011";
WHEN "0101001" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001010010110010001000111";
WHEN "0101010" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001001111111110001000100";
WHEN "0101011" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001001101000101100110110";
WHEN "0101100" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001001010001001001111011";
WHEN "0101101" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001000111001001000001110";
WHEN "0101110" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001000100000100011110110";
WHEN "0101111" => memoryC4_uid229_sinPiZTableGenerator_q <= "01001000000111100001111001";
WHEN "0110000" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000111101101111111011111";
WHEN "0110001" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000111010011111111100110";
WHEN "0110010" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000110111001011110100100";
WHEN "0110011" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000110011110100010000111";
WHEN "0110100" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000110000011000010001001";
WHEN "0110101" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000101100111000101000011";
WHEN "0110110" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000101001010101101011111";
WHEN "0110111" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000100101101110011101110";
WHEN "0111000" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000100010000100000111110";
WHEN "0111001" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000011110010101101110100";
WHEN "0111010" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000011010100011010011110";
WHEN "0111011" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000010110101101011010111";
WHEN "0111100" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000010010110100011011101";
WHEN "0111101" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000001110110111100001001";
WHEN "0111110" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000001010110110110010000";
WHEN "0111111" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000000110110011000001101";
WHEN "1000000" => memoryC4_uid229_sinPiZTableGenerator_q <= "01000000010101011011011001";
WHEN "1000001" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111111110100000101110010";
WHEN "1000010" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111111010010001110101001";
WHEN "1000011" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111110110000000001101011";
WHEN "1000100" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111110001101011001110011";
WHEN "1000101" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111101101010010101011101";
WHEN "1000110" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111101000110110101111111";
WHEN "1000111" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111100100010111100111100";
WHEN "1001000" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111011111110101110100100";
WHEN "1001001" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111011011001111111110100";
WHEN "1001010" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111010110100111101000111";
WHEN "1001011" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111010001111011100101001";
WHEN "1001100" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111001101001100111100001";
WHEN "1001101" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111001000011011000101011";
WHEN "1001110" => memoryC4_uid229_sinPiZTableGenerator_q <= "00111000011100101100110010";
WHEN "1001111" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110111110101110000000011";
WHEN "1010000" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110111001110011001111101";
WHEN "1010001" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110110100110101001110001";
WHEN "1010010" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110101111110100101001011";
WHEN "1010011" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110101010110000110010110";
WHEN "1010100" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110100101101010100111010";
WHEN "1010101" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110100000100001101101101";
WHEN "1010110" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110011011010101110011000";
WHEN "1010111" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110010110000111001010011";
WHEN "1011000" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110010000110101101010010";
WHEN "1011001" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110001011100010001000010";
WHEN "1011010" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110000110001011111001110";
WHEN "1011011" => memoryC4_uid229_sinPiZTableGenerator_q <= "00110000000110010110110100";
WHEN "1011100" => memoryC4_uid229_sinPiZTableGenerator_q <= "00101111011010111010001000";
WHEN "1011101" => memoryC4_uid229_sinPiZTableGenerator_q <= "00101110101111001110001011";
WHEN "1011110" => memoryC4_uid229_sinPiZTableGenerator_q <= "00101110000011001011001100";
WHEN "1011111" => memoryC4_uid229_sinPiZTableGenerator_q <= "00101101010110110100111111";
WHEN "1100000" => memoryC4_uid229_sinPiZTableGenerator_q <= "00101100101010001011011001";
WHEN "1100001" => memoryC4_uid229_sinPiZTableGenerator_q <= "00101011111101010010000000";
WHEN "1100010" => memoryC4_uid229_sinPiZTableGenerator_q <= "00101011010000000101001000";
WHEN "1100011" => memoryC4_uid229_sinPiZTableGenerator_q <= "00101010100010100111110111";
WHEN "1100100" => memoryC4_uid229_sinPiZTableGenerator_q <= "00101001110100111011010110";
WHEN "1100101" => memoryC4_uid229_sinPiZTableGenerator_q <= "00101001000110110111101100";
WHEN "1100110" => memoryC4_uid229_sinPiZTableGenerator_q <= "00101000011000101000001000";
WHEN "1100111" => memoryC4_uid229_sinPiZTableGenerator_q <= "00100111101010001001010101";
WHEN "1101000" => memoryC4_uid229_sinPiZTableGenerator_q <= "00100110111011010110000011";
WHEN "1101001" => memoryC4_uid229_sinPiZTableGenerator_q <= "00100110001100010011011010";
WHEN "1101010" => memoryC4_uid229_sinPiZTableGenerator_q <= "00100101011101000100011001";
WHEN "1101011" => memoryC4_uid229_sinPiZTableGenerator_q <= "00100100101101100110100111";
WHEN "1101100" => memoryC4_uid229_sinPiZTableGenerator_q <= "00100011111101110111111010";
WHEN "1101101" => memoryC4_uid229_sinPiZTableGenerator_q <= "00100011001110000000101100";
WHEN "1101110" => memoryC4_uid229_sinPiZTableGenerator_q <= "00100010011101110011110101";
WHEN "1101111" => memoryC4_uid229_sinPiZTableGenerator_q <= "00100001101101100000010000";
WHEN "1110000" => memoryC4_uid229_sinPiZTableGenerator_q <= "00100000111100111010001011";
WHEN "1110001" => memoryC4_uid229_sinPiZTableGenerator_q <= "00100000001100000111111010";
WHEN "1110010" => memoryC4_uid229_sinPiZTableGenerator_q <= "00011111011011001110101000";
WHEN "1110011" => memoryC4_uid229_sinPiZTableGenerator_q <= "00011110101010000110010111";
WHEN "1110100" => memoryC4_uid229_sinPiZTableGenerator_q <= "00011101111000110001000001";
WHEN "1110101" => memoryC4_uid229_sinPiZTableGenerator_q <= "00011101000111001101001001";
WHEN "1110110" => memoryC4_uid229_sinPiZTableGenerator_q <= "00011100010101100011001010";
WHEN "1110111" => memoryC4_uid229_sinPiZTableGenerator_q <= "00011011100011101111010110";
WHEN "1111000" => memoryC4_uid229_sinPiZTableGenerator_q <= "00011010110001101110011110";
WHEN "1111001" => memoryC4_uid229_sinPiZTableGenerator_q <= "00011001111111100011010111";
WHEN "1111010" => memoryC4_uid229_sinPiZTableGenerator_q <= "00011001001101010000100101";
WHEN "1111011" => memoryC4_uid229_sinPiZTableGenerator_q <= "00011000011010110101101110";
WHEN "1111100" => memoryC4_uid229_sinPiZTableGenerator_q <= "00010111101000010001000000";
WHEN "1111101" => memoryC4_uid229_sinPiZTableGenerator_q <= "00010110110101100011000101";
WHEN "1111110" => memoryC4_uid229_sinPiZTableGenerator_q <= "00010110000010101101010111";
WHEN "1111111" => memoryC4_uid229_sinPiZTableGenerator_q <= "00010101001111110001011010";
WHEN OTHERS =>
memoryC4_uid229_sinPiZTableGenerator_q <= "01010001100110110001011110";
END CASE;
END IF;
END PROCESS;
--sumAHighB_uid235_sinPiZPolyEval(ADD,234)@9
sumAHighB_uid235_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((26 downto 26 => memoryC4_uid229_sinPiZTableGenerator_q(25)) & memoryC4_uid229_sinPiZTableGenerator_q);
sumAHighB_uid235_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((26 downto 17 => highBBits_uid234_sinPiZPolyEval_b(16)) & highBBits_uid234_sinPiZPolyEval_b);
sumAHighB_uid235_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid235_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid235_sinPiZPolyEval_b));
sumAHighB_uid235_sinPiZPolyEval_q <= sumAHighB_uid235_sinPiZPolyEval_o(26 downto 0);
--lowRangeB_uid233_sinPiZPolyEval(BITSELECT,232)@9
lowRangeB_uid233_sinPiZPolyEval_in <= prodXYTruncFR_uid263_pT1_uid232_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid233_sinPiZPolyEval_b <= lowRangeB_uid233_sinPiZPolyEval_in(0 downto 0);
--s1_uid233_uid236_sinPiZPolyEval(BITJOIN,235)@9
s1_uid233_uid236_sinPiZPolyEval_q <= sumAHighB_uid235_sinPiZPolyEval_q & lowRangeB_uid233_sinPiZPolyEval_b;
--reg_s1_uid233_uid236_sinPiZPolyEval_0_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_1(REG,373)@9
reg_s1_uid233_uid236_sinPiZPolyEval_0_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid233_uid236_sinPiZPolyEval_0_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_1_q <= "0000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_s1_uid233_uid236_sinPiZPolyEval_0_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_1_q <= s1_uid233_uid236_sinPiZPolyEval_q;
END IF;
END PROCESS;
--ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_nor(LOGICAL,977)
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_nor_b <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_sticky_ena_q;
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_nor_q <= not (ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_nor_a or ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_nor_b);
--ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_cmpReg(REG,975)
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_cmpReg_q <= VCC_q;
END IF;
END PROCESS;
--ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_sticky_ena(REG,978)
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_nor_q = "1") THEN
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_sticky_ena_q <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_enaAnd(LOGICAL,979)
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_enaAnd_a <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_sticky_ena_q;
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_enaAnd_b <= VCC_q;
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_enaAnd_q <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_enaAnd_a and ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_enaAnd_b;
--yT2_uid237_sinPiZPolyEval(BITSELECT,236)@6
yT2_uid237_sinPiZPolyEval_in <= zPPolyEval_uid65_fpCosPiTest_b;
yT2_uid237_sinPiZPolyEval_b <= yT2_uid237_sinPiZPolyEval_in(44 downto 19);
--ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt(COUNTER,971)
-- every=1, low=0, high=1, step=1, init=1
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt_i <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt_i + 1;
END IF;
END PROCESS;
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt_i,1));
--ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdreg(REG,972)
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdreg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdreg_q <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux(MUX,973)
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux_s <= VCC_q;
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux: PROCESS (ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux_s, ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdreg_q, ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt_q)
BEGIN
CASE ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux_s IS
WHEN "0" => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux_q <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdreg_q;
WHEN "1" => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux_q <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdcnt_q;
WHEN OTHERS => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem(DUALMEM,1059)
ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_ia <= yT2_uid237_sinPiZPolyEval_b;
ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_aa <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdreg_q;
ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_ab <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux_q;
ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 26,
widthad_a => 1,
numwords_a => 2,
width_b => 26,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_ia
);
ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_q <= ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_iq(25 downto 0);
--ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_outputreg(DELAY,1058)
ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_outputreg : dspba_delay
GENERIC MAP ( width => 26, depth => 1 )
PORT MAP ( xin => ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_replace_mem_q, xout => ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset );
--prodXY_uid265_pT2_uid238_sinPiZPolyEval(MULT,264)@10
prodXY_uid265_pT2_uid238_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid265_pT2_uid238_sinPiZPolyEval_a),27)) * SIGNED(prodXY_uid265_pT2_uid238_sinPiZPolyEval_b);
prodXY_uid265_pT2_uid238_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid265_pT2_uid238_sinPiZPolyEval_a <= (others => '0');
prodXY_uid265_pT2_uid238_sinPiZPolyEval_b <= (others => '0');
prodXY_uid265_pT2_uid238_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prodXY_uid265_pT2_uid238_sinPiZPolyEval_a <= ld_yT2_uid237_sinPiZPolyEval_b_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_a_outputreg_q;
prodXY_uid265_pT2_uid238_sinPiZPolyEval_b <= reg_s1_uid233_uid236_sinPiZPolyEval_0_to_prodXY_uid265_pT2_uid238_sinPiZPolyEval_1_q;
prodXY_uid265_pT2_uid238_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid265_pT2_uid238_sinPiZPolyEval_pr,54));
END IF;
END PROCESS;
prodXY_uid265_pT2_uid238_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid265_pT2_uid238_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
prodXY_uid265_pT2_uid238_sinPiZPolyEval_q <= prodXY_uid265_pT2_uid238_sinPiZPolyEval_s1;
END IF;
END PROCESS;
--prodXYTruncFR_uid266_pT2_uid238_sinPiZPolyEval(BITSELECT,265)@13
prodXYTruncFR_uid266_pT2_uid238_sinPiZPolyEval_in <= prodXY_uid265_pT2_uid238_sinPiZPolyEval_q;
prodXYTruncFR_uid266_pT2_uid238_sinPiZPolyEval_b <= prodXYTruncFR_uid266_pT2_uid238_sinPiZPolyEval_in(53 downto 25);
--highBBits_uid240_sinPiZPolyEval(BITSELECT,239)@13
highBBits_uid240_sinPiZPolyEval_in <= prodXYTruncFR_uid266_pT2_uid238_sinPiZPolyEval_b;
highBBits_uid240_sinPiZPolyEval_b <= highBBits_uid240_sinPiZPolyEval_in(28 downto 1);
--reg_highBBits_uid240_sinPiZPolyEval_0_to_sumAHighB_uid241_sinPiZPolyEval_1(REG,374)@13
reg_highBBits_uid240_sinPiZPolyEval_0_to_sumAHighB_uid241_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid240_sinPiZPolyEval_0_to_sumAHighB_uid241_sinPiZPolyEval_1_q <= "0000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_highBBits_uid240_sinPiZPolyEval_0_to_sumAHighB_uid241_sinPiZPolyEval_1_q <= highBBits_uid240_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_nor(LOGICAL,1029)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_nor_b <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_nor_q <= not (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_nor_a or ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_nor_b);
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_mem_top(CONSTANT,1025)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_mem_top_q <= "0101";
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmp(LOGICAL,1026)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmp_a <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_mem_top_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux_q);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmp_q <= "1" when ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmp_a = ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmp_b else "0";
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmpReg(REG,1027)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmpReg_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmp_q;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_sticky_ena(REG,1030)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_sticky_ena_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_enaAnd(LOGICAL,1031)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_enaAnd_a <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_enaAnd_b <= VCC_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_enaAnd_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_enaAnd_a and ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_enaAnd_b;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,1021)
-- every=1, low=0, high=5, step=1, init=1
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_i = 4 THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_i - 5;
ELSE
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_i,3));
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdreg(REG,1022)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdreg_q <= "000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdreg_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux(MUX,1023)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux_s <= VCC_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux_s, ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdreg_q, ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem(DUALMEM,1020)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_ia <= zAddr_uid64_fpCosPiTest_b;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_aa <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdreg_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_ab <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_rdmux_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 3,
numwords_a => 6,
width_b => 7,
widthad_b => 3,
numwords_b => 6,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_ia
);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_outputreg(DELAY,1019)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_outputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_replace_mem_q, xout => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_outputreg_q, clk => clk, aclr => areset );
--memoryC3_uid228_sinPiZTableGenerator(LOOKUP,227)@13
memoryC3_uid228_sinPiZTableGenerator: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
memoryC3_uid228_sinPiZTableGenerator_q <= "11111111111111111111111111111001011";
ELSIF (clk'EVENT AND clk = '1'AND VCC_q = "1") THEN
CASE (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC3_uid228_sinPiZTableGenerator_a_outputreg_q) IS
WHEN "0000000" => memoryC3_uid228_sinPiZTableGenerator_q <= "11111111111111111111111111111001011";
WHEN "0000001" => memoryC3_uid228_sinPiZTableGenerator_q <= "00000001010001100110101000111010101";
WHEN "0000010" => memoryC3_uid228_sinPiZTableGenerator_q <= "00000010100011001100101101010110011";
WHEN "0000011" => memoryC3_uid228_sinPiZTableGenerator_q <= "00000011110100110001101010100011011";
WHEN "0000100" => memoryC3_uid228_sinPiZTableGenerator_q <= "00000101000110010100111100101110011";
WHEN "0000101" => memoryC3_uid228_sinPiZTableGenerator_q <= "00000110010111110101111101101101000";
WHEN "0000110" => memoryC3_uid228_sinPiZTableGenerator_q <= "00000111101001010100001100001001101";
WHEN "0000111" => memoryC3_uid228_sinPiZTableGenerator_q <= "00001000111010101111000010100001000";
WHEN "0001000" => memoryC3_uid228_sinPiZTableGenerator_q <= "00001010001100000101111101001011010";
WHEN "0001001" => memoryC3_uid228_sinPiZTableGenerator_q <= "00001011011101011000011001000111110";
WHEN "0001010" => memoryC3_uid228_sinPiZTableGenerator_q <= "00001100101110100101110001001110101";
WHEN "0001011" => memoryC3_uid228_sinPiZTableGenerator_q <= "00001101111111101101100010100000001";
WHEN "0001100" => memoryC3_uid228_sinPiZTableGenerator_q <= "00001111010000101111001001101010110";
WHEN "0001101" => memoryC3_uid228_sinPiZTableGenerator_q <= "00010000100001101010000011000110101";
WHEN "0001110" => memoryC3_uid228_sinPiZTableGenerator_q <= "00010001110010011101101001010101000";
WHEN "0001111" => memoryC3_uid228_sinPiZTableGenerator_q <= "00010011000011001001011011101011111";
WHEN "0010000" => memoryC3_uid228_sinPiZTableGenerator_q <= "00010100010011101100110100011101011";
WHEN "0010001" => memoryC3_uid228_sinPiZTableGenerator_q <= "00010101100100000111010000011110001";
WHEN "0010010" => memoryC3_uid228_sinPiZTableGenerator_q <= "00010110110100011000001011111010110";
WHEN "0010011" => memoryC3_uid228_sinPiZTableGenerator_q <= "00011000000100011111000101110110101";
WHEN "0010100" => memoryC3_uid228_sinPiZTableGenerator_q <= "00011001010100011011011001000001011";
WHEN "0010101" => memoryC3_uid228_sinPiZTableGenerator_q <= "00011010100100001100100010010100101";
WHEN "0010110" => memoryC3_uid228_sinPiZTableGenerator_q <= "00011011110011110001111110110101010";
WHEN "0010111" => memoryC3_uid228_sinPiZTableGenerator_q <= "00011101000011001011001100000011011";
WHEN "0011000" => memoryC3_uid228_sinPiZTableGenerator_q <= "00011110010010010111100111000010100";
WHEN "0011001" => memoryC3_uid228_sinPiZTableGenerator_q <= "00011111100001010110101011110000110";
WHEN "0011010" => memoryC3_uid228_sinPiZTableGenerator_q <= "00100000110000000111111001110100010";
WHEN "0011011" => memoryC3_uid228_sinPiZTableGenerator_q <= "00100001111110101010101100100101101";
WHEN "0011100" => memoryC3_uid228_sinPiZTableGenerator_q <= "00100011001100111110100010110001111";
WHEN "0011101" => memoryC3_uid228_sinPiZTableGenerator_q <= "00100100011011000010111001001011111";
WHEN "0011110" => memoryC3_uid228_sinPiZTableGenerator_q <= "00100101101000110111001101001101001";
WHEN "0011111" => memoryC3_uid228_sinPiZTableGenerator_q <= "00100110110110011010111110011001100";
WHEN "0100000" => memoryC3_uid228_sinPiZTableGenerator_q <= "00101000000011101101101010000100110";
WHEN "0100001" => memoryC3_uid228_sinPiZTableGenerator_q <= "00101001010000101110101101000010110";
WHEN "0100010" => memoryC3_uid228_sinPiZTableGenerator_q <= "00101010011101011101100111100100100";
WHEN "0100011" => memoryC3_uid228_sinPiZTableGenerator_q <= "00101011101001111001110110000110010";
WHEN "0100100" => memoryC3_uid228_sinPiZTableGenerator_q <= "00101100110110000010111000000110011";
WHEN "0100101" => memoryC3_uid228_sinPiZTableGenerator_q <= "00101110000001111000001100011110100";
WHEN "0100110" => memoryC3_uid228_sinPiZTableGenerator_q <= "00101111001101011001010010000000001";
WHEN "0100111" => memoryC3_uid228_sinPiZTableGenerator_q <= "00110000011000100101100111100001110";
WHEN "0101000" => memoryC3_uid228_sinPiZTableGenerator_q <= "00110001100011011100101011010100101";
WHEN "0101001" => memoryC3_uid228_sinPiZTableGenerator_q <= "00110010101101111101111110000010101";
WHEN "0101010" => memoryC3_uid228_sinPiZTableGenerator_q <= "00110011111000001000111101011101100";
WHEN "0101011" => memoryC3_uid228_sinPiZTableGenerator_q <= "00110101000001111101001011001100010";
WHEN "0101100" => memoryC3_uid228_sinPiZTableGenerator_q <= "00110110001011011010000101101010010";
WHEN "0101101" => memoryC3_uid228_sinPiZTableGenerator_q <= "00110111010100011111001100111101100";
WHEN "0101110" => memoryC3_uid228_sinPiZTableGenerator_q <= "00111000011101001100000010000100010";
WHEN "0101111" => memoryC3_uid228_sinPiZTableGenerator_q <= "00111001100101100000000100001010000";
WHEN "0110000" => memoryC3_uid228_sinPiZTableGenerator_q <= "00111010101101011010110100011101100";
WHEN "0110001" => memoryC3_uid228_sinPiZTableGenerator_q <= "00111011110100111011110011000011110";
WHEN "0110010" => memoryC3_uid228_sinPiZTableGenerator_q <= "00111100111100000010100001101010000";
WHEN "0110011" => memoryC3_uid228_sinPiZTableGenerator_q <= "00111110000010101110100000001010000";
WHEN "0110100" => memoryC3_uid228_sinPiZTableGenerator_q <= "00111111001000111111010001101010001";
WHEN "0110101" => memoryC3_uid228_sinPiZTableGenerator_q <= "01000000001110110100010110001111010";
WHEN "0110110" => memoryC3_uid228_sinPiZTableGenerator_q <= "01000001010100001101001110111110101";
WHEN "0110111" => memoryC3_uid228_sinPiZTableGenerator_q <= "01000010011001001001011111110000001";
WHEN "0111000" => memoryC3_uid228_sinPiZTableGenerator_q <= "01000011011101101000101000010101111";
WHEN "0111001" => memoryC3_uid228_sinPiZTableGenerator_q <= "01000100100001101010001101000100100";
WHEN "0111010" => memoryC3_uid228_sinPiZTableGenerator_q <= "01000101100101001101110000011010101";
WHEN "0111011" => memoryC3_uid228_sinPiZTableGenerator_q <= "01000110101000010010110100001011010";
WHEN "0111100" => memoryC3_uid228_sinPiZTableGenerator_q <= "01000111101010111000111010101011110";
WHEN "0111101" => memoryC3_uid228_sinPiZTableGenerator_q <= "01001000101100111111101000110111000";
WHEN "0111110" => memoryC3_uid228_sinPiZTableGenerator_q <= "01001001101110100110100001111001100";
WHEN "0111111" => memoryC3_uid228_sinPiZTableGenerator_q <= "01001010101111101101001000001001010";
WHEN "1000000" => memoryC3_uid228_sinPiZTableGenerator_q <= "01001011110000010011000001001000011";
WHEN "1000001" => memoryC3_uid228_sinPiZTableGenerator_q <= "01001100110000010111101111101010011";
WHEN "1000010" => memoryC3_uid228_sinPiZTableGenerator_q <= "01001101101111111010111010011001111";
WHEN "1000011" => memoryC3_uid228_sinPiZTableGenerator_q <= "01001110101110111100000011010000110";
WHEN "1000100" => memoryC3_uid228_sinPiZTableGenerator_q <= "01001111101101011010110000011010010";
WHEN "1000101" => memoryC3_uid228_sinPiZTableGenerator_q <= "01010000101011010110100111100000101";
WHEN "1000110" => memoryC3_uid228_sinPiZTableGenerator_q <= "01010001101000101111001101110100011";
WHEN "1000111" => memoryC3_uid228_sinPiZTableGenerator_q <= "01010010100101100100001000101010010";
WHEN "1001000" => memoryC3_uid228_sinPiZTableGenerator_q <= "01010011100001110100111101001010100";
WHEN "1001001" => memoryC3_uid228_sinPiZTableGenerator_q <= "01010100011101100001010100001011100";
WHEN "1001010" => memoryC3_uid228_sinPiZTableGenerator_q <= "01010101011000101000110001011100100";
WHEN "1001011" => memoryC3_uid228_sinPiZTableGenerator_q <= "01010110010011001010111110000100100";
WHEN "1001100" => memoryC3_uid228_sinPiZTableGenerator_q <= "01010111001101000111011111001000111";
WHEN "1001101" => memoryC3_uid228_sinPiZTableGenerator_q <= "01011000000110011101111101001011111";
WHEN "1001110" => memoryC3_uid228_sinPiZTableGenerator_q <= "01011000111111001110000000110011110";
WHEN "1001111" => memoryC3_uid228_sinPiZTableGenerator_q <= "01011001110111010111001110111111110";
WHEN "1010000" => memoryC3_uid228_sinPiZTableGenerator_q <= "01011010101110111001010010001110110";
WHEN "1010001" => memoryC3_uid228_sinPiZTableGenerator_q <= "01011011100101110011110011000111101";
WHEN "1010010" => memoryC3_uid228_sinPiZTableGenerator_q <= "01011100011100000110011001001001001";
WHEN "1010011" => memoryC3_uid228_sinPiZTableGenerator_q <= "01011101010001110000101111000101100";
WHEN "1010100" => memoryC3_uid228_sinPiZTableGenerator_q <= "01011110000110110010011100011000111";
WHEN "1010101" => memoryC3_uid228_sinPiZTableGenerator_q <= "01011110111011001011001011101010011";
WHEN "1010110" => memoryC3_uid228_sinPiZTableGenerator_q <= "01011111101110111010100111100011100";
WHEN "1010111" => memoryC3_uid228_sinPiZTableGenerator_q <= "01100000100010000000011001111101101";
WHEN "1011000" => memoryC3_uid228_sinPiZTableGenerator_q <= "01100001010100011100001101110011100";
WHEN "1011001" => memoryC3_uid228_sinPiZTableGenerator_q <= "01100010000110001101101100011100011";
WHEN "1011010" => memoryC3_uid228_sinPiZTableGenerator_q <= "01100010110111010100100010100000100";
WHEN "1011011" => memoryC3_uid228_sinPiZTableGenerator_q <= "01100011100111110000011100000001010";
WHEN "1011100" => memoryC3_uid228_sinPiZTableGenerator_q <= "01100100010111100001000100001101001";
WHEN "1011101" => memoryC3_uid228_sinPiZTableGenerator_q <= "01100101000110100110000110001111011";
WHEN "1011110" => memoryC3_uid228_sinPiZTableGenerator_q <= "01100101110100111111010000100111001";
WHEN "1011111" => memoryC3_uid228_sinPiZTableGenerator_q <= "01100110100010101100001111010001101";
WHEN "1100000" => memoryC3_uid228_sinPiZTableGenerator_q <= "01100111001111101100101111101110000";
WHEN "1100001" => memoryC3_uid228_sinPiZTableGenerator_q <= "01100111111100000000011110011100101";
WHEN "1100010" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101000100111100111001010011110100";
WHEN "1100011" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101001010010100000100001001001101";
WHEN "1100100" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101001111100101100010000111001000";
WHEN "1100101" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101010100110001010001010100001101";
WHEN "1100110" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101011001110111001111010101110101";
WHEN "1100111" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101011110110111011010001101111010";
WHEN "1101000" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101100011110001110000000111001111";
WHEN "1101001" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101101000100110001110111010010001";
WHEN "1101010" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101101101010100110100100110101101";
WHEN "1101011" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101110001111101011111011001010101";
WHEN "1101100" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101110110100000001101100000100000";
WHEN "1101101" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101111010111100111100111010111000";
WHEN "1101110" => memoryC3_uid228_sinPiZTableGenerator_q <= "01101111111010011101100010000110110";
WHEN "1101111" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110000011100100011001011010100000";
WHEN "1110000" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110000111101111000011000011110011";
WHEN "1110001" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110001011110011100111011010000000";
WHEN "1110010" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110001111110010000100101111100001";
WHEN "1110011" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110010011101010011001110010000111";
WHEN "1110100" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110010111011100100100111111111001";
WHEN "1110101" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110011011001000100101000000101011";
WHEN "1110110" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110011110101110011000001011101010";
WHEN "1110111" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110100010001101111101010010100010";
WHEN "1111000" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110100101100111010011001000110011";
WHEN "1111001" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110101000111010011000011010000011";
WHEN "1111010" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110101100000111001011110100010010";
WHEN "1111011" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110101111001101101100001110011100";
WHEN "1111100" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110110010001101111000100101110110";
WHEN "1111101" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110110101000111101111110101001010";
WHEN "1111110" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110110111111011010000111000110000";
WHEN "1111111" => memoryC3_uid228_sinPiZTableGenerator_q <= "01110111010101000011010110000100000";
WHEN OTHERS =>
memoryC3_uid228_sinPiZTableGenerator_q <= "11111111111111111111111111111001011";
END CASE;
END IF;
END PROCESS;
--sumAHighB_uid241_sinPiZPolyEval(ADD,240)@14
sumAHighB_uid241_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((35 downto 35 => memoryC3_uid228_sinPiZTableGenerator_q(34)) & memoryC3_uid228_sinPiZTableGenerator_q);
sumAHighB_uid241_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((35 downto 28 => reg_highBBits_uid240_sinPiZPolyEval_0_to_sumAHighB_uid241_sinPiZPolyEval_1_q(27)) & reg_highBBits_uid240_sinPiZPolyEval_0_to_sumAHighB_uid241_sinPiZPolyEval_1_q);
sumAHighB_uid241_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid241_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid241_sinPiZPolyEval_b));
sumAHighB_uid241_sinPiZPolyEval_q <= sumAHighB_uid241_sinPiZPolyEval_o(35 downto 0);
--lowRangeB_uid239_sinPiZPolyEval(BITSELECT,238)@13
lowRangeB_uid239_sinPiZPolyEval_in <= prodXYTruncFR_uid266_pT2_uid238_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid239_sinPiZPolyEval_b <= lowRangeB_uid239_sinPiZPolyEval_in(0 downto 0);
--ld_lowRangeB_uid239_sinPiZPolyEval_b_to_s2_uid239_uid242_sinPiZPolyEval_a(DELAY,652)@13
ld_lowRangeB_uid239_sinPiZPolyEval_b_to_s2_uid239_uid242_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => lowRangeB_uid239_sinPiZPolyEval_b, xout => ld_lowRangeB_uid239_sinPiZPolyEval_b_to_s2_uid239_uid242_sinPiZPolyEval_a_q, clk => clk, aclr => areset );
--s2_uid239_uid242_sinPiZPolyEval(BITJOIN,241)@14
s2_uid239_uid242_sinPiZPolyEval_q <= sumAHighB_uid241_sinPiZPolyEval_q & ld_lowRangeB_uid239_sinPiZPolyEval_b_to_s2_uid239_uid242_sinPiZPolyEval_a_q;
--yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval(BITSELECT,273)@14
yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_in <= s2_uid239_uid242_sinPiZPolyEval_q;
yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_b <= yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_in(36 downto 19);
--reg_yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_9(REG,375)@14
reg_yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_9_q <= "000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_9_q <= yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_nor(LOGICAL,1042)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_nor_b <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_nor_q <= not (ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_nor_a or ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_nor_b);
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_mem_top(CONSTANT,1038)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_mem_top_q <= "0110";
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmp(LOGICAL,1039)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmp_a <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_mem_top_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux_q);
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmp_a = ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmp_b else "0";
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmpReg(REG,1040)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmp_q;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_sticky_ena(REG,1043)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_enaAnd(LOGICAL,1044)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_enaAnd_b <= VCC_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_enaAnd_a and ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt(COUNTER,1034)
-- every=1, low=0, high=6, step=1, init=1
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_i = 5 THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_i - 6;
ELSE
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_i,3));
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdreg(REG,1035)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdreg_q <= "000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux(MUX,1036)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux_s <= VCC_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem(DUALMEM,1033)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid65_fpCosPiTest_b;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdreg_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_rdmux_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 45,
widthad_a => 3,
numwords_a => 7,
width_b => 45,
widthad_b => 3,
numwords_b => 7,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_iq(44 downto 0);
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_outputreg(DELAY,1032)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_outputreg : dspba_delay
GENERIC MAP ( width => 45, depth => 1 )
PORT MAP ( xin => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset );
--yT3_uid243_sinPiZPolyEval(BITSELECT,242)@15
yT3_uid243_sinPiZPolyEval_in <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT3_uid243_sinPiZPolyEval_a_outputreg_q;
yT3_uid243_sinPiZPolyEval_b <= yT3_uid243_sinPiZPolyEval_in(44 downto 10);
--xBottomBits_uid273_pT3_uid244_sinPiZPolyEval(BITSELECT,272)@15
xBottomBits_uid273_pT3_uid244_sinPiZPolyEval_in <= yT3_uid243_sinPiZPolyEval_b(7 downto 0);
xBottomBits_uid273_pT3_uid244_sinPiZPolyEval_b <= xBottomBits_uid273_pT3_uid244_sinPiZPolyEval_in(7 downto 0);
--pad_xBottomBits_uid273_uid276_pT3_uid244_sinPiZPolyEval(BITJOIN,275)@15
pad_xBottomBits_uid273_uid276_pT3_uid244_sinPiZPolyEval_q <= xBottomBits_uid273_pT3_uid244_sinPiZPolyEval_b & STD_LOGIC_VECTOR((8 downto 1 => GND_q(0)) & GND_q);
--yBottomBits_uid272_pT3_uid244_sinPiZPolyEval(BITSELECT,271)@14
yBottomBits_uid272_pT3_uid244_sinPiZPolyEval_in <= s2_uid239_uid242_sinPiZPolyEval_q(9 downto 0);
yBottomBits_uid272_pT3_uid244_sinPiZPolyEval_b <= yBottomBits_uid272_pT3_uid244_sinPiZPolyEval_in(9 downto 0);
--spad_yBottomBits_uid272_uid275_pT3_uid244_sinPiZPolyEval(BITJOIN,274)@14
spad_yBottomBits_uid272_uid275_pT3_uid244_sinPiZPolyEval_q <= GND_q & yBottomBits_uid272_pT3_uid244_sinPiZPolyEval_b;
--pad_yBottomBits_uid272_uid277_pT3_uid244_sinPiZPolyEval(BITJOIN,276)@14
pad_yBottomBits_uid272_uid277_pT3_uid244_sinPiZPolyEval_q <= spad_yBottomBits_uid272_uid275_pT3_uid244_sinPiZPolyEval_q & STD_LOGIC_VECTOR((6 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid272_uid277_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_6(REG,376)@14
reg_pad_yBottomBits_uid272_uid277_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid272_uid277_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_6_q <= "000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_pad_yBottomBits_uid272_uid277_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid272_uid277_pT3_uid244_sinPiZPolyEval_q;
END IF;
END PROCESS;
--xTop18Bits_uid271_pT3_uid244_sinPiZPolyEval(BITSELECT,270)@15
xTop18Bits_uid271_pT3_uid244_sinPiZPolyEval_in <= yT3_uid243_sinPiZPolyEval_b;
xTop18Bits_uid271_pT3_uid244_sinPiZPolyEval_b <= xTop18Bits_uid271_pT3_uid244_sinPiZPolyEval_in(34 downto 17);
--multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma(CHAINMULTADD,344)@15
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_p(0) <= multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_a(0) * multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_c(0);
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_p(1) <= multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_a(1) * multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_c(1);
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_p(0),38) + RESIZE(multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_p(1),38);
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_x(0) <= multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_w(0);
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_y(0) <= multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_x(0);
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(xTop18Bits_uid271_pT3_uid244_sinPiZPolyEval_b),19));
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(pad_xBottomBits_uid273_uid276_pT3_uid244_sinPiZPolyEval_q),19));
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid272_uid277_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_6_q),18));
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop18Bits_uid274_pT3_uid244_sinPiZPolyEval_0_to_multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_9_q),18));
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_s(0) <= multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_y(0);
END IF;
END PROCESS;
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_s(0),37));
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_q <= multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_s0;
END IF;
END PROCESS;
--multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval(BITSELECT,278)@18
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_in <= multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_cma_q;
multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_b <= multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_in(36 downto 7);
--highBBits_uid281_pT3_uid244_sinPiZPolyEval(BITSELECT,280)@18
highBBits_uid281_pT3_uid244_sinPiZPolyEval_in <= multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_b;
highBBits_uid281_pT3_uid244_sinPiZPolyEval_b <= highBBits_uid281_pT3_uid244_sinPiZPolyEval_in(29 downto 1);
--reg_highBBits_uid281_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_1(REG,378)@18
reg_highBBits_uid281_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid281_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_1_q <= "00000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_highBBits_uid281_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_1_q <= highBBits_uid281_pT3_uid244_sinPiZPolyEval_b;
END IF;
END PROCESS;
--yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval(BITSELECT,268)@14
yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_in <= s2_uid239_uid242_sinPiZPolyEval_q;
yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_b <= yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_in(36 downto 10);
--reg_yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_0_to_topProd_uid270_pT3_uid244_sinPiZPolyEval_1(REG,377)@14
reg_yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_0_to_topProd_uid270_pT3_uid244_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_0_to_topProd_uid270_pT3_uid244_sinPiZPolyEval_1_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_0_to_topProd_uid270_pT3_uid244_sinPiZPolyEval_1_q <= yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_b;
END IF;
END PROCESS;
--xTop27Bits_uid268_pT3_uid244_sinPiZPolyEval(BITSELECT,267)@15
xTop27Bits_uid268_pT3_uid244_sinPiZPolyEval_in <= yT3_uid243_sinPiZPolyEval_b;
xTop27Bits_uid268_pT3_uid244_sinPiZPolyEval_b <= xTop27Bits_uid268_pT3_uid244_sinPiZPolyEval_in(34 downto 8);
--topProd_uid270_pT3_uid244_sinPiZPolyEval(MULT,269)@15
topProd_uid270_pT3_uid244_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid270_pT3_uid244_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid270_pT3_uid244_sinPiZPolyEval_b);
topProd_uid270_pT3_uid244_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid270_pT3_uid244_sinPiZPolyEval_a <= (others => '0');
topProd_uid270_pT3_uid244_sinPiZPolyEval_b <= (others => '0');
topProd_uid270_pT3_uid244_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
topProd_uid270_pT3_uid244_sinPiZPolyEval_a <= xTop27Bits_uid268_pT3_uid244_sinPiZPolyEval_b;
topProd_uid270_pT3_uid244_sinPiZPolyEval_b <= reg_yTop27Bits_uid269_pT3_uid244_sinPiZPolyEval_0_to_topProd_uid270_pT3_uid244_sinPiZPolyEval_1_q;
topProd_uid270_pT3_uid244_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid270_pT3_uid244_sinPiZPolyEval_pr,54));
END IF;
END PROCESS;
topProd_uid270_pT3_uid244_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid270_pT3_uid244_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
topProd_uid270_pT3_uid244_sinPiZPolyEval_q <= topProd_uid270_pT3_uid244_sinPiZPolyEval_s1;
END IF;
END PROCESS;
--reg_topProd_uid270_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_0(REG,379)@18
reg_topProd_uid270_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_topProd_uid270_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_topProd_uid270_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_0_q <= topProd_uid270_pT3_uid244_sinPiZPolyEval_q;
END IF;
END PROCESS;
--sumAHighB_uid282_pT3_uid244_sinPiZPolyEval(ADD,281)@19
sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid270_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_0_q(53)) & reg_topProd_uid270_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_0_q);
sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid281_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid281_pT3_uid244_sinPiZPolyEval_0_to_sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_1_q);
sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_b));
sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_q <= sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_o(54 downto 0);
--lowRangeB_uid280_pT3_uid244_sinPiZPolyEval(BITSELECT,279)@18
lowRangeB_uid280_pT3_uid244_sinPiZPolyEval_in <= multSumOfTwo18_uid275_pT3_uid244_sinPiZPolyEval_b(0 downto 0);
lowRangeB_uid280_pT3_uid244_sinPiZPolyEval_b <= lowRangeB_uid280_pT3_uid244_sinPiZPolyEval_in(0 downto 0);
--ld_lowRangeB_uid280_pT3_uid244_sinPiZPolyEval_b_to_add0_uid280_uid283_pT3_uid244_sinPiZPolyEval_a(DELAY,690)@18
ld_lowRangeB_uid280_pT3_uid244_sinPiZPolyEval_b_to_add0_uid280_uid283_pT3_uid244_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => lowRangeB_uid280_pT3_uid244_sinPiZPolyEval_b, xout => ld_lowRangeB_uid280_pT3_uid244_sinPiZPolyEval_b_to_add0_uid280_uid283_pT3_uid244_sinPiZPolyEval_a_q, clk => clk, aclr => areset );
--add0_uid280_uid283_pT3_uid244_sinPiZPolyEval(BITJOIN,282)@19
add0_uid280_uid283_pT3_uid244_sinPiZPolyEval_q <= sumAHighB_uid282_pT3_uid244_sinPiZPolyEval_q & ld_lowRangeB_uid280_pT3_uid244_sinPiZPolyEval_b_to_add0_uid280_uid283_pT3_uid244_sinPiZPolyEval_a_q;
--R_uid284_pT3_uid244_sinPiZPolyEval(BITSELECT,283)@19
R_uid284_pT3_uid244_sinPiZPolyEval_in <= add0_uid280_uid283_pT3_uid244_sinPiZPolyEval_q(54 downto 0);
R_uid284_pT3_uid244_sinPiZPolyEval_b <= R_uid284_pT3_uid244_sinPiZPolyEval_in(54 downto 18);
--reg_R_uid284_pT3_uid244_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_1(REG,380)@19
reg_R_uid284_pT3_uid244_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid284_pT3_uid244_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_1_q <= "0000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_R_uid284_pT3_uid244_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_1_q <= R_uid284_pT3_uid244_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_nor(LOGICAL,1016)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_nor_b <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_nor_q <= not (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_nor_a or ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_nor_b);
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_mem_top(CONSTANT,1012)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_mem_top_q <= "01011";
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmp(LOGICAL,1013)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmp_a <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_mem_top_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux_q);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmp_q <= "1" when ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmp_a = ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmp_b else "0";
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmpReg(REG,1014)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmpReg_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmp_q;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_sticky_ena(REG,1017)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_sticky_ena_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_enaAnd(LOGICAL,1018)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_enaAnd_a <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_enaAnd_b <= VCC_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_enaAnd_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_enaAnd_a and ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_enaAnd_b;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,1008)
-- every=1, low=0, high=11, step=1, init=1
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_i = 10 THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_i - 11;
ELSE
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_i,4));
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdreg(REG,1009)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdreg_q <= "0000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdreg_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux(MUX,1010)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux_s <= VCC_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux_s, ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdreg_q, ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem(DUALMEM,1007)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_ia <= zAddr_uid64_fpCosPiTest_b;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_aa <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdreg_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_ab <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_rdmux_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 4,
numwords_a => 12,
width_b => 7,
widthad_b => 4,
numwords_b => 12,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_ia
);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_outputreg(DELAY,1006)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_outputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_replace_mem_q, xout => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_outputreg_q, clk => clk, aclr => areset );
--memoryC2_uid227_sinPiZTableGenerator(LOOKUP,226)@19
memoryC2_uid227_sinPiZTableGenerator: PROCESS (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_outputreg_q)
BEGIN
-- Begin reserved scope level
CASE (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC2_uid227_sinPiZTableGenerator_a_outputreg_q) IS
WHEN "0000000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110101010001000011000110011101100111000";
WHEN "0000001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110101010010000000010011011110101101000";
WHEN "0000010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110101010100110111111010000111001000101";
WHEN "0000011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110101011001101001111001000101101101011";
WHEN "0000100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110101100000010110001110010011100100110";
WHEN "0000101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110101101000111100110110110100100001100";
WHEN "0000110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110101110011011101101110110101011000001";
WHEN "0000111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110101111111111000110001101110000001000";
WHEN "0001000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110110001110001101111010000000001001001";
WHEN "0001001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110110011110011101000001010111100010011";
WHEN "0001010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110110110000100110000000101010101010010";
WHEN "0001011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110111000100101000101111111001111001110";
WHEN "0001100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110111011010100101000110010000000110000";
WHEN "0001101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010110111110010011010111010000010100101101";
WHEN "0001110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111000001100001010000000110001101010110";
WHEN "0001111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111000100111110010001111000111001110001";
WHEN "0010000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111001000101010011011000111000110111111";
WHEN "0010001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111001100100101101010001000110100001110";
WHEN "0010010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111010000101111111101001111011000110110";
WHEN "0010011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111010101001001010010100101011111010000";
WHEN "0010100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111011001110001101000001111010001111100";
WHEN "0010101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111011110101000111100001010010001101000";
WHEN "0010110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111100011101111001100001101011001010011";
WHEN "0010111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111101001000100010110001000111111011001";
WHEN "0011000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111101110101000010111100110110111011101";
WHEN "0011001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111110100011011001110001010010101001001";
WHEN "0011010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1010111111010011100110111010000000101010000";
WHEN "0011011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011000000000101101010000001110011011110111";
WHEN "0011100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011000000111001100010110010101001001001010";
WHEN "0011101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011000001101111010000110101101100011101100";
WHEN "0011110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011000010100110110011110011010100101011100";
WHEN "0011111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011000011100000001011010011000101010010101";
WHEN "0100000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011000100011011010110111011101111001100010";
WHEN "0100001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011000101011000010110010011010000011100100";
WHEN "0100010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011000110010111001000111110110011110000010";
WHEN "0100011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011000111010111101110100010110010000011111";
WHEN "0100100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011001000011010000110100010110001010111111";
WHEN "0100101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011001001011110010000100001100101110011011";
WHEN "0100110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011001010100100001100000001010001100011000";
WHEN "0100111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011001011101011111000100011000101001100001";
WHEN "0101000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011001100110101010101100111100000000011011";
WHEN "0101001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011001110000000100010101110001111101110010";
WHEN "0101010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011001111001101011111010110010001100011010";
WHEN "0101011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011010000011100001010111101110001010011110";
WHEN "0101100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011010001101100100101000010001011000100111";
WHEN "0101101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011010010111110101101000000001010011000010";
WHEN "0101110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011010100010010100010010011101010101101010";
WHEN "0101111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011010101101000000100010111111000010000011";
WHEN "0110000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011010110111111010010100111001111011100110";
WHEN "0110001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011011000011000001100011011011101110111001";
WHEN "0110010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011011001110010110001001101100001111110101";
WHEN "0110011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011011011001111000000010101101100000111100";
WHEN "0110100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011011100101100111001001011011101110011000";
WHEN "0110101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011011110001100011011000101101011001110101";
WHEN "0110110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011011111101101100101011010011010110110001";
WHEN "0110111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011100001010000010111011111000101001101100";
WHEN "0111000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011100010110100110000101000010110110110100";
WHEN "0111001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011100100011010110000001010001110101000110";
WHEN "0111010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011100110000010010101010111111111100101100";
WHEN "0111011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011100111101011011111100100010000110111111";
WHEN "0111100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011101001010110001110000000111101111100101";
WHEN "0111101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011101011000010011111111111010110011011100";
WHEN "0111110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011101100110000010100101111111111011010100";
WHEN "0111111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011101110011111101011100010110011100010110";
WHEN "1000000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011110000010000100011100111000010100111110";
WHEN "1000001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011110010000010111100001011010011001010101";
WHEN "1000010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011110011110110110100011101100001011001000";
WHEN "1000011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011110101101100001011101011000001011011001";
WHEN "1000100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011110111100011000001000000011101110001111";
WHEN "1000101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011111001011011010011101001111000101110001";
WHEN "1000110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011111011010101000010110010101100101000110";
WHEN "1000111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011111101010000001101100101101100010111111";
WHEN "1001000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1011111111001100110011001101000011100111011";
WHEN "1001001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100000001001010110010110010010110100011100";
WHEN "1001010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100000011001010001011011110100100000011000";
WHEN "1001011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100000101001010111100011010000011111011101";
WHEN "1001100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100000111001101000100101100101001010011111";
WHEN "1001101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100001001010000100011011101100001100000010";
WHEN "1001110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100001011010101010111110011010101000110000";
WHEN "1001111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100001101011011100000110100001001001100100";
WHEN "1010000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100001111100010111101100101011101111001100";
WHEN "1010001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100010001101011101101001100010000010111010";
WHEN "1010010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100010011110101101110101100111011000000101";
WHEN "1010011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100010110000001000001001011010101000000100";
WHEN "1010100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100011000001101100011101010110100010000110";
WHEN "1010101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100011010011011010101001110001100010110011";
WHEN "1010110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100011100101010010100110111101111101101001";
WHEN "1010111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100011110111010100001101001010000001101110";
WHEN "1011000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100100001001011111010100011111111010110111";
WHEN "1011001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100100011011110011110101000101111001011001";
WHEN "1011010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100100101110010001100110111110001101101110";
WHEN "1011011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100101000000111000100010000111010010100101";
WHEN "1011100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100101010011101000011110011011110001111001";
WHEN "1011101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100101100110100001010011110010100110010101";
WHEN "1011110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100101111001100010111001111110111010001011";
WHEN "1011111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100110001100101101001000110000010101000001";
WHEN "1100000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100110011111111111110111110010111000010010";
WHEN "1100001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100110110011011010111110101111001000100111";
WHEN "1100010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100111000110111110010101001010001010011010";
WHEN "1100011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100111011010101001110010100101101110010111";
WHEN "1100100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1100111101110011101001110100000001111101010";
WHEN "1100101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101000000010011000100000010100110110100000";
WHEN "1100110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101000010110011011011111011011100110110011";
WHEN "1100111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101000101010100110000011001001011000000001";
WHEN "1101000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101000111110111000000010101111111100010101";
WHEN "1101001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101001010011010001010101011110001011010100";
WHEN "1101010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101001100111110001110010100000000000010111";
WHEN "1101011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101001111100011001010000111110011101110000";
WHEN "1101100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101010010001000111100111111111110011011101";
WHEN "1101101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101010100101111100101110100111100110010101";
WHEN "1101110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101010111010111000011011110110101001010101";
WHEN "1101111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101011001111111010100110101011010011011011";
WHEN "1110000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101011100101000011000110000001010000000100";
WHEN "1110001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101011111010010001110000110001110011111011";
WHEN "1110010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101100001111100110011101110011111001111111";
WHEN "1110011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101100100101000001000011111100000011011011";
WHEN "1110100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101100111010100001011001111100100100101001";
WHEN "1110101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101101010000000111010110100101100100010111";
WHEN "1110110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101101100101110010110000100101000101101101";
WHEN "1110111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101101111011100011011110100111000011010111";
WHEN "1111000" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101110010001011001010111010101011001010001";
WHEN "1111001" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101110100111010100010001011000001010110100";
WHEN "1111010" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101110111101010100000011010101100101100011";
WHEN "1111011" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101111010011011000100011110010000011111011";
WHEN "1111100" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101111101001100001101001010000010010001011";
WHEN "1111101" => memoryC2_uid227_sinPiZTableGenerator_q <= "1101111111111101111001010010001010101000011";
WHEN "1111110" => memoryC2_uid227_sinPiZTableGenerator_q <= "1110000010110000000111101010100101101001001";
WHEN "1111111" => memoryC2_uid227_sinPiZTableGenerator_q <= "1110000101100010110111000111000011010110101";
WHEN OTHERS =>
memoryC2_uid227_sinPiZTableGenerator_q <= "1010110101010001000011000110011101100111000";
END CASE;
-- End reserved scope level
END PROCESS;
--rndBit_uid245_sinPiZPolyEval(CONSTANT,244)
rndBit_uid245_sinPiZPolyEval_q <= "01";
--cIncludingRoundingBit_uid246_sinPiZPolyEval(BITJOIN,245)@19
cIncludingRoundingBit_uid246_sinPiZPolyEval_q <= memoryC2_uid227_sinPiZTableGenerator_q & rndBit_uid245_sinPiZPolyEval_q;
--reg_cIncludingRoundingBit_uid246_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_0(REG,381)@19
reg_cIncludingRoundingBit_uid246_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid246_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_cIncludingRoundingBit_uid246_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid246_sinPiZPolyEval_q;
END IF;
END PROCESS;
--ts3_uid247_sinPiZPolyEval(ADD,246)@20
ts3_uid247_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((45 downto 45 => reg_cIncludingRoundingBit_uid246_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_0_q(44)) & reg_cIncludingRoundingBit_uid246_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_0_q);
ts3_uid247_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((45 downto 37 => reg_R_uid284_pT3_uid244_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_1_q(36)) & reg_R_uid284_pT3_uid244_sinPiZPolyEval_0_to_ts3_uid247_sinPiZPolyEval_1_q);
ts3_uid247_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts3_uid247_sinPiZPolyEval_a) + SIGNED(ts3_uid247_sinPiZPolyEval_b));
ts3_uid247_sinPiZPolyEval_q <= ts3_uid247_sinPiZPolyEval_o(45 downto 0);
--s3_uid248_sinPiZPolyEval(BITSELECT,247)@20
s3_uid248_sinPiZPolyEval_in <= ts3_uid247_sinPiZPolyEval_q;
s3_uid248_sinPiZPolyEval_b <= s3_uid248_sinPiZPolyEval_in(45 downto 1);
--yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval(BITSELECT,285)@20
yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_in <= s3_uid248_sinPiZPolyEval_b;
yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_b <= yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_in(44 downto 18);
--reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_9(REG,382)@20
reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_9_q <= yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_nor(LOGICAL,1055)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_nor_b <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_nor_q <= not (ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_nor_a or ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_nor_b);
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_mem_top(CONSTANT,1051)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_mem_top_q <= "01100";
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmp(LOGICAL,1052)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmp_a <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_mem_top_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux_q);
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmp_a = ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmp_b else "0";
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmpReg(REG,1053)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmp_q;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_sticky_ena(REG,1056)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_enaAnd(LOGICAL,1057)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_enaAnd_b <= VCC_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_enaAnd_a and ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt(COUNTER,1047)
-- every=1, low=0, high=12, step=1, init=1
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,4);
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_i = 11 THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_i - 12;
ELSE
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_i,4));
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdreg(REG,1048)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdreg_q <= "0000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux(MUX,1049)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux_s <= VCC_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem(DUALMEM,1046)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid65_fpCosPiTest_b;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdreg_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_rdmux_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 45,
widthad_a => 4,
numwords_a => 13,
width_b => 45,
widthad_b => 4,
numwords_b => 13,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_iq(44 downto 0);
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_outputreg(DELAY,1045)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_outputreg : dspba_delay
GENERIC MAP ( width => 45, depth => 1 )
PORT MAP ( xin => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset );
--yT4_uid249_sinPiZPolyEval(BITSELECT,248)@21
yT4_uid249_sinPiZPolyEval_in <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_yT4_uid249_sinPiZPolyEval_a_outputreg_q;
yT4_uid249_sinPiZPolyEval_b <= yT4_uid249_sinPiZPolyEval_in(44 downto 2);
--xBottomBits_uid289_pT4_uid250_sinPiZPolyEval(BITSELECT,288)@21
xBottomBits_uid289_pT4_uid250_sinPiZPolyEval_in <= yT4_uid249_sinPiZPolyEval_b(15 downto 0);
xBottomBits_uid289_pT4_uid250_sinPiZPolyEval_b <= xBottomBits_uid289_pT4_uid250_sinPiZPolyEval_in(15 downto 0);
--pad_xBottomBits_uid289_uid291_pT4_uid250_sinPiZPolyEval(BITJOIN,290)@21
pad_xBottomBits_uid289_uid291_pT4_uid250_sinPiZPolyEval_q <= xBottomBits_uid289_pT4_uid250_sinPiZPolyEval_b & STD_LOGIC_VECTOR((9 downto 1 => GND_q(0)) & GND_q);
--yBottomBits_uid288_pT4_uid250_sinPiZPolyEval(BITSELECT,287)@20
yBottomBits_uid288_pT4_uid250_sinPiZPolyEval_in <= s3_uid248_sinPiZPolyEval_b(17 downto 0);
yBottomBits_uid288_pT4_uid250_sinPiZPolyEval_b <= yBottomBits_uid288_pT4_uid250_sinPiZPolyEval_in(17 downto 0);
--ld_yBottomBits_uid288_pT4_uid250_sinPiZPolyEval_b_to_spad_yBottomBits_uid288_uid290_pT4_uid250_sinPiZPolyEval_a(DELAY,699)@20
ld_yBottomBits_uid288_pT4_uid250_sinPiZPolyEval_b_to_spad_yBottomBits_uid288_uid290_pT4_uid250_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => yBottomBits_uid288_pT4_uid250_sinPiZPolyEval_b, xout => ld_yBottomBits_uid288_pT4_uid250_sinPiZPolyEval_b_to_spad_yBottomBits_uid288_uid290_pT4_uid250_sinPiZPolyEval_a_q, clk => clk, aclr => areset );
--spad_yBottomBits_uid288_uid290_pT4_uid250_sinPiZPolyEval(BITJOIN,289)@21
spad_yBottomBits_uid288_uid290_pT4_uid250_sinPiZPolyEval_q <= GND_q & ld_yBottomBits_uid288_pT4_uid250_sinPiZPolyEval_b_to_spad_yBottomBits_uid288_uid290_pT4_uid250_sinPiZPolyEval_a_q;
--pad_yBottomBits_uid288_uid292_pT4_uid250_sinPiZPolyEval(BITJOIN,291)@21
pad_yBottomBits_uid288_uid292_pT4_uid250_sinPiZPolyEval_q <= spad_yBottomBits_uid288_uid290_pT4_uid250_sinPiZPolyEval_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--reg_pad_yBottomBits_uid288_uid292_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_6(REG,383)@21
reg_pad_yBottomBits_uid288_uid292_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid288_uid292_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_pad_yBottomBits_uid288_uid292_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid288_uid292_pT4_uid250_sinPiZPolyEval_q;
END IF;
END PROCESS;
--ld_yT4_uid249_sinPiZPolyEval_b_to_xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_a(DELAY,693)@21
ld_yT4_uid249_sinPiZPolyEval_b_to_xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 43, depth => 1 )
PORT MAP ( xin => yT4_uid249_sinPiZPolyEval_b, xout => ld_yT4_uid249_sinPiZPolyEval_b_to_xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_a_q, clk => clk, aclr => areset );
--xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval(BITSELECT,284)@22
xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_in <= ld_yT4_uid249_sinPiZPolyEval_b_to_xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_a_q;
xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_b <= xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_in(42 downto 16);
--multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma(CHAINMULTADD,345)@22
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_p(0) <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_a(0) * multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_c(0);
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_p(1) <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_a(1) * multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_c(1);
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_p(0),56);
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_p(1),56);
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_x(0) <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_w(0);
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_x(1) <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_w(1);
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_y(0) <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_s(1) + multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_x(0);
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_y(1) <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_x(1);
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_b),28));
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(pad_xBottomBits_uid289_uid291_pT4_uid250_sinPiZPolyEval_q),28));
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid288_uid292_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_6_q),27));
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_9_q),27));
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_s(0) <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_y(0);
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_s(1) <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_y(1);
END IF;
END PROCESS;
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_s(0),55));
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_q <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_s0;
END IF;
END PROCESS;
--multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval(BITSELECT,293)@25
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_in <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_cma_q;
multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_b <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_in(54 downto 8);
--highBBits_uid296_pT4_uid250_sinPiZPolyEval(BITSELECT,295)@25
highBBits_uid296_pT4_uid250_sinPiZPolyEval_in <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_b;
highBBits_uid296_pT4_uid250_sinPiZPolyEval_b <= highBBits_uid296_pT4_uid250_sinPiZPolyEval_in(46 downto 18);
--reg_highBBits_uid296_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_1(REG,385)@25
reg_highBBits_uid296_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid296_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_1_q <= "00000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_highBBits_uid296_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_1_q <= highBBits_uid296_pT4_uid250_sinPiZPolyEval_b;
END IF;
END PROCESS;
--reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_1(REG,384)@20
reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_1_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_1_q <= yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_1_q_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_b(DELAY,696)@21
ld_reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_1_q_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_1_q, xout => ld_reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_1_q_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_b_q, clk => clk, aclr => areset );
--topProd_uid287_pT4_uid250_sinPiZPolyEval(MULT,286)@22
topProd_uid287_pT4_uid250_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid287_pT4_uid250_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid287_pT4_uid250_sinPiZPolyEval_b);
topProd_uid287_pT4_uid250_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid287_pT4_uid250_sinPiZPolyEval_a <= (others => '0');
topProd_uid287_pT4_uid250_sinPiZPolyEval_b <= (others => '0');
topProd_uid287_pT4_uid250_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
topProd_uid287_pT4_uid250_sinPiZPolyEval_a <= xTop27Bits_uid285_pT4_uid250_sinPiZPolyEval_b;
topProd_uid287_pT4_uid250_sinPiZPolyEval_b <= ld_reg_yTop27Bits_uid286_pT4_uid250_sinPiZPolyEval_0_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_1_q_to_topProd_uid287_pT4_uid250_sinPiZPolyEval_b_q;
topProd_uid287_pT4_uid250_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid287_pT4_uid250_sinPiZPolyEval_pr,54));
END IF;
END PROCESS;
topProd_uid287_pT4_uid250_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid287_pT4_uid250_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
topProd_uid287_pT4_uid250_sinPiZPolyEval_q <= topProd_uid287_pT4_uid250_sinPiZPolyEval_s1;
END IF;
END PROCESS;
--reg_topProd_uid287_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_0(REG,386)@25
reg_topProd_uid287_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_topProd_uid287_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_topProd_uid287_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_0_q <= topProd_uid287_pT4_uid250_sinPiZPolyEval_q;
END IF;
END PROCESS;
--sumAHighB_uid297_pT4_uid250_sinPiZPolyEval(ADD,296)@26
sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid287_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_0_q(53)) & reg_topProd_uid287_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_0_q);
sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid296_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid296_pT4_uid250_sinPiZPolyEval_0_to_sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_1_q);
sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_b));
sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_q <= sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_o(54 downto 0);
--lowRangeB_uid295_pT4_uid250_sinPiZPolyEval(BITSELECT,294)@25
lowRangeB_uid295_pT4_uid250_sinPiZPolyEval_in <= multSumOfTwo27_uid290_pT4_uid250_sinPiZPolyEval_b(17 downto 0);
lowRangeB_uid295_pT4_uid250_sinPiZPolyEval_b <= lowRangeB_uid295_pT4_uid250_sinPiZPolyEval_in(17 downto 0);
--ld_lowRangeB_uid295_pT4_uid250_sinPiZPolyEval_b_to_add0_uid295_uid298_pT4_uid250_sinPiZPolyEval_a(DELAY,707)@25
ld_lowRangeB_uid295_pT4_uid250_sinPiZPolyEval_b_to_add0_uid295_uid298_pT4_uid250_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => lowRangeB_uid295_pT4_uid250_sinPiZPolyEval_b, xout => ld_lowRangeB_uid295_pT4_uid250_sinPiZPolyEval_b_to_add0_uid295_uid298_pT4_uid250_sinPiZPolyEval_a_q, clk => clk, aclr => areset );
--add0_uid295_uid298_pT4_uid250_sinPiZPolyEval(BITJOIN,297)@26
add0_uid295_uid298_pT4_uid250_sinPiZPolyEval_q <= sumAHighB_uid297_pT4_uid250_sinPiZPolyEval_q & ld_lowRangeB_uid295_pT4_uid250_sinPiZPolyEval_b_to_add0_uid295_uid298_pT4_uid250_sinPiZPolyEval_a_q;
--R_uid299_pT4_uid250_sinPiZPolyEval(BITSELECT,298)@26
R_uid299_pT4_uid250_sinPiZPolyEval_in <= add0_uid295_uid298_pT4_uid250_sinPiZPolyEval_q(71 downto 0);
R_uid299_pT4_uid250_sinPiZPolyEval_b <= R_uid299_pT4_uid250_sinPiZPolyEval_in(71 downto 26);
--reg_R_uid299_pT4_uid250_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_1(REG,387)@26
reg_R_uid299_pT4_uid250_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid299_pT4_uid250_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_1_q <= "0000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_R_uid299_pT4_uid250_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_1_q <= R_uid299_pT4_uid250_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_nor(LOGICAL,1003)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_nor_b <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_nor_q <= not (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_nor_a or ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_nor_b);
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_mem_top(CONSTANT,999)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_mem_top_q <= "010010";
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmp(LOGICAL,1000)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmp_a <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_mem_top_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux_q);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmp_q <= "1" when ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmp_a = ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmp_b else "0";
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmpReg(REG,1001)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmpReg_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmp_q;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_sticky_ena(REG,1004)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_sticky_ena_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_enaAnd(LOGICAL,1005)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_enaAnd_a <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_enaAnd_b <= VCC_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_enaAnd_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_enaAnd_a and ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_enaAnd_b;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,995)
-- every=1, low=0, high=18, step=1, init=1
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_i = 17 THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_i - 18;
ELSE
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_i,5));
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdreg(REG,996)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdreg_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux(MUX,997)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux_s <= VCC_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux_s, ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdreg_q, ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem(DUALMEM,994)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_ia <= zAddr_uid64_fpCosPiTest_b;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_aa <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdreg_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_ab <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_rdmux_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 5,
numwords_a => 19,
width_b => 7,
widthad_b => 5,
numwords_b => 19,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_ia
);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_outputreg(DELAY,993)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_outputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_replace_mem_q, xout => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_outputreg_q, clk => clk, aclr => areset );
--memoryC1_uid226_sinPiZTableGenerator(LOOKUP,225)@26
memoryC1_uid226_sinPiZTableGenerator: PROCESS (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_outputreg_q)
BEGIN
-- Begin reserved scope level
CASE (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC1_uid226_sinPiZTableGenerator_a_outputreg_q) IS
WHEN "0000000" => memoryC1_uid226_sinPiZTableGenerator_q <= "00000000000000000000000000000000000000000000000110";
WHEN "0000001" => memoryC1_uid226_sinPiZTableGenerator_q <= "11111110101101010100010101111000000010001111100011";
WHEN "0000010" => memoryC1_uid226_sinPiZTableGenerator_q <= "11111101011010101001001010010110100010110001011110";
WHEN "0000011" => memoryC1_uid226_sinPiZTableGenerator_q <= "11111100000111111110111100000001110010011010000110";
WHEN "0000100" => memoryC1_uid226_sinPiZTableGenerator_q <= "11111010110101010110001001011111100110111111100011";
WHEN "0000101" => memoryC1_uid226_sinPiZTableGenerator_q <= "11111001100010101111010001010101001101111010110100";
WHEN "0000110" => memoryC1_uid226_sinPiZTableGenerator_q <= "11111000010000001010110010000110111110101011111000";
WHEN "0000111" => memoryC1_uid226_sinPiZTableGenerator_q <= "11110110111101101001001010011000001101011000111010";
WHEN "0001000" => memoryC1_uid226_sinPiZTableGenerator_q <= "11110101101011001010111000101010111101010010100111";
WHEN "0001001" => memoryC1_uid226_sinPiZTableGenerator_q <= "11110100011000110000011011011111110011010111001110";
WHEN "0001010" => memoryC1_uid226_sinPiZTableGenerator_q <= "11110011000110011010010001010101101000110101101101";
WHEN "0001011" => memoryC1_uid226_sinPiZTableGenerator_q <= "11110001110100001000111000101001011101110011011101";
WHEN "0001100" => memoryC1_uid226_sinPiZTableGenerator_q <= "11110000100001111100101111110110001011110001011001";
WHEN "0001101" => memoryC1_uid226_sinPiZTableGenerator_q <= "11101111001111110110010101010100011000010010100110";
WHEN "0001110" => memoryC1_uid226_sinPiZTableGenerator_q <= "11101101111101110110000111011010000111100011100100";
WHEN "0001111" => memoryC1_uid226_sinPiZTableGenerator_q <= "11101100101011111100100100011010101111000101000111";
WHEN "0010000" => memoryC1_uid226_sinPiZTableGenerator_q <= "11101011011010001010001010100110101000010011111000";
WHEN "0010001" => memoryC1_uid226_sinPiZTableGenerator_q <= "11101010001000011111011000001011000011010110000100";
WHEN "0010010" => memoryC1_uid226_sinPiZTableGenerator_q <= "11101000110110111100101011010001111001100111110010";
WHEN "0010011" => memoryC1_uid226_sinPiZTableGenerator_q <= "11100111100101100010100010000001100000101010111010";
WHEN "0010100" => memoryC1_uid226_sinPiZTableGenerator_q <= "11100110010100010001011010011100011100110101011100";
WHEN "0010101" => memoryC1_uid226_sinPiZTableGenerator_q <= "11100101000011001001110010100001010100000101101100";
WHEN "0010110" => memoryC1_uid226_sinPiZTableGenerator_q <= "11100011110010001100001000001010100000110110000000";
WHEN "0010111" => memoryC1_uid226_sinPiZTableGenerator_q <= "11100010100001011000111001001110000100110010111000";
WHEN "0011000" => memoryC1_uid226_sinPiZTableGenerator_q <= "11100001010000110000100011011101011011110011010110";
WHEN "0011001" => memoryC1_uid226_sinPiZTableGenerator_q <= "11100000000000010011100100100101001110110011000010";
WHEN "0011010" => memoryC1_uid226_sinPiZTableGenerator_q <= "11011110110000000010011010001101000110110000011100";
WHEN "0011011" => memoryC1_uid226_sinPiZTableGenerator_q <= "11011101011111111101100001110111011111101010000000";
WHEN "0011100" => memoryC1_uid226_sinPiZTableGenerator_q <= "11011100010000000101011001000001011011100001111010";
WHEN "0011101" => memoryC1_uid226_sinPiZTableGenerator_q <= "11011011000000011010011101000010010101100000110110";
WHEN "0011110" => memoryC1_uid226_sinPiZTableGenerator_q <= "11011001110000111101001011001011110100111101110010";
WHEN "0011111" => memoryC1_uid226_sinPiZTableGenerator_q <= "11011000100001101110000000101001100000101000010010";
WHEN "0100000" => memoryC1_uid226_sinPiZTableGenerator_q <= "11010111010010101101011010100000110001110011110001";
WHEN "0100001" => memoryC1_uid226_sinPiZTableGenerator_q <= "11010110000011111011110101110000100111100111110101";
WHEN "0100010" => memoryC1_uid226_sinPiZTableGenerator_q <= "11010100110101011001101111010001011010010011110011";
WHEN "0100011" => memoryC1_uid226_sinPiZTableGenerator_q <= "11010011100111000111100011110100101110100010111000";
WHEN "0100100" => memoryC1_uid226_sinPiZTableGenerator_q <= "11010010011001000101110000000101001000110111000111";
WHEN "0100101" => memoryC1_uid226_sinPiZTableGenerator_q <= "11010001001011010100110000100110000001000100101001";
WHEN "0100110" => memoryC1_uid226_sinPiZTableGenerator_q <= "11001111111101110101000001110011010101110010001110";
WHEN "0100111" => memoryC1_uid226_sinPiZTableGenerator_q <= "11001110110000100111000000000001011111111100011001";
WHEN "0101000" => memoryC1_uid226_sinPiZTableGenerator_q <= "11001101100011101011000111011101000110011100100000";
WHEN "0101001" => memoryC1_uid226_sinPiZTableGenerator_q <= "11001100010111000001110100001010110001110100101001";
WHEN "0101010" => memoryC1_uid226_sinPiZTableGenerator_q <= "11001011001010101011100010000110111111111100011001";
WHEN "0101011" => memoryC1_uid226_sinPiZTableGenerator_q <= "11001001111110101000101101000101110111110101110110";
WHEN "0101100" => memoryC1_uid226_sinPiZTableGenerator_q <= "11001000110010111001110000110010111101100001101110";
WHEN "0101101" => memoryC1_uid226_sinPiZTableGenerator_q <= "11000111100111011111001000110001000101111011110000";
WHEN "0101110" => memoryC1_uid226_sinPiZTableGenerator_q <= "11000110011100011001010000011010001010111001000100";
WHEN "0101111" => memoryC1_uid226_sinPiZTableGenerator_q <= "11000101010001101000100010111110111111001010110011";
WHEN "0110000" => memoryC1_uid226_sinPiZTableGenerator_q <= "11000100000111001101011011100111000010100110100100";
WHEN "0110001" => memoryC1_uid226_sinPiZTableGenerator_q <= "11000010111101001000010101010000010110010001100101";
WHEN "0110010" => memoryC1_uid226_sinPiZTableGenerator_q <= "11000001110011011001101010101111010000110001110001";
WHEN "0110011" => memoryC1_uid226_sinPiZTableGenerator_q <= "11000000101010000001110110101110010010100010001010";
WHEN "0110100" => memoryC1_uid226_sinPiZTableGenerator_q <= "10111111100001000001010011101101111010001101110100";
WHEN "0110101" => memoryC1_uid226_sinPiZTableGenerator_q <= "10111110011000011000011100000100011001001100111111";
WHEN "0110110" => memoryC1_uid226_sinPiZTableGenerator_q <= "10111101010000000111101001111101101000001001100111";
WHEN "0110111" => memoryC1_uid226_sinPiZTableGenerator_q <= "10111100001000001111010111011010111011101000011000";
WHEN "0111000" => memoryC1_uid226_sinPiZTableGenerator_q <= "10111011000000101111111110010010111000110100000100";
WHEN "0111001" => memoryC1_uid226_sinPiZTableGenerator_q <= "10111001111001101001111000010001001010010011000111";
WHEN "0111010" => memoryC1_uid226_sinPiZTableGenerator_q <= "10111000110010111101011110110110010100111101001111";
WHEN "0111011" => memoryC1_uid226_sinPiZTableGenerator_q <= "10110111101100101011001011010111101100111001001111";
WHEN "0111100" => memoryC1_uid226_sinPiZTableGenerator_q <= "10110110100110110011010110111111001010011111110011";
WHEN "0111101" => memoryC1_uid226_sinPiZTableGenerator_q <= "10110101100001010110011010101010111111100100001011";
WHEN "0111110" => memoryC1_uid226_sinPiZTableGenerator_q <= "10110100011100010100101111001101101100100000011010";
WHEN "0111111" => memoryC1_uid226_sinPiZTableGenerator_q <= "10110011010111101110101101001101110101101001000101";
WHEN "1000000" => memoryC1_uid226_sinPiZTableGenerator_q <= "10110010010011100100101101000101111000100111000101";
WHEN "1000001" => memoryC1_uid226_sinPiZTableGenerator_q <= "10110001001111110111000111000100000001110100110010";
WHEN "1000010" => memoryC1_uid226_sinPiZTableGenerator_q <= "10110000001100100110010011001010000010000100100001";
WHEN "1000011" => memoryC1_uid226_sinPiZTableGenerator_q <= "10101111001001110010101001001101000100001000011111";
WHEN "1000100" => memoryC1_uid226_sinPiZTableGenerator_q <= "10101110000111011100100000110101100010100101111011";
WHEN "1000101" => memoryC1_uid226_sinPiZTableGenerator_q <= "10101101000101100100010001011110111101101010011001";
WHEN "1000110" => memoryC1_uid226_sinPiZTableGenerator_q <= "10101100000100001010010010010111110001001000100100";
WHEN "1000111" => memoryC1_uid226_sinPiZTableGenerator_q <= "10101011000011001110111010100001001010011011010001";
WHEN "1001000" => memoryC1_uid226_sinPiZTableGenerator_q <= "10101010000010110010100000101110111110101110111011";
WHEN "1001001" => memoryC1_uid226_sinPiZTableGenerator_q <= "10101001000010110101011011100111100001010010001010";
WHEN "1001010" => memoryC1_uid226_sinPiZTableGenerator_q <= "10101000000011011000000001100011011001101001101101";
WHEN "1001011" => memoryC1_uid226_sinPiZTableGenerator_q <= "10100111000100011010101000101101011010001111110100";
WHEN "1001100" => memoryC1_uid226_sinPiZTableGenerator_q <= "10100110000101111101100111000010010110110101001010";
WHEN "1001101" => memoryC1_uid226_sinPiZTableGenerator_q <= "10100101001000000001010010010000111011001100101001";
WHEN "1001110" => memoryC1_uid226_sinPiZTableGenerator_q <= "10100100001010100101111111111001100001111011011000";
WHEN "1001111" => memoryC1_uid226_sinPiZTableGenerator_q <= "10100011001101101100000101001110001011001110111100";
WHEN "1010000" => memoryC1_uid226_sinPiZTableGenerator_q <= "10100010010001010011110111010010010011111110100100";
WHEN "1010001" => memoryC1_uid226_sinPiZTableGenerator_q <= "10100001010101011101101010111010101100101110000010";
WHEN "1010010" => memoryC1_uid226_sinPiZTableGenerator_q <= "10100000011010001001110100101101010000111010011101";
WHEN "1010011" => memoryC1_uid226_sinPiZTableGenerator_q <= "10011111011111011000101001000000111110001110111111";
WHEN "1010100" => memoryC1_uid226_sinPiZTableGenerator_q <= "10011110100101001010011011111101101011111101000010";
WHEN "1010101" => memoryC1_uid226_sinPiZTableGenerator_q <= "10011101101011011111100001011100000010100000001101";
WHEN "1010110" => memoryC1_uid226_sinPiZTableGenerator_q <= "10011100110010011000001101000101010011000110001101";
WHEN "1010111" => memoryC1_uid226_sinPiZTableGenerator_q <= "10011011111001110100110010010011001111011110111011";
WHEN "1011000" => memoryC1_uid226_sinPiZTableGenerator_q <= "10011011000001110101100100010000000001110100011101";
WHEN "1011001" => memoryC1_uid226_sinPiZTableGenerator_q <= "10011010001010011010110101110110000100101001100010";
WHEN "1011010" => memoryC1_uid226_sinPiZTableGenerator_q <= "10011001010011100100111001101111111011000001100001";
WHEN "1011011" => memoryC1_uid226_sinPiZTableGenerator_q <= "10011000011101010100000010011000001000101101011001";
WHEN "1011100" => memoryC1_uid226_sinPiZTableGenerator_q <= "10010111100111101000100001111001001010100001001100";
WHEN "1011101" => memoryC1_uid226_sinPiZTableGenerator_q <= "10010110110010100010101010001101001110110001111011";
WHEN "1011110" => memoryC1_uid226_sinPiZTableGenerator_q <= "10010101111110000010101100111110001101111011011100";
WHEN "1011111" => memoryC1_uid226_sinPiZTableGenerator_q <= "10010101001010001000111011100101100011001011100101";
WHEN "1100000" => memoryC1_uid226_sinPiZTableGenerator_q <= "10010100010110110101100111001100000101011000010000";
WHEN "1100001" => memoryC1_uid226_sinPiZTableGenerator_q <= "10010011100100001001000000101001111111111010110011";
WHEN "1100010" => memoryC1_uid226_sinPiZTableGenerator_q <= "10010010110010000011011000100110101011110110000011";
WHEN "1100011" => memoryC1_uid226_sinPiZTableGenerator_q <= "10010010000000100100111111011000101001000001000001";
WHEN "1100100" => memoryC1_uid226_sinPiZTableGenerator_q <= "10010001001111101110000101000101010111011100100101";
WHEN "1100101" => memoryC1_uid226_sinPiZTableGenerator_q <= "10010000011111011110111001100001010000110000001000";
WHEN "1100110" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001111101111110111101100001111100001101100011111";
WHEN "1100111" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001111000000111000101100100010000011111010101010";
WHEN "1101000" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001110010010100010001001011001010111110000100010";
WHEN "1101001" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001101100100110100010001100100011110001100110110";
WHEN "1101010" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001100110111101111010011100000110010111101110011";
WHEN "1101011" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001100001011010011011101011010000110101111000110";
WHEN "1101100" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001011011111100000111101001010011001011111101101";
WHEN "1101101" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001010110100011000000000011001110101000000001010";
WHEN "1101110" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001010001001111000110100011110100111011011010110";
WHEN "1101111" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001001100000000011100110011100111110000011010110";
WHEN "1110000" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001000110110111000100011000111000000001100101100";
WHEN "1110001" => memoryC1_uid226_sinPiZTableGenerator_q <= "10001000001110010111110110111100101010001100011100";
WHEN "1110010" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000111100110100001101110001011101000100010101000";
WHEN "1110011" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000110111111010110010100101111010011001100111001";
WHEN "1110100" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000110011000110101110110010000101000111111101001";
WHEN "1110101" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000101110011000000011110000110001011001010001101";
WHEN "1110110" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000101001101110110010111010011111001000001110011";
WHEN "1110111" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000100101001010111101100101011001011110111111001";
WHEN "1111000" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000100000101100100101000101010110010110110110011";
WHEN "1111001" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000011100010011101010101011110101111000111101111";
WHEN "1111010" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000011000000000001111101000000010000000010001101";
WHEN "1111011" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000010011110010010101000110101101111100100010110";
WHEN "1111100" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000001111101001111100010010010101110110011110010";
WHEN "1111101" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000001011100111000110010010111110010100110111110";
WHEN "1111110" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000000111101001110100001110010100000011000001001";
WHEN "1111111" => memoryC1_uid226_sinPiZTableGenerator_q <= "10000000011110010000111000111101011011000001000111";
WHEN OTHERS =>
memoryC1_uid226_sinPiZTableGenerator_q <= "00000000000000000000000000000000000000000000000110";
END CASE;
-- End reserved scope level
END PROCESS;
--cIncludingRoundingBit_uid252_sinPiZPolyEval(BITJOIN,251)@26
cIncludingRoundingBit_uid252_sinPiZPolyEval_q <= memoryC1_uid226_sinPiZTableGenerator_q & rndBit_uid245_sinPiZPolyEval_q;
--reg_cIncludingRoundingBit_uid252_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_0(REG,388)@26
reg_cIncludingRoundingBit_uid252_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid252_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_0_q <= "0000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_cIncludingRoundingBit_uid252_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid252_sinPiZPolyEval_q;
END IF;
END PROCESS;
--ts4_uid253_sinPiZPolyEval(ADD,252)@27
ts4_uid253_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((52 downto 52 => reg_cIncludingRoundingBit_uid252_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_0_q(51)) & reg_cIncludingRoundingBit_uid252_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_0_q);
ts4_uid253_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((52 downto 46 => reg_R_uid299_pT4_uid250_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_1_q(45)) & reg_R_uid299_pT4_uid250_sinPiZPolyEval_0_to_ts4_uid253_sinPiZPolyEval_1_q);
ts4_uid253_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts4_uid253_sinPiZPolyEval_a) + SIGNED(ts4_uid253_sinPiZPolyEval_b));
ts4_uid253_sinPiZPolyEval_q <= ts4_uid253_sinPiZPolyEval_o(52 downto 0);
--s4_uid254_sinPiZPolyEval(BITSELECT,253)@27
s4_uid254_sinPiZPolyEval_in <= ts4_uid253_sinPiZPolyEval_q;
s4_uid254_sinPiZPolyEval_b <= s4_uid254_sinPiZPolyEval_in(52 downto 1);
--yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval(BITSELECT,300)@27
yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_in <= s4_uid254_sinPiZPolyEval_b;
yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_b <= yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_in(51 downto 25);
--reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_9(REG,389)@27
reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_9: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_9_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_9_q <= yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_nor(LOGICAL,1092)
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_nor_b <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_nor_q <= not (ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_nor_a or ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_nor_b);
--ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_mem_top(CONSTANT,1088)
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_mem_top_q <= "010011";
--ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmp(LOGICAL,1089)
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmp_a <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_mem_top_q;
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux_q);
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmp_q <= "1" when ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmp_a = ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmp_b else "0";
--ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmpReg(REG,1090)
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmpReg_q <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmp_q;
END IF;
END PROCESS;
--ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_sticky_ena(REG,1093)
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_nor_q = "1") THEN
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_sticky_ena_q <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_enaAnd(LOGICAL,1094)
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_enaAnd_a <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_sticky_ena_q;
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_enaAnd_b <= VCC_q;
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_enaAnd_q <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_enaAnd_a and ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_enaAnd_b;
--xBottomBits_uid304_pT5_uid256_sinPiZPolyEval(BITSELECT,303)@6
xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_in <= zPPolyEval_uid65_fpCosPiTest_b(17 downto 0);
xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b <= xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_in(17 downto 0);
--ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt(COUNTER,1084)
-- every=1, low=0, high=19, step=1, init=1
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_i = 18 THEN
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_eq <= '1';
ELSE
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_eq = '1') THEN
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_i - 19;
ELSE
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_i <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_i,5));
--ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdreg(REG,1085)
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdreg_q <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux(MUX,1086)
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux_s <= VCC_q;
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux: PROCESS (ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux_s, ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdreg_q, ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_q)
BEGIN
CASE ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux_s IS
WHEN "0" => ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdreg_q;
WHEN "1" => ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux_q <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdcnt_q;
WHEN OTHERS => ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem(DUALMEM,1083)
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_reset0 <= areset;
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_ia <= xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b;
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_aa <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdreg_q;
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_ab <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_rdmux_q;
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 18,
widthad_a => 5,
numwords_a => 20,
width_b => 18,
widthad_b => 5,
numwords_b => 20,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_iq,
address_a => ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_aa,
data_a => ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_ia
);
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_q <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_iq(17 downto 0);
--ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_outputreg(DELAY,1082)
ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_outputreg : dspba_delay
GENERIC MAP ( width => 18, depth => 1 )
PORT MAP ( xin => ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_replace_mem_q, xout => ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_outputreg_q, clk => clk, aclr => areset );
--pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval(BITJOIN,305)@28
pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_q <= ld_xBottomBits_uid304_pT5_uid256_sinPiZPolyEval_b_to_pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_b_outputreg_q & STD_LOGIC_VECTOR((7 downto 1 => GND_q(0)) & GND_q);
--yBottomBits_uid303_pT5_uid256_sinPiZPolyEval(BITSELECT,302)@27
yBottomBits_uid303_pT5_uid256_sinPiZPolyEval_in <= s4_uid254_sinPiZPolyEval_b(24 downto 0);
yBottomBits_uid303_pT5_uid256_sinPiZPolyEval_b <= yBottomBits_uid303_pT5_uid256_sinPiZPolyEval_in(24 downto 0);
--ld_yBottomBits_uid303_pT5_uid256_sinPiZPolyEval_b_to_spad_yBottomBits_uid303_uid305_pT5_uid256_sinPiZPolyEval_a(DELAY,716)@27
ld_yBottomBits_uid303_pT5_uid256_sinPiZPolyEval_b_to_spad_yBottomBits_uid303_uid305_pT5_uid256_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 25, depth => 1 )
PORT MAP ( xin => yBottomBits_uid303_pT5_uid256_sinPiZPolyEval_b, xout => ld_yBottomBits_uid303_pT5_uid256_sinPiZPolyEval_b_to_spad_yBottomBits_uid303_uid305_pT5_uid256_sinPiZPolyEval_a_q, clk => clk, aclr => areset );
--spad_yBottomBits_uid303_uid305_pT5_uid256_sinPiZPolyEval(BITJOIN,304)@28
spad_yBottomBits_uid303_uid305_pT5_uid256_sinPiZPolyEval_q <= GND_q & ld_yBottomBits_uid303_pT5_uid256_sinPiZPolyEval_b_to_spad_yBottomBits_uid303_uid305_pT5_uid256_sinPiZPolyEval_a_q;
--pad_yBottomBits_uid303_uid307_pT5_uid256_sinPiZPolyEval(BITJOIN,306)@28
pad_yBottomBits_uid303_uid307_pT5_uid256_sinPiZPolyEval_q <= spad_yBottomBits_uid303_uid305_pT5_uid256_sinPiZPolyEval_q & GND_q;
--reg_pad_yBottomBits_uid303_uid307_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_6(REG,390)@28
reg_pad_yBottomBits_uid303_uid307_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_6: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_pad_yBottomBits_uid303_uid307_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_6_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_pad_yBottomBits_uid303_uid307_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_6_q <= pad_yBottomBits_uid303_uid307_pT5_uid256_sinPiZPolyEval_q;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_nor(LOGICAL,1079)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_nor_b <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_nor_q <= not (ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_nor_a or ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_nor_b);
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_mem_top(CONSTANT,1075)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_mem_top_q <= "010100";
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmp(LOGICAL,1076)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmp_a <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_mem_top_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux_q);
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmp_q <= "1" when ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmp_a = ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmp_b else "0";
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmpReg(REG,1077)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmpReg_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmp_q;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_sticky_ena(REG,1080)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_nor_q = "1") THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_sticky_ena_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_enaAnd(LOGICAL,1081)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_enaAnd_a <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_sticky_ena_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_enaAnd_b <= VCC_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_enaAnd_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_enaAnd_a and ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_enaAnd_b;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt(COUNTER,1071)
-- every=1, low=0, high=20, step=1, init=1
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_i = 19 THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_eq <= '1';
ELSE
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_i - 20;
ELSE
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_i <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_i,5));
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdreg(REG,1072)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdreg_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux(MUX,1073)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux_s <= VCC_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux_s, ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdreg_q, ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_q)
BEGIN
CASE ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux_s IS
WHEN "0" => ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdreg_q;
WHEN "1" => ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdcnt_q;
WHEN OTHERS => ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem(DUALMEM,1070)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_reset0 <= areset;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_ia <= zPPolyEval_uid65_fpCosPiTest_b;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_aa <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdreg_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_ab <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_rdmux_q;
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 45,
widthad_a => 5,
numwords_a => 21,
width_b => 45,
widthad_b => 5,
numwords_b => 21,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_iq,
address_a => ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_aa,
data_a => ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_ia
);
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_q <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_iq(44 downto 0);
--ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_outputreg(DELAY,1069)
ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_outputreg : dspba_delay
GENERIC MAP ( width => 45, depth => 1 )
PORT MAP ( xin => ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_replace_mem_q, xout => ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_outputreg_q, clk => clk, aclr => areset );
--xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval(BITSELECT,299)@29
xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_in <= ld_zPPolyEval_uid65_fpCosPiTest_b_to_xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_a_outputreg_q;
xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_b <= xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_in(44 downto 18);
--multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma(CHAINMULTADD,346)@29
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_p(0) <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_a(0) * multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_c(0);
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_p(1) <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_a(1) * multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_c(1);
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_w(0) <= RESIZE(multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_p(0),56);
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_w(1) <= RESIZE(multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_p(1),56);
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_x(0) <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_w(0);
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_x(1) <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_w(1);
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_y(0) <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_s(1) + multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_x(0);
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_y(1) <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_x(1);
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_chainmultadd: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_a <= (others => (others => '0'));
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_c <= (others => (others => '0'));
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_s <= (others => (others => '0'));
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_a(0) <= SIGNED(RESIZE(UNSIGNED(xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_b),28));
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_a(1) <= SIGNED(RESIZE(UNSIGNED(pad_xBottomBits_uid304_uid306_pT5_uid256_sinPiZPolyEval_q),28));
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_c(0) <= SIGNED(RESIZE(SIGNED(reg_pad_yBottomBits_uid303_uid307_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_6_q),27));
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_c(1) <= SIGNED(RESIZE(SIGNED(reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_9_q),27));
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_s(0) <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_y(0);
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_s(1) <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_y(1);
END IF;
END PROCESS;
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_s0 <= STD_LOGIC_VECTOR(RESIZE(multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_s(0),55));
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_q <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_s0;
END IF;
END PROCESS;
--multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval(BITSELECT,308)@32
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_in <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_cma_q;
multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_b <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_in(54 downto 1);
--highBBits_uid311_pT5_uid256_sinPiZPolyEval(BITSELECT,310)@32
highBBits_uid311_pT5_uid256_sinPiZPolyEval_in <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_b;
highBBits_uid311_pT5_uid256_sinPiZPolyEval_b <= highBBits_uid311_pT5_uid256_sinPiZPolyEval_in(53 downto 25);
--reg_highBBits_uid311_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_1(REG,392)@32
reg_highBBits_uid311_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_highBBits_uid311_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_1_q <= "00000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_highBBits_uid311_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_1_q <= highBBits_uid311_pT5_uid256_sinPiZPolyEval_b;
END IF;
END PROCESS;
--reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_1(REG,391)@27
reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_1_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_1_q <= yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_1_q_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_b(DELAY,713)@28
ld_reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_1_q_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_b : dspba_delay
GENERIC MAP ( width => 27, depth => 1 )
PORT MAP ( xin => reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_1_q, xout => ld_reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_1_q_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_b_q, clk => clk, aclr => areset );
--topProd_uid302_pT5_uid256_sinPiZPolyEval(MULT,301)@29
topProd_uid302_pT5_uid256_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(topProd_uid302_pT5_uid256_sinPiZPolyEval_a),28)) * SIGNED(topProd_uid302_pT5_uid256_sinPiZPolyEval_b);
topProd_uid302_pT5_uid256_sinPiZPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid302_pT5_uid256_sinPiZPolyEval_a <= (others => '0');
topProd_uid302_pT5_uid256_sinPiZPolyEval_b <= (others => '0');
topProd_uid302_pT5_uid256_sinPiZPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
topProd_uid302_pT5_uid256_sinPiZPolyEval_a <= xTop27Bits_uid300_pT5_uid256_sinPiZPolyEval_b;
topProd_uid302_pT5_uid256_sinPiZPolyEval_b <= ld_reg_yTop27Bits_uid301_pT5_uid256_sinPiZPolyEval_0_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_1_q_to_topProd_uid302_pT5_uid256_sinPiZPolyEval_b_q;
topProd_uid302_pT5_uid256_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(topProd_uid302_pT5_uid256_sinPiZPolyEval_pr,54));
END IF;
END PROCESS;
topProd_uid302_pT5_uid256_sinPiZPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
topProd_uid302_pT5_uid256_sinPiZPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
topProd_uid302_pT5_uid256_sinPiZPolyEval_q <= topProd_uid302_pT5_uid256_sinPiZPolyEval_s1;
END IF;
END PROCESS;
--reg_topProd_uid302_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_0(REG,393)@32
reg_topProd_uid302_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_topProd_uid302_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_0_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_topProd_uid302_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_0_q <= topProd_uid302_pT5_uid256_sinPiZPolyEval_q;
END IF;
END PROCESS;
--sumAHighB_uid312_pT5_uid256_sinPiZPolyEval(ADD,311)@33
sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((54 downto 54 => reg_topProd_uid302_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_0_q(53)) & reg_topProd_uid302_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_0_q);
sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((54 downto 29 => reg_highBBits_uid311_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_1_q(28)) & reg_highBBits_uid311_pT5_uid256_sinPiZPolyEval_0_to_sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_1_q);
sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_b));
sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_q <= sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_o(54 downto 0);
--lowRangeB_uid310_pT5_uid256_sinPiZPolyEval(BITSELECT,309)@32
lowRangeB_uid310_pT5_uid256_sinPiZPolyEval_in <= multSumOfTwo27_uid305_pT5_uid256_sinPiZPolyEval_b(24 downto 0);
lowRangeB_uid310_pT5_uid256_sinPiZPolyEval_b <= lowRangeB_uid310_pT5_uid256_sinPiZPolyEval_in(24 downto 0);
--ld_lowRangeB_uid310_pT5_uid256_sinPiZPolyEval_b_to_add0_uid310_uid313_pT5_uid256_sinPiZPolyEval_a(DELAY,724)@32
ld_lowRangeB_uid310_pT5_uid256_sinPiZPolyEval_b_to_add0_uid310_uid313_pT5_uid256_sinPiZPolyEval_a : dspba_delay
GENERIC MAP ( width => 25, depth => 1 )
PORT MAP ( xin => lowRangeB_uid310_pT5_uid256_sinPiZPolyEval_b, xout => ld_lowRangeB_uid310_pT5_uid256_sinPiZPolyEval_b_to_add0_uid310_uid313_pT5_uid256_sinPiZPolyEval_a_q, clk => clk, aclr => areset );
--add0_uid310_uid313_pT5_uid256_sinPiZPolyEval(BITJOIN,312)@33
add0_uid310_uid313_pT5_uid256_sinPiZPolyEval_q <= sumAHighB_uid312_pT5_uid256_sinPiZPolyEval_q & ld_lowRangeB_uid310_pT5_uid256_sinPiZPolyEval_b_to_add0_uid310_uid313_pT5_uid256_sinPiZPolyEval_a_q;
--R_uid314_pT5_uid256_sinPiZPolyEval(BITSELECT,313)@33
R_uid314_pT5_uid256_sinPiZPolyEval_in <= add0_uid310_uid313_pT5_uid256_sinPiZPolyEval_q(78 downto 0);
R_uid314_pT5_uid256_sinPiZPolyEval_b <= R_uid314_pT5_uid256_sinPiZPolyEval_in(78 downto 25);
--reg_R_uid314_pT5_uid256_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_1(REG,394)@33
reg_R_uid314_pT5_uid256_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_R_uid314_pT5_uid256_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_1_q <= "000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_R_uid314_pT5_uid256_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_1_q <= R_uid314_pT5_uid256_sinPiZPolyEval_b;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_nor(LOGICAL,990)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_nor_b <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_nor_q <= not (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_nor_a or ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_nor_b);
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_mem_top(CONSTANT,986)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_mem_top_q <= "011001";
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmp(LOGICAL,987)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmp_a <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_mem_top_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux_q);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmp_q <= "1" when ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmp_a = ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmp_b else "0";
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmpReg(REG,988)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmpReg_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmp_q;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_sticky_ena(REG,991)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_nor_q = "1") THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_sticky_ena_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_enaAnd(LOGICAL,992)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_enaAnd_a <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_sticky_ena_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_enaAnd_b <= VCC_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_enaAnd_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_enaAnd_a and ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_enaAnd_b;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt(COUNTER,982)
-- every=1, low=0, high=25, step=1, init=1
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_i = 24 THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_eq <= '1';
ELSE
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_eq = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_i - 25;
ELSE
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_i <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_i,5));
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdreg(REG,983)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdreg_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux(MUX,984)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux_s <= VCC_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux: PROCESS (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux_s, ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdreg_q, ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_q)
BEGIN
CASE ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux_s IS
WHEN "0" => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdreg_q;
WHEN "1" => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdcnt_q;
WHEN OTHERS => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem(DUALMEM,981)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_reset0 <= areset;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_ia <= zAddr_uid64_fpCosPiTest_b;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_aa <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdreg_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_ab <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_rdmux_q;
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 5,
numwords_a => 26,
width_b => 7,
widthad_b => 5,
numwords_b => 26,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_iq,
address_a => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_aa,
data_a => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_ia
);
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_q <= ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_iq(6 downto 0);
--ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_outputreg(DELAY,980)
ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_outputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_replace_mem_q, xout => ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_outputreg_q, clk => clk, aclr => areset );
--memoryC0_uid225_sinPiZTableGenerator(LOOKUP,224)@33
memoryC0_uid225_sinPiZTableGenerator: PROCESS (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_outputreg_q)
BEGIN
-- Begin reserved scope level
CASE (ld_zAddr_uid64_fpCosPiTest_b_to_memoryC0_uid225_sinPiZTableGenerator_a_outputreg_q) IS
WHEN "0000000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010010000111111011010101000100010000101101000110001000";
WHEN "0000001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010010000111010001111111001101111011000111100001001010";
WHEN "0000010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010010000101010101111101111010001101100110011111100100";
WHEN "0000011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010010000010000111010001110111000001110010011001110001";
WHEN "0000100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010001111101100101111100010000110111011000000101000010";
WHEN "0000101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010001110111110001111110110010110011100111000110011101";
WHEN "0000110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010001110000101011011011100110100000100010100111010101";
WHEN "0000111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010001101000010010010101010100001100000100101011101101";
WHEN "0001000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010001011110100110101111000010100110110100001011000010";
WHEN "0001001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010001010011101000101100010111000010101101001011110101";
WHEN "0001010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010001000111011000010001010101010001011100000010111010";
WHEN "0001011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010000111001110101100010011111100010101010110110110111";
WHEN "0001100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010000101011000000100100110110100010000001101000110010";
WHEN "0001101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010000011010111001011101111001010100111001000011000110";
WHEN "0001110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110010000001001100000010011100101010111111111101111100110";
WHEN "0001111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001111110110110101001100010110011100110010010101101111";
WHEN "0010000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001111100010111000001111000110100110100110000010101111";
WHEN "0010001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001111001101101001100011001110000111100101111100011100";
WHEN "0010010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001110110111001001010000100011011101100011000000101111";
WHEN "0010011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001110011111010111011111011011001110010110110010111000";
WHEN "0010100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001110000110010100011000101000000100011000111000100110";
WHEN "0010101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001101101100000000000101011010101010100111001000011100";
WHEN "0010110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001101010000011010101111100001101000100000101011011110";
WHEN "0010111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001100110011100100100001001001011101110011110100001011";
WHEN "0011000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001100010101011101100100111100011101111110101100100111";
WHEN "0011001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001011110110000110000110000010101011100010111110000011";
WHEN "0011010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001011010101011110010000000001110011001100010100001001";
WHEN "0011011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001010110011100110001110111101000110101001111110010101";
WHEN "0011100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001010010000011110001111010101010111011011010001011111";
WHEN "0011101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001001101100000110011110001000110001001111001100110001";
WHEN "0011110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001001000110011111001000110010110100010111000011111111";
WHEN "0011111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110001000011111101000011101001100001111101100010010011001";
WHEN "0100000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110000111110111100010101001101010111010101001011000110001";
WHEN "0100001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110000111001110001101111101000001101110110110001001100100";
WHEN "0100010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110000110100011101010100110100000100001100111000110001110";
WHEN "0100011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110000101110111111000110101110011111101010000010000111000";
WHEN "0100100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110000101001010111000111011000101011010001011010101011100";
WHEN "0100101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110000100011100101011000110111010110111110001001101100111";
WHEN "0100110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110000011101101001111101010010110110101000111000011000010";
WHEN "0100111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110000010111100100110110110111000001001011110110011001101";
WHEN "0101000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110000010001010110000111110011001111100101011011000101100";
WHEN "0101001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110000001010111101110010011010011011111001000011101001111";
WHEN "0101010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0110000000100011011111001000011000000001110101111000110101";
WHEN "0101011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101111111101110000011110000110110101110000111000001001000";
WHEN "0101100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101111110110111011100100000011010011101000101101101101111";
WHEN "0101101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101111101111111101001101011001001101111001001010100111010";
WHEN "0101110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101111101000110101011100101100110100011000001100101000111";
WHEN "0101111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101111100001100100010100100101110001100110101011111100110";
WHEN "0110000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101111011010001001110111101111001001100110110011000001101";
WHEN "0110001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101111010010100110001000110111011000110000110111110111111";
WHEN "0110010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101111001010111001001010110000010010100110110110111111101";
WHEN "0110011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101111000011000011000000001111000000100110010000101101101";
WHEN "0110100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101110111011000011101100001100000000111000101001011011010";
WHEN "0110101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101110110010111011010001100011000101000010101101011001001";
WHEN "0110110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101110101010101001110011010011010000110001111000101001011";
WHEN "0110111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101110100010001111010100011110111000101000100011101001111";
WHEN "0111000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101110011001101011111000001011100000101000110101010111101";
WHEN "0111001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101110010000111111100001100001111010111101111011010000110";
WHEN "0111010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101110001000001010010011101110000110100100001000000010111";
WHEN "0111011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101101111111001100010001111111001101101111011001101100100";
WHEN "0111100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101101110110000101011111100111100100110000100111011101101";
WHEN "0111101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101101101100110101111111111100101000011001011000100010101";
WHEN "0111110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101101100011011101110110010110111100011110100100000110011";
WHEN "0111111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101101011001111101000110010010001010011001011011010110110";
WHEN "1000000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101101010000010011110011001100111111100111011110011001101";
WHEN "1000001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101101000110100010000000101001001100001000111100100001001";
WHEN "1000010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101100111100100111110010001011100000111110000000101011101";
WHEN "1000011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101100110010100101001011011011101110100010101011000001110";
WHEN "1000100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101100101000011010010000000100100011001001010111111110011";
WHEN "1000101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101100011110000111000011110011101001010100010101110100101";
WHEN "1000110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101100010011101011101010011001100110001101101001100010111";
WHEN "1000111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101100001001001000000111101001110111111110000011100100111";
WHEN "1001000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101011111110011100011111011010110100000010100101010111001";
WHEN "1001001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101011110011101000110101100101100101100000111000011110001";
WHEN "1001010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101011101000101101001110000110001011011010011000000110010";
WHEN "1001011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101011011101101001101100111011010110111110001101101101010";
WHEN "1001100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101011010010011110010110000110101001111010000001101101100";
WHEN "1001101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101011000111001011001101101100010100101001100000111100110";
WHEN "1001110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101010111011110000010111110011010100100100110111110110011";
WHEN "1001111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101010110000001101111000100101010010001110000100000110101";
WHEN "1010000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101010100100100011110100001110011111011100111101101011110";
WHEN "1010001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101010011000110010001110111101110101101010011000000111111";
WHEN "1010010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101010001100111001001101000100110011111001111100111000001";
WHEN "1010011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101010000000111000110010110111011101000010111111101010001";
WHEN "1010100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101001110100110001000100101100010101111000001101101010100";
WHEN "1010101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101001101000100010000110111100100011001110011000100010010";
WHEN "1010110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101001011100001011111110000011101000000001111110000000000";
WHEN "1010111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101001001111101110101110011111100011011011101101000101110";
WHEN "1011000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101001000011001010011100110000101110110100001001110110000";
WHEN "1011001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101000110110011111001101011001111011110110010000011100000";
WHEN "1011010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101000101001101101000101000000010010100000111000101001110";
WHEN "1011011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101000011100110100001000001011001111000111011010101001101";
WHEN "1011100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101000001111110100011011100100100000010001010101111111000";
WHEN "1011101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0101000000010101110000011111000000100111000111011110010110";
WHEN "1011110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100111110101100001000101110100001010001000111101001001101";
WHEN "1011111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100111101000001101100110001001001001011001011110100011010";
WHEN "1100000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100111011010110011101001101001100110001011110001011110000";
WHEN "1100001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100111001101010011010101001010001100000101010101000000111";
WHEN "1100010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100110111111101100101101100001101100101001111110101000001";
WHEN "1100011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100110110001111111110111101000111101010101001011110111000";
WHEN "1100100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100110100100001100111000011010110101010010011110001011110";
WHEN "1100101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100110010110010011110100110100001011010101000001111000001";
WHEN "1100110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100110001000010100110001110011110011101110100000111111001";
WHEN "1100111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100101111010001111110100011010011110000101000011010111010";
WHEN "1101000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100101101100000101000001101010110011001000011100110100101";
WHEN "1101001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100101011101110100011110101001010010100110101010011100110";
WHEN "1101010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100101001111011110010000011100010000111111100000000100011";
WHEN "1101011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100101000001000010011100001011110101010111100110111011100";
WHEN "1101100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100100110010100001000111000001110111001010101110101010001";
WHEN "1101101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100100100011111010010110001001111011111101010001100000100";
WHEN "1101110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100100010101001110001110110001010101001101001100111101111";
WHEN "1101111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100100000110011100110110000110111110000010001111110011101";
WHEN "1110000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100011110111100110010001011011011000111101011110100101010";
WHEN "1110001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100011101000101010100110000000101101101000001111101101101";
WHEN "1110010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100011011001101001111001001010100110100010100000001010111";
WHEN "1110011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100011001010100100010000001110001110110000100001110111001";
WHEN "1110100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100010111011011001110000100010001111101000000100110100000";
WHEN "1110101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100010101100001010011111011110101110011100111100001100101";
WHEN "1110110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100010011100110110100010011101001010001101000000010101011";
WHEN "1110111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100010001101011101111110111000011001001011101110101101100";
WHEN "1111000" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100001111110000000111010001100100110101101001001001010110";
WHEN "1111001" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100001101110011111011001110111010000110000010101010100001";
WHEN "1111010" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100001011110111001100011010111000101101001011101010010011";
WHEN "1111011" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100001001111001111011100001100000001101011010010111101001";
WHEN "1111100" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100000111111100001001001110111001100110000010110101011110";
WHEN "1111101" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100000101111101110110001111010111000000011100010110001010";
WHEN "1111110" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100000011111111000011001111010011011101000011100101001111";
WHEN "1111111" => memoryC0_uid225_sinPiZTableGenerator_q <= "0100000001111111110000111011010010100000011001101000010011";
WHEN OTHERS =>
memoryC0_uid225_sinPiZTableGenerator_q <= "0110010010000111111011010101000100010000101101000110001000";
END CASE;
-- End reserved scope level
END PROCESS;
--rndBit_uid257_sinPiZPolyEval(CONSTANT,256)
rndBit_uid257_sinPiZPolyEval_q <= "001";
--cIncludingRoundingBit_uid258_sinPiZPolyEval(BITJOIN,257)@33
cIncludingRoundingBit_uid258_sinPiZPolyEval_q <= memoryC0_uid225_sinPiZTableGenerator_q & rndBit_uid257_sinPiZPolyEval_q;
--reg_cIncludingRoundingBit_uid258_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_0(REG,395)@33
reg_cIncludingRoundingBit_uid258_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_cIncludingRoundingBit_uid258_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_0_q <= "0000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_cIncludingRoundingBit_uid258_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_0_q <= cIncludingRoundingBit_uid258_sinPiZPolyEval_q;
END IF;
END PROCESS;
--ts5_uid259_sinPiZPolyEval(ADD,258)@34
ts5_uid259_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((61 downto 61 => reg_cIncludingRoundingBit_uid258_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_0_q(60)) & reg_cIncludingRoundingBit_uid258_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_0_q);
ts5_uid259_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((61 downto 54 => reg_R_uid314_pT5_uid256_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_1_q(53)) & reg_R_uid314_pT5_uid256_sinPiZPolyEval_0_to_ts5_uid259_sinPiZPolyEval_1_q);
ts5_uid259_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(ts5_uid259_sinPiZPolyEval_a) + SIGNED(ts5_uid259_sinPiZPolyEval_b));
ts5_uid259_sinPiZPolyEval_q <= ts5_uid259_sinPiZPolyEval_o(61 downto 0);
--s5_uid260_sinPiZPolyEval(BITSELECT,259)@34
s5_uid260_sinPiZPolyEval_in <= ts5_uid259_sinPiZPolyEval_q;
s5_uid260_sinPiZPolyEval_b <= s5_uid260_sinPiZPolyEval_in(61 downto 1);
--fxpSinRes_uid67_fpCosPiTest(BITSELECT,66)@34
fxpSinRes_uid67_fpCosPiTest_in <= s5_uid260_sinPiZPolyEval_b(58 downto 0);
fxpSinRes_uid67_fpCosPiTest_b <= fxpSinRes_uid67_fpCosPiTest_in(58 downto 5);
--mul2xSinRes_uid68_fpCosPiTest_b_1(BITSELECT,317)@34
mul2xSinRes_uid68_fpCosPiTest_b_1_in <= fxpSinRes_uid67_fpCosPiTest_b;
mul2xSinRes_uid68_fpCosPiTest_b_1_b <= mul2xSinRes_uid68_fpCosPiTest_b_1_in(53 downto 27);
--reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_1(REG,400)@34
reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_1_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_1_q <= mul2xSinRes_uid68_fpCosPiTest_b_1_b;
END IF;
END PROCESS;
--ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_nor(LOGICAL,877)
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_nor_b <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_sticky_ena_q;
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_nor_q <= not (ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_nor_a or ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_nor_b);
--ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_mem_top(CONSTANT,873)
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_mem_top_q <= "010110";
--ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmp(LOGICAL,874)
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmp_a <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_mem_top_q;
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_q);
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmp_q <= "1" when ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmp_a = ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmp_b else "0";
--ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmpReg(REG,875)
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmpReg_q <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmp_q;
END IF;
END PROCESS;
--ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_sticky_ena(REG,878)
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_nor_q = "1") THEN
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_sticky_ena_q <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_enaAnd(LOGICAL,879)
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_enaAnd_a <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_sticky_ena_q;
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_enaAnd_b <= VCC_q;
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_enaAnd_q <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_enaAnd_a and ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_enaAnd_b;
--LeftShiftStage277dto0_uid220_alignedZ_uid59_fpCosPiTest(BITSELECT,219)@9
LeftShiftStage277dto0_uid220_alignedZ_uid59_fpCosPiTest_in <= leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_q(77 downto 0);
LeftShiftStage277dto0_uid220_alignedZ_uid59_fpCosPiTest_b <= LeftShiftStage277dto0_uid220_alignedZ_uid59_fpCosPiTest_in(77 downto 0);
--leftShiftStage3Idx1_uid221_alignedZ_uid59_fpCosPiTest(BITJOIN,220)@9
leftShiftStage3Idx1_uid221_alignedZ_uid59_fpCosPiTest_q <= LeftShiftStage277dto0_uid220_alignedZ_uid59_fpCosPiTest_b & GND_q;
--LeftShiftStage172dto0_uid215_alignedZ_uid59_fpCosPiTest(BITSELECT,214)@9
LeftShiftStage172dto0_uid215_alignedZ_uid59_fpCosPiTest_in <= leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_q(72 downto 0);
LeftShiftStage172dto0_uid215_alignedZ_uid59_fpCosPiTest_b <= LeftShiftStage172dto0_uid215_alignedZ_uid59_fpCosPiTest_in(72 downto 0);
--leftShiftStage2Idx3_uid216_alignedZ_uid59_fpCosPiTest(BITJOIN,215)@9
leftShiftStage2Idx3_uid216_alignedZ_uid59_fpCosPiTest_q <= LeftShiftStage172dto0_uid215_alignedZ_uid59_fpCosPiTest_b & leftShiftStage2Idx3Pad6_uid133_fxpX_uid43_fpCosPiTest_q;
--LeftShiftStage174dto0_uid212_alignedZ_uid59_fpCosPiTest(BITSELECT,211)@9
LeftShiftStage174dto0_uid212_alignedZ_uid59_fpCosPiTest_in <= leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_q(74 downto 0);
LeftShiftStage174dto0_uid212_alignedZ_uid59_fpCosPiTest_b <= LeftShiftStage174dto0_uid212_alignedZ_uid59_fpCosPiTest_in(74 downto 0);
--leftShiftStage2Idx2_uid213_alignedZ_uid59_fpCosPiTest(BITJOIN,212)@9
leftShiftStage2Idx2_uid213_alignedZ_uid59_fpCosPiTest_q <= LeftShiftStage174dto0_uid212_alignedZ_uid59_fpCosPiTest_b & leftShiftStage2Idx2Pad4_uid130_fxpX_uid43_fpCosPiTest_q;
--LeftShiftStage176dto0_uid209_alignedZ_uid59_fpCosPiTest(BITSELECT,208)@9
LeftShiftStage176dto0_uid209_alignedZ_uid59_fpCosPiTest_in <= leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_q(76 downto 0);
LeftShiftStage176dto0_uid209_alignedZ_uid59_fpCosPiTest_b <= LeftShiftStage176dto0_uid209_alignedZ_uid59_fpCosPiTest_in(76 downto 0);
--leftShiftStage2Idx1_uid210_alignedZ_uid59_fpCosPiTest(BITJOIN,209)@9
leftShiftStage2Idx1_uid210_alignedZ_uid59_fpCosPiTest_q <= LeftShiftStage176dto0_uid209_alignedZ_uid59_fpCosPiTest_b & leftShiftStage2Idx1Pad2_uid127_fxpX_uid43_fpCosPiTest_q;
--LeftShiftStage054dto0_uid204_alignedZ_uid59_fpCosPiTest(BITSELECT,203)@9
LeftShiftStage054dto0_uid204_alignedZ_uid59_fpCosPiTest_in <= leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_q(54 downto 0);
LeftShiftStage054dto0_uid204_alignedZ_uid59_fpCosPiTest_b <= LeftShiftStage054dto0_uid204_alignedZ_uid59_fpCosPiTest_in(54 downto 0);
--leftShiftStage1Idx3_uid205_alignedZ_uid59_fpCosPiTest(BITJOIN,204)@9
leftShiftStage1Idx3_uid205_alignedZ_uid59_fpCosPiTest_q <= LeftShiftStage054dto0_uid204_alignedZ_uid59_fpCosPiTest_b & leftShiftStage1Idx3Pad24_uid122_fxpX_uid43_fpCosPiTest_q;
--LeftShiftStage062dto0_uid201_alignedZ_uid59_fpCosPiTest(BITSELECT,200)@9
LeftShiftStage062dto0_uid201_alignedZ_uid59_fpCosPiTest_in <= leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_q(62 downto 0);
LeftShiftStage062dto0_uid201_alignedZ_uid59_fpCosPiTest_b <= LeftShiftStage062dto0_uid201_alignedZ_uid59_fpCosPiTest_in(62 downto 0);
--leftShiftStage1Idx2_uid202_alignedZ_uid59_fpCosPiTest(BITJOIN,201)@9
leftShiftStage1Idx2_uid202_alignedZ_uid59_fpCosPiTest_q <= LeftShiftStage062dto0_uid201_alignedZ_uid59_fpCosPiTest_b & leftShiftStage1Idx2Pad16_uid119_fxpX_uid43_fpCosPiTest_q;
--LeftShiftStage070dto0_uid198_alignedZ_uid59_fpCosPiTest(BITSELECT,197)@9
LeftShiftStage070dto0_uid198_alignedZ_uid59_fpCosPiTest_in <= leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_q(70 downto 0);
LeftShiftStage070dto0_uid198_alignedZ_uid59_fpCosPiTest_b <= LeftShiftStage070dto0_uid198_alignedZ_uid59_fpCosPiTest_in(70 downto 0);
--leftShiftStage1Idx1_uid199_alignedZ_uid59_fpCosPiTest(BITJOIN,198)@9
leftShiftStage1Idx1_uid199_alignedZ_uid59_fpCosPiTest_q <= LeftShiftStage070dto0_uid198_alignedZ_uid59_fpCosPiTest_b & leftShiftStage1Idx1Pad8_uid116_fxpX_uid43_fpCosPiTest_q;
--ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_nor(LOGICAL,954)
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_nor_b <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_sticky_ena_q;
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_nor_q <= not (ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_nor_a or ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_nor_b);
--ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_mem_top(CONSTANT,950)
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_mem_top_q <= "010";
--ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmp(LOGICAL,951)
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmp_a <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_mem_top_q;
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux_q);
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmp_q <= "1" when ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmp_a = ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmp_b else "0";
--ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmpReg(REG,952)
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmpReg_q <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmp_q;
END IF;
END PROCESS;
--ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_sticky_ena(REG,955)
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_nor_q = "1") THEN
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_sticky_ena_q <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_enaAnd(LOGICAL,956)
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_enaAnd_a <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_sticky_ena_q;
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_enaAnd_b <= VCC_q;
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_enaAnd_q <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_enaAnd_a and ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_enaAnd_b;
--vStage_uid148_lzcZ_uid58_fpCosPiTest(BITSELECT,147)@5
vStage_uid148_lzcZ_uid58_fpCosPiTest_in <= z_uid56_fpCosPiTest_b(14 downto 0);
vStage_uid148_lzcZ_uid58_fpCosPiTest_b <= vStage_uid148_lzcZ_uid58_fpCosPiTest_in(14 downto 0);
--ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt(COUNTER,946)
-- every=1, low=0, high=2, step=1, init=1
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,2);
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_i = 1 THEN
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_i <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_i - 2;
ELSE
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_i <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_i,2));
--ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdreg(REG,947)
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdreg_q <= "00";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdreg_q <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux(MUX,948)
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux_s <= VCC_q;
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux: PROCESS (ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux_s, ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdreg_q, ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux_q <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux_q <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem(DUALMEM,957)
ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_ia <= vStage_uid148_lzcZ_uid58_fpCosPiTest_b;
ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_aa <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdreg_q;
ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_ab <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux_q;
ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 2,
numwords_a => 3,
width_b => 15,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_iq,
address_a => ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_aa,
data_a => ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_ia
);
ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_q <= ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_iq(14 downto 0);
--leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest(BITJOIN,192)@9
leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_q <= ld_vStage_uid148_lzcZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_b_replace_mem_q & leftShiftStage0Idx2Pad64_uid110_fxpX_uid43_fpCosPiTest_q;
--X46dto0_uid189_alignedZ_uid59_fpCosPiTest(BITSELECT,188)@5
X46dto0_uid189_alignedZ_uid59_fpCosPiTest_in <= z_uid56_fpCosPiTest_b(46 downto 0);
X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b <= X46dto0_uid189_alignedZ_uid59_fpCosPiTest_in(46 downto 0);
--ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem(DUALMEM,945)
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_ia <= X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b;
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_aa <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdreg_q;
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_ab <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_rdmux_q;
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 47,
widthad_a => 2,
numwords_a => 3,
width_b => 47,
widthad_b => 2,
numwords_b => 3,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_iq,
address_a => ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_aa,
data_a => ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_ia
);
ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_q <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_iq(46 downto 0);
--leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest(BITJOIN,189)@9
leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_q <= ld_X46dto0_uid189_alignedZ_uid59_fpCosPiTest_b_to_leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_b_replace_mem_q & leftShiftStage0Idx1Pad32_uid107_fxpX_uid43_fpCosPiTest_q;
--ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem(DUALMEM,970)
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_reset0 <= areset;
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_ia <= z_uid56_fpCosPiTest_b;
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_aa <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdreg_q;
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_ab <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_rdmux_q;
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 79,
widthad_a => 1,
numwords_a => 2,
width_b => 79,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_iq,
address_a => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_aa,
data_a => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_ia
);
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_q <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_iq(78 downto 0);
--ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_outputreg(DELAY,969)
ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_outputreg : dspba_delay
GENERIC MAP ( width => 79, depth => 1 )
PORT MAP ( xin => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_replace_mem_q, xout => ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_outputreg_q, clk => clk, aclr => areset );
--rVStage_uid145_lzcZ_uid58_fpCosPiTest(BITSELECT,144)@5
rVStage_uid145_lzcZ_uid58_fpCosPiTest_in <= z_uid56_fpCosPiTest_b;
rVStage_uid145_lzcZ_uid58_fpCosPiTest_b <= rVStage_uid145_lzcZ_uid58_fpCosPiTest_in(78 downto 15);
--vCount_uid146_lzcZ_uid58_fpCosPiTest(LOGICAL,145)@5
vCount_uid146_lzcZ_uid58_fpCosPiTest_a <= rVStage_uid145_lzcZ_uid58_fpCosPiTest_b;
vCount_uid146_lzcZ_uid58_fpCosPiTest_b <= leftShiftStage0Idx2Pad64_uid110_fxpX_uid43_fpCosPiTest_q;
vCount_uid146_lzcZ_uid58_fpCosPiTest_q <= "1" when vCount_uid146_lzcZ_uid58_fpCosPiTest_a = vCount_uid146_lzcZ_uid58_fpCosPiTest_b else "0";
--ld_vCount_uid146_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_g(DELAY,595)@5
ld_vCount_uid146_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_g : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => vCount_uid146_lzcZ_uid58_fpCosPiTest_q, xout => ld_vCount_uid146_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_g_q, clk => clk, aclr => areset );
--mO_uid147_lzcZ_uid58_fpCosPiTest(CONSTANT,146)
mO_uid147_lzcZ_uid58_fpCosPiTest_q <= "1111111111111111111111111111111111111111111111111";
--cStage_uid149_lzcZ_uid58_fpCosPiTest(BITJOIN,148)@5
cStage_uid149_lzcZ_uid58_fpCosPiTest_q <= vStage_uid148_lzcZ_uid58_fpCosPiTest_b & mO_uid147_lzcZ_uid58_fpCosPiTest_q;
--vStagei_uid151_lzcZ_uid58_fpCosPiTest(MUX,150)@5
vStagei_uid151_lzcZ_uid58_fpCosPiTest_s <= vCount_uid146_lzcZ_uid58_fpCosPiTest_q;
vStagei_uid151_lzcZ_uid58_fpCosPiTest: PROCESS (vStagei_uid151_lzcZ_uid58_fpCosPiTest_s, rVStage_uid145_lzcZ_uid58_fpCosPiTest_b, cStage_uid149_lzcZ_uid58_fpCosPiTest_q)
BEGIN
CASE vStagei_uid151_lzcZ_uid58_fpCosPiTest_s IS
WHEN "0" => vStagei_uid151_lzcZ_uid58_fpCosPiTest_q <= rVStage_uid145_lzcZ_uid58_fpCosPiTest_b;
WHEN "1" => vStagei_uid151_lzcZ_uid58_fpCosPiTest_q <= cStage_uid149_lzcZ_uid58_fpCosPiTest_q;
WHEN OTHERS => vStagei_uid151_lzcZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid153_lzcZ_uid58_fpCosPiTest(BITSELECT,152)@5
rVStage_uid153_lzcZ_uid58_fpCosPiTest_in <= vStagei_uid151_lzcZ_uid58_fpCosPiTest_q;
rVStage_uid153_lzcZ_uid58_fpCosPiTest_b <= rVStage_uid153_lzcZ_uid58_fpCosPiTest_in(63 downto 32);
--reg_rVStage_uid153_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid154_lzcZ_uid58_fpCosPiTest_0(REG,364)@5
reg_rVStage_uid153_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid154_lzcZ_uid58_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid153_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid154_lzcZ_uid58_fpCosPiTest_0_q <= "00000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_rVStage_uid153_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid154_lzcZ_uid58_fpCosPiTest_0_q <= rVStage_uid153_lzcZ_uid58_fpCosPiTest_b;
END IF;
END PROCESS;
--vCount_uid154_lzcZ_uid58_fpCosPiTest(LOGICAL,153)@6
vCount_uid154_lzcZ_uid58_fpCosPiTest_a <= reg_rVStage_uid153_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid154_lzcZ_uid58_fpCosPiTest_0_q;
vCount_uid154_lzcZ_uid58_fpCosPiTest_b <= leftShiftStage0Idx1Pad32_uid107_fxpX_uid43_fpCosPiTest_q;
vCount_uid154_lzcZ_uid58_fpCosPiTest_q <= "1" when vCount_uid154_lzcZ_uid58_fpCosPiTest_a = vCount_uid154_lzcZ_uid58_fpCosPiTest_b else "0";
--ld_vCount_uid154_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_f(DELAY,594)@6
ld_vCount_uid154_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_f : dspba_delay
GENERIC MAP ( width => 1, depth => 2 )
PORT MAP ( xin => vCount_uid154_lzcZ_uid58_fpCosPiTest_q, xout => ld_vCount_uid154_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_f_q, clk => clk, aclr => areset );
--vStage_uid155_lzcZ_uid58_fpCosPiTest(BITSELECT,154)@5
vStage_uid155_lzcZ_uid58_fpCosPiTest_in <= vStagei_uid151_lzcZ_uid58_fpCosPiTest_q(31 downto 0);
vStage_uid155_lzcZ_uid58_fpCosPiTest_b <= vStage_uid155_lzcZ_uid58_fpCosPiTest_in(31 downto 0);
--ld_vStage_uid155_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_d(DELAY,562)@5
ld_vStage_uid155_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => vStage_uid155_lzcZ_uid58_fpCosPiTest_b, xout => ld_vStage_uid155_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_d_q, clk => clk, aclr => areset );
--ld_rVStage_uid153_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_c(DELAY,561)@5
ld_rVStage_uid153_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 32, depth => 1 )
PORT MAP ( xin => rVStage_uid153_lzcZ_uid58_fpCosPiTest_b, xout => ld_rVStage_uid153_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_c_q, clk => clk, aclr => areset );
--vStagei_uid157_lzcZ_uid58_fpCosPiTest(MUX,156)@6
vStagei_uid157_lzcZ_uid58_fpCosPiTest_s <= vCount_uid154_lzcZ_uid58_fpCosPiTest_q;
vStagei_uid157_lzcZ_uid58_fpCosPiTest: PROCESS (vStagei_uid157_lzcZ_uid58_fpCosPiTest_s, ld_rVStage_uid153_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_c_q, ld_vStage_uid155_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_d_q)
BEGIN
CASE vStagei_uid157_lzcZ_uid58_fpCosPiTest_s IS
WHEN "0" => vStagei_uid157_lzcZ_uid58_fpCosPiTest_q <= ld_rVStage_uid153_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_c_q;
WHEN "1" => vStagei_uid157_lzcZ_uid58_fpCosPiTest_q <= ld_vStage_uid155_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid157_lzcZ_uid58_fpCosPiTest_d_q;
WHEN OTHERS => vStagei_uid157_lzcZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid159_lzcZ_uid58_fpCosPiTest(BITSELECT,158)@6
rVStage_uid159_lzcZ_uid58_fpCosPiTest_in <= vStagei_uid157_lzcZ_uid58_fpCosPiTest_q;
rVStage_uid159_lzcZ_uid58_fpCosPiTest_b <= rVStage_uid159_lzcZ_uid58_fpCosPiTest_in(31 downto 16);
--reg_rVStage_uid159_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid160_lzcZ_uid58_fpCosPiTest_0(REG,365)@6
reg_rVStage_uid159_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid160_lzcZ_uid58_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid159_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid160_lzcZ_uid58_fpCosPiTest_0_q <= "0000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_rVStage_uid159_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid160_lzcZ_uid58_fpCosPiTest_0_q <= rVStage_uid159_lzcZ_uid58_fpCosPiTest_b;
END IF;
END PROCESS;
--vCount_uid160_lzcZ_uid58_fpCosPiTest(LOGICAL,159)@7
vCount_uid160_lzcZ_uid58_fpCosPiTest_a <= reg_rVStage_uid159_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid160_lzcZ_uid58_fpCosPiTest_0_q;
vCount_uid160_lzcZ_uid58_fpCosPiTest_b <= leftShiftStage1Idx2Pad16_uid119_fxpX_uid43_fpCosPiTest_q;
vCount_uid160_lzcZ_uid58_fpCosPiTest_q <= "1" when vCount_uid160_lzcZ_uid58_fpCosPiTest_a = vCount_uid160_lzcZ_uid58_fpCosPiTest_b else "0";
--ld_vCount_uid160_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_e(DELAY,593)@7
ld_vCount_uid160_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_e : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => vCount_uid160_lzcZ_uid58_fpCosPiTest_q, xout => ld_vCount_uid160_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_e_q, clk => clk, aclr => areset );
--vStage_uid161_lzcZ_uid58_fpCosPiTest(BITSELECT,160)@6
vStage_uid161_lzcZ_uid58_fpCosPiTest_in <= vStagei_uid157_lzcZ_uid58_fpCosPiTest_q(15 downto 0);
vStage_uid161_lzcZ_uid58_fpCosPiTest_b <= vStage_uid161_lzcZ_uid58_fpCosPiTest_in(15 downto 0);
--ld_vStage_uid161_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_d(DELAY,568)@6
ld_vStage_uid161_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => vStage_uid161_lzcZ_uid58_fpCosPiTest_b, xout => ld_vStage_uid161_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_d_q, clk => clk, aclr => areset );
--ld_rVStage_uid159_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_c(DELAY,567)@6
ld_rVStage_uid159_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 16, depth => 1 )
PORT MAP ( xin => rVStage_uid159_lzcZ_uid58_fpCosPiTest_b, xout => ld_rVStage_uid159_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_c_q, clk => clk, aclr => areset );
--vStagei_uid163_lzcZ_uid58_fpCosPiTest(MUX,162)@7
vStagei_uid163_lzcZ_uid58_fpCosPiTest_s <= vCount_uid160_lzcZ_uid58_fpCosPiTest_q;
vStagei_uid163_lzcZ_uid58_fpCosPiTest: PROCESS (vStagei_uid163_lzcZ_uid58_fpCosPiTest_s, ld_rVStage_uid159_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_c_q, ld_vStage_uid161_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_d_q)
BEGIN
CASE vStagei_uid163_lzcZ_uid58_fpCosPiTest_s IS
WHEN "0" => vStagei_uid163_lzcZ_uid58_fpCosPiTest_q <= ld_rVStage_uid159_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_c_q;
WHEN "1" => vStagei_uid163_lzcZ_uid58_fpCosPiTest_q <= ld_vStage_uid161_lzcZ_uid58_fpCosPiTest_b_to_vStagei_uid163_lzcZ_uid58_fpCosPiTest_d_q;
WHEN OTHERS => vStagei_uid163_lzcZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid165_lzcZ_uid58_fpCosPiTest(BITSELECT,164)@7
rVStage_uid165_lzcZ_uid58_fpCosPiTest_in <= vStagei_uid163_lzcZ_uid58_fpCosPiTest_q;
rVStage_uid165_lzcZ_uid58_fpCosPiTest_b <= rVStage_uid165_lzcZ_uid58_fpCosPiTest_in(15 downto 8);
--reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid166_lzcZ_uid58_fpCosPiTest_0(REG,366)@7
reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid166_lzcZ_uid58_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid166_lzcZ_uid58_fpCosPiTest_0_q <= "00000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid166_lzcZ_uid58_fpCosPiTest_0_q <= rVStage_uid165_lzcZ_uid58_fpCosPiTest_b;
END IF;
END PROCESS;
--vCount_uid166_lzcZ_uid58_fpCosPiTest(LOGICAL,165)@8
vCount_uid166_lzcZ_uid58_fpCosPiTest_a <= reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vCount_uid166_lzcZ_uid58_fpCosPiTest_0_q;
vCount_uid166_lzcZ_uid58_fpCosPiTest_b <= leftShiftStage1Idx1Pad8_uid116_fxpX_uid43_fpCosPiTest_q;
vCount_uid166_lzcZ_uid58_fpCosPiTest_q <= "1" when vCount_uid166_lzcZ_uid58_fpCosPiTest_a = vCount_uid166_lzcZ_uid58_fpCosPiTest_b else "0";
--vStage_uid167_lzcZ_uid58_fpCosPiTest(BITSELECT,166)@7
vStage_uid167_lzcZ_uid58_fpCosPiTest_in <= vStagei_uid163_lzcZ_uid58_fpCosPiTest_q(7 downto 0);
vStage_uid167_lzcZ_uid58_fpCosPiTest_b <= vStage_uid167_lzcZ_uid58_fpCosPiTest_in(7 downto 0);
--reg_vStage_uid167_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_3(REG,367)@7
reg_vStage_uid167_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_3: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_vStage_uid167_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_3_q <= "00000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_vStage_uid167_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_3_q <= vStage_uid167_lzcZ_uid58_fpCosPiTest_b;
END IF;
END PROCESS;
--reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_2(REG,368)@7
reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_2_q <= "00000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_2_q <= rVStage_uid165_lzcZ_uid58_fpCosPiTest_b;
END IF;
END PROCESS;
--vStagei_uid169_lzcZ_uid58_fpCosPiTest(MUX,168)@8
vStagei_uid169_lzcZ_uid58_fpCosPiTest_s <= vCount_uid166_lzcZ_uid58_fpCosPiTest_q;
vStagei_uid169_lzcZ_uid58_fpCosPiTest: PROCESS (vStagei_uid169_lzcZ_uid58_fpCosPiTest_s, reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_2_q, reg_vStage_uid167_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_3_q)
BEGIN
CASE vStagei_uid169_lzcZ_uid58_fpCosPiTest_s IS
WHEN "0" => vStagei_uid169_lzcZ_uid58_fpCosPiTest_q <= reg_rVStage_uid165_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_2_q;
WHEN "1" => vStagei_uid169_lzcZ_uid58_fpCosPiTest_q <= reg_vStage_uid167_lzcZ_uid58_fpCosPiTest_0_to_vStagei_uid169_lzcZ_uid58_fpCosPiTest_3_q;
WHEN OTHERS => vStagei_uid169_lzcZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid171_lzcZ_uid58_fpCosPiTest(BITSELECT,170)@8
rVStage_uid171_lzcZ_uid58_fpCosPiTest_in <= vStagei_uid169_lzcZ_uid58_fpCosPiTest_q;
rVStage_uid171_lzcZ_uid58_fpCosPiTest_b <= rVStage_uid171_lzcZ_uid58_fpCosPiTest_in(7 downto 4);
--vCount_uid172_lzcZ_uid58_fpCosPiTest(LOGICAL,171)@8
vCount_uid172_lzcZ_uid58_fpCosPiTest_a <= rVStage_uid171_lzcZ_uid58_fpCosPiTest_b;
vCount_uid172_lzcZ_uid58_fpCosPiTest_b <= leftShiftStage2Idx2Pad4_uid130_fxpX_uid43_fpCosPiTest_q;
vCount_uid172_lzcZ_uid58_fpCosPiTest_q <= "1" when vCount_uid172_lzcZ_uid58_fpCosPiTest_a = vCount_uid172_lzcZ_uid58_fpCosPiTest_b else "0";
--vStage_uid173_lzcZ_uid58_fpCosPiTest(BITSELECT,172)@8
vStage_uid173_lzcZ_uid58_fpCosPiTest_in <= vStagei_uid169_lzcZ_uid58_fpCosPiTest_q(3 downto 0);
vStage_uid173_lzcZ_uid58_fpCosPiTest_b <= vStage_uid173_lzcZ_uid58_fpCosPiTest_in(3 downto 0);
--vStagei_uid175_lzcZ_uid58_fpCosPiTest(MUX,174)@8
vStagei_uid175_lzcZ_uid58_fpCosPiTest_s <= vCount_uid172_lzcZ_uid58_fpCosPiTest_q;
vStagei_uid175_lzcZ_uid58_fpCosPiTest: PROCESS (vStagei_uid175_lzcZ_uid58_fpCosPiTest_s, rVStage_uid171_lzcZ_uid58_fpCosPiTest_b, vStage_uid173_lzcZ_uid58_fpCosPiTest_b)
BEGIN
CASE vStagei_uid175_lzcZ_uid58_fpCosPiTest_s IS
WHEN "0" => vStagei_uid175_lzcZ_uid58_fpCosPiTest_q <= rVStage_uid171_lzcZ_uid58_fpCosPiTest_b;
WHEN "1" => vStagei_uid175_lzcZ_uid58_fpCosPiTest_q <= vStage_uid173_lzcZ_uid58_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid175_lzcZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid177_lzcZ_uid58_fpCosPiTest(BITSELECT,176)@8
rVStage_uid177_lzcZ_uid58_fpCosPiTest_in <= vStagei_uid175_lzcZ_uid58_fpCosPiTest_q;
rVStage_uid177_lzcZ_uid58_fpCosPiTest_b <= rVStage_uid177_lzcZ_uid58_fpCosPiTest_in(3 downto 2);
--vCount_uid178_lzcZ_uid58_fpCosPiTest(LOGICAL,177)@8
vCount_uid178_lzcZ_uid58_fpCosPiTest_a <= rVStage_uid177_lzcZ_uid58_fpCosPiTest_b;
vCount_uid178_lzcZ_uid58_fpCosPiTest_b <= leftShiftStage2Idx1Pad2_uid127_fxpX_uid43_fpCosPiTest_q;
vCount_uid178_lzcZ_uid58_fpCosPiTest_q <= "1" when vCount_uid178_lzcZ_uid58_fpCosPiTest_a = vCount_uid178_lzcZ_uid58_fpCosPiTest_b else "0";
--vStage_uid179_lzcZ_uid58_fpCosPiTest(BITSELECT,178)@8
vStage_uid179_lzcZ_uid58_fpCosPiTest_in <= vStagei_uid175_lzcZ_uid58_fpCosPiTest_q(1 downto 0);
vStage_uid179_lzcZ_uid58_fpCosPiTest_b <= vStage_uid179_lzcZ_uid58_fpCosPiTest_in(1 downto 0);
--vStagei_uid181_lzcZ_uid58_fpCosPiTest(MUX,180)@8
vStagei_uid181_lzcZ_uid58_fpCosPiTest_s <= vCount_uid178_lzcZ_uid58_fpCosPiTest_q;
vStagei_uid181_lzcZ_uid58_fpCosPiTest: PROCESS (vStagei_uid181_lzcZ_uid58_fpCosPiTest_s, rVStage_uid177_lzcZ_uid58_fpCosPiTest_b, vStage_uid179_lzcZ_uid58_fpCosPiTest_b)
BEGIN
CASE vStagei_uid181_lzcZ_uid58_fpCosPiTest_s IS
WHEN "0" => vStagei_uid181_lzcZ_uid58_fpCosPiTest_q <= rVStage_uid177_lzcZ_uid58_fpCosPiTest_b;
WHEN "1" => vStagei_uid181_lzcZ_uid58_fpCosPiTest_q <= vStage_uid179_lzcZ_uid58_fpCosPiTest_b;
WHEN OTHERS => vStagei_uid181_lzcZ_uid58_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--rVStage_uid183_lzcZ_uid58_fpCosPiTest(BITSELECT,182)@8
rVStage_uid183_lzcZ_uid58_fpCosPiTest_in <= vStagei_uid181_lzcZ_uid58_fpCosPiTest_q;
rVStage_uid183_lzcZ_uid58_fpCosPiTest_b <= rVStage_uid183_lzcZ_uid58_fpCosPiTest_in(1 downto 1);
--vCount_uid184_lzcZ_uid58_fpCosPiTest(LOGICAL,183)@8
vCount_uid184_lzcZ_uid58_fpCosPiTest_a <= rVStage_uid183_lzcZ_uid58_fpCosPiTest_b;
vCount_uid184_lzcZ_uid58_fpCosPiTest_b <= GND_q;
vCount_uid184_lzcZ_uid58_fpCosPiTest_q <= "1" when vCount_uid184_lzcZ_uid58_fpCosPiTest_a = vCount_uid184_lzcZ_uid58_fpCosPiTest_b else "0";
--r_uid185_lzcZ_uid58_fpCosPiTest(BITJOIN,184)@8
r_uid185_lzcZ_uid58_fpCosPiTest_q <= ld_vCount_uid146_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_g_q & ld_vCount_uid154_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_f_q & ld_vCount_uid160_lzcZ_uid58_fpCosPiTest_q_to_r_uid185_lzcZ_uid58_fpCosPiTest_e_q & vCount_uid166_lzcZ_uid58_fpCosPiTest_q & vCount_uid172_lzcZ_uid58_fpCosPiTest_q & vCount_uid178_lzcZ_uid58_fpCosPiTest_q & vCount_uid184_lzcZ_uid58_fpCosPiTest_q;
--leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest(BITSELECT,194)@8
leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_in <= r_uid185_lzcZ_uid58_fpCosPiTest_q;
leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_b <= leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_in(6 downto 5);
--reg_leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_1(REG,369)@8
reg_leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_1_q <= "00";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_1_q <= leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_b;
END IF;
END PROCESS;
--leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest(MUX,195)@9
leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_s <= reg_leftShiftStageSel6Dto5_uid195_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_1_q;
leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest: PROCESS (leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_s, ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_outputreg_q, leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_q, leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_q)
BEGIN
CASE leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_s IS
WHEN "00" => leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_q <= ld_z_uid56_fpCosPiTest_b_to_leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_c_outputreg_q;
WHEN "01" => leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage0Idx1_uid190_alignedZ_uid59_fpCosPiTest_q;
WHEN "10" => leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage0Idx2_uid193_alignedZ_uid59_fpCosPiTest_q;
WHEN "11" => leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_q <= cstZwSwF_uid16_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest(BITSELECT,205)@8
leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_in <= r_uid185_lzcZ_uid58_fpCosPiTest_q(4 downto 0);
leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_b <= leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_in(4 downto 3);
--reg_leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_1(REG,370)@8
reg_leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_1_q <= "00";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_1_q <= leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_b;
END IF;
END PROCESS;
--leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest(MUX,206)@9
leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_s <= reg_leftShiftStageSel4Dto3_uid206_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_1_q;
leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest: PROCESS (leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_s, leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_q, leftShiftStage1Idx1_uid199_alignedZ_uid59_fpCosPiTest_q, leftShiftStage1Idx2_uid202_alignedZ_uid59_fpCosPiTest_q, leftShiftStage1Idx3_uid205_alignedZ_uid59_fpCosPiTest_q)
BEGIN
CASE leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_s IS
WHEN "00" => leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage0_uid196_alignedZ_uid59_fpCosPiTest_q;
WHEN "01" => leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage1Idx1_uid199_alignedZ_uid59_fpCosPiTest_q;
WHEN "10" => leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage1Idx2_uid202_alignedZ_uid59_fpCosPiTest_q;
WHEN "11" => leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage1Idx3_uid205_alignedZ_uid59_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest(BITSELECT,216)@8
leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_in <= r_uid185_lzcZ_uid58_fpCosPiTest_q(2 downto 0);
leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_b <= leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_in(2 downto 1);
--reg_leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_1(REG,371)@8
reg_leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_1_q <= "00";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_1_q <= leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_b;
END IF;
END PROCESS;
--leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest(MUX,217)@9
leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_s <= reg_leftShiftStageSel2Dto1_uid217_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_1_q;
leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest: PROCESS (leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_s, leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_q, leftShiftStage2Idx1_uid210_alignedZ_uid59_fpCosPiTest_q, leftShiftStage2Idx2_uid213_alignedZ_uid59_fpCosPiTest_q, leftShiftStage2Idx3_uid216_alignedZ_uid59_fpCosPiTest_q)
BEGIN
CASE leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_s IS
WHEN "00" => leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage1_uid207_alignedZ_uid59_fpCosPiTest_q;
WHEN "01" => leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage2Idx1_uid210_alignedZ_uid59_fpCosPiTest_q;
WHEN "10" => leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage2Idx2_uid213_alignedZ_uid59_fpCosPiTest_q;
WHEN "11" => leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage2Idx3_uid216_alignedZ_uid59_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest(BITSELECT,221)@8
leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_in <= r_uid185_lzcZ_uid58_fpCosPiTest_q(0 downto 0);
leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_b <= leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_in(0 downto 0);
--reg_leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_1(REG,372)@8
reg_leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_1_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_1_q <= leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_b;
END IF;
END PROCESS;
--leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest(MUX,222)@9
leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_s <= reg_leftShiftStageSel0Dto0_uid222_alignedZ_uid59_fpCosPiTest_0_to_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_1_q;
leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest: PROCESS (leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_s, leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_q, leftShiftStage3Idx1_uid221_alignedZ_uid59_fpCosPiTest_q)
BEGIN
CASE leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_s IS
WHEN "0" => leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage2_uid218_alignedZ_uid59_fpCosPiTest_q;
WHEN "1" => leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q <= leftShiftStage3Idx1_uid221_alignedZ_uid59_fpCosPiTest_q;
WHEN OTHERS => leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_inputreg(DELAY,869)
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 79, depth => 1 )
PORT MAP ( xin => leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q, xout => ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_inputreg_q, clk => clk, aclr => areset );
--ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_wrreg(REG,872)
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_wrreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_wrreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_wrreg_q <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt(COUNTER,871)
-- every=1, low=0, high=22, step=1, init=1
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_i = 21 THEN
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_eq <= '1';
ELSE
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_eq = '1') THEN
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_i <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_i - 22;
ELSE
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_i <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_i,5));
--ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem(DUALMEM,870)
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_reset0 <= areset;
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_ia <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_inputreg_q;
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_aa <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_wrreg_q;
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_ab <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_rdcnt_q;
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 79,
widthad_a => 5,
numwords_a => 23,
width_b => 79,
widthad_b => 5,
numwords_b => 23,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_enaAnd_q(0),
clocken0 => VCC_q(0),
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_iq,
address_a => ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_aa,
data_a => ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_ia
);
ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_q <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_iq(78 downto 0);
--alignedZLow_uid60_fpCosPiTest(BITSELECT,59)@34
alignedZLow_uid60_fpCosPiTest_in <= ld_leftShiftStage3_uid223_alignedZ_uid59_fpCosPiTest_q_to_alignedZLow_uid60_fpCosPiTest_a_replace_mem_q;
alignedZLow_uid60_fpCosPiTest_b <= alignedZLow_uid60_fpCosPiTest_in(78 downto 26);
--mul2xSinRes_uid68_fpCosPiTest_a_1(BITSELECT,315)@34
mul2xSinRes_uid68_fpCosPiTest_a_1_in <= STD_LOGIC_VECTOR("0" & alignedZLow_uid60_fpCosPiTest_b);
mul2xSinRes_uid68_fpCosPiTest_a_1_b <= mul2xSinRes_uid68_fpCosPiTest_a_1_in(53 downto 27);
--reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_0(REG,401)@34
reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_0_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_0_q <= mul2xSinRes_uid68_fpCosPiTest_a_1_b;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest_a1_b1(MULT,321)@35
mul2xSinRes_uid68_fpCosPiTest_a1_b1_pr <= UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a1_b1_a) * UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a1_b1_b);
mul2xSinRes_uid68_fpCosPiTest_a1_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a1_b1_a <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_a1_b1_b <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_a1_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a1_b1_a <= reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_0_q;
mul2xSinRes_uid68_fpCosPiTest_a1_b1_b <= reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b1_1_q;
mul2xSinRes_uid68_fpCosPiTest_a1_b1_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid68_fpCosPiTest_a1_b1_pr);
END IF;
END PROCESS;
mul2xSinRes_uid68_fpCosPiTest_a1_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a1_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a1_b1_q <= mul2xSinRes_uid68_fpCosPiTest_a1_b1_s1;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b1(BITSELECT,328)@38
mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b1_in <= mul2xSinRes_uid68_fpCosPiTest_a1_b1_q(26 downto 0);
mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b1_b <= mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b1_in(26 downto 0);
--reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_1(REG,402)@34
reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_1_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_1_q <= mul2xSinRes_uid68_fpCosPiTest_b_1_b;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest_a_0(BITSELECT,314)@34
mul2xSinRes_uid68_fpCosPiTest_a_0_in <= alignedZLow_uid60_fpCosPiTest_b(26 downto 0);
mul2xSinRes_uid68_fpCosPiTest_a_0_b <= mul2xSinRes_uid68_fpCosPiTest_a_0_in(26 downto 0);
--reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_0(REG,403)@34
reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_0_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_0_q <= mul2xSinRes_uid68_fpCosPiTest_a_0_b;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest_a0_b1(MULT,320)@35
mul2xSinRes_uid68_fpCosPiTest_a0_b1_pr <= UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a0_b1_a) * UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a0_b1_b);
mul2xSinRes_uid68_fpCosPiTest_a0_b1_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a0_b1_a <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_a0_b1_b <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_a0_b1_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a0_b1_a <= reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_0_q;
mul2xSinRes_uid68_fpCosPiTest_a0_b1_b <= reg_mul2xSinRes_uid68_fpCosPiTest_b_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b1_1_q;
mul2xSinRes_uid68_fpCosPiTest_a0_b1_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid68_fpCosPiTest_a0_b1_pr);
END IF;
END PROCESS;
mul2xSinRes_uid68_fpCosPiTest_a0_b1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a0_b1_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a0_b1_q <= mul2xSinRes_uid68_fpCosPiTest_a0_b1_s1;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b1(BITSELECT,326)@38
mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b1_in <= mul2xSinRes_uid68_fpCosPiTest_a0_b1_q(26 downto 0);
mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b1_b <= mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b1_in(26 downto 0);
--mul2xSinRes_uid68_fpCosPiTest_zero_36(CONSTANT,331)
mul2xSinRes_uid68_fpCosPiTest_zero_36_q <= "000000000000000000000000000";
--mul2xSinRes_uid68_fpCosPiTest_joined_BJ_2(BITJOIN,335)@38
mul2xSinRes_uid68_fpCosPiTest_joined_BJ_2_q <= mul2xSinRes_uid68_fpCosPiTest_zero_36_q & mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b1_b & mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b1_b & mul2xSinRes_uid68_fpCosPiTest_zero_36_q;
--mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b1(BITSELECT,327)@38
mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b1_in <= mul2xSinRes_uid68_fpCosPiTest_a0_b1_q;
mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b1_b <= mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b1_in(53 downto 27);
--mul2xSinRes_uid68_fpCosPiTest_b_0(BITSELECT,316)@34
mul2xSinRes_uid68_fpCosPiTest_b_0_in <= fxpSinRes_uid67_fpCosPiTest_b(26 downto 0);
mul2xSinRes_uid68_fpCosPiTest_b_0_b <= mul2xSinRes_uid68_fpCosPiTest_b_0_in(26 downto 0);
--reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_1(REG,398)@34
reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_1_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_1_q <= mul2xSinRes_uid68_fpCosPiTest_b_0_b;
END IF;
END PROCESS;
--reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_0(REG,399)@34
reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_0_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_0_q <= mul2xSinRes_uid68_fpCosPiTest_a_1_b;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest_a1_b0(MULT,319)@35
mul2xSinRes_uid68_fpCosPiTest_a1_b0_pr <= UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a1_b0_a) * UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a1_b0_b);
mul2xSinRes_uid68_fpCosPiTest_a1_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a1_b0_a <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_a1_b0_b <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_a1_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a1_b0_a <= reg_mul2xSinRes_uid68_fpCosPiTest_a_1_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_0_q;
mul2xSinRes_uid68_fpCosPiTest_a1_b0_b <= reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a1_b0_1_q;
mul2xSinRes_uid68_fpCosPiTest_a1_b0_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid68_fpCosPiTest_a1_b0_pr);
END IF;
END PROCESS;
mul2xSinRes_uid68_fpCosPiTest_a1_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a1_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a1_b0_q <= mul2xSinRes_uid68_fpCosPiTest_a1_b0_s1;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b0(BITSELECT,324)@38
mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b0_in <= mul2xSinRes_uid68_fpCosPiTest_a1_b0_q(26 downto 0);
mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b0_b <= mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b0_in(26 downto 0);
--mul2xSinRes_uid68_fpCosPiTest_joined_BJ_1(BITJOIN,334)@38
mul2xSinRes_uid68_fpCosPiTest_joined_BJ_1_q <= mul2xSinRes_uid68_fpCosPiTest_zero_36_q & mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b1_b & mul2xSinRes_uid68_fpCosPiTest_LSB_a1_b0_b & mul2xSinRes_uid68_fpCosPiTest_zero_36_q;
--mul2xSinRes_uid68_fpCosPiTest_32COMP0_andBC(LOGICAL,339)@38
mul2xSinRes_uid68_fpCosPiTest_32COMP0_andBC_a <= mul2xSinRes_uid68_fpCosPiTest_joined_BJ_1_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_andBC_b <= mul2xSinRes_uid68_fpCosPiTest_joined_BJ_2_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_andBC_q <= mul2xSinRes_uid68_fpCosPiTest_32COMP0_andBC_a and mul2xSinRes_uid68_fpCosPiTest_32COMP0_andBC_b;
--mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b1(BITSELECT,329)@38
mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b1_in <= mul2xSinRes_uid68_fpCosPiTest_a1_b1_q;
mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b1_b <= mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b1_in(53 downto 27);
--mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b0(BITSELECT,325)@38
mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b0_in <= mul2xSinRes_uid68_fpCosPiTest_a1_b0_q;
mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b0_b <= mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b0_in(53 downto 27);
--reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_1(REG,396)@34
reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_1_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_1_q <= mul2xSinRes_uid68_fpCosPiTest_b_0_b;
END IF;
END PROCESS;
--reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_0(REG,397)@34
reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_0_q <= "000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_0_q <= mul2xSinRes_uid68_fpCosPiTest_a_0_b;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest_a0_b0(MULT,318)@35
mul2xSinRes_uid68_fpCosPiTest_a0_b0_pr <= UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a0_b0_a) * UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a0_b0_b);
mul2xSinRes_uid68_fpCosPiTest_a0_b0_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a0_b0_a <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_a0_b0_b <= (others => '0');
mul2xSinRes_uid68_fpCosPiTest_a0_b0_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a0_b0_a <= reg_mul2xSinRes_uid68_fpCosPiTest_a_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_0_q;
mul2xSinRes_uid68_fpCosPiTest_a0_b0_b <= reg_mul2xSinRes_uid68_fpCosPiTest_b_0_0_to_mul2xSinRes_uid68_fpCosPiTest_a0_b0_1_q;
mul2xSinRes_uid68_fpCosPiTest_a0_b0_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid68_fpCosPiTest_a0_b0_pr);
END IF;
END PROCESS;
mul2xSinRes_uid68_fpCosPiTest_a0_b0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a0_b0_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_a0_b0_q <= mul2xSinRes_uid68_fpCosPiTest_a0_b0_s1;
END IF;
END PROCESS;
--mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b0(BITSELECT,323)@38
mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b0_in <= mul2xSinRes_uid68_fpCosPiTest_a0_b0_q;
mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b0_b <= mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b0_in(53 downto 27);
--mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b0(BITSELECT,322)@38
mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b0_in <= mul2xSinRes_uid68_fpCosPiTest_a0_b0_q(26 downto 0);
mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b0_b <= mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b0_in(26 downto 0);
--mul2xSinRes_uid68_fpCosPiTest_joined_BJ_0(BITJOIN,333)@38
mul2xSinRes_uid68_fpCosPiTest_joined_BJ_0_q <= mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b1_b & mul2xSinRes_uid68_fpCosPiTest_MSB_a1_b0_b & mul2xSinRes_uid68_fpCosPiTest_MSB_a0_b0_b & mul2xSinRes_uid68_fpCosPiTest_LSB_a0_b0_b;
--mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAC(LOGICAL,338)@38
mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAC_a <= mul2xSinRes_uid68_fpCosPiTest_joined_BJ_0_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAC_b <= mul2xSinRes_uid68_fpCosPiTest_joined_BJ_2_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAC_q <= mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAC_a and mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAC_b;
--mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAB(LOGICAL,337)@38
mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAB_a <= mul2xSinRes_uid68_fpCosPiTest_joined_BJ_0_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAB_b <= mul2xSinRes_uid68_fpCosPiTest_joined_BJ_1_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAB_q <= mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAB_a and mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAB_b;
--mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne(LOGICAL,340)@38
mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_a <= mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAB_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_b <= mul2xSinRes_uid68_fpCosPiTest_32COMP0_andAC_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_c <= mul2xSinRes_uid68_fpCosPiTest_32COMP0_andBC_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_q <= mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_a or mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_b or mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_c;
--mul2xSinRes_uid68_fpCosPiTest_comp_0_out1_lsb_BS(BITSELECT,341)@38
mul2xSinRes_uid68_fpCosPiTest_comp_0_out1_lsb_BS_in <= mul2xSinRes_uid68_fpCosPiTest_32COMP0_orOne_q(106 downto 0);
mul2xSinRes_uid68_fpCosPiTest_comp_0_out1_lsb_BS_b <= mul2xSinRes_uid68_fpCosPiTest_comp_0_out1_lsb_BS_in(106 downto 0);
--mul2xSinRes_uid68_fpCosPiTest_comp_0_out1_BJ(BITJOIN,342)@38
mul2xSinRes_uid68_fpCosPiTest_comp_0_out1_BJ_q <= mul2xSinRes_uid68_fpCosPiTest_comp_0_out1_lsb_BS_b & GND_q;
--mul2xSinRes_uid68_fpCosPiTest_ADD_BitExpansion_for_b(BITJOIN,349)@38
mul2xSinRes_uid68_fpCosPiTest_ADD_BitExpansion_for_b_q <= GND_q & mul2xSinRes_uid68_fpCosPiTest_comp_0_out1_BJ_q;
--mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b(BITSELECT,352)@38
mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_in <= mul2xSinRes_uid68_fpCosPiTest_ADD_BitExpansion_for_b_q;
mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_b <= mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_in(88 downto 0);
mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_c <= mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_in(108 downto 89);
--mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne(LOGICAL,336)@38
mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_a <= mul2xSinRes_uid68_fpCosPiTest_joined_BJ_0_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_b <= mul2xSinRes_uid68_fpCosPiTest_joined_BJ_1_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_c <= mul2xSinRes_uid68_fpCosPiTest_joined_BJ_2_q;
mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_q <= mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_a xor mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_b xor mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_c;
--mul2xSinRes_uid68_fpCosPiTest_ADD_BitExpansion_for_a(BITJOIN,347)@38
mul2xSinRes_uid68_fpCosPiTest_ADD_BitExpansion_for_a_q <= GND_q & mul2xSinRes_uid68_fpCosPiTest_32COMP0_xorOne_q;
--mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a(BITSELECT,351)@38
mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_in <= mul2xSinRes_uid68_fpCosPiTest_ADD_BitExpansion_for_a_q;
mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_b <= mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_in(88 downto 0);
mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_c <= mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_in(108 downto 89);
--mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2(ADD,353)@38
mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_cin <= GND_q;
mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_a <= STD_LOGIC_VECTOR("0" & mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_b) & '1';
mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_b <= STD_LOGIC_VECTOR("0" & mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_b) & mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_cin(0);
mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_o <= STD_LOGIC_VECTOR(UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_a) + UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_b));
END IF;
END PROCESS;
mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_c(0) <= mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_o(90);
mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_q <= mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_o(89 downto 1);
--ld_mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_b(DELAY,788)@38
ld_mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_b : dspba_delay
GENERIC MAP ( width => 20, depth => 1 )
PORT MAP ( xin => mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_c, xout => ld_mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_b_q, clk => clk, aclr => areset );
--ld_mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_a(DELAY,787)@38
ld_mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_a : dspba_delay
GENERIC MAP ( width => 20, depth => 1 )
PORT MAP ( xin => mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_c, xout => ld_mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_a_q, clk => clk, aclr => areset );
--mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2(ADD,354)@39
mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_cin <= mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_c;
mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_a <= STD_LOGIC_VECTOR("0" & ld_mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_a_c_to_mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_a_q) & '1';
mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_b <= STD_LOGIC_VECTOR("0" & ld_mul2xSinRes_uid68_fpCosPiTest_ADD_BitSelect_for_b_c_to_mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_b_q) & mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_cin(0);
mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_o <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_o <= STD_LOGIC_VECTOR(UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_a) + UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_b));
END IF;
END PROCESS;
mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_q <= mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_o(20 downto 1);
--ld_mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid68_fpCosPiTest_ADD_BitJoin_for_q_a(DELAY,790)@39
ld_mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid68_fpCosPiTest_ADD_BitJoin_for_q_a : dspba_delay
GENERIC MAP ( width => 89, depth => 1 )
PORT MAP ( xin => mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_q, xout => ld_mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid68_fpCosPiTest_ADD_BitJoin_for_q_a_q, clk => clk, aclr => areset );
--mul2xSinRes_uid68_fpCosPiTest_ADD_BitJoin_for_q(BITJOIN,355)@40
mul2xSinRes_uid68_fpCosPiTest_ADD_BitJoin_for_q_q <= mul2xSinRes_uid68_fpCosPiTest_ADD_p2_of_2_q & ld_mul2xSinRes_uid68_fpCosPiTest_ADD_p1_of_2_q_to_mul2xSinRes_uid68_fpCosPiTest_ADD_BitJoin_for_q_a_q;
--normBit_uid69_fpCosPiTest(BITSELECT,68)@40
normBit_uid69_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_ADD_BitJoin_for_q_q(106 downto 0);
normBit_uid69_fpCosPiTest_b <= normBit_uid69_fpCosPiTest_in(106 downto 106);
--ld_normBit_uid69_fpCosPiTest_b_to_rndExpUpdate_uid74_uid75_fpCosPiTest_c(DELAY,462)@40
ld_normBit_uid69_fpCosPiTest_b_to_rndExpUpdate_uid74_uid75_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => normBit_uid69_fpCosPiTest_b, xout => ld_normBit_uid69_fpCosPiTest_b_to_rndExpUpdate_uid74_uid75_fpCosPiTest_c_q, clk => clk, aclr => areset );
--cstAllZWF_uid9_fpCosPiTest(CONSTANT,8)
cstAllZWF_uid9_fpCosPiTest_q <= "0000000000000000000000000000000000000000000000000000";
--rndExpUpdate_uid74_uid75_fpCosPiTest(BITJOIN,74)@41
rndExpUpdate_uid74_uid75_fpCosPiTest_q <= ld_normBit_uid69_fpCosPiTest_b_to_rndExpUpdate_uid74_uid75_fpCosPiTest_c_q & cstAllZWF_uid9_fpCosPiTest_q & VCC_q;
--ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor(LOGICAL,890)
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q <= not (ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a or ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b);
--ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top(CONSTANT,886)
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q <= "011100";
--ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp(LOGICAL,887)
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q;
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q);
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q <= "1" when ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a = ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b else "0";
--ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg(REG,888)
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q;
END IF;
END PROCESS;
--ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena(REG,891)
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q = "1") THEN
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd(LOGICAL,892)
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q;
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b <= VCC_q;
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a and ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b;
--reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1(REG,404)@8
reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q <= "0000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q <= r_uid185_lzcZ_uid58_fpCosPiTest_q;
END IF;
END PROCESS;
--ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt(COUNTER,882)
-- every=1, low=0, high=28, step=1, init=1
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,5);
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i = 27 THEN
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i - 28;
ELSE
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i,5));
--ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg(REG,883)
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q <= "00000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux(MUX,884)
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s <= VCC_q;
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s, ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q, ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem(DUALMEM,881)
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia <= reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q;
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q;
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q;
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 7,
widthad_a => 5,
numwords_a => 29,
width_b => 7,
widthad_b => 5,
numwords_b => 29,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq,
address_a => ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa,
data_a => ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia
);
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q <= ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq(6 downto 0);
--ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_outputreg(DELAY,880)
ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_outputreg : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q, xout => ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_outputreg_q, clk => clk, aclr => areset );
--cstBiasM1_uid11_fpCosPiTest(CONSTANT,10)
cstBiasM1_uid11_fpCosPiTest_q <= "01111111110";
--expHardCase_uid61_fpCosPiTest(SUB,60)@40
expHardCase_uid61_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid11_fpCosPiTest_q);
expHardCase_uid61_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000" & ld_reg_r_uid185_lzcZ_uid58_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_outputreg_q);
expHardCase_uid61_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid61_fpCosPiTest_a) - UNSIGNED(expHardCase_uid61_fpCosPiTest_b));
expHardCase_uid61_fpCosPiTest_q <= expHardCase_uid61_fpCosPiTest_o(11 downto 0);
--expP_uid62_fpCosPiTest(BITSELECT,61)@40
expP_uid62_fpCosPiTest_in <= expHardCase_uid61_fpCosPiTest_q(10 downto 0);
expP_uid62_fpCosPiTest_b <= expP_uid62_fpCosPiTest_in(10 downto 0);
--highRes_uid70_fpCosPiTest(BITSELECT,69)@40
highRes_uid70_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_ADD_BitJoin_for_q_q(105 downto 0);
highRes_uid70_fpCosPiTest_b <= highRes_uid70_fpCosPiTest_in(105 downto 53);
--lowRes_uid71_fpCosPiTest(BITSELECT,70)@40
lowRes_uid71_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_ADD_BitJoin_for_q_q(104 downto 0);
lowRes_uid71_fpCosPiTest_b <= lowRes_uid71_fpCosPiTest_in(104 downto 52);
--fracRCompPreRnd_uid72_fpCosPiTest(MUX,71)@40
fracRCompPreRnd_uid72_fpCosPiTest_s <= normBit_uid69_fpCosPiTest_b;
fracRCompPreRnd_uid72_fpCosPiTest: PROCESS (fracRCompPreRnd_uid72_fpCosPiTest_s, lowRes_uid71_fpCosPiTest_b, highRes_uid70_fpCosPiTest_b)
BEGIN
CASE fracRCompPreRnd_uid72_fpCosPiTest_s IS
WHEN "0" => fracRCompPreRnd_uid72_fpCosPiTest_q <= lowRes_uid71_fpCosPiTest_b;
WHEN "1" => fracRCompPreRnd_uid72_fpCosPiTest_q <= highRes_uid70_fpCosPiTest_b;
WHEN OTHERS => fracRCompPreRnd_uid72_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--expFracPreRnd_uid73_uid73_fpCosPiTest(BITJOIN,72)@40
expFracPreRnd_uid73_uid73_fpCosPiTest_q <= expP_uid62_fpCosPiTest_b & fracRCompPreRnd_uid72_fpCosPiTest_q;
--reg_expFracPreRnd_uid73_uid73_fpCosPiTest_0_to_expFracComp_uid76_fpCosPiTest_0(REG,405)@40
reg_expFracPreRnd_uid73_uid73_fpCosPiTest_0_to_expFracComp_uid76_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_expFracPreRnd_uid73_uid73_fpCosPiTest_0_to_expFracComp_uid76_fpCosPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_expFracPreRnd_uid73_uid73_fpCosPiTest_0_to_expFracComp_uid76_fpCosPiTest_0_q <= expFracPreRnd_uid73_uid73_fpCosPiTest_q;
END IF;
END PROCESS;
--expFracComp_uid76_fpCosPiTest(ADD,75)@41
expFracComp_uid76_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracPreRnd_uid73_uid73_fpCosPiTest_0_to_expFracComp_uid76_fpCosPiTest_0_q);
expFracComp_uid76_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000000" & rndExpUpdate_uid74_uid75_fpCosPiTest_q);
expFracComp_uid76_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracComp_uid76_fpCosPiTest_a) + UNSIGNED(expFracComp_uid76_fpCosPiTest_b));
expFracComp_uid76_fpCosPiTest_q <= expFracComp_uid76_fpCosPiTest_o(64 downto 0);
--expRComp_uid78_fpCosPiTest(BITSELECT,77)@41
expRComp_uid78_fpCosPiTest_in <= expFracComp_uid76_fpCosPiTest_q(63 downto 0);
expRComp_uid78_fpCosPiTest_b <= expRComp_uid78_fpCosPiTest_in(63 downto 53);
--ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_nor(LOGICAL,929)
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_nor_b <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_sticky_ena_q;
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_nor_q <= not (ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_nor_a or ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_nor_b);
--ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_mem_top(CONSTANT,925)
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_mem_top_q <= "0100100";
--ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmp(LOGICAL,926)
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmp_a <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_mem_top_q;
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux_q);
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmp_q <= "1" when ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmp_a = ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmp_b else "0";
--ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmpReg(REG,927)
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmpReg_q <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmp_q;
END IF;
END PROCESS;
--ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_sticky_ena(REG,930)
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_nor_q = "1") THEN
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_sticky_ena_q <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_enaAnd(LOGICAL,931)
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_enaAnd_a <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_sticky_ena_q;
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_enaAnd_b <= VCC_q;
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_enaAnd_q <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_enaAnd_a and ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_enaAnd_b;
--fracXIsZero_uid28_fpCosPiTest(LOGICAL,27)@0
fracXIsZero_uid28_fpCosPiTest_a <= fracX_uid7_fpCosPiTest_b;
fracXIsZero_uid28_fpCosPiTest_b <= cstAllZWF_uid9_fpCosPiTest_q;
fracXIsZero_uid28_fpCosPiTest_q <= "1" when fracXIsZero_uid28_fpCosPiTest_a = fracXIsZero_uid28_fpCosPiTest_b else "0";
--InvFracXIsZero_uid30_fpCosPiTest(LOGICAL,29)@0
InvFracXIsZero_uid30_fpCosPiTest_a <= fracXIsZero_uid28_fpCosPiTest_q;
InvFracXIsZero_uid30_fpCosPiTest_q <= not InvFracXIsZero_uid30_fpCosPiTest_a;
--expXIsMax_uid26_fpCosPiTest(LOGICAL,25)@0
expXIsMax_uid26_fpCosPiTest_a <= expX_uid6_fpCosPiTest_b;
expXIsMax_uid26_fpCosPiTest_b <= cstAllOWE_uid8_fpCosPiTest_q;
expXIsMax_uid26_fpCosPiTest_q <= "1" when expXIsMax_uid26_fpCosPiTest_a = expXIsMax_uid26_fpCosPiTest_b else "0";
--And2ExpXIsMaxInvFracXIsZero_uid31_fpCosPiTest(LOGICAL,30)@0
And2ExpXIsMaxInvFracXIsZero_uid31_fpCosPiTest_a <= expXIsMax_uid26_fpCosPiTest_q;
And2ExpXIsMaxInvFracXIsZero_uid31_fpCosPiTest_b <= InvFracXIsZero_uid30_fpCosPiTest_q;
And2ExpXIsMaxInvFracXIsZero_uid31_fpCosPiTest_q <= And2ExpXIsMaxInvFracXIsZero_uid31_fpCosPiTest_a and And2ExpXIsMaxInvFracXIsZero_uid31_fpCosPiTest_b;
--InvAnd2ExpXIsMaxInvFracXIsZero_uid32_fpCosPiTest(LOGICAL,31)@0
InvAnd2ExpXIsMaxInvFracXIsZero_uid32_fpCosPiTest_a <= And2ExpXIsMaxInvFracXIsZero_uid31_fpCosPiTest_q;
InvAnd2ExpXIsMaxInvFracXIsZero_uid32_fpCosPiTest_q <= not InvAnd2ExpXIsMaxInvFracXIsZero_uid32_fpCosPiTest_a;
--And2ExpXIsMaxFracXIsZero_uid29_fpCosPiTest(LOGICAL,28)@0
And2ExpXIsMaxFracXIsZero_uid29_fpCosPiTest_a <= expXIsMax_uid26_fpCosPiTest_q;
And2ExpXIsMaxFracXIsZero_uid29_fpCosPiTest_b <= fracXIsZero_uid28_fpCosPiTest_q;
And2ExpXIsMaxFracXIsZero_uid29_fpCosPiTest_q <= And2ExpXIsMaxFracXIsZero_uid29_fpCosPiTest_a and And2ExpXIsMaxFracXIsZero_uid29_fpCosPiTest_b;
--InvAnd2ExpXIsMaxFracXIsZero_uid33_fpCosPiTest(LOGICAL,32)@0
InvAnd2ExpXIsMaxFracXIsZero_uid33_fpCosPiTest_a <= And2ExpXIsMaxFracXIsZero_uid29_fpCosPiTest_q;
InvAnd2ExpXIsMaxFracXIsZero_uid33_fpCosPiTest_q <= not InvAnd2ExpXIsMaxFracXIsZero_uid33_fpCosPiTest_a;
--expXIsZero_uid24_fpCosPiTest(LOGICAL,23)@0
expXIsZero_uid24_fpCosPiTest_a <= expX_uid6_fpCosPiTest_b;
expXIsZero_uid24_fpCosPiTest_b <= cstAllZWE_uid22_fpCosPiTest_q;
expXIsZero_uid24_fpCosPiTest_q <= "1" when expXIsZero_uid24_fpCosPiTest_a = expXIsZero_uid24_fpCosPiTest_b else "0";
--InvExpXIsZero_uid34_fpCosPiTest(LOGICAL,33)@0
InvExpXIsZero_uid34_fpCosPiTest_a <= expXIsZero_uid24_fpCosPiTest_q;
InvExpXIsZero_uid34_fpCosPiTest_q <= not InvExpXIsZero_uid34_fpCosPiTest_a;
--And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid35_fpCosPiTest(LOGICAL,34)@0
And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid35_fpCosPiTest_a <= InvExpXIsZero_uid34_fpCosPiTest_q;
And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid35_fpCosPiTest_b <= InvAnd2ExpXIsMaxFracXIsZero_uid33_fpCosPiTest_q;
And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid35_fpCosPiTest_q <= And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid35_fpCosPiTest_a and And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid35_fpCosPiTest_b;
--And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest(LOGICAL,35)@0
And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_a <= And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZero_uid35_fpCosPiTest_q;
And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_b <= InvAnd2ExpXIsMaxInvFracXIsZero_uid32_fpCosPiTest_q;
And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_q <= And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_a and And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_b;
END IF;
END PROCESS;
--ld_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_q_to_xIsInt_uid82_fpCosPiTest_a(DELAY,472)@1
ld_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_q_to_xIsInt_uid82_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_q, xout => ld_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_q_to_xIsInt_uid82_fpCosPiTest_a_q, clk => clk, aclr => areset );
--xIsHalf_uid85_fpCosPiTest(LOGICAL,84)@2
xIsHalf_uid85_fpCosPiTest_a <= ld_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_q_to_xIsInt_uid82_fpCosPiTest_a_q;
xIsHalf_uid85_fpCosPiTest_b <= fxpXFracHalf_uid48_fpCosPiTest_q;
xIsHalf_uid85_fpCosPiTest_c <= InvCosXIsOne_uid79_fpCosPiTest_q;
xIsHalf_uid85_fpCosPiTest_d <= InvXEvenInt_uid83_fpCosPiTest_q;
xIsHalf_uid85_fpCosPiTest_q <= xIsHalf_uid85_fpCosPiTest_a and xIsHalf_uid85_fpCosPiTest_b and xIsHalf_uid85_fpCosPiTest_c and xIsHalf_uid85_fpCosPiTest_d;
--ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_inputreg(DELAY,919)
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => xIsHalf_uid85_fpCosPiTest_q, xout => ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_inputreg_q, clk => clk, aclr => areset );
--ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt(COUNTER,921)
-- every=1, low=0, high=36, step=1, init=1
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_i = 35 THEN
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_i <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_i - 36;
ELSE
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_i <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_i,6));
--ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdreg(REG,922)
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdreg_q <= "000000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdreg_q <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux(MUX,923)
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux_s <= VCC_q;
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux: PROCESS (ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux_s, ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdreg_q, ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux_q <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux_q <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem(DUALMEM,920)
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_ia <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_inputreg_q;
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_aa <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdreg_q;
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_ab <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_rdmux_q;
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 37,
width_b => 1,
widthad_b => 6,
numwords_b => 37,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_iq,
address_a => ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_aa,
data_a => ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_ia
);
ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_q <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_iq(0 downto 0);
--expRPostExc1_uid93_fpCosPiTest(MUX,92)@41
expRPostExc1_uid93_fpCosPiTest_s <= ld_xIsHalf_uid85_fpCosPiTest_q_to_expRPostExc1_uid93_fpCosPiTest_b_replace_mem_q;
expRPostExc1_uid93_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
expRPostExc1_uid93_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
CASE expRPostExc1_uid93_fpCosPiTest_s IS
WHEN "0" => expRPostExc1_uid93_fpCosPiTest_q <= expRComp_uid78_fpCosPiTest_b;
WHEN "1" => expRPostExc1_uid93_fpCosPiTest_q <= cstAllZWE_uid22_fpCosPiTest_q;
WHEN OTHERS => expRPostExc1_uid93_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END PROCESS;
--ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_nor(LOGICAL,1105)
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_nor_b <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_sticky_ena_q;
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_nor_q <= not (ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_nor_a or ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_nor_b);
--ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_mem_top(CONSTANT,1101)
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_mem_top_q <= "0100011";
--ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmp(LOGICAL,1102)
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmp_a <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_mem_top_q;
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux_q);
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmp_q <= "1" when ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmp_a = ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmp_b else "0";
--ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmpReg(REG,1103)
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmpReg_q <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmp_q;
END IF;
END PROCESS;
--ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_sticky_ena(REG,1106)
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_nor_q = "1") THEN
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_sticky_ena_q <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_enaAnd(LOGICAL,1107)
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_enaAnd_a <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_sticky_ena_q;
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_enaAnd_b <= VCC_q;
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_enaAnd_q <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_enaAnd_a and ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_enaAnd_b;
--ld_cosXIsOne_uid38_fpCosPiTest_c_to_or_uid87_fpCosPiTest_a(DELAY,481)@0
ld_cosXIsOne_uid38_fpCosPiTest_c_to_or_uid87_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => cosXIsOne_uid38_fpCosPiTest_c, xout => ld_cosXIsOne_uid38_fpCosPiTest_c_to_or_uid87_fpCosPiTest_a_q, clk => clk, aclr => areset );
--ld_expXIsZero_uid24_fpCosPiTest_q_to_or_uid87_fpCosPiTest_d(DELAY,484)@0
ld_expXIsZero_uid24_fpCosPiTest_q_to_or_uid87_fpCosPiTest_d : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => expXIsZero_uid24_fpCosPiTest_q, xout => ld_expXIsZero_uid24_fpCosPiTest_q_to_or_uid87_fpCosPiTest_d_q, clk => clk, aclr => areset );
--reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracZero_uid47_fpCosPiTest_0(REG,358)@1
reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracZero_uid47_fpCosPiTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracZero_uid47_fpCosPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000000000000000000";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracZero_uid47_fpCosPiTest_0_q <= fxpXFrac_uid45_fpCosPiTest_b;
END IF;
END PROCESS;
--fxpXFracZero_uid47_fpCosPiTest(LOGICAL,46)@2
fxpXFracZero_uid47_fpCosPiTest_a <= reg_fxpXFrac_uid45_fpCosPiTest_0_to_fxpXFracZero_uid47_fpCosPiTest_0_q;
fxpXFracZero_uid47_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & cstZwSwF_uid16_fpCosPiTest_q);
fxpXFracZero_uid47_fpCosPiTest_q <= "1" when fxpXFracZero_uid47_fpCosPiTest_a = fxpXFracZero_uid47_fpCosPiTest_b else "0";
--And2FxpXFracZeroInvCosXIsOne_uid80_fpCosPiTest(LOGICAL,79)@2
And2FxpXFracZeroInvCosXIsOne_uid80_fpCosPiTest_a <= fxpXFracZero_uid47_fpCosPiTest_q;
And2FxpXFracZeroInvCosXIsOne_uid80_fpCosPiTest_b <= InvCosXIsOne_uid79_fpCosPiTest_q;
And2FxpXFracZeroInvCosXIsOne_uid80_fpCosPiTest_q <= And2FxpXFracZeroInvCosXIsOne_uid80_fpCosPiTest_a and And2FxpXFracZeroInvCosXIsOne_uid80_fpCosPiTest_b;
--Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest(LOGICAL,80)@2
Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_a <= ld_xEvenInt_uid37_fpCosPiTest_c_to_Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_a_q;
Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_b <= And2FxpXFracZeroInvCosXIsOne_uid80_fpCosPiTest_q;
Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_q <= Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_a or Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_b;
--xIsInt_uid82_fpCosPiTest(LOGICAL,81)@2
xIsInt_uid82_fpCosPiTest_a <= ld_And2And2InvExpXIsZeroInvAnd2ExpXIsMaxFracXIsZeroInvAnd2ExpXIsMax_uid36_fpCosPiTest_q_to_xIsInt_uid82_fpCosPiTest_a_q;
xIsInt_uid82_fpCosPiTest_b <= Or2XEvenIntAnd2FxpXFracZeroInvCosXIsOne_uid81_fpCosPiTest_q;
xIsInt_uid82_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
xIsInt_uid82_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
xIsInt_uid82_fpCosPiTest_q <= xIsInt_uid82_fpCosPiTest_a and xIsInt_uid82_fpCosPiTest_b;
END IF;
END PROCESS;
--or_uid95_fpCosPiTest(LOGICAL,94)@3
or_uid95_fpCosPiTest_a <= xIsInt_uid82_fpCosPiTest_q;
or_uid95_fpCosPiTest_b <= ld_expXIsZero_uid24_fpCosPiTest_q_to_or_uid87_fpCosPiTest_d_q;
or_uid95_fpCosPiTest_c <= ld_cosXIsOne_uid38_fpCosPiTest_c_to_or_uid87_fpCosPiTest_a_q;
or_uid95_fpCosPiTest_q <= or_uid95_fpCosPiTest_a or or_uid95_fpCosPiTest_b or or_uid95_fpCosPiTest_c;
--excRNaN_uid86_fpCosPiTest(LOGICAL,85)@0
excRNaN_uid86_fpCosPiTest_a <= And2ExpXIsMaxInvFracXIsZero_uid31_fpCosPiTest_q;
excRNaN_uid86_fpCosPiTest_b <= And2ExpXIsMaxFracXIsZero_uid29_fpCosPiTest_q;
excRNaN_uid86_fpCosPiTest_q <= excRNaN_uid86_fpCosPiTest_a or excRNaN_uid86_fpCosPiTest_b;
--Or2ZeroExcRNaN_uid94_fpCosPiTest(LOGICAL,93)@0
Or2ZeroExcRNaN_uid94_fpCosPiTest_a <= GND_q;
Or2ZeroExcRNaN_uid94_fpCosPiTest_b <= excRNaN_uid86_fpCosPiTest_q;
Or2ZeroExcRNaN_uid94_fpCosPiTest_q <= Or2ZeroExcRNaN_uid94_fpCosPiTest_a or Or2ZeroExcRNaN_uid94_fpCosPiTest_b;
--ld_Or2ZeroExcRNaN_uid94_fpCosPiTest_q_to_join_uid96_fpCosPiTest_a(DELAY,496)@0
ld_Or2ZeroExcRNaN_uid94_fpCosPiTest_q_to_join_uid96_fpCosPiTest_a : dspba_delay
GENERIC MAP ( width => 1, depth => 3 )
PORT MAP ( xin => Or2ZeroExcRNaN_uid94_fpCosPiTest_q, xout => ld_Or2ZeroExcRNaN_uid94_fpCosPiTest_q_to_join_uid96_fpCosPiTest_a_q, clk => clk, aclr => areset );
--join_uid96_fpCosPiTest(BITJOIN,95)@3
join_uid96_fpCosPiTest_q <= or_uid95_fpCosPiTest_q & ld_Or2ZeroExcRNaN_uid94_fpCosPiTest_q_to_join_uid96_fpCosPiTest_a_q;
--ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt(COUNTER,1097)
-- every=1, low=0, high=35, step=1, init=1
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_i = 34 THEN
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_eq <= '1';
ELSE
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_eq = '1') THEN
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_i <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_i - 35;
ELSE
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_i <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_i,6));
--ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdreg(REG,1098)
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdreg_q <= "000000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdreg_q <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux(MUX,1099)
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux_s <= VCC_q;
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux: PROCESS (ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux_s, ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdreg_q, ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_q)
BEGIN
CASE ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux_s IS
WHEN "0" => ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux_q <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdreg_q;
WHEN "1" => ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux_q <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdcnt_q;
WHEN OTHERS => ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem(DUALMEM,1096)
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_reset0 <= areset;
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_ia <= join_uid96_fpCosPiTest_q;
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_aa <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdreg_q;
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_ab <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_rdmux_q;
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 2,
widthad_a => 6,
numwords_a => 36,
width_b => 2,
widthad_b => 6,
numwords_b => 36,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_iq,
address_a => ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_aa,
data_a => ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_ia
);
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_q <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_iq(1 downto 0);
--ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_outputreg(DELAY,1095)
ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_outputreg : dspba_delay
GENERIC MAP ( width => 2, depth => 1 )
PORT MAP ( xin => ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_replace_mem_q, xout => ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_outputreg_q, clk => clk, aclr => areset );
--reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1(REG,406)@41
reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_q <= "00";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_q <= ld_join_uid96_fpCosPiTest_q_to_reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_a_outputreg_q;
END IF;
END PROCESS;
--expRPostExc_uid97_fpCosPiTest(MUX,96)@42
expRPostExc_uid97_fpCosPiTest_s <= reg_join_uid96_fpCosPiTest_0_to_expRPostExc_uid97_fpCosPiTest_1_q;
expRPostExc_uid97_fpCosPiTest: PROCESS (expRPostExc_uid97_fpCosPiTest_s, expRPostExc1_uid93_fpCosPiTest_q)
BEGIN
CASE expRPostExc_uid97_fpCosPiTest_s IS
WHEN "00" => expRPostExc_uid97_fpCosPiTest_q <= expRPostExc1_uid93_fpCosPiTest_q;
WHEN "01" => expRPostExc_uid97_fpCosPiTest_q <= cstAllOWE_uid8_fpCosPiTest_q;
WHEN "10" => expRPostExc_uid97_fpCosPiTest_q <= cstBias_uid10_fpCosPiTest_q;
WHEN "11" => expRPostExc_uid97_fpCosPiTest_q <= cstBias_uid10_fpCosPiTest_q;
WHEN OTHERS => expRPostExc_uid97_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--oneFracRPostExc2_uid89_fpCosPiTest(CONSTANT,88)
oneFracRPostExc2_uid89_fpCosPiTest_q <= "0000000000000000000000000000000000000000000000000001";
--fracRComp_uid77_fpCosPiTest(BITSELECT,76)@41
fracRComp_uid77_fpCosPiTest_in <= expFracComp_uid76_fpCosPiTest_q(52 downto 0);
fracRComp_uid77_fpCosPiTest_b <= fracRComp_uid77_fpCosPiTest_in(52 downto 1);
--ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_nor(LOGICAL,903)
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_nor_b <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_sticky_ena_q;
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_nor_q <= not (ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_nor_a or ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_nor_b);
--ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_mem_top(CONSTANT,899)
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_mem_top_q <= "0100010";
--ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmp(LOGICAL,900)
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmp_a <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_mem_top_q;
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux_q);
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmp_q <= "1" when ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmp_a = ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmp_b else "0";
--ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmpReg(REG,901)
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmpReg_q <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmp_q;
END IF;
END PROCESS;
--ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_sticky_ena(REG,904)
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_nor_q = "1") THEN
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_sticky_ena_q <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_enaAnd(LOGICAL,905)
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_enaAnd_a <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_sticky_ena_q;
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_enaAnd_b <= VCC_q;
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_enaAnd_q <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_enaAnd_a and ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_enaAnd_b;
--reg_xIsHalf_uid85_fpCosPiTest_0_to_or_uid87_fpCosPiTest_4(REG,360)@2
reg_xIsHalf_uid85_fpCosPiTest_0_to_or_uid87_fpCosPiTest_4: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_xIsHalf_uid85_fpCosPiTest_0_to_or_uid87_fpCosPiTest_4_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
reg_xIsHalf_uid85_fpCosPiTest_0_to_or_uid87_fpCosPiTest_4_q <= xIsHalf_uid85_fpCosPiTest_q;
END IF;
END PROCESS;
--ld_fxpXFracHalf_uid48_fpCosPiTest_q_to_or_uid87_fpCosPiTest_c(DELAY,483)@2
ld_fxpXFracHalf_uid48_fpCosPiTest_q_to_or_uid87_fpCosPiTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => fxpXFracHalf_uid48_fpCosPiTest_q, xout => ld_fxpXFracHalf_uid48_fpCosPiTest_q_to_or_uid87_fpCosPiTest_c_q, clk => clk, aclr => areset );
--or_uid87_fpCosPiTest(LOGICAL,86)@3
or_uid87_fpCosPiTest_a <= ld_cosXIsOne_uid38_fpCosPiTest_c_to_or_uid87_fpCosPiTest_a_q;
or_uid87_fpCosPiTest_b <= xIsInt_uid82_fpCosPiTest_q;
or_uid87_fpCosPiTest_c <= ld_fxpXFracHalf_uid48_fpCosPiTest_q_to_or_uid87_fpCosPiTest_c_q;
or_uid87_fpCosPiTest_d <= ld_expXIsZero_uid24_fpCosPiTest_q_to_or_uid87_fpCosPiTest_d_q;
or_uid87_fpCosPiTest_e <= reg_xIsHalf_uid85_fpCosPiTest_0_to_or_uid87_fpCosPiTest_4_q;
or_uid87_fpCosPiTest_f <= GND_q;
or_uid87_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
or_uid87_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
or_uid87_fpCosPiTest_q <= or_uid87_fpCosPiTest_a or or_uid87_fpCosPiTest_b or or_uid87_fpCosPiTest_c or or_uid87_fpCosPiTest_d or or_uid87_fpCosPiTest_e or or_uid87_fpCosPiTest_f;
END IF;
END PROCESS;
--ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt(COUNTER,895)
-- every=1, low=0, high=34, step=1, init=1
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_i = 33 THEN
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_eq <= '1';
ELSE
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_eq <= '0';
END IF;
IF (ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_i <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_i - 34;
ELSE
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_i <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_i,6));
--ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdreg(REG,896)
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdreg_q <= "000000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdreg_q <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux(MUX,897)
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux_s <= VCC_q;
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux: PROCESS (ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux_s, ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdreg_q, ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_q)
BEGIN
CASE ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux_s IS
WHEN "0" => ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux_q <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdreg_q;
WHEN "1" => ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux_q <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem(DUALMEM,894)
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_ia <= or_uid87_fpCosPiTest_q;
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_aa <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdreg_q;
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_ab <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_rdmux_q;
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 35,
width_b => 1,
widthad_b => 6,
numwords_b => 35,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_iq,
address_a => ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_aa,
data_a => ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_ia
);
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_q <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_iq(0 downto 0);
--ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_outputreg(DELAY,893)
ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_outputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_replace_mem_q, xout => ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_outputreg_q, clk => clk, aclr => areset );
--fracRPostExc1_uid88_fpCosPiTest(MUX,87)@41
fracRPostExc1_uid88_fpCosPiTest_s <= ld_or_uid87_fpCosPiTest_q_to_fracRPostExc1_uid88_fpCosPiTest_b_outputreg_q;
fracRPostExc1_uid88_fpCosPiTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
fracRPostExc1_uid88_fpCosPiTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
CASE fracRPostExc1_uid88_fpCosPiTest_s IS
WHEN "0" => fracRPostExc1_uid88_fpCosPiTest_q <= fracRComp_uid77_fpCosPiTest_b;
WHEN "1" => fracRPostExc1_uid88_fpCosPiTest_q <= cstAllZWF_uid9_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc1_uid88_fpCosPiTest_q <= (others => '0');
END CASE;
END IF;
END PROCESS;
--ld_xIn_v_to_xOut_v_nor(LOGICAL,853)
ld_xIn_v_to_xOut_v_nor_a <= ld_xIn_v_to_xOut_v_notEnable_q;
ld_xIn_v_to_xOut_v_nor_b <= ld_xIn_v_to_xOut_v_sticky_ena_q;
ld_xIn_v_to_xOut_v_nor_q <= not (ld_xIn_v_to_xOut_v_nor_a or ld_xIn_v_to_xOut_v_nor_b);
--ld_xIn_v_to_xOut_v_mem_top(CONSTANT,849)
ld_xIn_v_to_xOut_v_mem_top_q <= "0100111";
--ld_xIn_v_to_xOut_v_cmp(LOGICAL,850)
ld_xIn_v_to_xOut_v_cmp_a <= ld_xIn_v_to_xOut_v_mem_top_q;
ld_xIn_v_to_xOut_v_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIn_v_to_xOut_v_replace_rdmux_q);
ld_xIn_v_to_xOut_v_cmp_q <= "1" when ld_xIn_v_to_xOut_v_cmp_a = ld_xIn_v_to_xOut_v_cmp_b else "0";
--ld_xIn_v_to_xOut_v_cmpReg(REG,851)
ld_xIn_v_to_xOut_v_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_v_to_xOut_v_cmpReg_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_xIn_v_to_xOut_v_cmpReg_q <= ld_xIn_v_to_xOut_v_cmp_q;
END IF;
END PROCESS;
--ld_xIn_v_to_xOut_v_sticky_ena(REG,854)
ld_xIn_v_to_xOut_v_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_v_to_xOut_v_sticky_ena_q <= "0";
ELSIF(clk'EVENT AND clk = '1') THEN
IF (ld_xIn_v_to_xOut_v_nor_q = "1") THEN
ld_xIn_v_to_xOut_v_sticky_ena_q <= ld_xIn_v_to_xOut_v_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_xIn_v_to_xOut_v_enaAnd(LOGICAL,855)
ld_xIn_v_to_xOut_v_enaAnd_a <= ld_xIn_v_to_xOut_v_sticky_ena_q;
ld_xIn_v_to_xOut_v_enaAnd_b <= VCC_q;
ld_xIn_v_to_xOut_v_enaAnd_q <= ld_xIn_v_to_xOut_v_enaAnd_a and ld_xIn_v_to_xOut_v_enaAnd_b;
--ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_inputreg(DELAY,906)
ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => excRNaN_uid86_fpCosPiTest_q, xout => ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_inputreg_q, clk => clk, aclr => areset );
--ld_xIn_v_to_xOut_v_replace_rdcnt(COUNTER,845)
-- every=1, low=0, high=39, step=1, init=1
ld_xIn_v_to_xOut_v_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_v_to_xOut_v_replace_rdcnt_i <= TO_UNSIGNED(1,6);
ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF ld_xIn_v_to_xOut_v_replace_rdcnt_i = 38 THEN
ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '1';
ELSE
ld_xIn_v_to_xOut_v_replace_rdcnt_eq <= '0';
END IF;
IF (ld_xIn_v_to_xOut_v_replace_rdcnt_eq = '1') THEN
ld_xIn_v_to_xOut_v_replace_rdcnt_i <= ld_xIn_v_to_xOut_v_replace_rdcnt_i - 39;
ELSE
ld_xIn_v_to_xOut_v_replace_rdcnt_i <= ld_xIn_v_to_xOut_v_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_xIn_v_to_xOut_v_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIn_v_to_xOut_v_replace_rdcnt_i,6));
--ld_xIn_v_to_xOut_v_replace_rdreg(REG,846)
ld_xIn_v_to_xOut_v_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_xIn_v_to_xOut_v_replace_rdreg_q <= "000000";
ELSIF(clk'EVENT AND clk = '1') THEN
ld_xIn_v_to_xOut_v_replace_rdreg_q <= ld_xIn_v_to_xOut_v_replace_rdcnt_q;
END IF;
END PROCESS;
--ld_xIn_v_to_xOut_v_replace_rdmux(MUX,847)
ld_xIn_v_to_xOut_v_replace_rdmux_s <= VCC_q;
ld_xIn_v_to_xOut_v_replace_rdmux: PROCESS (ld_xIn_v_to_xOut_v_replace_rdmux_s, ld_xIn_v_to_xOut_v_replace_rdreg_q, ld_xIn_v_to_xOut_v_replace_rdcnt_q)
BEGIN
CASE ld_xIn_v_to_xOut_v_replace_rdmux_s IS
WHEN "0" => ld_xIn_v_to_xOut_v_replace_rdmux_q <= ld_xIn_v_to_xOut_v_replace_rdreg_q;
WHEN "1" => ld_xIn_v_to_xOut_v_replace_rdmux_q <= ld_xIn_v_to_xOut_v_replace_rdcnt_q;
WHEN OTHERS => ld_xIn_v_to_xOut_v_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem(DUALMEM,907)
ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0 <= areset;
ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_ia <= ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_inputreg_q;
ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q;
ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q;
ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 40,
width_b => 1,
widthad_b => 6,
numwords_b => 40,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_iq,
address_a => ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_aa,
data_a => ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_ia
);
ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_q <= ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_iq(0 downto 0);
--fracRPostExc_uid90_fpCosPiTest(MUX,89)@42
fracRPostExc_uid90_fpCosPiTest_s <= ld_excRNaN_uid86_fpCosPiTest_q_to_fracRPostExc_uid90_fpCosPiTest_b_replace_mem_q;
fracRPostExc_uid90_fpCosPiTest: PROCESS (fracRPostExc_uid90_fpCosPiTest_s, fracRPostExc1_uid88_fpCosPiTest_q)
BEGIN
CASE fracRPostExc_uid90_fpCosPiTest_s IS
WHEN "0" => fracRPostExc_uid90_fpCosPiTest_q <= fracRPostExc1_uid88_fpCosPiTest_q;
WHEN "1" => fracRPostExc_uid90_fpCosPiTest_q <= oneFracRPostExc2_uid89_fpCosPiTest_q;
WHEN OTHERS => fracRPostExc_uid90_fpCosPiTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid104_fpCosPiTest(BITJOIN,103)@42
R_uid104_fpCosPiTest_q <= ld_signR_uid103_fpCosPiTest_q_to_R_uid104_fpCosPiTest_c_replace_mem_q & expRPostExc_uid97_fpCosPiTest_q & fracRPostExc_uid90_fpCosPiTest_q;
--ld_xIn_c_to_xOut_c_replace_mem(DUALMEM,857)
ld_xIn_c_to_xOut_c_replace_mem_reset0 <= areset;
ld_xIn_c_to_xOut_c_replace_mem_ia <= xIn_c;
ld_xIn_c_to_xOut_c_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q;
ld_xIn_c_to_xOut_c_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q;
ld_xIn_c_to_xOut_c_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 6,
numwords_a => 40,
width_b => 8,
widthad_b => 6,
numwords_b => 40,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_xIn_c_to_xOut_c_replace_mem_reset0,
clock1 => clk,
address_b => ld_xIn_c_to_xOut_c_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xIn_c_to_xOut_c_replace_mem_iq,
address_a => ld_xIn_c_to_xOut_c_replace_mem_aa,
data_a => ld_xIn_c_to_xOut_c_replace_mem_ia
);
ld_xIn_c_to_xOut_c_replace_mem_q <= ld_xIn_c_to_xOut_c_replace_mem_iq(7 downto 0);
--ld_xIn_c_to_xOut_c_outputreg(DELAY,856)
ld_xIn_c_to_xOut_c_outputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => ld_xIn_c_to_xOut_c_replace_mem_q, xout => ld_xIn_c_to_xOut_c_outputreg_q, clk => clk, aclr => areset );
--ld_xIn_v_to_xOut_v_replace_mem(DUALMEM,844)
ld_xIn_v_to_xOut_v_replace_mem_reset0 <= areset;
ld_xIn_v_to_xOut_v_replace_mem_ia <= xIn_v;
ld_xIn_v_to_xOut_v_replace_mem_aa <= ld_xIn_v_to_xOut_v_replace_rdreg_q;
ld_xIn_v_to_xOut_v_replace_mem_ab <= ld_xIn_v_to_xOut_v_replace_rdmux_q;
ld_xIn_v_to_xOut_v_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 1,
widthad_a => 6,
numwords_a => 40,
width_b => 1,
widthad_b => 6,
numwords_b => 40,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_a => "CLOCK1",
outdata_reg_b => "CLOCK1",
outdata_aclr_a => "CLEAR1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
-- indata_aclr_a => "CLEAR0",
-- indata_aclr_b => "CLEAR0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_xIn_v_to_xOut_v_enaAnd_q(0),
clocken0 => '1',
wren_a => VCC_q(0),
clock0 => clk,
aclr1 => ld_xIn_v_to_xOut_v_replace_mem_reset0,
clock1 => clk,
address_b => ld_xIn_v_to_xOut_v_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_xIn_v_to_xOut_v_replace_mem_iq,
address_a => ld_xIn_v_to_xOut_v_replace_mem_aa,
data_a => ld_xIn_v_to_xOut_v_replace_mem_ia
);
ld_xIn_v_to_xOut_v_replace_mem_q <= ld_xIn_v_to_xOut_v_replace_mem_iq(0 downto 0);
--ld_xIn_v_to_xOut_v_outputreg(DELAY,843)
ld_xIn_v_to_xOut_v_outputreg : dspba_delay
GENERIC MAP ( width => 1, depth => 1 )
PORT MAP ( xin => ld_xIn_v_to_xOut_v_replace_mem_q, xout => ld_xIn_v_to_xOut_v_outputreg_q, clk => clk, aclr => areset );
--xOut(PORTOUT,4)@42
xOut_v <= ld_xIn_v_to_xOut_v_outputreg_q;
xOut_c <= ld_xIn_c_to_xOut_c_outputreg_q;
xOut_0 <= R_uid104_fpCosPiTest_q;
end normal;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
Gaussian_Filter/ip/Gaussian_Filter/hcc_delay.vhd
|
10
|
3399
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_DELAY.VHD ***
--*** ***
--*** Function: Delay an arbitrary width an ***
--*** arbitrary number of stages ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_delay IS
GENERIC (
width : positive := 32;
delay : positive := 10;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END hcc_delay;
ARCHITECTURE rtl OF hcc_delay IS
type delmemfftype IS ARRAY (delay DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1);
signal delmemff : delmemfftype;
signal delinff, deloutff : STD_LOGIC_VECTOR (width DOWNTO 1);
component hcc_delmem
GENERIC (
width : positive := 64;
delay : positive := 18
);
PORT (
sysclk : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gda: IF (delay = 1) GENERATE
pone: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
delinff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delinff <= aa;
END IF;
END IF;
END PROCESS;
cc <= delinff;
END GENERATE;
gdb: IF ( ((delay > 1) AND (delay < 5) AND synthesize = 1) OR ((delay > 1) AND synthesize = 0)) GENERATE
ptwo: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR j IN 1 TO delay LOOP
FOR k IN 1 TO width LOOP
delmemff(j)(k) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
delmemff(1)(width DOWNTO 1) <= aa;
FOR k IN 2 TO delay LOOP
delmemff(k)(width DOWNTO 1) <= delmemff(k-1)(width DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
cc <= delmemff(delay)(width DOWNTO 1);
END GENERATE;
gdc: IF (delay > 4 AND synthesize = 1) GENERATE
core: hcc_delmem
GENERIC MAP (width=>width,delay=>delay)
PORT MAP (sysclk=>sysclk,enable=>enable,
aa=>aa,cc=>cc);
END GENERATE;
END rtl;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
Gaussian_Filter/ip/Gaussian_Filter/dp_lsft64.vhd
|
10
|
4251
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_LSFT64.VHD ***
--*** ***
--*** Function: Combinatorial Left Shift 64 ***
--*** Bits ***
--*** ***
--*** 01/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_lsft64 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END dp_lsft64;
ARCHITECTURE rtl of dp_lsft64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
gla: FOR k IN 4 TO 64 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k-2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k-3) AND shift(2) AND shift(1));
END GENERATE;
levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(2) AND NOT(shift(2)) AND shift(1)) OR
(levzip(1) AND shift(2) AND NOT(shift(1)));
levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(1) AND NOT(shift(2)) AND shift(1));
levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1)));
glba: FOR k IN 13 TO 64 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3))) OR
(levone(k-12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 9 TO 12 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k-8) AND shift(4) AND NOT(shift(3)));
END GENERATE;
glbc: FOR k IN 5 TO 8 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k-4) AND NOT(shift(4)) AND shift(3));
END GENERATE;
glbd: FOR k IN 1 TO 4 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3)));
END GENERATE;
glca: FOR k IN 49 TO 64 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5))) OR
(levtwo(k-48) AND shift(6) AND shift(5));
END GENERATE;
glcb: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR
(levtwo(k-32) AND shift(6) AND NOT(shift(5)));
END GENERATE;
glcc: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR
(levtwo(k-16) AND NOT(shift(6)) AND shift(5));
END GENERATE;
glcd: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
Gaussian_Filter/ip/Gaussian_Filter/fp_sqrroot.vhd
|
10
|
5288
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--********************************************************************
--*** ***
--*** FP_SQRROOT.VHD ***
--*** ***
--*** Fixed Point Square Root Core - Restoring ***
--*** ***
--*** 21/12/06 ML ***
--*** ***
--*** Copyright Altera 2006 ***
--*** ***
--*** ***
--********************************************************************
ENTITY fp_sqrroot IS
GENERIC (width : positive := 52);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
rad : IN STD_LOGIC_VECTOR (width+1 DOWNTO 1);
root : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END fp_sqrroot;
ARCHITECTURE rtl OF fp_sqrroot IS
type nodetype IS ARRAY (width DOWNTO 1) OF STD_LOGIC_VECTOR (width+2 DOWNTO 1);
type qfftype IS ARRAY (width-1 DOWNTO 1) OF STD_LOGIC_VECTOR (width-1 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (width DOWNTO 1);
signal onevec : STD_LOGIC_VECTOR (width+1 DOWNTO 1);
signal subnode, slevel, qlevel, radff : nodetype;
signal qff : qfftype;
BEGIN
gza: FOR k IN 1 TO width GENERATE
zerovec(k) <= '0';
END GENERATE;
onevec <= "01" & zerovec(width-1 DOWNTO 1);
-- 1 <= input range < 4, therefore 1 <= root < 2
-- input may be shifted left by 1, therefore first subtract "001" not "01"
slevel(1)(width+2 DOWNTO 1) <= '0' & rad;
qlevel(1)(width+2 DOWNTO 1) <= "001" & zerovec(width-1 DOWNTO 1);
subnode(1)(width+2 DOWNTO width) <= slevel(1)(width+2 DOWNTO width) - qlevel(1)(width+2 DOWNTO width);
subnode(1)(width-1 DOWNTO 1) <= slevel(1)(width-1 DOWNTO 1);
slevel(2)(width+2 DOWNTO 1) <= radff(1)(width+1 DOWNTO 1) & '0';
qlevel(2)(width+2 DOWNTO 1) <= "0101" & zerovec(width-2 DOWNTO 1);
subnode(2)(width+2 DOWNTO width-1) <= slevel(2)(width+2 DOWNTO width-1) - qlevel(2)(width+2 DOWNTO width-1);
subnode(2)(width-2 DOWNTO 1) <= slevel(2)(width-2 DOWNTO 1);
gla: FOR k IN 3 TO width GENERATE
glb: FOR j IN 1 TO k-2 GENERATE
qlevel(k)(width+1-j) <= qff(width-j)(k-1-j);
END GENERATE;
END GENERATE;
gsa: FOR k IN 3 TO width-1 GENERATE
slevel(k)(width+2 DOWNTO 1) <= radff(k-1)(width+1 DOWNTO 1) & '0';
qlevel(k)(width+2 DOWNTO width+1) <= "01";
qlevel(k)(width+2-k DOWNTO 1) <= "01" & zerovec(width-k DOWNTO 1);
subnode(k)(width+2 DOWNTO width+1-k) <= slevel(k)(width+2 DOWNTO width+1-k) -
qlevel(k)(width+2 DOWNTO width+1-k);
subnode(k)(width-k DOWNTO 1) <= slevel(k)(width-k DOWNTO 1);
END GENERATE;
slevel(width)(width+2 DOWNTO 1) <= radff(width-1)(width+1 DOWNTO 1) & '0';
qlevel(width)(width+2 DOWNTO width+1) <= "01";
qlevel(width)(2 DOWNTO 1) <= "01";
subnode(width)(width+2 DOWNTO 1) <= slevel(width)(width+2 DOWNTO 1) - qlevel(width)(width+2 DOWNTO 1);
pma: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO width LOOP
FOR j IN 1 TO width+2 LOOP
radff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO width-1 LOOP
FOR j IN 1 TO width-1 LOOP
qff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
radff(1)(width+2 DOWNTO 1) <= subnode(1)(width+2 DOWNTO 1);
FOR k IN 2 TO width LOOP
FOR j IN 1 TO width+2 LOOP
radff(k)(j) <= (slevel(k)(j) AND subnode(k)(width+2)) OR
(subnode(k)(j) AND NOT(subnode(k)(width+2)));
END LOOP;
END LOOP;
FOR k IN 1 TO width-1 LOOP
qff(width-k)(1) <= NOT(subnode(k+1)(width+2));
FOR j IN 2 TO width-1 LOOP
qff(k)(j) <= qff(k)(j-1);
END LOOP;
END LOOP;
END IF;
END IF;
END PROCESS;
fro: FOR k IN 1 TO width-1 GENERATE
root(k) <= qff(k)(k);
END GENERATE;
root(width) <= '1';
END rtl;
|
mit
|
Reiuiji/ECE368-Lab
|
Lab 3/VGA Part 1/vga_controller.vhd
|
3
|
4026
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: VGA Controller
-- Project Name: VGA
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Driver a VGA display
-- Display out an resolution of 800x600@60Hz
-- Notes:
-- For more information on a VGA display:
-- https://eewiki.net/pages/viewpage.action?pageId=15925278
-- http://digilentinc.com/Data/Documents/Reference%20Designs/VGA%20RefComp.zip
-- Always read the spec sheets
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vga_controller is
Port ( RST : in std_logic;
PIXEL_CLK : inout std_logic;
HS : out std_logic;
VS : out std_logic;
HCOUNT : out std_logic_vector(10 downto 0);
VCOUNT : out std_logic_vector(10 downto 0);
BLANK : out std_logic);
end vga_controller;
architecture Behavioral of vga_controller is
-- maximum value - horizontal pixel counter
constant HMAX : std_logic_vector(10 downto 0) := "10000100000"; -- 1056
-- maximum value - vertical pixel counter
constant VMAX : std_logic_vector(10 downto 0) := "01001110100"; -- 628
-- total visible columns
constant HLINES: std_logic_vector(10 downto 0) := "01100100000"; -- 800
-- horizontal counter - front porch ends
constant HFP : std_logic_vector(10 downto 0) := "01101001000"; -- 840
-- horizontal counter - synch pulse ends
constant HSP : std_logic_vector(10 downto 0) := "01111001000"; -- 968
-- total visible lines
constant VLINES: std_logic_vector(10 downto 0) := "01001011000"; -- 600
-- vertical counter - front porch ends
constant VFP : std_logic_vector(10 downto 0) := "01001011001"; -- 601
-- vertical counter - synch pulse ends
constant VSP : std_logic_vector(10 downto 0) := "01001011101"; -- 605
-- polarity of the horizontal and vertical synch pulse
constant SPP : std_logic := '1';
signal hcounter : std_logic_vector(10 downto 0) := (others => '0');
signal vcounter : std_logic_vector(10 downto 0) := (others => '0');
signal video_enable: std_logic;
begin
hcount <= hcounter;
vcount <= vcounter;
blank <= not video_enable when rising_edge(PIXEL_CLK);
video_enable <= '1' when (hcounter < HLINES and vcounter < VLINES) else '0';
-- horizontal counter
h_count: process(PIXEL_CLK)
begin
if(rising_edge(PIXEL_CLK)) then
if(rst = '1') then
hcounter <= (others => '0');
elsif(hcounter = HMAX) then
hcounter <= (others => '0');
else
hcounter <= hcounter + 1;
end if;
end if;
end process h_count;
-- vertical counter
v_count: process(PIXEL_CLK)
begin
if(rising_edge(PIXEL_CLK)) then
if(rst = '1') then
vcounter <= (others => '0');
elsif(hcounter = HMAX) then
if(vcounter = VMAX) then
vcounter <= (others => '0');
else
vcounter <= vcounter + 1;
end if;
end if;
end if;
end process v_count;
-- horizontal synch pulse
do_hs: process(PIXEL_CLK)
begin
if(rising_edge(PIXEL_CLK)) then
if(hcounter >= HFP and hcounter < HSP) then
HS <= SPP;
else
HS <= not SPP;
end if;
end if;
end process do_hs;
-- generate vertical synch pulse
do_vs: process(PIXEL_CLK)
begin
if(rising_edge(PIXEL_CLK)) then
if(vcounter >= VFP and vcounter < VSP) then
VS <= SPP;
else
VS <= not SPP;
end if;
end if;
end process do_vs;
end Behavioral;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
bin_Gaussian_Filter/ip/Gaussian_Filter/fp_atan_core1.vhd
|
10
|
8323
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_ATAN_CORE1.VHD ***
--*** ***
--*** Function: Single Precision Floating Point ***
--*** ATAN Core for ACOS/ASIN Function ***
--*** ***
--*** 23/12/09 ML ***
--*** ***
--*** (c) 2009 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** 1. Latency = 21 ***
--*** 2. Valid for inputs < 1 ***
--***************************************************
ENTITY fp_atan_core1 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1);
mantissain : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
atan : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
END fp_atan_core1;
ARCHITECTURE rtl OF fp_atan_core1 IS
constant b_precision : positive := 10;
signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal mantissainff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal a_fixedpointff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal luttermff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal ab_plusoneff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal atan_sumff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal a_shift : STD_LOGIC_VECTOR (8 DOWNTO 1);
signal a_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal b_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal c_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal b_address : STD_LOGIC_VECTOR (10 DOWNTO 1);
signal lutterm : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal dellutterm : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal ab_fixedpoint : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal numerator, denominator : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal addterm : STD_LOGIC_VECTOR (36 DOWNTO 1);
component fp_inv_core
GENERIC (synthesize : integer := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
divisor : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
quotient : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_rsft36
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_fxmul
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_atanlut
PORT (
add : IN STD_LOGIC_VECTOR (10 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 36 GENERATE
zerovec(k) <= '0';
END GENERATE;
pinx: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
mantissainff(k) <= '0';
END LOOP;
FOR k IN 1 TO 8 LOOP
exponentinff(k) <= '0';
END LOOP;
FOR k IN 1 TO 36 LOOP
a_fixedpointff(k) <= '0';
luttermff(k) <= '0';
ab_plusoneff(k) <= '0';
atan_sumff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
mantissainff <= mantissain; -- level 1
exponentinff <= exponentin; -- level 1
a_fixedpointff <= a_fixedpoint; -- level 2
luttermff <= lutterm; -- level 4
ab_plusoneff <= '1' & ab_fixedpoint(35 DOWNTO 1); -- ab_fixedpoint always 1/4 true value, level 6
atan_sumff <= dellutterm + (zerovec(9 DOWNTO 1) & addterm(36 DOWNTO 10));
END IF;
END IF;
END PROCESS;
a_shift <= 127 - exponentinff; -- a_exponent will always be 126 or less
asr: fp_rsft36
PORT MAP (inbus=>mantissainff,shift=>a_shift(6 DOWNTO 1),
outbus=>a_fixedpoint);
b_fixedpoint <= a_fixedpoint(36 DOWNTO 37-b_precision) & zerovec(36-b_precision DOWNTO 1);
c_fixedpoint <= a_fixedpoint(36-b_precision DOWNTO 1) & zerovec(b_precision DOWNTO 1);
b_address <= a_fixedpointff(36 DOWNTO 37-b_precision);
-- level 3
clut: fp_atanlut
PORT MAP (add=>b_address,
data=>lutterm);
-- level 3 in, level 20 out
cdlut: fp_del
GENERIC MAP (width=>36,pipes=>17)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>luttermff,
cc=>dellutterm);
-- level 1 in, level 17 out
cdnum: fp_del
GENERIC MAP (width=>36,pipes=>16)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>c_fixedpoint,
cc=>numerator);
-- level 2 in, level 5 out
cmab: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>37,
pipes=>3,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>a_fixedpoint,databb=>b_fixedpoint,
result=>ab_fixedpoint);
-- level 5 in, level 17 out
cinv: fp_inv_core
GENERIC MAP (synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
divisor=>ab_plusoneff,
quotient=>denominator);
-- level 17 in, level 20 out
cmo: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>36,
pipes=>3,synthesize=>0)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>numerator,databb=>denominator,
result=>addterm);
--*** OUTPUTS ***
atan <= atan_sumff;
end rtl;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
Gaussian_Filter/ip/Gaussian_Filter/hcc_normusgn3236_sv.vhd
|
10
|
4902
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_NORMFP2X.VHD ***
--*** ***
--*** Function: Normalize 32 or 36 bit unsigned ***
--*** mantissa ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_normusgn3236 IS
GENERIC (
mantissa : positive := 32;
normspeed : positive := 1 -- 1 or 2
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); -- 1 clock earlier than fracout
fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1)
);
END hcc_normusgn3236;
ARCHITECTURE rtl OF hcc_normusgn3236 IS
signal count, countff : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracff : STD_LOGIC_VECTOR (mantissa DOWNTO 1);
component hcc_cntusgn32 IS
PORT (
frac : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_cntusgn36 IS
PORT (
frac : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
count : OUT STD_LOGIC_VECTOR (6 DOWNTO 1)
);
end component;
component hcc_lsftpipe32 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftcomb32 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
component hcc_lsftpipe36 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
component hcc_lsftcomb36 IS
PORT (
inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1)
);
end component;
BEGIN
pfrc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
countff <= "000000";
FOR k IN 1 TO mantissa LOOP
fracff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
countff <= count;
fracff <= fracin;
END IF;
END IF;
END PROCESS;
gna: IF (mantissa = 32) GENERATE
countone: hcc_cntusgn32
PORT MAP (frac=>fracin,count=>count);
gnb: IF (normspeed = 1) GENERATE
shiftone: hcc_lsftcomb32
PORT MAP (inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnc: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftone: hcc_lsftpipe32
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(5 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
gnd: IF (mantissa = 36) GENERATE
counttwo: hcc_cntusgn36
PORT MAP (frac=>fracin,count=>count);
gne: IF (normspeed = 1) GENERATE
shiftthr: hcc_lsftcomb36
PORT MAP (inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
gnf: IF (normspeed > 1) GENERATE -- if mixed single & double, 3 is possible
shiftfor: hcc_lsftpipe36
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
inbus=>fracff,shift=>countff(6 DOWNTO 1),
outbus=>fracout);
END GENERATE;
END GENERATE;
countout <= countff; -- same time as fracout for normspeed = 1, 1 clock earlier otherwise
END rtl;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
Gaussian_Filter/ip/Gaussian_Filter/dp_invsqr_core.vhd
|
10
|
13707
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** DOUBLE PRECISION INVERSE SQUARE ROOT ***
--*** CORE ***
--*** ***
--*** DP_INVSQR_CORE.VHD ***
--*** ***
--*** Function: 54 bit Inverse Square Root ***
--*** (multiplicative iterative algorithm) ***
--*** ***
--*** 09/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 24/04/09 - SIII/SIV multiplier support ***
--*** ***
--*** ***
--***************************************************
--***************************************************
--*** Notes: ***
--*** SII Latency = 31 + 2*doublespeed ***
--*** SIII/IV Latency = 30 + doublespeed ***
--*** 1. Output is rounded already, LSB always 0 ***
--***************************************************
ENTITY dp_invsqr_core IS
GENERIC (
doublespeed : integer := 0; -- 0/1
doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 1 -- 0/1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (54 DOWNTO 1);
odd : IN STD_LOGIC;
invroot : OUT STD_LOGIC_VECTOR (54 DOWNTO 1)
);
END dp_invsqr_core;
ARCHITECTURE rtl OF dp_invsqr_core IS
--SII mullatency = speed+5, SIII/IV mullatency = 4
constant mullatency : positive := doublespeed+5 - device*(1+doublespeed);
signal zerovec : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal evennum : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal oddnum : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal guessvec : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal oddff : STD_LOGIC_VECTOR (25+doublespeed DOWNTO 1);
signal scalenumff : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal guess : STD_LOGIC_VECTOR (18 DOWNTO 1);
-- 1st iteration
signal radicanddelone : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal guessdel : STD_LOGIC_VECTOR (18 DOWNTO 1);
signal multoneone : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multonetwo : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal multonetwoff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal suboneff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multonethr : STD_LOGIC_VECTOR (37 DOWNTO 1);
signal guessonevec : STD_LOGIC_VECTOR (36 DOWNTO 1);
-- 2ns iteration
signal radicanddeltwo : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal guessonevecdelone : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal guessonevecdeltwo : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal multtwoone : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal multtwotwo : STD_LOGIC_VECTOR (72 DOWNTO 1);
signal multtwotwoff : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal finaladdsub : STD_LOGIC;
signal finaladdsubff : STD_LOGIC_VECTOR (4 DOWNTO 1);
signal finaladdff : STD_LOGIC_VECTOR (55 DOWNTO 1);
signal multtwothr : STD_LOGIC_VECTOR (36 DOWNTO 1);
signal finalguessvec : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal invrootvec : STD_LOGIC_VECTOR (53 DOWNTO 1);
component fp_invsqr_est IS
GENERIC (synthesize : integer := 0); -- 0 = behavioral, 1 = syntheziable
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
radicand : IN STD_LOGIC_VECTOR (19 DOWNTO 1);
invroot : OUT STD_LOGIC_VECTOR (18 DOWNTO 1)
);
end component;
component dp_fxadd IS
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component fp_fxmul IS
GENERIC (
widthaa : positive := 18;
widthbb : positive := 18;
widthcc : positive := 36;
pipes : positive := 1;
accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier
device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4)
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1);
databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1);
result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1)
);
end component;
component fp_del
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (width DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
oddnum <= conv_std_logic_vector(185363,18); -- mult by 2^-.5 (odd exp)
evennum <= conv_std_logic_vector(262143,18); -- mult by 1 (even exp)
gza: FOR k IN 1 TO 54 GENERATE
zerovec(k) <= '0';
END GENERATE;
-- in level 0, out level 5
look: fp_invsqr_est
GENERIC MAP (synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
radicand=>radicand(54 DOWNTO 36),invroot=>guessvec);
pta: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 25+doublespeed LOOP
oddff(k) <= '0';
END LOOP;
FOR k IN 1 TO 18 LOOP
scalenumff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
oddff(1) <= odd;
FOR k IN 2 TO 25+doublespeed LOOP
oddff(k) <= oddff(k-1);
END LOOP;
FOR k IN 1 TO 18 LOOP
scalenumff(k) <= (oddnum(k) AND oddff(4)) OR (evennum(k) AND NOT(oddff(4)));
END LOOP;
END IF;
END IF;
END PROCESS;
-- in level 5, out level 7
mulscale: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>18,pipes=>2,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guessvec,databb=>scalenumff,
result=>guess);
--*********************
--*** ITERATION ONE ***
--*********************
--X' = X/2(3-YXX)
deloneone: fp_del
GENERIC MAP(width=>54,pipes=>9)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>radicand,cc=>radicanddelone);
delonetwo: fp_del
GENERIC MAP(width=>18,pipes=>7)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guess,cc=>guessdel);
-- in level 7, out level 9 (18x18=36)
oneone: fp_fxmul
GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36,pipes=>2,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guess,databb=>guess,
result=>multoneone);
-- in level 9, out level 12 (36x36=37)
onetwo: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>37,pipes=>3,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>radicanddelone(54 DOWNTO 19),databb=>multoneone,
result=>multonetwo);
-- multonetwo is about 1 - either 1.000000XXX or 0.9999999
-- mult by 2 if odd exponent (37 DOWNTO 2), otherwise (38 DOWNTO 3)
-- round bit in position 1 or 2
pone: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
multonetwoff(k) <= '0';
suboneff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
--invert here so that borrow can be added in simple expression
-- level 13
FOR k IN 1 TO 36 LOOP
multonetwoff(k) <= NOT((multonetwo(k) AND oddff(12)) OR (multonetwo(k+1) AND NOT(oddff(12))));
END LOOP;
-- level 14
suboneff <= ("11" & zerovec(34 DOWNTO 1)) +
('1' & multonetwoff(36 DOWNTO 2)) +
(zerovec(35 DOWNTO 1) & multonetwoff(1));
END IF;
END IF;
END PROCESS;
-- in level 14, out level 17 (36x18=37)
onethr: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>18,widthcc=>37,pipes=>3,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>suboneff,databb=>guessdel,
result=>multonethr);
-- mult by 2 - subone is about 1 (1.000 or 0.9999) so will effectively multiply by 0.5
guessonevec <= multonethr(36 DOWNTO 1);
--************************
--*** SECOND ITERATION ***
--************************
--X' = X/2(3-YXX)
deltwoone: fp_del
GENERIC MAP(width=>54,pipes=>11)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>radicanddelone,cc=>radicanddeltwo);
-- SII level in 17, level out 26+doublespeed
-- SIII/IV level in 17, level out 25
deltwotwo: fp_del
GENERIC MAP(width=>36,pipes=>(9+doublespeed-device*(1+doublespeed)))
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guessonevec,cc=>guessonevecdelone);
deltwothr: fp_del
GENERIC MAP (width=>36,pipes=>4)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>guessonevecdelone,cc=>guessonevecdeltwo);
-- in level 17, out level 20 (36x36=54)
twoone: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>54,pipes=>3,
accuracy=>doubleaccuracy,device=>device,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>guessonevec,databb=>guessonevec,
result=>multtwoone);
-- in level 20,
-- SII out level 25/26 - 25+doublespeed
-- SIII/SIV out level 24
twotwo: fp_fxmul
GENERIC MAP (widthaa=>54,widthbb=>54,widthcc=>72,pipes=>mullatency,
accuracy=>doubleaccuracy,device=>device,
synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multtwoone,databb=>radicanddeltwo,
result=>multtwotwo);
-- multtwotwo is about 1 - either 1.000000XXX or 0.9999999
-- mult by 2 if odd exponent (55 DOWNTO 2), otherwise (56 DOWNTO 3)
-- round bit in position 1 or 2
ptwo: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 36 LOOP
multtwotwoff(k) <= '0';
END LOOP;
finaladdsubff <= "0000";
FOR k IN 1 TO 55 LOOP
finaladdff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
-- SII in level 25+doublespeed, out level 26+doublespeed
-- SIII in level 24, out level 25
-- if multwotwo > 1, subtwo negative, subtract multwothr from guessonevec
-- if multwotwo <= 1, subtwo positive, add multwothr to guessonevec
FOR k IN 1 TO 36 LOOP
multtwotwoff(k) <= ((multtwotwo(k+6) AND oddff(25+doublespeed-device*(1+doublespeed))) OR
(multtwotwo(k+7) AND NOT(oddff(25+doublespeed-device*(1+doublespeed))))) XOR finaladdsub;
END LOOP;
finaladdsubff(1) <= finaladdsub;
FOR k IN 2 TO 4 LOOP
finaladdsubff(k) <= finaladdsubff(k-1);
END LOOP;
-- makes sure no overflow happens here, for example if less than 30 leading 1s/0s
-- in multtwotwoff
-- SII level in 29+doublespeed level out 30+doublespeed
-- SIII level in 28 level out 29
FOR k IN 1 TO 26 LOOP
finaladdff(k) <= multtwothr(k+10) XOR NOT(finaladdsubff(4));
END LOOP;
FOR k IN 27 TO 55 LOOP
finaladdff(k) <= NOT(finaladdsubff(4));
END LOOP;
END IF;
END IF;
END PROCESS;
-- doesnt have to be near msb
finaladdsub <= multtwotwo(60);
-- SII level in (26+doublespeed), level out (29+doublespeed)
-- SII level in 25, level out 28
twothr: fp_fxmul
GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>36,pipes=>3,
device=>device,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
dataaa=>multtwotwoff,databb=>guessonevecdelone,
result=>multtwothr);
finalguessvec <= guessonevecdeltwo & zerovec(17 DOWNTO 1);
-- SII level in 30+doublespeed, level out 31+2*doublespeed
-- SIII level in 29, level out 30+doublespeed
final: dp_fxadd
GENERIC MAP (width=>53,pipes=>doublespeed+1,synthesize=>synthesize)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>finalguessvec,bb=>finaladdff(55 DOWNTO 3),carryin=>finaladdff(2),
cc=>invrootvec);
invroot <= invrootvec & '0';
END rtl;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
Gaussian_Filter/ip/Gaussian_Filter/dspba_library_sv.vhd
|
22
|
1907
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_loop: for i in depth-1 downto 0 generate
begin
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
xout <= delay_signals(0);
end delay;
|
mit
|
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC
|
bin_Gaussian_Filter/ip/Gaussian_Filter/dspba_library.vhd
|
22
|
1907
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural;
depth : natural;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_loop: for i in depth-1 downto 0 generate
begin
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
xout <= delay_signals(0);
end delay;
|
mit
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