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MarkBlanco/FPGA_Sandbox
|
RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_1/impl/vhdl/project.srcs/sources_1/ip/convolve_kernel_ap_fadd_7_full_dsp_32/hdl/xbip_utils_v3_0_vh_rfs.vhd
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7
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171224
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`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect end_protected
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_1/impl/vhdl/project.srcs/sources_1/ip/convolve_kernel_ap_fmul_3_max_dsp_32/hdl/xbip_utils_v3_0_vh_rfs.vhd
|
7
|
171224
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinxt_2017_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VELOCE-RSA", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-2", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 124208)
`protect data_block
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`protect end_protected
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/93db88faeb00921e/zqynq_lab_1_design_axi_timer_0_1_sim_netlist.vhdl
|
1
|
419053
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Fri Sep 22 23:00:37 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_timer_0_1_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_axi_timer_0_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
port (
captureTrig0_d0 : out STD_LOGIC;
read_Mux_In : in STD_LOGIC_VECTOR ( 0 to 0 );
capturetrig0 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
signal CaptureTrig0_int : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => capturetrig0,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d3,
Q => CaptureTrig0_int,
R => '0'
);
captureTrig0_d_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => read_Mux_In(0),
I1 => CaptureTrig0_int,
O => captureTrig0_d0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_1 is
port (
captureTrig1_d0 : out STD_LOGIC;
read_Mux_In : in STD_LOGIC_VECTOR ( 0 to 0 );
capturetrig1 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_1 : entity is "cdc_sync";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_1 is
signal CaptureTrig1_int : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => capturetrig1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d3,
Q => CaptureTrig1_int,
R => '0'
);
captureTrig1_d_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => read_Mux_In(0),
I1 => CaptureTrig1_int,
O => captureTrig1_d0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_2 is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\INFERRED_GEN.icount_out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
S : out STD_LOGIC_VECTOR ( 0 to 0 );
\INFERRED_GEN.icount_out_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\TCSR0_GENERATE[20].TCSR0_FF_I\ : in STD_LOGIC;
\TCSR0_GENERATE[24].TCSR0_FF_I\ : in STD_LOGIC;
counter_TC : in STD_LOGIC_VECTOR ( 0 to 1 );
read_Mux_In : in STD_LOGIC_VECTOR ( 7 downto 0 );
generateOutPre0 : in STD_LOGIC;
\TCSR1_GENERATE[24].TCSR1_FF_I\ : in STD_LOGIC;
Load_Counter_Reg030_out : in STD_LOGIC;
Load_Counter_Reg031_out : in STD_LOGIC;
\Load_Counter_Reg0__0\ : in STD_LOGIC;
Load_Counter_Reg028_out : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
freeze : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_2 : entity is "cdc_sync";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_2 is
signal \Counter_En041_out__2\ : STD_LOGIC;
signal \Counter_En043_out__0\ : STD_LOGIC;
signal \Counter_En045_out__1\ : STD_LOGIC;
signal \Counter_En0__4\ : STD_LOGIC;
signal Freeze_int : STD_LOGIC;
signal counter_En : STD_LOGIC_VECTOR ( 0 to 1 );
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => freeze,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d3,
Q => Freeze_int,
R => '0'
);
\INFERRED_GEN.icount_out[31]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FCFFFCAA"
)
port map (
I0 => Load_Counter_Reg030_out,
I1 => Load_Counter_Reg031_out,
I2 => \Counter_En043_out__0\,
I3 => \TCSR0_GENERATE[20].TCSR0_FF_I\,
I4 => \Counter_En041_out__2\,
O => E(0)
);
\INFERRED_GEN.icount_out[31]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FCFFFCAA"
)
port map (
I0 => \Load_Counter_Reg0__0\,
I1 => Load_Counter_Reg028_out,
I2 => \Counter_En045_out__1\,
I3 => \TCSR0_GENERATE[20].TCSR0_FF_I\,
I4 => \Counter_En0__4\,
O => \INFERRED_GEN.icount_out_reg[0]\(0)
);
\INFERRED_GEN.icount_out[31]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00FB0000"
)
port map (
I0 => read_Mux_In(4),
I1 => counter_TC(1),
I2 => read_Mux_In(6),
I3 => Freeze_int,
I4 => \TCSR0_GENERATE[24].TCSR0_FF_I\,
O => \Counter_En043_out__0\
);
\INFERRED_GEN.icount_out[31]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4040404040004040"
)
port map (
I0 => Freeze_int,
I1 => \TCSR0_GENERATE[24].TCSR0_FF_I\,
I2 => generateOutPre0,
I3 => read_Mux_In(6),
I4 => counter_TC(1),
I5 => read_Mux_In(4),
O => \Counter_En045_out__1\
);
\INFERRED_GEN.icount_out[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444444444404"
)
port map (
I0 => Freeze_int,
I1 => \TCSR0_GENERATE[24].TCSR0_FF_I\,
I2 => counter_TC(0),
I3 => read_Mux_In(7),
I4 => read_Mux_In(6),
I5 => read_Mux_In(4),
O => \Counter_En041_out__2\
);
\INFERRED_GEN.icount_out[31]_i_6__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2222222222202222"
)
port map (
I0 => \TCSR1_GENERATE[24].TCSR1_FF_I\,
I1 => Freeze_int,
I2 => read_Mux_In(3),
I3 => read_Mux_In(2),
I4 => counter_TC(1),
I5 => read_Mux_In(0),
O => \Counter_En0__4\
);
icount_out0_carry_i_5: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \INFERRED_GEN.icount_out_reg[1]\(1),
I1 => counter_En(0),
I2 => read_Mux_In(5),
O => S(0)
);
\icount_out0_carry_i_5__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"6A666AAA"
)
port map (
I0 => \INFERRED_GEN.icount_out_reg[1]\(0),
I1 => counter_En(1),
I2 => read_Mux_In(5),
I3 => \TCSR0_GENERATE[20].TCSR0_FF_I\,
I4 => read_Mux_In(1),
O => \INFERRED_GEN.icount_out_reg[4]\(0)
);
icount_out0_carry_i_6: unisim.vcomponents.MUXF7
port map (
I0 => \Counter_En041_out__2\,
I1 => \Counter_En043_out__0\,
O => counter_En(0),
S => \TCSR0_GENERATE[20].TCSR0_FF_I\
);
\icount_out0_carry_i_6__0\: unisim.vcomponents.MUXF7
port map (
I0 => \Counter_En0__4\,
I1 => \Counter_En045_out__1\,
O => counter_En(1),
S => \TCSR0_GENERATE[20].TCSR0_FF_I\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_counter_f is
port (
Q : out STD_LOGIC_VECTOR ( 31 downto 0 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_rdata_i_reg[0]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[1]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[2]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[3]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[4]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[5]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[6]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[7]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[8]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[9]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[10]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[11]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[12]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[13]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[14]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[15]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[16]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[17]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[18]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[19]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[20]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[21]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[22]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[23]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[24]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[25]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[26]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[27]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[28]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[29]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[30]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[31]\ : out STD_LOGIC;
generateOutPre1_reg : out STD_LOGIC;
counter_TC : out STD_LOGIC_VECTOR ( 0 to 0 );
S : in STD_LOGIC_VECTOR ( 0 to 0 );
read_Mux_In : in STD_LOGIC_VECTOR ( 31 downto 0 );
load_Counter_Reg : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aresetn : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[31]_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
\counter_TC_Reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_counter_f;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_counter_f is
signal \INFERRED_GEN.icount_out[0]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[10]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[11]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[12]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[13]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[14]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[15]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[16]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[17]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[18]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[19]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[1]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[20]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[21]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[22]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[23]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[24]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[25]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[26]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[27]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[28]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[29]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[2]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[30]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[31]_i_2_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[32]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[3]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[4]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[5]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[6]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[7]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[8]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[9]_i_1_n_0\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^counter_tc\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \icount_out0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_n_1\ : STD_LOGIC;
signal \icount_out0_carry__0_n_2\ : STD_LOGIC;
signal \icount_out0_carry__0_n_3\ : STD_LOGIC;
signal \icount_out0_carry__0_n_4\ : STD_LOGIC;
signal \icount_out0_carry__0_n_5\ : STD_LOGIC;
signal \icount_out0_carry__0_n_6\ : STD_LOGIC;
signal \icount_out0_carry__0_n_7\ : STD_LOGIC;
signal \icount_out0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_n_1\ : STD_LOGIC;
signal \icount_out0_carry__1_n_2\ : STD_LOGIC;
signal \icount_out0_carry__1_n_3\ : STD_LOGIC;
signal \icount_out0_carry__1_n_4\ : STD_LOGIC;
signal \icount_out0_carry__1_n_5\ : STD_LOGIC;
signal \icount_out0_carry__1_n_6\ : STD_LOGIC;
signal \icount_out0_carry__1_n_7\ : STD_LOGIC;
signal \icount_out0_carry__2_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_n_1\ : STD_LOGIC;
signal \icount_out0_carry__2_n_2\ : STD_LOGIC;
signal \icount_out0_carry__2_n_3\ : STD_LOGIC;
signal \icount_out0_carry__2_n_4\ : STD_LOGIC;
signal \icount_out0_carry__2_n_5\ : STD_LOGIC;
signal \icount_out0_carry__2_n_6\ : STD_LOGIC;
signal \icount_out0_carry__2_n_7\ : STD_LOGIC;
signal \icount_out0_carry__3_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_n_1\ : STD_LOGIC;
signal \icount_out0_carry__3_n_2\ : STD_LOGIC;
signal \icount_out0_carry__3_n_3\ : STD_LOGIC;
signal \icount_out0_carry__3_n_4\ : STD_LOGIC;
signal \icount_out0_carry__3_n_5\ : STD_LOGIC;
signal \icount_out0_carry__3_n_6\ : STD_LOGIC;
signal \icount_out0_carry__3_n_7\ : STD_LOGIC;
signal \icount_out0_carry__4_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_n_1\ : STD_LOGIC;
signal \icount_out0_carry__4_n_2\ : STD_LOGIC;
signal \icount_out0_carry__4_n_3\ : STD_LOGIC;
signal \icount_out0_carry__4_n_4\ : STD_LOGIC;
signal \icount_out0_carry__4_n_5\ : STD_LOGIC;
signal \icount_out0_carry__4_n_6\ : STD_LOGIC;
signal \icount_out0_carry__4_n_7\ : STD_LOGIC;
signal \icount_out0_carry__5_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_n_1\ : STD_LOGIC;
signal \icount_out0_carry__5_n_2\ : STD_LOGIC;
signal \icount_out0_carry__5_n_3\ : STD_LOGIC;
signal \icount_out0_carry__5_n_4\ : STD_LOGIC;
signal \icount_out0_carry__5_n_5\ : STD_LOGIC;
signal \icount_out0_carry__5_n_6\ : STD_LOGIC;
signal \icount_out0_carry__5_n_7\ : STD_LOGIC;
signal \icount_out0_carry__6_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_n_1\ : STD_LOGIC;
signal \icount_out0_carry__6_n_2\ : STD_LOGIC;
signal \icount_out0_carry__6_n_3\ : STD_LOGIC;
signal \icount_out0_carry__6_n_4\ : STD_LOGIC;
signal \icount_out0_carry__6_n_5\ : STD_LOGIC;
signal \icount_out0_carry__6_n_6\ : STD_LOGIC;
signal \icount_out0_carry__6_n_7\ : STD_LOGIC;
signal icount_out0_carry_i_1_n_0 : STD_LOGIC;
signal icount_out0_carry_i_2_n_0 : STD_LOGIC;
signal icount_out0_carry_i_3_n_0 : STD_LOGIC;
signal icount_out0_carry_i_4_n_0 : STD_LOGIC;
signal icount_out0_carry_n_0 : STD_LOGIC;
signal icount_out0_carry_n_1 : STD_LOGIC;
signal icount_out0_carry_n_2 : STD_LOGIC;
signal icount_out0_carry_n_3 : STD_LOGIC;
signal icount_out0_carry_n_4 : STD_LOGIC;
signal icount_out0_carry_n_5 : STD_LOGIC;
signal icount_out0_carry_n_6 : STD_LOGIC;
signal icount_out0_carry_n_7 : STD_LOGIC;
signal \NLW_icount_out0_carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[0]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[10]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[11]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[12]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[13]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[14]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[15]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[16]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[17]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[18]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[19]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[1]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[20]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[21]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[22]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[23]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[24]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[25]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[26]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[27]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[28]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[29]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[2]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[30]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[31]_i_2\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[3]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[4]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[5]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[6]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[7]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[8]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[9]_i_1\ : label is "soft_lutpair45";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of icount_out0_carry : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__0\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__1\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__2\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__3\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__4\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__5\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__6\ : label is "{SYNTH-8 {cell *THIS*}}";
begin
Q(31 downto 0) <= \^q\(31 downto 0);
SR(0) <= \^sr\(0);
counter_TC(0) <= \^counter_tc\(0);
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(31),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(31),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(31),
O => \s_axi_rdata_i_reg[31]\
);
\GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(21),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(21),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(21),
O => \s_axi_rdata_i_reg[21]\
);
\GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(20),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(20),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(20),
O => \s_axi_rdata_i_reg[20]\
);
\GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(19),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(19),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(19),
O => \s_axi_rdata_i_reg[19]\
);
\GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(18),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(18),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(18),
O => \s_axi_rdata_i_reg[18]\
);
\GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(17),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(17),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(17),
O => \s_axi_rdata_i_reg[17]\
);
\GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(16),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(16),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(16),
O => \s_axi_rdata_i_reg[16]\
);
\GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(15),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(15),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(15),
O => \s_axi_rdata_i_reg[15]\
);
\GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(14),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(14),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(14),
O => \s_axi_rdata_i_reg[14]\
);
\GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(13),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(13),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(13),
O => \s_axi_rdata_i_reg[13]\
);
\GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(12),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(12),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(12),
O => \s_axi_rdata_i_reg[12]\
);
\GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(30),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(30),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(30),
O => \s_axi_rdata_i_reg[30]\
);
\GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(11),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(11),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(11),
O => \s_axi_rdata_i_reg[11]\
);
\GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(10),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(10),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(10),
O => \s_axi_rdata_i_reg[10]\
);
\GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(9),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(9),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(9),
O => \s_axi_rdata_i_reg[9]\
);
\GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(8),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(8),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(8),
O => \s_axi_rdata_i_reg[8]\
);
\GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(7),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(7),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(7),
O => \s_axi_rdata_i_reg[7]\
);
\GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(6),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(6),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(6),
O => \s_axi_rdata_i_reg[6]\
);
\GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(5),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(5),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(5),
O => \s_axi_rdata_i_reg[5]\
);
\GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(4),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(4),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(4),
O => \s_axi_rdata_i_reg[4]\
);
\GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(3),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(3),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(3),
O => \s_axi_rdata_i_reg[3]\
);
\GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(2),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(2),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(2),
O => \s_axi_rdata_i_reg[2]\
);
\GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(29),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(29),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(29),
O => \s_axi_rdata_i_reg[29]\
);
\GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(1),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(1),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(1),
O => \s_axi_rdata_i_reg[1]\
);
\GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(0),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(0),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(0),
O => \s_axi_rdata_i_reg[0]\
);
\GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(28),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(28),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(28),
O => \s_axi_rdata_i_reg[28]\
);
\GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(27),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(27),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(27),
O => \s_axi_rdata_i_reg[27]\
);
\GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(26),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(26),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(26),
O => \s_axi_rdata_i_reg[26]\
);
\GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(25),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(25),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(25),
O => \s_axi_rdata_i_reg[25]\
);
\GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(24),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(24),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(24),
O => \s_axi_rdata_i_reg[24]\
);
\GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(23),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(23),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(23),
O => \s_axi_rdata_i_reg[23]\
);
\GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(22),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(22),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(22),
O => \s_axi_rdata_i_reg[22]\
);
GenerateOut0_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => \^sr\(0)
);
\INFERRED_GEN.icount_out[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"A3"
)
port map (
I0 => read_Mux_In(0),
I1 => \^q\(0),
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[0]_i_1_n_0\
);
\INFERRED_GEN.icount_out[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(10),
I1 => \icount_out0_carry__1_n_6\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[10]_i_1_n_0\
);
\INFERRED_GEN.icount_out[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(11),
I1 => \icount_out0_carry__1_n_5\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[11]_i_1_n_0\
);
\INFERRED_GEN.icount_out[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(12),
I1 => \icount_out0_carry__1_n_4\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[12]_i_1_n_0\
);
\INFERRED_GEN.icount_out[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(13),
I1 => \icount_out0_carry__2_n_7\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[13]_i_1_n_0\
);
\INFERRED_GEN.icount_out[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(14),
I1 => \icount_out0_carry__2_n_6\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[14]_i_1_n_0\
);
\INFERRED_GEN.icount_out[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(15),
I1 => \icount_out0_carry__2_n_5\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[15]_i_1_n_0\
);
\INFERRED_GEN.icount_out[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(16),
I1 => \icount_out0_carry__2_n_4\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[16]_i_1_n_0\
);
\INFERRED_GEN.icount_out[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(17),
I1 => \icount_out0_carry__3_n_7\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[17]_i_1_n_0\
);
\INFERRED_GEN.icount_out[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(18),
I1 => \icount_out0_carry__3_n_6\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[18]_i_1_n_0\
);
\INFERRED_GEN.icount_out[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(19),
I1 => \icount_out0_carry__3_n_5\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[19]_i_1_n_0\
);
\INFERRED_GEN.icount_out[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(1),
I1 => icount_out0_carry_n_7,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[1]_i_1_n_0\
);
\INFERRED_GEN.icount_out[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(20),
I1 => \icount_out0_carry__3_n_4\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[20]_i_1_n_0\
);
\INFERRED_GEN.icount_out[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(21),
I1 => \icount_out0_carry__4_n_7\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[21]_i_1_n_0\
);
\INFERRED_GEN.icount_out[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(22),
I1 => \icount_out0_carry__4_n_6\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[22]_i_1_n_0\
);
\INFERRED_GEN.icount_out[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(23),
I1 => \icount_out0_carry__4_n_5\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[23]_i_1_n_0\
);
\INFERRED_GEN.icount_out[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(24),
I1 => \icount_out0_carry__4_n_4\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[24]_i_1_n_0\
);
\INFERRED_GEN.icount_out[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(25),
I1 => \icount_out0_carry__5_n_7\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[25]_i_1_n_0\
);
\INFERRED_GEN.icount_out[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(26),
I1 => \icount_out0_carry__5_n_6\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[26]_i_1_n_0\
);
\INFERRED_GEN.icount_out[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(27),
I1 => \icount_out0_carry__5_n_5\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[27]_i_1_n_0\
);
\INFERRED_GEN.icount_out[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(28),
I1 => \icount_out0_carry__5_n_4\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[28]_i_1_n_0\
);
\INFERRED_GEN.icount_out[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(29),
I1 => \icount_out0_carry__6_n_7\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[29]_i_1_n_0\
);
\INFERRED_GEN.icount_out[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(2),
I1 => icount_out0_carry_n_6,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[2]_i_1_n_0\
);
\INFERRED_GEN.icount_out[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(30),
I1 => \icount_out0_carry__6_n_6\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[30]_i_1_n_0\
);
\INFERRED_GEN.icount_out[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(31),
I1 => \icount_out0_carry__6_n_5\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[31]_i_2_n_0\
);
\INFERRED_GEN.icount_out[32]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000E200"
)
port map (
I0 => \^counter_tc\(0),
I1 => E(0),
I2 => \icount_out0_carry__6_n_4\,
I3 => s_axi_aresetn,
I4 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[32]_i_1_n_0\
);
\INFERRED_GEN.icount_out[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(3),
I1 => icount_out0_carry_n_5,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[3]_i_1_n_0\
);
\INFERRED_GEN.icount_out[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(4),
I1 => icount_out0_carry_n_4,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[4]_i_1_n_0\
);
\INFERRED_GEN.icount_out[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(5),
I1 => \icount_out0_carry__0_n_7\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[5]_i_1_n_0\
);
\INFERRED_GEN.icount_out[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(6),
I1 => \icount_out0_carry__0_n_6\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[6]_i_1_n_0\
);
\INFERRED_GEN.icount_out[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(7),
I1 => \icount_out0_carry__0_n_5\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[7]_i_1_n_0\
);
\INFERRED_GEN.icount_out[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(8),
I1 => \icount_out0_carry__0_n_4\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[8]_i_1_n_0\
);
\INFERRED_GEN.icount_out[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(9),
I1 => \icount_out0_carry__1_n_7\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[9]_i_1_n_0\
);
\INFERRED_GEN.icount_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[0]_i_1_n_0\,
Q => \^q\(0),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[10]_i_1_n_0\,
Q => \^q\(10),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[11]_i_1_n_0\,
Q => \^q\(11),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[12]_i_1_n_0\,
Q => \^q\(12),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[13]_i_1_n_0\,
Q => \^q\(13),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[14]_i_1_n_0\,
Q => \^q\(14),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[15]_i_1_n_0\,
Q => \^q\(15),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[16]_i_1_n_0\,
Q => \^q\(16),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[17]_i_1_n_0\,
Q => \^q\(17),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[18]_i_1_n_0\,
Q => \^q\(18),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[19]_i_1_n_0\,
Q => \^q\(19),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[1]_i_1_n_0\,
Q => \^q\(1),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[20]_i_1_n_0\,
Q => \^q\(20),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[21]_i_1_n_0\,
Q => \^q\(21),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[22]_i_1_n_0\,
Q => \^q\(22),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[23]_i_1_n_0\,
Q => \^q\(23),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[24]_i_1_n_0\,
Q => \^q\(24),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[25]_i_1_n_0\,
Q => \^q\(25),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[26]_i_1_n_0\,
Q => \^q\(26),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[27]_i_1_n_0\,
Q => \^q\(27),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[28]_i_1_n_0\,
Q => \^q\(28),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[29]_i_1_n_0\,
Q => \^q\(29),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[2]_i_1_n_0\,
Q => \^q\(2),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[30]_i_1_n_0\,
Q => \^q\(30),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[31]_i_2_n_0\,
Q => \^q\(31),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[32]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \INFERRED_GEN.icount_out[32]_i_1_n_0\,
Q => \^counter_tc\(0),
R => '0'
);
\INFERRED_GEN.icount_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[3]_i_1_n_0\,
Q => \^q\(3),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[4]_i_1_n_0\,
Q => \^q\(4),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[5]_i_1_n_0\,
Q => \^q\(5),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[6]_i_1_n_0\,
Q => \^q\(6),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[7]_i_1_n_0\,
Q => \^q\(7),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[8]_i_1_n_0\,
Q => \^q\(8),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[9]_i_1_n_0\,
Q => \^q\(9),
R => \^sr\(0)
);
generateOutPre1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^counter_tc\(0),
I1 => \counter_TC_Reg_reg[1]\(0),
O => generateOutPre1_reg
);
icount_out0_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => icount_out0_carry_n_0,
CO(2) => icount_out0_carry_n_1,
CO(1) => icount_out0_carry_n_2,
CO(0) => icount_out0_carry_n_3,
CYINIT => \^q\(0),
DI(3 downto 1) => \^q\(3 downto 1),
DI(0) => icount_out0_carry_i_1_n_0,
O(3) => icount_out0_carry_n_4,
O(2) => icount_out0_carry_n_5,
O(1) => icount_out0_carry_n_6,
O(0) => icount_out0_carry_n_7,
S(3) => icount_out0_carry_i_2_n_0,
S(2) => icount_out0_carry_i_3_n_0,
S(1) => icount_out0_carry_i_4_n_0,
S(0) => S(0)
);
\icount_out0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => icount_out0_carry_n_0,
CO(3) => \icount_out0_carry__0_n_0\,
CO(2) => \icount_out0_carry__0_n_1\,
CO(1) => \icount_out0_carry__0_n_2\,
CO(0) => \icount_out0_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^q\(7 downto 4),
O(3) => \icount_out0_carry__0_n_4\,
O(2) => \icount_out0_carry__0_n_5\,
O(1) => \icount_out0_carry__0_n_6\,
O(0) => \icount_out0_carry__0_n_7\,
S(3) => \icount_out0_carry__0_i_1_n_0\,
S(2) => \icount_out0_carry__0_i_2_n_0\,
S(1) => \icount_out0_carry__0_i_3_n_0\,
S(0) => \icount_out0_carry__0_i_4_n_0\
);
\icount_out0_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(7),
I1 => \^q\(8),
O => \icount_out0_carry__0_i_1_n_0\
);
\icount_out0_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(6),
I1 => \^q\(7),
O => \icount_out0_carry__0_i_2_n_0\
);
\icount_out0_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(5),
I1 => \^q\(6),
O => \icount_out0_carry__0_i_3_n_0\
);
\icount_out0_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(4),
I1 => \^q\(5),
O => \icount_out0_carry__0_i_4_n_0\
);
\icount_out0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__0_n_0\,
CO(3) => \icount_out0_carry__1_n_0\,
CO(2) => \icount_out0_carry__1_n_1\,
CO(1) => \icount_out0_carry__1_n_2\,
CO(0) => \icount_out0_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^q\(11 downto 8),
O(3) => \icount_out0_carry__1_n_4\,
O(2) => \icount_out0_carry__1_n_5\,
O(1) => \icount_out0_carry__1_n_6\,
O(0) => \icount_out0_carry__1_n_7\,
S(3) => \icount_out0_carry__1_i_1_n_0\,
S(2) => \icount_out0_carry__1_i_2_n_0\,
S(1) => \icount_out0_carry__1_i_3_n_0\,
S(0) => \icount_out0_carry__1_i_4_n_0\
);
\icount_out0_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(11),
I1 => \^q\(12),
O => \icount_out0_carry__1_i_1_n_0\
);
\icount_out0_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(10),
I1 => \^q\(11),
O => \icount_out0_carry__1_i_2_n_0\
);
\icount_out0_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(9),
I1 => \^q\(10),
O => \icount_out0_carry__1_i_3_n_0\
);
\icount_out0_carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(8),
I1 => \^q\(9),
O => \icount_out0_carry__1_i_4_n_0\
);
\icount_out0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__1_n_0\,
CO(3) => \icount_out0_carry__2_n_0\,
CO(2) => \icount_out0_carry__2_n_1\,
CO(1) => \icount_out0_carry__2_n_2\,
CO(0) => \icount_out0_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^q\(15 downto 12),
O(3) => \icount_out0_carry__2_n_4\,
O(2) => \icount_out0_carry__2_n_5\,
O(1) => \icount_out0_carry__2_n_6\,
O(0) => \icount_out0_carry__2_n_7\,
S(3) => \icount_out0_carry__2_i_1_n_0\,
S(2) => \icount_out0_carry__2_i_2_n_0\,
S(1) => \icount_out0_carry__2_i_3_n_0\,
S(0) => \icount_out0_carry__2_i_4_n_0\
);
\icount_out0_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(15),
I1 => \^q\(16),
O => \icount_out0_carry__2_i_1_n_0\
);
\icount_out0_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(14),
I1 => \^q\(15),
O => \icount_out0_carry__2_i_2_n_0\
);
\icount_out0_carry__2_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(13),
I1 => \^q\(14),
O => \icount_out0_carry__2_i_3_n_0\
);
\icount_out0_carry__2_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(12),
I1 => \^q\(13),
O => \icount_out0_carry__2_i_4_n_0\
);
\icount_out0_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__2_n_0\,
CO(3) => \icount_out0_carry__3_n_0\,
CO(2) => \icount_out0_carry__3_n_1\,
CO(1) => \icount_out0_carry__3_n_2\,
CO(0) => \icount_out0_carry__3_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^q\(19 downto 16),
O(3) => \icount_out0_carry__3_n_4\,
O(2) => \icount_out0_carry__3_n_5\,
O(1) => \icount_out0_carry__3_n_6\,
O(0) => \icount_out0_carry__3_n_7\,
S(3) => \icount_out0_carry__3_i_1_n_0\,
S(2) => \icount_out0_carry__3_i_2_n_0\,
S(1) => \icount_out0_carry__3_i_3_n_0\,
S(0) => \icount_out0_carry__3_i_4_n_0\
);
\icount_out0_carry__3_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(19),
I1 => \^q\(20),
O => \icount_out0_carry__3_i_1_n_0\
);
\icount_out0_carry__3_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(18),
I1 => \^q\(19),
O => \icount_out0_carry__3_i_2_n_0\
);
\icount_out0_carry__3_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(17),
I1 => \^q\(18),
O => \icount_out0_carry__3_i_3_n_0\
);
\icount_out0_carry__3_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(16),
I1 => \^q\(17),
O => \icount_out0_carry__3_i_4_n_0\
);
\icount_out0_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__3_n_0\,
CO(3) => \icount_out0_carry__4_n_0\,
CO(2) => \icount_out0_carry__4_n_1\,
CO(1) => \icount_out0_carry__4_n_2\,
CO(0) => \icount_out0_carry__4_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^q\(23 downto 20),
O(3) => \icount_out0_carry__4_n_4\,
O(2) => \icount_out0_carry__4_n_5\,
O(1) => \icount_out0_carry__4_n_6\,
O(0) => \icount_out0_carry__4_n_7\,
S(3) => \icount_out0_carry__4_i_1_n_0\,
S(2) => \icount_out0_carry__4_i_2_n_0\,
S(1) => \icount_out0_carry__4_i_3_n_0\,
S(0) => \icount_out0_carry__4_i_4_n_0\
);
\icount_out0_carry__4_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(23),
I1 => \^q\(24),
O => \icount_out0_carry__4_i_1_n_0\
);
\icount_out0_carry__4_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(22),
I1 => \^q\(23),
O => \icount_out0_carry__4_i_2_n_0\
);
\icount_out0_carry__4_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(21),
I1 => \^q\(22),
O => \icount_out0_carry__4_i_3_n_0\
);
\icount_out0_carry__4_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(20),
I1 => \^q\(21),
O => \icount_out0_carry__4_i_4_n_0\
);
\icount_out0_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__4_n_0\,
CO(3) => \icount_out0_carry__5_n_0\,
CO(2) => \icount_out0_carry__5_n_1\,
CO(1) => \icount_out0_carry__5_n_2\,
CO(0) => \icount_out0_carry__5_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^q\(27 downto 24),
O(3) => \icount_out0_carry__5_n_4\,
O(2) => \icount_out0_carry__5_n_5\,
O(1) => \icount_out0_carry__5_n_6\,
O(0) => \icount_out0_carry__5_n_7\,
S(3) => \icount_out0_carry__5_i_1_n_0\,
S(2) => \icount_out0_carry__5_i_2_n_0\,
S(1) => \icount_out0_carry__5_i_3_n_0\,
S(0) => \icount_out0_carry__5_i_4_n_0\
);
\icount_out0_carry__5_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(27),
I1 => \^q\(28),
O => \icount_out0_carry__5_i_1_n_0\
);
\icount_out0_carry__5_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(26),
I1 => \^q\(27),
O => \icount_out0_carry__5_i_2_n_0\
);
\icount_out0_carry__5_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(25),
I1 => \^q\(26),
O => \icount_out0_carry__5_i_3_n_0\
);
\icount_out0_carry__5_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(24),
I1 => \^q\(25),
O => \icount_out0_carry__5_i_4_n_0\
);
\icount_out0_carry__6\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__5_n_0\,
CO(3) => \NLW_icount_out0_carry__6_CO_UNCONNECTED\(3),
CO(2) => \icount_out0_carry__6_n_1\,
CO(1) => \icount_out0_carry__6_n_2\,
CO(0) => \icount_out0_carry__6_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => \^q\(30 downto 28),
O(3) => \icount_out0_carry__6_n_4\,
O(2) => \icount_out0_carry__6_n_5\,
O(1) => \icount_out0_carry__6_n_6\,
O(0) => \icount_out0_carry__6_n_7\,
S(3) => \icount_out0_carry__6_i_1_n_0\,
S(2) => \icount_out0_carry__6_i_2_n_0\,
S(1) => \icount_out0_carry__6_i_3_n_0\,
S(0) => \icount_out0_carry__6_i_4_n_0\
);
\icount_out0_carry__6_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(31),
O => \icount_out0_carry__6_i_1_n_0\
);
\icount_out0_carry__6_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(30),
I1 => \^q\(31),
O => \icount_out0_carry__6_i_2_n_0\
);
\icount_out0_carry__6_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(29),
I1 => \^q\(30),
O => \icount_out0_carry__6_i_3_n_0\
);
\icount_out0_carry__6_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(28),
I1 => \^q\(29),
O => \icount_out0_carry__6_i_4_n_0\
);
icount_out0_carry_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(1),
O => icount_out0_carry_i_1_n_0
);
icount_out0_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(3),
I1 => \^q\(4),
O => icount_out0_carry_i_2_n_0
);
icount_out0_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(2),
I1 => \^q\(3),
O => icount_out0_carry_i_3_n_0
);
icount_out0_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(1),
I1 => \^q\(2),
O => icount_out0_carry_i_4_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_counter_f_3 is
port (
\LOAD_REG_GEN[0].LOAD_REG_I\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
generateOutPre0_reg : out STD_LOGIC;
counter_TC : out STD_LOGIC_VECTOR ( 0 to 0 );
S : in STD_LOGIC_VECTOR ( 0 to 0 );
read_Mux_In : in STD_LOGIC_VECTOR ( 10 downto 0 );
load_Counter_Reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\LOAD_REG_GEN[0].LOAD_REG_I_0\ : in STD_LOGIC_VECTOR ( 20 downto 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aresetn_0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_counter_f_3 : entity is "counter_f";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_counter_f_3;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_counter_f_3 is
signal \INFERRED_GEN.icount_out[32]_i_1_n_0\ : STD_LOGIC;
signal \^load_reg_gen[0].load_reg_i\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^counter_tc\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \icount_out0_carry__0_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_n_1\ : STD_LOGIC;
signal \icount_out0_carry__0_n_2\ : STD_LOGIC;
signal \icount_out0_carry__0_n_3\ : STD_LOGIC;
signal \icount_out0_carry__0_n_4\ : STD_LOGIC;
signal \icount_out0_carry__0_n_5\ : STD_LOGIC;
signal \icount_out0_carry__0_n_6\ : STD_LOGIC;
signal \icount_out0_carry__0_n_7\ : STD_LOGIC;
signal \icount_out0_carry__1_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_n_1\ : STD_LOGIC;
signal \icount_out0_carry__1_n_2\ : STD_LOGIC;
signal \icount_out0_carry__1_n_3\ : STD_LOGIC;
signal \icount_out0_carry__1_n_4\ : STD_LOGIC;
signal \icount_out0_carry__1_n_5\ : STD_LOGIC;
signal \icount_out0_carry__1_n_6\ : STD_LOGIC;
signal \icount_out0_carry__1_n_7\ : STD_LOGIC;
signal \icount_out0_carry__2_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_n_1\ : STD_LOGIC;
signal \icount_out0_carry__2_n_2\ : STD_LOGIC;
signal \icount_out0_carry__2_n_3\ : STD_LOGIC;
signal \icount_out0_carry__2_n_4\ : STD_LOGIC;
signal \icount_out0_carry__2_n_5\ : STD_LOGIC;
signal \icount_out0_carry__2_n_6\ : STD_LOGIC;
signal \icount_out0_carry__2_n_7\ : STD_LOGIC;
signal \icount_out0_carry__3_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_n_1\ : STD_LOGIC;
signal \icount_out0_carry__3_n_2\ : STD_LOGIC;
signal \icount_out0_carry__3_n_3\ : STD_LOGIC;
signal \icount_out0_carry__3_n_4\ : STD_LOGIC;
signal \icount_out0_carry__3_n_5\ : STD_LOGIC;
signal \icount_out0_carry__3_n_6\ : STD_LOGIC;
signal \icount_out0_carry__3_n_7\ : STD_LOGIC;
signal \icount_out0_carry__4_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_n_1\ : STD_LOGIC;
signal \icount_out0_carry__4_n_2\ : STD_LOGIC;
signal \icount_out0_carry__4_n_3\ : STD_LOGIC;
signal \icount_out0_carry__4_n_4\ : STD_LOGIC;
signal \icount_out0_carry__4_n_5\ : STD_LOGIC;
signal \icount_out0_carry__4_n_6\ : STD_LOGIC;
signal \icount_out0_carry__4_n_7\ : STD_LOGIC;
signal \icount_out0_carry__5_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_n_1\ : STD_LOGIC;
signal \icount_out0_carry__5_n_2\ : STD_LOGIC;
signal \icount_out0_carry__5_n_3\ : STD_LOGIC;
signal \icount_out0_carry__5_n_4\ : STD_LOGIC;
signal \icount_out0_carry__5_n_5\ : STD_LOGIC;
signal \icount_out0_carry__5_n_6\ : STD_LOGIC;
signal \icount_out0_carry__5_n_7\ : STD_LOGIC;
signal \icount_out0_carry__6_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_n_1\ : STD_LOGIC;
signal \icount_out0_carry__6_n_2\ : STD_LOGIC;
signal \icount_out0_carry__6_n_3\ : STD_LOGIC;
signal \icount_out0_carry__6_n_4\ : STD_LOGIC;
signal \icount_out0_carry__6_n_5\ : STD_LOGIC;
signal \icount_out0_carry__6_n_6\ : STD_LOGIC;
signal \icount_out0_carry__6_n_7\ : STD_LOGIC;
signal \icount_out0_carry_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry_i_4__0_n_0\ : STD_LOGIC;
signal icount_out0_carry_n_0 : STD_LOGIC;
signal icount_out0_carry_n_1 : STD_LOGIC;
signal icount_out0_carry_n_2 : STD_LOGIC;
signal icount_out0_carry_n_3 : STD_LOGIC;
signal icount_out0_carry_n_4 : STD_LOGIC;
signal icount_out0_carry_n_5 : STD_LOGIC;
signal icount_out0_carry_n_6 : STD_LOGIC;
signal icount_out0_carry_n_7 : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_icount_out0_carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[0]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[10]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[11]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[12]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[13]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[14]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[15]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[16]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[17]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[18]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[19]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[1]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[20]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[21]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[22]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[23]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[24]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[25]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[26]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[27]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[28]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[29]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[2]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[30]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[31]_i_2__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[3]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[4]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[5]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[6]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[7]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[8]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[9]_i_1__0\ : label is "soft_lutpair29";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of icount_out0_carry : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__0\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__1\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__2\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__3\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__4\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__5\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__6\ : label is "{SYNTH-8 {cell *THIS*}}";
begin
\LOAD_REG_GEN[0].LOAD_REG_I\(31 downto 0) <= \^load_reg_gen[0].load_reg_i\(31 downto 0);
counter_TC(0) <= \^counter_tc\(0);
\INFERRED_GEN.icount_out[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => read_Mux_In(0),
I1 => load_Counter_Reg(0),
I2 => \^load_reg_gen[0].load_reg_i\(0),
O => p_1_in(0)
);
\INFERRED_GEN.icount_out[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(10),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__1_n_6\,
O => p_1_in(10)
);
\INFERRED_GEN.icount_out[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(0),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__1_n_5\,
O => p_1_in(11)
);
\INFERRED_GEN.icount_out[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(1),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__1_n_4\,
O => p_1_in(12)
);
\INFERRED_GEN.icount_out[13]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(2),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__2_n_7\,
O => p_1_in(13)
);
\INFERRED_GEN.icount_out[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(3),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__2_n_6\,
O => p_1_in(14)
);
\INFERRED_GEN.icount_out[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(4),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__2_n_5\,
O => p_1_in(15)
);
\INFERRED_GEN.icount_out[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(5),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__2_n_4\,
O => p_1_in(16)
);
\INFERRED_GEN.icount_out[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(6),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__3_n_7\,
O => p_1_in(17)
);
\INFERRED_GEN.icount_out[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(7),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__3_n_6\,
O => p_1_in(18)
);
\INFERRED_GEN.icount_out[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(8),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__3_n_5\,
O => p_1_in(19)
);
\INFERRED_GEN.icount_out[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(1),
I1 => load_Counter_Reg(0),
I2 => icount_out0_carry_n_7,
O => p_1_in(1)
);
\INFERRED_GEN.icount_out[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(9),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__3_n_4\,
O => p_1_in(20)
);
\INFERRED_GEN.icount_out[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(10),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__4_n_7\,
O => p_1_in(21)
);
\INFERRED_GEN.icount_out[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(11),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__4_n_6\,
O => p_1_in(22)
);
\INFERRED_GEN.icount_out[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(12),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__4_n_5\,
O => p_1_in(23)
);
\INFERRED_GEN.icount_out[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(13),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__4_n_4\,
O => p_1_in(24)
);
\INFERRED_GEN.icount_out[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(14),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__5_n_7\,
O => p_1_in(25)
);
\INFERRED_GEN.icount_out[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(15),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__5_n_6\,
O => p_1_in(26)
);
\INFERRED_GEN.icount_out[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(16),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__5_n_5\,
O => p_1_in(27)
);
\INFERRED_GEN.icount_out[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(17),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__5_n_4\,
O => p_1_in(28)
);
\INFERRED_GEN.icount_out[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(18),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__6_n_7\,
O => p_1_in(29)
);
\INFERRED_GEN.icount_out[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(2),
I1 => load_Counter_Reg(0),
I2 => icount_out0_carry_n_6,
O => p_1_in(2)
);
\INFERRED_GEN.icount_out[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(19),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__6_n_6\,
O => p_1_in(30)
);
\INFERRED_GEN.icount_out[31]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(20),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__6_n_5\,
O => p_1_in(31)
);
\INFERRED_GEN.icount_out[32]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000E200"
)
port map (
I0 => \^counter_tc\(0),
I1 => E(0),
I2 => \icount_out0_carry__6_n_4\,
I3 => s_axi_aresetn,
I4 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[32]_i_1_n_0\
);
\INFERRED_GEN.icount_out[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(3),
I1 => load_Counter_Reg(0),
I2 => icount_out0_carry_n_5,
O => p_1_in(3)
);
\INFERRED_GEN.icount_out[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(4),
I1 => load_Counter_Reg(0),
I2 => icount_out0_carry_n_4,
O => p_1_in(4)
);
\INFERRED_GEN.icount_out[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(5),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__0_n_7\,
O => p_1_in(5)
);
\INFERRED_GEN.icount_out[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(6),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__0_n_6\,
O => p_1_in(6)
);
\INFERRED_GEN.icount_out[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(7),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__0_n_5\,
O => p_1_in(7)
);
\INFERRED_GEN.icount_out[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(8),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__0_n_4\,
O => p_1_in(8)
);
\INFERRED_GEN.icount_out[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(9),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__1_n_7\,
O => p_1_in(9)
);
\INFERRED_GEN.icount_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(0),
Q => \^load_reg_gen[0].load_reg_i\(0),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(10),
Q => \^load_reg_gen[0].load_reg_i\(10),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(11),
Q => \^load_reg_gen[0].load_reg_i\(11),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(12),
Q => \^load_reg_gen[0].load_reg_i\(12),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(13),
Q => \^load_reg_gen[0].load_reg_i\(13),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(14),
Q => \^load_reg_gen[0].load_reg_i\(14),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(15),
Q => \^load_reg_gen[0].load_reg_i\(15),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(16),
Q => \^load_reg_gen[0].load_reg_i\(16),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(17),
Q => \^load_reg_gen[0].load_reg_i\(17),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(18),
Q => \^load_reg_gen[0].load_reg_i\(18),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(19),
Q => \^load_reg_gen[0].load_reg_i\(19),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(1),
Q => \^load_reg_gen[0].load_reg_i\(1),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(20),
Q => \^load_reg_gen[0].load_reg_i\(20),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(21),
Q => \^load_reg_gen[0].load_reg_i\(21),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(22),
Q => \^load_reg_gen[0].load_reg_i\(22),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(23),
Q => \^load_reg_gen[0].load_reg_i\(23),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(24),
Q => \^load_reg_gen[0].load_reg_i\(24),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(25),
Q => \^load_reg_gen[0].load_reg_i\(25),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(26),
Q => \^load_reg_gen[0].load_reg_i\(26),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(27),
Q => \^load_reg_gen[0].load_reg_i\(27),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(28),
Q => \^load_reg_gen[0].load_reg_i\(28),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(29),
Q => \^load_reg_gen[0].load_reg_i\(29),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(2),
Q => \^load_reg_gen[0].load_reg_i\(2),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(30),
Q => \^load_reg_gen[0].load_reg_i\(30),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(31),
Q => \^load_reg_gen[0].load_reg_i\(31),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[32]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \INFERRED_GEN.icount_out[32]_i_1_n_0\,
Q => \^counter_tc\(0),
R => '0'
);
\INFERRED_GEN.icount_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(3),
Q => \^load_reg_gen[0].load_reg_i\(3),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(4),
Q => \^load_reg_gen[0].load_reg_i\(4),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(5),
Q => \^load_reg_gen[0].load_reg_i\(5),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(6),
Q => \^load_reg_gen[0].load_reg_i\(6),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(7),
Q => \^load_reg_gen[0].load_reg_i\(7),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(8),
Q => \^load_reg_gen[0].load_reg_i\(8),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(9),
Q => \^load_reg_gen[0].load_reg_i\(9),
R => s_axi_aresetn_0
);
generateOutPre0_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^counter_tc\(0),
I1 => Q(0),
O => generateOutPre0_reg
);
icount_out0_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => icount_out0_carry_n_0,
CO(2) => icount_out0_carry_n_1,
CO(1) => icount_out0_carry_n_2,
CO(0) => icount_out0_carry_n_3,
CYINIT => \^load_reg_gen[0].load_reg_i\(0),
DI(3 downto 1) => \^load_reg_gen[0].load_reg_i\(3 downto 1),
DI(0) => \icount_out0_carry_i_1__0_n_0\,
O(3) => icount_out0_carry_n_4,
O(2) => icount_out0_carry_n_5,
O(1) => icount_out0_carry_n_6,
O(0) => icount_out0_carry_n_7,
S(3) => \icount_out0_carry_i_2__0_n_0\,
S(2) => \icount_out0_carry_i_3__0_n_0\,
S(1) => \icount_out0_carry_i_4__0_n_0\,
S(0) => S(0)
);
\icount_out0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => icount_out0_carry_n_0,
CO(3) => \icount_out0_carry__0_n_0\,
CO(2) => \icount_out0_carry__0_n_1\,
CO(1) => \icount_out0_carry__0_n_2\,
CO(0) => \icount_out0_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(7 downto 4),
O(3) => \icount_out0_carry__0_n_4\,
O(2) => \icount_out0_carry__0_n_5\,
O(1) => \icount_out0_carry__0_n_6\,
O(0) => \icount_out0_carry__0_n_7\,
S(3) => \icount_out0_carry__0_i_1__0_n_0\,
S(2) => \icount_out0_carry__0_i_2__0_n_0\,
S(1) => \icount_out0_carry__0_i_3__0_n_0\,
S(0) => \icount_out0_carry__0_i_4__0_n_0\
);
\icount_out0_carry__0_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(7),
I1 => \^load_reg_gen[0].load_reg_i\(8),
O => \icount_out0_carry__0_i_1__0_n_0\
);
\icount_out0_carry__0_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(6),
I1 => \^load_reg_gen[0].load_reg_i\(7),
O => \icount_out0_carry__0_i_2__0_n_0\
);
\icount_out0_carry__0_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(5),
I1 => \^load_reg_gen[0].load_reg_i\(6),
O => \icount_out0_carry__0_i_3__0_n_0\
);
\icount_out0_carry__0_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(4),
I1 => \^load_reg_gen[0].load_reg_i\(5),
O => \icount_out0_carry__0_i_4__0_n_0\
);
\icount_out0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__0_n_0\,
CO(3) => \icount_out0_carry__1_n_0\,
CO(2) => \icount_out0_carry__1_n_1\,
CO(1) => \icount_out0_carry__1_n_2\,
CO(0) => \icount_out0_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(11 downto 8),
O(3) => \icount_out0_carry__1_n_4\,
O(2) => \icount_out0_carry__1_n_5\,
O(1) => \icount_out0_carry__1_n_6\,
O(0) => \icount_out0_carry__1_n_7\,
S(3) => \icount_out0_carry__1_i_1__0_n_0\,
S(2) => \icount_out0_carry__1_i_2__0_n_0\,
S(1) => \icount_out0_carry__1_i_3__0_n_0\,
S(0) => \icount_out0_carry__1_i_4__0_n_0\
);
\icount_out0_carry__1_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(11),
I1 => \^load_reg_gen[0].load_reg_i\(12),
O => \icount_out0_carry__1_i_1__0_n_0\
);
\icount_out0_carry__1_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(10),
I1 => \^load_reg_gen[0].load_reg_i\(11),
O => \icount_out0_carry__1_i_2__0_n_0\
);
\icount_out0_carry__1_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(9),
I1 => \^load_reg_gen[0].load_reg_i\(10),
O => \icount_out0_carry__1_i_3__0_n_0\
);
\icount_out0_carry__1_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(8),
I1 => \^load_reg_gen[0].load_reg_i\(9),
O => \icount_out0_carry__1_i_4__0_n_0\
);
\icount_out0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__1_n_0\,
CO(3) => \icount_out0_carry__2_n_0\,
CO(2) => \icount_out0_carry__2_n_1\,
CO(1) => \icount_out0_carry__2_n_2\,
CO(0) => \icount_out0_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(15 downto 12),
O(3) => \icount_out0_carry__2_n_4\,
O(2) => \icount_out0_carry__2_n_5\,
O(1) => \icount_out0_carry__2_n_6\,
O(0) => \icount_out0_carry__2_n_7\,
S(3) => \icount_out0_carry__2_i_1__0_n_0\,
S(2) => \icount_out0_carry__2_i_2__0_n_0\,
S(1) => \icount_out0_carry__2_i_3__0_n_0\,
S(0) => \icount_out0_carry__2_i_4__0_n_0\
);
\icount_out0_carry__2_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(15),
I1 => \^load_reg_gen[0].load_reg_i\(16),
O => \icount_out0_carry__2_i_1__0_n_0\
);
\icount_out0_carry__2_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(14),
I1 => \^load_reg_gen[0].load_reg_i\(15),
O => \icount_out0_carry__2_i_2__0_n_0\
);
\icount_out0_carry__2_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(13),
I1 => \^load_reg_gen[0].load_reg_i\(14),
O => \icount_out0_carry__2_i_3__0_n_0\
);
\icount_out0_carry__2_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(12),
I1 => \^load_reg_gen[0].load_reg_i\(13),
O => \icount_out0_carry__2_i_4__0_n_0\
);
\icount_out0_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__2_n_0\,
CO(3) => \icount_out0_carry__3_n_0\,
CO(2) => \icount_out0_carry__3_n_1\,
CO(1) => \icount_out0_carry__3_n_2\,
CO(0) => \icount_out0_carry__3_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(19 downto 16),
O(3) => \icount_out0_carry__3_n_4\,
O(2) => \icount_out0_carry__3_n_5\,
O(1) => \icount_out0_carry__3_n_6\,
O(0) => \icount_out0_carry__3_n_7\,
S(3) => \icount_out0_carry__3_i_1__0_n_0\,
S(2) => \icount_out0_carry__3_i_2__0_n_0\,
S(1) => \icount_out0_carry__3_i_3__0_n_0\,
S(0) => \icount_out0_carry__3_i_4__0_n_0\
);
\icount_out0_carry__3_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(19),
I1 => \^load_reg_gen[0].load_reg_i\(20),
O => \icount_out0_carry__3_i_1__0_n_0\
);
\icount_out0_carry__3_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(18),
I1 => \^load_reg_gen[0].load_reg_i\(19),
O => \icount_out0_carry__3_i_2__0_n_0\
);
\icount_out0_carry__3_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(17),
I1 => \^load_reg_gen[0].load_reg_i\(18),
O => \icount_out0_carry__3_i_3__0_n_0\
);
\icount_out0_carry__3_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(16),
I1 => \^load_reg_gen[0].load_reg_i\(17),
O => \icount_out0_carry__3_i_4__0_n_0\
);
\icount_out0_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__3_n_0\,
CO(3) => \icount_out0_carry__4_n_0\,
CO(2) => \icount_out0_carry__4_n_1\,
CO(1) => \icount_out0_carry__4_n_2\,
CO(0) => \icount_out0_carry__4_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(23 downto 20),
O(3) => \icount_out0_carry__4_n_4\,
O(2) => \icount_out0_carry__4_n_5\,
O(1) => \icount_out0_carry__4_n_6\,
O(0) => \icount_out0_carry__4_n_7\,
S(3) => \icount_out0_carry__4_i_1__0_n_0\,
S(2) => \icount_out0_carry__4_i_2__0_n_0\,
S(1) => \icount_out0_carry__4_i_3__0_n_0\,
S(0) => \icount_out0_carry__4_i_4__0_n_0\
);
\icount_out0_carry__4_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(23),
I1 => \^load_reg_gen[0].load_reg_i\(24),
O => \icount_out0_carry__4_i_1__0_n_0\
);
\icount_out0_carry__4_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(22),
I1 => \^load_reg_gen[0].load_reg_i\(23),
O => \icount_out0_carry__4_i_2__0_n_0\
);
\icount_out0_carry__4_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(21),
I1 => \^load_reg_gen[0].load_reg_i\(22),
O => \icount_out0_carry__4_i_3__0_n_0\
);
\icount_out0_carry__4_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(20),
I1 => \^load_reg_gen[0].load_reg_i\(21),
O => \icount_out0_carry__4_i_4__0_n_0\
);
\icount_out0_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__4_n_0\,
CO(3) => \icount_out0_carry__5_n_0\,
CO(2) => \icount_out0_carry__5_n_1\,
CO(1) => \icount_out0_carry__5_n_2\,
CO(0) => \icount_out0_carry__5_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(27 downto 24),
O(3) => \icount_out0_carry__5_n_4\,
O(2) => \icount_out0_carry__5_n_5\,
O(1) => \icount_out0_carry__5_n_6\,
O(0) => \icount_out0_carry__5_n_7\,
S(3) => \icount_out0_carry__5_i_1__0_n_0\,
S(2) => \icount_out0_carry__5_i_2__0_n_0\,
S(1) => \icount_out0_carry__5_i_3__0_n_0\,
S(0) => \icount_out0_carry__5_i_4__0_n_0\
);
\icount_out0_carry__5_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(27),
I1 => \^load_reg_gen[0].load_reg_i\(28),
O => \icount_out0_carry__5_i_1__0_n_0\
);
\icount_out0_carry__5_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(26),
I1 => \^load_reg_gen[0].load_reg_i\(27),
O => \icount_out0_carry__5_i_2__0_n_0\
);
\icount_out0_carry__5_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(25),
I1 => \^load_reg_gen[0].load_reg_i\(26),
O => \icount_out0_carry__5_i_3__0_n_0\
);
\icount_out0_carry__5_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(24),
I1 => \^load_reg_gen[0].load_reg_i\(25),
O => \icount_out0_carry__5_i_4__0_n_0\
);
\icount_out0_carry__6\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__5_n_0\,
CO(3) => \NLW_icount_out0_carry__6_CO_UNCONNECTED\(3),
CO(2) => \icount_out0_carry__6_n_1\,
CO(1) => \icount_out0_carry__6_n_2\,
CO(0) => \icount_out0_carry__6_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => \^load_reg_gen[0].load_reg_i\(30 downto 28),
O(3) => \icount_out0_carry__6_n_4\,
O(2) => \icount_out0_carry__6_n_5\,
O(1) => \icount_out0_carry__6_n_6\,
O(0) => \icount_out0_carry__6_n_7\,
S(3) => \icount_out0_carry__6_i_1__0_n_0\,
S(2) => \icount_out0_carry__6_i_2__0_n_0\,
S(1) => \icount_out0_carry__6_i_3__0_n_0\,
S(0) => \icount_out0_carry__6_i_4__0_n_0\
);
\icount_out0_carry__6_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(31),
O => \icount_out0_carry__6_i_1__0_n_0\
);
\icount_out0_carry__6_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(30),
I1 => \^load_reg_gen[0].load_reg_i\(31),
O => \icount_out0_carry__6_i_2__0_n_0\
);
\icount_out0_carry__6_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(29),
I1 => \^load_reg_gen[0].load_reg_i\(30),
O => \icount_out0_carry__6_i_3__0_n_0\
);
\icount_out0_carry__6_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(28),
I1 => \^load_reg_gen[0].load_reg_i\(29),
O => \icount_out0_carry__6_i_4__0_n_0\
);
\icount_out0_carry_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(1),
O => \icount_out0_carry_i_1__0_n_0\
);
\icount_out0_carry_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(3),
I1 => \^load_reg_gen[0].load_reg_i\(4),
O => \icount_out0_carry_i_2__0_n_0\
);
\icount_out0_carry_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(2),
I1 => \^load_reg_gen[0].load_reg_i\(3),
O => \icount_out0_carry_i_3__0_n_0\
);
\icount_out0_carry_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(1),
I1 => \^load_reg_gen[0].load_reg_i\(2),
O => \icount_out0_carry_i_4__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mux_onehot_f is
port (
D : out STD_LOGIC_VECTOR ( 31 downto 0 );
Bus_RNW_reg_reg : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[31]\ : in STD_LOGIC;
Bus_RNW_reg_reg_0 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[30]\ : in STD_LOGIC;
Bus_RNW_reg_reg_1 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[29]\ : in STD_LOGIC;
Bus_RNW_reg_reg_2 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[28]\ : in STD_LOGIC;
Bus_RNW_reg_reg_3 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[27]\ : in STD_LOGIC;
Bus_RNW_reg_reg_4 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[26]\ : in STD_LOGIC;
Bus_RNW_reg_reg_5 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[25]\ : in STD_LOGIC;
Bus_RNW_reg_reg_6 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[24]\ : in STD_LOGIC;
Bus_RNW_reg_reg_7 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[23]\ : in STD_LOGIC;
Bus_RNW_reg_reg_8 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[22]\ : in STD_LOGIC;
Bus_RNW_reg_reg_9 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[21]\ : in STD_LOGIC;
Bus_RNW_reg_reg_10 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[20]\ : in STD_LOGIC;
Bus_RNW_reg_reg_11 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[19]\ : in STD_LOGIC;
Bus_RNW_reg_reg_12 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[18]\ : in STD_LOGIC;
Bus_RNW_reg_reg_13 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[17]\ : in STD_LOGIC;
Bus_RNW_reg_reg_14 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[16]\ : in STD_LOGIC;
Bus_RNW_reg_reg_15 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[15]\ : in STD_LOGIC;
Bus_RNW_reg_reg_16 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[14]\ : in STD_LOGIC;
Bus_RNW_reg_reg_17 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[13]\ : in STD_LOGIC;
Bus_RNW_reg_reg_18 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[12]\ : in STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[11]\ : in STD_LOGIC;
\LOAD_REG_GEN[21].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[10]\ : in STD_LOGIC;
\LOAD_REG_GEN[22].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[9]\ : in STD_LOGIC;
\LOAD_REG_GEN[23].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[8]\ : in STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[7]\ : in STD_LOGIC;
\LOAD_REG_GEN[25].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[6]\ : in STD_LOGIC;
\LOAD_REG_GEN[26].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[5]\ : in STD_LOGIC;
\LOAD_REG_GEN[27].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[4]\ : in STD_LOGIC;
\LOAD_REG_GEN[28].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[3]\ : in STD_LOGIC;
\LOAD_REG_GEN[29].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[2]\ : in STD_LOGIC;
\LOAD_REG_GEN[30].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[1]\ : in STD_LOGIC;
\LOAD_REG_GEN[31].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[0]\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mux_onehot_f;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mux_onehot_f is
signal \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal cyout_1 : STD_LOGIC;
signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
begin
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(31),
CO(0) => cyout_1,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[31]\,
S(0) => Bus_RNW_reg_reg
);
\GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(21),
CO(0) => \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[21]\,
S(0) => Bus_RNW_reg_reg_9
);
\GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(20),
CO(0) => \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[20]\,
S(0) => Bus_RNW_reg_reg_10
);
\GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(19),
CO(0) => \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[19]\,
S(0) => Bus_RNW_reg_reg_11
);
\GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(18),
CO(0) => \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[18]\,
S(0) => Bus_RNW_reg_reg_12
);
\GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(17),
CO(0) => \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[17]\,
S(0) => Bus_RNW_reg_reg_13
);
\GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(16),
CO(0) => \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[16]\,
S(0) => Bus_RNW_reg_reg_14
);
\GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(15),
CO(0) => \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[15]\,
S(0) => Bus_RNW_reg_reg_15
);
\GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(14),
CO(0) => \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[14]\,
S(0) => Bus_RNW_reg_reg_16
);
\GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(13),
CO(0) => \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[13]\,
S(0) => Bus_RNW_reg_reg_17
);
\GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(12),
CO(0) => \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[12]\,
S(0) => Bus_RNW_reg_reg_18
);
\GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(30),
CO(0) => \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[30]\,
S(0) => Bus_RNW_reg_reg_0
);
\GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(11),
CO(0) => \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[11]\,
S(0) => \LOAD_REG_GEN[20].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(10),
CO(0) => \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[10]\,
S(0) => \LOAD_REG_GEN[21].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(9),
CO(0) => \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[9]\,
S(0) => \LOAD_REG_GEN[22].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(8),
CO(0) => \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[8]\,
S(0) => \LOAD_REG_GEN[23].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(7),
CO(0) => \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[7]\,
S(0) => \LOAD_REG_GEN[24].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(6),
CO(0) => \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[6]\,
S(0) => \LOAD_REG_GEN[25].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(5),
CO(0) => \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[5]\,
S(0) => \LOAD_REG_GEN[26].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(4),
CO(0) => \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[4]\,
S(0) => \LOAD_REG_GEN[27].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(3),
CO(0) => \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[3]\,
S(0) => \LOAD_REG_GEN[28].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(2),
CO(0) => \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[2]\,
S(0) => \LOAD_REG_GEN[29].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(29),
CO(0) => \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[29]\,
S(0) => Bus_RNW_reg_reg_1
);
\GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(1),
CO(0) => \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[1]\,
S(0) => \LOAD_REG_GEN[30].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(0),
CO(0) => \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[0]\,
S(0) => \LOAD_REG_GEN[31].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(28),
CO(0) => \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[28]\,
S(0) => Bus_RNW_reg_reg_2
);
\GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(27),
CO(0) => \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[27]\,
S(0) => Bus_RNW_reg_reg_3
);
\GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(26),
CO(0) => \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[26]\,
S(0) => Bus_RNW_reg_reg_4
);
\GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(25),
CO(0) => \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[25]\,
S(0) => Bus_RNW_reg_reg_5
);
\GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(24),
CO(0) => \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[24]\,
S(0) => Bus_RNW_reg_reg_6
);
\GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(23),
CO(0) => \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[23]\,
S(0) => Bus_RNW_reg_reg_7
);
\GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(22),
CO(0) => \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[22]\,
S(0) => Bus_RNW_reg_reg_8
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f is
port (
ce_expnd_i_7 : out STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f is
begin
CS: unisim.vcomponents.LUT4
generic map(
INIT => X"0010"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(2),
I1 => \bus2ip_addr_i_reg[4]\(1),
I2 => Q,
I3 => \bus2ip_addr_i_reg[4]\(0),
O => ce_expnd_i_7
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized1\ is
port (
ce_expnd_i_5 : out STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized1\ : entity is "pselect_f";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized1\ is
begin
CS: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(2),
I1 => \bus2ip_addr_i_reg[4]\(0),
I2 => Q,
I3 => \bus2ip_addr_i_reg[4]\(1),
O => ce_expnd_i_5
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized3\ is
port (
ce_expnd_i_3 : out STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized3\ : entity is "pselect_f";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized3\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized3\ is
begin
CS: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(1),
I1 => \bus2ip_addr_i_reg[4]\(0),
I2 => \bus2ip_addr_i_reg[4]\(2),
I3 => Q,
O => ce_expnd_i_3
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized4\ is
port (
ce_expnd_i_2 : out STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized4\ : entity is "pselect_f";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized4\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized4\ is
begin
CS: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(1),
I1 => \bus2ip_addr_i_reg[4]\(2),
I2 => Q,
I3 => \bus2ip_addr_i_reg[4]\(0),
O => ce_expnd_i_2
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized5\ is
port (
ce_expnd_i_1 : out STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized5\ : entity is "pselect_f";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized5\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized5\ is
begin
CS: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(0),
I1 => \bus2ip_addr_i_reg[4]\(2),
I2 => Q,
I3 => \bus2ip_addr_i_reg[4]\(1),
O => ce_expnd_i_1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized6\ is
port (
ce_expnd_i_0 : out STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized6\ : entity is "pselect_f";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized6\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized6\ is
begin
CS: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(1),
I1 => \bus2ip_addr_i_reg[4]\(0),
I2 => \bus2ip_addr_i_reg[4]\(2),
I3 => Q,
O => ce_expnd_i_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is
port (
\LOAD_REG_GEN[31].LOAD_REG_I\ : out STD_LOGIC;
\TCSR0_GENERATE[23].TCSR0_FF_I\ : out STD_LOGIC;
\s_axi_rdata_i_reg[12]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[13]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[14]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[15]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[16]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[17]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[18]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[19]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[20]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[21]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[22]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[23]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[24]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[25]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[26]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[27]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[28]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[29]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[30]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[31]\ : out STD_LOGIC;
pair0_Select : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
\s_axi_rdata_i_reg[11]\ : out STD_LOGIC;
\TCSR0_GENERATE[24].TCSR0_FF_I\ : out STD_LOGIC;
\TCSR1_GENERATE[24].TCSR1_FF_I\ : out STD_LOGIC;
\LOAD_REG_GEN[31].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[30].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[29].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[28].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[27].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[26].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[25].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[23].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[22].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[21].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[19].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[18].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[17].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[16].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[15].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[14].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[13].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[12].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[11].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[10].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[9].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[8].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[7].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[6].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[5].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[4].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[3].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[2].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[1].LOAD_REG_I\ : out STD_LOGIC;
D_0 : out STD_LOGIC;
\bus2ip_wrce__0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_wrce : out STD_LOGIC_VECTOR ( 1 downto 0 );
\LOAD_REG_GEN[31].LOAD_REG_I_1\ : out STD_LOGIC;
\LOAD_REG_GEN[30].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[29].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[28].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[27].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[26].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[25].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[23].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[22].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[21].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[19].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[18].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[17].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[16].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[15].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[14].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[13].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[12].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[11].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[10].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[9].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[8].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[7].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[6].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[5].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[4].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[3].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[2].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[1].LOAD_REG_I_0\ : out STD_LOGIC;
D_1 : out STD_LOGIC;
s_axi_rvalid_i_reg : out STD_LOGIC;
s_axi_rvalid_i_reg_0 : out STD_LOGIC;
s_axi_rvalid_i_reg_1 : out STD_LOGIC;
s_axi_rvalid_i_reg_2 : out STD_LOGIC;
s_axi_bvalid_i_reg : out STD_LOGIC;
\TCSR0_GENERATE[23].TCSR0_FF_I_0\ : out STD_LOGIC;
\TCSR1_GENERATE[23].TCSR1_FF_I\ : out STD_LOGIC;
\s_axi_rdata_i_reg[10]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[0]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[0]_0\ : out STD_LOGIC;
READ_DONE0_I : out STD_LOGIC;
READ_DONE1_I : out STD_LOGIC;
Q : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
read_Mux_In : in STD_LOGIC_VECTOR ( 87 downto 0 );
s_axi_aresetn : in STD_LOGIC;
\state1__2\ : in STD_LOGIC;
s_axi_arvalid_0 : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arvalid : in STD_LOGIC;
is_write_reg : in STD_LOGIC;
is_read : in STD_LOGIC;
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_rready : in STD_LOGIC;
s_axi_rvalid_i_reg_3 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_bvalid_i_reg_0 : in STD_LOGIC;
bus2ip_rnw_i : in STD_LOGIC;
D_2 : in STD_LOGIC;
read_done1 : in STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is
signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg\ : STD_LOGIC;
signal \^load_reg_gen[31].load_reg_i\ : STD_LOGIC;
signal \^tcsr0_generate[23].tcsr0_ff_i\ : STD_LOGIC;
signal ce_expnd_i_0 : STD_LOGIC;
signal ce_expnd_i_1 : STD_LOGIC;
signal ce_expnd_i_2 : STD_LOGIC;
signal ce_expnd_i_3 : STD_LOGIC;
signal ce_expnd_i_5 : STD_LOGIC;
signal ce_expnd_i_6 : STD_LOGIC;
signal ce_expnd_i_7 : STD_LOGIC;
signal cs_ce_clr : STD_LOGIC;
signal \eqOp__4\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal s_axi_arready_INST_0_i_4_n_0 : STD_LOGIC;
signal \^s_axi_rvalid_i_reg\ : STD_LOGIC;
signal \^s_axi_rvalid_i_reg_0\ : STD_LOGIC;
signal \^s_axi_rvalid_i_reg_1\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal s_axi_wready_INST_0_i_1_n_0 : STD_LOGIC;
signal s_axi_wready_INST_0_i_2_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of Bus_RNW_reg_i_1 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_2\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_3\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[0].LOAD_REG_I_i_2__0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[0].LOAD_REG_I_i_7\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[1].LOAD_REG_I_i_1__0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[2].LOAD_REG_I_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[2].LOAD_REG_I_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[3].LOAD_REG_I_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[3].LOAD_REG_I_i_1__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[4].LOAD_REG_I_i_1__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[9].LOAD_REG_I_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of READ_DONE0_I_i_2 : label is "soft_lutpair7";
attribute SOFT_HLUTNM of READ_DONE1_I_i_2 : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \TCSR0_GENERATE[20].TCSR0_FF_I_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \TCSR0_GENERATE[21].TCSR0_FF_I_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \TCSR0_GENERATE[23].TCSR0_FF_I_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \TCSR0_GENERATE[24].TCSR0_FF_I_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \TCSR1_GENERATE[22].TCSR1_FF_I_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \TCSR1_GENERATE[23].TCSR1_FF_I_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \TCSR1_GENERATE[24].TCSR1_FF_I_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of s_axi_arready_INST_0_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of s_axi_arready_INST_0_i_2 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of s_axi_arready_INST_0_i_3 : label is "soft_lutpair8";
attribute SOFT_HLUTNM of s_axi_arready_INST_0_i_4 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of s_axi_wready_INST_0_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of s_axi_wready_INST_0_i_2 : label is "soft_lutpair2";
begin
\LOAD_REG_GEN[31].LOAD_REG_I\ <= \^load_reg_gen[31].load_reg_i\;
\TCSR0_GENERATE[23].TCSR0_FF_I\ <= \^tcsr0_generate[23].tcsr0_ff_i\;
s_axi_arready <= \^s_axi_arready\;
s_axi_rvalid_i_reg <= \^s_axi_rvalid_i_reg\;
s_axi_rvalid_i_reg_0 <= \^s_axi_rvalid_i_reg_0\;
s_axi_rvalid_i_reg_1 <= \^s_axi_rvalid_i_reg_1\;
s_axi_wready <= \^s_axi_wready\;
Bus_RNW_reg_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => bus2ip_rnw_i,
I1 => Q,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => Bus_RNW_reg_i_1_n_0
);
Bus_RNW_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_i_1_n_0,
Q => \^tcsr0_generate[23].tcsr0_ff_i\,
R => '0'
);
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(84),
O => \s_axi_rdata_i_reg[31]\
);
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \s_axi_rdata_i_reg[0]_0\
);
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \s_axi_rdata_i_reg[0]\
);
\GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(74),
O => \s_axi_rdata_i_reg[21]\
);
\GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(73),
O => \s_axi_rdata_i_reg[20]\
);
\GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(72),
O => \s_axi_rdata_i_reg[19]\
);
\GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(71),
O => \s_axi_rdata_i_reg[18]\
);
\GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(70),
O => \s_axi_rdata_i_reg[17]\
);
\GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(69),
O => \s_axi_rdata_i_reg[16]\
);
\GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(68),
O => \s_axi_rdata_i_reg[15]\
);
\GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(67),
O => \s_axi_rdata_i_reg[14]\
);
\GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(66),
O => \s_axi_rdata_i_reg[13]\
);
\GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(65),
O => \s_axi_rdata_i_reg[12]\
);
\GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(83),
O => \s_axi_rdata_i_reg[30]\
);
\GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0777FFFF"
)
port map (
I0 => read_Mux_In(64),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(87),
I3 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I4 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \s_axi_rdata_i_reg[11]\
);
\GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \s_axi_rdata_i_reg[10]\
);
\GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(82),
O => \s_axi_rdata_i_reg[29]\
);
\GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(81),
O => \s_axi_rdata_i_reg[28]\
);
\GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(80),
O => \s_axi_rdata_i_reg[27]\
);
\GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(79),
O => \s_axi_rdata_i_reg[26]\
);
\GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(78),
O => \s_axi_rdata_i_reg[25]\
);
\GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(77),
O => \s_axi_rdata_i_reg[24]\
);
\GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(76),
O => \s_axi_rdata_i_reg[23]\
);
\GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(75),
O => \s_axi_rdata_i_reg[22]\
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_7,
Q => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(2),
I1 => \bus2ip_addr_i_reg[4]\(1),
I2 => Q,
I3 => \bus2ip_addr_i_reg[4]\(0),
O => ce_expnd_i_6
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_6,
Q => \^load_reg_gen[31].load_reg_i\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_5,
Q => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_3,
Q => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_2,
Q => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_1,
Q => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => \^s_axi_wready\,
I1 => \^s_axi_arready\,
I2 => s_axi_aresetn,
O => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_0,
Q => \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg\,
R => cs_ce_clr
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(31),
I1 => read_Mux_In(31),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => D_0
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(31),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(63),
O => D_1
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \bus2ip_wrce__0\(0)
);
\LOAD_REG_GEN[10].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(21),
I1 => read_Mux_In(21),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[10].LOAD_REG_I\
);
\LOAD_REG_GEN[10].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(21),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(53),
O => \LOAD_REG_GEN[10].LOAD_REG_I_0\
);
\LOAD_REG_GEN[11].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(20),
I1 => read_Mux_In(20),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[11].LOAD_REG_I\
);
\LOAD_REG_GEN[11].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(20),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(52),
O => \LOAD_REG_GEN[11].LOAD_REG_I_0\
);
\LOAD_REG_GEN[12].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(19),
I1 => read_Mux_In(19),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[12].LOAD_REG_I\
);
\LOAD_REG_GEN[12].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(19),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(51),
O => \LOAD_REG_GEN[12].LOAD_REG_I_0\
);
\LOAD_REG_GEN[13].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(18),
I1 => read_Mux_In(18),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[13].LOAD_REG_I\
);
\LOAD_REG_GEN[13].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(18),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(50),
O => \LOAD_REG_GEN[13].LOAD_REG_I_0\
);
\LOAD_REG_GEN[14].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(17),
I1 => read_Mux_In(17),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[14].LOAD_REG_I\
);
\LOAD_REG_GEN[14].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(17),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(49),
O => \LOAD_REG_GEN[14].LOAD_REG_I_0\
);
\LOAD_REG_GEN[15].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(16),
I1 => read_Mux_In(16),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[15].LOAD_REG_I\
);
\LOAD_REG_GEN[15].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(16),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(48),
O => \LOAD_REG_GEN[15].LOAD_REG_I_0\
);
\LOAD_REG_GEN[16].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(15),
I1 => read_Mux_In(15),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[16].LOAD_REG_I\
);
\LOAD_REG_GEN[16].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(15),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(47),
O => \LOAD_REG_GEN[16].LOAD_REG_I_0\
);
\LOAD_REG_GEN[17].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(14),
I1 => read_Mux_In(14),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[17].LOAD_REG_I\
);
\LOAD_REG_GEN[17].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(14),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(46),
O => \LOAD_REG_GEN[17].LOAD_REG_I_0\
);
\LOAD_REG_GEN[18].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(13),
I1 => read_Mux_In(13),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[18].LOAD_REG_I\
);
\LOAD_REG_GEN[18].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(13),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(45),
O => \LOAD_REG_GEN[18].LOAD_REG_I_0\
);
\LOAD_REG_GEN[19].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(12),
I1 => read_Mux_In(12),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[19].LOAD_REG_I\
);
\LOAD_REG_GEN[19].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(12),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(44),
O => \LOAD_REG_GEN[19].LOAD_REG_I_0\
);
\LOAD_REG_GEN[1].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(30),
I1 => read_Mux_In(30),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[1].LOAD_REG_I\
);
\LOAD_REG_GEN[1].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(30),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(62),
O => \LOAD_REG_GEN[1].LOAD_REG_I_0\
);
\LOAD_REG_GEN[20].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(11),
I1 => read_Mux_In(11),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[20].LOAD_REG_I\
);
\LOAD_REG_GEN[20].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(11),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(43),
O => \LOAD_REG_GEN[20].LOAD_REG_I_0\
);
\LOAD_REG_GEN[21].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(10),
I1 => read_Mux_In(10),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[21].LOAD_REG_I\
);
\LOAD_REG_GEN[21].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(10),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(42),
O => \LOAD_REG_GEN[21].LOAD_REG_I_0\
);
\LOAD_REG_GEN[22].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(9),
I1 => read_Mux_In(9),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[22].LOAD_REG_I\
);
\LOAD_REG_GEN[22].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(9),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(41),
O => \LOAD_REG_GEN[22].LOAD_REG_I_0\
);
\LOAD_REG_GEN[23].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(8),
I1 => read_Mux_In(8),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[23].LOAD_REG_I\
);
\LOAD_REG_GEN[23].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(8),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(40),
O => \LOAD_REG_GEN[23].LOAD_REG_I_0\
);
\LOAD_REG_GEN[24].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(7),
I1 => read_Mux_In(7),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[24].LOAD_REG_I\
);
\LOAD_REG_GEN[24].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(7),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(39),
O => \LOAD_REG_GEN[24].LOAD_REG_I_0\
);
\LOAD_REG_GEN[25].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(6),
I1 => read_Mux_In(6),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[25].LOAD_REG_I\
);
\LOAD_REG_GEN[25].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(6),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(38),
O => \LOAD_REG_GEN[25].LOAD_REG_I_0\
);
\LOAD_REG_GEN[26].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(5),
I1 => read_Mux_In(5),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[26].LOAD_REG_I\
);
\LOAD_REG_GEN[26].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(5),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(37),
O => \LOAD_REG_GEN[26].LOAD_REG_I_0\
);
\LOAD_REG_GEN[27].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(4),
I1 => read_Mux_In(4),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[27].LOAD_REG_I\
);
\LOAD_REG_GEN[27].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(4),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(36),
O => \LOAD_REG_GEN[27].LOAD_REG_I_0\
);
\LOAD_REG_GEN[28].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(3),
I1 => read_Mux_In(3),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[28].LOAD_REG_I\
);
\LOAD_REG_GEN[28].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(3),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(35),
O => \LOAD_REG_GEN[28].LOAD_REG_I_0\
);
\LOAD_REG_GEN[29].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(2),
I1 => read_Mux_In(2),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[29].LOAD_REG_I\
);
\LOAD_REG_GEN[29].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(2),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(34),
O => \LOAD_REG_GEN[29].LOAD_REG_I_0\
);
\LOAD_REG_GEN[2].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(29),
I1 => read_Mux_In(29),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[2].LOAD_REG_I\
);
\LOAD_REG_GEN[2].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(29),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(61),
O => \LOAD_REG_GEN[2].LOAD_REG_I_0\
);
\LOAD_REG_GEN[30].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(1),
I1 => read_Mux_In(1),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[30].LOAD_REG_I\
);
\LOAD_REG_GEN[30].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(1),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(33),
O => \LOAD_REG_GEN[30].LOAD_REG_I_0\
);
\LOAD_REG_GEN[31].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(0),
I1 => read_Mux_In(0),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[31].LOAD_REG_I_0\
);
\LOAD_REG_GEN[31].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(0),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(32),
O => \LOAD_REG_GEN[31].LOAD_REG_I_1\
);
\LOAD_REG_GEN[3].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(28),
I1 => read_Mux_In(28),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[3].LOAD_REG_I\
);
\LOAD_REG_GEN[3].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(28),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(60),
O => \LOAD_REG_GEN[3].LOAD_REG_I_0\
);
\LOAD_REG_GEN[4].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(27),
I1 => read_Mux_In(27),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[4].LOAD_REG_I\
);
\LOAD_REG_GEN[4].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(27),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(59),
O => \LOAD_REG_GEN[4].LOAD_REG_I_0\
);
\LOAD_REG_GEN[5].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(26),
I1 => read_Mux_In(26),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[5].LOAD_REG_I\
);
\LOAD_REG_GEN[5].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(26),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(58),
O => \LOAD_REG_GEN[5].LOAD_REG_I_0\
);
\LOAD_REG_GEN[6].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(25),
I1 => read_Mux_In(25),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[6].LOAD_REG_I\
);
\LOAD_REG_GEN[6].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(25),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(57),
O => \LOAD_REG_GEN[6].LOAD_REG_I_0\
);
\LOAD_REG_GEN[7].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(24),
I1 => read_Mux_In(24),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[7].LOAD_REG_I\
);
\LOAD_REG_GEN[7].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(24),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(56),
O => \LOAD_REG_GEN[7].LOAD_REG_I_0\
);
\LOAD_REG_GEN[8].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(23),
I1 => read_Mux_In(23),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[8].LOAD_REG_I\
);
\LOAD_REG_GEN[8].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(23),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(55),
O => \LOAD_REG_GEN[8].LOAD_REG_I_0\
);
\LOAD_REG_GEN[9].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(22),
I1 => read_Mux_In(22),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[9].LOAD_REG_I\
);
\LOAD_REG_GEN[9].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(22),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(54),
O => \LOAD_REG_GEN[9].LOAD_REG_I_0\
);
\MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f
port map (
Q => Q,
\bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0),
ce_expnd_i_7 => ce_expnd_i_7
);
\MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized1\
port map (
Q => Q,
\bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0),
ce_expnd_i_5 => ce_expnd_i_5
);
\MEM_DECODE_GEN[0].PER_CE_GEN[4].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized3\
port map (
Q => Q,
\bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0),
ce_expnd_i_3 => ce_expnd_i_3
);
\MEM_DECODE_GEN[0].PER_CE_GEN[5].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized4\
port map (
Q => Q,
\bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0),
ce_expnd_i_2 => ce_expnd_i_2
);
\MEM_DECODE_GEN[0].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized5\
port map (
Q => Q,
\bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0),
ce_expnd_i_1 => ce_expnd_i_1
);
\MEM_DECODE_GEN[0].PER_CE_GEN[7].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_pselect_f__parameterized6\
port map (
Q => Q,
\bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0),
ce_expnd_i_0 => ce_expnd_i_0
);
READ_DONE0_I_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^load_reg_gen[31].load_reg_i\,
I1 => D_2,
O => READ_DONE0_I
);
READ_DONE1_I_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I1 => read_done1,
O => READ_DONE1_I
);
\TCSR0_GENERATE[20].TCSR0_FF_I_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => bus2ip_wrce(1)
);
\TCSR0_GENERATE[21].TCSR0_FF_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"32"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
I2 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
O => pair0_Select
);
\TCSR0_GENERATE[23].TCSR0_FF_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
I2 => s_axi_wdata(8),
I3 => s_axi_aresetn,
O => \TCSR0_GENERATE[23].TCSR0_FF_I_0\
);
\TCSR0_GENERATE[24].TCSR0_FF_I_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EFEEEAEE"
)
port map (
I0 => s_axi_wdata(10),
I1 => read_Mux_In(86),
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I4 => s_axi_wdata(7),
O => \TCSR0_GENERATE[24].TCSR0_FF_I\
);
\TCSR1_GENERATE[22].TCSR1_FF_I_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => bus2ip_wrce(0)
);
\TCSR1_GENERATE[23].TCSR1_FF_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
I2 => s_axi_wdata(8),
I3 => s_axi_aresetn,
O => \TCSR1_GENERATE[23].TCSR1_FF_I\
);
\TCSR1_GENERATE[24].TCSR1_FF_I_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EFEEEAEE"
)
port map (
I0 => s_axi_wdata(10),
I1 => read_Mux_In(85),
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
I4 => s_axi_wdata(7),
O => \TCSR1_GENERATE[24].TCSR1_FF_I\
);
s_axi_arready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFEFFFEFFFEFF"
)
port map (
I0 => \^s_axi_rvalid_i_reg\,
I1 => \^s_axi_rvalid_i_reg_0\,
I2 => \^s_axi_rvalid_i_reg_1\,
I3 => s_axi_arready_INST_0_i_4_n_0,
I4 => is_read,
I5 => \eqOp__4\,
O => \^s_axi_arready\
);
s_axi_arready_INST_0_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^load_reg_gen[31].load_reg_i\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \^s_axi_rvalid_i_reg\
);
s_axi_arready_INST_0_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \^s_axi_rvalid_i_reg_0\
);
s_axi_arready_INST_0_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \^s_axi_rvalid_i_reg_1\
);
s_axi_arready_INST_0_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"00FF01FF"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\,
I2 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
I4 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
O => s_axi_arready_INST_0_i_4_n_0
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_wready\,
I1 => \state_reg[1]\(1),
I2 => \state_reg[1]\(0),
I3 => s_axi_bready,
I4 => s_axi_bvalid_i_reg_0,
O => s_axi_bvalid_i_reg
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_arready\,
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => s_axi_rready,
I4 => s_axi_rvalid_i_reg_3,
O => s_axi_rvalid_i_reg_2
);
s_axi_wready_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"F777"
)
port map (
I0 => s_axi_wready_INST_0_i_1_n_0,
I1 => s_axi_wready_INST_0_i_2_n_0,
I2 => is_write_reg,
I3 => \eqOp__4\,
O => \^s_axi_wready\
);
s_axi_wready_INST_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F0F1"
)
port map (
I0 => \^load_reg_gen[31].load_reg_i\,
I1 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
O => s_axi_wready_INST_0_i_1_n_0
);
s_axi_wready_INST_0_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FF00FF01"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\,
I2 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
I4 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
O => s_axi_wready_INST_0_i_2_n_0
);
s_axi_wready_INST_0_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(4),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(2),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(3),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(5),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(0),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(1),
O => \eqOp__4\
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"77FC44FC"
)
port map (
I0 => \state1__2\,
I1 => \state_reg[1]\(0),
I2 => s_axi_arvalid,
I3 => \state_reg[1]\(1),
I4 => \^s_axi_wready\,
O => D(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"5FFC50FC"
)
port map (
I0 => \state1__2\,
I1 => s_axi_arvalid_0,
I2 => \state_reg[1]\(1),
I3 => \state_reg[1]\(0),
I4 => \^s_axi_arready\,
O => D(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_count_module is
port (
\INFERRED_GEN.icount_out_reg[31]\ : out STD_LOGIC_VECTOR ( 52 downto 0 );
read_Mux_In : out STD_LOGIC_VECTOR ( 10 downto 0 );
generateOutPre0_reg : out STD_LOGIC;
counter_TC : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aresetn_0 : in STD_LOGIC;
\TCSR0_GENERATE[27].TCSR0_FF_I\ : in STD_LOGIC;
D_1 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\ : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 0 to 0 );
load_Counter_Reg : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aresetn : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_count_module;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_count_module is
signal \^inferred_gen.icount_out_reg[31]\ : STD_LOGIC_VECTOR ( 52 downto 0 );
signal \^read_mux_in\ : STD_LOGIC_VECTOR ( 10 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \LOAD_REG_GEN[0].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[10].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[11].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[12].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[13].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[14].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[15].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[16].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[17].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[18].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[19].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[1].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[20].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[21].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[22].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[23].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[24].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[25].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[26].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[27].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[28].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[29].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[2].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[30].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[31].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[3].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[4].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[5].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[6].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[7].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[8].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[9].LOAD_REG_I\ : label is "PRIMITIVE";
begin
\INFERRED_GEN.icount_out_reg[31]\(52 downto 0) <= \^inferred_gen.icount_out_reg[31]\(52 downto 0);
read_Mux_In(10 downto 0) <= \^read_mux_in\(10 downto 0);
COUNTER_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_counter_f_3
port map (
E(0) => E(0),
\LOAD_REG_GEN[0].LOAD_REG_I\(31 downto 0) => \^inferred_gen.icount_out_reg[31]\(31 downto 0),
\LOAD_REG_GEN[0].LOAD_REG_I_0\(20 downto 0) => \^inferred_gen.icount_out_reg[31]\(52 downto 32),
Q(0) => Q(0),
S(0) => S(0),
counter_TC(0) => counter_TC(0),
generateOutPre0_reg => generateOutPre0_reg,
load_Counter_Reg(0) => load_Counter_Reg(0),
read_Mux_In(10 downto 0) => \^read_mux_in\(10 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_aresetn_0 => s_axi_aresetn_0
);
\LOAD_REG_GEN[0].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => D_1,
Q => \^inferred_gen.icount_out_reg[31]\(52),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[10].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\,
Q => \^inferred_gen.icount_out_reg[31]\(42),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[11].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\,
Q => \^inferred_gen.icount_out_reg[31]\(41),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[12].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\,
Q => \^inferred_gen.icount_out_reg[31]\(40),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[13].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\,
Q => \^inferred_gen.icount_out_reg[31]\(39),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[14].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\,
Q => \^inferred_gen.icount_out_reg[31]\(38),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[15].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\,
Q => \^inferred_gen.icount_out_reg[31]\(37),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[16].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\,
Q => \^inferred_gen.icount_out_reg[31]\(36),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[17].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\,
Q => \^inferred_gen.icount_out_reg[31]\(35),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[18].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\,
Q => \^inferred_gen.icount_out_reg[31]\(34),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[19].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\,
Q => \^inferred_gen.icount_out_reg[31]\(33),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[1].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
Q => \^inferred_gen.icount_out_reg[31]\(51),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[20].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\,
Q => \^inferred_gen.icount_out_reg[31]\(32),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[21].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\,
Q => \^read_mux_in\(10),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[22].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\,
Q => \^read_mux_in\(9),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[23].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\,
Q => \^read_mux_in\(8),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[24].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\,
Q => \^read_mux_in\(7),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[25].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\,
Q => \^read_mux_in\(6),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[26].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\,
Q => \^read_mux_in\(5),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[27].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\,
Q => \^read_mux_in\(4),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[28].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\,
Q => \^read_mux_in\(3),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[29].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\,
Q => \^read_mux_in\(2),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[2].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
Q => \^inferred_gen.icount_out_reg[31]\(50),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[30].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\,
Q => \^read_mux_in\(1),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[31].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\,
Q => \^read_mux_in\(0),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[3].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\,
Q => \^inferred_gen.icount_out_reg[31]\(49),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[4].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\,
Q => \^inferred_gen.icount_out_reg[31]\(48),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[5].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\,
Q => \^inferred_gen.icount_out_reg[31]\(47),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[6].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\,
Q => \^inferred_gen.icount_out_reg[31]\(46),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[7].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\,
Q => \^inferred_gen.icount_out_reg[31]\(45),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[8].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\,
Q => \^inferred_gen.icount_out_reg[31]\(44),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[9].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\,
Q => \^inferred_gen.icount_out_reg[31]\(43),
R => s_axi_aresetn_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_count_module_0 is
port (
\INFERRED_GEN.icount_out_reg[31]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 31 downto 0 );
\s_axi_rdata_i_reg[0]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[1]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[2]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[3]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[4]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[5]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[6]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[7]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[8]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[9]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[10]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[11]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[12]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[13]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[14]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[15]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[16]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[17]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[18]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[19]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[20]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[21]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[22]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[23]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[24]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[25]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[26]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[27]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[28]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[29]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[30]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[31]\ : out STD_LOGIC;
generateOutPre1_reg : out STD_LOGIC;
counter_TC : out STD_LOGIC_VECTOR ( 0 to 0 );
\TCSR0_GENERATE[20].TCSR0_FF_I\ : in STD_LOGIC;
D_2 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[30]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[29]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[28]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[27]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[26]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[25]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[24]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[23]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[22]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[21]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[20]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[19]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[18]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[17]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[16]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[15]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[14]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[13]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[12]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[11]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[10]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[9]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[8]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[7]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[6]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[5]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[4]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[3]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[2]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[1]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[0]\ : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 0 to 0 );
load_Counter_Reg : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aresetn : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[31]_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
\counter_TC_Reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_count_module_0 : entity is "count_module";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_count_module_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_count_module_0 is
signal \^inferred_gen.icount_out_reg[31]\ : STD_LOGIC;
signal read_Mux_In : STD_LOGIC_VECTOR ( 96 to 127 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \LOAD_REG_GEN[0].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[10].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[11].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[12].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[13].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[14].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[15].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[16].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[17].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[18].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[19].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[1].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[20].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[21].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[22].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[23].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[24].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[25].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[26].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[27].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[28].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[29].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[2].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[30].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[31].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[3].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[4].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[5].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[6].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[7].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[8].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[9].LOAD_REG_I\ : label is "PRIMITIVE";
begin
\INFERRED_GEN.icount_out_reg[31]\ <= \^inferred_gen.icount_out_reg[31]\;
COUNTER_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_counter_f
port map (
E(0) => E(0),
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
\INFERRED_GEN.icount_out_reg[31]_0\(31 downto 0) => \INFERRED_GEN.icount_out_reg[31]_0\(31 downto 0),
Q(31 downto 0) => Q(31 downto 0),
S(0) => S(0),
SR(0) => \^inferred_gen.icount_out_reg[31]\,
counter_TC(0) => counter_TC(0),
\counter_TC_Reg_reg[1]\(0) => \counter_TC_Reg_reg[1]\(0),
generateOutPre1_reg => generateOutPre1_reg,
load_Counter_Reg(0) => load_Counter_Reg(0),
read_Mux_In(31) => read_Mux_In(96),
read_Mux_In(30) => read_Mux_In(97),
read_Mux_In(29) => read_Mux_In(98),
read_Mux_In(28) => read_Mux_In(99),
read_Mux_In(27) => read_Mux_In(100),
read_Mux_In(26) => read_Mux_In(101),
read_Mux_In(25) => read_Mux_In(102),
read_Mux_In(24) => read_Mux_In(103),
read_Mux_In(23) => read_Mux_In(104),
read_Mux_In(22) => read_Mux_In(105),
read_Mux_In(21) => read_Mux_In(106),
read_Mux_In(20) => read_Mux_In(107),
read_Mux_In(19) => read_Mux_In(108),
read_Mux_In(18) => read_Mux_In(109),
read_Mux_In(17) => read_Mux_In(110),
read_Mux_In(16) => read_Mux_In(111),
read_Mux_In(15) => read_Mux_In(112),
read_Mux_In(14) => read_Mux_In(113),
read_Mux_In(13) => read_Mux_In(114),
read_Mux_In(12) => read_Mux_In(115),
read_Mux_In(11) => read_Mux_In(116),
read_Mux_In(10) => read_Mux_In(117),
read_Mux_In(9) => read_Mux_In(118),
read_Mux_In(8) => read_Mux_In(119),
read_Mux_In(7) => read_Mux_In(120),
read_Mux_In(6) => read_Mux_In(121),
read_Mux_In(5) => read_Mux_In(122),
read_Mux_In(4) => read_Mux_In(123),
read_Mux_In(3) => read_Mux_In(124),
read_Mux_In(2) => read_Mux_In(125),
read_Mux_In(1) => read_Mux_In(126),
read_Mux_In(0) => read_Mux_In(127),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
\s_axi_rdata_i_reg[0]\ => \s_axi_rdata_i_reg[0]\,
\s_axi_rdata_i_reg[10]\ => \s_axi_rdata_i_reg[10]\,
\s_axi_rdata_i_reg[11]\ => \s_axi_rdata_i_reg[11]\,
\s_axi_rdata_i_reg[12]\ => \s_axi_rdata_i_reg[12]\,
\s_axi_rdata_i_reg[13]\ => \s_axi_rdata_i_reg[13]\,
\s_axi_rdata_i_reg[14]\ => \s_axi_rdata_i_reg[14]\,
\s_axi_rdata_i_reg[15]\ => \s_axi_rdata_i_reg[15]\,
\s_axi_rdata_i_reg[16]\ => \s_axi_rdata_i_reg[16]\,
\s_axi_rdata_i_reg[17]\ => \s_axi_rdata_i_reg[17]\,
\s_axi_rdata_i_reg[18]\ => \s_axi_rdata_i_reg[18]\,
\s_axi_rdata_i_reg[19]\ => \s_axi_rdata_i_reg[19]\,
\s_axi_rdata_i_reg[1]\ => \s_axi_rdata_i_reg[1]\,
\s_axi_rdata_i_reg[20]\ => \s_axi_rdata_i_reg[20]\,
\s_axi_rdata_i_reg[21]\ => \s_axi_rdata_i_reg[21]\,
\s_axi_rdata_i_reg[22]\ => \s_axi_rdata_i_reg[22]\,
\s_axi_rdata_i_reg[23]\ => \s_axi_rdata_i_reg[23]\,
\s_axi_rdata_i_reg[24]\ => \s_axi_rdata_i_reg[24]\,
\s_axi_rdata_i_reg[25]\ => \s_axi_rdata_i_reg[25]\,
\s_axi_rdata_i_reg[26]\ => \s_axi_rdata_i_reg[26]\,
\s_axi_rdata_i_reg[27]\ => \s_axi_rdata_i_reg[27]\,
\s_axi_rdata_i_reg[28]\ => \s_axi_rdata_i_reg[28]\,
\s_axi_rdata_i_reg[29]\ => \s_axi_rdata_i_reg[29]\,
\s_axi_rdata_i_reg[2]\ => \s_axi_rdata_i_reg[2]\,
\s_axi_rdata_i_reg[30]\ => \s_axi_rdata_i_reg[30]\,
\s_axi_rdata_i_reg[31]\ => \s_axi_rdata_i_reg[31]\,
\s_axi_rdata_i_reg[3]\ => \s_axi_rdata_i_reg[3]\,
\s_axi_rdata_i_reg[4]\ => \s_axi_rdata_i_reg[4]\,
\s_axi_rdata_i_reg[5]\ => \s_axi_rdata_i_reg[5]\,
\s_axi_rdata_i_reg[6]\ => \s_axi_rdata_i_reg[6]\,
\s_axi_rdata_i_reg[7]\ => \s_axi_rdata_i_reg[7]\,
\s_axi_rdata_i_reg[8]\ => \s_axi_rdata_i_reg[8]\,
\s_axi_rdata_i_reg[9]\ => \s_axi_rdata_i_reg[9]\
);
\LOAD_REG_GEN[0].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => D_2,
Q => read_Mux_In(96),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[10].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[21]\,
Q => read_Mux_In(106),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[11].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[20]\,
Q => read_Mux_In(107),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[12].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[19]\,
Q => read_Mux_In(108),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[13].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[18]\,
Q => read_Mux_In(109),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[14].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[17]\,
Q => read_Mux_In(110),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[15].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[16]\,
Q => read_Mux_In(111),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[16].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[15]\,
Q => read_Mux_In(112),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[17].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[14]\,
Q => read_Mux_In(113),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[18].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[13]\,
Q => read_Mux_In(114),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[19].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[12]\,
Q => read_Mux_In(115),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[1].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[30]\,
Q => read_Mux_In(97),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[20].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[11]\,
Q => read_Mux_In(116),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[21].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[10]\,
Q => read_Mux_In(117),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[22].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[9]\,
Q => read_Mux_In(118),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[23].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[8]\,
Q => read_Mux_In(119),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[24].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[7]\,
Q => read_Mux_In(120),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[25].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[6]\,
Q => read_Mux_In(121),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[26].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[5]\,
Q => read_Mux_In(122),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[27].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[4]\,
Q => read_Mux_In(123),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[28].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[3]\,
Q => read_Mux_In(124),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[29].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[2]\,
Q => read_Mux_In(125),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[2].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[29]\,
Q => read_Mux_In(98),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[30].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[1]\,
Q => read_Mux_In(126),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[31].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[0]\,
Q => read_Mux_In(127),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[3].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[28]\,
Q => read_Mux_In(99),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[4].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[27]\,
Q => read_Mux_In(100),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[5].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[26]\,
Q => read_Mux_In(101),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[6].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[25]\,
Q => read_Mux_In(102),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[7].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[24]\,
Q => read_Mux_In(103),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[8].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[23]\,
Q => read_Mux_In(104),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[9].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[22]\,
Q => read_Mux_In(105),
R => \^inferred_gen.icount_out_reg[31]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_timer_control is
port (
generateout0 : out STD_LOGIC;
generateout1 : out STD_LOGIC;
interrupt : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\INFERRED_GEN.icount_out_reg[0]\ : out STD_LOGIC;
\TCSR0_GENERATE[24].TCSR0_FF_I_0\ : out STD_LOGIC;
\TCSR1_GENERATE[23].TCSR1_FF_I_0\ : out STD_LOGIC;
D_0 : out STD_LOGIC;
read_done1 : out STD_LOGIC;
load_Counter_Reg : out STD_LOGIC_VECTOR ( 0 to 1 );
\s_axi_rdata_i_reg[0]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[1]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[2]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[3]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[4]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[5]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[6]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[7]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[8]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[9]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[10]\ : out STD_LOGIC;
R : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\INFERRED_GEN.icount_out_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
PWM_FF_I : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 0 to 0 );
\LOAD_REG_GEN[24].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I_0\ : out STD_LOGIC;
\INFERRED_GEN.icount_out_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\INFERRED_GEN.icount_out_reg[32]\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[32]_0\ : in STD_LOGIC;
bus2ip_wrce : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 9 downto 0 );
\LOAD_REG_GEN[21].LOAD_REG_I\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
pair0_Select : in STD_LOGIC;
\TCSR0_GENERATE[24].TCSR0_FF_I_1\ : in STD_LOGIC;
\TCSR1_GENERATE[24].TCSR1_FF_I_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : in STD_LOGIC;
counter_TC : in STD_LOGIC_VECTOR ( 0 to 1 );
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ : in STD_LOGIC;
pwm0 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
Bus_RNW_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC;
\bus2ip_wrce__0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
freeze : in STD_LOGIC;
capturetrig0 : in STD_LOGIC;
capturetrig1 : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_timer_control;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_timer_control is
signal \^d_0\ : STD_LOGIC;
signal GenerateOut00 : STD_LOGIC;
signal GenerateOut10 : STD_LOGIC;
signal \^inferred_gen.icount_out_reg[0]\ : STD_LOGIC;
signal Interrupt0 : STD_LOGIC;
signal \LOAD_REG_GEN[0].LOAD_REG_I_i_3_n_0\ : STD_LOGIC;
signal \LOAD_REG_GEN[0].LOAD_REG_I_i_5_n_0\ : STD_LOGIC;
signal Load_Counter_Reg028_out : STD_LOGIC;
signal Load_Counter_Reg030_out : STD_LOGIC;
signal Load_Counter_Reg031_out : STD_LOGIC;
signal \Load_Counter_Reg0__0\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal READ_DONE0_I_i_3_n_0 : STD_LOGIC;
signal READ_DONE1_I_i_1_n_0 : STD_LOGIC;
signal READ_DONE1_I_i_3_n_0 : STD_LOGIC;
signal R_0 : STD_LOGIC;
signal \TCSR0_GENERATE[23].TCSR0_FF_I_i_2_n_0\ : STD_LOGIC;
signal \^tcsr0_generate[24].tcsr0_ff_i_0\ : STD_LOGIC;
signal \TCSR0_Set2__0\ : STD_LOGIC;
signal \^tcsr1_generate[23].tcsr1_ff_i_0\ : STD_LOGIC;
signal \TCSR1_GENERATE[23].TCSR1_FF_I_i_2_n_0\ : STD_LOGIC;
signal captureTrig0_d : STD_LOGIC;
signal captureTrig0_d0 : STD_LOGIC;
signal captureTrig0_d2 : STD_LOGIC;
signal captureTrig0_pulse_d1 : STD_LOGIC;
signal captureTrig0_pulse_d1_i_1_n_0 : STD_LOGIC;
signal captureTrig0_pulse_d2 : STD_LOGIC;
signal captureTrig1_d : STD_LOGIC;
signal captureTrig1_d0 : STD_LOGIC;
signal captureTrig1_d2 : STD_LOGIC;
signal counter_TC_Reg2 : STD_LOGIC;
signal generateOutPre0 : STD_LOGIC;
signal generateOutPre1 : STD_LOGIC;
signal \^generateout0\ : STD_LOGIC;
signal \^generateout1\ : STD_LOGIC;
signal p_33_in : STD_LOGIC;
signal p_38_in : STD_LOGIC;
signal read_Mux_In : STD_LOGIC_VECTOR ( 21 to 63 );
signal \^read_done1\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of GenerateOut0_i_2 : label is "soft_lutpair50";
attribute SOFT_HLUTNM of GenerateOut1_i_1 : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[31]_i_4\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[31]_i_4__0\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[0].LOAD_REG_I_i_3\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[0].LOAD_REG_I_i_5\ : label is "soft_lutpair53";
attribute BOX_TYPE : string;
attribute BOX_TYPE of READ_DONE0_I : label is "PRIMITIVE";
attribute IS_CE_INVERTED : string;
attribute IS_CE_INVERTED of READ_DONE0_I : label is "1'b0";
attribute IS_S_INVERTED : string;
attribute IS_S_INVERTED of READ_DONE0_I : label is "1'b0";
attribute BOX_TYPE of READ_DONE1_I : label is "PRIMITIVE";
attribute IS_CE_INVERTED of READ_DONE1_I : label is "1'b0";
attribute IS_S_INVERTED of READ_DONE1_I : label is "1'b0";
attribute SOFT_HLUTNM of READ_DONE1_I_i_3 : label is "soft_lutpair52";
attribute BOX_TYPE of \TCSR0_GENERATE[20].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[20].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[20].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[21].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[21].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[21].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[22].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[22].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[22].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[23].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[23].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[23].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[24].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[24].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[24].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[25].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[25].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[25].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[26].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[26].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[26].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[27].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[27].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[27].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[28].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[28].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[28].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[29].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[29].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[29].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[30].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[30].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[30].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[31].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[31].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[31].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[21].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[21].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[21].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[22].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[22].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[22].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[23].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[23].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[23].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[24].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[24].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[24].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[25].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[25].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[25].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[26].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[26].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[26].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[27].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[27].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[27].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[28].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[28].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[28].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[29].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[29].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[29].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[30].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[30].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[30].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[31].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[31].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[31].TCSR1_FF_I\ : label is "1'b0";
attribute SOFT_HLUTNM of captureTrig0_pulse_d1_i_1 : label is "soft_lutpair52";
begin
D_0 <= \^d_0\;
\INFERRED_GEN.icount_out_reg[0]\ <= \^inferred_gen.icount_out_reg[0]\;
Q(1 downto 0) <= \^q\(1 downto 0);
\TCSR0_GENERATE[24].TCSR0_FF_I_0\ <= \^tcsr0_generate[24].tcsr0_ff_i_0\;
\TCSR1_GENERATE[23].TCSR1_FF_I_0\ <= \^tcsr1_generate[23].tcsr1_ff_i_0\;
generateout0 <= \^generateout0\;
generateout1 <= \^generateout1\;
read_done1 <= \^read_done1\;
\GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(10),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(21),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(53),
O => \s_axi_rdata_i_reg[10]\
);
\GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(9),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(22),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(54),
O => \s_axi_rdata_i_reg[9]\
);
\GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(8),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(23),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(55),
O => \s_axi_rdata_i_reg[8]\
);
\GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(7),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => \^tcsr0_generate[24].tcsr0_ff_i_0\,
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => \^tcsr1_generate[23].tcsr1_ff_i_0\,
O => \s_axi_rdata_i_reg[7]\
);
\GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(6),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(25),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(57),
O => \s_axi_rdata_i_reg[6]\
);
\GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(5),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(26),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(58),
O => \s_axi_rdata_i_reg[5]\
);
\GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(4),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(27),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(59),
O => \s_axi_rdata_i_reg[4]\
);
\GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(3),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(28),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(60),
O => \s_axi_rdata_i_reg[3]\
);
\GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(2),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(29),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(61),
O => \s_axi_rdata_i_reg[2]\
);
\GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(1),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(30),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(62),
O => \s_axi_rdata_i_reg[1]\
);
\GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(0),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(31),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(63),
O => \s_axi_rdata_i_reg[0]\
);
GenerateOut0_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"B800"
)
port map (
I0 => generateOutPre1,
I1 => \^inferred_gen.icount_out_reg[0]\,
I2 => generateOutPre0,
I3 => read_Mux_In(29),
O => GenerateOut00
);
GenerateOut0_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GenerateOut00,
Q => \^generateout0\,
R => SR(0)
);
GenerateOut1_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"8F808080"
)
port map (
I0 => generateOutPre0,
I1 => read_Mux_In(29),
I2 => \^inferred_gen.icount_out_reg[0]\,
I3 => read_Mux_In(61),
I4 => generateOutPre1,
O => GenerateOut10
);
GenerateOut1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GenerateOut10,
Q => \^generateout1\,
R => SR(0)
);
\INFERRED_GEN.icount_out[31]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAFEAAAA"
)
port map (
I0 => read_Mux_In(26),
I1 => read_Mux_In(22),
I2 => read_Mux_In(27),
I3 => read_Mux_In(31),
I4 => counter_TC(0),
O => Load_Counter_Reg030_out
);
\INFERRED_GEN.icount_out[31]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAEAAAAAAAEA"
)
port map (
I0 => read_Mux_In(58),
I1 => counter_TC(1),
I2 => read_Mux_In(59),
I3 => read_Mux_In(63),
I4 => read_Mux_In(54),
I5 => counter_TC(0),
O => \Load_Counter_Reg0__0\
);
\INFERRED_GEN.icount_out[31]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FF40"
)
port map (
I0 => read_Mux_In(31),
I1 => counter_TC(1),
I2 => read_Mux_In(27),
I3 => read_Mux_In(58),
O => Load_Counter_Reg028_out
);
\INFERRED_GEN.icount_out[31]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FF40"
)
port map (
I0 => read_Mux_In(31),
I1 => counter_TC(1),
I2 => read_Mux_In(27),
I3 => read_Mux_In(26),
O => Load_Counter_Reg031_out
);
\INFERRED_GEN.icount_out[31]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF40FFFFFF400000"
)
port map (
I0 => read_Mux_In(31),
I1 => counter_TC(1),
I2 => read_Mux_In(27),
I3 => read_Mux_In(58),
I4 => \^inferred_gen.icount_out_reg[0]\,
I5 => \Load_Counter_Reg0__0\,
O => load_Counter_Reg(1)
);
\INFERRED_GEN.icount_out[31]_i_7__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF40FFFFFF400000"
)
port map (
I0 => read_Mux_In(31),
I1 => counter_TC(1),
I2 => read_Mux_In(27),
I3 => read_Mux_In(26),
I4 => \^inferred_gen.icount_out_reg[0]\,
I5 => Load_Counter_Reg030_out,
O => load_Counter_Reg(0)
);
INPUT_DOUBLE_REGS: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
port map (
captureTrig0_d0 => captureTrig0_d0,
capturetrig0 => capturetrig0,
read_Mux_In(0) => read_Mux_In(28),
s_axi_aclk => s_axi_aclk
);
INPUT_DOUBLE_REGS2: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_1
port map (
captureTrig1_d0 => captureTrig1_d0,
capturetrig1 => capturetrig1,
read_Mux_In(0) => read_Mux_In(60),
s_axi_aclk => s_axi_aclk
);
INPUT_DOUBLE_REGS3: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_2
port map (
E(0) => E(0),
\INFERRED_GEN.icount_out_reg[0]\(0) => \INFERRED_GEN.icount_out_reg[0]_0\(0),
\INFERRED_GEN.icount_out_reg[1]\(1 downto 0) => \INFERRED_GEN.icount_out_reg[1]\(1 downto 0),
\INFERRED_GEN.icount_out_reg[4]\(0) => \INFERRED_GEN.icount_out_reg[4]\(0),
Load_Counter_Reg028_out => Load_Counter_Reg028_out,
Load_Counter_Reg030_out => Load_Counter_Reg030_out,
Load_Counter_Reg031_out => Load_Counter_Reg031_out,
\Load_Counter_Reg0__0\ => \Load_Counter_Reg0__0\,
S(0) => S(0),
\TCSR0_GENERATE[20].TCSR0_FF_I\ => \^inferred_gen.icount_out_reg[0]\,
\TCSR0_GENERATE[24].TCSR0_FF_I\ => \^tcsr0_generate[24].tcsr0_ff_i_0\,
\TCSR1_GENERATE[24].TCSR1_FF_I\ => \^tcsr1_generate[23].tcsr1_ff_i_0\,
counter_TC(0 to 1) => counter_TC(0 to 1),
freeze => freeze,
generateOutPre0 => generateOutPre0,
read_Mux_In(7) => read_Mux_In(22),
read_Mux_In(6) => read_Mux_In(27),
read_Mux_In(5) => read_Mux_In(30),
read_Mux_In(4) => read_Mux_In(31),
read_Mux_In(3) => read_Mux_In(54),
read_Mux_In(2) => read_Mux_In(59),
read_Mux_In(1) => read_Mux_In(62),
read_Mux_In(0) => read_Mux_In(63),
s_axi_aclk => s_axi_aclk
);
Interrupt_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => read_Mux_In(25),
I1 => read_Mux_In(23),
I2 => read_Mux_In(57),
I3 => read_Mux_In(55),
O => Interrupt0
);
Interrupt_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Interrupt0,
Q => interrupt,
R => SR(0)
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E000FFFFE000E000"
)
port map (
I0 => read_Mux_In(27),
I1 => \^d_0\,
I2 => R_0,
I3 => read_Mux_In(31),
I4 => Bus_RNW_reg,
I5 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
O => \LOAD_REG_GEN[24].LOAD_REG_I\
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFF8080808"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_i_3_n_0\,
I1 => p_38_in,
I2 => \^inferred_gen.icount_out_reg[0]\,
I3 => \LOAD_REG_GEN[0].LOAD_REG_I_i_5_n_0\,
I4 => p_33_in,
I5 => \bus2ip_wrce__0\(0),
O => \LOAD_REG_GEN[24].LOAD_REG_I_0\
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => read_Mux_In(59),
I1 => \^read_done1\,
O => \LOAD_REG_GEN[0].LOAD_REG_I_i_3_n_0\
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4F4F40400000000"
)
port map (
I0 => captureTrig1_d2,
I1 => captureTrig1_d,
I2 => \^inferred_gen.icount_out_reg[0]\,
I3 => READ_DONE1_I_i_3_n_0,
I4 => READ_DONE0_I_i_3_n_0,
I5 => read_Mux_In(63),
O => p_38_in
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => read_Mux_In(27),
I1 => \^read_done1\,
O => \LOAD_REG_GEN[0].LOAD_REG_I_i_5_n_0\
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4F4F40400000000"
)
port map (
I0 => captureTrig1_d2,
I1 => captureTrig1_d,
I2 => \^inferred_gen.icount_out_reg[0]\,
I3 => READ_DONE1_I_i_3_n_0,
I4 => READ_DONE0_I_i_3_n_0,
I5 => read_Mux_In(31),
O => p_33_in
);
PWM_FF_I_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"AB"
)
port map (
I0 => \^generateout1\,
I1 => read_Mux_In(22),
I2 => read_Mux_In(54),
O => R
);
PWM_FF_I_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^generateout0\,
I1 => pwm0,
O => PWM_FF_I
);
READ_DONE0_I: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
Q => \^d_0\,
R => R_0
);
READ_DONE0_I_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AA00AA00ABFFAA00"
)
port map (
I0 => READ_DONE0_I_i_3_n_0,
I1 => \^q\(1),
I2 => counter_TC(0),
I3 => \^inferred_gen.icount_out_reg[0]\,
I4 => captureTrig0_d,
I5 => captureTrig0_d2,
O => R_0
);
READ_DONE0_I_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => counter_TC_Reg2,
I1 => captureTrig0_pulse_d2,
I2 => captureTrig0_pulse_d1,
O => READ_DONE0_I_i_3_n_0
);
READ_DONE1_I: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
Q => \^read_done1\,
R => READ_DONE1_I_i_1_n_0
);
READ_DONE1_I_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"E0E0EFE0"
)
port map (
I0 => READ_DONE0_I_i_3_n_0,
I1 => READ_DONE1_I_i_3_n_0,
I2 => \^inferred_gen.icount_out_reg[0]\,
I3 => captureTrig1_d,
I4 => captureTrig1_d2,
O => READ_DONE1_I_i_1_n_0
);
READ_DONE1_I_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => captureTrig0_d2,
I1 => captureTrig0_d,
I2 => counter_TC(0),
I3 => \^q\(1),
O => READ_DONE1_I_i_3_n_0
);
\TCSR0_GENERATE[20].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(9),
Q => \^inferred_gen.icount_out_reg[0]\,
R => SR(0)
);
\TCSR0_GENERATE[21].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => pair0_Select,
D => s_axi_wdata(8),
Q => read_Mux_In(21),
R => SR(0)
);
\TCSR0_GENERATE[22].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(7),
Q => read_Mux_In(22),
R => SR(0)
);
\TCSR0_GENERATE[23].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \TCSR0_GENERATE[23].TCSR0_FF_I_i_2_n_0\,
Q => read_Mux_In(23),
R => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\
);
\TCSR0_GENERATE[23].TCSR0_FF_I_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFF3F2F0F2"
)
port map (
I0 => generateOutPre0,
I1 => read_Mux_In(31),
I2 => \TCSR0_Set2__0\,
I3 => \^inferred_gen.icount_out_reg[0]\,
I4 => generateOutPre1,
I5 => read_Mux_In(23),
O => \TCSR0_GENERATE[23].TCSR0_FF_I_i_2_n_0\
);
\TCSR0_GENERATE[23].TCSR0_FF_I_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8AAA80000000000"
)
port map (
I0 => read_Mux_In(31),
I1 => READ_DONE0_I_i_3_n_0,
I2 => READ_DONE1_I_i_3_n_0,
I3 => \^inferred_gen.icount_out_reg[0]\,
I4 => captureTrig0_pulse_d1_i_1_n_0,
I5 => \^tcsr0_generate[24].tcsr0_ff_i_0\,
O => \TCSR0_Set2__0\
);
\TCSR0_GENERATE[24].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => pair0_Select,
D => \TCSR0_GENERATE[24].TCSR0_FF_I_1\,
Q => \^tcsr0_generate[24].tcsr0_ff_i_0\,
R => SR(0)
);
\TCSR0_GENERATE[25].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(6),
Q => read_Mux_In(25),
R => SR(0)
);
\TCSR0_GENERATE[26].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(5),
Q => read_Mux_In(26),
R => SR(0)
);
\TCSR0_GENERATE[27].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(4),
Q => read_Mux_In(27),
R => SR(0)
);
\TCSR0_GENERATE[28].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(3),
Q => read_Mux_In(28),
R => SR(0)
);
\TCSR0_GENERATE[29].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(2),
Q => read_Mux_In(29),
R => SR(0)
);
\TCSR0_GENERATE[30].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(1),
Q => read_Mux_In(30),
R => SR(0)
);
\TCSR0_GENERATE[31].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(0),
Q => read_Mux_In(31),
R => SR(0)
);
\TCSR1_GENERATE[21].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => pair0_Select,
D => s_axi_wdata(8),
Q => read_Mux_In(53),
R => SR(0)
);
\TCSR1_GENERATE[22].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(7),
Q => read_Mux_In(54),
R => SR(0)
);
\TCSR1_GENERATE[23].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \TCSR1_GENERATE[23].TCSR1_FF_I_i_2_n_0\,
Q => read_Mux_In(55),
R => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\
);
\TCSR1_GENERATE[23].TCSR1_FF_I_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00008F80"
)
port map (
I0 => \^tcsr1_generate[23].tcsr1_ff_i_0\,
I1 => READ_DONE1_I_i_1_n_0,
I2 => read_Mux_In(63),
I3 => generateOutPre1,
I4 => \^inferred_gen.icount_out_reg[0]\,
I5 => read_Mux_In(55),
O => \TCSR1_GENERATE[23].TCSR1_FF_I_i_2_n_0\
);
\TCSR1_GENERATE[24].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => pair0_Select,
D => \TCSR1_GENERATE[24].TCSR1_FF_I_0\,
Q => \^tcsr1_generate[23].tcsr1_ff_i_0\,
R => SR(0)
);
\TCSR1_GENERATE[25].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(6),
Q => read_Mux_In(57),
R => SR(0)
);
\TCSR1_GENERATE[26].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(5),
Q => read_Mux_In(58),
R => SR(0)
);
\TCSR1_GENERATE[27].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(4),
Q => read_Mux_In(59),
R => SR(0)
);
\TCSR1_GENERATE[28].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(3),
Q => read_Mux_In(60),
R => SR(0)
);
\TCSR1_GENERATE[29].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(2),
Q => read_Mux_In(61),
R => SR(0)
);
\TCSR1_GENERATE[30].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(1),
Q => read_Mux_In(62),
R => SR(0)
);
\TCSR1_GENERATE[31].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(0),
Q => read_Mux_In(63),
R => SR(0)
);
captureTrig0_d2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => captureTrig0_d,
Q => captureTrig0_d2,
R => SR(0)
);
captureTrig0_d_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => captureTrig0_d0,
Q => captureTrig0_d,
R => SR(0)
);
captureTrig0_pulse_d1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => captureTrig0_d,
I1 => captureTrig0_d2,
O => captureTrig0_pulse_d1_i_1_n_0
);
captureTrig0_pulse_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => captureTrig0_pulse_d1_i_1_n_0,
Q => captureTrig0_pulse_d1,
R => SR(0)
);
captureTrig0_pulse_d2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => captureTrig0_pulse_d1,
Q => captureTrig0_pulse_d2,
R => SR(0)
);
captureTrig1_d2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => captureTrig1_d,
Q => captureTrig1_d2,
R => SR(0)
);
captureTrig1_d_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => captureTrig1_d0,
Q => captureTrig1_d,
R => SR(0)
);
counter_TC_Reg2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^q\(1),
Q => counter_TC_Reg2,
R => SR(0)
);
\counter_TC_Reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => counter_TC(0),
Q => \^q\(1),
R => SR(0)
);
\counter_TC_Reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => counter_TC(1),
Q => \^q\(0),
R => SR(0)
);
generateOutPre0_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \INFERRED_GEN.icount_out_reg[32]_0\,
Q => generateOutPre0,
R => SR(0)
);
generateOutPre1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \INFERRED_GEN.icount_out_reg[32]\,
Q => generateOutPre1,
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is
port (
\LOAD_REG_GEN[31].LOAD_REG_I\ : out STD_LOGIC;
\TCSR0_GENERATE[23].TCSR0_FF_I\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
\s_axi_rdata_i_reg[12]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[13]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[14]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[15]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[16]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[17]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[18]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[19]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[20]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[21]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[22]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[23]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[24]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[25]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[26]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[27]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[28]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[29]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[30]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[31]_0\ : out STD_LOGIC;
pair0_Select : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
\s_axi_rdata_i_reg[11]_0\ : out STD_LOGIC;
\TCSR0_GENERATE[24].TCSR0_FF_I\ : out STD_LOGIC;
\TCSR1_GENERATE[24].TCSR1_FF_I\ : out STD_LOGIC;
\LOAD_REG_GEN[31].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[30].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[29].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[28].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[27].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[26].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[25].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[23].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[22].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[21].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[19].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[18].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[17].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[16].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[15].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[14].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[13].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[12].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[11].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[10].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[9].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[8].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[7].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[6].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[5].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[4].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[3].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[2].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[1].LOAD_REG_I\ : out STD_LOGIC;
D_0 : out STD_LOGIC;
\bus2ip_wrce__0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_wrce : out STD_LOGIC_VECTOR ( 1 downto 0 );
\LOAD_REG_GEN[31].LOAD_REG_I_1\ : out STD_LOGIC;
\LOAD_REG_GEN[30].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[29].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[28].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[27].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[26].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[25].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[23].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[22].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[21].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[19].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[18].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[17].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[16].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[15].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[14].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[13].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[12].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[11].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[10].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[9].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[8].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[7].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[6].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[5].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[4].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[3].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[2].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[1].LOAD_REG_I_0\ : out STD_LOGIC;
D_1 : out STD_LOGIC;
s_axi_rvalid_i_reg_0 : out STD_LOGIC;
s_axi_rvalid_i_reg_1 : out STD_LOGIC;
s_axi_rvalid_i_reg_2 : out STD_LOGIC;
\TCSR0_GENERATE[23].TCSR0_FF_I_0\ : out STD_LOGIC;
\TCSR1_GENERATE[23].TCSR1_FF_I\ : out STD_LOGIC;
\s_axi_rdata_i_reg[10]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[0]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[0]_1\ : out STD_LOGIC;
READ_DONE0_I : out STD_LOGIC;
READ_DONE1_I : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
bus2ip_reset : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
read_Mux_In : in STD_LOGIC_VECTOR ( 87 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D_2 : in STD_LOGIC;
read_done1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal I_DECODER_n_100 : STD_LOGIC;
signal I_DECODER_n_101 : STD_LOGIC;
signal I_DECODER_n_25 : STD_LOGIC;
signal I_DECODER_n_26 : STD_LOGIC;
signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 2 );
signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[4]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[4]_i_2_n_0\ : STD_LOGIC;
signal bus2ip_rnw_i : STD_LOGIC;
signal bus2ip_rnw_i06_out : STD_LOGIC;
signal clear : STD_LOGIC;
signal is_read : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_write : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 5 downto 0 );
signal rst : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal \s_axi_rdata_i[31]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state1__2\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[4]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \bus2ip_addr_i[4]_i_2\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair16";
begin
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rvalid <= \^s_axi_rvalid\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(4),
O => plusOp(4)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(0),
I1 => state(1),
O => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(4),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(5),
O => plusOp(5)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(4),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(4),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(5),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(5),
R => clear
);
I_DECODER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
port map (
D(1) => I_DECODER_n_25,
D(0) => I_DECODER_n_26,
D_0 => D_0,
D_1 => D_1,
D_2 => D_2,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(5 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(5 downto 0),
\LOAD_REG_GEN[10].LOAD_REG_I\ => \LOAD_REG_GEN[10].LOAD_REG_I\,
\LOAD_REG_GEN[10].LOAD_REG_I_0\ => \LOAD_REG_GEN[10].LOAD_REG_I_0\,
\LOAD_REG_GEN[11].LOAD_REG_I\ => \LOAD_REG_GEN[11].LOAD_REG_I\,
\LOAD_REG_GEN[11].LOAD_REG_I_0\ => \LOAD_REG_GEN[11].LOAD_REG_I_0\,
\LOAD_REG_GEN[12].LOAD_REG_I\ => \LOAD_REG_GEN[12].LOAD_REG_I\,
\LOAD_REG_GEN[12].LOAD_REG_I_0\ => \LOAD_REG_GEN[12].LOAD_REG_I_0\,
\LOAD_REG_GEN[13].LOAD_REG_I\ => \LOAD_REG_GEN[13].LOAD_REG_I\,
\LOAD_REG_GEN[13].LOAD_REG_I_0\ => \LOAD_REG_GEN[13].LOAD_REG_I_0\,
\LOAD_REG_GEN[14].LOAD_REG_I\ => \LOAD_REG_GEN[14].LOAD_REG_I\,
\LOAD_REG_GEN[14].LOAD_REG_I_0\ => \LOAD_REG_GEN[14].LOAD_REG_I_0\,
\LOAD_REG_GEN[15].LOAD_REG_I\ => \LOAD_REG_GEN[15].LOAD_REG_I\,
\LOAD_REG_GEN[15].LOAD_REG_I_0\ => \LOAD_REG_GEN[15].LOAD_REG_I_0\,
\LOAD_REG_GEN[16].LOAD_REG_I\ => \LOAD_REG_GEN[16].LOAD_REG_I\,
\LOAD_REG_GEN[16].LOAD_REG_I_0\ => \LOAD_REG_GEN[16].LOAD_REG_I_0\,
\LOAD_REG_GEN[17].LOAD_REG_I\ => \LOAD_REG_GEN[17].LOAD_REG_I\,
\LOAD_REG_GEN[17].LOAD_REG_I_0\ => \LOAD_REG_GEN[17].LOAD_REG_I_0\,
\LOAD_REG_GEN[18].LOAD_REG_I\ => \LOAD_REG_GEN[18].LOAD_REG_I\,
\LOAD_REG_GEN[18].LOAD_REG_I_0\ => \LOAD_REG_GEN[18].LOAD_REG_I_0\,
\LOAD_REG_GEN[19].LOAD_REG_I\ => \LOAD_REG_GEN[19].LOAD_REG_I\,
\LOAD_REG_GEN[19].LOAD_REG_I_0\ => \LOAD_REG_GEN[19].LOAD_REG_I_0\,
\LOAD_REG_GEN[1].LOAD_REG_I\ => \LOAD_REG_GEN[1].LOAD_REG_I\,
\LOAD_REG_GEN[1].LOAD_REG_I_0\ => \LOAD_REG_GEN[1].LOAD_REG_I_0\,
\LOAD_REG_GEN[20].LOAD_REG_I\ => \LOAD_REG_GEN[20].LOAD_REG_I\,
\LOAD_REG_GEN[20].LOAD_REG_I_0\ => \LOAD_REG_GEN[20].LOAD_REG_I_0\,
\LOAD_REG_GEN[21].LOAD_REG_I\ => \LOAD_REG_GEN[21].LOAD_REG_I\,
\LOAD_REG_GEN[21].LOAD_REG_I_0\ => \LOAD_REG_GEN[21].LOAD_REG_I_0\,
\LOAD_REG_GEN[22].LOAD_REG_I\ => \LOAD_REG_GEN[22].LOAD_REG_I\,
\LOAD_REG_GEN[22].LOAD_REG_I_0\ => \LOAD_REG_GEN[22].LOAD_REG_I_0\,
\LOAD_REG_GEN[23].LOAD_REG_I\ => \LOAD_REG_GEN[23].LOAD_REG_I\,
\LOAD_REG_GEN[23].LOAD_REG_I_0\ => \LOAD_REG_GEN[23].LOAD_REG_I_0\,
\LOAD_REG_GEN[24].LOAD_REG_I\ => \LOAD_REG_GEN[24].LOAD_REG_I\,
\LOAD_REG_GEN[24].LOAD_REG_I_0\ => \LOAD_REG_GEN[24].LOAD_REG_I_0\,
\LOAD_REG_GEN[25].LOAD_REG_I\ => \LOAD_REG_GEN[25].LOAD_REG_I\,
\LOAD_REG_GEN[25].LOAD_REG_I_0\ => \LOAD_REG_GEN[25].LOAD_REG_I_0\,
\LOAD_REG_GEN[26].LOAD_REG_I\ => \LOAD_REG_GEN[26].LOAD_REG_I\,
\LOAD_REG_GEN[26].LOAD_REG_I_0\ => \LOAD_REG_GEN[26].LOAD_REG_I_0\,
\LOAD_REG_GEN[27].LOAD_REG_I\ => \LOAD_REG_GEN[27].LOAD_REG_I\,
\LOAD_REG_GEN[27].LOAD_REG_I_0\ => \LOAD_REG_GEN[27].LOAD_REG_I_0\,
\LOAD_REG_GEN[28].LOAD_REG_I\ => \LOAD_REG_GEN[28].LOAD_REG_I\,
\LOAD_REG_GEN[28].LOAD_REG_I_0\ => \LOAD_REG_GEN[28].LOAD_REG_I_0\,
\LOAD_REG_GEN[29].LOAD_REG_I\ => \LOAD_REG_GEN[29].LOAD_REG_I\,
\LOAD_REG_GEN[29].LOAD_REG_I_0\ => \LOAD_REG_GEN[29].LOAD_REG_I_0\,
\LOAD_REG_GEN[2].LOAD_REG_I\ => \LOAD_REG_GEN[2].LOAD_REG_I\,
\LOAD_REG_GEN[2].LOAD_REG_I_0\ => \LOAD_REG_GEN[2].LOAD_REG_I_0\,
\LOAD_REG_GEN[30].LOAD_REG_I\ => \LOAD_REG_GEN[30].LOAD_REG_I\,
\LOAD_REG_GEN[30].LOAD_REG_I_0\ => \LOAD_REG_GEN[30].LOAD_REG_I_0\,
\LOAD_REG_GEN[31].LOAD_REG_I\ => \LOAD_REG_GEN[31].LOAD_REG_I\,
\LOAD_REG_GEN[31].LOAD_REG_I_0\ => \LOAD_REG_GEN[31].LOAD_REG_I_0\,
\LOAD_REG_GEN[31].LOAD_REG_I_1\ => \LOAD_REG_GEN[31].LOAD_REG_I_1\,
\LOAD_REG_GEN[3].LOAD_REG_I\ => \LOAD_REG_GEN[3].LOAD_REG_I\,
\LOAD_REG_GEN[3].LOAD_REG_I_0\ => \LOAD_REG_GEN[3].LOAD_REG_I_0\,
\LOAD_REG_GEN[4].LOAD_REG_I\ => \LOAD_REG_GEN[4].LOAD_REG_I\,
\LOAD_REG_GEN[4].LOAD_REG_I_0\ => \LOAD_REG_GEN[4].LOAD_REG_I_0\,
\LOAD_REG_GEN[5].LOAD_REG_I\ => \LOAD_REG_GEN[5].LOAD_REG_I\,
\LOAD_REG_GEN[5].LOAD_REG_I_0\ => \LOAD_REG_GEN[5].LOAD_REG_I_0\,
\LOAD_REG_GEN[6].LOAD_REG_I\ => \LOAD_REG_GEN[6].LOAD_REG_I\,
\LOAD_REG_GEN[6].LOAD_REG_I_0\ => \LOAD_REG_GEN[6].LOAD_REG_I_0\,
\LOAD_REG_GEN[7].LOAD_REG_I\ => \LOAD_REG_GEN[7].LOAD_REG_I\,
\LOAD_REG_GEN[7].LOAD_REG_I_0\ => \LOAD_REG_GEN[7].LOAD_REG_I_0\,
\LOAD_REG_GEN[8].LOAD_REG_I\ => \LOAD_REG_GEN[8].LOAD_REG_I\,
\LOAD_REG_GEN[8].LOAD_REG_I_0\ => \LOAD_REG_GEN[8].LOAD_REG_I_0\,
\LOAD_REG_GEN[9].LOAD_REG_I\ => \LOAD_REG_GEN[9].LOAD_REG_I\,
\LOAD_REG_GEN[9].LOAD_REG_I_0\ => \LOAD_REG_GEN[9].LOAD_REG_I_0\,
Q => start2,
READ_DONE0_I => READ_DONE0_I,
READ_DONE1_I => READ_DONE1_I,
\TCSR0_GENERATE[23].TCSR0_FF_I\ => \TCSR0_GENERATE[23].TCSR0_FF_I\,
\TCSR0_GENERATE[23].TCSR0_FF_I_0\ => \TCSR0_GENERATE[23].TCSR0_FF_I_0\,
\TCSR0_GENERATE[24].TCSR0_FF_I\ => \TCSR0_GENERATE[24].TCSR0_FF_I\,
\TCSR1_GENERATE[23].TCSR1_FF_I\ => \TCSR1_GENERATE[23].TCSR1_FF_I\,
\TCSR1_GENERATE[24].TCSR1_FF_I\ => \TCSR1_GENERATE[24].TCSR1_FF_I\,
\bus2ip_addr_i_reg[4]\(2) => bus2ip_addr(0),
\bus2ip_addr_i_reg[4]\(1) => bus2ip_addr(1),
\bus2ip_addr_i_reg[4]\(0) => bus2ip_addr(2),
bus2ip_rnw_i => bus2ip_rnw_i,
bus2ip_wrce(1 downto 0) => bus2ip_wrce(1 downto 0),
\bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(0),
is_read => is_read,
is_write_reg => is_write_reg_n_0,
pair0_Select => pair0_Select,
read_Mux_In(87 downto 0) => read_Mux_In(87 downto 0),
read_done1 => read_done1,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_arvalid_0 => \state[1]_i_3_n_0\,
s_axi_bready => s_axi_bready,
s_axi_bvalid_i_reg => I_DECODER_n_101,
s_axi_bvalid_i_reg_0 => \^s_axi_bvalid\,
\s_axi_rdata_i_reg[0]\ => \s_axi_rdata_i_reg[0]_0\,
\s_axi_rdata_i_reg[0]_0\ => \s_axi_rdata_i_reg[0]_1\,
\s_axi_rdata_i_reg[10]\ => \s_axi_rdata_i_reg[10]_0\,
\s_axi_rdata_i_reg[11]\ => \s_axi_rdata_i_reg[11]_0\,
\s_axi_rdata_i_reg[12]\ => \s_axi_rdata_i_reg[12]_0\,
\s_axi_rdata_i_reg[13]\ => \s_axi_rdata_i_reg[13]_0\,
\s_axi_rdata_i_reg[14]\ => \s_axi_rdata_i_reg[14]_0\,
\s_axi_rdata_i_reg[15]\ => \s_axi_rdata_i_reg[15]_0\,
\s_axi_rdata_i_reg[16]\ => \s_axi_rdata_i_reg[16]_0\,
\s_axi_rdata_i_reg[17]\ => \s_axi_rdata_i_reg[17]_0\,
\s_axi_rdata_i_reg[18]\ => \s_axi_rdata_i_reg[18]_0\,
\s_axi_rdata_i_reg[19]\ => \s_axi_rdata_i_reg[19]_0\,
\s_axi_rdata_i_reg[20]\ => \s_axi_rdata_i_reg[20]_0\,
\s_axi_rdata_i_reg[21]\ => \s_axi_rdata_i_reg[21]_0\,
\s_axi_rdata_i_reg[22]\ => \s_axi_rdata_i_reg[22]_0\,
\s_axi_rdata_i_reg[23]\ => \s_axi_rdata_i_reg[23]_0\,
\s_axi_rdata_i_reg[24]\ => \s_axi_rdata_i_reg[24]_0\,
\s_axi_rdata_i_reg[25]\ => \s_axi_rdata_i_reg[25]_0\,
\s_axi_rdata_i_reg[26]\ => \s_axi_rdata_i_reg[26]_0\,
\s_axi_rdata_i_reg[27]\ => \s_axi_rdata_i_reg[27]_0\,
\s_axi_rdata_i_reg[28]\ => \s_axi_rdata_i_reg[28]_0\,
\s_axi_rdata_i_reg[29]\ => \s_axi_rdata_i_reg[29]_0\,
\s_axi_rdata_i_reg[30]\ => \s_axi_rdata_i_reg[30]_0\,
\s_axi_rdata_i_reg[31]\ => \s_axi_rdata_i_reg[31]_0\,
s_axi_rready => s_axi_rready,
s_axi_rvalid_i_reg => s_axi_rvalid_i_reg_0,
s_axi_rvalid_i_reg_0 => s_axi_rvalid_i_reg_1,
s_axi_rvalid_i_reg_1 => s_axi_rvalid_i_reg_2,
s_axi_rvalid_i_reg_2 => I_DECODER_n_100,
s_axi_rvalid_i_reg_3 => \^s_axi_rvalid\,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
\state1__2\ => \state1__2\,
\state_reg[1]\(1 downto 0) => state(1 downto 0)
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFF0200"
)
port map (
I0 => s_axi_araddr(0),
I1 => state(0),
I2 => state(1),
I3 => s_axi_arvalid,
I4 => s_axi_awaddr(0),
O => \bus2ip_addr_i[2]_i_1_n_0\
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFF0200"
)
port map (
I0 => s_axi_araddr(1),
I1 => state(0),
I2 => state(1),
I3 => s_axi_arvalid,
I4 => s_axi_awaddr(1),
O => \bus2ip_addr_i[3]_i_1_n_0\
);
\bus2ip_addr_i[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000EA"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => state(0),
O => \bus2ip_addr_i[4]_i_1_n_0\
);
\bus2ip_addr_i[4]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFF0200"
)
port map (
I0 => s_axi_araddr(2),
I1 => state(0),
I2 => state(1),
I3 => s_axi_arvalid,
I4 => s_axi_awaddr(2),
O => \bus2ip_addr_i[4]_i_2_n_0\
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[4]_i_1_n_0\,
D => \bus2ip_addr_i[2]_i_1_n_0\,
Q => bus2ip_addr(2),
R => rst
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[4]_i_1_n_0\,
D => \bus2ip_addr_i[3]_i_1_n_0\,
Q => bus2ip_addr(1),
R => rst
);
\bus2ip_addr_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[4]_i_1_n_0\,
D => \bus2ip_addr_i[4]_i_2_n_0\,
Q => bus2ip_addr(0),
R => rst
);
bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => state(0),
I1 => state(1),
I2 => s_axi_arvalid,
O => bus2ip_rnw_i06_out
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[4]_i_1_n_0\,
D => bus2ip_rnw_i06_out,
Q => bus2ip_rnw_i,
R => rst
);
is_read_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"3FFA000A"
)
port map (
I0 => s_axi_arvalid,
I1 => \state1__2\,
I2 => state(0),
I3 => state(1),
I4 => is_read,
O => is_read_i_1_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read,
R => rst
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0040FFFF00400000"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => is_write,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F88800000000FFFF"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => \^s_axi_bvalid\,
I3 => s_axi_bready,
I4 => state(0),
I5 => state(1),
O => is_write
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => rst
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => bus2ip_reset,
Q => rst,
R => '0'
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_DECODER_n_101,
Q => \^s_axi_bvalid\,
R => rst
);
\s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => \s_axi_rdata_i[31]_i_1_n_0\
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(0),
Q => s_axi_rdata(0),
R => rst
);
\s_axi_rdata_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(10),
Q => s_axi_rdata(10),
R => rst
);
\s_axi_rdata_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(11),
Q => s_axi_rdata(11),
R => rst
);
\s_axi_rdata_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(12),
Q => s_axi_rdata(12),
R => rst
);
\s_axi_rdata_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(13),
Q => s_axi_rdata(13),
R => rst
);
\s_axi_rdata_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(14),
Q => s_axi_rdata(14),
R => rst
);
\s_axi_rdata_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(15),
Q => s_axi_rdata(15),
R => rst
);
\s_axi_rdata_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(16),
Q => s_axi_rdata(16),
R => rst
);
\s_axi_rdata_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(17),
Q => s_axi_rdata(17),
R => rst
);
\s_axi_rdata_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(18),
Q => s_axi_rdata(18),
R => rst
);
\s_axi_rdata_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(19),
Q => s_axi_rdata(19),
R => rst
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(1),
Q => s_axi_rdata(1),
R => rst
);
\s_axi_rdata_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(20),
Q => s_axi_rdata(20),
R => rst
);
\s_axi_rdata_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(21),
Q => s_axi_rdata(21),
R => rst
);
\s_axi_rdata_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(22),
Q => s_axi_rdata(22),
R => rst
);
\s_axi_rdata_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(23),
Q => s_axi_rdata(23),
R => rst
);
\s_axi_rdata_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(24),
Q => s_axi_rdata(24),
R => rst
);
\s_axi_rdata_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(25),
Q => s_axi_rdata(25),
R => rst
);
\s_axi_rdata_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(26),
Q => s_axi_rdata(26),
R => rst
);
\s_axi_rdata_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(27),
Q => s_axi_rdata(27),
R => rst
);
\s_axi_rdata_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(28),
Q => s_axi_rdata(28),
R => rst
);
\s_axi_rdata_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(29),
Q => s_axi_rdata(29),
R => rst
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(2),
Q => s_axi_rdata(2),
R => rst
);
\s_axi_rdata_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(30),
Q => s_axi_rdata(30),
R => rst
);
\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(31),
Q => s_axi_rdata(31),
R => rst
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(3),
Q => s_axi_rdata(3),
R => rst
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(4),
Q => s_axi_rdata(4),
R => rst
);
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(5),
Q => s_axi_rdata(5),
R => rst
);
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(6),
Q => s_axi_rdata(6),
R => rst
);
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(7),
Q => s_axi_rdata(7),
R => rst
);
\s_axi_rdata_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(8),
Q => s_axi_rdata(8),
R => rst
);
\s_axi_rdata_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(9),
Q => s_axi_rdata(9),
R => rst
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_DECODER_n_100,
Q => \^s_axi_rvalid\,
R => rst
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => state(1),
I4 => state(0),
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => rst
);
\state[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \state1__2\
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_awvalid,
I2 => s_axi_arvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => I_DECODER_n_26,
Q => state(0),
R => rst
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => I_DECODER_n_25,
Q => state(1),
R => rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_tc_core is
port (
D : out STD_LOGIC_VECTOR ( 31 downto 0 );
\INFERRED_GEN.icount_out_reg[0]\ : out STD_LOGIC_VECTOR ( 87 downto 0 );
bus2ip_reset : out STD_LOGIC;
generateout0 : out STD_LOGIC;
generateout1 : out STD_LOGIC;
interrupt : out STD_LOGIC;
D_0 : out STD_LOGIC;
read_done1 : out STD_LOGIC;
pwm0 : out STD_LOGIC;
Bus_RNW_reg_reg : in STD_LOGIC;
Bus_RNW_reg_reg_0 : in STD_LOGIC;
Bus_RNW_reg_reg_1 : in STD_LOGIC;
Bus_RNW_reg_reg_2 : in STD_LOGIC;
Bus_RNW_reg_reg_3 : in STD_LOGIC;
Bus_RNW_reg_reg_4 : in STD_LOGIC;
Bus_RNW_reg_reg_5 : in STD_LOGIC;
Bus_RNW_reg_reg_6 : in STD_LOGIC;
Bus_RNW_reg_reg_7 : in STD_LOGIC;
Bus_RNW_reg_reg_8 : in STD_LOGIC;
Bus_RNW_reg_reg_9 : in STD_LOGIC;
Bus_RNW_reg_reg_10 : in STD_LOGIC;
Bus_RNW_reg_reg_11 : in STD_LOGIC;
Bus_RNW_reg_reg_12 : in STD_LOGIC;
Bus_RNW_reg_reg_13 : in STD_LOGIC;
Bus_RNW_reg_reg_14 : in STD_LOGIC;
Bus_RNW_reg_reg_15 : in STD_LOGIC;
Bus_RNW_reg_reg_16 : in STD_LOGIC;
Bus_RNW_reg_reg_17 : in STD_LOGIC;
Bus_RNW_reg_reg_18 : in STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I\ : in STD_LOGIC;
D_1 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\ : in STD_LOGIC;
D_2 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[30]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[29]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[28]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[27]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[26]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[25]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[24]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[23]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[22]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[21]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[20]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[19]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[18]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[17]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[16]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[15]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[14]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[13]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[12]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[11]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[10]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[9]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[8]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[7]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[6]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[5]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[4]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[3]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[2]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[1]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[0]_0\ : in STD_LOGIC;
bus2ip_wrce : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 9 downto 0 );
pair0_Select : in STD_LOGIC;
\TCSR0_GENERATE[24].TCSR0_FF_I\ : in STD_LOGIC;
\TCSR1_GENERATE[24].TCSR1_FF_I\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_30\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_31\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC;
\bus2ip_wrce__0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
freeze : in STD_LOGIC;
capturetrig0 : in STD_LOGIC;
capturetrig1 : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_tc_core;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_tc_core is
signal COUNTER_0_I_n_64 : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_33\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_34\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_35\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_36\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_37\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_38\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_39\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_40\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_41\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_42\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_43\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_44\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_45\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_46\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_47\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_48\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_49\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_50\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_51\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_52\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_53\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_54\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_55\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_56\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_57\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_58\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_59\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_60\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_61\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_62\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_63\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_64\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_65\ : STD_LOGIC;
signal \^inferred_gen.icount_out_reg[0]\ : STD_LOGIC_VECTOR ( 87 downto 0 );
signal R : STD_LOGIC;
signal TIMER_CONTROL_I_n_12 : STD_LOGIC;
signal TIMER_CONTROL_I_n_13 : STD_LOGIC;
signal TIMER_CONTROL_I_n_14 : STD_LOGIC;
signal TIMER_CONTROL_I_n_15 : STD_LOGIC;
signal TIMER_CONTROL_I_n_16 : STD_LOGIC;
signal TIMER_CONTROL_I_n_17 : STD_LOGIC;
signal TIMER_CONTROL_I_n_18 : STD_LOGIC;
signal TIMER_CONTROL_I_n_19 : STD_LOGIC;
signal TIMER_CONTROL_I_n_20 : STD_LOGIC;
signal TIMER_CONTROL_I_n_21 : STD_LOGIC;
signal TIMER_CONTROL_I_n_22 : STD_LOGIC;
signal TIMER_CONTROL_I_n_24 : STD_LOGIC;
signal TIMER_CONTROL_I_n_25 : STD_LOGIC;
signal TIMER_CONTROL_I_n_26 : STD_LOGIC;
signal TIMER_CONTROL_I_n_27 : STD_LOGIC;
signal TIMER_CONTROL_I_n_28 : STD_LOGIC;
signal TIMER_CONTROL_I_n_29 : STD_LOGIC;
signal TIMER_CONTROL_I_n_3 : STD_LOGIC;
signal TIMER_CONTROL_I_n_30 : STD_LOGIC;
signal TIMER_CONTROL_I_n_4 : STD_LOGIC;
signal \^bus2ip_reset\ : STD_LOGIC;
signal counter_TC : STD_LOGIC_VECTOR ( 0 to 1 );
signal load_Counter_Reg : STD_LOGIC_VECTOR ( 0 to 1 );
signal \^pwm0\ : STD_LOGIC;
signal read_Mux_In : STD_LOGIC_VECTOR ( 85 to 95 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of PWM_FF_I : label is "PRIMITIVE";
attribute IS_S_INVERTED : string;
attribute IS_S_INVERTED of PWM_FF_I : label is "1'b0";
begin
\INFERRED_GEN.icount_out_reg[0]\(87 downto 0) <= \^inferred_gen.icount_out_reg[0]\(87 downto 0);
bus2ip_reset <= \^bus2ip_reset\;
pwm0 <= \^pwm0\;
COUNTER_0_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_count_module
port map (
D_1 => D_1,
E(0) => TIMER_CONTROL_I_n_24,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\,
\INFERRED_GEN.icount_out_reg[31]\(52 downto 0) => \^inferred_gen.icount_out_reg[0]\(84 downto 32),
Q(0) => TIMER_CONTROL_I_n_3,
S(0) => TIMER_CONTROL_I_n_27,
\TCSR0_GENERATE[27].TCSR0_FF_I\ => TIMER_CONTROL_I_n_28,
counter_TC(0) => counter_TC(0),
generateOutPre0_reg => COUNTER_0_I_n_64,
load_Counter_Reg(0) => load_Counter_Reg(0),
read_Mux_In(10) => read_Mux_In(85),
read_Mux_In(9) => read_Mux_In(86),
read_Mux_In(8) => read_Mux_In(87),
read_Mux_In(7) => read_Mux_In(88),
read_Mux_In(6) => read_Mux_In(89),
read_Mux_In(5) => read_Mux_In(90),
read_Mux_In(4) => read_Mux_In(91),
read_Mux_In(3) => read_Mux_In(92),
read_Mux_In(2) => read_Mux_In(93),
read_Mux_In(1) => read_Mux_In(94),
read_Mux_In(0) => read_Mux_In(95),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_aresetn_0 => \^bus2ip_reset\
);
\GEN_SECOND_TIMER.COUNTER_1_I\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_count_module_0
port map (
D_2 => D_2,
E(0) => TIMER_CONTROL_I_n_25,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0\,
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
\INFERRED_GEN.icount_out_reg[0]\ => \INFERRED_GEN.icount_out_reg[0]_0\,
\INFERRED_GEN.icount_out_reg[10]\ => \INFERRED_GEN.icount_out_reg[10]\,
\INFERRED_GEN.icount_out_reg[11]\ => \INFERRED_GEN.icount_out_reg[11]\,
\INFERRED_GEN.icount_out_reg[12]\ => \INFERRED_GEN.icount_out_reg[12]\,
\INFERRED_GEN.icount_out_reg[13]\ => \INFERRED_GEN.icount_out_reg[13]\,
\INFERRED_GEN.icount_out_reg[14]\ => \INFERRED_GEN.icount_out_reg[14]\,
\INFERRED_GEN.icount_out_reg[15]\ => \INFERRED_GEN.icount_out_reg[15]\,
\INFERRED_GEN.icount_out_reg[16]\ => \INFERRED_GEN.icount_out_reg[16]\,
\INFERRED_GEN.icount_out_reg[17]\ => \INFERRED_GEN.icount_out_reg[17]\,
\INFERRED_GEN.icount_out_reg[18]\ => \INFERRED_GEN.icount_out_reg[18]\,
\INFERRED_GEN.icount_out_reg[19]\ => \INFERRED_GEN.icount_out_reg[19]\,
\INFERRED_GEN.icount_out_reg[1]\ => \INFERRED_GEN.icount_out_reg[1]\,
\INFERRED_GEN.icount_out_reg[20]\ => \INFERRED_GEN.icount_out_reg[20]\,
\INFERRED_GEN.icount_out_reg[21]\ => \INFERRED_GEN.icount_out_reg[21]\,
\INFERRED_GEN.icount_out_reg[22]\ => \INFERRED_GEN.icount_out_reg[22]\,
\INFERRED_GEN.icount_out_reg[23]\ => \INFERRED_GEN.icount_out_reg[23]\,
\INFERRED_GEN.icount_out_reg[24]\ => \INFERRED_GEN.icount_out_reg[24]\,
\INFERRED_GEN.icount_out_reg[25]\ => \INFERRED_GEN.icount_out_reg[25]\,
\INFERRED_GEN.icount_out_reg[26]\ => \INFERRED_GEN.icount_out_reg[26]\,
\INFERRED_GEN.icount_out_reg[27]\ => \INFERRED_GEN.icount_out_reg[27]\,
\INFERRED_GEN.icount_out_reg[28]\ => \INFERRED_GEN.icount_out_reg[28]\,
\INFERRED_GEN.icount_out_reg[29]\ => \INFERRED_GEN.icount_out_reg[29]\,
\INFERRED_GEN.icount_out_reg[2]\ => \INFERRED_GEN.icount_out_reg[2]\,
\INFERRED_GEN.icount_out_reg[30]\ => \INFERRED_GEN.icount_out_reg[30]\,
\INFERRED_GEN.icount_out_reg[31]\ => \^bus2ip_reset\,
\INFERRED_GEN.icount_out_reg[31]_0\(31 downto 0) => \^inferred_gen.icount_out_reg[0]\(63 downto 32),
\INFERRED_GEN.icount_out_reg[3]\ => \INFERRED_GEN.icount_out_reg[3]\,
\INFERRED_GEN.icount_out_reg[4]\ => \INFERRED_GEN.icount_out_reg[4]\,
\INFERRED_GEN.icount_out_reg[5]\ => \INFERRED_GEN.icount_out_reg[5]\,
\INFERRED_GEN.icount_out_reg[6]\ => \INFERRED_GEN.icount_out_reg[6]\,
\INFERRED_GEN.icount_out_reg[7]\ => \INFERRED_GEN.icount_out_reg[7]\,
\INFERRED_GEN.icount_out_reg[8]\ => \INFERRED_GEN.icount_out_reg[8]\,
\INFERRED_GEN.icount_out_reg[9]\ => \INFERRED_GEN.icount_out_reg[9]\,
Q(31 downto 0) => \^inferred_gen.icount_out_reg[0]\(31 downto 0),
S(0) => TIMER_CONTROL_I_n_30,
\TCSR0_GENERATE[20].TCSR0_FF_I\ => TIMER_CONTROL_I_n_29,
counter_TC(0) => counter_TC(1),
\counter_TC_Reg_reg[1]\(0) => TIMER_CONTROL_I_n_4,
generateOutPre1_reg => \GEN_SECOND_TIMER.COUNTER_1_I_n_65\,
load_Counter_Reg(0) => load_Counter_Reg(1),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
\s_axi_rdata_i_reg[0]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_33\,
\s_axi_rdata_i_reg[10]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_43\,
\s_axi_rdata_i_reg[11]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_44\,
\s_axi_rdata_i_reg[12]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_45\,
\s_axi_rdata_i_reg[13]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_46\,
\s_axi_rdata_i_reg[14]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_47\,
\s_axi_rdata_i_reg[15]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_48\,
\s_axi_rdata_i_reg[16]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_49\,
\s_axi_rdata_i_reg[17]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_50\,
\s_axi_rdata_i_reg[18]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_51\,
\s_axi_rdata_i_reg[19]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_52\,
\s_axi_rdata_i_reg[1]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_34\,
\s_axi_rdata_i_reg[20]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_53\,
\s_axi_rdata_i_reg[21]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_54\,
\s_axi_rdata_i_reg[22]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_55\,
\s_axi_rdata_i_reg[23]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_56\,
\s_axi_rdata_i_reg[24]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_57\,
\s_axi_rdata_i_reg[25]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_58\,
\s_axi_rdata_i_reg[26]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_59\,
\s_axi_rdata_i_reg[27]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_60\,
\s_axi_rdata_i_reg[28]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_61\,
\s_axi_rdata_i_reg[29]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_62\,
\s_axi_rdata_i_reg[2]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_35\,
\s_axi_rdata_i_reg[30]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_63\,
\s_axi_rdata_i_reg[31]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_64\,
\s_axi_rdata_i_reg[3]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_36\,
\s_axi_rdata_i_reg[4]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_37\,
\s_axi_rdata_i_reg[5]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_38\,
\s_axi_rdata_i_reg[6]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_39\,
\s_axi_rdata_i_reg[7]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_40\,
\s_axi_rdata_i_reg[8]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_41\,
\s_axi_rdata_i_reg[9]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_42\
);
PWM_FF_I: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => TIMER_CONTROL_I_n_26,
Q => \^pwm0\,
R => R
);
READ_MUX_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_mux_onehot_f
port map (
Bus_RNW_reg_reg => Bus_RNW_reg_reg,
Bus_RNW_reg_reg_0 => Bus_RNW_reg_reg_0,
Bus_RNW_reg_reg_1 => Bus_RNW_reg_reg_1,
Bus_RNW_reg_reg_10 => Bus_RNW_reg_reg_10,
Bus_RNW_reg_reg_11 => Bus_RNW_reg_reg_11,
Bus_RNW_reg_reg_12 => Bus_RNW_reg_reg_12,
Bus_RNW_reg_reg_13 => Bus_RNW_reg_reg_13,
Bus_RNW_reg_reg_14 => Bus_RNW_reg_reg_14,
Bus_RNW_reg_reg_15 => Bus_RNW_reg_reg_15,
Bus_RNW_reg_reg_16 => Bus_RNW_reg_reg_16,
Bus_RNW_reg_reg_17 => Bus_RNW_reg_reg_17,
Bus_RNW_reg_reg_18 => Bus_RNW_reg_reg_18,
Bus_RNW_reg_reg_2 => Bus_RNW_reg_reg_2,
Bus_RNW_reg_reg_3 => Bus_RNW_reg_reg_3,
Bus_RNW_reg_reg_4 => Bus_RNW_reg_reg_4,
Bus_RNW_reg_reg_5 => Bus_RNW_reg_reg_5,
Bus_RNW_reg_reg_6 => Bus_RNW_reg_reg_6,
Bus_RNW_reg_reg_7 => Bus_RNW_reg_reg_7,
Bus_RNW_reg_reg_8 => Bus_RNW_reg_reg_8,
Bus_RNW_reg_reg_9 => Bus_RNW_reg_reg_9,
D(31 downto 0) => D(31 downto 0),
\INFERRED_GEN.icount_out_reg[0]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_33\,
\INFERRED_GEN.icount_out_reg[10]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_43\,
\INFERRED_GEN.icount_out_reg[11]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_44\,
\INFERRED_GEN.icount_out_reg[12]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_45\,
\INFERRED_GEN.icount_out_reg[13]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_46\,
\INFERRED_GEN.icount_out_reg[14]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_47\,
\INFERRED_GEN.icount_out_reg[15]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_48\,
\INFERRED_GEN.icount_out_reg[16]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_49\,
\INFERRED_GEN.icount_out_reg[17]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_50\,
\INFERRED_GEN.icount_out_reg[18]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_51\,
\INFERRED_GEN.icount_out_reg[19]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_52\,
\INFERRED_GEN.icount_out_reg[1]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_34\,
\INFERRED_GEN.icount_out_reg[20]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_53\,
\INFERRED_GEN.icount_out_reg[21]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_54\,
\INFERRED_GEN.icount_out_reg[22]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_55\,
\INFERRED_GEN.icount_out_reg[23]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_56\,
\INFERRED_GEN.icount_out_reg[24]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_57\,
\INFERRED_GEN.icount_out_reg[25]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_58\,
\INFERRED_GEN.icount_out_reg[26]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_59\,
\INFERRED_GEN.icount_out_reg[27]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_60\,
\INFERRED_GEN.icount_out_reg[28]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_61\,
\INFERRED_GEN.icount_out_reg[29]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_62\,
\INFERRED_GEN.icount_out_reg[2]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_35\,
\INFERRED_GEN.icount_out_reg[30]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_63\,
\INFERRED_GEN.icount_out_reg[31]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_64\,
\INFERRED_GEN.icount_out_reg[3]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_36\,
\INFERRED_GEN.icount_out_reg[4]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_37\,
\INFERRED_GEN.icount_out_reg[5]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_38\,
\INFERRED_GEN.icount_out_reg[6]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_39\,
\INFERRED_GEN.icount_out_reg[7]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_40\,
\INFERRED_GEN.icount_out_reg[8]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_41\,
\INFERRED_GEN.icount_out_reg[9]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_42\,
\LOAD_REG_GEN[20].LOAD_REG_I\ => \LOAD_REG_GEN[20].LOAD_REG_I\,
\LOAD_REG_GEN[21].LOAD_REG_I\ => TIMER_CONTROL_I_n_22,
\LOAD_REG_GEN[22].LOAD_REG_I\ => TIMER_CONTROL_I_n_21,
\LOAD_REG_GEN[23].LOAD_REG_I\ => TIMER_CONTROL_I_n_20,
\LOAD_REG_GEN[24].LOAD_REG_I\ => TIMER_CONTROL_I_n_19,
\LOAD_REG_GEN[25].LOAD_REG_I\ => TIMER_CONTROL_I_n_18,
\LOAD_REG_GEN[26].LOAD_REG_I\ => TIMER_CONTROL_I_n_17,
\LOAD_REG_GEN[27].LOAD_REG_I\ => TIMER_CONTROL_I_n_16,
\LOAD_REG_GEN[28].LOAD_REG_I\ => TIMER_CONTROL_I_n_15,
\LOAD_REG_GEN[29].LOAD_REG_I\ => TIMER_CONTROL_I_n_14,
\LOAD_REG_GEN[30].LOAD_REG_I\ => TIMER_CONTROL_I_n_13,
\LOAD_REG_GEN[31].LOAD_REG_I\ => TIMER_CONTROL_I_n_12
);
TIMER_CONTROL_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_timer_control
port map (
Bus_RNW_reg => Bus_RNW_reg,
D_0 => D_0,
E(0) => TIMER_CONTROL_I_n_24,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_30\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_31\,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
\INFERRED_GEN.icount_out_reg[0]\ => \^inferred_gen.icount_out_reg[0]\(87),
\INFERRED_GEN.icount_out_reg[0]_0\(0) => TIMER_CONTROL_I_n_25,
\INFERRED_GEN.icount_out_reg[1]\(1) => \^inferred_gen.icount_out_reg[0]\(33),
\INFERRED_GEN.icount_out_reg[1]\(0) => \^inferred_gen.icount_out_reg[0]\(1),
\INFERRED_GEN.icount_out_reg[32]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_65\,
\INFERRED_GEN.icount_out_reg[32]_0\ => COUNTER_0_I_n_64,
\INFERRED_GEN.icount_out_reg[4]\(0) => TIMER_CONTROL_I_n_30,
\LOAD_REG_GEN[21].LOAD_REG_I\(10) => read_Mux_In(85),
\LOAD_REG_GEN[21].LOAD_REG_I\(9) => read_Mux_In(86),
\LOAD_REG_GEN[21].LOAD_REG_I\(8) => read_Mux_In(87),
\LOAD_REG_GEN[21].LOAD_REG_I\(7) => read_Mux_In(88),
\LOAD_REG_GEN[21].LOAD_REG_I\(6) => read_Mux_In(89),
\LOAD_REG_GEN[21].LOAD_REG_I\(5) => read_Mux_In(90),
\LOAD_REG_GEN[21].LOAD_REG_I\(4) => read_Mux_In(91),
\LOAD_REG_GEN[21].LOAD_REG_I\(3) => read_Mux_In(92),
\LOAD_REG_GEN[21].LOAD_REG_I\(2) => read_Mux_In(93),
\LOAD_REG_GEN[21].LOAD_REG_I\(1) => read_Mux_In(94),
\LOAD_REG_GEN[21].LOAD_REG_I\(0) => read_Mux_In(95),
\LOAD_REG_GEN[24].LOAD_REG_I\ => TIMER_CONTROL_I_n_28,
\LOAD_REG_GEN[24].LOAD_REG_I_0\ => TIMER_CONTROL_I_n_29,
PWM_FF_I => TIMER_CONTROL_I_n_26,
Q(1) => TIMER_CONTROL_I_n_3,
Q(0) => TIMER_CONTROL_I_n_4,
R => R,
S(0) => TIMER_CONTROL_I_n_27,
SR(0) => \^bus2ip_reset\,
\TCSR0_GENERATE[24].TCSR0_FF_I_0\ => \^inferred_gen.icount_out_reg[0]\(86),
\TCSR0_GENERATE[24].TCSR0_FF_I_1\ => \TCSR0_GENERATE[24].TCSR0_FF_I\,
\TCSR1_GENERATE[23].TCSR1_FF_I_0\ => \^inferred_gen.icount_out_reg[0]\(85),
\TCSR1_GENERATE[24].TCSR1_FF_I_0\ => \TCSR1_GENERATE[24].TCSR1_FF_I\,
bus2ip_wrce(1 downto 0) => bus2ip_wrce(1 downto 0),
\bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(0),
capturetrig0 => capturetrig0,
capturetrig1 => capturetrig1,
counter_TC(0 to 1) => counter_TC(0 to 1),
freeze => freeze,
generateout0 => generateout0,
generateout1 => generateout1,
interrupt => interrupt,
load_Counter_Reg(0 to 1) => load_Counter_Reg(0 to 1),
pair0_Select => pair0_Select,
pwm0 => \^pwm0\,
read_done1 => read_done1,
s_axi_aclk => s_axi_aclk,
\s_axi_rdata_i_reg[0]\ => TIMER_CONTROL_I_n_12,
\s_axi_rdata_i_reg[10]\ => TIMER_CONTROL_I_n_22,
\s_axi_rdata_i_reg[1]\ => TIMER_CONTROL_I_n_13,
\s_axi_rdata_i_reg[2]\ => TIMER_CONTROL_I_n_14,
\s_axi_rdata_i_reg[3]\ => TIMER_CONTROL_I_n_15,
\s_axi_rdata_i_reg[4]\ => TIMER_CONTROL_I_n_16,
\s_axi_rdata_i_reg[5]\ => TIMER_CONTROL_I_n_17,
\s_axi_rdata_i_reg[6]\ => TIMER_CONTROL_I_n_18,
\s_axi_rdata_i_reg[7]\ => TIMER_CONTROL_I_n_19,
\s_axi_rdata_i_reg[8]\ => TIMER_CONTROL_I_n_20,
\s_axi_rdata_i_reg[9]\ => TIMER_CONTROL_I_n_21,
s_axi_wdata(9 downto 0) => s_axi_wdata(9 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is
port (
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : out STD_LOGIC;
Bus_RNW_reg : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
\s_axi_rdata_i_reg[12]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[13]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[14]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[15]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[16]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[17]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[18]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[19]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[20]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[21]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[22]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[23]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[24]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[25]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[26]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[27]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[28]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[29]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[30]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[31]\ : out STD_LOGIC;
pair0_Select : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
\s_axi_rdata_i_reg[11]\ : out STD_LOGIC;
\TCSR0_GENERATE[24].TCSR0_FF_I\ : out STD_LOGIC;
\TCSR1_GENERATE[24].TCSR1_FF_I\ : out STD_LOGIC;
\LOAD_REG_GEN[31].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[30].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[29].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[28].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[27].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[26].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[25].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[23].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[22].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[21].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[19].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[18].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[17].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[16].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[15].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[14].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[13].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[12].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[11].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[10].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[9].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[8].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[7].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[6].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[5].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[4].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[3].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[2].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[1].LOAD_REG_I\ : out STD_LOGIC;
D_0 : out STD_LOGIC;
\bus2ip_wrce__0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_wrce : out STD_LOGIC_VECTOR ( 1 downto 0 );
\LOAD_REG_GEN[31].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[30].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[29].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[28].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[27].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[26].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[25].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[23].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[22].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[21].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[19].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[18].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[17].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[16].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[15].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[14].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[13].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[12].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[11].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[10].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[9].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[8].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[7].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[6].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[5].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[4].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[3].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[2].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[1].LOAD_REG_I_0\ : out STD_LOGIC;
D_1 : out STD_LOGIC;
s_axi_rvalid_i_reg : out STD_LOGIC;
s_axi_rvalid_i_reg_0 : out STD_LOGIC;
s_axi_rvalid_i_reg_1 : out STD_LOGIC;
\TCSR0_GENERATE[23].TCSR0_FF_I\ : out STD_LOGIC;
\TCSR1_GENERATE[23].TCSR1_FF_I\ : out STD_LOGIC;
\s_axi_rdata_i_reg[10]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[0]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[0]_0\ : out STD_LOGIC;
READ_DONE0_I : out STD_LOGIC;
READ_DONE1_I : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
bus2ip_reset : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
read_Mux_In : in STD_LOGIC_VECTOR ( 87 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D_2 : in STD_LOGIC;
read_done1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
port map (
D(31 downto 0) => D(31 downto 0),
D_0 => D_0,
D_1 => D_1,
D_2 => D_2,
\LOAD_REG_GEN[10].LOAD_REG_I\ => \LOAD_REG_GEN[10].LOAD_REG_I\,
\LOAD_REG_GEN[10].LOAD_REG_I_0\ => \LOAD_REG_GEN[10].LOAD_REG_I_0\,
\LOAD_REG_GEN[11].LOAD_REG_I\ => \LOAD_REG_GEN[11].LOAD_REG_I\,
\LOAD_REG_GEN[11].LOAD_REG_I_0\ => \LOAD_REG_GEN[11].LOAD_REG_I_0\,
\LOAD_REG_GEN[12].LOAD_REG_I\ => \LOAD_REG_GEN[12].LOAD_REG_I\,
\LOAD_REG_GEN[12].LOAD_REG_I_0\ => \LOAD_REG_GEN[12].LOAD_REG_I_0\,
\LOAD_REG_GEN[13].LOAD_REG_I\ => \LOAD_REG_GEN[13].LOAD_REG_I\,
\LOAD_REG_GEN[13].LOAD_REG_I_0\ => \LOAD_REG_GEN[13].LOAD_REG_I_0\,
\LOAD_REG_GEN[14].LOAD_REG_I\ => \LOAD_REG_GEN[14].LOAD_REG_I\,
\LOAD_REG_GEN[14].LOAD_REG_I_0\ => \LOAD_REG_GEN[14].LOAD_REG_I_0\,
\LOAD_REG_GEN[15].LOAD_REG_I\ => \LOAD_REG_GEN[15].LOAD_REG_I\,
\LOAD_REG_GEN[15].LOAD_REG_I_0\ => \LOAD_REG_GEN[15].LOAD_REG_I_0\,
\LOAD_REG_GEN[16].LOAD_REG_I\ => \LOAD_REG_GEN[16].LOAD_REG_I\,
\LOAD_REG_GEN[16].LOAD_REG_I_0\ => \LOAD_REG_GEN[16].LOAD_REG_I_0\,
\LOAD_REG_GEN[17].LOAD_REG_I\ => \LOAD_REG_GEN[17].LOAD_REG_I\,
\LOAD_REG_GEN[17].LOAD_REG_I_0\ => \LOAD_REG_GEN[17].LOAD_REG_I_0\,
\LOAD_REG_GEN[18].LOAD_REG_I\ => \LOAD_REG_GEN[18].LOAD_REG_I\,
\LOAD_REG_GEN[18].LOAD_REG_I_0\ => \LOAD_REG_GEN[18].LOAD_REG_I_0\,
\LOAD_REG_GEN[19].LOAD_REG_I\ => \LOAD_REG_GEN[19].LOAD_REG_I\,
\LOAD_REG_GEN[19].LOAD_REG_I_0\ => \LOAD_REG_GEN[19].LOAD_REG_I_0\,
\LOAD_REG_GEN[1].LOAD_REG_I\ => \LOAD_REG_GEN[1].LOAD_REG_I\,
\LOAD_REG_GEN[1].LOAD_REG_I_0\ => \LOAD_REG_GEN[1].LOAD_REG_I_0\,
\LOAD_REG_GEN[20].LOAD_REG_I\ => \LOAD_REG_GEN[20].LOAD_REG_I\,
\LOAD_REG_GEN[20].LOAD_REG_I_0\ => \LOAD_REG_GEN[20].LOAD_REG_I_0\,
\LOAD_REG_GEN[21].LOAD_REG_I\ => \LOAD_REG_GEN[21].LOAD_REG_I\,
\LOAD_REG_GEN[21].LOAD_REG_I_0\ => \LOAD_REG_GEN[21].LOAD_REG_I_0\,
\LOAD_REG_GEN[22].LOAD_REG_I\ => \LOAD_REG_GEN[22].LOAD_REG_I\,
\LOAD_REG_GEN[22].LOAD_REG_I_0\ => \LOAD_REG_GEN[22].LOAD_REG_I_0\,
\LOAD_REG_GEN[23].LOAD_REG_I\ => \LOAD_REG_GEN[23].LOAD_REG_I\,
\LOAD_REG_GEN[23].LOAD_REG_I_0\ => \LOAD_REG_GEN[23].LOAD_REG_I_0\,
\LOAD_REG_GEN[24].LOAD_REG_I\ => \LOAD_REG_GEN[24].LOAD_REG_I\,
\LOAD_REG_GEN[24].LOAD_REG_I_0\ => \LOAD_REG_GEN[24].LOAD_REG_I_0\,
\LOAD_REG_GEN[25].LOAD_REG_I\ => \LOAD_REG_GEN[25].LOAD_REG_I\,
\LOAD_REG_GEN[25].LOAD_REG_I_0\ => \LOAD_REG_GEN[25].LOAD_REG_I_0\,
\LOAD_REG_GEN[26].LOAD_REG_I\ => \LOAD_REG_GEN[26].LOAD_REG_I\,
\LOAD_REG_GEN[26].LOAD_REG_I_0\ => \LOAD_REG_GEN[26].LOAD_REG_I_0\,
\LOAD_REG_GEN[27].LOAD_REG_I\ => \LOAD_REG_GEN[27].LOAD_REG_I\,
\LOAD_REG_GEN[27].LOAD_REG_I_0\ => \LOAD_REG_GEN[27].LOAD_REG_I_0\,
\LOAD_REG_GEN[28].LOAD_REG_I\ => \LOAD_REG_GEN[28].LOAD_REG_I\,
\LOAD_REG_GEN[28].LOAD_REG_I_0\ => \LOAD_REG_GEN[28].LOAD_REG_I_0\,
\LOAD_REG_GEN[29].LOAD_REG_I\ => \LOAD_REG_GEN[29].LOAD_REG_I\,
\LOAD_REG_GEN[29].LOAD_REG_I_0\ => \LOAD_REG_GEN[29].LOAD_REG_I_0\,
\LOAD_REG_GEN[2].LOAD_REG_I\ => \LOAD_REG_GEN[2].LOAD_REG_I\,
\LOAD_REG_GEN[2].LOAD_REG_I_0\ => \LOAD_REG_GEN[2].LOAD_REG_I_0\,
\LOAD_REG_GEN[30].LOAD_REG_I\ => \LOAD_REG_GEN[30].LOAD_REG_I\,
\LOAD_REG_GEN[30].LOAD_REG_I_0\ => \LOAD_REG_GEN[30].LOAD_REG_I_0\,
\LOAD_REG_GEN[31].LOAD_REG_I\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\LOAD_REG_GEN[31].LOAD_REG_I_0\ => \LOAD_REG_GEN[31].LOAD_REG_I\,
\LOAD_REG_GEN[31].LOAD_REG_I_1\ => \LOAD_REG_GEN[31].LOAD_REG_I_0\,
\LOAD_REG_GEN[3].LOAD_REG_I\ => \LOAD_REG_GEN[3].LOAD_REG_I\,
\LOAD_REG_GEN[3].LOAD_REG_I_0\ => \LOAD_REG_GEN[3].LOAD_REG_I_0\,
\LOAD_REG_GEN[4].LOAD_REG_I\ => \LOAD_REG_GEN[4].LOAD_REG_I\,
\LOAD_REG_GEN[4].LOAD_REG_I_0\ => \LOAD_REG_GEN[4].LOAD_REG_I_0\,
\LOAD_REG_GEN[5].LOAD_REG_I\ => \LOAD_REG_GEN[5].LOAD_REG_I\,
\LOAD_REG_GEN[5].LOAD_REG_I_0\ => \LOAD_REG_GEN[5].LOAD_REG_I_0\,
\LOAD_REG_GEN[6].LOAD_REG_I\ => \LOAD_REG_GEN[6].LOAD_REG_I\,
\LOAD_REG_GEN[6].LOAD_REG_I_0\ => \LOAD_REG_GEN[6].LOAD_REG_I_0\,
\LOAD_REG_GEN[7].LOAD_REG_I\ => \LOAD_REG_GEN[7].LOAD_REG_I\,
\LOAD_REG_GEN[7].LOAD_REG_I_0\ => \LOAD_REG_GEN[7].LOAD_REG_I_0\,
\LOAD_REG_GEN[8].LOAD_REG_I\ => \LOAD_REG_GEN[8].LOAD_REG_I\,
\LOAD_REG_GEN[8].LOAD_REG_I_0\ => \LOAD_REG_GEN[8].LOAD_REG_I_0\,
\LOAD_REG_GEN[9].LOAD_REG_I\ => \LOAD_REG_GEN[9].LOAD_REG_I\,
\LOAD_REG_GEN[9].LOAD_REG_I_0\ => \LOAD_REG_GEN[9].LOAD_REG_I_0\,
READ_DONE0_I => READ_DONE0_I,
READ_DONE1_I => READ_DONE1_I,
\TCSR0_GENERATE[23].TCSR0_FF_I\ => Bus_RNW_reg,
\TCSR0_GENERATE[23].TCSR0_FF_I_0\ => \TCSR0_GENERATE[23].TCSR0_FF_I\,
\TCSR0_GENERATE[24].TCSR0_FF_I\ => \TCSR0_GENERATE[24].TCSR0_FF_I\,
\TCSR1_GENERATE[23].TCSR1_FF_I\ => \TCSR1_GENERATE[23].TCSR1_FF_I\,
\TCSR1_GENERATE[24].TCSR1_FF_I\ => \TCSR1_GENERATE[24].TCSR1_FF_I\,
bus2ip_reset => bus2ip_reset,
bus2ip_wrce(1 downto 0) => bus2ip_wrce(1 downto 0),
\bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(0),
pair0_Select => pair0_Select,
read_Mux_In(87 downto 0) => read_Mux_In(87 downto 0),
read_done1 => read_done1,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2 downto 0) => s_axi_araddr(2 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
\s_axi_rdata_i_reg[0]_0\ => \s_axi_rdata_i_reg[0]\,
\s_axi_rdata_i_reg[0]_1\ => \s_axi_rdata_i_reg[0]_0\,
\s_axi_rdata_i_reg[10]_0\ => \s_axi_rdata_i_reg[10]\,
\s_axi_rdata_i_reg[11]_0\ => \s_axi_rdata_i_reg[11]\,
\s_axi_rdata_i_reg[12]_0\ => \s_axi_rdata_i_reg[12]\,
\s_axi_rdata_i_reg[13]_0\ => \s_axi_rdata_i_reg[13]\,
\s_axi_rdata_i_reg[14]_0\ => \s_axi_rdata_i_reg[14]\,
\s_axi_rdata_i_reg[15]_0\ => \s_axi_rdata_i_reg[15]\,
\s_axi_rdata_i_reg[16]_0\ => \s_axi_rdata_i_reg[16]\,
\s_axi_rdata_i_reg[17]_0\ => \s_axi_rdata_i_reg[17]\,
\s_axi_rdata_i_reg[18]_0\ => \s_axi_rdata_i_reg[18]\,
\s_axi_rdata_i_reg[19]_0\ => \s_axi_rdata_i_reg[19]\,
\s_axi_rdata_i_reg[20]_0\ => \s_axi_rdata_i_reg[20]\,
\s_axi_rdata_i_reg[21]_0\ => \s_axi_rdata_i_reg[21]\,
\s_axi_rdata_i_reg[22]_0\ => \s_axi_rdata_i_reg[22]\,
\s_axi_rdata_i_reg[23]_0\ => \s_axi_rdata_i_reg[23]\,
\s_axi_rdata_i_reg[24]_0\ => \s_axi_rdata_i_reg[24]\,
\s_axi_rdata_i_reg[25]_0\ => \s_axi_rdata_i_reg[25]\,
\s_axi_rdata_i_reg[26]_0\ => \s_axi_rdata_i_reg[26]\,
\s_axi_rdata_i_reg[27]_0\ => \s_axi_rdata_i_reg[27]\,
\s_axi_rdata_i_reg[28]_0\ => \s_axi_rdata_i_reg[28]\,
\s_axi_rdata_i_reg[29]_0\ => \s_axi_rdata_i_reg[29]\,
\s_axi_rdata_i_reg[30]_0\ => \s_axi_rdata_i_reg[30]\,
\s_axi_rdata_i_reg[31]_0\ => \s_axi_rdata_i_reg[31]\,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_rvalid_i_reg_0 => s_axi_rvalid_i_reg,
s_axi_rvalid_i_reg_1 => s_axi_rvalid_i_reg_0,
s_axi_rvalid_i_reg_2 => s_axi_rvalid_i_reg_1,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer is
port (
capturetrig0 : in STD_LOGIC;
capturetrig1 : in STD_LOGIC;
generateout0 : out STD_LOGIC;
generateout1 : out STD_LOGIC;
pwm0 : out STD_LOGIC;
interrupt : out STD_LOGIC;
freeze : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC
);
attribute C_COUNT_WIDTH : integer;
attribute C_COUNT_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer : entity is 32;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer : entity is "zynq";
attribute C_GEN0_ASSERT : string;
attribute C_GEN0_ASSERT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer : entity is "1'b1";
attribute C_GEN1_ASSERT : string;
attribute C_GEN1_ASSERT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer : entity is "1'b1";
attribute C_ONE_TIMER_ONLY : integer;
attribute C_ONE_TIMER_ONLY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer : entity is 5;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer : entity is 32;
attribute C_TRIG0_ASSERT : string;
attribute C_TRIG0_ASSERT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer : entity is "1'b1";
attribute C_TRIG1_ASSERT : string;
attribute C_TRIG1_ASSERT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer : entity is "1'b1";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer is
signal \<const0>\ : STD_LOGIC;
signal AXI4_LITE_I_n_10 : STD_LOGIC;
signal AXI4_LITE_I_n_100 : STD_LOGIC;
signal AXI4_LITE_I_n_101 : STD_LOGIC;
signal AXI4_LITE_I_n_102 : STD_LOGIC;
signal AXI4_LITE_I_n_103 : STD_LOGIC;
signal AXI4_LITE_I_n_104 : STD_LOGIC;
signal AXI4_LITE_I_n_105 : STD_LOGIC;
signal AXI4_LITE_I_n_106 : STD_LOGIC;
signal AXI4_LITE_I_n_11 : STD_LOGIC;
signal AXI4_LITE_I_n_12 : STD_LOGIC;
signal AXI4_LITE_I_n_13 : STD_LOGIC;
signal AXI4_LITE_I_n_14 : STD_LOGIC;
signal AXI4_LITE_I_n_15 : STD_LOGIC;
signal AXI4_LITE_I_n_16 : STD_LOGIC;
signal AXI4_LITE_I_n_17 : STD_LOGIC;
signal AXI4_LITE_I_n_18 : STD_LOGIC;
signal AXI4_LITE_I_n_19 : STD_LOGIC;
signal AXI4_LITE_I_n_20 : STD_LOGIC;
signal AXI4_LITE_I_n_21 : STD_LOGIC;
signal AXI4_LITE_I_n_22 : STD_LOGIC;
signal AXI4_LITE_I_n_23 : STD_LOGIC;
signal AXI4_LITE_I_n_27 : STD_LOGIC;
signal AXI4_LITE_I_n_28 : STD_LOGIC;
signal AXI4_LITE_I_n_29 : STD_LOGIC;
signal AXI4_LITE_I_n_30 : STD_LOGIC;
signal AXI4_LITE_I_n_31 : STD_LOGIC;
signal AXI4_LITE_I_n_32 : STD_LOGIC;
signal AXI4_LITE_I_n_33 : STD_LOGIC;
signal AXI4_LITE_I_n_34 : STD_LOGIC;
signal AXI4_LITE_I_n_35 : STD_LOGIC;
signal AXI4_LITE_I_n_36 : STD_LOGIC;
signal AXI4_LITE_I_n_37 : STD_LOGIC;
signal AXI4_LITE_I_n_38 : STD_LOGIC;
signal AXI4_LITE_I_n_39 : STD_LOGIC;
signal AXI4_LITE_I_n_4 : STD_LOGIC;
signal AXI4_LITE_I_n_40 : STD_LOGIC;
signal AXI4_LITE_I_n_41 : STD_LOGIC;
signal AXI4_LITE_I_n_42 : STD_LOGIC;
signal AXI4_LITE_I_n_43 : STD_LOGIC;
signal AXI4_LITE_I_n_44 : STD_LOGIC;
signal AXI4_LITE_I_n_45 : STD_LOGIC;
signal AXI4_LITE_I_n_46 : STD_LOGIC;
signal AXI4_LITE_I_n_47 : STD_LOGIC;
signal AXI4_LITE_I_n_48 : STD_LOGIC;
signal AXI4_LITE_I_n_49 : STD_LOGIC;
signal AXI4_LITE_I_n_5 : STD_LOGIC;
signal AXI4_LITE_I_n_50 : STD_LOGIC;
signal AXI4_LITE_I_n_51 : STD_LOGIC;
signal AXI4_LITE_I_n_52 : STD_LOGIC;
signal AXI4_LITE_I_n_53 : STD_LOGIC;
signal AXI4_LITE_I_n_54 : STD_LOGIC;
signal AXI4_LITE_I_n_55 : STD_LOGIC;
signal AXI4_LITE_I_n_56 : STD_LOGIC;
signal AXI4_LITE_I_n_57 : STD_LOGIC;
signal AXI4_LITE_I_n_58 : STD_LOGIC;
signal AXI4_LITE_I_n_59 : STD_LOGIC;
signal AXI4_LITE_I_n_6 : STD_LOGIC;
signal AXI4_LITE_I_n_60 : STD_LOGIC;
signal AXI4_LITE_I_n_65 : STD_LOGIC;
signal AXI4_LITE_I_n_66 : STD_LOGIC;
signal AXI4_LITE_I_n_67 : STD_LOGIC;
signal AXI4_LITE_I_n_68 : STD_LOGIC;
signal AXI4_LITE_I_n_69 : STD_LOGIC;
signal AXI4_LITE_I_n_7 : STD_LOGIC;
signal AXI4_LITE_I_n_70 : STD_LOGIC;
signal AXI4_LITE_I_n_71 : STD_LOGIC;
signal AXI4_LITE_I_n_72 : STD_LOGIC;
signal AXI4_LITE_I_n_73 : STD_LOGIC;
signal AXI4_LITE_I_n_74 : STD_LOGIC;
signal AXI4_LITE_I_n_75 : STD_LOGIC;
signal AXI4_LITE_I_n_76 : STD_LOGIC;
signal AXI4_LITE_I_n_77 : STD_LOGIC;
signal AXI4_LITE_I_n_78 : STD_LOGIC;
signal AXI4_LITE_I_n_79 : STD_LOGIC;
signal AXI4_LITE_I_n_8 : STD_LOGIC;
signal AXI4_LITE_I_n_80 : STD_LOGIC;
signal AXI4_LITE_I_n_81 : STD_LOGIC;
signal AXI4_LITE_I_n_82 : STD_LOGIC;
signal AXI4_LITE_I_n_83 : STD_LOGIC;
signal AXI4_LITE_I_n_84 : STD_LOGIC;
signal AXI4_LITE_I_n_85 : STD_LOGIC;
signal AXI4_LITE_I_n_86 : STD_LOGIC;
signal AXI4_LITE_I_n_87 : STD_LOGIC;
signal AXI4_LITE_I_n_88 : STD_LOGIC;
signal AXI4_LITE_I_n_89 : STD_LOGIC;
signal AXI4_LITE_I_n_9 : STD_LOGIC;
signal AXI4_LITE_I_n_90 : STD_LOGIC;
signal AXI4_LITE_I_n_91 : STD_LOGIC;
signal AXI4_LITE_I_n_92 : STD_LOGIC;
signal AXI4_LITE_I_n_93 : STD_LOGIC;
signal AXI4_LITE_I_n_94 : STD_LOGIC;
signal AXI4_LITE_I_n_95 : STD_LOGIC;
signal AXI4_LITE_I_n_97 : STD_LOGIC;
signal AXI4_LITE_I_n_98 : STD_LOGIC;
signal AXI4_LITE_I_n_99 : STD_LOGIC;
signal \COUNTER_0_I/D\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I/D\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : STD_LOGIC;
signal \TIMER_CONTROL_I/D\ : STD_LOGIC;
signal \TIMER_CONTROL_I/pair0_Select\ : STD_LOGIC;
signal \TIMER_CONTROL_I/read_done1\ : STD_LOGIC;
signal bus2ip_reset : STD_LOGIC;
signal bus2ip_wrce : STD_LOGIC_VECTOR ( 0 to 4 );
signal \bus2ip_wrce__0\ : STD_LOGIC_VECTOR ( 5 to 5 );
signal ip2bus_data : STD_LOGIC_VECTOR ( 0 to 31 );
signal read_Mux_In : STD_LOGIC_VECTOR ( 20 to 191 );
signal \^s_axi_wready\ : STD_LOGIC;
begin
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
AXI4_LITE_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
D(31) => ip2bus_data(0),
D(30) => ip2bus_data(1),
D(29) => ip2bus_data(2),
D(28) => ip2bus_data(3),
D(27) => ip2bus_data(4),
D(26) => ip2bus_data(5),
D(25) => ip2bus_data(6),
D(24) => ip2bus_data(7),
D(23) => ip2bus_data(8),
D(22) => ip2bus_data(9),
D(21) => ip2bus_data(10),
D(20) => ip2bus_data(11),
D(19) => ip2bus_data(12),
D(18) => ip2bus_data(13),
D(17) => ip2bus_data(14),
D(16) => ip2bus_data(15),
D(15) => ip2bus_data(16),
D(14) => ip2bus_data(17),
D(13) => ip2bus_data(18),
D(12) => ip2bus_data(19),
D(11) => ip2bus_data(20),
D(10) => ip2bus_data(21),
D(9) => ip2bus_data(22),
D(8) => ip2bus_data(23),
D(7) => ip2bus_data(24),
D(6) => ip2bus_data(25),
D(5) => ip2bus_data(26),
D(4) => ip2bus_data(27),
D(3) => ip2bus_data(28),
D(2) => ip2bus_data(29),
D(1) => ip2bus_data(30),
D(0) => ip2bus_data(31),
D_0 => \GEN_SECOND_TIMER.COUNTER_1_I/D\,
D_1 => \COUNTER_0_I/D\,
D_2 => \TIMER_CONTROL_I/D\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\LOAD_REG_GEN[10].LOAD_REG_I\ => AXI4_LITE_I_n_51,
\LOAD_REG_GEN[10].LOAD_REG_I_0\ => AXI4_LITE_I_n_86,
\LOAD_REG_GEN[11].LOAD_REG_I\ => AXI4_LITE_I_n_50,
\LOAD_REG_GEN[11].LOAD_REG_I_0\ => AXI4_LITE_I_n_85,
\LOAD_REG_GEN[12].LOAD_REG_I\ => AXI4_LITE_I_n_49,
\LOAD_REG_GEN[12].LOAD_REG_I_0\ => AXI4_LITE_I_n_84,
\LOAD_REG_GEN[13].LOAD_REG_I\ => AXI4_LITE_I_n_48,
\LOAD_REG_GEN[13].LOAD_REG_I_0\ => AXI4_LITE_I_n_83,
\LOAD_REG_GEN[14].LOAD_REG_I\ => AXI4_LITE_I_n_47,
\LOAD_REG_GEN[14].LOAD_REG_I_0\ => AXI4_LITE_I_n_82,
\LOAD_REG_GEN[15].LOAD_REG_I\ => AXI4_LITE_I_n_46,
\LOAD_REG_GEN[15].LOAD_REG_I_0\ => AXI4_LITE_I_n_81,
\LOAD_REG_GEN[16].LOAD_REG_I\ => AXI4_LITE_I_n_45,
\LOAD_REG_GEN[16].LOAD_REG_I_0\ => AXI4_LITE_I_n_80,
\LOAD_REG_GEN[17].LOAD_REG_I\ => AXI4_LITE_I_n_44,
\LOAD_REG_GEN[17].LOAD_REG_I_0\ => AXI4_LITE_I_n_79,
\LOAD_REG_GEN[18].LOAD_REG_I\ => AXI4_LITE_I_n_43,
\LOAD_REG_GEN[18].LOAD_REG_I_0\ => AXI4_LITE_I_n_78,
\LOAD_REG_GEN[19].LOAD_REG_I\ => AXI4_LITE_I_n_42,
\LOAD_REG_GEN[19].LOAD_REG_I_0\ => AXI4_LITE_I_n_77,
\LOAD_REG_GEN[1].LOAD_REG_I\ => AXI4_LITE_I_n_60,
\LOAD_REG_GEN[1].LOAD_REG_I_0\ => AXI4_LITE_I_n_95,
\LOAD_REG_GEN[20].LOAD_REG_I\ => AXI4_LITE_I_n_41,
\LOAD_REG_GEN[20].LOAD_REG_I_0\ => AXI4_LITE_I_n_76,
\LOAD_REG_GEN[21].LOAD_REG_I\ => AXI4_LITE_I_n_40,
\LOAD_REG_GEN[21].LOAD_REG_I_0\ => AXI4_LITE_I_n_75,
\LOAD_REG_GEN[22].LOAD_REG_I\ => AXI4_LITE_I_n_39,
\LOAD_REG_GEN[22].LOAD_REG_I_0\ => AXI4_LITE_I_n_74,
\LOAD_REG_GEN[23].LOAD_REG_I\ => AXI4_LITE_I_n_38,
\LOAD_REG_GEN[23].LOAD_REG_I_0\ => AXI4_LITE_I_n_73,
\LOAD_REG_GEN[24].LOAD_REG_I\ => AXI4_LITE_I_n_37,
\LOAD_REG_GEN[24].LOAD_REG_I_0\ => AXI4_LITE_I_n_72,
\LOAD_REG_GEN[25].LOAD_REG_I\ => AXI4_LITE_I_n_36,
\LOAD_REG_GEN[25].LOAD_REG_I_0\ => AXI4_LITE_I_n_71,
\LOAD_REG_GEN[26].LOAD_REG_I\ => AXI4_LITE_I_n_35,
\LOAD_REG_GEN[26].LOAD_REG_I_0\ => AXI4_LITE_I_n_70,
\LOAD_REG_GEN[27].LOAD_REG_I\ => AXI4_LITE_I_n_34,
\LOAD_REG_GEN[27].LOAD_REG_I_0\ => AXI4_LITE_I_n_69,
\LOAD_REG_GEN[28].LOAD_REG_I\ => AXI4_LITE_I_n_33,
\LOAD_REG_GEN[28].LOAD_REG_I_0\ => AXI4_LITE_I_n_68,
\LOAD_REG_GEN[29].LOAD_REG_I\ => AXI4_LITE_I_n_32,
\LOAD_REG_GEN[29].LOAD_REG_I_0\ => AXI4_LITE_I_n_67,
\LOAD_REG_GEN[2].LOAD_REG_I\ => AXI4_LITE_I_n_59,
\LOAD_REG_GEN[2].LOAD_REG_I_0\ => AXI4_LITE_I_n_94,
\LOAD_REG_GEN[30].LOAD_REG_I\ => AXI4_LITE_I_n_31,
\LOAD_REG_GEN[30].LOAD_REG_I_0\ => AXI4_LITE_I_n_66,
\LOAD_REG_GEN[31].LOAD_REG_I\ => AXI4_LITE_I_n_30,
\LOAD_REG_GEN[31].LOAD_REG_I_0\ => AXI4_LITE_I_n_65,
\LOAD_REG_GEN[3].LOAD_REG_I\ => AXI4_LITE_I_n_58,
\LOAD_REG_GEN[3].LOAD_REG_I_0\ => AXI4_LITE_I_n_93,
\LOAD_REG_GEN[4].LOAD_REG_I\ => AXI4_LITE_I_n_57,
\LOAD_REG_GEN[4].LOAD_REG_I_0\ => AXI4_LITE_I_n_92,
\LOAD_REG_GEN[5].LOAD_REG_I\ => AXI4_LITE_I_n_56,
\LOAD_REG_GEN[5].LOAD_REG_I_0\ => AXI4_LITE_I_n_91,
\LOAD_REG_GEN[6].LOAD_REG_I\ => AXI4_LITE_I_n_55,
\LOAD_REG_GEN[6].LOAD_REG_I_0\ => AXI4_LITE_I_n_90,
\LOAD_REG_GEN[7].LOAD_REG_I\ => AXI4_LITE_I_n_54,
\LOAD_REG_GEN[7].LOAD_REG_I_0\ => AXI4_LITE_I_n_89,
\LOAD_REG_GEN[8].LOAD_REG_I\ => AXI4_LITE_I_n_53,
\LOAD_REG_GEN[8].LOAD_REG_I_0\ => AXI4_LITE_I_n_88,
\LOAD_REG_GEN[9].LOAD_REG_I\ => AXI4_LITE_I_n_52,
\LOAD_REG_GEN[9].LOAD_REG_I_0\ => AXI4_LITE_I_n_87,
READ_DONE0_I => AXI4_LITE_I_n_105,
READ_DONE1_I => AXI4_LITE_I_n_106,
\TCSR0_GENERATE[23].TCSR0_FF_I\ => AXI4_LITE_I_n_100,
\TCSR0_GENERATE[24].TCSR0_FF_I\ => AXI4_LITE_I_n_28,
\TCSR1_GENERATE[23].TCSR1_FF_I\ => AXI4_LITE_I_n_101,
\TCSR1_GENERATE[24].TCSR1_FF_I\ => AXI4_LITE_I_n_29,
bus2ip_reset => bus2ip_reset,
bus2ip_wrce(1) => bus2ip_wrce(0),
bus2ip_wrce(0) => bus2ip_wrce(4),
\bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(5),
pair0_Select => \TIMER_CONTROL_I/pair0_Select\,
read_Mux_In(87) => read_Mux_In(20),
read_Mux_In(86) => read_Mux_In(24),
read_Mux_In(85) => read_Mux_In(56),
read_Mux_In(84) => read_Mux_In(64),
read_Mux_In(83) => read_Mux_In(65),
read_Mux_In(82) => read_Mux_In(66),
read_Mux_In(81) => read_Mux_In(67),
read_Mux_In(80) => read_Mux_In(68),
read_Mux_In(79) => read_Mux_In(69),
read_Mux_In(78) => read_Mux_In(70),
read_Mux_In(77) => read_Mux_In(71),
read_Mux_In(76) => read_Mux_In(72),
read_Mux_In(75) => read_Mux_In(73),
read_Mux_In(74) => read_Mux_In(74),
read_Mux_In(73) => read_Mux_In(75),
read_Mux_In(72) => read_Mux_In(76),
read_Mux_In(71) => read_Mux_In(77),
read_Mux_In(70) => read_Mux_In(78),
read_Mux_In(69) => read_Mux_In(79),
read_Mux_In(68) => read_Mux_In(80),
read_Mux_In(67) => read_Mux_In(81),
read_Mux_In(66) => read_Mux_In(82),
read_Mux_In(65) => read_Mux_In(83),
read_Mux_In(64) => read_Mux_In(84),
read_Mux_In(63) => read_Mux_In(128),
read_Mux_In(62) => read_Mux_In(129),
read_Mux_In(61) => read_Mux_In(130),
read_Mux_In(60) => read_Mux_In(131),
read_Mux_In(59) => read_Mux_In(132),
read_Mux_In(58) => read_Mux_In(133),
read_Mux_In(57) => read_Mux_In(134),
read_Mux_In(56) => read_Mux_In(135),
read_Mux_In(55) => read_Mux_In(136),
read_Mux_In(54) => read_Mux_In(137),
read_Mux_In(53) => read_Mux_In(138),
read_Mux_In(52) => read_Mux_In(139),
read_Mux_In(51) => read_Mux_In(140),
read_Mux_In(50) => read_Mux_In(141),
read_Mux_In(49) => read_Mux_In(142),
read_Mux_In(48) => read_Mux_In(143),
read_Mux_In(47) => read_Mux_In(144),
read_Mux_In(46) => read_Mux_In(145),
read_Mux_In(45) => read_Mux_In(146),
read_Mux_In(44) => read_Mux_In(147),
read_Mux_In(43) => read_Mux_In(148),
read_Mux_In(42) => read_Mux_In(149),
read_Mux_In(41) => read_Mux_In(150),
read_Mux_In(40) => read_Mux_In(151),
read_Mux_In(39) => read_Mux_In(152),
read_Mux_In(38) => read_Mux_In(153),
read_Mux_In(37) => read_Mux_In(154),
read_Mux_In(36) => read_Mux_In(155),
read_Mux_In(35) => read_Mux_In(156),
read_Mux_In(34) => read_Mux_In(157),
read_Mux_In(33) => read_Mux_In(158),
read_Mux_In(32) => read_Mux_In(159),
read_Mux_In(31) => read_Mux_In(160),
read_Mux_In(30) => read_Mux_In(161),
read_Mux_In(29) => read_Mux_In(162),
read_Mux_In(28) => read_Mux_In(163),
read_Mux_In(27) => read_Mux_In(164),
read_Mux_In(26) => read_Mux_In(165),
read_Mux_In(25) => read_Mux_In(166),
read_Mux_In(24) => read_Mux_In(167),
read_Mux_In(23) => read_Mux_In(168),
read_Mux_In(22) => read_Mux_In(169),
read_Mux_In(21) => read_Mux_In(170),
read_Mux_In(20) => read_Mux_In(171),
read_Mux_In(19) => read_Mux_In(172),
read_Mux_In(18) => read_Mux_In(173),
read_Mux_In(17) => read_Mux_In(174),
read_Mux_In(16) => read_Mux_In(175),
read_Mux_In(15) => read_Mux_In(176),
read_Mux_In(14) => read_Mux_In(177),
read_Mux_In(13) => read_Mux_In(178),
read_Mux_In(12) => read_Mux_In(179),
read_Mux_In(11) => read_Mux_In(180),
read_Mux_In(10) => read_Mux_In(181),
read_Mux_In(9) => read_Mux_In(182),
read_Mux_In(8) => read_Mux_In(183),
read_Mux_In(7) => read_Mux_In(184),
read_Mux_In(6) => read_Mux_In(185),
read_Mux_In(5) => read_Mux_In(186),
read_Mux_In(4) => read_Mux_In(187),
read_Mux_In(3) => read_Mux_In(188),
read_Mux_In(2) => read_Mux_In(189),
read_Mux_In(1) => read_Mux_In(190),
read_Mux_In(0) => read_Mux_In(191),
read_done1 => \TIMER_CONTROL_I/read_done1\,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2 downto 0) => s_axi_araddr(4 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(4 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
\s_axi_rdata_i_reg[0]\ => AXI4_LITE_I_n_103,
\s_axi_rdata_i_reg[0]_0\ => AXI4_LITE_I_n_104,
\s_axi_rdata_i_reg[10]\ => AXI4_LITE_I_n_102,
\s_axi_rdata_i_reg[11]\ => AXI4_LITE_I_n_27,
\s_axi_rdata_i_reg[12]\ => AXI4_LITE_I_n_4,
\s_axi_rdata_i_reg[13]\ => AXI4_LITE_I_n_5,
\s_axi_rdata_i_reg[14]\ => AXI4_LITE_I_n_6,
\s_axi_rdata_i_reg[15]\ => AXI4_LITE_I_n_7,
\s_axi_rdata_i_reg[16]\ => AXI4_LITE_I_n_8,
\s_axi_rdata_i_reg[17]\ => AXI4_LITE_I_n_9,
\s_axi_rdata_i_reg[18]\ => AXI4_LITE_I_n_10,
\s_axi_rdata_i_reg[19]\ => AXI4_LITE_I_n_11,
\s_axi_rdata_i_reg[20]\ => AXI4_LITE_I_n_12,
\s_axi_rdata_i_reg[21]\ => AXI4_LITE_I_n_13,
\s_axi_rdata_i_reg[22]\ => AXI4_LITE_I_n_14,
\s_axi_rdata_i_reg[23]\ => AXI4_LITE_I_n_15,
\s_axi_rdata_i_reg[24]\ => AXI4_LITE_I_n_16,
\s_axi_rdata_i_reg[25]\ => AXI4_LITE_I_n_17,
\s_axi_rdata_i_reg[26]\ => AXI4_LITE_I_n_18,
\s_axi_rdata_i_reg[27]\ => AXI4_LITE_I_n_19,
\s_axi_rdata_i_reg[28]\ => AXI4_LITE_I_n_20,
\s_axi_rdata_i_reg[29]\ => AXI4_LITE_I_n_21,
\s_axi_rdata_i_reg[30]\ => AXI4_LITE_I_n_22,
\s_axi_rdata_i_reg[31]\ => AXI4_LITE_I_n_23,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_rvalid_i_reg => AXI4_LITE_I_n_97,
s_axi_rvalid_i_reg_0 => AXI4_LITE_I_n_98,
s_axi_rvalid_i_reg_1 => AXI4_LITE_I_n_99,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => \^s_axi_wready\,
s_axi_wvalid => s_axi_wvalid
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
TC_CORE_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_tc_core
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
Bus_RNW_reg_reg => AXI4_LITE_I_n_23,
Bus_RNW_reg_reg_0 => AXI4_LITE_I_n_22,
Bus_RNW_reg_reg_1 => AXI4_LITE_I_n_21,
Bus_RNW_reg_reg_10 => AXI4_LITE_I_n_12,
Bus_RNW_reg_reg_11 => AXI4_LITE_I_n_11,
Bus_RNW_reg_reg_12 => AXI4_LITE_I_n_10,
Bus_RNW_reg_reg_13 => AXI4_LITE_I_n_9,
Bus_RNW_reg_reg_14 => AXI4_LITE_I_n_8,
Bus_RNW_reg_reg_15 => AXI4_LITE_I_n_7,
Bus_RNW_reg_reg_16 => AXI4_LITE_I_n_6,
Bus_RNW_reg_reg_17 => AXI4_LITE_I_n_5,
Bus_RNW_reg_reg_18 => AXI4_LITE_I_n_4,
Bus_RNW_reg_reg_2 => AXI4_LITE_I_n_20,
Bus_RNW_reg_reg_3 => AXI4_LITE_I_n_19,
Bus_RNW_reg_reg_4 => AXI4_LITE_I_n_18,
Bus_RNW_reg_reg_5 => AXI4_LITE_I_n_17,
Bus_RNW_reg_reg_6 => AXI4_LITE_I_n_16,
Bus_RNW_reg_reg_7 => AXI4_LITE_I_n_15,
Bus_RNW_reg_reg_8 => AXI4_LITE_I_n_14,
Bus_RNW_reg_reg_9 => AXI4_LITE_I_n_13,
D(31) => ip2bus_data(0),
D(30) => ip2bus_data(1),
D(29) => ip2bus_data(2),
D(28) => ip2bus_data(3),
D(27) => ip2bus_data(4),
D(26) => ip2bus_data(5),
D(25) => ip2bus_data(6),
D(24) => ip2bus_data(7),
D(23) => ip2bus_data(8),
D(22) => ip2bus_data(9),
D(21) => ip2bus_data(10),
D(20) => ip2bus_data(11),
D(19) => ip2bus_data(12),
D(18) => ip2bus_data(13),
D(17) => ip2bus_data(14),
D(16) => ip2bus_data(15),
D(15) => ip2bus_data(16),
D(14) => ip2bus_data(17),
D(13) => ip2bus_data(18),
D(12) => ip2bus_data(19),
D(11) => ip2bus_data(20),
D(10) => ip2bus_data(21),
D(9) => ip2bus_data(22),
D(8) => ip2bus_data(23),
D(7) => ip2bus_data(24),
D(6) => ip2bus_data(25),
D(5) => ip2bus_data(26),
D(4) => ip2bus_data(27),
D(3) => ip2bus_data(28),
D(2) => ip2bus_data(29),
D(1) => ip2bus_data(30),
D(0) => ip2bus_data(31),
D_0 => \TIMER_CONTROL_I/D\,
D_1 => \COUNTER_0_I/D\,
D_2 => \GEN_SECOND_TIMER.COUNTER_1_I/D\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => AXI4_LITE_I_n_100,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ => AXI4_LITE_I_n_102,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => AXI4_LITE_I_n_95,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ => AXI4_LITE_I_n_94,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\ => AXI4_LITE_I_n_93,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\ => AXI4_LITE_I_n_84,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\ => AXI4_LITE_I_n_83,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\ => AXI4_LITE_I_n_82,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\ => AXI4_LITE_I_n_81,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\ => AXI4_LITE_I_n_80,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\ => AXI4_LITE_I_n_79,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\ => AXI4_LITE_I_n_78,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\ => AXI4_LITE_I_n_77,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\ => AXI4_LITE_I_n_76,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\ => AXI4_LITE_I_n_75,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\ => AXI4_LITE_I_n_92,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\ => AXI4_LITE_I_n_74,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\ => AXI4_LITE_I_n_73,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\ => AXI4_LITE_I_n_72,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\ => AXI4_LITE_I_n_71,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\ => AXI4_LITE_I_n_70,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\ => AXI4_LITE_I_n_69,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\ => AXI4_LITE_I_n_68,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\ => AXI4_LITE_I_n_67,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\ => AXI4_LITE_I_n_66,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\ => AXI4_LITE_I_n_65,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\ => AXI4_LITE_I_n_91,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_30\ => AXI4_LITE_I_n_105,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_31\ => AXI4_LITE_I_n_97,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\ => AXI4_LITE_I_n_90,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\ => AXI4_LITE_I_n_89,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\ => AXI4_LITE_I_n_88,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\ => AXI4_LITE_I_n_87,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\ => AXI4_LITE_I_n_86,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\ => AXI4_LITE_I_n_85,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ => AXI4_LITE_I_n_99,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => AXI4_LITE_I_n_101,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ => AXI4_LITE_I_n_98,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ => AXI4_LITE_I_n_106,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0\ => AXI4_LITE_I_n_103,
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ => AXI4_LITE_I_n_104,
\INFERRED_GEN.icount_out_reg[0]\(87) => read_Mux_In(20),
\INFERRED_GEN.icount_out_reg[0]\(86) => read_Mux_In(24),
\INFERRED_GEN.icount_out_reg[0]\(85) => read_Mux_In(56),
\INFERRED_GEN.icount_out_reg[0]\(84) => read_Mux_In(64),
\INFERRED_GEN.icount_out_reg[0]\(83) => read_Mux_In(65),
\INFERRED_GEN.icount_out_reg[0]\(82) => read_Mux_In(66),
\INFERRED_GEN.icount_out_reg[0]\(81) => read_Mux_In(67),
\INFERRED_GEN.icount_out_reg[0]\(80) => read_Mux_In(68),
\INFERRED_GEN.icount_out_reg[0]\(79) => read_Mux_In(69),
\INFERRED_GEN.icount_out_reg[0]\(78) => read_Mux_In(70),
\INFERRED_GEN.icount_out_reg[0]\(77) => read_Mux_In(71),
\INFERRED_GEN.icount_out_reg[0]\(76) => read_Mux_In(72),
\INFERRED_GEN.icount_out_reg[0]\(75) => read_Mux_In(73),
\INFERRED_GEN.icount_out_reg[0]\(74) => read_Mux_In(74),
\INFERRED_GEN.icount_out_reg[0]\(73) => read_Mux_In(75),
\INFERRED_GEN.icount_out_reg[0]\(72) => read_Mux_In(76),
\INFERRED_GEN.icount_out_reg[0]\(71) => read_Mux_In(77),
\INFERRED_GEN.icount_out_reg[0]\(70) => read_Mux_In(78),
\INFERRED_GEN.icount_out_reg[0]\(69) => read_Mux_In(79),
\INFERRED_GEN.icount_out_reg[0]\(68) => read_Mux_In(80),
\INFERRED_GEN.icount_out_reg[0]\(67) => read_Mux_In(81),
\INFERRED_GEN.icount_out_reg[0]\(66) => read_Mux_In(82),
\INFERRED_GEN.icount_out_reg[0]\(65) => read_Mux_In(83),
\INFERRED_GEN.icount_out_reg[0]\(64) => read_Mux_In(84),
\INFERRED_GEN.icount_out_reg[0]\(63) => read_Mux_In(128),
\INFERRED_GEN.icount_out_reg[0]\(62) => read_Mux_In(129),
\INFERRED_GEN.icount_out_reg[0]\(61) => read_Mux_In(130),
\INFERRED_GEN.icount_out_reg[0]\(60) => read_Mux_In(131),
\INFERRED_GEN.icount_out_reg[0]\(59) => read_Mux_In(132),
\INFERRED_GEN.icount_out_reg[0]\(58) => read_Mux_In(133),
\INFERRED_GEN.icount_out_reg[0]\(57) => read_Mux_In(134),
\INFERRED_GEN.icount_out_reg[0]\(56) => read_Mux_In(135),
\INFERRED_GEN.icount_out_reg[0]\(55) => read_Mux_In(136),
\INFERRED_GEN.icount_out_reg[0]\(54) => read_Mux_In(137),
\INFERRED_GEN.icount_out_reg[0]\(53) => read_Mux_In(138),
\INFERRED_GEN.icount_out_reg[0]\(52) => read_Mux_In(139),
\INFERRED_GEN.icount_out_reg[0]\(51) => read_Mux_In(140),
\INFERRED_GEN.icount_out_reg[0]\(50) => read_Mux_In(141),
\INFERRED_GEN.icount_out_reg[0]\(49) => read_Mux_In(142),
\INFERRED_GEN.icount_out_reg[0]\(48) => read_Mux_In(143),
\INFERRED_GEN.icount_out_reg[0]\(47) => read_Mux_In(144),
\INFERRED_GEN.icount_out_reg[0]\(46) => read_Mux_In(145),
\INFERRED_GEN.icount_out_reg[0]\(45) => read_Mux_In(146),
\INFERRED_GEN.icount_out_reg[0]\(44) => read_Mux_In(147),
\INFERRED_GEN.icount_out_reg[0]\(43) => read_Mux_In(148),
\INFERRED_GEN.icount_out_reg[0]\(42) => read_Mux_In(149),
\INFERRED_GEN.icount_out_reg[0]\(41) => read_Mux_In(150),
\INFERRED_GEN.icount_out_reg[0]\(40) => read_Mux_In(151),
\INFERRED_GEN.icount_out_reg[0]\(39) => read_Mux_In(152),
\INFERRED_GEN.icount_out_reg[0]\(38) => read_Mux_In(153),
\INFERRED_GEN.icount_out_reg[0]\(37) => read_Mux_In(154),
\INFERRED_GEN.icount_out_reg[0]\(36) => read_Mux_In(155),
\INFERRED_GEN.icount_out_reg[0]\(35) => read_Mux_In(156),
\INFERRED_GEN.icount_out_reg[0]\(34) => read_Mux_In(157),
\INFERRED_GEN.icount_out_reg[0]\(33) => read_Mux_In(158),
\INFERRED_GEN.icount_out_reg[0]\(32) => read_Mux_In(159),
\INFERRED_GEN.icount_out_reg[0]\(31) => read_Mux_In(160),
\INFERRED_GEN.icount_out_reg[0]\(30) => read_Mux_In(161),
\INFERRED_GEN.icount_out_reg[0]\(29) => read_Mux_In(162),
\INFERRED_GEN.icount_out_reg[0]\(28) => read_Mux_In(163),
\INFERRED_GEN.icount_out_reg[0]\(27) => read_Mux_In(164),
\INFERRED_GEN.icount_out_reg[0]\(26) => read_Mux_In(165),
\INFERRED_GEN.icount_out_reg[0]\(25) => read_Mux_In(166),
\INFERRED_GEN.icount_out_reg[0]\(24) => read_Mux_In(167),
\INFERRED_GEN.icount_out_reg[0]\(23) => read_Mux_In(168),
\INFERRED_GEN.icount_out_reg[0]\(22) => read_Mux_In(169),
\INFERRED_GEN.icount_out_reg[0]\(21) => read_Mux_In(170),
\INFERRED_GEN.icount_out_reg[0]\(20) => read_Mux_In(171),
\INFERRED_GEN.icount_out_reg[0]\(19) => read_Mux_In(172),
\INFERRED_GEN.icount_out_reg[0]\(18) => read_Mux_In(173),
\INFERRED_GEN.icount_out_reg[0]\(17) => read_Mux_In(174),
\INFERRED_GEN.icount_out_reg[0]\(16) => read_Mux_In(175),
\INFERRED_GEN.icount_out_reg[0]\(15) => read_Mux_In(176),
\INFERRED_GEN.icount_out_reg[0]\(14) => read_Mux_In(177),
\INFERRED_GEN.icount_out_reg[0]\(13) => read_Mux_In(178),
\INFERRED_GEN.icount_out_reg[0]\(12) => read_Mux_In(179),
\INFERRED_GEN.icount_out_reg[0]\(11) => read_Mux_In(180),
\INFERRED_GEN.icount_out_reg[0]\(10) => read_Mux_In(181),
\INFERRED_GEN.icount_out_reg[0]\(9) => read_Mux_In(182),
\INFERRED_GEN.icount_out_reg[0]\(8) => read_Mux_In(183),
\INFERRED_GEN.icount_out_reg[0]\(7) => read_Mux_In(184),
\INFERRED_GEN.icount_out_reg[0]\(6) => read_Mux_In(185),
\INFERRED_GEN.icount_out_reg[0]\(5) => read_Mux_In(186),
\INFERRED_GEN.icount_out_reg[0]\(4) => read_Mux_In(187),
\INFERRED_GEN.icount_out_reg[0]\(3) => read_Mux_In(188),
\INFERRED_GEN.icount_out_reg[0]\(2) => read_Mux_In(189),
\INFERRED_GEN.icount_out_reg[0]\(1) => read_Mux_In(190),
\INFERRED_GEN.icount_out_reg[0]\(0) => read_Mux_In(191),
\INFERRED_GEN.icount_out_reg[0]_0\ => AXI4_LITE_I_n_30,
\INFERRED_GEN.icount_out_reg[10]\ => AXI4_LITE_I_n_40,
\INFERRED_GEN.icount_out_reg[11]\ => AXI4_LITE_I_n_41,
\INFERRED_GEN.icount_out_reg[12]\ => AXI4_LITE_I_n_42,
\INFERRED_GEN.icount_out_reg[13]\ => AXI4_LITE_I_n_43,
\INFERRED_GEN.icount_out_reg[14]\ => AXI4_LITE_I_n_44,
\INFERRED_GEN.icount_out_reg[15]\ => AXI4_LITE_I_n_45,
\INFERRED_GEN.icount_out_reg[16]\ => AXI4_LITE_I_n_46,
\INFERRED_GEN.icount_out_reg[17]\ => AXI4_LITE_I_n_47,
\INFERRED_GEN.icount_out_reg[18]\ => AXI4_LITE_I_n_48,
\INFERRED_GEN.icount_out_reg[19]\ => AXI4_LITE_I_n_49,
\INFERRED_GEN.icount_out_reg[1]\ => AXI4_LITE_I_n_31,
\INFERRED_GEN.icount_out_reg[20]\ => AXI4_LITE_I_n_50,
\INFERRED_GEN.icount_out_reg[21]\ => AXI4_LITE_I_n_51,
\INFERRED_GEN.icount_out_reg[22]\ => AXI4_LITE_I_n_52,
\INFERRED_GEN.icount_out_reg[23]\ => AXI4_LITE_I_n_53,
\INFERRED_GEN.icount_out_reg[24]\ => AXI4_LITE_I_n_54,
\INFERRED_GEN.icount_out_reg[25]\ => AXI4_LITE_I_n_55,
\INFERRED_GEN.icount_out_reg[26]\ => AXI4_LITE_I_n_56,
\INFERRED_GEN.icount_out_reg[27]\ => AXI4_LITE_I_n_57,
\INFERRED_GEN.icount_out_reg[28]\ => AXI4_LITE_I_n_58,
\INFERRED_GEN.icount_out_reg[29]\ => AXI4_LITE_I_n_59,
\INFERRED_GEN.icount_out_reg[2]\ => AXI4_LITE_I_n_32,
\INFERRED_GEN.icount_out_reg[30]\ => AXI4_LITE_I_n_60,
\INFERRED_GEN.icount_out_reg[3]\ => AXI4_LITE_I_n_33,
\INFERRED_GEN.icount_out_reg[4]\ => AXI4_LITE_I_n_34,
\INFERRED_GEN.icount_out_reg[5]\ => AXI4_LITE_I_n_35,
\INFERRED_GEN.icount_out_reg[6]\ => AXI4_LITE_I_n_36,
\INFERRED_GEN.icount_out_reg[7]\ => AXI4_LITE_I_n_37,
\INFERRED_GEN.icount_out_reg[8]\ => AXI4_LITE_I_n_38,
\INFERRED_GEN.icount_out_reg[9]\ => AXI4_LITE_I_n_39,
\LOAD_REG_GEN[20].LOAD_REG_I\ => AXI4_LITE_I_n_27,
\TCSR0_GENERATE[24].TCSR0_FF_I\ => AXI4_LITE_I_n_28,
\TCSR1_GENERATE[24].TCSR1_FF_I\ => AXI4_LITE_I_n_29,
bus2ip_reset => bus2ip_reset,
bus2ip_wrce(1) => bus2ip_wrce(0),
bus2ip_wrce(0) => bus2ip_wrce(4),
\bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(5),
capturetrig0 => capturetrig0,
capturetrig1 => capturetrig1,
freeze => freeze,
generateout0 => generateout0,
generateout1 => generateout1,
interrupt => interrupt,
pair0_Select => \TIMER_CONTROL_I/pair0_Select\,
pwm0 => pwm0,
read_done1 => \TIMER_CONTROL_I/read_done1\,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_wdata(9 downto 7) => s_axi_wdata(11 downto 9),
s_axi_wdata(6 downto 0) => s_axi_wdata(6 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
capturetrig0 : in STD_LOGIC;
capturetrig1 : in STD_LOGIC;
generateout0 : out STD_LOGIC;
generateout1 : out STD_LOGIC;
pwm0 : out STD_LOGIC;
interrupt : out STD_LOGIC;
freeze : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zqynq_lab_1_design_axi_timer_0_1,axi_timer,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_timer,Vivado 2017.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute C_COUNT_WIDTH : integer;
attribute C_COUNT_WIDTH of U0 : label is 32;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_GEN0_ASSERT : string;
attribute C_GEN0_ASSERT of U0 : label is "1'b1";
attribute C_GEN1_ASSERT : string;
attribute C_GEN1_ASSERT of U0 : label is "1'b1";
attribute C_ONE_TIMER_ONLY : integer;
attribute C_ONE_TIMER_ONLY of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 5;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TRIG0_ASSERT : string;
attribute C_TRIG0_ASSERT of U0 : label is "1'b1";
attribute C_TRIG1_ASSERT : string;
attribute C_TRIG1_ASSERT of U0 : label is "1'b1";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_timer
port map (
capturetrig0 => capturetrig0,
capturetrig1 => capturetrig1,
freeze => freeze,
generateout0 => generateout0,
generateout1 => generateout1,
interrupt => interrupt,
pwm0 => pwm0,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(4 downto 0) => s_axi_araddr(4 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(4 downto 0) => s_axi_awaddr(4 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
mit
|
MarkBlanco/FPGA_Sandbox
|
RecComp/Lab3/lab3_project.xpr/project_1/project_1.srcs/sources_1/bd/design_1/ipshared/7b8d/hdl/xbip_dsp48_addsub_v3_0_vh_rfs.vhd
|
7
|
95183
|
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`protect end_protected
|
mit
|
VerkhovtsovPavel/BSUIR_Labs
|
Master/POCP/My_Designs/GPR/src/TestBench/mrom_TB.vhd
|
1
|
1373
|
library gpr;
use gpr.OneHotGPR.all;
library ieee;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity mrom_tb is
end mrom_tb;
architecture TB_ARCHITECTURE of mrom_tb is
-- Component declaration of the tested unit
component mrom
port(
RE : in STD_LOGIC;
ADDR : in mem_addr;
DOUT : out command );
end component;
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal RE : STD_LOGIC;
signal ADDR : mem_addr;
-- Observed signals - signals mapped to the output ports of tested entity
signal DOUT : command;
constant WAIT_period: time := 10 ns;
begin
-- Unit Under Test port map
UUT : mrom
port map (
RE => RE,
ADDR => ADDR,
DOUT => DOUT
);
-- Add your stimulus here ...
main: process
begin
re <= '0';
addr <= "00010";
wait for 1 * WAIT_period;
re <= '1';
wait for 1 * WAIT_period;
addr <= "00000";
re <= '1';
wait for 1 * WAIT_period;
re <= '0';
wait for 100 * WAIT_period;
wait;
end process;
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_mrom of mrom_tb is
for TB_ARCHITECTURE
for UUT : mrom
use entity work.mrom(beh_gpr);
end for;
end for;
end TESTBENCH_FOR_mrom;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_clock_splitter_1_0/sim/system_clock_splitter_1_0.vhd
|
2
|
3120
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:clock_splitter:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_clock_splitter_1_0 IS
PORT (
clk_in : IN STD_LOGIC;
latch_edge : IN STD_LOGIC;
clk_out : OUT STD_LOGIC
);
END system_clock_splitter_1_0;
ARCHITECTURE system_clock_splitter_1_0_arch OF system_clock_splitter_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_clock_splitter_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT clock_splitter IS
PORT (
clk_in : IN STD_LOGIC;
latch_edge : IN STD_LOGIC;
clk_out : OUT STD_LOGIC
);
END COMPONENT clock_splitter;
BEGIN
U0 : clock_splitter
PORT MAP (
clk_in => clk_in,
latch_edge => latch_edge,
clk_out => clk_out
);
END system_clock_splitter_1_0_arch;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_vga_gaussian_blur_0_0/synth/system_vga_gaussian_blur_0_0.vhd
|
1
|
4598
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_gaussian_blur:1.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_gaussian_blur_0_0 IS
PORT (
clk_25 : IN STD_LOGIC;
hsync_in : IN STD_LOGIC;
vsync_in : IN STD_LOGIC;
rgb_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
hsync_out : OUT STD_LOGIC;
vsync_out : OUT STD_LOGIC;
rgb_blur : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_pass : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_gaussian_blur_0_0;
ARCHITECTURE system_vga_gaussian_blur_0_0_arch OF system_vga_gaussian_blur_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_gaussian_blur_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_gaussian_blur IS
GENERIC (
H_SIZE : INTEGER;
H_DELAY : INTEGER;
KERNEL : INTEGER
);
PORT (
clk_25 : IN STD_LOGIC;
hsync_in : IN STD_LOGIC;
vsync_in : IN STD_LOGIC;
rgb_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
hsync_out : OUT STD_LOGIC;
vsync_out : OUT STD_LOGIC;
rgb_blur : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_pass : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_gaussian_blur;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_gaussian_blur_0_0_arch: ARCHITECTURE IS "vga_gaussian_blur,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_gaussian_blur_0_0_arch : ARCHITECTURE IS "system_vga_gaussian_blur_0_0,vga_gaussian_blur,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_gaussian_blur_0_0_arch: ARCHITECTURE IS "system_vga_gaussian_blur_0_0,vga_gaussian_blur,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_gaussian_blur,x_ipVersion=1.0,x_ipCoreRevision=9,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,H_SIZE=640,H_DELAY=160,KERNEL=3}";
BEGIN
U0 : vga_gaussian_blur
GENERIC MAP (
H_SIZE => 640,
H_DELAY => 160,
KERNEL => 3
)
PORT MAP (
clk_25 => clk_25,
hsync_in => hsync_in,
vsync_in => vsync_in,
rgb_in => rgb_in,
hsync_out => hsync_out,
vsync_out => vsync_out,
rgb_blur => rgb_blur,
rgb_pass => rgb_pass
);
END system_vga_gaussian_blur_0_0_arch;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_clock_splitter_0_0/synth/system_clock_splitter_0_0.vhd
|
5
|
3769
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:clock_splitter:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_clock_splitter_0_0 IS
PORT (
clk_in : IN STD_LOGIC;
latch_edge : IN STD_LOGIC;
clk_out : OUT STD_LOGIC
);
END system_clock_splitter_0_0;
ARCHITECTURE system_clock_splitter_0_0_arch OF system_clock_splitter_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_clock_splitter_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT clock_splitter IS
PORT (
clk_in : IN STD_LOGIC;
latch_edge : IN STD_LOGIC;
clk_out : OUT STD_LOGIC
);
END COMPONENT clock_splitter;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_clock_splitter_0_0_arch: ARCHITECTURE IS "clock_splitter,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_clock_splitter_0_0_arch : ARCHITECTURE IS "system_clock_splitter_0_0,clock_splitter,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_clock_splitter_0_0_arch: ARCHITECTURE IS "system_clock_splitter_0_0,clock_splitter,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=clock_splitter,x_ipVersion=1.0,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : clock_splitter
PORT MAP (
clk_in => clk_in,
latch_edge => latch_edge,
clk_out => clk_out
);
END system_clock_splitter_0_0_arch;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ipshared/bf57/ov7670_controller.vhd
|
6
|
2356
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: Controller for the OV760 camera - transfers registers to the
-- camera over an I2C like bus
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ov7670_controller is
port(
clk: in std_logic;
resend: in std_logic;
config_finished : out std_logic;
sioc: out std_logic;
siod: inout std_logic;
reset: out std_logic;
pwdn: out std_logic;
xclk: out std_logic
);
end ov7670_controller;
architecture Structural of ov7670_controller is
component ov7670_registers is
port(
clk: in std_logic;
resend: in std_logic;
advance: in std_logic;
command: out std_logic_vector(15 downto 0);
finished: out std_logic
);
end component;
component i2c_sender is
port (
clk: in std_logic;
siod: inout std_logic;
sioc: out std_logic;
taken: out std_logic;
send: in std_logic;
id: in std_logic_vector(7 downto 0);
reg: in std_logic_vector(7 downto 0);
value: in std_logic_vector(7 downto 0)
);
end component;
signal command : std_logic_vector(15 downto 0);
signal finished : std_logic := '0';
signal taken : std_logic := '0';
signal send : std_logic;
constant camera_address : std_logic_vector(7 downto 0) := x"42"; -- 42"; -- Device write ID - see top of page 11 of data sheet
begin
config_finished <= finished;
send <= not finished;
Inst_i2c_sender: i2c_sender port map(
clk => clk,
taken => taken,
siod => siod,
sioc => sioc,
send => send,
id => camera_address,
reg => command(15 downto 8),
value => command(7 downto 0)
);
reset <= '1'; -- Normal mode
pwdn <= '0'; -- Power device up
Inst_ov7670_registers: ov7670_registers port map(
clk => clk,
advance => taken,
command => command,
finished => finished,
resend => resend
);
end Structural;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ipshared/e147/xlconstant.vhd
|
7
|
1063
|
------------------------------------------------------------------------
--
-- Filename : xlconstant.vhd
--
-- Date : 06/05/12
--
-- Description : VHDL description of a constant block. This
-- block does not use a core.
--
------------------------------------------------------------------------
------------------------------------------------------------------------
--
-- Entity : xlconstant
--
-- Architecture : behavior
--
-- Description : Top level VHDL description of constant block
--
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity xlconstant is
generic (
CONST_VAL : std_logic_vector := "1"; -- Din lsb position to constant to
CONST_WIDTH : integer := 1); -- Width of output
port (
dout : out std_logic_vector (CONST_WIDTH-1 downto 0)
);
end xlconstant;
architecture behavioral of xlconstant is
begin
dout <= CONST_VAL;
end behavioral;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_vga_color_test_0_0/synth/system_vga_color_test_0_0.vhd
|
6
|
4080
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_color_test:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_color_test_0_0 IS
PORT (
clk_25 : IN STD_LOGIC;
xaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_color_test_0_0;
ARCHITECTURE system_vga_color_test_0_0_arch OF system_vga_color_test_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_color_test_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_color_test IS
GENERIC (
H_SIZE : INTEGER;
V_SIZE : INTEGER
);
PORT (
clk_25 : IN STD_LOGIC;
xaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_color_test;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_color_test_0_0_arch: ARCHITECTURE IS "vga_color_test,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_color_test_0_0_arch : ARCHITECTURE IS "system_vga_color_test_0_0,vga_color_test,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_color_test_0_0_arch: ARCHITECTURE IS "system_vga_color_test_0_0,vga_color_test,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_color_test,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,H_SIZE=640,V_SIZE=480}";
BEGIN
U0 : vga_color_test
GENERIC MAP (
H_SIZE => 640,
V_SIZE => 480
)
PORT MAP (
clk_25 => clk_25,
xaddr => xaddr,
yaddr => yaddr,
rgb => rgb
);
END system_vga_color_test_0_0_arch;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ip/system_vga_color_test_0_0/synth/system_vga_color_test_0_0.vhd
|
6
|
4080
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_color_test:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_color_test_0_0 IS
PORT (
clk_25 : IN STD_LOGIC;
xaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_color_test_0_0;
ARCHITECTURE system_vga_color_test_0_0_arch OF system_vga_color_test_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_color_test_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_color_test IS
GENERIC (
H_SIZE : INTEGER;
V_SIZE : INTEGER
);
PORT (
clk_25 : IN STD_LOGIC;
xaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_color_test;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_color_test_0_0_arch: ARCHITECTURE IS "vga_color_test,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_color_test_0_0_arch : ARCHITECTURE IS "system_vga_color_test_0_0,vga_color_test,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_color_test_0_0_arch: ARCHITECTURE IS "system_vga_color_test_0_0,vga_color_test,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_color_test,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,H_SIZE=640,V_SIZE=480}";
BEGIN
U0 : vga_color_test
GENERIC MAP (
H_SIZE => 640,
V_SIZE => 480
)
PORT MAP (
clk_25 => clk_25,
xaddr => xaddr,
yaddr => yaddr,
rgb => rgb
);
END system_vga_color_test_0_0_arch;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_0/system_ov7670_vga_0_0_stub.vhdl
|
3
|
1414
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 20:55:11 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_0/system_ov7670_vga_0_0_stub.vhdl
-- Design : system_ov7670_vga_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_ov7670_vga_0_0 is
Port (
clk_x2 : in STD_LOGIC;
active : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end system_ov7670_vga_0_0;
architecture stub of system_ov7670_vga_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_x2,active,data[7:0],rgb[15:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "ov7670_vga,Vivado 2016.4";
begin
end;
|
mit
|
freecores/tcp_socket
|
source/gigabit_ethernet.vhd
|
1
|
22521
|
--------------------------------------------------------------------------------
---
--- Gigabit Ethernet MAC
---
--- :Author: Jonathan P Dawson
--- :Date: 17/10/2013
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2013
---
--- A gigabit ethernet MAC
---
--------------------------------------------------------------------------------
---
---Gigabit Ethernet
---================
---
---Send and receive Ethernet packets. Using a Ethernet Physical Interface.
---
---Features:
---
---+ Supports 1Gbit/s ethernet only via a gmii interface.
---+ Supports full duplex mode only.
---
---Interface
------------
---:input: TX - Data to send (16 bits).
---:output: RX - Data to send (16 bits).
---
---Ethernet Packet Structure
----------------------------
---
---+-------------+-------------+--------+--------+---------+---------+-----+
---| Description | destination | source | length | payload | padding | FSC |
---+=============+=============+========+========+=========+=========+=====+
---| Bytes | 6 | 6 | 2 | 0-1500 | 0-46 | 4 |
---+-------------+-------------+--------+--------+---------+---------+-----+
---
---Notes:
---
---+ The *length* field is the length of the ethernet payload.
---+ The *Ethernet Output* block will automatically append the FSC to
--- outgoing packets.
---+ The *FSC* of incoming packets will be checked, and bad packets will
--- be discarded. The *FSC* will be stripped from incoming packets.
---+ The length of the *payload* + *padding* must be 46-1500 bytes.
---+ Incoming packets of incorrect *length* will be discarded.
---
---Usage
--------
---
---Transmit
---~~~~~~~~
---The first 16 bit word on the TX input is interpreted as the length of the
---packet in bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the TX input are interpreted as the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will be ignored.
---The FSC will be appended for you, but you need to supply the destination,
---source and length fields.
---
---Receive
---~~~~~~~~
---The first 16 bit word on the RX output will be the length of the packet in
---bytes (including the MAC address, length and payload, but not the
---preamble or FSC). Subsequent words on the RX output will be the
---content of the packet. If length is an odd number of bytes, then the least
---significant byte of the last word will not contain usefull data.
---The FSC will be stripped from incoming packets, but the destination,
---source and length fields will be included.
---
---Hardware details
-------------------
---This component used two clocks, the local clock used to transfer data
---between components, and a 125MHz clock source for sending data to the
---Ethernet physical interface. This clock is also forwarded along with the
---data to the ethernet phy.
---
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity gigabit_ethernet is
port(
CLK : in std_logic;
RST : in std_logic;
--Ethernet Clock
CLK_125_MHZ : in std_logic;
--GMII IF
GTXCLK : out std_logic;
TXCLK : in std_logic;
TXER : out std_logic;
TXEN : out std_logic;
TXD : out std_logic_vector(7 downto 0);
PHY_RESET : out std_logic;
RXCLK : in std_logic;
RXER : in std_logic;
RXDV : in std_logic;
RXD : in std_logic_vector(7 downto 0);
--RX STREAM
TX : in std_logic_vector(15 downto 0);
TX_STB : in std_logic;
TX_ACK : out std_logic;
--RX STREAM
RX : out std_logic_vector(15 downto 0);
RX_STB : out std_logic;
RX_ACK : in std_logic
);
end entity gigabit_ethernet;
architecture RTL of gigabit_ethernet is
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 8
-- convention: the first serial bit is D[0]
function NEXTCRC32_D8
(DATA: std_logic_vector(7 downto 0);
CRC: std_logic_vector(31 downto 0))
return std_logic_vector is
variable D: std_logic_vector(7 downto 0);
variable C: std_logic_vector(31 downto 0);
variable NEWCRC: std_logic_vector(31 downto 0);
begin
D := DATA;
C := CRC;
NewCRC(0):=C(24) xor C(30) xor D(1) xor D(7);
NewCRC(1):=C(25) xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1)
xor D(7);
NewCRC(2):=C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(3):=C(27) xor D(4) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0)
xor D(6);
NewCRC(4):=C(28) xor D(3) xor C(27) xor D(4) xor C(26) xor D(5) xor C(24)
xor C(30) xor D(1) xor D(7);
NewCRC(5):=C(29) xor D(2) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25)
xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(6):=C(30) xor D(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26)
xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(7):=C(31) xor D(0) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26)
xor D(5) xor C(24) xor D(7);
NewCRC(8):=C(0) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(9):=C(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6);
NewCRC(10):=C(2) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26) xor D(5)
xor C(24) xor D(7);
NewCRC(11):=C(3) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6)
xor C(24) xor D(7);
NewCRC(12):=C(4) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5)
xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(13):=C(5) xor C(30) xor D(1) xor C(29) xor D(2) xor C(27) xor D(4)
xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(14):=C(6) xor C(31) xor D(0) xor C(30) xor D(1) xor C(28) xor D(3)
xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(15):=C(7) xor C(31) xor D(0) xor C(29) xor D(2) xor C(28) xor D(3)
xor C(27) xor D(4);
NewCRC(16):=C(8) xor C(29) xor D(2) xor C(28) xor D(3) xor C(24) xor D(7);
NewCRC(17):=C(9) xor C(30) xor D(1) xor C(29) xor D(2) xor C(25) xor D(6);
NewCRC(18):=C(10) xor C(31) xor D(0) xor C(30) xor D(1) xor C(26) xor D(5);
NewCRC(19):=C(11) xor C(31) xor D(0) xor C(27) xor D(4);
NewCRC(20):=C(12) xor C(28) xor D(3);
NewCRC(21):=C(13) xor C(29) xor D(2);
NewCRC(22):=C(14) xor C(24) xor D(7);
NewCRC(23):=C(15) xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(24):=C(16) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(25):=C(17) xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(26):=C(18) xor C(28) xor D(3) xor C(27) xor D(4) xor C(24) xor C(30)
xor D(1) xor D(7);
NewCRC(27):=C(19) xor C(29) xor D(2) xor C(28) xor D(3) xor C(25) xor C(31)
xor D(0) xor D(6);
NewCRC(28):=C(20) xor C(30) xor D(1) xor C(29) xor D(2) xor C(26) xor D(5);
NewCRC(29):=C(21) xor C(31) xor D(0) xor C(30) xor D(1) xor C(27) xor D(4);
NewCRC(30):=C(22) xor C(31) xor D(0) xor C(28) xor D(3);
NewCRC(31):=C(23) xor C(29) xor D(2);
return NEWCRC;
end NEXTCRC32_D8;
-- Reverse the input vector.
function REVERSED(slv: std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(slv'reverse_range);
begin
for i in slv'range loop
result(i) := slv(i);
end loop;
return result;
end REVERSED;
--constants
constant ADDRESS_BITS : integer := 11;
constant ADDRESS_MAX : integer := (2**ADDRESS_BITS) - 1;
--memories
type TX_MEMORY_TYPE is array (0 to 511) of
std_logic_vector(15 downto 0);
shared variable TX_MEMORY : TX_MEMORY_TYPE;
type RX_MEMORY_TYPE is array (0 to ADDRESS_MAX) of
std_logic_vector(15 downto 0);
shared variable RX_MEMORY : RX_MEMORY_TYPE;
type ADDRESS_ARRAY is array (0 to 31) of
unsigned(ADDRESS_BITS - 1 downto 0);
--state variables
type TX_PHY_STATE_TYPE is (WAIT_NEW_PACKET, PREAMBLE_0, PREAMBLE_1,
PREAMBLE_2, PREAMBLE_3, PREAMBLE_4, PREAMBLE_5, PREAMBLE_6, SFD,
SEND_DATA_HI, SEND_DATA_LO, SEND_CRC_3, SEND_CRC_2, SEND_CRC_1,
SEND_CRC_0, DONE_STATE);
signal TX_PHY_STATE : TX_PHY_STATE_TYPE;
type TX_PACKET_STATE_TYPE is(GET_LENGTH, GET_DATA, SEND_PACKET,
WAIT_NOT_DONE);
signal TX_PACKET_STATE : TX_PACKET_STATE_TYPE;
type RX_PHY_STATE_TYPE is (WAIT_START, PREAMBLE, DATA_HIGH, DATA_LOW,
END_OF_FRAME, NOTIFY_NEW_PACKET);
signal RX_PHY_STATE : RX_PHY_STATE_TYPE;
type RX_PACKET_STATE_TYPE is (WAIT_INITIALISE, WAIT_NEW_PACKET,
SEND_DATA, PREFETCH0, PREFETCH1, SEND_LENGTH);
signal RX_PACKET_STATE : RX_PACKET_STATE_TYPE;
--TX signals
signal TX_WRITE : std_logic;
signal TX_WRITE_DATA : std_logic_vector(15 downto 0);
signal TX_READ_DATA : std_logic_vector(15 downto 0);
signal TX_WRITE_ADDRESS : integer range 0 to 1513;
signal TX_WRITE_ADDRESS_DEL : integer range 0 to 1513;
signal TX_READ_ADDRESS : integer range 0 to 1513;
signal TX_CRC : std_logic_vector(31 downto 0);
signal TX_IN_COUNT : integer range 0 to 1513;
signal TX_OUT_COUNT : integer range 0 to 1513;
signal TX_PACKET_LENGTH : std_logic_vector(15 downto 0);
signal GO, GO_DEL, GO_SYNC : std_logic;
signal DONE, DONE_DEL, DONE_SYNC : std_logic;
signal S_TX_ACK : std_logic;
--RX signals
signal RX_WRITE_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_READ_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_START_ADDRESS_BUFFER : ADDRESS_ARRAY;
signal RX_PACKET_LENGTH_BUFFER : ADDRESS_ARRAY;
signal RX_WRITE_BUFFER : integer range 0 to 31;
signal RX_READ_BUFFER : integer range 0 to 31;
signal RX_BUFFER_BUSY : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_DEL : std_logic_vector(31 downto 0);
signal RX_BUFFER_BUSY_SYNC : std_logic_vector(31 downto 0);
signal RX_START_ADDRESS_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_PACKET_LENGTH_SYNC : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_END_ADDRESS : unsigned(ADDRESS_BITS - 1 downto 0);
signal RX_WRITE_DATA : std_logic_vector(15 downto 0);
signal RX_WRITE_ENABLE : std_logic;
signal RX_ERROR : std_logic;
signal RX_CRC : std_logic_vector(31 downto 0);
signal RXD_D : std_logic_vector(7 downto 0);
signal RXDV_D : std_logic;
signal RXER_D : std_logic;
begin
--This process is in the local clock domain.
--It gets data and puts it into a RAM.
--Once a packets worth of data has been stored it is
--sent to the packet sending state machine.
TX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
TX_WRITE <= '0';
case TX_PACKET_STATE is
when GET_LENGTH =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
S_TX_ACK <= '0';
TX_PACKET_LENGTH <= TX;
TX_IN_COUNT <= 2;
TX_PACKET_STATE <= GET_DATA;
end if;
when GET_DATA =>
S_TX_ACK <= '1';
if S_TX_ACK = '1' and TX_STB = '1' then
TX_WRITE_DATA <= TX;
TX_WRITE <= '1';
if TX_IN_COUNT >= unsigned(TX_PACKET_LENGTH) then
TX_PACKET_STATE <= SEND_PACKET;
S_TX_ACK <= '0';
else
TX_WRITE_ADDRESS <= TX_WRITE_ADDRESS + 1;
TX_IN_COUNT <= TX_IN_COUNT + 2;
end if;
end if;
when SEND_PACKET =>
GO <= '1';
TX_WRITE_ADDRESS <= 0;
if DONE_SYNC = '1' then
GO <= '0';
TX_PACKET_STATE <= WAIT_NOT_DONE;
end if;
when WAIT_NOT_DONE =>
if DONE_SYNC = '0' then
TX_PACKET_STATE <= GET_LENGTH;
end if;
end case;
if RST = '1' then
TX_PACKET_STATE <= GET_LENGTH;
TX_WRITE_ADDRESS <= 0;
S_TX_ACK <= '0';
GO <= '0';
end if;
end process TX_PACKET_FSM;
TX_ACK <= S_TX_ACK;
--This process writes data into a dual port RAM
WRITE_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(CLK);
TX_WRITE_ADDRESS_DEL <= TX_WRITE_ADDRESS;
if TX_WRITE = '1' then
TX_MEMORY(TX_WRITE_ADDRESS_DEL) := TX_WRITE_DATA;
end if;
end process;
--This process read data from a dual port RAM
READ_DUAL_PORT_MEMORY : process
begin
wait until rising_edge(CLK_125_MHZ);
TX_READ_DATA <= TX_MEMORY(TX_READ_ADDRESS);
end process;
--This process synchronises ethernet signals
--to the local clock domain
LOCAL_TO_CLK_125 : process
begin
wait until rising_edge(CLK_125_MHZ);
GO_DEL <= GO; GO_SYNC <= GO_DEL;
end process;
--This process synchronises local signals to the ethernet clock domain
CLK_125_TO_LOCAL : process
begin
wait until rising_edge(CLK);
DONE_DEL <= DONE; DONE_SYNC <= DONE_DEL;
end process;
--Transmit the stored packet via the phy.
TX_PHY_FSM : process
begin
wait until rising_edge(CLK_125_MHZ);
case TX_PHY_STATE is
when WAIT_NEW_PACKET =>
if GO_SYNC = '1' then
TX_PHY_STATE <= PREAMBLE_0;
TX_READ_ADDRESS <= 0;
TX_OUT_COUNT <= to_integer(unsigned(TX_PACKET_LENGTH)-1);
end if;
when PREAMBLE_0 =>
TXD <= X"55";
TX_PHY_STATE <= PREAMBLE_1;
TXEN <= '1';
when PREAMBLE_1 =>
TXD <= X"55";
TX_PHY_STATE <= PREAMBLE_2;
when PREAMBLE_2 =>
TXD <= X"55";
TX_PHY_STATE <= PREAMBLE_3;
when PREAMBLE_3 =>
TXD <= X"55";
TX_PHY_STATE <= PREAMBLE_4;
when PREAMBLE_4 =>
TXD <= X"55";
TX_PHY_STATE <= PREAMBLE_5;
when PREAMBLE_5 =>
TXD <= X"55";
TX_PHY_STATE <= PREAMBLE_6;
when PREAMBLE_6 =>
TXD <= X"55";
TX_PHY_STATE <= SFD;
when SFD =>
TXD <= X"D5";
TX_PHY_STATE <= SEND_DATA_HI;
TX_CRC <= X"FFFFFFFF";
when SEND_DATA_HI =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(15 downto 8), TX_CRC);
TXD <= TX_READ_DATA(15 downto 8);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_3;
else
TX_PHY_STATE <= SEND_DATA_LO;
TX_READ_ADDRESS <= TX_READ_ADDRESS + 1;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_DATA_LO =>
TX_CRC <= NEXTCRC32_D8(TX_READ_DATA(7 downto 0), TX_CRC);
TXD <= TX_READ_DATA(7 downto 0);
If TX_OUT_COUNT = 0 then
TX_PHY_STATE <= SEND_CRC_3;
else
TX_PHY_STATE <= SEND_DATA_HI;
TX_OUT_COUNT <= TX_OUT_COUNT - 1;
end if;
when SEND_CRC_3 =>
TXD <= not REVERSED(TX_CRC(31 downto 24));
TX_PHY_STATE <= SEND_CRC_2;
when SEND_CRC_2 =>
TXD <= not REVERSED(TX_CRC(23 downto 16));
TX_PHY_STATE <= SEND_CRC_1;
when SEND_CRC_1 =>
TXD <= not REVERSED(TX_CRC(15 downto 8));
TX_PHY_STATE <= SEND_CRC_0;
when SEND_CRC_0 =>
TXD <= not REVERSED(TX_CRC(7 downto 0));
TX_PHY_STATE <= DONE_STATE;
when DONE_STATE =>
TXEN <= '0';
DONE <= '1';
if GO_SYNC = '0' then
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
end if;
end case;
if RST = '1' then
TXEN <= '0';
TX_PHY_STATE <= WAIT_NEW_PACKET;
DONE <= '0';
TXD <= (others => '0');
end if;
end process TX_PHY_FSM;
TXER <= '0';
GTXCLK <= CLK_125_MHZ;
--This process reads data out of the phy and puts it into a buffer.
--There are many buffers on the RX side to cope with data arriving at
--a high rate. If a very large packet is received, followed by many small
--packets, a large number of packets need to be stored.
RX_PHY_FSM : process
begin
wait until rising_edge(RXCLK);
RX_WRITE_ENABLE <= '0';
RXDV_D <= RXDV;
RXER_D <= RXER;
RXD_D <= RXD;
case RX_PHY_STATE is
when WAIT_START =>
if RXDV_D = '1' and RXD_D = X"55" then
RX_PHY_STATE <= PREAMBLE;
RX_ERROR <= '0';
end if;
when PREAMBLE =>
if RXD_D = X"d5" then
RX_PHY_STATE <= DATA_HIGH;
RX_START_ADDRESS <= RX_WRITE_ADDRESS;
RX_PACKET_LENGTH <= to_unsigned(0, ADDRESS_BITS);
RX_CRC <= X"ffffffff";
elsif RXD_D /= X"55" or RXDV_D = '0' then
RX_PHY_STATE <= WAIT_START;
end if;
when DATA_HIGH =>
RX_WRITE_DATA(15 downto 8) <= RXD_D;
if RXDV_D = '1' then
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_LOW;
RX_CRC <= nextCRC32_D8(RXD_D, RX_CRC);
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when DATA_LOW =>
RX_WRITE_DATA(7 downto 0) <= RXD_D;
RX_WRITE_ENABLE <= '1';
if RXDV_D = '1' then
RX_PACKET_LENGTH <= RX_PACKET_LENGTH + 1;
RX_PHY_STATE <= DATA_HIGH;
RX_CRC <= nextCRC32_D8(RXD_D, RX_CRC);
else
RX_PHY_STATE <= END_OF_FRAME;
end if;
when END_OF_FRAME =>
if RX_ERROR = '1' then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH < 64 then
RX_PHY_STATE <= WAIT_START;
elsif RX_PACKET_LENGTH > 1518 then
RX_PHY_STATE <= WAIT_START;
elsif RX_CRC /= X"C704dd7B" then
RX_PHY_STATE <= WAIT_START;
else
RX_PHY_STATE <= NOTIFY_NEW_PACKET;
end if;
when NOTIFY_NEW_PACKET =>
RX_PHY_STATE <= WAIT_START;
RX_START_ADDRESS_BUFFER(RX_WRITE_BUFFER) <= RX_START_ADDRESS;
RX_PACKET_LENGTH_BUFFER(RX_WRITE_BUFFER) <= RX_PACKET_LENGTH;
if RX_WRITE_BUFFER = 31 then
RX_WRITE_BUFFER <= 0;
else
RX_WRITE_BUFFER <= RX_WRITE_BUFFER + 1;
end if;
end case;
if RXER_D = '1' then
RX_ERROR <= '1';
end if;
if RST = '1' then
RX_PHY_STATE <= WAIT_START;
end if;
end process RX_PHY_FSM;
--generate a signal for each buffer to indicate that is is being used.
GENERATE_BUFFER_BUSY : process
begin
wait until rising_edge(RXCLK);
for I in 0 to 31 loop
if I = RX_WRITE_BUFFER then
RX_BUFFER_BUSY(I) <= '1';
else
RX_BUFFER_BUSY(I) <= '0';
end if;
end loop;
end process GENERATE_BUFFER_BUSY;
--This is the memory that implements the RX buffers
WRITE_RX_MEMORY : process
begin
wait until rising_edge(RXCLK);
if RX_WRITE_ENABLE = '1' then
RX_MEMORY(to_integer(RX_WRITE_ADDRESS)) := RX_WRITE_DATA;
RX_WRITE_ADDRESS <= RX_WRITE_ADDRESS + 1;
end if;
if RST = '1' then
RX_WRITE_ADDRESS <= (others => '0');
end if;
end process WRITE_RX_MEMORY;
SYNCHRONISE_BUFFER_BUSY : process
begin
wait until rising_edge(CLK);
RX_BUFFER_BUSY_DEL <= RX_BUFFER_BUSY;
RX_BUFFER_BUSY_SYNC <= RX_BUFFER_BUSY_DEL;
end process SYNCHRONISE_BUFFER_BUSY;
--CLK __/""\__/" _/" "\__/""\
--RX_BUFFER_BUSY_SYNC[0] ""\_______ ____________
--RX_BUFFER_BUSY_SYNC[1] ________/" "\__________
--RX_BUFFER_BUSY_SYNC[2] __________ _______/""""
-- ^
-- Start to read packet 0 here.
-- Note: since RX_BUFFER_BUSY originates in a different clock domain,
-- it is possible that a clock cycle or so could elapse between
-- RX_BUFFER_BUSY_SYNC[0] becoming low and RX_BUFFER_BUSY_SYNC[1] becoming
-- high. We are relying on the delay through the state machine to be
-- long enough that we don't try to read BUFFER1 during this period.
RX_PACKET_FSM : process
begin
wait until rising_edge(CLK);
case RX_PACKET_STATE is
when WAIT_INITIALISE =>
if RX_BUFFER_BUSY_SYNC(0) = '1' then
RX_PACKET_STATE <= WAIT_NEW_PACKET;
RX_READ_BUFFER <= 0;
end if;
when WAIT_NEW_PACKET =>
if RX_BUFFER_BUSY_SYNC(RX_READ_BUFFER) = '0' then
RX_PACKET_STATE <= SEND_LENGTH;
RX_START_ADDRESS_SYNC <= RX_START_ADDRESS_BUFFER(RX_READ_BUFFER);
RX_PACKET_LENGTH_SYNC <= RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER);
RX <=
std_logic_vector(
resize(RX_PACKET_LENGTH_BUFFER(RX_READ_BUFFER)-4, 16));
RX_STB <= '1';
end if;
when SEND_LENGTH =>
if RX_ACK = '1' then
RX_PACKET_STATE <= PREFETCH0;
RX_STB <= '0';
end if;
when PREFETCH0 =>
RX_READ_ADDRESS <= RX_START_ADDRESS_SYNC;
RX_END_ADDRESS <= RX_START_ADDRESS_SYNC + (RX_PACKET_LENGTH_SYNC-3)/2;
RX_PACKET_STATE <= PREFETCH1;
when PREFETCH1 =>
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
RX_STB <= '1';
RX_PACKET_STATE <= SEND_DATA;
when SEND_DATA =>
if RX_ACK = '1' then
RX_READ_ADDRESS <= RX_READ_ADDRESS + 1;
RX <= RX_MEMORY(to_integer(RX_READ_ADDRESS));
if RX_READ_ADDRESS = RX_END_ADDRESS then --don't send last packet
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_NEW_PACKET;
if RX_READ_BUFFER = 31 then
RX_READ_BUFFER <= 0;
else
RX_READ_BUFFER <= RX_READ_BUFFER + 1;
end if;
end if;
end if;
end case;
if RST = '1' then
RX_STB <= '0';
RX_PACKET_STATE <= WAIT_INITIALISE;
end if;
end process RX_PACKET_FSM;
----------------------------------------------------------------------
-- RESET PHY CHIP
----------------------------------------------------------------------
PHY_RESET <= not RST;
end architecture RTL;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_0_0/sim/system_rgb565_to_rgb888_0_0.vhd
|
2
|
3128
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:rgb565_to_rgb888:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_rgb565_to_rgb888_0_0 IS
PORT (
rgb_565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rgb_888 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_rgb565_to_rgb888_0_0;
ARCHITECTURE system_rgb565_to_rgb888_0_0_arch OF system_rgb565_to_rgb888_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rgb565_to_rgb888_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT rgb565_to_rgb888 IS
PORT (
rgb_565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rgb_888 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT rgb565_to_rgb888;
BEGIN
U0 : rgb565_to_rgb888
PORT MAP (
rgb_565 => rgb_565,
rgb_888 => rgb_888
);
END system_rgb565_to_rgb888_0_0_arch;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_nmsuppression_0_0/system_vga_nmsuppression_0_0_sim_netlist.vhdl
|
1
|
215472
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue May 30 22:29:19 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_vga_nmsuppression_0_0 -prefix
-- system_vga_nmsuppression_0_0_ system_vga_nmsuppression_1_0_sim_netlist.vhdl
-- Design : system_vga_nmsuppression_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_nmsuppression_0_0_vga_nmsuppression is
port (
x_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 );
active : in STD_LOGIC;
clk : in STD_LOGIC;
x_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
enable : in STD_LOGIC
);
end system_vga_nmsuppression_0_0_vga_nmsuppression;
architecture STRUCTURE of system_vga_nmsuppression_0_0_vga_nmsuppression is
signal \hessian_out2_carry__0_i_1_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_i_2_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_i_3_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_i_4_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_i_5_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_i_6_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_i_7_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_i_8_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__0_n_1\ : STD_LOGIC;
signal \hessian_out2_carry__0_n_2\ : STD_LOGIC;
signal \hessian_out2_carry__0_n_3\ : STD_LOGIC;
signal \hessian_out2_carry__1_i_1_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_i_2_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_i_3_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_i_4_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_i_5_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_i_6_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_i_7_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_i_8_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__1_n_1\ : STD_LOGIC;
signal \hessian_out2_carry__1_n_2\ : STD_LOGIC;
signal \hessian_out2_carry__1_n_3\ : STD_LOGIC;
signal \hessian_out2_carry__2_i_1_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_i_2_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_i_3_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_i_4_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_i_5_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_i_6_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_i_7_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_i_8_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_n_0\ : STD_LOGIC;
signal \hessian_out2_carry__2_n_1\ : STD_LOGIC;
signal \hessian_out2_carry__2_n_2\ : STD_LOGIC;
signal \hessian_out2_carry__2_n_3\ : STD_LOGIC;
signal hessian_out2_carry_i_1_n_0 : STD_LOGIC;
signal hessian_out2_carry_i_2_n_0 : STD_LOGIC;
signal hessian_out2_carry_i_3_n_0 : STD_LOGIC;
signal hessian_out2_carry_i_4_n_0 : STD_LOGIC;
signal hessian_out2_carry_i_5_n_0 : STD_LOGIC;
signal hessian_out2_carry_i_6_n_0 : STD_LOGIC;
signal hessian_out2_carry_i_7_n_0 : STD_LOGIC;
signal hessian_out2_carry_i_8_n_0 : STD_LOGIC;
signal hessian_out2_carry_n_0 : STD_LOGIC;
signal hessian_out2_carry_n_1 : STD_LOGIC;
signal hessian_out2_carry_n_2 : STD_LOGIC;
signal hessian_out2_carry_n_3 : STD_LOGIC;
signal \hessian_out3_carry__0_i_1_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_i_2_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_i_3_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_i_4_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_i_5_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_i_6_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_i_7_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_i_8_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__0_n_1\ : STD_LOGIC;
signal \hessian_out3_carry__0_n_2\ : STD_LOGIC;
signal \hessian_out3_carry__0_n_3\ : STD_LOGIC;
signal \hessian_out3_carry__1_i_1_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_i_2_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_i_3_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_i_4_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_i_5_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_i_6_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_i_7_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_i_8_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__1_n_1\ : STD_LOGIC;
signal \hessian_out3_carry__1_n_2\ : STD_LOGIC;
signal \hessian_out3_carry__1_n_3\ : STD_LOGIC;
signal \hessian_out3_carry__2_i_1_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_i_2_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_i_3_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_i_4_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_i_5_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_i_6_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_i_7_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_i_8_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_n_0\ : STD_LOGIC;
signal \hessian_out3_carry__2_n_1\ : STD_LOGIC;
signal \hessian_out3_carry__2_n_2\ : STD_LOGIC;
signal \hessian_out3_carry__2_n_3\ : STD_LOGIC;
signal hessian_out3_carry_i_1_n_0 : STD_LOGIC;
signal hessian_out3_carry_i_2_n_0 : STD_LOGIC;
signal hessian_out3_carry_i_3_n_0 : STD_LOGIC;
signal hessian_out3_carry_i_4_n_0 : STD_LOGIC;
signal hessian_out3_carry_i_5_n_0 : STD_LOGIC;
signal hessian_out3_carry_i_6_n_0 : STD_LOGIC;
signal hessian_out3_carry_i_7_n_0 : STD_LOGIC;
signal hessian_out3_carry_i_8_n_0 : STD_LOGIC;
signal hessian_out3_carry_n_0 : STD_LOGIC;
signal hessian_out3_carry_n_1 : STD_LOGIC;
signal hessian_out3_carry_n_2 : STD_LOGIC;
signal hessian_out3_carry_n_3 : STD_LOGIC;
signal \hessian_out4_carry__0_i_1_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_i_2_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_i_3_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_i_4_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_i_5_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_i_6_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_i_7_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_i_8_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__0_n_1\ : STD_LOGIC;
signal \hessian_out4_carry__0_n_2\ : STD_LOGIC;
signal \hessian_out4_carry__0_n_3\ : STD_LOGIC;
signal \hessian_out4_carry__1_i_1_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_i_2_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_i_3_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_i_4_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_i_5_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_i_6_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_i_7_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_i_8_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__1_n_1\ : STD_LOGIC;
signal \hessian_out4_carry__1_n_2\ : STD_LOGIC;
signal \hessian_out4_carry__1_n_3\ : STD_LOGIC;
signal \hessian_out4_carry__2_i_1_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_i_2_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_i_3_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_i_4_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_i_5_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_i_6_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_i_7_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_i_8_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_n_0\ : STD_LOGIC;
signal \hessian_out4_carry__2_n_1\ : STD_LOGIC;
signal \hessian_out4_carry__2_n_2\ : STD_LOGIC;
signal \hessian_out4_carry__2_n_3\ : STD_LOGIC;
signal hessian_out4_carry_i_1_n_0 : STD_LOGIC;
signal hessian_out4_carry_i_2_n_0 : STD_LOGIC;
signal hessian_out4_carry_i_3_n_0 : STD_LOGIC;
signal hessian_out4_carry_i_4_n_0 : STD_LOGIC;
signal hessian_out4_carry_i_5_n_0 : STD_LOGIC;
signal hessian_out4_carry_i_6_n_0 : STD_LOGIC;
signal hessian_out4_carry_i_7_n_0 : STD_LOGIC;
signal hessian_out4_carry_i_8_n_0 : STD_LOGIC;
signal hessian_out4_carry_n_0 : STD_LOGIC;
signal hessian_out4_carry_n_1 : STD_LOGIC;
signal hessian_out4_carry_n_2 : STD_LOGIC;
signal hessian_out4_carry_n_3 : STD_LOGIC;
signal \hessian_out5_carry__0_i_1_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_i_2_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_i_3_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_i_4_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_i_5_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_i_6_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_i_7_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_i_8_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__0_n_1\ : STD_LOGIC;
signal \hessian_out5_carry__0_n_2\ : STD_LOGIC;
signal \hessian_out5_carry__0_n_3\ : STD_LOGIC;
signal \hessian_out5_carry__1_i_1_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_i_2_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_i_3_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_i_4_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_i_5_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_i_6_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_i_7_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_i_8_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__1_n_1\ : STD_LOGIC;
signal \hessian_out5_carry__1_n_2\ : STD_LOGIC;
signal \hessian_out5_carry__1_n_3\ : STD_LOGIC;
signal \hessian_out5_carry__2_i_1_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_i_2_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_i_3_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_i_4_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_i_5_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_i_6_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_i_7_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_i_8_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_n_0\ : STD_LOGIC;
signal \hessian_out5_carry__2_n_1\ : STD_LOGIC;
signal \hessian_out5_carry__2_n_2\ : STD_LOGIC;
signal \hessian_out5_carry__2_n_3\ : STD_LOGIC;
signal hessian_out5_carry_i_1_n_0 : STD_LOGIC;
signal hessian_out5_carry_i_2_n_0 : STD_LOGIC;
signal hessian_out5_carry_i_3_n_0 : STD_LOGIC;
signal hessian_out5_carry_i_4_n_0 : STD_LOGIC;
signal hessian_out5_carry_i_5_n_0 : STD_LOGIC;
signal hessian_out5_carry_i_6_n_0 : STD_LOGIC;
signal hessian_out5_carry_i_7_n_0 : STD_LOGIC;
signal hessian_out5_carry_i_8_n_0 : STD_LOGIC;
signal hessian_out5_carry_n_0 : STD_LOGIC;
signal hessian_out5_carry_n_1 : STD_LOGIC;
signal hessian_out5_carry_n_2 : STD_LOGIC;
signal hessian_out5_carry_n_3 : STD_LOGIC;
signal \hessian_out6_carry__0_i_1_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_i_2_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_i_3_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_i_4_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_i_5_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_i_6_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_i_7_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_i_8_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__0_n_1\ : STD_LOGIC;
signal \hessian_out6_carry__0_n_2\ : STD_LOGIC;
signal \hessian_out6_carry__0_n_3\ : STD_LOGIC;
signal \hessian_out6_carry__1_i_1_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_i_2_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_i_3_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_i_4_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_i_5_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_i_6_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_i_7_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_i_8_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__1_n_1\ : STD_LOGIC;
signal \hessian_out6_carry__1_n_2\ : STD_LOGIC;
signal \hessian_out6_carry__1_n_3\ : STD_LOGIC;
signal \hessian_out6_carry__2_i_1_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_i_2_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_i_3_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_i_4_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_i_5_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_i_6_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_i_7_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_i_8_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_n_0\ : STD_LOGIC;
signal \hessian_out6_carry__2_n_1\ : STD_LOGIC;
signal \hessian_out6_carry__2_n_2\ : STD_LOGIC;
signal \hessian_out6_carry__2_n_3\ : STD_LOGIC;
signal hessian_out6_carry_i_1_n_0 : STD_LOGIC;
signal hessian_out6_carry_i_2_n_0 : STD_LOGIC;
signal hessian_out6_carry_i_3_n_0 : STD_LOGIC;
signal hessian_out6_carry_i_4_n_0 : STD_LOGIC;
signal hessian_out6_carry_i_5_n_0 : STD_LOGIC;
signal hessian_out6_carry_i_6_n_0 : STD_LOGIC;
signal hessian_out6_carry_i_7_n_0 : STD_LOGIC;
signal hessian_out6_carry_i_8_n_0 : STD_LOGIC;
signal hessian_out6_carry_n_0 : STD_LOGIC;
signal hessian_out6_carry_n_1 : STD_LOGIC;
signal hessian_out6_carry_n_2 : STD_LOGIC;
signal hessian_out6_carry_n_3 : STD_LOGIC;
signal \hessian_out7_carry__0_i_1_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_i_2_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_i_3_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_i_4_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_i_5_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_i_6_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_i_7_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_i_8_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__0_n_1\ : STD_LOGIC;
signal \hessian_out7_carry__0_n_2\ : STD_LOGIC;
signal \hessian_out7_carry__0_n_3\ : STD_LOGIC;
signal \hessian_out7_carry__1_i_1_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_i_2_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_i_3_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_i_4_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_i_5_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_i_6_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_i_7_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_i_8_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__1_n_1\ : STD_LOGIC;
signal \hessian_out7_carry__1_n_2\ : STD_LOGIC;
signal \hessian_out7_carry__1_n_3\ : STD_LOGIC;
signal \hessian_out7_carry__2_i_1_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_i_2_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_i_3_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_i_4_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_i_5_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_i_6_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_i_7_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_i_8_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_n_0\ : STD_LOGIC;
signal \hessian_out7_carry__2_n_1\ : STD_LOGIC;
signal \hessian_out7_carry__2_n_2\ : STD_LOGIC;
signal \hessian_out7_carry__2_n_3\ : STD_LOGIC;
signal hessian_out7_carry_i_1_n_0 : STD_LOGIC;
signal hessian_out7_carry_i_2_n_0 : STD_LOGIC;
signal hessian_out7_carry_i_3_n_0 : STD_LOGIC;
signal hessian_out7_carry_i_4_n_0 : STD_LOGIC;
signal hessian_out7_carry_i_5_n_0 : STD_LOGIC;
signal hessian_out7_carry_i_6_n_0 : STD_LOGIC;
signal hessian_out7_carry_i_7_n_0 : STD_LOGIC;
signal hessian_out7_carry_i_8_n_0 : STD_LOGIC;
signal hessian_out7_carry_n_0 : STD_LOGIC;
signal hessian_out7_carry_n_1 : STD_LOGIC;
signal hessian_out7_carry_n_2 : STD_LOGIC;
signal hessian_out7_carry_n_3 : STD_LOGIC;
signal \hessian_out8__15_carry__0_i_1_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_i_2_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_i_3_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_i_4_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_i_5_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_i_6_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_i_7_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_i_8_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_n_1\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_n_2\ : STD_LOGIC;
signal \hessian_out8__15_carry__0_n_3\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_i_1_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_i_2_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_i_3_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_i_4_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_i_5_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_i_6_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_i_7_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_i_8_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_n_1\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_n_2\ : STD_LOGIC;
signal \hessian_out8__15_carry__1_n_3\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_i_1_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_i_2_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_i_3_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_i_4_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_i_5_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_i_6_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_i_7_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_i_8_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_n_1\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_n_2\ : STD_LOGIC;
signal \hessian_out8__15_carry__2_n_3\ : STD_LOGIC;
signal \hessian_out8__15_carry_i_1_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_i_2_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_i_3_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_i_4_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_i_5_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_i_6_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_i_7_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_i_8_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_n_0\ : STD_LOGIC;
signal \hessian_out8__15_carry_n_1\ : STD_LOGIC;
signal \hessian_out8__15_carry_n_2\ : STD_LOGIC;
signal \hessian_out8__15_carry_n_3\ : STD_LOGIC;
signal \hessian_out8_carry__0_i_1_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_i_2_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_i_3_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_i_4_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_i_5_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_i_6_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_i_7_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_i_8_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__0_n_1\ : STD_LOGIC;
signal \hessian_out8_carry__0_n_2\ : STD_LOGIC;
signal \hessian_out8_carry__0_n_3\ : STD_LOGIC;
signal \hessian_out8_carry__1_i_1_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_i_2_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_i_3_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_i_4_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_i_5_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_i_6_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_i_7_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_i_8_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__1_n_1\ : STD_LOGIC;
signal \hessian_out8_carry__1_n_2\ : STD_LOGIC;
signal \hessian_out8_carry__1_n_3\ : STD_LOGIC;
signal \hessian_out8_carry__2_i_1_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_i_2_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_i_3_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_i_4_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_i_5_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_i_6_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_i_7_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_i_8_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_n_0\ : STD_LOGIC;
signal \hessian_out8_carry__2_n_1\ : STD_LOGIC;
signal \hessian_out8_carry__2_n_2\ : STD_LOGIC;
signal \hessian_out8_carry__2_n_3\ : STD_LOGIC;
signal hessian_out8_carry_i_1_n_0 : STD_LOGIC;
signal hessian_out8_carry_i_2_n_0 : STD_LOGIC;
signal hessian_out8_carry_i_3_n_0 : STD_LOGIC;
signal hessian_out8_carry_i_4_n_0 : STD_LOGIC;
signal hessian_out8_carry_i_5_n_0 : STD_LOGIC;
signal hessian_out8_carry_i_6_n_0 : STD_LOGIC;
signal hessian_out8_carry_i_7_n_0 : STD_LOGIC;
signal hessian_out8_carry_i_8_n_0 : STD_LOGIC;
signal hessian_out8_carry_n_0 : STD_LOGIC;
signal hessian_out8_carry_n_1 : STD_LOGIC;
signal hessian_out8_carry_n_2 : STD_LOGIC;
signal hessian_out8_carry_n_3 : STD_LOGIC;
signal \hessian_out[31]_i_1_n_0\ : STD_LOGIC;
signal \hessian_out[31]_i_2_n_0\ : STD_LOGIC;
signal \hessian_reg[0]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \hessian_reg[10]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \hessian_reg[11]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \hessian_reg[1]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \hessian_reg[4][0]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][10]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][11]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][12]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][13]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][14]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][15]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][16]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][17]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][18]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][19]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][1]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][20]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][21]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][22]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][23]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][24]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][25]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][26]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][27]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][28]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][29]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][2]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][30]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][31]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][3]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][4]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][5]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][6]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][7]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][8]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[4][9]_srl3_n_0\ : STD_LOGIC;
signal \hessian_reg[5]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \hessian_reg[6]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \hessian_reg[7]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \hessian_reg[8]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \hessian_reg[9]\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal minusOp : STD_LOGIC_VECTOR ( 0 to 0 );
signal \minusOp_inferred__0/y_addr_out[0]_i_1_n_0\ : STD_LOGIC;
signal \minusOp_inferred__0/y_addr_out[9]_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out[1]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[2]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[3]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[4]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[5]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[6]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[7]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[8]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[9]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[9]_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out[1]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out[2]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out[3]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out[4]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out[5]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out[6]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out[7]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out[8]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out[9]_i_1_n_0\ : STD_LOGIC;
signal NLW_hessian_out2_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out2_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out2_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out2_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_hessian_out3_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out3_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out3_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out3_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_hessian_out4_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out4_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out4_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out4_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_hessian_out5_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out5_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out5_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out5_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_hessian_out6_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out6_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out6_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out6_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_hessian_out7_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out7_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out7_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out7_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out8__15_carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out8__15_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out8__15_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out8__15_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_hessian_out8_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out8_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out8_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hessian_out8_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute srl_bus_name : string;
attribute srl_bus_name of \hessian_reg[4][0]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name : string;
attribute srl_name of \hessian_reg[4][0]_srl3\ : label is "\U0/hessian_reg[4][0]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][10]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][10]_srl3\ : label is "\U0/hessian_reg[4][10]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][11]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][11]_srl3\ : label is "\U0/hessian_reg[4][11]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][12]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][12]_srl3\ : label is "\U0/hessian_reg[4][12]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][13]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][13]_srl3\ : label is "\U0/hessian_reg[4][13]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][14]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][14]_srl3\ : label is "\U0/hessian_reg[4][14]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][15]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][15]_srl3\ : label is "\U0/hessian_reg[4][15]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][16]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][16]_srl3\ : label is "\U0/hessian_reg[4][16]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][17]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][17]_srl3\ : label is "\U0/hessian_reg[4][17]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][18]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][18]_srl3\ : label is "\U0/hessian_reg[4][18]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][19]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][19]_srl3\ : label is "\U0/hessian_reg[4][19]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][1]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][1]_srl3\ : label is "\U0/hessian_reg[4][1]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][20]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][20]_srl3\ : label is "\U0/hessian_reg[4][20]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][21]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][21]_srl3\ : label is "\U0/hessian_reg[4][21]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][22]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][22]_srl3\ : label is "\U0/hessian_reg[4][22]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][23]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][23]_srl3\ : label is "\U0/hessian_reg[4][23]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][24]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][24]_srl3\ : label is "\U0/hessian_reg[4][24]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][25]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][25]_srl3\ : label is "\U0/hessian_reg[4][25]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][26]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][26]_srl3\ : label is "\U0/hessian_reg[4][26]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][27]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][27]_srl3\ : label is "\U0/hessian_reg[4][27]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][28]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][28]_srl3\ : label is "\U0/hessian_reg[4][28]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][29]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][29]_srl3\ : label is "\U0/hessian_reg[4][29]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][2]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][2]_srl3\ : label is "\U0/hessian_reg[4][2]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][30]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][30]_srl3\ : label is "\U0/hessian_reg[4][30]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][31]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][31]_srl3\ : label is "\U0/hessian_reg[4][31]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][3]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][3]_srl3\ : label is "\U0/hessian_reg[4][3]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][4]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][4]_srl3\ : label is "\U0/hessian_reg[4][4]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][5]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][5]_srl3\ : label is "\U0/hessian_reg[4][5]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][6]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][6]_srl3\ : label is "\U0/hessian_reg[4][6]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][7]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][7]_srl3\ : label is "\U0/hessian_reg[4][7]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][8]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][8]_srl3\ : label is "\U0/hessian_reg[4][8]_srl3 ";
attribute srl_bus_name of \hessian_reg[4][9]_srl3\ : label is "\U0/hessian_reg[4] ";
attribute srl_name of \hessian_reg[4][9]_srl3\ : label is "\U0/hessian_reg[4][9]_srl3 ";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \x_addr_out[1]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \x_addr_out[2]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \x_addr_out[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \x_addr_out[4]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \x_addr_out[6]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \x_addr_out[7]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \x_addr_out[8]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \x_addr_out[9]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \y_addr_out[1]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \y_addr_out[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \y_addr_out[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \y_addr_out[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \y_addr_out[6]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \y_addr_out[7]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \y_addr_out[8]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \y_addr_out[9]_i_1\ : label is "soft_lutpair3";
begin
hessian_out2_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => hessian_out2_carry_n_0,
CO(2) => hessian_out2_carry_n_1,
CO(1) => hessian_out2_carry_n_2,
CO(0) => hessian_out2_carry_n_3,
CYINIT => '0',
DI(3) => hessian_out2_carry_i_1_n_0,
DI(2) => hessian_out2_carry_i_2_n_0,
DI(1) => hessian_out2_carry_i_3_n_0,
DI(0) => hessian_out2_carry_i_4_n_0,
O(3 downto 0) => NLW_hessian_out2_carry_O_UNCONNECTED(3 downto 0),
S(3) => hessian_out2_carry_i_5_n_0,
S(2) => hessian_out2_carry_i_6_n_0,
S(1) => hessian_out2_carry_i_7_n_0,
S(0) => hessian_out2_carry_i_8_n_0
);
\hessian_out2_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => hessian_out2_carry_n_0,
CO(3) => \hessian_out2_carry__0_n_0\,
CO(2) => \hessian_out2_carry__0_n_1\,
CO(1) => \hessian_out2_carry__0_n_2\,
CO(0) => \hessian_out2_carry__0_n_3\,
CYINIT => '0',
DI(3) => \hessian_out2_carry__0_i_1_n_0\,
DI(2) => \hessian_out2_carry__0_i_2_n_0\,
DI(1) => \hessian_out2_carry__0_i_3_n_0\,
DI(0) => \hessian_out2_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out2_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out2_carry__0_i_5_n_0\,
S(2) => \hessian_out2_carry__0_i_6_n_0\,
S(1) => \hessian_out2_carry__0_i_7_n_0\,
S(0) => \hessian_out2_carry__0_i_8_n_0\
);
\hessian_out2_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[11]\(14),
I3 => \hessian_reg[6]\(15),
O => \hessian_out2_carry__0_i_1_n_0\
);
\hessian_out2_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[11]\(12),
I3 => \hessian_reg[6]\(13),
O => \hessian_out2_carry__0_i_2_n_0\
);
\hessian_out2_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[11]\(10),
I3 => \hessian_reg[6]\(11),
O => \hessian_out2_carry__0_i_3_n_0\
);
\hessian_out2_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[11]\(8),
I3 => \hessian_reg[6]\(9),
O => \hessian_out2_carry__0_i_4_n_0\
);
\hessian_out2_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[11]\(14),
I3 => \hessian_reg[6]\(15),
O => \hessian_out2_carry__0_i_5_n_0\
);
\hessian_out2_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[11]\(12),
I3 => \hessian_reg[6]\(13),
O => \hessian_out2_carry__0_i_6_n_0\
);
\hessian_out2_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[11]\(10),
I3 => \hessian_reg[6]\(11),
O => \hessian_out2_carry__0_i_7_n_0\
);
\hessian_out2_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[11]\(8),
I3 => \hessian_reg[6]\(9),
O => \hessian_out2_carry__0_i_8_n_0\
);
\hessian_out2_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out2_carry__0_n_0\,
CO(3) => \hessian_out2_carry__1_n_0\,
CO(2) => \hessian_out2_carry__1_n_1\,
CO(1) => \hessian_out2_carry__1_n_2\,
CO(0) => \hessian_out2_carry__1_n_3\,
CYINIT => '0',
DI(3) => \hessian_out2_carry__1_i_1_n_0\,
DI(2) => \hessian_out2_carry__1_i_2_n_0\,
DI(1) => \hessian_out2_carry__1_i_3_n_0\,
DI(0) => \hessian_out2_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out2_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out2_carry__1_i_5_n_0\,
S(2) => \hessian_out2_carry__1_i_6_n_0\,
S(1) => \hessian_out2_carry__1_i_7_n_0\,
S(0) => \hessian_out2_carry__1_i_8_n_0\
);
\hessian_out2_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[11]\(22),
I3 => \hessian_reg[6]\(23),
O => \hessian_out2_carry__1_i_1_n_0\
);
\hessian_out2_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[11]\(20),
I3 => \hessian_reg[6]\(21),
O => \hessian_out2_carry__1_i_2_n_0\
);
\hessian_out2_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[11]\(18),
I3 => \hessian_reg[6]\(19),
O => \hessian_out2_carry__1_i_3_n_0\
);
\hessian_out2_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[11]\(16),
I3 => \hessian_reg[6]\(17),
O => \hessian_out2_carry__1_i_4_n_0\
);
\hessian_out2_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[11]\(22),
I3 => \hessian_reg[6]\(23),
O => \hessian_out2_carry__1_i_5_n_0\
);
\hessian_out2_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[11]\(20),
I3 => \hessian_reg[6]\(21),
O => \hessian_out2_carry__1_i_6_n_0\
);
\hessian_out2_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[11]\(18),
I3 => \hessian_reg[6]\(19),
O => \hessian_out2_carry__1_i_7_n_0\
);
\hessian_out2_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[11]\(16),
I3 => \hessian_reg[6]\(17),
O => \hessian_out2_carry__1_i_8_n_0\
);
\hessian_out2_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out2_carry__1_n_0\,
CO(3) => \hessian_out2_carry__2_n_0\,
CO(2) => \hessian_out2_carry__2_n_1\,
CO(1) => \hessian_out2_carry__2_n_2\,
CO(0) => \hessian_out2_carry__2_n_3\,
CYINIT => '0',
DI(3) => \hessian_out2_carry__2_i_1_n_0\,
DI(2) => \hessian_out2_carry__2_i_2_n_0\,
DI(1) => \hessian_out2_carry__2_i_3_n_0\,
DI(0) => \hessian_out2_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out2_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out2_carry__2_i_5_n_0\,
S(2) => \hessian_out2_carry__2_i_6_n_0\,
S(1) => \hessian_out2_carry__2_i_7_n_0\,
S(0) => \hessian_out2_carry__2_i_8_n_0\
);
\hessian_out2_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[11]\(30),
I3 => \hessian_reg[6]\(31),
O => \hessian_out2_carry__2_i_1_n_0\
);
\hessian_out2_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[11]\(28),
I3 => \hessian_reg[6]\(29),
O => \hessian_out2_carry__2_i_2_n_0\
);
\hessian_out2_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[11]\(26),
I3 => \hessian_reg[6]\(27),
O => \hessian_out2_carry__2_i_3_n_0\
);
\hessian_out2_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[11]\(24),
I3 => \hessian_reg[6]\(25),
O => \hessian_out2_carry__2_i_4_n_0\
);
\hessian_out2_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[11]\(30),
I3 => \hessian_reg[6]\(31),
O => \hessian_out2_carry__2_i_5_n_0\
);
\hessian_out2_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[11]\(28),
I3 => \hessian_reg[6]\(29),
O => \hessian_out2_carry__2_i_6_n_0\
);
\hessian_out2_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[11]\(26),
I3 => \hessian_reg[6]\(27),
O => \hessian_out2_carry__2_i_7_n_0\
);
\hessian_out2_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[11]\(24),
I3 => \hessian_reg[6]\(25),
O => \hessian_out2_carry__2_i_8_n_0\
);
hessian_out2_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[11]\(6),
I3 => \hessian_reg[6]\(7),
O => hessian_out2_carry_i_1_n_0
);
hessian_out2_carry_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[11]\(4),
I3 => \hessian_reg[6]\(5),
O => hessian_out2_carry_i_2_n_0
);
hessian_out2_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[11]\(2),
I3 => \hessian_reg[6]\(3),
O => hessian_out2_carry_i_3_n_0
);
hessian_out2_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[11]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[11]\(0),
I3 => \hessian_reg[6]\(1),
O => hessian_out2_carry_i_4_n_0
);
hessian_out2_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[11]\(6),
I3 => \hessian_reg[6]\(7),
O => hessian_out2_carry_i_5_n_0
);
hessian_out2_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[11]\(4),
I3 => \hessian_reg[6]\(5),
O => hessian_out2_carry_i_6_n_0
);
hessian_out2_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[11]\(2),
I3 => \hessian_reg[6]\(3),
O => hessian_out2_carry_i_7_n_0
);
hessian_out2_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[11]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[11]\(0),
I3 => \hessian_reg[6]\(1),
O => hessian_out2_carry_i_8_n_0
);
hessian_out3_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => hessian_out3_carry_n_0,
CO(2) => hessian_out3_carry_n_1,
CO(1) => hessian_out3_carry_n_2,
CO(0) => hessian_out3_carry_n_3,
CYINIT => '0',
DI(3) => hessian_out3_carry_i_1_n_0,
DI(2) => hessian_out3_carry_i_2_n_0,
DI(1) => hessian_out3_carry_i_3_n_0,
DI(0) => hessian_out3_carry_i_4_n_0,
O(3 downto 0) => NLW_hessian_out3_carry_O_UNCONNECTED(3 downto 0),
S(3) => hessian_out3_carry_i_5_n_0,
S(2) => hessian_out3_carry_i_6_n_0,
S(1) => hessian_out3_carry_i_7_n_0,
S(0) => hessian_out3_carry_i_8_n_0
);
\hessian_out3_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => hessian_out3_carry_n_0,
CO(3) => \hessian_out3_carry__0_n_0\,
CO(2) => \hessian_out3_carry__0_n_1\,
CO(1) => \hessian_out3_carry__0_n_2\,
CO(0) => \hessian_out3_carry__0_n_3\,
CYINIT => '0',
DI(3) => \hessian_out3_carry__0_i_1_n_0\,
DI(2) => \hessian_out3_carry__0_i_2_n_0\,
DI(1) => \hessian_out3_carry__0_i_3_n_0\,
DI(0) => \hessian_out3_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out3_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out3_carry__0_i_5_n_0\,
S(2) => \hessian_out3_carry__0_i_6_n_0\,
S(1) => \hessian_out3_carry__0_i_7_n_0\,
S(0) => \hessian_out3_carry__0_i_8_n_0\
);
\hessian_out3_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[10]\(14),
I3 => \hessian_reg[6]\(15),
O => \hessian_out3_carry__0_i_1_n_0\
);
\hessian_out3_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[10]\(12),
I3 => \hessian_reg[6]\(13),
O => \hessian_out3_carry__0_i_2_n_0\
);
\hessian_out3_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[10]\(10),
I3 => \hessian_reg[6]\(11),
O => \hessian_out3_carry__0_i_3_n_0\
);
\hessian_out3_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[10]\(8),
I3 => \hessian_reg[6]\(9),
O => \hessian_out3_carry__0_i_4_n_0\
);
\hessian_out3_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[10]\(14),
I3 => \hessian_reg[6]\(15),
O => \hessian_out3_carry__0_i_5_n_0\
);
\hessian_out3_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[10]\(12),
I3 => \hessian_reg[6]\(13),
O => \hessian_out3_carry__0_i_6_n_0\
);
\hessian_out3_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[10]\(10),
I3 => \hessian_reg[6]\(11),
O => \hessian_out3_carry__0_i_7_n_0\
);
\hessian_out3_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[10]\(8),
I3 => \hessian_reg[6]\(9),
O => \hessian_out3_carry__0_i_8_n_0\
);
\hessian_out3_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out3_carry__0_n_0\,
CO(3) => \hessian_out3_carry__1_n_0\,
CO(2) => \hessian_out3_carry__1_n_1\,
CO(1) => \hessian_out3_carry__1_n_2\,
CO(0) => \hessian_out3_carry__1_n_3\,
CYINIT => '0',
DI(3) => \hessian_out3_carry__1_i_1_n_0\,
DI(2) => \hessian_out3_carry__1_i_2_n_0\,
DI(1) => \hessian_out3_carry__1_i_3_n_0\,
DI(0) => \hessian_out3_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out3_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out3_carry__1_i_5_n_0\,
S(2) => \hessian_out3_carry__1_i_6_n_0\,
S(1) => \hessian_out3_carry__1_i_7_n_0\,
S(0) => \hessian_out3_carry__1_i_8_n_0\
);
\hessian_out3_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[10]\(22),
I3 => \hessian_reg[6]\(23),
O => \hessian_out3_carry__1_i_1_n_0\
);
\hessian_out3_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[10]\(20),
I3 => \hessian_reg[6]\(21),
O => \hessian_out3_carry__1_i_2_n_0\
);
\hessian_out3_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[10]\(18),
I3 => \hessian_reg[6]\(19),
O => \hessian_out3_carry__1_i_3_n_0\
);
\hessian_out3_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[10]\(16),
I3 => \hessian_reg[6]\(17),
O => \hessian_out3_carry__1_i_4_n_0\
);
\hessian_out3_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[10]\(22),
I3 => \hessian_reg[6]\(23),
O => \hessian_out3_carry__1_i_5_n_0\
);
\hessian_out3_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[10]\(20),
I3 => \hessian_reg[6]\(21),
O => \hessian_out3_carry__1_i_6_n_0\
);
\hessian_out3_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[10]\(18),
I3 => \hessian_reg[6]\(19),
O => \hessian_out3_carry__1_i_7_n_0\
);
\hessian_out3_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[10]\(16),
I3 => \hessian_reg[6]\(17),
O => \hessian_out3_carry__1_i_8_n_0\
);
\hessian_out3_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out3_carry__1_n_0\,
CO(3) => \hessian_out3_carry__2_n_0\,
CO(2) => \hessian_out3_carry__2_n_1\,
CO(1) => \hessian_out3_carry__2_n_2\,
CO(0) => \hessian_out3_carry__2_n_3\,
CYINIT => '0',
DI(3) => \hessian_out3_carry__2_i_1_n_0\,
DI(2) => \hessian_out3_carry__2_i_2_n_0\,
DI(1) => \hessian_out3_carry__2_i_3_n_0\,
DI(0) => \hessian_out3_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out3_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out3_carry__2_i_5_n_0\,
S(2) => \hessian_out3_carry__2_i_6_n_0\,
S(1) => \hessian_out3_carry__2_i_7_n_0\,
S(0) => \hessian_out3_carry__2_i_8_n_0\
);
\hessian_out3_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[10]\(30),
I3 => \hessian_reg[6]\(31),
O => \hessian_out3_carry__2_i_1_n_0\
);
\hessian_out3_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[10]\(28),
I3 => \hessian_reg[6]\(29),
O => \hessian_out3_carry__2_i_2_n_0\
);
\hessian_out3_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[10]\(26),
I3 => \hessian_reg[6]\(27),
O => \hessian_out3_carry__2_i_3_n_0\
);
\hessian_out3_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[10]\(24),
I3 => \hessian_reg[6]\(25),
O => \hessian_out3_carry__2_i_4_n_0\
);
\hessian_out3_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[10]\(30),
I3 => \hessian_reg[6]\(31),
O => \hessian_out3_carry__2_i_5_n_0\
);
\hessian_out3_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[10]\(28),
I3 => \hessian_reg[6]\(29),
O => \hessian_out3_carry__2_i_6_n_0\
);
\hessian_out3_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[10]\(26),
I3 => \hessian_reg[6]\(27),
O => \hessian_out3_carry__2_i_7_n_0\
);
\hessian_out3_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[10]\(24),
I3 => \hessian_reg[6]\(25),
O => \hessian_out3_carry__2_i_8_n_0\
);
hessian_out3_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[10]\(6),
I3 => \hessian_reg[6]\(7),
O => hessian_out3_carry_i_1_n_0
);
hessian_out3_carry_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[10]\(4),
I3 => \hessian_reg[6]\(5),
O => hessian_out3_carry_i_2_n_0
);
hessian_out3_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[10]\(2),
I3 => \hessian_reg[6]\(3),
O => hessian_out3_carry_i_3_n_0
);
hessian_out3_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[10]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[10]\(0),
I3 => \hessian_reg[6]\(1),
O => hessian_out3_carry_i_4_n_0
);
hessian_out3_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[10]\(6),
I3 => \hessian_reg[6]\(7),
O => hessian_out3_carry_i_5_n_0
);
hessian_out3_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[10]\(4),
I3 => \hessian_reg[6]\(5),
O => hessian_out3_carry_i_6_n_0
);
hessian_out3_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[10]\(2),
I3 => \hessian_reg[6]\(3),
O => hessian_out3_carry_i_7_n_0
);
hessian_out3_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[10]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[10]\(0),
I3 => \hessian_reg[6]\(1),
O => hessian_out3_carry_i_8_n_0
);
hessian_out4_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => hessian_out4_carry_n_0,
CO(2) => hessian_out4_carry_n_1,
CO(1) => hessian_out4_carry_n_2,
CO(0) => hessian_out4_carry_n_3,
CYINIT => '0',
DI(3) => hessian_out4_carry_i_1_n_0,
DI(2) => hessian_out4_carry_i_2_n_0,
DI(1) => hessian_out4_carry_i_3_n_0,
DI(0) => hessian_out4_carry_i_4_n_0,
O(3 downto 0) => NLW_hessian_out4_carry_O_UNCONNECTED(3 downto 0),
S(3) => hessian_out4_carry_i_5_n_0,
S(2) => hessian_out4_carry_i_6_n_0,
S(1) => hessian_out4_carry_i_7_n_0,
S(0) => hessian_out4_carry_i_8_n_0
);
\hessian_out4_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => hessian_out4_carry_n_0,
CO(3) => \hessian_out4_carry__0_n_0\,
CO(2) => \hessian_out4_carry__0_n_1\,
CO(1) => \hessian_out4_carry__0_n_2\,
CO(0) => \hessian_out4_carry__0_n_3\,
CYINIT => '0',
DI(3) => \hessian_out4_carry__0_i_1_n_0\,
DI(2) => \hessian_out4_carry__0_i_2_n_0\,
DI(1) => \hessian_out4_carry__0_i_3_n_0\,
DI(0) => \hessian_out4_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out4_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out4_carry__0_i_5_n_0\,
S(2) => \hessian_out4_carry__0_i_6_n_0\,
S(1) => \hessian_out4_carry__0_i_7_n_0\,
S(0) => \hessian_out4_carry__0_i_8_n_0\
);
\hessian_out4_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[9]\(14),
I3 => \hessian_reg[6]\(15),
O => \hessian_out4_carry__0_i_1_n_0\
);
\hessian_out4_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[9]\(12),
I3 => \hessian_reg[6]\(13),
O => \hessian_out4_carry__0_i_2_n_0\
);
\hessian_out4_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[9]\(10),
I3 => \hessian_reg[6]\(11),
O => \hessian_out4_carry__0_i_3_n_0\
);
\hessian_out4_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[9]\(8),
I3 => \hessian_reg[6]\(9),
O => \hessian_out4_carry__0_i_4_n_0\
);
\hessian_out4_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[9]\(14),
I3 => \hessian_reg[6]\(15),
O => \hessian_out4_carry__0_i_5_n_0\
);
\hessian_out4_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[9]\(12),
I3 => \hessian_reg[6]\(13),
O => \hessian_out4_carry__0_i_6_n_0\
);
\hessian_out4_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[9]\(10),
I3 => \hessian_reg[6]\(11),
O => \hessian_out4_carry__0_i_7_n_0\
);
\hessian_out4_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[9]\(8),
I3 => \hessian_reg[6]\(9),
O => \hessian_out4_carry__0_i_8_n_0\
);
\hessian_out4_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out4_carry__0_n_0\,
CO(3) => \hessian_out4_carry__1_n_0\,
CO(2) => \hessian_out4_carry__1_n_1\,
CO(1) => \hessian_out4_carry__1_n_2\,
CO(0) => \hessian_out4_carry__1_n_3\,
CYINIT => '0',
DI(3) => \hessian_out4_carry__1_i_1_n_0\,
DI(2) => \hessian_out4_carry__1_i_2_n_0\,
DI(1) => \hessian_out4_carry__1_i_3_n_0\,
DI(0) => \hessian_out4_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out4_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out4_carry__1_i_5_n_0\,
S(2) => \hessian_out4_carry__1_i_6_n_0\,
S(1) => \hessian_out4_carry__1_i_7_n_0\,
S(0) => \hessian_out4_carry__1_i_8_n_0\
);
\hessian_out4_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[9]\(22),
I3 => \hessian_reg[6]\(23),
O => \hessian_out4_carry__1_i_1_n_0\
);
\hessian_out4_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[9]\(20),
I3 => \hessian_reg[6]\(21),
O => \hessian_out4_carry__1_i_2_n_0\
);
\hessian_out4_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[9]\(18),
I3 => \hessian_reg[6]\(19),
O => \hessian_out4_carry__1_i_3_n_0\
);
\hessian_out4_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[9]\(16),
I3 => \hessian_reg[6]\(17),
O => \hessian_out4_carry__1_i_4_n_0\
);
\hessian_out4_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[9]\(22),
I3 => \hessian_reg[6]\(23),
O => \hessian_out4_carry__1_i_5_n_0\
);
\hessian_out4_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[9]\(20),
I3 => \hessian_reg[6]\(21),
O => \hessian_out4_carry__1_i_6_n_0\
);
\hessian_out4_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[9]\(18),
I3 => \hessian_reg[6]\(19),
O => \hessian_out4_carry__1_i_7_n_0\
);
\hessian_out4_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[9]\(16),
I3 => \hessian_reg[6]\(17),
O => \hessian_out4_carry__1_i_8_n_0\
);
\hessian_out4_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out4_carry__1_n_0\,
CO(3) => \hessian_out4_carry__2_n_0\,
CO(2) => \hessian_out4_carry__2_n_1\,
CO(1) => \hessian_out4_carry__2_n_2\,
CO(0) => \hessian_out4_carry__2_n_3\,
CYINIT => '0',
DI(3) => \hessian_out4_carry__2_i_1_n_0\,
DI(2) => \hessian_out4_carry__2_i_2_n_0\,
DI(1) => \hessian_out4_carry__2_i_3_n_0\,
DI(0) => \hessian_out4_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out4_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out4_carry__2_i_5_n_0\,
S(2) => \hessian_out4_carry__2_i_6_n_0\,
S(1) => \hessian_out4_carry__2_i_7_n_0\,
S(0) => \hessian_out4_carry__2_i_8_n_0\
);
\hessian_out4_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[9]\(30),
I3 => \hessian_reg[6]\(31),
O => \hessian_out4_carry__2_i_1_n_0\
);
\hessian_out4_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[9]\(28),
I3 => \hessian_reg[6]\(29),
O => \hessian_out4_carry__2_i_2_n_0\
);
\hessian_out4_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[9]\(26),
I3 => \hessian_reg[6]\(27),
O => \hessian_out4_carry__2_i_3_n_0\
);
\hessian_out4_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[9]\(24),
I3 => \hessian_reg[6]\(25),
O => \hessian_out4_carry__2_i_4_n_0\
);
\hessian_out4_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[9]\(30),
I3 => \hessian_reg[6]\(31),
O => \hessian_out4_carry__2_i_5_n_0\
);
\hessian_out4_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[9]\(28),
I3 => \hessian_reg[6]\(29),
O => \hessian_out4_carry__2_i_6_n_0\
);
\hessian_out4_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[9]\(26),
I3 => \hessian_reg[6]\(27),
O => \hessian_out4_carry__2_i_7_n_0\
);
\hessian_out4_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[9]\(24),
I3 => \hessian_reg[6]\(25),
O => \hessian_out4_carry__2_i_8_n_0\
);
hessian_out4_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[9]\(6),
I3 => \hessian_reg[6]\(7),
O => hessian_out4_carry_i_1_n_0
);
hessian_out4_carry_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[9]\(4),
I3 => \hessian_reg[6]\(5),
O => hessian_out4_carry_i_2_n_0
);
hessian_out4_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[9]\(2),
I3 => \hessian_reg[6]\(3),
O => hessian_out4_carry_i_3_n_0
);
hessian_out4_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[9]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[9]\(0),
I3 => \hessian_reg[6]\(1),
O => hessian_out4_carry_i_4_n_0
);
hessian_out4_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[9]\(6),
I3 => \hessian_reg[6]\(7),
O => hessian_out4_carry_i_5_n_0
);
hessian_out4_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[9]\(4),
I3 => \hessian_reg[6]\(5),
O => hessian_out4_carry_i_6_n_0
);
hessian_out4_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[9]\(2),
I3 => \hessian_reg[6]\(3),
O => hessian_out4_carry_i_7_n_0
);
hessian_out4_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[9]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[9]\(0),
I3 => \hessian_reg[6]\(1),
O => hessian_out4_carry_i_8_n_0
);
hessian_out5_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => hessian_out5_carry_n_0,
CO(2) => hessian_out5_carry_n_1,
CO(1) => hessian_out5_carry_n_2,
CO(0) => hessian_out5_carry_n_3,
CYINIT => '0',
DI(3) => hessian_out5_carry_i_1_n_0,
DI(2) => hessian_out5_carry_i_2_n_0,
DI(1) => hessian_out5_carry_i_3_n_0,
DI(0) => hessian_out5_carry_i_4_n_0,
O(3 downto 0) => NLW_hessian_out5_carry_O_UNCONNECTED(3 downto 0),
S(3) => hessian_out5_carry_i_5_n_0,
S(2) => hessian_out5_carry_i_6_n_0,
S(1) => hessian_out5_carry_i_7_n_0,
S(0) => hessian_out5_carry_i_8_n_0
);
\hessian_out5_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => hessian_out5_carry_n_0,
CO(3) => \hessian_out5_carry__0_n_0\,
CO(2) => \hessian_out5_carry__0_n_1\,
CO(1) => \hessian_out5_carry__0_n_2\,
CO(0) => \hessian_out5_carry__0_n_3\,
CYINIT => '0',
DI(3) => \hessian_out5_carry__0_i_1_n_0\,
DI(2) => \hessian_out5_carry__0_i_2_n_0\,
DI(1) => \hessian_out5_carry__0_i_3_n_0\,
DI(0) => \hessian_out5_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out5_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out5_carry__0_i_5_n_0\,
S(2) => \hessian_out5_carry__0_i_6_n_0\,
S(1) => \hessian_out5_carry__0_i_7_n_0\,
S(0) => \hessian_out5_carry__0_i_8_n_0\
);
\hessian_out5_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[7]\(14),
I3 => \hessian_reg[7]\(15),
O => \hessian_out5_carry__0_i_1_n_0\
);
\hessian_out5_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[7]\(12),
I3 => \hessian_reg[7]\(13),
O => \hessian_out5_carry__0_i_2_n_0\
);
\hessian_out5_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[7]\(10),
I3 => \hessian_reg[7]\(11),
O => \hessian_out5_carry__0_i_3_n_0\
);
\hessian_out5_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[7]\(8),
I3 => \hessian_reg[7]\(9),
O => \hessian_out5_carry__0_i_4_n_0\
);
\hessian_out5_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[7]\(14),
I3 => \hessian_reg[7]\(15),
O => \hessian_out5_carry__0_i_5_n_0\
);
\hessian_out5_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[7]\(12),
I3 => \hessian_reg[7]\(13),
O => \hessian_out5_carry__0_i_6_n_0\
);
\hessian_out5_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[7]\(10),
I3 => \hessian_reg[7]\(11),
O => \hessian_out5_carry__0_i_7_n_0\
);
\hessian_out5_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[7]\(8),
I3 => \hessian_reg[7]\(9),
O => \hessian_out5_carry__0_i_8_n_0\
);
\hessian_out5_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out5_carry__0_n_0\,
CO(3) => \hessian_out5_carry__1_n_0\,
CO(2) => \hessian_out5_carry__1_n_1\,
CO(1) => \hessian_out5_carry__1_n_2\,
CO(0) => \hessian_out5_carry__1_n_3\,
CYINIT => '0',
DI(3) => \hessian_out5_carry__1_i_1_n_0\,
DI(2) => \hessian_out5_carry__1_i_2_n_0\,
DI(1) => \hessian_out5_carry__1_i_3_n_0\,
DI(0) => \hessian_out5_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out5_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out5_carry__1_i_5_n_0\,
S(2) => \hessian_out5_carry__1_i_6_n_0\,
S(1) => \hessian_out5_carry__1_i_7_n_0\,
S(0) => \hessian_out5_carry__1_i_8_n_0\
);
\hessian_out5_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[7]\(22),
I3 => \hessian_reg[7]\(23),
O => \hessian_out5_carry__1_i_1_n_0\
);
\hessian_out5_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[7]\(20),
I3 => \hessian_reg[7]\(21),
O => \hessian_out5_carry__1_i_2_n_0\
);
\hessian_out5_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[7]\(18),
I3 => \hessian_reg[7]\(19),
O => \hessian_out5_carry__1_i_3_n_0\
);
\hessian_out5_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[7]\(16),
I3 => \hessian_reg[7]\(17),
O => \hessian_out5_carry__1_i_4_n_0\
);
\hessian_out5_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[7]\(22),
I3 => \hessian_reg[7]\(23),
O => \hessian_out5_carry__1_i_5_n_0\
);
\hessian_out5_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[7]\(20),
I3 => \hessian_reg[7]\(21),
O => \hessian_out5_carry__1_i_6_n_0\
);
\hessian_out5_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[7]\(18),
I3 => \hessian_reg[7]\(19),
O => \hessian_out5_carry__1_i_7_n_0\
);
\hessian_out5_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[7]\(16),
I3 => \hessian_reg[7]\(17),
O => \hessian_out5_carry__1_i_8_n_0\
);
\hessian_out5_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out5_carry__1_n_0\,
CO(3) => \hessian_out5_carry__2_n_0\,
CO(2) => \hessian_out5_carry__2_n_1\,
CO(1) => \hessian_out5_carry__2_n_2\,
CO(0) => \hessian_out5_carry__2_n_3\,
CYINIT => '0',
DI(3) => \hessian_out5_carry__2_i_1_n_0\,
DI(2) => \hessian_out5_carry__2_i_2_n_0\,
DI(1) => \hessian_out5_carry__2_i_3_n_0\,
DI(0) => \hessian_out5_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out5_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out5_carry__2_i_5_n_0\,
S(2) => \hessian_out5_carry__2_i_6_n_0\,
S(1) => \hessian_out5_carry__2_i_7_n_0\,
S(0) => \hessian_out5_carry__2_i_8_n_0\
);
\hessian_out5_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[7]\(30),
I3 => \hessian_reg[7]\(31),
O => \hessian_out5_carry__2_i_1_n_0\
);
\hessian_out5_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[7]\(28),
I3 => \hessian_reg[7]\(29),
O => \hessian_out5_carry__2_i_2_n_0\
);
\hessian_out5_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[7]\(26),
I3 => \hessian_reg[7]\(27),
O => \hessian_out5_carry__2_i_3_n_0\
);
\hessian_out5_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[7]\(24),
I3 => \hessian_reg[7]\(25),
O => \hessian_out5_carry__2_i_4_n_0\
);
\hessian_out5_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[7]\(30),
I3 => \hessian_reg[7]\(31),
O => \hessian_out5_carry__2_i_5_n_0\
);
\hessian_out5_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[7]\(28),
I3 => \hessian_reg[7]\(29),
O => \hessian_out5_carry__2_i_6_n_0\
);
\hessian_out5_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[7]\(26),
I3 => \hessian_reg[7]\(27),
O => \hessian_out5_carry__2_i_7_n_0\
);
\hessian_out5_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[7]\(24),
I3 => \hessian_reg[7]\(25),
O => \hessian_out5_carry__2_i_8_n_0\
);
hessian_out5_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[7]\(6),
I3 => \hessian_reg[7]\(7),
O => hessian_out5_carry_i_1_n_0
);
hessian_out5_carry_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[7]\(4),
I3 => \hessian_reg[7]\(5),
O => hessian_out5_carry_i_2_n_0
);
hessian_out5_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[7]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[7]\(2),
I3 => \hessian_reg[6]\(3),
O => hessian_out5_carry_i_3_n_0
);
hessian_out5_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => \hessian_reg[7]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[7]\(0),
I3 => \hessian_reg[6]\(1),
O => hessian_out5_carry_i_4_n_0
);
hessian_out5_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[7]\(6),
I3 => \hessian_reg[7]\(7),
O => hessian_out5_carry_i_5_n_0
);
hessian_out5_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[7]\(4),
I3 => \hessian_reg[7]\(5),
O => hessian_out5_carry_i_6_n_0
);
hessian_out5_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[7]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[7]\(2),
I3 => \hessian_reg[6]\(3),
O => hessian_out5_carry_i_7_n_0
);
hessian_out5_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[7]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[7]\(0),
I3 => \hessian_reg[6]\(1),
O => hessian_out5_carry_i_8_n_0
);
hessian_out6_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => hessian_out6_carry_n_0,
CO(2) => hessian_out6_carry_n_1,
CO(1) => hessian_out6_carry_n_2,
CO(0) => hessian_out6_carry_n_3,
CYINIT => '0',
DI(3) => hessian_out6_carry_i_1_n_0,
DI(2) => hessian_out6_carry_i_2_n_0,
DI(1) => hessian_out6_carry_i_3_n_0,
DI(0) => hessian_out6_carry_i_4_n_0,
O(3 downto 0) => NLW_hessian_out6_carry_O_UNCONNECTED(3 downto 0),
S(3) => hessian_out6_carry_i_5_n_0,
S(2) => hessian_out6_carry_i_6_n_0,
S(1) => hessian_out6_carry_i_7_n_0,
S(0) => hessian_out6_carry_i_8_n_0
);
\hessian_out6_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => hessian_out6_carry_n_0,
CO(3) => \hessian_out6_carry__0_n_0\,
CO(2) => \hessian_out6_carry__0_n_1\,
CO(1) => \hessian_out6_carry__0_n_2\,
CO(0) => \hessian_out6_carry__0_n_3\,
CYINIT => '0',
DI(3) => \hessian_out6_carry__0_i_1_n_0\,
DI(2) => \hessian_out6_carry__0_i_2_n_0\,
DI(1) => \hessian_out6_carry__0_i_3_n_0\,
DI(0) => \hessian_out6_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out6_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out6_carry__0_i_5_n_0\,
S(2) => \hessian_out6_carry__0_i_6_n_0\,
S(1) => \hessian_out6_carry__0_i_7_n_0\,
S(0) => \hessian_out6_carry__0_i_8_n_0\
);
\hessian_out6_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[5]\(14),
I3 => \hessian_reg[5]\(15),
O => \hessian_out6_carry__0_i_1_n_0\
);
\hessian_out6_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[5]\(12),
I3 => \hessian_reg[5]\(13),
O => \hessian_out6_carry__0_i_2_n_0\
);
\hessian_out6_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[5]\(10),
I3 => \hessian_reg[5]\(11),
O => \hessian_out6_carry__0_i_3_n_0\
);
\hessian_out6_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[5]\(8),
I3 => \hessian_reg[5]\(9),
O => \hessian_out6_carry__0_i_4_n_0\
);
\hessian_out6_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[5]\(14),
I3 => \hessian_reg[5]\(15),
O => \hessian_out6_carry__0_i_5_n_0\
);
\hessian_out6_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[5]\(12),
I3 => \hessian_reg[5]\(13),
O => \hessian_out6_carry__0_i_6_n_0\
);
\hessian_out6_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[5]\(10),
I3 => \hessian_reg[5]\(11),
O => \hessian_out6_carry__0_i_7_n_0\
);
\hessian_out6_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[5]\(8),
I3 => \hessian_reg[5]\(9),
O => \hessian_out6_carry__0_i_8_n_0\
);
\hessian_out6_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out6_carry__0_n_0\,
CO(3) => \hessian_out6_carry__1_n_0\,
CO(2) => \hessian_out6_carry__1_n_1\,
CO(1) => \hessian_out6_carry__1_n_2\,
CO(0) => \hessian_out6_carry__1_n_3\,
CYINIT => '0',
DI(3) => \hessian_out6_carry__1_i_1_n_0\,
DI(2) => \hessian_out6_carry__1_i_2_n_0\,
DI(1) => \hessian_out6_carry__1_i_3_n_0\,
DI(0) => \hessian_out6_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out6_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out6_carry__1_i_5_n_0\,
S(2) => \hessian_out6_carry__1_i_6_n_0\,
S(1) => \hessian_out6_carry__1_i_7_n_0\,
S(0) => \hessian_out6_carry__1_i_8_n_0\
);
\hessian_out6_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[5]\(22),
I3 => \hessian_reg[5]\(23),
O => \hessian_out6_carry__1_i_1_n_0\
);
\hessian_out6_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[5]\(20),
I3 => \hessian_reg[5]\(21),
O => \hessian_out6_carry__1_i_2_n_0\
);
\hessian_out6_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[5]\(18),
I3 => \hessian_reg[5]\(19),
O => \hessian_out6_carry__1_i_3_n_0\
);
\hessian_out6_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[5]\(16),
I3 => \hessian_reg[5]\(17),
O => \hessian_out6_carry__1_i_4_n_0\
);
\hessian_out6_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[5]\(22),
I3 => \hessian_reg[5]\(23),
O => \hessian_out6_carry__1_i_5_n_0\
);
\hessian_out6_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[5]\(20),
I3 => \hessian_reg[5]\(21),
O => \hessian_out6_carry__1_i_6_n_0\
);
\hessian_out6_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[5]\(18),
I3 => \hessian_reg[5]\(19),
O => \hessian_out6_carry__1_i_7_n_0\
);
\hessian_out6_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[5]\(16),
I3 => \hessian_reg[5]\(17),
O => \hessian_out6_carry__1_i_8_n_0\
);
\hessian_out6_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out6_carry__1_n_0\,
CO(3) => \hessian_out6_carry__2_n_0\,
CO(2) => \hessian_out6_carry__2_n_1\,
CO(1) => \hessian_out6_carry__2_n_2\,
CO(0) => \hessian_out6_carry__2_n_3\,
CYINIT => '0',
DI(3) => \hessian_out6_carry__2_i_1_n_0\,
DI(2) => \hessian_out6_carry__2_i_2_n_0\,
DI(1) => \hessian_out6_carry__2_i_3_n_0\,
DI(0) => \hessian_out6_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out6_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out6_carry__2_i_5_n_0\,
S(2) => \hessian_out6_carry__2_i_6_n_0\,
S(1) => \hessian_out6_carry__2_i_7_n_0\,
S(0) => \hessian_out6_carry__2_i_8_n_0\
);
\hessian_out6_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[5]\(30),
I3 => \hessian_reg[5]\(31),
O => \hessian_out6_carry__2_i_1_n_0\
);
\hessian_out6_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[5]\(28),
I3 => \hessian_reg[5]\(29),
O => \hessian_out6_carry__2_i_2_n_0\
);
\hessian_out6_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[5]\(26),
I3 => \hessian_reg[5]\(27),
O => \hessian_out6_carry__2_i_3_n_0\
);
\hessian_out6_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[5]\(24),
I3 => \hessian_reg[5]\(25),
O => \hessian_out6_carry__2_i_4_n_0\
);
\hessian_out6_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[5]\(30),
I3 => \hessian_reg[5]\(31),
O => \hessian_out6_carry__2_i_5_n_0\
);
\hessian_out6_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[5]\(28),
I3 => \hessian_reg[5]\(29),
O => \hessian_out6_carry__2_i_6_n_0\
);
\hessian_out6_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[5]\(26),
I3 => \hessian_reg[5]\(27),
O => \hessian_out6_carry__2_i_7_n_0\
);
\hessian_out6_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[5]\(24),
I3 => \hessian_reg[5]\(25),
O => \hessian_out6_carry__2_i_8_n_0\
);
hessian_out6_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[5]\(6),
I3 => \hessian_reg[5]\(7),
O => hessian_out6_carry_i_1_n_0
);
hessian_out6_carry_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[5]\(4),
I3 => \hessian_reg[5]\(5),
O => hessian_out6_carry_i_2_n_0
);
hessian_out6_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[5]\(2),
I3 => \hessian_reg[5]\(3),
O => hessian_out6_carry_i_3_n_0
);
hessian_out6_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[5]\(0),
I3 => \hessian_reg[5]\(1),
O => hessian_out6_carry_i_4_n_0
);
hessian_out6_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[5]\(6),
I3 => \hessian_reg[5]\(7),
O => hessian_out6_carry_i_5_n_0
);
hessian_out6_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[5]\(4),
I3 => \hessian_reg[5]\(5),
O => hessian_out6_carry_i_6_n_0
);
hessian_out6_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[5]\(2),
I3 => \hessian_reg[5]\(3),
O => hessian_out6_carry_i_7_n_0
);
hessian_out6_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[5]\(0),
I3 => \hessian_reg[5]\(1),
O => hessian_out6_carry_i_8_n_0
);
hessian_out7_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => hessian_out7_carry_n_0,
CO(2) => hessian_out7_carry_n_1,
CO(1) => hessian_out7_carry_n_2,
CO(0) => hessian_out7_carry_n_3,
CYINIT => '0',
DI(3) => hessian_out7_carry_i_1_n_0,
DI(2) => hessian_out7_carry_i_2_n_0,
DI(1) => hessian_out7_carry_i_3_n_0,
DI(0) => hessian_out7_carry_i_4_n_0,
O(3 downto 0) => NLW_hessian_out7_carry_O_UNCONNECTED(3 downto 0),
S(3) => hessian_out7_carry_i_5_n_0,
S(2) => hessian_out7_carry_i_6_n_0,
S(1) => hessian_out7_carry_i_7_n_0,
S(0) => hessian_out7_carry_i_8_n_0
);
\hessian_out7_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => hessian_out7_carry_n_0,
CO(3) => \hessian_out7_carry__0_n_0\,
CO(2) => \hessian_out7_carry__0_n_1\,
CO(1) => \hessian_out7_carry__0_n_2\,
CO(0) => \hessian_out7_carry__0_n_3\,
CYINIT => '0',
DI(3) => \hessian_out7_carry__0_i_1_n_0\,
DI(2) => \hessian_out7_carry__0_i_2_n_0\,
DI(1) => \hessian_out7_carry__0_i_3_n_0\,
DI(0) => \hessian_out7_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out7_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out7_carry__0_i_5_n_0\,
S(2) => \hessian_out7_carry__0_i_6_n_0\,
S(1) => \hessian_out7_carry__0_i_7_n_0\,
S(0) => \hessian_out7_carry__0_i_8_n_0\
);
\hessian_out7_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[1]\(14),
I3 => \hessian_reg[1]\(15),
O => \hessian_out7_carry__0_i_1_n_0\
);
\hessian_out7_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[1]\(12),
I3 => \hessian_reg[1]\(13),
O => \hessian_out7_carry__0_i_2_n_0\
);
\hessian_out7_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[1]\(10),
I3 => \hessian_reg[1]\(11),
O => \hessian_out7_carry__0_i_3_n_0\
);
\hessian_out7_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[1]\(8),
I3 => \hessian_reg[1]\(9),
O => \hessian_out7_carry__0_i_4_n_0\
);
\hessian_out7_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[1]\(14),
I3 => \hessian_reg[1]\(15),
O => \hessian_out7_carry__0_i_5_n_0\
);
\hessian_out7_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[1]\(12),
I3 => \hessian_reg[1]\(13),
O => \hessian_out7_carry__0_i_6_n_0\
);
\hessian_out7_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[1]\(10),
I3 => \hessian_reg[1]\(11),
O => \hessian_out7_carry__0_i_7_n_0\
);
\hessian_out7_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[1]\(8),
I3 => \hessian_reg[1]\(9),
O => \hessian_out7_carry__0_i_8_n_0\
);
\hessian_out7_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out7_carry__0_n_0\,
CO(3) => \hessian_out7_carry__1_n_0\,
CO(2) => \hessian_out7_carry__1_n_1\,
CO(1) => \hessian_out7_carry__1_n_2\,
CO(0) => \hessian_out7_carry__1_n_3\,
CYINIT => '0',
DI(3) => \hessian_out7_carry__1_i_1_n_0\,
DI(2) => \hessian_out7_carry__1_i_2_n_0\,
DI(1) => \hessian_out7_carry__1_i_3_n_0\,
DI(0) => \hessian_out7_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out7_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out7_carry__1_i_5_n_0\,
S(2) => \hessian_out7_carry__1_i_6_n_0\,
S(1) => \hessian_out7_carry__1_i_7_n_0\,
S(0) => \hessian_out7_carry__1_i_8_n_0\
);
\hessian_out7_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[1]\(22),
I3 => \hessian_reg[1]\(23),
O => \hessian_out7_carry__1_i_1_n_0\
);
\hessian_out7_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[1]\(20),
I3 => \hessian_reg[1]\(21),
O => \hessian_out7_carry__1_i_2_n_0\
);
\hessian_out7_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[1]\(18),
I3 => \hessian_reg[1]\(19),
O => \hessian_out7_carry__1_i_3_n_0\
);
\hessian_out7_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[1]\(16),
I3 => \hessian_reg[1]\(17),
O => \hessian_out7_carry__1_i_4_n_0\
);
\hessian_out7_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[1]\(22),
I3 => \hessian_reg[1]\(23),
O => \hessian_out7_carry__1_i_5_n_0\
);
\hessian_out7_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[1]\(20),
I3 => \hessian_reg[1]\(21),
O => \hessian_out7_carry__1_i_6_n_0\
);
\hessian_out7_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[1]\(18),
I3 => \hessian_reg[1]\(19),
O => \hessian_out7_carry__1_i_7_n_0\
);
\hessian_out7_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[1]\(16),
I3 => \hessian_reg[1]\(17),
O => \hessian_out7_carry__1_i_8_n_0\
);
\hessian_out7_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out7_carry__1_n_0\,
CO(3) => \hessian_out7_carry__2_n_0\,
CO(2) => \hessian_out7_carry__2_n_1\,
CO(1) => \hessian_out7_carry__2_n_2\,
CO(0) => \hessian_out7_carry__2_n_3\,
CYINIT => '0',
DI(3) => \hessian_out7_carry__2_i_1_n_0\,
DI(2) => \hessian_out7_carry__2_i_2_n_0\,
DI(1) => \hessian_out7_carry__2_i_3_n_0\,
DI(0) => \hessian_out7_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out7_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out7_carry__2_i_5_n_0\,
S(2) => \hessian_out7_carry__2_i_6_n_0\,
S(1) => \hessian_out7_carry__2_i_7_n_0\,
S(0) => \hessian_out7_carry__2_i_8_n_0\
);
\hessian_out7_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[1]\(30),
I3 => \hessian_reg[1]\(31),
O => \hessian_out7_carry__2_i_1_n_0\
);
\hessian_out7_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[1]\(28),
I3 => \hessian_reg[1]\(29),
O => \hessian_out7_carry__2_i_2_n_0\
);
\hessian_out7_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[1]\(26),
I3 => \hessian_reg[1]\(27),
O => \hessian_out7_carry__2_i_3_n_0\
);
\hessian_out7_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[1]\(24),
I3 => \hessian_reg[1]\(25),
O => \hessian_out7_carry__2_i_4_n_0\
);
\hessian_out7_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(31),
I1 => \hessian_reg[1]\(30),
I2 => \hessian_reg[6]\(30),
I3 => \hessian_reg[1]\(31),
O => \hessian_out7_carry__2_i_5_n_0\
);
\hessian_out7_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[1]\(28),
I3 => \hessian_reg[1]\(29),
O => \hessian_out7_carry__2_i_6_n_0\
);
\hessian_out7_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[1]\(26),
I3 => \hessian_reg[1]\(27),
O => \hessian_out7_carry__2_i_7_n_0\
);
\hessian_out7_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[1]\(24),
I3 => \hessian_reg[1]\(25),
O => \hessian_out7_carry__2_i_8_n_0\
);
hessian_out7_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[1]\(6),
I3 => \hessian_reg[1]\(7),
O => hessian_out7_carry_i_1_n_0
);
hessian_out7_carry_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[1]\(4),
I3 => \hessian_reg[1]\(5),
O => hessian_out7_carry_i_2_n_0
);
hessian_out7_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[1]\(2),
I3 => \hessian_reg[1]\(3),
O => hessian_out7_carry_i_3_n_0
);
hessian_out7_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[1]\(0),
I3 => \hessian_reg[1]\(1),
O => hessian_out7_carry_i_4_n_0
);
hessian_out7_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[1]\(6),
I3 => \hessian_reg[1]\(7),
O => hessian_out7_carry_i_5_n_0
);
hessian_out7_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[1]\(4),
I3 => \hessian_reg[1]\(5),
O => hessian_out7_carry_i_6_n_0
);
hessian_out7_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[1]\(2),
I3 => \hessian_reg[1]\(3),
O => hessian_out7_carry_i_7_n_0
);
hessian_out7_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[1]\(0),
I3 => \hessian_reg[1]\(1),
O => hessian_out7_carry_i_8_n_0
);
\hessian_out8__15_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \hessian_out8__15_carry_n_0\,
CO(2) => \hessian_out8__15_carry_n_1\,
CO(1) => \hessian_out8__15_carry_n_2\,
CO(0) => \hessian_out8__15_carry_n_3\,
CYINIT => '0',
DI(3) => \hessian_out8__15_carry_i_1_n_0\,
DI(2) => \hessian_out8__15_carry_i_2_n_0\,
DI(1) => \hessian_out8__15_carry_i_3_n_0\,
DI(0) => \hessian_out8__15_carry_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out8__15_carry_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out8__15_carry_i_5_n_0\,
S(2) => \hessian_out8__15_carry_i_6_n_0\,
S(1) => \hessian_out8__15_carry_i_7_n_0\,
S(0) => \hessian_out8__15_carry_i_8_n_0\
);
\hessian_out8__15_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out8__15_carry_n_0\,
CO(3) => \hessian_out8__15_carry__0_n_0\,
CO(2) => \hessian_out8__15_carry__0_n_1\,
CO(1) => \hessian_out8__15_carry__0_n_2\,
CO(0) => \hessian_out8__15_carry__0_n_3\,
CYINIT => '0',
DI(3) => \hessian_out8__15_carry__0_i_1_n_0\,
DI(2) => \hessian_out8__15_carry__0_i_2_n_0\,
DI(1) => \hessian_out8__15_carry__0_i_3_n_0\,
DI(0) => \hessian_out8__15_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out8__15_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out8__15_carry__0_i_5_n_0\,
S(2) => \hessian_out8__15_carry__0_i_6_n_0\,
S(1) => \hessian_out8__15_carry__0_i_7_n_0\,
S(0) => \hessian_out8__15_carry__0_i_8_n_0\
);
\hessian_out8__15_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(15),
I1 => \hessian_reg[6]\(14),
I2 => hessian_in(14),
I3 => \hessian_reg[6]\(15),
O => \hessian_out8__15_carry__0_i_1_n_0\
);
\hessian_out8__15_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(13),
I1 => \hessian_reg[6]\(12),
I2 => hessian_in(12),
I3 => \hessian_reg[6]\(13),
O => \hessian_out8__15_carry__0_i_2_n_0\
);
\hessian_out8__15_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(11),
I1 => \hessian_reg[6]\(10),
I2 => hessian_in(10),
I3 => \hessian_reg[6]\(11),
O => \hessian_out8__15_carry__0_i_3_n_0\
);
\hessian_out8__15_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(9),
I1 => \hessian_reg[6]\(8),
I2 => hessian_in(8),
I3 => \hessian_reg[6]\(9),
O => \hessian_out8__15_carry__0_i_4_n_0\
);
\hessian_out8__15_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(15),
I1 => \hessian_reg[6]\(14),
I2 => hessian_in(14),
I3 => \hessian_reg[6]\(15),
O => \hessian_out8__15_carry__0_i_5_n_0\
);
\hessian_out8__15_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(13),
I1 => \hessian_reg[6]\(12),
I2 => hessian_in(12),
I3 => \hessian_reg[6]\(13),
O => \hessian_out8__15_carry__0_i_6_n_0\
);
\hessian_out8__15_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(11),
I1 => \hessian_reg[6]\(10),
I2 => hessian_in(10),
I3 => \hessian_reg[6]\(11),
O => \hessian_out8__15_carry__0_i_7_n_0\
);
\hessian_out8__15_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(9),
I1 => \hessian_reg[6]\(8),
I2 => hessian_in(8),
I3 => \hessian_reg[6]\(9),
O => \hessian_out8__15_carry__0_i_8_n_0\
);
\hessian_out8__15_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out8__15_carry__0_n_0\,
CO(3) => \hessian_out8__15_carry__1_n_0\,
CO(2) => \hessian_out8__15_carry__1_n_1\,
CO(1) => \hessian_out8__15_carry__1_n_2\,
CO(0) => \hessian_out8__15_carry__1_n_3\,
CYINIT => '0',
DI(3) => \hessian_out8__15_carry__1_i_1_n_0\,
DI(2) => \hessian_out8__15_carry__1_i_2_n_0\,
DI(1) => \hessian_out8__15_carry__1_i_3_n_0\,
DI(0) => \hessian_out8__15_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out8__15_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out8__15_carry__1_i_5_n_0\,
S(2) => \hessian_out8__15_carry__1_i_6_n_0\,
S(1) => \hessian_out8__15_carry__1_i_7_n_0\,
S(0) => \hessian_out8__15_carry__1_i_8_n_0\
);
\hessian_out8__15_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(23),
I1 => \hessian_reg[6]\(22),
I2 => hessian_in(22),
I3 => \hessian_reg[6]\(23),
O => \hessian_out8__15_carry__1_i_1_n_0\
);
\hessian_out8__15_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(21),
I1 => \hessian_reg[6]\(20),
I2 => hessian_in(20),
I3 => \hessian_reg[6]\(21),
O => \hessian_out8__15_carry__1_i_2_n_0\
);
\hessian_out8__15_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(19),
I1 => \hessian_reg[6]\(18),
I2 => hessian_in(18),
I3 => \hessian_reg[6]\(19),
O => \hessian_out8__15_carry__1_i_3_n_0\
);
\hessian_out8__15_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(17),
I1 => \hessian_reg[6]\(16),
I2 => hessian_in(16),
I3 => \hessian_reg[6]\(17),
O => \hessian_out8__15_carry__1_i_4_n_0\
);
\hessian_out8__15_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(23),
I1 => \hessian_reg[6]\(22),
I2 => hessian_in(22),
I3 => \hessian_reg[6]\(23),
O => \hessian_out8__15_carry__1_i_5_n_0\
);
\hessian_out8__15_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(21),
I1 => \hessian_reg[6]\(20),
I2 => hessian_in(20),
I3 => \hessian_reg[6]\(21),
O => \hessian_out8__15_carry__1_i_6_n_0\
);
\hessian_out8__15_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(19),
I1 => \hessian_reg[6]\(18),
I2 => hessian_in(18),
I3 => \hessian_reg[6]\(19),
O => \hessian_out8__15_carry__1_i_7_n_0\
);
\hessian_out8__15_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(17),
I1 => \hessian_reg[6]\(16),
I2 => hessian_in(16),
I3 => \hessian_reg[6]\(17),
O => \hessian_out8__15_carry__1_i_8_n_0\
);
\hessian_out8__15_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out8__15_carry__1_n_0\,
CO(3) => \hessian_out8__15_carry__2_n_0\,
CO(2) => \hessian_out8__15_carry__2_n_1\,
CO(1) => \hessian_out8__15_carry__2_n_2\,
CO(0) => \hessian_out8__15_carry__2_n_3\,
CYINIT => '0',
DI(3) => \hessian_out8__15_carry__2_i_1_n_0\,
DI(2) => \hessian_out8__15_carry__2_i_2_n_0\,
DI(1) => \hessian_out8__15_carry__2_i_3_n_0\,
DI(0) => \hessian_out8__15_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out8__15_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out8__15_carry__2_i_5_n_0\,
S(2) => \hessian_out8__15_carry__2_i_6_n_0\,
S(1) => \hessian_out8__15_carry__2_i_7_n_0\,
S(0) => \hessian_out8__15_carry__2_i_8_n_0\
);
\hessian_out8__15_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(31),
I1 => \hessian_reg[6]\(30),
I2 => hessian_in(30),
I3 => \hessian_reg[6]\(31),
O => \hessian_out8__15_carry__2_i_1_n_0\
);
\hessian_out8__15_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(29),
I1 => \hessian_reg[6]\(28),
I2 => hessian_in(28),
I3 => \hessian_reg[6]\(29),
O => \hessian_out8__15_carry__2_i_2_n_0\
);
\hessian_out8__15_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(27),
I1 => \hessian_reg[6]\(26),
I2 => hessian_in(26),
I3 => \hessian_reg[6]\(27),
O => \hessian_out8__15_carry__2_i_3_n_0\
);
\hessian_out8__15_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(25),
I1 => \hessian_reg[6]\(24),
I2 => hessian_in(24),
I3 => \hessian_reg[6]\(25),
O => \hessian_out8__15_carry__2_i_4_n_0\
);
\hessian_out8__15_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(31),
I1 => \hessian_reg[6]\(30),
I2 => hessian_in(30),
I3 => \hessian_reg[6]\(31),
O => \hessian_out8__15_carry__2_i_5_n_0\
);
\hessian_out8__15_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(29),
I1 => \hessian_reg[6]\(28),
I2 => hessian_in(28),
I3 => \hessian_reg[6]\(29),
O => \hessian_out8__15_carry__2_i_6_n_0\
);
\hessian_out8__15_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(27),
I1 => \hessian_reg[6]\(26),
I2 => hessian_in(26),
I3 => \hessian_reg[6]\(27),
O => \hessian_out8__15_carry__2_i_7_n_0\
);
\hessian_out8__15_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(25),
I1 => \hessian_reg[6]\(24),
I2 => hessian_in(24),
I3 => \hessian_reg[6]\(25),
O => \hessian_out8__15_carry__2_i_8_n_0\
);
\hessian_out8__15_carry_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(7),
I1 => \hessian_reg[6]\(6),
I2 => hessian_in(6),
I3 => \hessian_reg[6]\(7),
O => \hessian_out8__15_carry_i_1_n_0\
);
\hessian_out8__15_carry_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(5),
I1 => \hessian_reg[6]\(4),
I2 => hessian_in(4),
I3 => \hessian_reg[6]\(5),
O => \hessian_out8__15_carry_i_2_n_0\
);
\hessian_out8__15_carry_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(3),
I1 => \hessian_reg[6]\(2),
I2 => hessian_in(2),
I3 => \hessian_reg[6]\(3),
O => \hessian_out8__15_carry_i_3_n_0\
);
\hessian_out8__15_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"20BA"
)
port map (
I0 => hessian_in(1),
I1 => \hessian_reg[6]\(0),
I2 => hessian_in(0),
I3 => \hessian_reg[6]\(1),
O => \hessian_out8__15_carry_i_4_n_0\
);
\hessian_out8__15_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(7),
I1 => \hessian_reg[6]\(6),
I2 => hessian_in(6),
I3 => \hessian_reg[6]\(7),
O => \hessian_out8__15_carry_i_5_n_0\
);
\hessian_out8__15_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(5),
I1 => \hessian_reg[6]\(4),
I2 => hessian_in(4),
I3 => \hessian_reg[6]\(5),
O => \hessian_out8__15_carry_i_6_n_0\
);
\hessian_out8__15_carry_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(3),
I1 => \hessian_reg[6]\(2),
I2 => hessian_in(2),
I3 => \hessian_reg[6]\(3),
O => \hessian_out8__15_carry_i_7_n_0\
);
\hessian_out8__15_carry_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => hessian_in(1),
I1 => \hessian_reg[6]\(0),
I2 => hessian_in(0),
I3 => \hessian_reg[6]\(1),
O => \hessian_out8__15_carry_i_8_n_0\
);
hessian_out8_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => hessian_out8_carry_n_0,
CO(2) => hessian_out8_carry_n_1,
CO(1) => hessian_out8_carry_n_2,
CO(0) => hessian_out8_carry_n_3,
CYINIT => '0',
DI(3) => hessian_out8_carry_i_1_n_0,
DI(2) => hessian_out8_carry_i_2_n_0,
DI(1) => hessian_out8_carry_i_3_n_0,
DI(0) => hessian_out8_carry_i_4_n_0,
O(3 downto 0) => NLW_hessian_out8_carry_O_UNCONNECTED(3 downto 0),
S(3) => hessian_out8_carry_i_5_n_0,
S(2) => hessian_out8_carry_i_6_n_0,
S(1) => hessian_out8_carry_i_7_n_0,
S(0) => hessian_out8_carry_i_8_n_0
);
\hessian_out8_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => hessian_out8_carry_n_0,
CO(3) => \hessian_out8_carry__0_n_0\,
CO(2) => \hessian_out8_carry__0_n_1\,
CO(1) => \hessian_out8_carry__0_n_2\,
CO(0) => \hessian_out8_carry__0_n_3\,
CYINIT => '0',
DI(3) => \hessian_out8_carry__0_i_1_n_0\,
DI(2) => \hessian_out8_carry__0_i_2_n_0\,
DI(1) => \hessian_out8_carry__0_i_3_n_0\,
DI(0) => \hessian_out8_carry__0_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out8_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out8_carry__0_i_5_n_0\,
S(2) => \hessian_out8_carry__0_i_6_n_0\,
S(1) => \hessian_out8_carry__0_i_7_n_0\,
S(0) => \hessian_out8_carry__0_i_8_n_0\
);
\hessian_out8_carry__0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(15),
I1 => \hessian_reg[6]\(14),
I2 => \hessian_reg[0]\(14),
I3 => \hessian_reg[0]\(15),
O => \hessian_out8_carry__0_i_1_n_0\
);
\hessian_out8_carry__0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(13),
I1 => \hessian_reg[6]\(12),
I2 => \hessian_reg[0]\(12),
I3 => \hessian_reg[0]\(13),
O => \hessian_out8_carry__0_i_2_n_0\
);
\hessian_out8_carry__0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(11),
I1 => \hessian_reg[6]\(10),
I2 => \hessian_reg[0]\(10),
I3 => \hessian_reg[0]\(11),
O => \hessian_out8_carry__0_i_3_n_0\
);
\hessian_out8_carry__0_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(9),
I1 => \hessian_reg[6]\(8),
I2 => \hessian_reg[0]\(8),
I3 => \hessian_reg[0]\(9),
O => \hessian_out8_carry__0_i_4_n_0\
);
\hessian_out8_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(15),
I1 => \hessian_reg[0]\(14),
I2 => \hessian_reg[6]\(14),
I3 => \hessian_reg[0]\(15),
O => \hessian_out8_carry__0_i_5_n_0\
);
\hessian_out8_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(13),
I1 => \hessian_reg[0]\(12),
I2 => \hessian_reg[6]\(12),
I3 => \hessian_reg[0]\(13),
O => \hessian_out8_carry__0_i_6_n_0\
);
\hessian_out8_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(11),
I1 => \hessian_reg[0]\(10),
I2 => \hessian_reg[6]\(10),
I3 => \hessian_reg[0]\(11),
O => \hessian_out8_carry__0_i_7_n_0\
);
\hessian_out8_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(9),
I1 => \hessian_reg[0]\(8),
I2 => \hessian_reg[6]\(8),
I3 => \hessian_reg[0]\(9),
O => \hessian_out8_carry__0_i_8_n_0\
);
\hessian_out8_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out8_carry__0_n_0\,
CO(3) => \hessian_out8_carry__1_n_0\,
CO(2) => \hessian_out8_carry__1_n_1\,
CO(1) => \hessian_out8_carry__1_n_2\,
CO(0) => \hessian_out8_carry__1_n_3\,
CYINIT => '0',
DI(3) => \hessian_out8_carry__1_i_1_n_0\,
DI(2) => \hessian_out8_carry__1_i_2_n_0\,
DI(1) => \hessian_out8_carry__1_i_3_n_0\,
DI(0) => \hessian_out8_carry__1_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out8_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out8_carry__1_i_5_n_0\,
S(2) => \hessian_out8_carry__1_i_6_n_0\,
S(1) => \hessian_out8_carry__1_i_7_n_0\,
S(0) => \hessian_out8_carry__1_i_8_n_0\
);
\hessian_out8_carry__1_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(23),
I1 => \hessian_reg[6]\(22),
I2 => \hessian_reg[0]\(22),
I3 => \hessian_reg[0]\(23),
O => \hessian_out8_carry__1_i_1_n_0\
);
\hessian_out8_carry__1_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(21),
I1 => \hessian_reg[6]\(20),
I2 => \hessian_reg[0]\(20),
I3 => \hessian_reg[0]\(21),
O => \hessian_out8_carry__1_i_2_n_0\
);
\hessian_out8_carry__1_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(19),
I1 => \hessian_reg[6]\(18),
I2 => \hessian_reg[0]\(18),
I3 => \hessian_reg[0]\(19),
O => \hessian_out8_carry__1_i_3_n_0\
);
\hessian_out8_carry__1_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(17),
I1 => \hessian_reg[6]\(16),
I2 => \hessian_reg[0]\(16),
I3 => \hessian_reg[0]\(17),
O => \hessian_out8_carry__1_i_4_n_0\
);
\hessian_out8_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(23),
I1 => \hessian_reg[0]\(22),
I2 => \hessian_reg[6]\(22),
I3 => \hessian_reg[0]\(23),
O => \hessian_out8_carry__1_i_5_n_0\
);
\hessian_out8_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(21),
I1 => \hessian_reg[0]\(20),
I2 => \hessian_reg[6]\(20),
I3 => \hessian_reg[0]\(21),
O => \hessian_out8_carry__1_i_6_n_0\
);
\hessian_out8_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(19),
I1 => \hessian_reg[0]\(18),
I2 => \hessian_reg[6]\(18),
I3 => \hessian_reg[0]\(19),
O => \hessian_out8_carry__1_i_7_n_0\
);
\hessian_out8_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(17),
I1 => \hessian_reg[0]\(16),
I2 => \hessian_reg[6]\(16),
I3 => \hessian_reg[0]\(17),
O => \hessian_out8_carry__1_i_8_n_0\
);
\hessian_out8_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \hessian_out8_carry__1_n_0\,
CO(3) => \hessian_out8_carry__2_n_0\,
CO(2) => \hessian_out8_carry__2_n_1\,
CO(1) => \hessian_out8_carry__2_n_2\,
CO(0) => \hessian_out8_carry__2_n_3\,
CYINIT => '0',
DI(3) => \hessian_out8_carry__2_i_1_n_0\,
DI(2) => \hessian_out8_carry__2_i_2_n_0\,
DI(1) => \hessian_out8_carry__2_i_3_n_0\,
DI(0) => \hessian_out8_carry__2_i_4_n_0\,
O(3 downto 0) => \NLW_hessian_out8_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \hessian_out8_carry__2_i_5_n_0\,
S(2) => \hessian_out8_carry__2_i_6_n_0\,
S(1) => \hessian_out8_carry__2_i_7_n_0\,
S(0) => \hessian_out8_carry__2_i_8_n_0\
);
\hessian_out8_carry__2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(31),
I1 => \hessian_reg[6]\(30),
I2 => \hessian_reg[0]\(30),
I3 => \hessian_reg[0]\(31),
O => \hessian_out8_carry__2_i_1_n_0\
);
\hessian_out8_carry__2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(29),
I1 => \hessian_reg[6]\(28),
I2 => \hessian_reg[0]\(28),
I3 => \hessian_reg[0]\(29),
O => \hessian_out8_carry__2_i_2_n_0\
);
\hessian_out8_carry__2_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(27),
I1 => \hessian_reg[6]\(26),
I2 => \hessian_reg[0]\(26),
I3 => \hessian_reg[0]\(27),
O => \hessian_out8_carry__2_i_3_n_0\
);
\hessian_out8_carry__2_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(25),
I1 => \hessian_reg[6]\(24),
I2 => \hessian_reg[0]\(24),
I3 => \hessian_reg[0]\(25),
O => \hessian_out8_carry__2_i_4_n_0\
);
\hessian_out8_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(31),
I1 => \hessian_reg[0]\(30),
I2 => \hessian_reg[6]\(30),
I3 => \hessian_reg[0]\(31),
O => \hessian_out8_carry__2_i_5_n_0\
);
\hessian_out8_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(29),
I1 => \hessian_reg[0]\(28),
I2 => \hessian_reg[6]\(28),
I3 => \hessian_reg[0]\(29),
O => \hessian_out8_carry__2_i_6_n_0\
);
\hessian_out8_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(27),
I1 => \hessian_reg[0]\(26),
I2 => \hessian_reg[6]\(26),
I3 => \hessian_reg[0]\(27),
O => \hessian_out8_carry__2_i_7_n_0\
);
\hessian_out8_carry__2_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(25),
I1 => \hessian_reg[0]\(24),
I2 => \hessian_reg[6]\(24),
I3 => \hessian_reg[0]\(25),
O => \hessian_out8_carry__2_i_8_n_0\
);
hessian_out8_carry_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(7),
I1 => \hessian_reg[6]\(6),
I2 => \hessian_reg[0]\(6),
I3 => \hessian_reg[0]\(7),
O => hessian_out8_carry_i_1_n_0
);
hessian_out8_carry_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(5),
I1 => \hessian_reg[6]\(4),
I2 => \hessian_reg[0]\(4),
I3 => \hessian_reg[0]\(5),
O => hessian_out8_carry_i_2_n_0
);
hessian_out8_carry_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(3),
I1 => \hessian_reg[6]\(2),
I2 => \hessian_reg[0]\(2),
I3 => \hessian_reg[0]\(3),
O => hessian_out8_carry_i_3_n_0
);
hessian_out8_carry_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7510"
)
port map (
I0 => \hessian_reg[6]\(1),
I1 => \hessian_reg[6]\(0),
I2 => \hessian_reg[0]\(0),
I3 => \hessian_reg[0]\(1),
O => hessian_out8_carry_i_4_n_0
);
hessian_out8_carry_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(7),
I1 => \hessian_reg[0]\(6),
I2 => \hessian_reg[6]\(6),
I3 => \hessian_reg[0]\(7),
O => hessian_out8_carry_i_5_n_0
);
hessian_out8_carry_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(5),
I1 => \hessian_reg[0]\(4),
I2 => \hessian_reg[6]\(4),
I3 => \hessian_reg[0]\(5),
O => hessian_out8_carry_i_6_n_0
);
hessian_out8_carry_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(3),
I1 => \hessian_reg[0]\(2),
I2 => \hessian_reg[6]\(2),
I3 => \hessian_reg[0]\(3),
O => hessian_out8_carry_i_7_n_0
);
hessian_out8_carry_i_8: unisim.vcomponents.LUT4
generic map(
INIT => X"8241"
)
port map (
I0 => \hessian_reg[6]\(1),
I1 => \hessian_reg[0]\(0),
I2 => \hessian_reg[6]\(0),
I3 => \hessian_reg[0]\(1),
O => hessian_out8_carry_i_8_n_0
);
\hessian_out[31]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAA80000"
)
port map (
I0 => active,
I1 => \hessian_out8__15_carry__2_n_0\,
I2 => \hessian_out[31]_i_2_n_0\,
I3 => \hessian_out2_carry__2_n_0\,
I4 => enable,
O => \hessian_out[31]_i_1_n_0\
);
\hessian_out[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \hessian_out3_carry__2_n_0\,
I1 => \hessian_out5_carry__2_n_0\,
I2 => \hessian_out8_carry__2_n_0\,
I3 => \hessian_out7_carry__2_n_0\,
I4 => \hessian_out6_carry__2_n_0\,
I5 => \hessian_out4_carry__2_n_0\,
O => \hessian_out[31]_i_2_n_0\
);
\hessian_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(0),
Q => hessian_out(0),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(10),
Q => hessian_out(10),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(11),
Q => hessian_out(11),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(12),
Q => hessian_out(12),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(13),
Q => hessian_out(13),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(14),
Q => hessian_out(14),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(15),
Q => hessian_out(15),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(16),
Q => hessian_out(16),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(17),
Q => hessian_out(17),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(18),
Q => hessian_out(18),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(19),
Q => hessian_out(19),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(1),
Q => hessian_out(1),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(20),
Q => hessian_out(20),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(21),
Q => hessian_out(21),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(22),
Q => hessian_out(22),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(23),
Q => hessian_out(23),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(24),
Q => hessian_out(24),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(25),
Q => hessian_out(25),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(26),
Q => hessian_out(26),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(27),
Q => hessian_out(27),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(28),
Q => hessian_out(28),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(29),
Q => hessian_out(29),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(2),
Q => hessian_out(2),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(30),
Q => hessian_out(30),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(31),
Q => hessian_out(31),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(3),
Q => hessian_out(3),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(4),
Q => hessian_out(4),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(5),
Q => hessian_out(5),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(6),
Q => hessian_out(6),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(7),
Q => hessian_out(7),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(8),
Q => hessian_out(8),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(9),
Q => hessian_out(9),
R => \hessian_out[31]_i_1_n_0\
);
\hessian_reg[0][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(0),
Q => \hessian_reg[0]\(0),
R => '0'
);
\hessian_reg[0][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(10),
Q => \hessian_reg[0]\(10),
R => '0'
);
\hessian_reg[0][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(11),
Q => \hessian_reg[0]\(11),
R => '0'
);
\hessian_reg[0][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(12),
Q => \hessian_reg[0]\(12),
R => '0'
);
\hessian_reg[0][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(13),
Q => \hessian_reg[0]\(13),
R => '0'
);
\hessian_reg[0][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(14),
Q => \hessian_reg[0]\(14),
R => '0'
);
\hessian_reg[0][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(15),
Q => \hessian_reg[0]\(15),
R => '0'
);
\hessian_reg[0][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(16),
Q => \hessian_reg[0]\(16),
R => '0'
);
\hessian_reg[0][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(17),
Q => \hessian_reg[0]\(17),
R => '0'
);
\hessian_reg[0][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(18),
Q => \hessian_reg[0]\(18),
R => '0'
);
\hessian_reg[0][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(19),
Q => \hessian_reg[0]\(19),
R => '0'
);
\hessian_reg[0][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(1),
Q => \hessian_reg[0]\(1),
R => '0'
);
\hessian_reg[0][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(20),
Q => \hessian_reg[0]\(20),
R => '0'
);
\hessian_reg[0][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(21),
Q => \hessian_reg[0]\(21),
R => '0'
);
\hessian_reg[0][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(22),
Q => \hessian_reg[0]\(22),
R => '0'
);
\hessian_reg[0][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(23),
Q => \hessian_reg[0]\(23),
R => '0'
);
\hessian_reg[0][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(24),
Q => \hessian_reg[0]\(24),
R => '0'
);
\hessian_reg[0][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(25),
Q => \hessian_reg[0]\(25),
R => '0'
);
\hessian_reg[0][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(26),
Q => \hessian_reg[0]\(26),
R => '0'
);
\hessian_reg[0][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(27),
Q => \hessian_reg[0]\(27),
R => '0'
);
\hessian_reg[0][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(28),
Q => \hessian_reg[0]\(28),
R => '0'
);
\hessian_reg[0][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(29),
Q => \hessian_reg[0]\(29),
R => '0'
);
\hessian_reg[0][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(2),
Q => \hessian_reg[0]\(2),
R => '0'
);
\hessian_reg[0][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(30),
Q => \hessian_reg[0]\(30),
R => '0'
);
\hessian_reg[0][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(31),
Q => \hessian_reg[0]\(31),
R => '0'
);
\hessian_reg[0][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(3),
Q => \hessian_reg[0]\(3),
R => '0'
);
\hessian_reg[0][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(4),
Q => \hessian_reg[0]\(4),
R => '0'
);
\hessian_reg[0][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(5),
Q => \hessian_reg[0]\(5),
R => '0'
);
\hessian_reg[0][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(6),
Q => \hessian_reg[0]\(6),
R => '0'
);
\hessian_reg[0][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(7),
Q => \hessian_reg[0]\(7),
R => '0'
);
\hessian_reg[0][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(8),
Q => \hessian_reg[0]\(8),
R => '0'
);
\hessian_reg[0][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => hessian_in(9),
Q => \hessian_reg[0]\(9),
R => '0'
);
\hessian_reg[10][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(0),
Q => \hessian_reg[10]\(0),
R => '0'
);
\hessian_reg[10][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(10),
Q => \hessian_reg[10]\(10),
R => '0'
);
\hessian_reg[10][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(11),
Q => \hessian_reg[10]\(11),
R => '0'
);
\hessian_reg[10][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(12),
Q => \hessian_reg[10]\(12),
R => '0'
);
\hessian_reg[10][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(13),
Q => \hessian_reg[10]\(13),
R => '0'
);
\hessian_reg[10][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(14),
Q => \hessian_reg[10]\(14),
R => '0'
);
\hessian_reg[10][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(15),
Q => \hessian_reg[10]\(15),
R => '0'
);
\hessian_reg[10][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(16),
Q => \hessian_reg[10]\(16),
R => '0'
);
\hessian_reg[10][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(17),
Q => \hessian_reg[10]\(17),
R => '0'
);
\hessian_reg[10][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(18),
Q => \hessian_reg[10]\(18),
R => '0'
);
\hessian_reg[10][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(19),
Q => \hessian_reg[10]\(19),
R => '0'
);
\hessian_reg[10][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(1),
Q => \hessian_reg[10]\(1),
R => '0'
);
\hessian_reg[10][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(20),
Q => \hessian_reg[10]\(20),
R => '0'
);
\hessian_reg[10][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(21),
Q => \hessian_reg[10]\(21),
R => '0'
);
\hessian_reg[10][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(22),
Q => \hessian_reg[10]\(22),
R => '0'
);
\hessian_reg[10][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(23),
Q => \hessian_reg[10]\(23),
R => '0'
);
\hessian_reg[10][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(24),
Q => \hessian_reg[10]\(24),
R => '0'
);
\hessian_reg[10][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(25),
Q => \hessian_reg[10]\(25),
R => '0'
);
\hessian_reg[10][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(26),
Q => \hessian_reg[10]\(26),
R => '0'
);
\hessian_reg[10][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(27),
Q => \hessian_reg[10]\(27),
R => '0'
);
\hessian_reg[10][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(28),
Q => \hessian_reg[10]\(28),
R => '0'
);
\hessian_reg[10][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(29),
Q => \hessian_reg[10]\(29),
R => '0'
);
\hessian_reg[10][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(2),
Q => \hessian_reg[10]\(2),
R => '0'
);
\hessian_reg[10][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(30),
Q => \hessian_reg[10]\(30),
R => '0'
);
\hessian_reg[10][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(31),
Q => \hessian_reg[10]\(31),
R => '0'
);
\hessian_reg[10][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(3),
Q => \hessian_reg[10]\(3),
R => '0'
);
\hessian_reg[10][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(4),
Q => \hessian_reg[10]\(4),
R => '0'
);
\hessian_reg[10][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(5),
Q => \hessian_reg[10]\(5),
R => '0'
);
\hessian_reg[10][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(6),
Q => \hessian_reg[10]\(6),
R => '0'
);
\hessian_reg[10][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(7),
Q => \hessian_reg[10]\(7),
R => '0'
);
\hessian_reg[10][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(8),
Q => \hessian_reg[10]\(8),
R => '0'
);
\hessian_reg[10][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[9]\(9),
Q => \hessian_reg[10]\(9),
R => '0'
);
\hessian_reg[11][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(0),
Q => \hessian_reg[11]\(0),
R => '0'
);
\hessian_reg[11][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(10),
Q => \hessian_reg[11]\(10),
R => '0'
);
\hessian_reg[11][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(11),
Q => \hessian_reg[11]\(11),
R => '0'
);
\hessian_reg[11][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(12),
Q => \hessian_reg[11]\(12),
R => '0'
);
\hessian_reg[11][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(13),
Q => \hessian_reg[11]\(13),
R => '0'
);
\hessian_reg[11][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(14),
Q => \hessian_reg[11]\(14),
R => '0'
);
\hessian_reg[11][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(15),
Q => \hessian_reg[11]\(15),
R => '0'
);
\hessian_reg[11][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(16),
Q => \hessian_reg[11]\(16),
R => '0'
);
\hessian_reg[11][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(17),
Q => \hessian_reg[11]\(17),
R => '0'
);
\hessian_reg[11][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(18),
Q => \hessian_reg[11]\(18),
R => '0'
);
\hessian_reg[11][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(19),
Q => \hessian_reg[11]\(19),
R => '0'
);
\hessian_reg[11][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(1),
Q => \hessian_reg[11]\(1),
R => '0'
);
\hessian_reg[11][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(20),
Q => \hessian_reg[11]\(20),
R => '0'
);
\hessian_reg[11][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(21),
Q => \hessian_reg[11]\(21),
R => '0'
);
\hessian_reg[11][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(22),
Q => \hessian_reg[11]\(22),
R => '0'
);
\hessian_reg[11][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(23),
Q => \hessian_reg[11]\(23),
R => '0'
);
\hessian_reg[11][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(24),
Q => \hessian_reg[11]\(24),
R => '0'
);
\hessian_reg[11][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(25),
Q => \hessian_reg[11]\(25),
R => '0'
);
\hessian_reg[11][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(26),
Q => \hessian_reg[11]\(26),
R => '0'
);
\hessian_reg[11][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(27),
Q => \hessian_reg[11]\(27),
R => '0'
);
\hessian_reg[11][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(28),
Q => \hessian_reg[11]\(28),
R => '0'
);
\hessian_reg[11][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(29),
Q => \hessian_reg[11]\(29),
R => '0'
);
\hessian_reg[11][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(2),
Q => \hessian_reg[11]\(2),
R => '0'
);
\hessian_reg[11][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(30),
Q => \hessian_reg[11]\(30),
R => '0'
);
\hessian_reg[11][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(31),
Q => \hessian_reg[11]\(31),
R => '0'
);
\hessian_reg[11][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(3),
Q => \hessian_reg[11]\(3),
R => '0'
);
\hessian_reg[11][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(4),
Q => \hessian_reg[11]\(4),
R => '0'
);
\hessian_reg[11][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(5),
Q => \hessian_reg[11]\(5),
R => '0'
);
\hessian_reg[11][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(6),
Q => \hessian_reg[11]\(6),
R => '0'
);
\hessian_reg[11][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(7),
Q => \hessian_reg[11]\(7),
R => '0'
);
\hessian_reg[11][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(8),
Q => \hessian_reg[11]\(8),
R => '0'
);
\hessian_reg[11][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[10]\(9),
Q => \hessian_reg[11]\(9),
R => '0'
);
\hessian_reg[1][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(0),
Q => \hessian_reg[1]\(0),
R => '0'
);
\hessian_reg[1][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(10),
Q => \hessian_reg[1]\(10),
R => '0'
);
\hessian_reg[1][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(11),
Q => \hessian_reg[1]\(11),
R => '0'
);
\hessian_reg[1][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(12),
Q => \hessian_reg[1]\(12),
R => '0'
);
\hessian_reg[1][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(13),
Q => \hessian_reg[1]\(13),
R => '0'
);
\hessian_reg[1][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(14),
Q => \hessian_reg[1]\(14),
R => '0'
);
\hessian_reg[1][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(15),
Q => \hessian_reg[1]\(15),
R => '0'
);
\hessian_reg[1][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(16),
Q => \hessian_reg[1]\(16),
R => '0'
);
\hessian_reg[1][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(17),
Q => \hessian_reg[1]\(17),
R => '0'
);
\hessian_reg[1][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(18),
Q => \hessian_reg[1]\(18),
R => '0'
);
\hessian_reg[1][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(19),
Q => \hessian_reg[1]\(19),
R => '0'
);
\hessian_reg[1][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(1),
Q => \hessian_reg[1]\(1),
R => '0'
);
\hessian_reg[1][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(20),
Q => \hessian_reg[1]\(20),
R => '0'
);
\hessian_reg[1][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(21),
Q => \hessian_reg[1]\(21),
R => '0'
);
\hessian_reg[1][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(22),
Q => \hessian_reg[1]\(22),
R => '0'
);
\hessian_reg[1][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(23),
Q => \hessian_reg[1]\(23),
R => '0'
);
\hessian_reg[1][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(24),
Q => \hessian_reg[1]\(24),
R => '0'
);
\hessian_reg[1][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(25),
Q => \hessian_reg[1]\(25),
R => '0'
);
\hessian_reg[1][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(26),
Q => \hessian_reg[1]\(26),
R => '0'
);
\hessian_reg[1][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(27),
Q => \hessian_reg[1]\(27),
R => '0'
);
\hessian_reg[1][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(28),
Q => \hessian_reg[1]\(28),
R => '0'
);
\hessian_reg[1][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(29),
Q => \hessian_reg[1]\(29),
R => '0'
);
\hessian_reg[1][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(2),
Q => \hessian_reg[1]\(2),
R => '0'
);
\hessian_reg[1][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(30),
Q => \hessian_reg[1]\(30),
R => '0'
);
\hessian_reg[1][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(31),
Q => \hessian_reg[1]\(31),
R => '0'
);
\hessian_reg[1][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(3),
Q => \hessian_reg[1]\(3),
R => '0'
);
\hessian_reg[1][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(4),
Q => \hessian_reg[1]\(4),
R => '0'
);
\hessian_reg[1][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(5),
Q => \hessian_reg[1]\(5),
R => '0'
);
\hessian_reg[1][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(6),
Q => \hessian_reg[1]\(6),
R => '0'
);
\hessian_reg[1][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(7),
Q => \hessian_reg[1]\(7),
R => '0'
);
\hessian_reg[1][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(8),
Q => \hessian_reg[1]\(8),
R => '0'
);
\hessian_reg[1][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[0]\(9),
Q => \hessian_reg[1]\(9),
R => '0'
);
\hessian_reg[4][0]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(0),
Q => \hessian_reg[4][0]_srl3_n_0\
);
\hessian_reg[4][10]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(10),
Q => \hessian_reg[4][10]_srl3_n_0\
);
\hessian_reg[4][11]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(11),
Q => \hessian_reg[4][11]_srl3_n_0\
);
\hessian_reg[4][12]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(12),
Q => \hessian_reg[4][12]_srl3_n_0\
);
\hessian_reg[4][13]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(13),
Q => \hessian_reg[4][13]_srl3_n_0\
);
\hessian_reg[4][14]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(14),
Q => \hessian_reg[4][14]_srl3_n_0\
);
\hessian_reg[4][15]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(15),
Q => \hessian_reg[4][15]_srl3_n_0\
);
\hessian_reg[4][16]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(16),
Q => \hessian_reg[4][16]_srl3_n_0\
);
\hessian_reg[4][17]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(17),
Q => \hessian_reg[4][17]_srl3_n_0\
);
\hessian_reg[4][18]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(18),
Q => \hessian_reg[4][18]_srl3_n_0\
);
\hessian_reg[4][19]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(19),
Q => \hessian_reg[4][19]_srl3_n_0\
);
\hessian_reg[4][1]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(1),
Q => \hessian_reg[4][1]_srl3_n_0\
);
\hessian_reg[4][20]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(20),
Q => \hessian_reg[4][20]_srl3_n_0\
);
\hessian_reg[4][21]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(21),
Q => \hessian_reg[4][21]_srl3_n_0\
);
\hessian_reg[4][22]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(22),
Q => \hessian_reg[4][22]_srl3_n_0\
);
\hessian_reg[4][23]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(23),
Q => \hessian_reg[4][23]_srl3_n_0\
);
\hessian_reg[4][24]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(24),
Q => \hessian_reg[4][24]_srl3_n_0\
);
\hessian_reg[4][25]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(25),
Q => \hessian_reg[4][25]_srl3_n_0\
);
\hessian_reg[4][26]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(26),
Q => \hessian_reg[4][26]_srl3_n_0\
);
\hessian_reg[4][27]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(27),
Q => \hessian_reg[4][27]_srl3_n_0\
);
\hessian_reg[4][28]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(28),
Q => \hessian_reg[4][28]_srl3_n_0\
);
\hessian_reg[4][29]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(29),
Q => \hessian_reg[4][29]_srl3_n_0\
);
\hessian_reg[4][2]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(2),
Q => \hessian_reg[4][2]_srl3_n_0\
);
\hessian_reg[4][30]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(30),
Q => \hessian_reg[4][30]_srl3_n_0\
);
\hessian_reg[4][31]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(31),
Q => \hessian_reg[4][31]_srl3_n_0\
);
\hessian_reg[4][3]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(3),
Q => \hessian_reg[4][3]_srl3_n_0\
);
\hessian_reg[4][4]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(4),
Q => \hessian_reg[4][4]_srl3_n_0\
);
\hessian_reg[4][5]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(5),
Q => \hessian_reg[4][5]_srl3_n_0\
);
\hessian_reg[4][6]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(6),
Q => \hessian_reg[4][6]_srl3_n_0\
);
\hessian_reg[4][7]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(7),
Q => \hessian_reg[4][7]_srl3_n_0\
);
\hessian_reg[4][8]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(8),
Q => \hessian_reg[4][8]_srl3_n_0\
);
\hessian_reg[4][9]_srl3\: unisim.vcomponents.SRL16E
port map (
A0 => '0',
A1 => '1',
A2 => '0',
A3 => '0',
CE => active,
CLK => clk,
D => \hessian_reg[1]\(9),
Q => \hessian_reg[4][9]_srl3_n_0\
);
\hessian_reg[5][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][0]_srl3_n_0\,
Q => \hessian_reg[5]\(0),
R => '0'
);
\hessian_reg[5][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][10]_srl3_n_0\,
Q => \hessian_reg[5]\(10),
R => '0'
);
\hessian_reg[5][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][11]_srl3_n_0\,
Q => \hessian_reg[5]\(11),
R => '0'
);
\hessian_reg[5][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][12]_srl3_n_0\,
Q => \hessian_reg[5]\(12),
R => '0'
);
\hessian_reg[5][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][13]_srl3_n_0\,
Q => \hessian_reg[5]\(13),
R => '0'
);
\hessian_reg[5][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][14]_srl3_n_0\,
Q => \hessian_reg[5]\(14),
R => '0'
);
\hessian_reg[5][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][15]_srl3_n_0\,
Q => \hessian_reg[5]\(15),
R => '0'
);
\hessian_reg[5][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][16]_srl3_n_0\,
Q => \hessian_reg[5]\(16),
R => '0'
);
\hessian_reg[5][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][17]_srl3_n_0\,
Q => \hessian_reg[5]\(17),
R => '0'
);
\hessian_reg[5][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][18]_srl3_n_0\,
Q => \hessian_reg[5]\(18),
R => '0'
);
\hessian_reg[5][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][19]_srl3_n_0\,
Q => \hessian_reg[5]\(19),
R => '0'
);
\hessian_reg[5][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][1]_srl3_n_0\,
Q => \hessian_reg[5]\(1),
R => '0'
);
\hessian_reg[5][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][20]_srl3_n_0\,
Q => \hessian_reg[5]\(20),
R => '0'
);
\hessian_reg[5][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][21]_srl3_n_0\,
Q => \hessian_reg[5]\(21),
R => '0'
);
\hessian_reg[5][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][22]_srl3_n_0\,
Q => \hessian_reg[5]\(22),
R => '0'
);
\hessian_reg[5][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][23]_srl3_n_0\,
Q => \hessian_reg[5]\(23),
R => '0'
);
\hessian_reg[5][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][24]_srl3_n_0\,
Q => \hessian_reg[5]\(24),
R => '0'
);
\hessian_reg[5][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][25]_srl3_n_0\,
Q => \hessian_reg[5]\(25),
R => '0'
);
\hessian_reg[5][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][26]_srl3_n_0\,
Q => \hessian_reg[5]\(26),
R => '0'
);
\hessian_reg[5][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][27]_srl3_n_0\,
Q => \hessian_reg[5]\(27),
R => '0'
);
\hessian_reg[5][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][28]_srl3_n_0\,
Q => \hessian_reg[5]\(28),
R => '0'
);
\hessian_reg[5][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][29]_srl3_n_0\,
Q => \hessian_reg[5]\(29),
R => '0'
);
\hessian_reg[5][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][2]_srl3_n_0\,
Q => \hessian_reg[5]\(2),
R => '0'
);
\hessian_reg[5][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][30]_srl3_n_0\,
Q => \hessian_reg[5]\(30),
R => '0'
);
\hessian_reg[5][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][31]_srl3_n_0\,
Q => \hessian_reg[5]\(31),
R => '0'
);
\hessian_reg[5][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][3]_srl3_n_0\,
Q => \hessian_reg[5]\(3),
R => '0'
);
\hessian_reg[5][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][4]_srl3_n_0\,
Q => \hessian_reg[5]\(4),
R => '0'
);
\hessian_reg[5][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][5]_srl3_n_0\,
Q => \hessian_reg[5]\(5),
R => '0'
);
\hessian_reg[5][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][6]_srl3_n_0\,
Q => \hessian_reg[5]\(6),
R => '0'
);
\hessian_reg[5][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][7]_srl3_n_0\,
Q => \hessian_reg[5]\(7),
R => '0'
);
\hessian_reg[5][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][8]_srl3_n_0\,
Q => \hessian_reg[5]\(8),
R => '0'
);
\hessian_reg[5][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[4][9]_srl3_n_0\,
Q => \hessian_reg[5]\(9),
R => '0'
);
\hessian_reg[6][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(0),
Q => \hessian_reg[6]\(0),
R => '0'
);
\hessian_reg[6][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(10),
Q => \hessian_reg[6]\(10),
R => '0'
);
\hessian_reg[6][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(11),
Q => \hessian_reg[6]\(11),
R => '0'
);
\hessian_reg[6][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(12),
Q => \hessian_reg[6]\(12),
R => '0'
);
\hessian_reg[6][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(13),
Q => \hessian_reg[6]\(13),
R => '0'
);
\hessian_reg[6][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(14),
Q => \hessian_reg[6]\(14),
R => '0'
);
\hessian_reg[6][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(15),
Q => \hessian_reg[6]\(15),
R => '0'
);
\hessian_reg[6][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(16),
Q => \hessian_reg[6]\(16),
R => '0'
);
\hessian_reg[6][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(17),
Q => \hessian_reg[6]\(17),
R => '0'
);
\hessian_reg[6][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(18),
Q => \hessian_reg[6]\(18),
R => '0'
);
\hessian_reg[6][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(19),
Q => \hessian_reg[6]\(19),
R => '0'
);
\hessian_reg[6][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(1),
Q => \hessian_reg[6]\(1),
R => '0'
);
\hessian_reg[6][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(20),
Q => \hessian_reg[6]\(20),
R => '0'
);
\hessian_reg[6][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(21),
Q => \hessian_reg[6]\(21),
R => '0'
);
\hessian_reg[6][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(22),
Q => \hessian_reg[6]\(22),
R => '0'
);
\hessian_reg[6][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(23),
Q => \hessian_reg[6]\(23),
R => '0'
);
\hessian_reg[6][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(24),
Q => \hessian_reg[6]\(24),
R => '0'
);
\hessian_reg[6][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(25),
Q => \hessian_reg[6]\(25),
R => '0'
);
\hessian_reg[6][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(26),
Q => \hessian_reg[6]\(26),
R => '0'
);
\hessian_reg[6][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(27),
Q => \hessian_reg[6]\(27),
R => '0'
);
\hessian_reg[6][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(28),
Q => \hessian_reg[6]\(28),
R => '0'
);
\hessian_reg[6][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(29),
Q => \hessian_reg[6]\(29),
R => '0'
);
\hessian_reg[6][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(2),
Q => \hessian_reg[6]\(2),
R => '0'
);
\hessian_reg[6][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(30),
Q => \hessian_reg[6]\(30),
R => '0'
);
\hessian_reg[6][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(31),
Q => \hessian_reg[6]\(31),
R => '0'
);
\hessian_reg[6][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(3),
Q => \hessian_reg[6]\(3),
R => '0'
);
\hessian_reg[6][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(4),
Q => \hessian_reg[6]\(4),
R => '0'
);
\hessian_reg[6][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(5),
Q => \hessian_reg[6]\(5),
R => '0'
);
\hessian_reg[6][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(6),
Q => \hessian_reg[6]\(6),
R => '0'
);
\hessian_reg[6][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(7),
Q => \hessian_reg[6]\(7),
R => '0'
);
\hessian_reg[6][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(8),
Q => \hessian_reg[6]\(8),
R => '0'
);
\hessian_reg[6][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[5]\(9),
Q => \hessian_reg[6]\(9),
R => '0'
);
\hessian_reg[7][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(0),
Q => \hessian_reg[7]\(0),
R => '0'
);
\hessian_reg[7][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(10),
Q => \hessian_reg[7]\(10),
R => '0'
);
\hessian_reg[7][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(11),
Q => \hessian_reg[7]\(11),
R => '0'
);
\hessian_reg[7][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(12),
Q => \hessian_reg[7]\(12),
R => '0'
);
\hessian_reg[7][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(13),
Q => \hessian_reg[7]\(13),
R => '0'
);
\hessian_reg[7][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(14),
Q => \hessian_reg[7]\(14),
R => '0'
);
\hessian_reg[7][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(15),
Q => \hessian_reg[7]\(15),
R => '0'
);
\hessian_reg[7][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(16),
Q => \hessian_reg[7]\(16),
R => '0'
);
\hessian_reg[7][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(17),
Q => \hessian_reg[7]\(17),
R => '0'
);
\hessian_reg[7][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(18),
Q => \hessian_reg[7]\(18),
R => '0'
);
\hessian_reg[7][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(19),
Q => \hessian_reg[7]\(19),
R => '0'
);
\hessian_reg[7][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(1),
Q => \hessian_reg[7]\(1),
R => '0'
);
\hessian_reg[7][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(20),
Q => \hessian_reg[7]\(20),
R => '0'
);
\hessian_reg[7][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(21),
Q => \hessian_reg[7]\(21),
R => '0'
);
\hessian_reg[7][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(22),
Q => \hessian_reg[7]\(22),
R => '0'
);
\hessian_reg[7][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(23),
Q => \hessian_reg[7]\(23),
R => '0'
);
\hessian_reg[7][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(24),
Q => \hessian_reg[7]\(24),
R => '0'
);
\hessian_reg[7][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(25),
Q => \hessian_reg[7]\(25),
R => '0'
);
\hessian_reg[7][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(26),
Q => \hessian_reg[7]\(26),
R => '0'
);
\hessian_reg[7][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(27),
Q => \hessian_reg[7]\(27),
R => '0'
);
\hessian_reg[7][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(28),
Q => \hessian_reg[7]\(28),
R => '0'
);
\hessian_reg[7][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(29),
Q => \hessian_reg[7]\(29),
R => '0'
);
\hessian_reg[7][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(2),
Q => \hessian_reg[7]\(2),
R => '0'
);
\hessian_reg[7][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(30),
Q => \hessian_reg[7]\(30),
R => '0'
);
\hessian_reg[7][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(31),
Q => \hessian_reg[7]\(31),
R => '0'
);
\hessian_reg[7][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(3),
Q => \hessian_reg[7]\(3),
R => '0'
);
\hessian_reg[7][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(4),
Q => \hessian_reg[7]\(4),
R => '0'
);
\hessian_reg[7][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(5),
Q => \hessian_reg[7]\(5),
R => '0'
);
\hessian_reg[7][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(6),
Q => \hessian_reg[7]\(6),
R => '0'
);
\hessian_reg[7][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(7),
Q => \hessian_reg[7]\(7),
R => '0'
);
\hessian_reg[7][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(8),
Q => \hessian_reg[7]\(8),
R => '0'
);
\hessian_reg[7][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[6]\(9),
Q => \hessian_reg[7]\(9),
R => '0'
);
\hessian_reg[8][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(0),
Q => \hessian_reg[8]\(0),
R => '0'
);
\hessian_reg[8][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(10),
Q => \hessian_reg[8]\(10),
R => '0'
);
\hessian_reg[8][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(11),
Q => \hessian_reg[8]\(11),
R => '0'
);
\hessian_reg[8][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(12),
Q => \hessian_reg[8]\(12),
R => '0'
);
\hessian_reg[8][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(13),
Q => \hessian_reg[8]\(13),
R => '0'
);
\hessian_reg[8][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(14),
Q => \hessian_reg[8]\(14),
R => '0'
);
\hessian_reg[8][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(15),
Q => \hessian_reg[8]\(15),
R => '0'
);
\hessian_reg[8][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(16),
Q => \hessian_reg[8]\(16),
R => '0'
);
\hessian_reg[8][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(17),
Q => \hessian_reg[8]\(17),
R => '0'
);
\hessian_reg[8][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(18),
Q => \hessian_reg[8]\(18),
R => '0'
);
\hessian_reg[8][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(19),
Q => \hessian_reg[8]\(19),
R => '0'
);
\hessian_reg[8][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(1),
Q => \hessian_reg[8]\(1),
R => '0'
);
\hessian_reg[8][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(20),
Q => \hessian_reg[8]\(20),
R => '0'
);
\hessian_reg[8][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(21),
Q => \hessian_reg[8]\(21),
R => '0'
);
\hessian_reg[8][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(22),
Q => \hessian_reg[8]\(22),
R => '0'
);
\hessian_reg[8][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(23),
Q => \hessian_reg[8]\(23),
R => '0'
);
\hessian_reg[8][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(24),
Q => \hessian_reg[8]\(24),
R => '0'
);
\hessian_reg[8][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(25),
Q => \hessian_reg[8]\(25),
R => '0'
);
\hessian_reg[8][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(26),
Q => \hessian_reg[8]\(26),
R => '0'
);
\hessian_reg[8][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(27),
Q => \hessian_reg[8]\(27),
R => '0'
);
\hessian_reg[8][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(28),
Q => \hessian_reg[8]\(28),
R => '0'
);
\hessian_reg[8][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(29),
Q => \hessian_reg[8]\(29),
R => '0'
);
\hessian_reg[8][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(2),
Q => \hessian_reg[8]\(2),
R => '0'
);
\hessian_reg[8][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(30),
Q => \hessian_reg[8]\(30),
R => '0'
);
\hessian_reg[8][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(31),
Q => \hessian_reg[8]\(31),
R => '0'
);
\hessian_reg[8][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(3),
Q => \hessian_reg[8]\(3),
R => '0'
);
\hessian_reg[8][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(4),
Q => \hessian_reg[8]\(4),
R => '0'
);
\hessian_reg[8][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(5),
Q => \hessian_reg[8]\(5),
R => '0'
);
\hessian_reg[8][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(6),
Q => \hessian_reg[8]\(6),
R => '0'
);
\hessian_reg[8][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(7),
Q => \hessian_reg[8]\(7),
R => '0'
);
\hessian_reg[8][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(8),
Q => \hessian_reg[8]\(8),
R => '0'
);
\hessian_reg[8][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[7]\(9),
Q => \hessian_reg[8]\(9),
R => '0'
);
\hessian_reg[9][0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(0),
Q => \hessian_reg[9]\(0),
R => '0'
);
\hessian_reg[9][10]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(10),
Q => \hessian_reg[9]\(10),
R => '0'
);
\hessian_reg[9][11]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(11),
Q => \hessian_reg[9]\(11),
R => '0'
);
\hessian_reg[9][12]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(12),
Q => \hessian_reg[9]\(12),
R => '0'
);
\hessian_reg[9][13]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(13),
Q => \hessian_reg[9]\(13),
R => '0'
);
\hessian_reg[9][14]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(14),
Q => \hessian_reg[9]\(14),
R => '0'
);
\hessian_reg[9][15]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(15),
Q => \hessian_reg[9]\(15),
R => '0'
);
\hessian_reg[9][16]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(16),
Q => \hessian_reg[9]\(16),
R => '0'
);
\hessian_reg[9][17]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(17),
Q => \hessian_reg[9]\(17),
R => '0'
);
\hessian_reg[9][18]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(18),
Q => \hessian_reg[9]\(18),
R => '0'
);
\hessian_reg[9][19]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(19),
Q => \hessian_reg[9]\(19),
R => '0'
);
\hessian_reg[9][1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(1),
Q => \hessian_reg[9]\(1),
R => '0'
);
\hessian_reg[9][20]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(20),
Q => \hessian_reg[9]\(20),
R => '0'
);
\hessian_reg[9][21]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(21),
Q => \hessian_reg[9]\(21),
R => '0'
);
\hessian_reg[9][22]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(22),
Q => \hessian_reg[9]\(22),
R => '0'
);
\hessian_reg[9][23]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(23),
Q => \hessian_reg[9]\(23),
R => '0'
);
\hessian_reg[9][24]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(24),
Q => \hessian_reg[9]\(24),
R => '0'
);
\hessian_reg[9][25]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(25),
Q => \hessian_reg[9]\(25),
R => '0'
);
\hessian_reg[9][26]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(26),
Q => \hessian_reg[9]\(26),
R => '0'
);
\hessian_reg[9][27]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(27),
Q => \hessian_reg[9]\(27),
R => '0'
);
\hessian_reg[9][28]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(28),
Q => \hessian_reg[9]\(28),
R => '0'
);
\hessian_reg[9][29]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(29),
Q => \hessian_reg[9]\(29),
R => '0'
);
\hessian_reg[9][2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(2),
Q => \hessian_reg[9]\(2),
R => '0'
);
\hessian_reg[9][30]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(30),
Q => \hessian_reg[9]\(30),
R => '0'
);
\hessian_reg[9][31]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(31),
Q => \hessian_reg[9]\(31),
R => '0'
);
\hessian_reg[9][3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(3),
Q => \hessian_reg[9]\(3),
R => '0'
);
\hessian_reg[9][4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(4),
Q => \hessian_reg[9]\(4),
R => '0'
);
\hessian_reg[9][5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(5),
Q => \hessian_reg[9]\(5),
R => '0'
);
\hessian_reg[9][6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(6),
Q => \hessian_reg[9]\(6),
R => '0'
);
\hessian_reg[9][7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(7),
Q => \hessian_reg[9]\(7),
R => '0'
);
\hessian_reg[9][8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(8),
Q => \hessian_reg[9]\(8),
R => '0'
);
\hessian_reg[9][9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \hessian_reg[8]\(9),
Q => \hessian_reg[9]\(9),
R => '0'
);
\minusOp_inferred__0/y_addr_out[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => y_addr_in(0),
O => \minusOp_inferred__0/y_addr_out[0]_i_1_n_0\
);
\minusOp_inferred__0/y_addr_out[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => y_addr_in(4),
I1 => y_addr_in(2),
I2 => y_addr_in(0),
I3 => y_addr_in(1),
I4 => y_addr_in(3),
I5 => y_addr_in(5),
O => \minusOp_inferred__0/y_addr_out[9]_i_2_n_0\
);
\x_addr_out[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => x_addr_in(0),
O => minusOp(0)
);
\x_addr_out[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => x_addr_in(0),
I1 => x_addr_in(1),
O => \x_addr_out[1]_i_1_n_0\
);
\x_addr_out[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => x_addr_in(1),
I1 => x_addr_in(0),
I2 => x_addr_in(2),
O => \x_addr_out[2]_i_1_n_0\
);
\x_addr_out[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE01"
)
port map (
I0 => x_addr_in(2),
I1 => x_addr_in(0),
I2 => x_addr_in(1),
I3 => x_addr_in(3),
O => \x_addr_out[3]_i_1_n_0\
);
\x_addr_out[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0001"
)
port map (
I0 => x_addr_in(3),
I1 => x_addr_in(1),
I2 => x_addr_in(0),
I3 => x_addr_in(2),
I4 => x_addr_in(4),
O => \x_addr_out[4]_i_1_n_0\
);
\x_addr_out[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFE00000001"
)
port map (
I0 => x_addr_in(4),
I1 => x_addr_in(2),
I2 => x_addr_in(0),
I3 => x_addr_in(1),
I4 => x_addr_in(3),
I5 => x_addr_in(5),
O => \x_addr_out[5]_i_1_n_0\
);
\x_addr_out[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \x_addr_out[9]_i_2_n_0\,
I1 => x_addr_in(6),
O => \x_addr_out[6]_i_1_n_0\
);
\x_addr_out[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => x_addr_in(6),
I1 => \x_addr_out[9]_i_2_n_0\,
I2 => x_addr_in(7),
O => \x_addr_out[7]_i_1_n_0\
);
\x_addr_out[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE01"
)
port map (
I0 => x_addr_in(7),
I1 => \x_addr_out[9]_i_2_n_0\,
I2 => x_addr_in(6),
I3 => x_addr_in(8),
O => \x_addr_out[8]_i_1_n_0\
);
\x_addr_out[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0001"
)
port map (
I0 => x_addr_in(8),
I1 => x_addr_in(6),
I2 => \x_addr_out[9]_i_2_n_0\,
I3 => x_addr_in(7),
I4 => x_addr_in(9),
O => \x_addr_out[9]_i_1_n_0\
);
\x_addr_out[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => x_addr_in(4),
I1 => x_addr_in(2),
I2 => x_addr_in(0),
I3 => x_addr_in(1),
I4 => x_addr_in(3),
I5 => x_addr_in(5),
O => \x_addr_out[9]_i_2_n_0\
);
\x_addr_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => minusOp(0),
Q => x_addr_out(0),
R => '0'
);
\x_addr_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[1]_i_1_n_0\,
Q => x_addr_out(1),
R => '0'
);
\x_addr_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[2]_i_1_n_0\,
Q => x_addr_out(2),
R => '0'
);
\x_addr_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[3]_i_1_n_0\,
Q => x_addr_out(3),
R => '0'
);
\x_addr_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[4]_i_1_n_0\,
Q => x_addr_out(4),
R => '0'
);
\x_addr_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[5]_i_1_n_0\,
Q => x_addr_out(5),
R => '0'
);
\x_addr_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[6]_i_1_n_0\,
Q => x_addr_out(6),
R => '0'
);
\x_addr_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[7]_i_1_n_0\,
Q => x_addr_out(7),
R => '0'
);
\x_addr_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[8]_i_1_n_0\,
Q => x_addr_out(8),
R => '0'
);
\x_addr_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \x_addr_out[9]_i_1_n_0\,
Q => x_addr_out(9),
R => '0'
);
\y_addr_out[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => y_addr_in(0),
I1 => y_addr_in(1),
O => \y_addr_out[1]_i_1_n_0\
);
\y_addr_out[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => y_addr_in(1),
I1 => y_addr_in(0),
I2 => y_addr_in(2),
O => \y_addr_out[2]_i_1_n_0\
);
\y_addr_out[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE01"
)
port map (
I0 => y_addr_in(2),
I1 => y_addr_in(0),
I2 => y_addr_in(1),
I3 => y_addr_in(3),
O => \y_addr_out[3]_i_1_n_0\
);
\y_addr_out[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0001"
)
port map (
I0 => y_addr_in(3),
I1 => y_addr_in(1),
I2 => y_addr_in(0),
I3 => y_addr_in(2),
I4 => y_addr_in(4),
O => \y_addr_out[4]_i_1_n_0\
);
\y_addr_out[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFE00000001"
)
port map (
I0 => y_addr_in(4),
I1 => y_addr_in(2),
I2 => y_addr_in(0),
I3 => y_addr_in(1),
I4 => y_addr_in(3),
I5 => y_addr_in(5),
O => \y_addr_out[5]_i_1_n_0\
);
\y_addr_out[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \minusOp_inferred__0/y_addr_out[9]_i_2_n_0\,
I1 => y_addr_in(6),
O => \y_addr_out[6]_i_1_n_0\
);
\y_addr_out[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => y_addr_in(6),
I1 => \minusOp_inferred__0/y_addr_out[9]_i_2_n_0\,
I2 => y_addr_in(7),
O => \y_addr_out[7]_i_1_n_0\
);
\y_addr_out[8]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FE01"
)
port map (
I0 => y_addr_in(7),
I1 => \minusOp_inferred__0/y_addr_out[9]_i_2_n_0\,
I2 => y_addr_in(6),
I3 => y_addr_in(8),
O => \y_addr_out[8]_i_1_n_0\
);
\y_addr_out[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0001"
)
port map (
I0 => y_addr_in(8),
I1 => y_addr_in(6),
I2 => \minusOp_inferred__0/y_addr_out[9]_i_2_n_0\,
I3 => y_addr_in(7),
I4 => y_addr_in(9),
O => \y_addr_out[9]_i_1_n_0\
);
\y_addr_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \minusOp_inferred__0/y_addr_out[0]_i_1_n_0\,
Q => y_addr_out(0),
R => '0'
);
\y_addr_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[1]_i_1_n_0\,
Q => y_addr_out(1),
R => '0'
);
\y_addr_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[2]_i_1_n_0\,
Q => y_addr_out(2),
R => '0'
);
\y_addr_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[3]_i_1_n_0\,
Q => y_addr_out(3),
R => '0'
);
\y_addr_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[4]_i_1_n_0\,
Q => y_addr_out(4),
R => '0'
);
\y_addr_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[5]_i_1_n_0\,
Q => y_addr_out(5),
R => '0'
);
\y_addr_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[6]_i_1_n_0\,
Q => y_addr_out(6),
R => '0'
);
\y_addr_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[7]_i_1_n_0\,
Q => y_addr_out(7),
R => '0'
);
\y_addr_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[8]_i_1_n_0\,
Q => y_addr_out(8),
R => '0'
);
\y_addr_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => active,
D => \y_addr_out[9]_i_1_n_0\,
Q => y_addr_out(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_nmsuppression_0_0 is
port (
clk : in STD_LOGIC;
enable : in STD_LOGIC;
active : in STD_LOGIC;
x_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
x_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
hessian_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_nmsuppression_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_nmsuppression_0_0 : entity is "system_vga_nmsuppression_1_0,vga_nmsuppression,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_nmsuppression_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_nmsuppression_0_0 : entity is "vga_nmsuppression,Vivado 2016.4";
end system_vga_nmsuppression_0_0;
architecture STRUCTURE of system_vga_nmsuppression_0_0 is
begin
U0: entity work.system_vga_nmsuppression_0_0_vga_nmsuppression
port map (
active => active,
clk => clk,
enable => enable,
hessian_in(31 downto 0) => hessian_in(31 downto 0),
hessian_out(31 downto 0) => hessian_out(31 downto 0),
x_addr_in(9 downto 0) => x_addr_in(9 downto 0),
x_addr_out(9 downto 0) => x_addr_out(9 downto 0),
y_addr_in(9 downto 0) => y_addr_in(9 downto 0),
y_addr_out(9 downto 0) => y_addr_out(9 downto 0)
);
end STRUCTURE;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
general_ip/comparator/comparator.srcs/sources_1/new/comparator.vhd
|
2
|
536
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity comparator is
generic (
WIDTH : integer := 32
);
port (
x : in std_logic_vector(WIDTH - 1 downto 0);
y : in std_logic_vector(WIDTH - 1 downto 0);
z : out std_logic
);
end comparator;
architecture Behavioral of comparator is
begin
process(x, y)
begin
if unsigned(x) < unsigned(y) then
z <= '0';
else
z <= '1';
end if;
end process;
end Behavioral;
|
mit
|
ashikpoojari/Hardware-Security
|
DES CryptoCore/src/desxor2.vhd
|
2
|
214
|
library ieee;
use ieee.std_logic_1164.all;
entity desxor2 is port
(
d,l : in std_logic_vector(1 to 32);
q : out std_logic_vector(1 to 32)
);
end desxor2;
architecture behaviour of desxor2 is
begin
q<=d xor l;
end;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ipshared/8064/affine_rotation_generator.vhd
|
2
|
4399
|
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: vga_buffer_addressable - Structural
-- Description: Outputs counterclockwise rotation over time
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity affine_rotation_generator is
port(
clk_25 : in std_logic;
reset : in std_logic;
-- IEEE 754 floating point 2x2 rotation matrix
a00 : out std_logic_vector(31 downto 0);
a01 : out std_logic_vector(31 downto 0);
a10 : out std_logic_vector(31 downto 0);
a11 : out std_logic_vector(31 downto 0)
);
end affine_rotation_generator;
architecture Structural of affine_rotation_generator is
begin
process(clk_25)
variable counter : integer := 0;
variable angle : integer := 0;
variable cosine : std_logic_vector(31 downto 0);
variable sine : std_logic_vector(31 downto 0);
begin
if rising_edge(clk_25) then
if reset = '1' then
counter := 0;
angle := 0;
else
counter := counter + 1;
if counter >= 25000000 then
counter := 0;
angle := angle + 4;
if angle >= 90 then
angle := 0;
end if;
end if;
end if;
if angle = 0 then
cosine := x"00000000";
sine := x"3f800000";
elsif angle = 4 then
cosine := x"3f7f605c";
sine := x"3d8edc7b";
elsif angle = 8 then
cosine := x"3f7d8235";
sine := x"3e0e8365";
elsif angle = 12 then
cosine := x"3f7a67e2";
sine := x"3e54e6cd";
elsif angle = 16 then
cosine := x"3f76153f";
sine := x"3e8d2057";
elsif angle = 20 then
cosine := x"3f708fb2";
sine := x"3eaf1d44";
elsif angle = 24 then
cosine := x"3f69de1d";
sine := x"3ed03fc9";
elsif angle = 28 then
cosine := x"3f6208da";
sine := x"3ef05e94";
elsif angle = 32 then
cosine := x"3f5919ae";
sine := x"3f07a8ca";
elsif angle = 36 then
cosine := x"3f4f1bbd";
sine := x"3f167918";
elsif angle = 40 then
cosine := x"3f441b7d";
sine := x"3f248dbb";
elsif angle = 44 then
cosine := x"3f3826a7";
sine := x"3f31d522";
elsif angle = 48 then
cosine := x"3f2b4c25";
sine := x"3f3e3ebd";
elsif angle = 52 then
cosine := x"3f1d9bfe";
sine := x"3f49bb13";
elsif angle = 56 then
cosine := x"3f0f2744";
sine := x"3f543bce";
elsif angle = 60 then
cosine := x"3f000000";
sine := x"3f5db3d7";
elsif angle = 64 then
cosine := x"3ee0722f";
sine := x"3f66175e";
elsif angle = 68 then
cosine := x"3ebfcc6f";
sine := x"3f6d5bec";
elsif angle = 72 then
cosine := x"3e9e377a";
sine := x"3f737871";
elsif angle = 76 then
cosine := x"3e77ba60";
sine := x"3f78654d";
elsif angle = 80 then
cosine := x"3e31d0d4";
sine := x"3f7c1c5c";
elsif angle = 84 then
cosine := x"3dd61305";
sine := x"3f7e98fd";
elsif angle = 88 then
cosine := x"3d0ef2c6";
sine := x"3f7fd814";
end if;
a00 <= cosine;
a01(31) <= not sine(31);
a01(30 downto 0) <= sine(30 downto 0);
a10 <= sine;
a11 <= cosine;
end if;
end process;
end Structural;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_xlconstant_0_2/sim/system_xlconstant_0_2.vhd
|
1
|
1296
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08/14/2014 12:18:30 PM
-- Design Name:
-- Module Name: tb_vhdl - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlconstant;
ENTITY system_xlconstant_0_2 IS
PORT (
dout : OUT STD_LOGIC_VECTOR(1-1 DOWNTO 0)
);
END system_xlconstant_0_2;
ARCHITECTURE system_xlconstant_0_2_arch OF system_xlconstant_0_2 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_xlconstant_0_2_arch: ARCHITECTURE IS "yes";
COMPONENT xlconstant IS
GENERIC (
CONST_VAL : STD_LOGIC_VECTOR(1-1 DOWNTO 0);
CONST_WIDTH : INTEGER
);
PORT (
dout : OUT STD_LOGIC_VECTOR(1-1 DOWNTO 0)
);
END COMPONENT xlconstant;
BEGIN
U0 : xlconstant
GENERIC MAP (
CONST_VAL => "1",
CONST_WIDTH => 1
)
PORT MAP (
dout => dout
);
END system_xlconstant_0_2_arch;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_vga_color_test_0_0/system_vga_color_test_0_0_stub.vhdl
|
1
|
1479
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 08:27:08 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_vga_color_test_0_0/system_vga_color_test_0_0_stub.vhdl
-- Design : system_vga_color_test_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_vga_color_test_0_0 is
Port (
clk_25 : in STD_LOGIC;
xaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end system_vga_color_test_0_0;
architecture stub of system_vga_color_test_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_25,xaddr[9:0],yaddr[9:0],rgb[23:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "vga_color_test,Vivado 2016.4";
begin
end;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0/synth/system_ov7670_controller_0_0.vhd
|
3
|
4423
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ov7670_controller:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_ov7670_controller_0_0 IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END system_ov7670_controller_0_0;
ARCHITECTURE system_ov7670_controller_0_0_arch OF system_ov7670_controller_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ov7670_controller_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT ov7670_controller IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END COMPONENT ov7670_controller;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_ov7670_controller_0_0_arch: ARCHITECTURE IS "ov7670_controller,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_ov7670_controller_0_0_arch : ARCHITECTURE IS "system_ov7670_controller_0_0,ov7670_controller,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_ov7670_controller_0_0_arch: ARCHITECTURE IS "system_ov7670_controller_0_0,ov7670_controller,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=ov7670_controller,x_ipVersion=1.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
BEGIN
U0 : ov7670_controller
PORT MAP (
clk => clk,
resend => resend,
config_finished => config_finished,
sioc => sioc,
siod => siod,
reset => reset,
pwdn => pwdn,
xclk => xclk
);
END system_ov7670_controller_0_0_arch;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_ov7670_vga_1_0/synth/system_ov7670_vga_1_0.vhd
|
2
|
3941
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ov7670_vga:1.0
-- IP Revision: 19
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_ov7670_vga_1_0 IS
PORT (
clk_x2 : IN STD_LOGIC;
active : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END system_ov7670_vga_1_0;
ARCHITECTURE system_ov7670_vga_1_0_arch OF system_ov7670_vga_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ov7670_vga_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT ov7670_vga IS
PORT (
clk_x2 : IN STD_LOGIC;
active : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT ov7670_vga;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_ov7670_vga_1_0_arch: ARCHITECTURE IS "ov7670_vga,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_ov7670_vga_1_0_arch : ARCHITECTURE IS "system_ov7670_vga_1_0,ov7670_vga,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_ov7670_vga_1_0_arch: ARCHITECTURE IS "system_ov7670_vga_1_0,ov7670_vga,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=ov7670_vga,x_ipVersion=1.0,x_ipCoreRevision=19,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF active: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : ov7670_vga
PORT MAP (
clk_x2 => clk_x2,
active => active,
data => data,
rgb => rgb
);
END system_ov7670_vga_1_0_arch;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_vga_overlay_0_0/synth/system_vga_overlay_0_0.vhd
|
3
|
3985
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_overlay:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_overlay_0_0 IS
PORT (
clk : IN STD_LOGIC;
rgb_0 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_overlay_0_0;
ARCHITECTURE system_vga_overlay_0_0_arch OF system_vga_overlay_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_overlay_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_overlay IS
PORT (
clk : IN STD_LOGIC;
rgb_0 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb_1 : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_overlay;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_overlay_0_0_arch: ARCHITECTURE IS "vga_overlay,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_overlay_0_0_arch : ARCHITECTURE IS "system_vga_overlay_0_0,vga_overlay,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_overlay_0_0_arch: ARCHITECTURE IS "system_vga_overlay_0_0,vga_overlay,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_overlay,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : vga_overlay
PORT MAP (
clk => clk,
rgb_0 => rgb_0,
rgb_1 => rgb_1,
rgb => rgb
);
END system_vga_overlay_0_0_arch;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_ov7670_controller_1_0_1/system_ov7670_controller_1_0_sim_netlist.vhdl
|
1
|
70948
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 07:03:52 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_ov7670_controller_1_0_1/system_ov7670_controller_1_0_sim_netlist.vhdl
-- Design : system_ov7670_controller_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_1_0_i2c_sender is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
sioc : out STD_LOGIC;
p_0_in : out STD_LOGIC;
\busy_sr_reg[1]_0\ : out STD_LOGIC;
siod : out STD_LOGIC;
\busy_sr_reg[31]_0\ : in STD_LOGIC;
clk : in STD_LOGIC;
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
DOADO : in STD_LOGIC_VECTOR ( 15 downto 0 );
\busy_sr_reg[31]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_controller_1_0_i2c_sender : entity is "i2c_sender";
end system_ov7670_controller_1_0_i2c_sender;
architecture STRUCTURE of system_ov7670_controller_1_0_i2c_sender is
signal busy_sr0 : STD_LOGIC;
signal \busy_sr[0]_i_3_n_0\ : STD_LOGIC;
signal \busy_sr[0]_i_5_n_0\ : STD_LOGIC;
signal \busy_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[11]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[1]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[20]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[21]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[23]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[24]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[25]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[26]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[28]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[29]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[2]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \busy_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \^busy_sr_reg[1]_0\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[0]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \data_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \data_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \data_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[20]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[31]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \divider_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 6 );
signal \divider_reg__1\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^p_0_in\ : STD_LOGIC;
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_1_in_0 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sioc_i_1_n_0 : STD_LOGIC;
signal sioc_i_2_n_0 : STD_LOGIC;
signal sioc_i_3_n_0 : STD_LOGIC;
signal sioc_i_4_n_0 : STD_LOGIC;
signal sioc_i_5_n_0 : STD_LOGIC;
signal siod_INST_0_i_1_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \busy_sr[0]_i_4\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \busy_sr[0]_i_5\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \busy_sr[10]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[11]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[12]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[13]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[14]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[15]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[16]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[17]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[18]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[19]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \busy_sr[20]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[21]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[22]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[23]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[24]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[25]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[26]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \busy_sr[27]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[28]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[29]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[2]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[30]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \busy_sr[31]_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \busy_sr[3]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[4]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[5]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[6]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[7]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[8]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[9]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \data_sr[10]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[12]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[13]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[14]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_sr[15]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[16]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[17]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[18]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[19]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[31]_i_2\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \data_sr[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[4]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[5]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[6]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[7]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[8]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[9]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \divider[0]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[1]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \divider[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[6]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \divider[7]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of sioc_i_3 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of sioc_i_4 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of sioc_i_5 : label is "soft_lutpair3";
begin
\busy_sr_reg[1]_0\ <= \^busy_sr_reg[1]_0\;
p_0_in <= \^p_0_in\;
\busy_sr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
I2 => \divider_reg__0\(7),
I3 => \^p_0_in\,
I4 => \^busy_sr_reg[1]_0\,
I5 => p_1_in(0),
O => busy_sr0
);
\busy_sr[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \busy_sr[0]_i_3_n_0\
);
\busy_sr[0]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(3),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \busy_sr[0]_i_5_n_0\,
O => \^busy_sr_reg[1]_0\
);
\busy_sr[0]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \divider_reg__1\(5),
I1 => \divider_reg__1\(4),
I2 => \divider_reg__0\(7),
I3 => \divider_reg__0\(6),
O => \busy_sr[0]_i_5_n_0\
);
\busy_sr[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
O => \busy_sr[10]_i_1_n_0\
);
\busy_sr[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[10]\,
I1 => \^p_0_in\,
O => \busy_sr[11]_i_1_n_0\
);
\busy_sr[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
O => \busy_sr[12]_i_1_n_0\
);
\busy_sr[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
O => \busy_sr[13]_i_1_n_0\
);
\busy_sr[14]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
O => \busy_sr[14]_i_1_n_0\
);
\busy_sr[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
O => \busy_sr[15]_i_1_n_0\
);
\busy_sr[16]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
O => \busy_sr[16]_i_1_n_0\
);
\busy_sr[17]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
O => \busy_sr[17]_i_1_n_0\
);
\busy_sr[18]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
O => \busy_sr[18]_i_1_n_0\
);
\busy_sr[19]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
O => \busy_sr[19]_i_1_n_0\
);
\busy_sr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \^p_0_in\,
O => \busy_sr[1]_i_1_n_0\
);
\busy_sr[20]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(0),
I1 => \^p_0_in\,
O => \busy_sr[20]_i_1_n_0\
);
\busy_sr[21]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(1),
I1 => \^p_0_in\,
O => \busy_sr[21]_i_1_n_0\
);
\busy_sr[22]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[21]\,
I1 => \^p_0_in\,
O => \busy_sr[22]_i_1_n_0\
);
\busy_sr[23]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[22]\,
I1 => \^p_0_in\,
O => \busy_sr[23]_i_1_n_0\
);
\busy_sr[24]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[23]\,
I1 => \^p_0_in\,
O => \busy_sr[24]_i_1_n_0\
);
\busy_sr[25]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[24]\,
I1 => \^p_0_in\,
O => \busy_sr[25]_i_1_n_0\
);
\busy_sr[26]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[25]\,
I1 => \^p_0_in\,
O => \busy_sr[26]_i_1_n_0\
);
\busy_sr[27]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[26]\,
I1 => \^p_0_in\,
O => \busy_sr[27]_i_1_n_0\
);
\busy_sr[28]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[27]\,
I1 => \^p_0_in\,
O => \busy_sr[28]_i_1_n_0\
);
\busy_sr[29]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \^p_0_in\,
O => \busy_sr[29]_i_1_n_0\
);
\busy_sr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[1]\,
I1 => \^p_0_in\,
O => \busy_sr[2]_i_1_n_0\
);
\busy_sr[30]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \^p_0_in\,
O => \busy_sr[30]_i_1_n_0\
);
\busy_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"22222222A2222222"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
I3 => \divider_reg__0\(7),
I4 => \divider_reg__0\(6),
I5 => \busy_sr[0]_i_3_n_0\,
O => \busy_sr[31]_i_1_n_0\
);
\busy_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^p_0_in\,
I1 => \busy_sr_reg_n_0_[30]\,
O => \busy_sr[31]_i_2_n_0\
);
\busy_sr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
O => \busy_sr[3]_i_1_n_0\
);
\busy_sr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
O => \busy_sr[4]_i_1_n_0\
);
\busy_sr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
O => \busy_sr[5]_i_1_n_0\
);
\busy_sr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
O => \busy_sr[6]_i_1_n_0\
);
\busy_sr[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
O => \busy_sr[7]_i_1_n_0\
);
\busy_sr[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
O => \busy_sr[8]_i_1_n_0\
);
\busy_sr[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
O => \busy_sr[9]_i_1_n_0\
);
\busy_sr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => p_1_in(0),
Q => \busy_sr_reg_n_0_[0]\,
R => '0'
);
\busy_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[10]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[10]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[11]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[11]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[11]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[12]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[12]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[12]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[13]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[13]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[13]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[14]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[14]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[14]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[15]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[15]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[15]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[16]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[16]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[16]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[17]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[17]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[17]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[18]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[18]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[18]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[19]_i_1_n_0\,
Q => p_1_in_0(0),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[1]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[1]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[20]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[20]_i_1_n_0\,
Q => p_1_in_0(1),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[21]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[21]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[21]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[22]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[22]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[22]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[23]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[23]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[23]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[24]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[24]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[24]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[25]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[25]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[25]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[26]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[26]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[26]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[27]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[27]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[27]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[28]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[28]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[28]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[29]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[29]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[29]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[2]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[2]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[30]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[30]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[30]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[31]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[31]_i_2_n_0\,
Q => \^p_0_in\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[3]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[3]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[4]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[4]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[5]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[5]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[6]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[6]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[7]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[7]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[8]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[8]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[9]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[9]\,
S => \busy_sr[31]_i_1_n_0\
);
\data_sr[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
I2 => DOADO(7),
O => \data_sr[10]_i_1_n_0\
);
\data_sr[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
I2 => DOADO(8),
O => \data_sr[12]_i_1_n_0\
);
\data_sr[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
I2 => DOADO(9),
O => \data_sr[13]_i_1_n_0\
);
\data_sr[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
I2 => DOADO(10),
O => \data_sr[14]_i_1_n_0\
);
\data_sr[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
I2 => DOADO(11),
O => \data_sr[15]_i_1_n_0\
);
\data_sr[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
I2 => DOADO(12),
O => \data_sr[16]_i_1_n_0\
);
\data_sr[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
I2 => DOADO(13),
O => \data_sr[17]_i_1_n_0\
);
\data_sr[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
I2 => DOADO(14),
O => \data_sr[18]_i_1_n_0\
);
\data_sr[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
I2 => DOADO(15),
O => \data_sr[19]_i_1_n_0\
);
\data_sr[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[22]\,
I1 => \data_sr_reg_n_0_[21]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[22]_i_1_n_0\
);
\data_sr[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[27]\,
I1 => \data_sr_reg_n_0_[26]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[27]_i_1_n_0\
);
\data_sr[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
O => \data_sr[30]_i_1_n_0\
);
\data_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => \data_sr_reg_n_0_[30]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[31]_i_1_n_0\
);
\data_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \data_sr[31]_i_2_n_0\
);
\data_sr[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
I2 => DOADO(0),
O => \data_sr[3]_i_1_n_0\
);
\data_sr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
I2 => DOADO(1),
O => \data_sr[4]_i_1_n_0\
);
\data_sr[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
I2 => DOADO(2),
O => \data_sr[5]_i_1_n_0\
);
\data_sr[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
I2 => DOADO(3),
O => \data_sr[6]_i_1_n_0\
);
\data_sr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
I2 => DOADO(4),
O => \data_sr[7]_i_1_n_0\
);
\data_sr[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
I2 => DOADO(5),
O => \data_sr[8]_i_1_n_0\
);
\data_sr[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
I2 => DOADO(6),
O => \data_sr[9]_i_1_n_0\
);
\data_sr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[10]_i_1_n_0\,
Q => \data_sr_reg_n_0_[10]\,
R => '0'
);
\data_sr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[10]\,
Q => \data_sr_reg_n_0_[11]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[12]_i_1_n_0\,
Q => \data_sr_reg_n_0_[12]\,
R => '0'
);
\data_sr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[13]_i_1_n_0\,
Q => \data_sr_reg_n_0_[13]\,
R => '0'
);
\data_sr_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[14]_i_1_n_0\,
Q => \data_sr_reg_n_0_[14]\,
R => '0'
);
\data_sr_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[15]_i_1_n_0\,
Q => \data_sr_reg_n_0_[15]\,
R => '0'
);
\data_sr_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[16]_i_1_n_0\,
Q => \data_sr_reg_n_0_[16]\,
R => '0'
);
\data_sr_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[17]_i_1_n_0\,
Q => \data_sr_reg_n_0_[17]\,
R => '0'
);
\data_sr_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[18]_i_1_n_0\,
Q => \data_sr_reg_n_0_[18]\,
R => '0'
);
\data_sr_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[19]_i_1_n_0\,
Q => \data_sr_reg_n_0_[19]\,
R => '0'
);
\data_sr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \^p_0_in\,
Q => \data_sr_reg_n_0_[1]\,
R => '0'
);
\data_sr_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[19]\,
Q => \data_sr_reg_n_0_[20]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[20]\,
Q => \data_sr_reg_n_0_[21]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[22]_i_1_n_0\,
Q => \data_sr_reg_n_0_[22]\,
R => '0'
);
\data_sr_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[22]\,
Q => \data_sr_reg_n_0_[23]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[23]\,
Q => \data_sr_reg_n_0_[24]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[24]\,
Q => \data_sr_reg_n_0_[25]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[25]\,
Q => \data_sr_reg_n_0_[26]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[27]_i_1_n_0\,
Q => \data_sr_reg_n_0_[27]\,
R => '0'
);
\data_sr_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[27]\,
Q => \data_sr_reg_n_0_[28]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[28]\,
Q => \data_sr_reg_n_0_[29]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[1]\,
Q => \data_sr_reg_n_0_[2]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[29]\,
Q => \data_sr_reg_n_0_[30]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[31]_i_1_n_0\,
Q => \data_sr_reg_n_0_[31]\,
R => '0'
);
\data_sr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[3]_i_1_n_0\,
Q => \data_sr_reg_n_0_[3]\,
R => '0'
);
\data_sr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[4]_i_1_n_0\,
Q => \data_sr_reg_n_0_[4]\,
R => '0'
);
\data_sr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[5]_i_1_n_0\,
Q => \data_sr_reg_n_0_[5]\,
R => '0'
);
\data_sr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[6]_i_1_n_0\,
Q => \data_sr_reg_n_0_[6]\,
R => '0'
);
\data_sr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[7]_i_1_n_0\,
Q => \data_sr_reg_n_0_[7]\,
R => '0'
);
\data_sr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[8]_i_1_n_0\,
Q => \data_sr_reg_n_0_[8]\,
R => '0'
);
\data_sr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[9]_i_1_n_0\,
Q => \data_sr_reg_n_0_[9]\,
R => '0'
);
\divider[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \divider_reg__1\(0),
O => \p_0_in__0\(0)
);
\divider[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__1\(0),
I1 => \divider_reg__1\(1),
O => \p_0_in__0\(1)
);
\divider[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \divider_reg__1\(1),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(2),
O => \p_0_in__0\(2)
);
\divider[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(1),
I3 => \divider_reg__1\(3),
O => \p_0_in__0\(3)
);
\divider[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \divider_reg__1\(3),
I1 => \divider_reg__1\(1),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(2),
I4 => \divider_reg__1\(4),
O => \p_0_in__0\(4)
);
\divider[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \p_0_in__0\(5)
);
\divider[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \p_0_in__0\(6)
);
\divider[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \busy_sr[0]_i_3_n_0\,
I2 => \divider_reg__0\(7),
O => \p_0_in__0\(7)
);
\divider_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(0),
Q => \divider_reg__1\(0),
R => '0'
);
\divider_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(1),
Q => \divider_reg__1\(1),
R => '0'
);
\divider_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(2),
Q => \divider_reg__1\(2),
R => '0'
);
\divider_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(3),
Q => \divider_reg__1\(3),
R => '0'
);
\divider_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(4),
Q => \divider_reg__1\(4),
R => '0'
);
\divider_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(5),
Q => \divider_reg__1\(5),
R => '0'
);
\divider_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(6),
Q => \divider_reg__0\(6),
R => '0'
);
\divider_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(7),
Q => \divider_reg__0\(7),
R => '0'
);
sioc_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFCFFF8FFFFFFFF"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => sioc_i_2_n_0,
I2 => sioc_i_3_n_0,
I3 => \busy_sr_reg_n_0_[1]\,
I4 => sioc_i_4_n_0,
I5 => \^p_0_in\,
O => sioc_i_1_n_0
);
sioc_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \divider_reg__0\(7),
O => sioc_i_2_n_0
);
sioc_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"A222"
)
port map (
I0 => sioc_i_5_n_0,
I1 => \busy_sr_reg_n_0_[30]\,
I2 => \divider_reg__0\(6),
I3 => \^p_0_in\,
O => sioc_i_3_n_0
);
sioc_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \busy_sr_reg_n_0_[2]\,
I2 => \^p_0_in\,
I3 => \busy_sr_reg_n_0_[30]\,
O => sioc_i_4_n_0
);
sioc_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \busy_sr_reg_n_0_[1]\,
I2 => \busy_sr_reg_n_0_[29]\,
I3 => \busy_sr_reg_n_0_[2]\,
O => sioc_i_5_n_0
);
sioc_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => sioc_i_1_n_0,
Q => sioc,
R => '0'
);
siod_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => siod_INST_0_i_1_n_0,
O => siod
);
siod_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"B0BBB0BB0000B0BB"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \busy_sr_reg_n_0_[29]\,
I2 => p_1_in_0(0),
I3 => p_1_in_0(1),
I4 => \busy_sr_reg_n_0_[11]\,
I5 => \busy_sr_reg_n_0_[10]\,
O => siod_INST_0_i_1_n_0
);
taken_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \busy_sr_reg[31]_0\,
Q => E(0),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_1_0_ov7670_registers is
port (
DOADO : out STD_LOGIC_VECTOR ( 15 downto 0 );
\divider_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
config_finished : out STD_LOGIC;
taken_reg : out STD_LOGIC;
p_1_in : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
\divider_reg[2]\ : in STD_LOGIC;
p_0_in : in STD_LOGIC;
resend : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_controller_1_0_ov7670_registers : entity is "ov7670_registers";
end system_ov7670_controller_1_0_ov7670_registers;
architecture STRUCTURE of system_ov7670_controller_1_0_ov7670_registers is
signal \^doado\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal address : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_rep[0]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[1]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[2]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[3]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[4]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[5]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[6]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_2_n_0\ : STD_LOGIC;
signal config_finished_INST_0_i_1_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_2_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_3_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_4_n_0 : STD_LOGIC;
signal NLW_sreg_reg_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_sreg_reg_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_sreg_reg_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \address_reg[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg[7]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[7]\ : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \address_rep[1]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[2]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[3]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[4]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[6]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \address_rep[7]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \busy_sr[0]_i_2\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of config_finished_INST_0 : label is "soft_lutpair30";
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of sreg_reg : label is "INDEPENDENT";
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of sreg_reg : label is "p0_d16";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of sreg_reg : label is "{SYNTH-6 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of sreg_reg : label is 4096;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of sreg_reg : label is "U0/Inst_ov7670_registers/sreg";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of sreg_reg : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of sreg_reg : label is 1023;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of sreg_reg : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of sreg_reg : label is 15;
begin
DOADO(15 downto 0) <= \^doado\(15 downto 0);
\address_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => \address_reg__0\(0),
R => resend
);
\address_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => \address_reg__0\(1),
R => resend
);
\address_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => \address_reg__0\(2),
R => resend
);
\address_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => \address_reg__0\(3),
R => resend
);
\address_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => \address_reg__0\(4),
R => resend
);
\address_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => \address_reg__0\(5),
R => resend
);
\address_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => \address_reg__0\(6),
R => resend
);
\address_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => \address_reg__0\(7),
R => resend
);
\address_reg_rep[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => address(0),
R => resend
);
\address_reg_rep[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => address(1),
R => resend
);
\address_reg_rep[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => address(2),
R => resend
);
\address_reg_rep[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => address(3),
R => resend
);
\address_reg_rep[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => address(4),
R => resend
);
\address_reg_rep[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => address(5),
R => resend
);
\address_reg_rep[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => address(6),
R => resend
);
\address_reg_rep[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => address(7),
R => resend
);
\address_rep[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \address_reg__0\(0),
O => \address_rep[0]_i_1_n_0\
);
\address_rep[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \address_reg__0\(0),
I1 => \address_reg__0\(1),
O => \address_rep[1]_i_1_n_0\
);
\address_rep[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \address_reg__0\(1),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(2),
O => \address_rep[2]_i_1_n_0\
);
\address_rep[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \address_reg__0\(2),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(1),
I3 => \address_reg__0\(3),
O => \address_rep[3]_i_1_n_0\
);
\address_rep[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \address_reg__0\(3),
I1 => \address_reg__0\(1),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(2),
I4 => \address_reg__0\(4),
O => \address_rep[4]_i_1_n_0\
);
\address_rep[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[5]_i_1_n_0\
);
\address_rep[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \address_rep[7]_i_2_n_0\,
I1 => \address_reg__0\(6),
O => \address_rep[6]_i_1_n_0\
);
\address_rep[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \address_reg__0\(6),
I1 => \address_rep[7]_i_2_n_0\,
I2 => \address_reg__0\(7),
O => \address_rep[7]_i_1_n_0\
);
\address_rep[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[7]_i_2_n_0\
);
\busy_sr[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FFFE"
)
port map (
I0 => config_finished_INST_0_i_4_n_0,
I1 => config_finished_INST_0_i_3_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_1_n_0,
I4 => p_0_in,
O => p_1_in(0)
);
config_finished_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
O => config_finished
);
config_finished_INST_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(5),
I1 => \^doado\(4),
I2 => \^doado\(7),
I3 => \^doado\(6),
O => config_finished_INST_0_i_1_n_0
);
config_finished_INST_0_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(1),
I1 => \^doado\(0),
I2 => \^doado\(3),
I3 => \^doado\(2),
O => config_finished_INST_0_i_2_n_0
);
config_finished_INST_0_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(13),
I1 => \^doado\(12),
I2 => \^doado\(15),
I3 => \^doado\(14),
O => config_finished_INST_0_i_3_n_0
);
config_finished_INST_0_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(9),
I1 => \^doado\(8),
I2 => \^doado\(11),
I3 => \^doado\(10),
O => config_finished_INST_0_i_4_n_0
);
\divider[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFE0000"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
I4 => \divider_reg[2]\,
I5 => p_0_in,
O => \divider_reg[7]\(0)
);
sreg_reg: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"53295217510C50344F4014383A04401004008C003E000C001100120412801280",
INIT_01 => X"229121021E3716020F4B0E61030A1A7B190332A41861171111003DC0581E5440",
INIT_02 => X"90008F008E008D4F74106B4A69004E204D403C78392A3871371D350B330B2907",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB80AB382B20EB10CB0849A0096009100",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(13 downto 12) => B"00",
ADDRARDADDR(11 downto 4) => address(7 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 0) => B"11111111111111",
CLKARDCLK => clk,
CLKBWRCLK => '0',
DIADI(15 downto 0) => B"1111111111111111",
DIBDI(15 downto 0) => B"1111111111111111",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"11",
DOADO(15 downto 0) => \^doado\(15 downto 0),
DOBDO(15 downto 0) => NLW_sreg_reg_DOBDO_UNCONNECTED(15 downto 0),
DOPADOP(1 downto 0) => NLW_sreg_reg_DOPADOP_UNCONNECTED(1 downto 0),
DOPBDOP(1 downto 0) => NLW_sreg_reg_DOPBDOP_UNCONNECTED(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"00",
WEBWE(3 downto 0) => B"0000"
);
taken_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055555554"
)
port map (
I0 => p_0_in,
I1 => config_finished_INST_0_i_1_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_3_n_0,
I4 => config_finished_INST_0_i_4_n_0,
I5 => \divider_reg[2]\,
O => taken_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_1_0_ov7670_controller is
port (
config_finished : out STD_LOGIC;
siod : out STD_LOGIC;
xclk : out STD_LOGIC;
sioc : out STD_LOGIC;
resend : in STD_LOGIC;
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_controller_1_0_ov7670_controller : entity is "ov7670_controller";
end system_ov7670_controller_1_0_ov7670_controller;
architecture STRUCTURE of system_ov7670_controller_1_0_ov7670_controller is
signal Inst_i2c_sender_n_3 : STD_LOGIC;
signal Inst_ov7670_registers_n_16 : STD_LOGIC;
signal Inst_ov7670_registers_n_18 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal sreg_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
signal sys_clk_i_1_n_0 : STD_LOGIC;
signal taken : STD_LOGIC;
signal \^xclk\ : STD_LOGIC;
begin
xclk <= \^xclk\;
Inst_i2c_sender: entity work.system_ov7670_controller_1_0_i2c_sender
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
\busy_sr_reg[1]_0\ => Inst_i2c_sender_n_3,
\busy_sr_reg[31]_0\ => Inst_ov7670_registers_n_18,
\busy_sr_reg[31]_1\(0) => Inst_ov7670_registers_n_16,
clk => clk,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
sioc => sioc,
siod => siod
);
Inst_ov7670_registers: entity work.system_ov7670_controller_1_0_ov7670_registers
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
clk => clk,
config_finished => config_finished,
\divider_reg[2]\ => Inst_i2c_sender_n_3,
\divider_reg[7]\(0) => Inst_ov7670_registers_n_16,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
resend => resend,
taken_reg => Inst_ov7670_registers_n_18
);
sys_clk_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^xclk\,
O => sys_clk_i_1_n_0
);
sys_clk_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => sys_clk_i_1_n_0,
Q => \^xclk\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_1_0 is
port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_ov7670_controller_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_ov7670_controller_1_0 : entity is "system_ov7670_controller_1_0,ov7670_controller,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_ov7670_controller_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_ov7670_controller_1_0 : entity is "ov7670_controller,Vivado 2016.4";
end system_ov7670_controller_1_0;
architecture STRUCTURE of system_ov7670_controller_1_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
pwdn <= \<const0>\;
reset <= \<const1>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_ov7670_controller_1_0_ov7670_controller
port map (
clk => clk,
config_finished => config_finished,
resend => resend,
sioc => sioc,
siod => siod,
xclk => xclk
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ipshared/e67f/i2c_sender.vhd
|
8
|
4935
|
----------------------------------------------------------------------------------
-- Engineer: <[email protected]
--
-- Description: Send the commands to the OV7670 over an I2C-like interface
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity i2c_sender is
port (
clk: in std_logic;
siod: inout std_logic;
sioc: out std_logic;
taken: out std_logic;
send: in std_logic;
id: in std_logic_vector(7 downto 0);
reg: in std_logic_vector(7 downto 0);
value: in std_logic_vector(7 downto 0)
);
end i2c_sender;
architecture Structural of i2c_sender is
-- this value gives a 254 cycle pause before the initial frame is sent
signal divider : unsigned (7 downto 0) := "00000001";
signal busy_sr : std_logic_vector(31 downto 0) := (others => '0');
signal data_sr : std_logic_vector(31 downto 0) := (others => '1');
begin
process(busy_sr, data_sr(31))
begin
if busy_sr(11 downto 10) = "10" or
busy_sr(20 downto 19) = "10" or
busy_sr(29 downto 28) = "10" then
siod <= 'Z';
else
siod <= data_sr(31);
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
taken <= '0';
if busy_sr(31) = '0' then
SIOC <= '1';
if send = '1' then
if divider = "00000000" then
data_sr <= "100" & id & '0' & reg & '0' & value & '0' & "01";
busy_sr <= "111" & "111111111" & "111111111" & "111111111" & "11";
taken <= '1';
else
divider <= divider+1; -- this only happens on powerup
end if;
end if;
else
case busy_sr(32-1 downto 32-3) & busy_sr(2 downto 0) is
when "111"&"111" => -- start seq #1
case divider(7 downto 6) is
when "00" => SIOC <= '1';
when "01" => SIOC <= '1';
when "10" => SIOC <= '1';
when others => SIOC <= '1';
end case;
when "111"&"110" => -- start seq #2
case divider(7 downto 6) is
when "00" => SIOC <= '1';
when "01" => SIOC <= '1';
when "10" => SIOC <= '1';
when others => SIOC <= '1';
end case;
when "111"&"100" => -- start seq #3
case divider(7 downto 6) is
when "00" => SIOC <= '0';
when "01" => SIOC <= '0';
when "10" => SIOC <= '0';
when others => SIOC <= '0';
end case;
when "110"&"000" => -- end seq #1
case divider(7 downto 6) is
when "00" => SIOC <= '0';
when "01" => SIOC <= '1';
when "10" => SIOC <= '1';
when others => SIOC <= '1';
end case;
when "100"&"000" => -- end seq #2
case divider(7 downto 6) is
when "00" => SIOC <= '1';
when "01" => SIOC <= '1';
when "10" => SIOC <= '1';
when others => SIOC <= '1';
end case;
when "000"&"000" => -- Idle
case divider(7 downto 6) is
when "00" => SIOC <= '1';
when "01" => SIOC <= '1';
when "10" => SIOC <= '1';
when others => SIOC <= '1';
end case;
when others =>
case divider(7 downto 6) is
when "00" => SIOC <= '0';
when "01" => SIOC <= '1';
when "10" => SIOC <= '1';
when others => SIOC <= '0';
end case;
end case;
if divider = "11111111" then
busy_sr <= busy_sr(32-2 downto 0) & '0';
data_sr <= data_sr(32-2 downto 0) & '1';
divider <= (others => '0');
else
divider <= divider+1;
end if;
end if;
end if;
end process;
end Structural;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_multiplier_1_2/synth/affine_block_ieee754_fp_multiplier_1_2.vhd
|
2
|
4008
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ieee754_fp_multiplier:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY affine_block_ieee754_fp_multiplier_1_2 IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END affine_block_ieee754_fp_multiplier_1_2;
ARCHITECTURE affine_block_ieee754_fp_multiplier_1_2_arch OF affine_block_ieee754_fp_multiplier_1_2 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF affine_block_ieee754_fp_multiplier_1_2_arch: ARCHITECTURE IS "yes";
COMPONENT ieee754_fp_multiplier IS
PORT (
x : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
y : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
z : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT ieee754_fp_multiplier;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF affine_block_ieee754_fp_multiplier_1_2_arch: ARCHITECTURE IS "ieee754_fp_multiplier,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF affine_block_ieee754_fp_multiplier_1_2_arch : ARCHITECTURE IS "affine_block_ieee754_fp_multiplier_1_2,ieee754_fp_multiplier,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF affine_block_ieee754_fp_multiplier_1_2_arch: ARCHITECTURE IS "affine_block_ieee754_fp_multiplier_1_2,ieee754_fp_multiplier,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=ieee754_fp_multiplier,x_ipVersion=1.0,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : ieee754_fp_multiplier
PORT MAP (
x => x,
y => y,
z => z
);
END affine_block_ieee754_fp_multiplier_1_2_arch;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_comparator_0_0/system_comparator_0_0_stub.vhdl
|
1
|
1368
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sat May 27 21:33:31 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/ZyboIP/examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_comparator_0_0/system_comparator_0_0_stub.vhdl
-- Design : system_comparator_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_comparator_0_0 is
Port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC
);
end system_comparator_0_0;
architecture stub of system_comparator_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "x[31:0],y[31:0],z";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "comparator,Vivado 2016.4";
begin
end;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_vga_hessian_0_0/sim/system_vga_hessian_0_0.vhd
|
1
|
3768
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_hessian:1.0
-- IP Revision: 40
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_hessian_0_0 IS
PORT (
clk_x16 : IN STD_LOGIC;
active : IN STD_LOGIC;
rst : IN STD_LOGIC;
x_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
g_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_vga_hessian_0_0;
ARCHITECTURE system_vga_hessian_0_0_arch OF system_vga_hessian_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_hessian_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_hessian IS
GENERIC (
ROW_WIDTH : INTEGER
);
PORT (
clk_x16 : IN STD_LOGIC;
active : IN STD_LOGIC;
rst : IN STD_LOGIC;
x_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
g_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
hessian_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT vga_hessian;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_hessian
GENERIC MAP (
ROW_WIDTH => 640
)
PORT MAP (
clk_x16 => clk_x16,
active => active,
rst => rst,
x_addr => x_addr,
y_addr => y_addr,
g_in => g_in,
hessian_out => hessian_out
);
END system_vga_hessian_0_0_arch;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/video_passthrough/video_passthrough.srcs/sources_1/bd/system/ip/system_zybo_hdmi_0_0/sim/system_zybo_hdmi_0_0.vhd
|
2
|
3819
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:zybo_hdmi:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_zybo_hdmi_0_0 IS
PORT (
clk_125 : IN STD_LOGIC;
clk_25 : IN STD_LOGIC;
hsync : IN STD_LOGIC;
vsync : IN STD_LOGIC;
active : IN STD_LOGIC;
rgb : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
tmds : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
tmdsb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
hdmi_cec : IN STD_LOGIC;
hdmi_hpd : IN STD_LOGIC;
hdmi_out_en : OUT STD_LOGIC
);
END system_zybo_hdmi_0_0;
ARCHITECTURE system_zybo_hdmi_0_0_arch OF system_zybo_hdmi_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_zybo_hdmi_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT zybo_hdmi IS
PORT (
clk_125 : IN STD_LOGIC;
clk_25 : IN STD_LOGIC;
hsync : IN STD_LOGIC;
vsync : IN STD_LOGIC;
active : IN STD_LOGIC;
rgb : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
tmds : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
tmdsb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
hdmi_cec : IN STD_LOGIC;
hdmi_hpd : IN STD_LOGIC;
hdmi_out_en : OUT STD_LOGIC
);
END COMPONENT zybo_hdmi;
BEGIN
U0 : zybo_hdmi
PORT MAP (
clk_125 => clk_125,
clk_25 => clk_25,
hsync => hsync,
vsync => vsync,
active => active,
rgb => rgb,
tmds => tmds,
tmdsb => tmdsb,
hdmi_cec => hdmi_cec,
hdmi_hpd => hdmi_hpd,
hdmi_out_en => hdmi_out_en
);
END system_zybo_hdmi_0_0_arch;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_rgb888_to_g8_0_0/system_rgb888_to_g8_0_0_stub.vhdl
|
1
|
1390
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue Jun 06 02:48:41 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_rgb888_to_g8_0_0/system_rgb888_to_g8_0_0_stub.vhdl
-- Design : system_rgb888_to_g8_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_rgb888_to_g8_0_0 is
Port (
clk : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
g8 : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end system_rgb888_to_g8_0_0;
architecture stub of system_rgb888_to_g8_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,rgb888[23:0],g8[7:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "rgb888_to_g8,Vivado 2016.4";
begin
end;
|
mit
|
ashikpoojari/Hardware-Security
|
DES CryptoCore/src/txt_util.vhd
|
2
|
15745
|
-- -------------------------------------------------------------------
-- Design:
--
-- Package for VHDL text output
--
-- Note:
-- -----
-- This package uses the VHDL 95 standard.
-- If VHDL 95 is not supported by your simulator
-- you need to comment out the file access functions.
--
-- The package provides a means to output text and
-- manipulate strings.
--
-- The basic usage is like this: >> print(s); <<
-- (where s is any string)
-- To print something which is not a string it has to be converted
-- into a string first. For this purpose the package contains
-- conversion functions called >> str(...) <<.
-- For example a std_logic_vector slv would be printed like this:
-- >> print(str(slv)); <<. To print several items on one line the
-- items have to concatenated as strings with the "&" operator eg:
-- >> print("The value of slv is "& str(slv)); <<
-- The string functions can also be used in assert statements as shown
-- in the example below:
-- >> assert DIN = "0101" <<
-- >> report "DIN = "& str(DIN)& " expected 0101 " <<
-- >> severity Error; <<
--
--
--
-- -------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
package txt_util is
-- prints a message to the screen
procedure print(text: string);
-- prints the message when active
-- useful for debug switches
procedure print(active: boolean; text: string);
-- converts std_logic into a character
function chr(sl: std_logic) return character;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string;
-- converts std_logic_vector into a string (binary base)
function str(slv: std_logic_vector) return string;
-- converts boolean into a string
function str(b: boolean) return string;
-- converts an integer into a single character
-- (can also be used for hex conversion and other bases)
function chr(int: integer) return character;
-- converts integer into string using specified base
function str(int: integer; base: integer) return string;
-- converts integer to string, using base 10
function str(int: integer) return string;
-- convert std_logic_vector into a string in hex format
function hstr(slv: std_logic_vector) return string;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character;
-- convert a character to lower case
function to_lower(c: character) return character;
-- convert a string to upper case
function to_upper(s: string) return string;
-- convert a string to lower case
function to_lower(s: string) return string;
-- functions to convert strings into other formats
--------------------------------------------------
-- converts a character into std_logic
function to_std_logic(c: character) return std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector;
-- file I/O
-----------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string);
-- print string to a file and start new line
procedure print(file out_file: TEXT;
new_string: in string);
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character);
end txt_util;
package body txt_util is
-- prints text to the screen
procedure print(text: string) is
variable msg_line: line;
begin
write(msg_line, text);
writeline(output, msg_line);
end print;
-- prints text to the screen when active
procedure print(active: boolean; text: string) is
begin
if active then
print(text);
end if;
end print;
-- converts std_logic into a character
function chr(sl: std_logic) return character is
variable c: character;
begin
case sl is
when 'U' => c:= 'U';
when 'X' => c:= 'X';
when '0' => c:= '0';
when '1' => c:= '1';
when 'Z' => c:= 'Z';
when 'W' => c:= 'W';
when 'L' => c:= 'L';
when 'H' => c:= 'H';
when '-' => c:= '-';
end case;
return c;
end chr;
-- converts std_logic into a string (1 to 1)
function str(sl: std_logic) return string is
variable s: string(1 to 1);
begin
s(1) := chr(sl);
return s;
end str;
-- converts std_logic_vector into a string (binary base)
-- (this also takes care of the fact that the range of
-- a string is natural while a std_logic_vector may
-- have an integer range)
function str(slv: std_logic_vector) return string is
variable result : string (1 to slv'length);
variable r : integer;
begin
r := 1;
for i in slv'range loop
result(r) := chr(slv(i));
r := r + 1;
end loop;
return result;
end str;
function str(b: boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
-- converts an integer into a character
-- for 0 to 9 the obvious mapping is used, higher
-- values are mapped to the characters A-Z
-- (this is usefull for systems with base > 10)
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function chr(int: integer) return character is
variable c: character;
begin
case int is
when 0 => c := '0';
when 1 => c := '1';
when 2 => c := '2';
when 3 => c := '3';
when 4 => c := '4';
when 5 => c := '5';
when 6 => c := '6';
when 7 => c := '7';
when 8 => c := '8';
when 9 => c := '9';
when 10 => c := 'A';
when 11 => c := 'B';
when 12 => c := 'C';
when 13 => c := 'D';
when 14 => c := 'E';
when 15 => c := 'F';
when 16 => c := 'G';
when 17 => c := 'H';
when 18 => c := 'I';
when 19 => c := 'J';
when 20 => c := 'K';
when 21 => c := 'L';
when 22 => c := 'M';
when 23 => c := 'N';
when 24 => c := 'O';
when 25 => c := 'P';
when 26 => c := 'Q';
when 27 => c := 'R';
when 28 => c := 'S';
when 29 => c := 'T';
when 30 => c := 'U';
when 31 => c := 'V';
when 32 => c := 'W';
when 33 => c := 'X';
when 34 => c := 'Y';
when 35 => c := 'Z';
when others => c := '?';
end case;
return c;
end chr;
-- convert integer to string using specified base
-- (adapted from Steve Vogwell's posting in comp.lang.vhdl)
function str(int: integer; base: integer) return string is
variable temp: string(1 to 10);
variable num: integer;
variable abs_int: integer;
variable len: integer := 1;
variable power: integer := 1;
begin
-- bug fix for negative numbers
abs_int := abs(int);
num := abs_int;
while num >= base loop -- Determine how many
len := len + 1; -- characters required
num := num / base; -- to represent the
end loop ; -- number.
for i in len downto 1 loop -- Convert the number to
temp(i) := chr(abs_int/power mod base); -- a string starting
power := power * base; -- with the right hand
end loop ; -- side.
-- return result and add sign if required
if int < 0 then
return '-'& temp(1 to len);
else
return temp(1 to len);
end if;
end str;
-- convert integer to string, using base 10
function str(int: integer) return string is
begin
return str(int, 10) ;
end str;
-- converts a std_logic_vector into a hex string.
function hstr(slv: std_logic_vector) return string is
variable hexlen: integer;
variable longslv : std_logic_vector(67 downto 0) := (others => '0');
variable hex : string(1 to 16);
variable fourbit : std_logic_vector(3 downto 0);
begin
hexlen := (slv'left+1)/4;
if (slv'left+1) mod 4 /= 0 then
hexlen := hexlen + 1;
end if;
longslv(slv'left downto 0) := slv;
for i in (hexlen -1) downto 0 loop
fourbit := longslv(((i*4)+3) downto (i*4));
case fourbit is
when "0000" => hex(hexlen -I) := '0';
when "0001" => hex(hexlen -I) := '1';
when "0010" => hex(hexlen -I) := '2';
when "0011" => hex(hexlen -I) := '3';
when "0100" => hex(hexlen -I) := '4';
when "0101" => hex(hexlen -I) := '5';
when "0110" => hex(hexlen -I) := '6';
when "0111" => hex(hexlen -I) := '7';
when "1000" => hex(hexlen -I) := '8';
when "1001" => hex(hexlen -I) := '9';
when "1010" => hex(hexlen -I) := 'A';
when "1011" => hex(hexlen -I) := 'B';
when "1100" => hex(hexlen -I) := 'C';
when "1101" => hex(hexlen -I) := 'D';
when "1110" => hex(hexlen -I) := 'E';
when "1111" => hex(hexlen -I) := 'F';
when "ZZZZ" => hex(hexlen -I) := 'z';
when "UUUU" => hex(hexlen -I) := 'u';
when "XXXX" => hex(hexlen -I) := 'x';
when others => hex(hexlen -I) := '?';
end case;
end loop;
return hex(1 to hexlen);
end hstr;
-- functions to manipulate strings
-----------------------------------
-- convert a character to upper case
function to_upper(c: character) return character is
variable u: character;
begin
case c is
when 'a' => u := 'A';
when 'b' => u := 'B';
when 'c' => u := 'C';
when 'd' => u := 'D';
when 'e' => u := 'E';
when 'f' => u := 'F';
when 'g' => u := 'G';
when 'h' => u := 'H';
when 'i' => u := 'I';
when 'j' => u := 'J';
when 'k' => u := 'K';
when 'l' => u := 'L';
when 'm' => u := 'M';
when 'n' => u := 'N';
when 'o' => u := 'O';
when 'p' => u := 'P';
when 'q' => u := 'Q';
when 'r' => u := 'R';
when 's' => u := 'S';
when 't' => u := 'T';
when 'u' => u := 'U';
when 'v' => u := 'V';
when 'w' => u := 'W';
when 'x' => u := 'X';
when 'y' => u := 'Y';
when 'z' => u := 'Z';
when others => u := c;
end case;
return u;
end to_upper;
-- convert a character to lower case
function to_lower(c: character) return character is
variable l: character;
begin
case c is
when 'A' => l := 'a';
when 'B' => l := 'b';
when 'C' => l := 'c';
when 'D' => l := 'd';
when 'E' => l := 'e';
when 'F' => l := 'f';
when 'G' => l := 'g';
when 'H' => l := 'h';
when 'I' => l := 'i';
when 'J' => l := 'j';
when 'K' => l := 'k';
when 'L' => l := 'l';
when 'M' => l := 'm';
when 'N' => l := 'n';
when 'O' => l := 'o';
when 'P' => l := 'p';
when 'Q' => l := 'q';
when 'R' => l := 'r';
when 'S' => l := 's';
when 'T' => l := 't';
when 'U' => l := 'u';
when 'V' => l := 'v';
when 'W' => l := 'w';
when 'X' => l := 'x';
when 'Y' => l := 'y';
when 'Z' => l := 'z';
when others => l := c;
end case;
return l;
end to_lower;
-- convert a string to upper case
function to_upper(s: string) return string is
variable uppercase: string (s'range);
begin
for i in s'range loop
uppercase(i):= to_upper(s(i));
end loop;
return uppercase;
end to_upper;
-- convert a string to lower case
function to_lower(s: string) return string is
variable lowercase: string (s'range);
begin
for i in s'range loop
lowercase(i):= to_lower(s(i));
end loop;
return lowercase;
end to_lower;
-- functions to convert strings into other types
-- converts a character into a std_logic
function to_std_logic(c: character) return std_logic is
variable sl: std_logic;
begin
case c is
when 'U' =>
sl := 'U';
when 'X' =>
sl := 'X';
when '0' =>
sl := '0';
when '1' =>
sl := '1';
when 'Z' =>
sl := 'Z';
when 'W' =>
sl := 'W';
when 'L' =>
sl := 'L';
when 'H' =>
sl := 'H';
when '-' =>
sl := '-';
when others =>
sl := 'X';
end case;
return sl;
end to_std_logic;
-- converts a string into std_logic_vector
function to_std_logic_vector(s: string) return std_logic_vector is
variable slv: std_logic_vector(s'high-s'low downto 0);
variable k: integer;
begin
k := s'high-s'low;
for i in s'range loop
slv(k) := to_std_logic(s(i));
k := k - 1;
end loop;
return slv;
end to_std_logic_vector;
----------------
-- file I/O --
----------------
-- read variable length string from input file
procedure str_read(file in_file: TEXT;
res_string: out string) is
variable l: line;
variable c: character;
variable is_string: boolean;
begin
readline(in_file, l);
-- clear the contents of the result string
for i in res_string'range loop
res_string(i) := ' ';
end loop;
-- read all characters of the line, up to the length
-- of the results string
for i in res_string'range loop
read(l, c, is_string);
res_string(i) := c;
if not is_string then -- found end of line
exit;
end if;
end loop;
end str_read;
-- print string to a file
procedure print(file out_file: TEXT;
new_string: in string) is
variable l: line;
begin
write(l, new_string);
writeline(out_file, l);
end print;
-- print character to a file and start new line
procedure print(file out_file: TEXT;
char: in character) is
variable l: line;
begin
write(l, char);
writeline(out_file, l);
end print;
-- appends contents of a string to a file until line feed occurs
-- (LF is considered to be the end of the string)
procedure str_write(file out_file: TEXT;
new_string: in string) is
begin
for i in new_string'range loop
print(out_file, new_string(i));
if new_string(i) = LF then -- end of string
exit;
end if;
end loop;
end str_write;
end txt_util;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_0_0/sim/system_rgb565_to_rgb888_0_0.vhd
|
5
|
3321
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:rgb565_to_rgb888:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_rgb565_to_rgb888_0_0 IS
PORT (
clk : IN STD_LOGIC;
rgb_565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rgb_888 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_rgb565_to_rgb888_0_0;
ARCHITECTURE system_rgb565_to_rgb888_0_0_arch OF system_rgb565_to_rgb888_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_rgb565_to_rgb888_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT rgb565_to_rgb888 IS
PORT (
clk : IN STD_LOGIC;
rgb_565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
rgb_888 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT rgb565_to_rgb888;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : rgb565_to_rgb888
PORT MAP (
clk => clk,
rgb_565 => rgb_565,
rgb_888 => rgb_888
);
END system_rgb565_to_rgb888_0_0_arch;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ipshared/f1ca/vga_pll.vhd
|
7
|
1175
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity vga_pll is
port (
clk_100 : in std_logic;
clk_50 : out std_logic;
clk_25 : out std_logic;
clk_12_5 : out std_logic;
clk_6_25 : out std_logic
);
end vga_pll;
architecture Behavioral of vga_pll is
signal clk_50_s : std_logic := '0';
signal clk_25_s : std_logic := '0';
signal clk_12_5_s : std_logic := '0';
signal clk_6_25_s : std_logic := '0';
begin
clk_50 <= clk_50_s;
clk_25 <= clk_25_s;
clk_12_5 <= clk_12_5_s;
clk_6_25 <= clk_6_25_s;
process(clk_100)
begin
if rising_edge(clk_100) then
clk_50_s <= not clk_50_s;
end if;
end process;
process(clk_50_s)
begin
if rising_edge(clk_50_s) then
clk_25_s <= not clk_25_s;
end if;
end process;
process(clk_25_s)
begin
if rising_edge(clk_25_s) then
clk_12_5_s <= not clk_12_5_s;
end if;
end process;
process(clk_6_25_s)
begin
if rising_edge(clk_6_25_s) then
clk_6_25_s <= not clk_6_25_s;
end if;
end process;
end Behavioral;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ipshared/349b/vga_pll.vhd
|
7
|
1175
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity vga_pll is
port (
clk_100 : in std_logic;
clk_50 : out std_logic;
clk_25 : out std_logic;
clk_12_5 : out std_logic;
clk_6_25 : out std_logic
);
end vga_pll;
architecture Behavioral of vga_pll is
signal clk_50_s : std_logic := '0';
signal clk_25_s : std_logic := '0';
signal clk_12_5_s : std_logic := '0';
signal clk_6_25_s : std_logic := '0';
begin
clk_50 <= clk_50_s;
clk_25 <= clk_25_s;
clk_12_5 <= clk_12_5_s;
clk_6_25 <= clk_6_25_s;
process(clk_100)
begin
if rising_edge(clk_100) then
clk_50_s <= not clk_50_s;
end if;
end process;
process(clk_50_s)
begin
if rising_edge(clk_50_s) then
clk_25_s <= not clk_25_s;
end if;
end process;
process(clk_25_s)
begin
if rising_edge(clk_25_s) then
clk_12_5_s <= not clk_12_5_s;
end if;
end process;
process(clk_6_25_s)
begin
if rising_edge(clk_6_25_s) then
clk_6_25_s <= not clk_6_25_s;
end if;
end process;
end Behavioral;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_vga_sync_reset_0_0/synth/system_vga_sync_reset_0_0.vhd
|
3
|
4935
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_sync_reset:1.0
-- IP Revision: 25
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_sync_reset_0_0 IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END system_vga_sync_reset_0_0;
ARCHITECTURE system_vga_sync_reset_0_0_arch OF system_vga_sync_reset_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_sync_reset_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_sync_reset IS
GENERIC (
H_SIZE : INTEGER;
H_FRONT_DELAY : INTEGER;
H_BACK_DELAY : INTEGER;
H_RETRACE_DELAY : INTEGER;
V_SIZE : INTEGER;
V_FRONT_DELAY : INTEGER;
V_BACK_DELAY : INTEGER;
V_RETRACE_DELAY : INTEGER
);
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
active : OUT STD_LOGIC;
hsync : OUT STD_LOGIC;
vsync : OUT STD_LOGIC;
xaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END COMPONENT vga_sync_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_sync_reset_0_0_arch: ARCHITECTURE IS "vga_sync_reset,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_sync_reset_0_0_arch : ARCHITECTURE IS "system_vga_sync_reset_0_0,vga_sync_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_sync_reset_0_0_arch: ARCHITECTURE IS "system_vga_sync_reset_0_0,vga_sync_reset,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_sync_reset,x_ipVersion=1.0,x_ipCoreRevision=25,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,H_SIZE=640,H_FRONT_DELAY=16,H_BACK_DELAY=48,H_RETRACE_DELAY=96,V_SIZE=480,V_FRONT_DELAY=10,V_BACK_DELAY=33,V_RETRACE_DELAY=2}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF rst: SIGNAL IS "xilinx.com:signal:reset:1.0 rst RST";
BEGIN
U0 : vga_sync_reset
GENERIC MAP (
H_SIZE => 640,
H_FRONT_DELAY => 16,
H_BACK_DELAY => 48,
H_RETRACE_DELAY => 96,
V_SIZE => 480,
V_FRONT_DELAY => 10,
V_BACK_DELAY => 33,
V_RETRACE_DELAY => 2
)
PORT MAP (
clk => clk,
rst => rst,
active => active,
hsync => hsync,
vsync => vsync,
xaddr => xaddr,
yaddr => yaddr
);
END system_vga_sync_reset_0_0_arch;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/video_passthrough/video_passthrough.srcs/sources_1/bd/system/hdl/system.vhd
|
1
|
18180
|
--Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
--Date : Thu Mar 10 14:13:03 2016
--Host : minmi running 64-bit elementary OS Freya
--Command : generate_target system.bd
--Design : system
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
hdmi_cec : in STD_LOGIC;
hdmi_hpd : in STD_LOGIC;
hdmi_out_en : out STD_LOGIC;
tmds : out STD_LOGIC_VECTOR ( 3 downto 0 );
tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of system : entity is "system,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=6,numReposBlks=6,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,da_ps7_cnt=1,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of system : entity is "system.hwdef";
end system;
architecture STRUCTURE of system is
component system_processing_system7_0_0 is
port (
SDIO0_WP : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component system_processing_system7_0_0;
component system_zybo_hdmi_0_0 is
port (
clk_125 : in STD_LOGIC;
clk_25 : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
active : in STD_LOGIC;
rgb : in STD_LOGIC_VECTOR ( 23 downto 0 );
tmds : out STD_LOGIC_VECTOR ( 3 downto 0 );
tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 );
hdmi_cec : in STD_LOGIC;
hdmi_hpd : in STD_LOGIC;
hdmi_out_en : out STD_LOGIC
);
end component system_zybo_hdmi_0_0;
component system_clk_wiz_0_0 is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC
);
end component system_clk_wiz_0_0;
component system_vga_sync_0_0 is
port (
clk_25 : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_vga_sync_0_0;
component system_vga_color_test_0_0 is
port (
clk_25 : in STD_LOGIC;
xaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_vga_color_test_0_0;
component system_inverter_0_0 is
port (
x : in STD_LOGIC;
x_not : out STD_LOGIC
);
end component system_inverter_0_0;
signal Net : STD_LOGIC;
signal hdmi_cec_1 : STD_LOGIC;
signal hdmi_hpd_1 : STD_LOGIC;
signal inverter_0_x_not : STD_LOGIC;
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal vga_color_test_0_rgb : STD_LOGIC_VECTOR ( 23 downto 0 );
signal vga_sync_0_active : STD_LOGIC;
signal vga_sync_0_hsync : STD_LOGIC;
signal vga_sync_0_vsync : STD_LOGIC;
signal vga_sync_0_xaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_0_yaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal zybo_hdmi_0_hdmi_out_en : STD_LOGIC;
signal zybo_hdmi_0_tmds : STD_LOGIC_VECTOR ( 3 downto 0 );
signal zybo_hdmi_0_tmdsb : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_clk_wiz_0_locked_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
hdmi_cec_1 <= hdmi_cec;
hdmi_hpd_1 <= hdmi_hpd;
hdmi_out_en <= zybo_hdmi_0_hdmi_out_en;
tmds(3 downto 0) <= zybo_hdmi_0_tmds(3 downto 0);
tmdsb(3 downto 0) <= zybo_hdmi_0_tmdsb(3 downto 0);
clk_wiz_0: component system_clk_wiz_0_0
port map (
clk_in1 => processing_system7_0_FCLK_CLK0,
clk_out1 => Net,
locked => NLW_clk_wiz_0_locked_UNCONNECTED,
resetn => processing_system7_0_FCLK_RESET0_N
);
inverter_0: component system_inverter_0_0
port map (
x => processing_system7_0_FCLK_RESET0_N,
x_not => inverter_0_x_not
);
processing_system7_0: component system_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP0_ARREADY => '0',
M_AXI_GP0_ARSIZE(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP0_ARVALID => NLW_processing_system7_0_M_AXI_GP0_ARVALID_UNCONNECTED,
M_AXI_GP0_AWADDR(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP0_AWREADY => '0',
M_AXI_GP0_AWSIZE(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP0_AWVALID => NLW_processing_system7_0_M_AXI_GP0_AWVALID_UNCONNECTED,
M_AXI_GP0_BID(11 downto 0) => B"000000000000",
M_AXI_GP0_BREADY => NLW_processing_system7_0_M_AXI_GP0_BREADY_UNCONNECTED,
M_AXI_GP0_BRESP(1 downto 0) => B"00",
M_AXI_GP0_BVALID => '0',
M_AXI_GP0_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP0_RID(11 downto 0) => B"000000000000",
M_AXI_GP0_RLAST => '0',
M_AXI_GP0_RREADY => NLW_processing_system7_0_M_AXI_GP0_RREADY_UNCONNECTED,
M_AXI_GP0_RRESP(1 downto 0) => B"00",
M_AXI_GP0_RVALID => '0',
M_AXI_GP0_WDATA(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WID_UNCONNECTED(11 downto 0),
M_AXI_GP0_WLAST => NLW_processing_system7_0_M_AXI_GP0_WLAST_UNCONNECTED,
M_AXI_GP0_WREADY => '0',
M_AXI_GP0_WSTRB(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP0_WVALID => NLW_processing_system7_0_M_AXI_GP0_WVALID_UNCONNECTED,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
SDIO0_WP => '0',
TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB0_VBUS_PWRFAULT => '0',
USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
);
vga_color_test_0: component system_vga_color_test_0_0
port map (
clk_25 => Net,
rgb(23 downto 0) => vga_color_test_0_rgb(23 downto 0),
xaddr(9 downto 0) => vga_sync_0_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_0_yaddr(9 downto 0)
);
vga_sync_0: component system_vga_sync_0_0
port map (
active => vga_sync_0_active,
clk_25 => Net,
hsync => vga_sync_0_hsync,
rst => inverter_0_x_not,
vsync => vga_sync_0_vsync,
xaddr(9 downto 0) => vga_sync_0_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_0_yaddr(9 downto 0)
);
zybo_hdmi_0: component system_zybo_hdmi_0_0
port map (
active => vga_sync_0_active,
clk_125 => processing_system7_0_FCLK_CLK0,
clk_25 => Net,
hdmi_cec => hdmi_cec_1,
hdmi_hpd => hdmi_hpd_1,
hdmi_out_en => zybo_hdmi_0_hdmi_out_en,
hsync => vga_sync_0_hsync,
rgb(23 downto 0) => vga_color_test_0_rgb(23 downto 0),
tmds(3 downto 0) => zybo_hdmi_0_tmds(3 downto 0),
tmdsb(3 downto 0) => zybo_hdmi_0_tmdsb(3 downto 0),
vsync => vga_sync_0_vsync
);
end STRUCTURE;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_vga_color_test_0_0_1/system_vga_color_test_0_0_stub.vhdl
|
1
|
1437
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 08:27:08 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_vga_color_test_0_0 -prefix
-- system_vga_color_test_0_0_ system_vga_color_test_0_0_stub.vhdl
-- Design : system_vga_color_test_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_vga_color_test_0_0 is
Port (
clk_25 : in STD_LOGIC;
xaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end system_vga_color_test_0_0;
architecture stub of system_vga_color_test_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_25,xaddr[9:0],yaddr[9:0],rgb[23:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "vga_color_test,Vivado 2016.4";
begin
end;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_hdmi_test/zed_hdmi_test.srcs/sources_1/bd/system/ipshared/0b31/i2c_sender.vhd
|
7
|
7166
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: i2c_sender h- Behavioral
--
-- Description: Send register writes over an I2C-like interface
--
-- Feel free to use this how you see fit, and fix any errors you find :-)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity i2c_sender is
Port ( clk : in STD_LOGIC;
resend : in STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC
);
end i2c_sender;
architecture Behavioral of i2c_sender is
signal divider : unsigned(8 downto 0) := (others => '0');
-- this value gives nearly 200ms cycles before the first register is written
signal initial_pause : unsigned(7 downto 0) := (others => '0');
signal finished : std_logic := '0';
signal address : std_logic_vector(7 downto 0) := (others => '0');
signal clk_first_quarter : std_logic_vector(28 downto 0) := (others => '1');
signal clk_last_quarter : std_logic_vector(28 downto 0) := (others => '1');
signal busy_sr : std_logic_vector(28 downto 0) := (others => '1');
signal data_sr : std_logic_vector(28 downto 0) := (others => '1');
signal tristate_sr : std_logic_vector(28 downto 0) := (others => '0');
signal reg_value : std_logic_vector(15 downto 0) := (others => '0');
constant i2c_wr_addr : std_logic_vector(7 downto 0) := x"72";
type reg_value_pair is ARRAY(0 TO 63) OF std_logic_vector(15 DOWNTO 0);
signal reg_value_pairs : reg_value_pair := (
-------------------
-- Powerup please!
-------------------
x"4110",
---------------------------------------
-- These values must be set as follows
---------------------------------------
x"9803", x"9AE0", x"9C30", x"9D61", x"A2A4", x"A3A4", x"E0D0", x"5512", x"F900",
---------------
-- Input mode
---------------
x"1506", -- YCbCr 422, DDR, External sync
x"4810", -- Left justified data (D23 downto 8)
x"1637", -- 444 output, 8 bit style 2, 1st half on rising edge - YCrCb clipping
x"1700", -- output aspect ratio 16:9, external DE
x"D03C", -- auto sync data - must be set for DDR modes. No DDR clock delay
---------------
-- Output mode
---------------
x"AF04", -- DVI mode
x"4c04", -- Deep colour off (HDMI only?) - not needed
x"4000", -- Turn off additional data packets - not needed
--------------------------------------------------------------
-- Here is the YCrCb => RGB conversion, as per programming guide
-- This is table 57 - HDTV YCbCr (16 to 255) to RGB (0 to 255)
--------------------------------------------------------------
-- (Cr * A1 + Y * A2 + Cb * A3)/4096 + A4 = Red
x"18E7", x"1934", x"1A04", x"1BAD", x"1C00", x"1D00", x"1E1C", x"1F1B",
-- (Cr * B1 + Y * B2 + Cb * B3)/4096 + B4 = Green
x"201D", x"21DC", x"2204", x"23AD", x"241F", x"2524", x"2601", x"2735",
-- (Cr * C1 + Y * C2 + Cb * C3)/4096 + C4 = Blue
x"2800", x"2900", x"2A04", x"2BAD", x"2C08", x"2D7C", x"2E1B", x"2F77",
-- Extra space filled with FFFFs to signify end of data
x"FFFF", x"FFFF", x"FFFF", x"FFFF", x"FFFF", x"FFFF", x"FFFF",
x"FFFF", x"FFFF", x"FFFF", x"FFFF", x"FFFF", x"FFFF", x"FFFF", x"FFFF",
x"FFFF", x"FFFF", x"FFFF", x"FFFF", x"FFFF", x"FFFF", x"FFFF"
);
begin
registers: process(clk)
begin
if rising_edge(clk) then
reg_value <= reg_value_pairs(to_integer(unsigned(address)));
end if;
end process;
i2c_tristate: process(data_sr, tristate_sr)
begin
if tristate_sr(tristate_sr'length-1) = '0' then
siod <= data_sr(data_sr'length-1);
else
siod <= 'Z';
end if;
end process;
with divider(divider'length-1 downto divider'length-2)
select sioc <= clk_first_quarter(clk_first_quarter'length -1) when "00",
clk_last_quarter(clk_last_quarter'length -1) when "11",
'1' when others;
i2c_send: process(clk)
begin
if rising_edge(clk) then
if resend = '1' then
address <= (others => '0');
clk_first_quarter <= (others => '1');
clk_last_quarter <= (others => '1');
busy_sr <= (others => '0');
divider <= (others => '0');
initial_pause <= (others => '0');
finished <= '0';
end if;
if busy_sr(busy_sr'length-1) = '0' then
if initial_pause(initial_pause'length-1) = '0' then
initial_pause <= initial_pause+1;
elsif finished = '0' then
if divider = "11111111" then
divider <= (others =>'0');
if reg_value(15 downto 8) = "11111111" then
finished <= '1';
else
-- move the new data into the shift registers
clk_first_quarter <= (others => '0'); clk_first_quarter(clk_first_quarter'length-1) <= '1';
clk_last_quarter <= (others => '0'); clk_last_quarter(0) <= '1';
-- Start Address Ack Register Ack Value Ack Stop
tristate_sr <= "0" & "00000000" & "1" & "00000000" & "1" & "00000000" & "1" & "0";
data_sr <= "0" & i2c_wr_addr & "1" & reg_value(15 downto 8) & "1" & reg_value( 7 downto 0) & "1" & "0";
busy_sr <= (others => '1');
address <= std_logic_vector(unsigned(address)+1);
end if;
else
divider <= divider+1;
end if;
end if;
else
if divider = "11111111" then -- divide clkin by 256 for I2C
tristate_sr <= tristate_sr(tristate_sr'length-2 downto 0) & '0';
busy_sr <= busy_sr(busy_sr'length-2 downto 0) & '0';
data_sr <= data_sr(data_sr'length-2 downto 0) & '1';
clk_first_quarter <= clk_first_quarter(clk_first_quarter'length-2 downto 0) & '1';
clk_last_quarter <= clk_last_quarter(clk_first_quarter'length-2 downto 0) & '1';
divider <= (others => '0');
else
divider <= divider+1;
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
video_ip/zed_hdmi/zed_hdmi.srcs/sources_1/new/i2c_sender.vhd
|
7
|
7166
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: i2c_sender h- Behavioral
--
-- Description: Send register writes over an I2C-like interface
--
-- Feel free to use this how you see fit, and fix any errors you find :-)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity i2c_sender is
Port ( clk : in STD_LOGIC;
resend : in STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC
);
end i2c_sender;
architecture Behavioral of i2c_sender is
signal divider : unsigned(8 downto 0) := (others => '0');
-- this value gives nearly 200ms cycles before the first register is written
signal initial_pause : unsigned(7 downto 0) := (others => '0');
signal finished : std_logic := '0';
signal address : std_logic_vector(7 downto 0) := (others => '0');
signal clk_first_quarter : std_logic_vector(28 downto 0) := (others => '1');
signal clk_last_quarter : std_logic_vector(28 downto 0) := (others => '1');
signal busy_sr : std_logic_vector(28 downto 0) := (others => '1');
signal data_sr : std_logic_vector(28 downto 0) := (others => '1');
signal tristate_sr : std_logic_vector(28 downto 0) := (others => '0');
signal reg_value : std_logic_vector(15 downto 0) := (others => '0');
constant i2c_wr_addr : std_logic_vector(7 downto 0) := x"72";
type reg_value_pair is ARRAY(0 TO 63) OF std_logic_vector(15 DOWNTO 0);
signal reg_value_pairs : reg_value_pair := (
-------------------
-- Powerup please!
-------------------
x"4110",
---------------------------------------
-- These values must be set as follows
---------------------------------------
x"9803", x"9AE0", x"9C30", x"9D61", x"A2A4", x"A3A4", x"E0D0", x"5512", x"F900",
---------------
-- Input mode
---------------
x"1506", -- YCbCr 422, DDR, External sync
x"4810", -- Left justified data (D23 downto 8)
x"1637", -- 444 output, 8 bit style 2, 1st half on rising edge - YCrCb clipping
x"1700", -- output aspect ratio 16:9, external DE
x"D03C", -- auto sync data - must be set for DDR modes. No DDR clock delay
---------------
-- Output mode
---------------
x"AF04", -- DVI mode
x"4c04", -- Deep colour off (HDMI only?) - not needed
x"4000", -- Turn off additional data packets - not needed
--------------------------------------------------------------
-- Here is the YCrCb => RGB conversion, as per programming guide
-- This is table 57 - HDTV YCbCr (16 to 255) to RGB (0 to 255)
--------------------------------------------------------------
-- (Cr * A1 + Y * A2 + Cb * A3)/4096 + A4 = Red
x"18E7", x"1934", x"1A04", x"1BAD", x"1C00", x"1D00", x"1E1C", x"1F1B",
-- (Cr * B1 + Y * B2 + Cb * B3)/4096 + B4 = Green
x"201D", x"21DC", x"2204", x"23AD", x"241F", x"2524", x"2601", x"2735",
-- (Cr * C1 + Y * C2 + Cb * C3)/4096 + C4 = Blue
x"2800", x"2900", x"2A04", x"2BAD", x"2C08", x"2D7C", x"2E1B", x"2F77",
-- Extra space filled with FFFFs to signify end of data
x"FFFF", x"FFFF", x"FFFF", x"FFFF", x"FFFF", x"FFFF", x"FFFF",
x"FFFF", x"FFFF", x"FFFF", x"FFFF", x"FFFF", x"FFFF", x"FFFF", x"FFFF",
x"FFFF", x"FFFF", x"FFFF", x"FFFF", x"FFFF", x"FFFF", x"FFFF"
);
begin
registers: process(clk)
begin
if rising_edge(clk) then
reg_value <= reg_value_pairs(to_integer(unsigned(address)));
end if;
end process;
i2c_tristate: process(data_sr, tristate_sr)
begin
if tristate_sr(tristate_sr'length-1) = '0' then
siod <= data_sr(data_sr'length-1);
else
siod <= 'Z';
end if;
end process;
with divider(divider'length-1 downto divider'length-2)
select sioc <= clk_first_quarter(clk_first_quarter'length -1) when "00",
clk_last_quarter(clk_last_quarter'length -1) when "11",
'1' when others;
i2c_send: process(clk)
begin
if rising_edge(clk) then
if resend = '1' then
address <= (others => '0');
clk_first_quarter <= (others => '1');
clk_last_quarter <= (others => '1');
busy_sr <= (others => '0');
divider <= (others => '0');
initial_pause <= (others => '0');
finished <= '0';
end if;
if busy_sr(busy_sr'length-1) = '0' then
if initial_pause(initial_pause'length-1) = '0' then
initial_pause <= initial_pause+1;
elsif finished = '0' then
if divider = "11111111" then
divider <= (others =>'0');
if reg_value(15 downto 8) = "11111111" then
finished <= '1';
else
-- move the new data into the shift registers
clk_first_quarter <= (others => '0'); clk_first_quarter(clk_first_quarter'length-1) <= '1';
clk_last_quarter <= (others => '0'); clk_last_quarter(0) <= '1';
-- Start Address Ack Register Ack Value Ack Stop
tristate_sr <= "0" & "00000000" & "1" & "00000000" & "1" & "00000000" & "1" & "0";
data_sr <= "0" & i2c_wr_addr & "1" & reg_value(15 downto 8) & "1" & reg_value( 7 downto 0) & "1" & "0";
busy_sr <= (others => '1');
address <= std_logic_vector(unsigned(address)+1);
end if;
else
divider <= divider+1;
end if;
end if;
else
if divider = "11111111" then -- divide clkin by 256 for I2C
tristate_sr <= tristate_sr(tristate_sr'length-2 downto 0) & '0';
busy_sr <= busy_sr(busy_sr'length-2 downto 0) & '0';
data_sr <= data_sr(data_sr'length-2 downto 0) & '1';
clk_first_quarter <= clk_first_quarter(clk_first_quarter'length-2 downto 0) & '1';
clk_last_quarter <= clk_last_quarter(clk_first_quarter'length-2 downto 0) & '1';
divider <= (others => '0');
else
divider <= divider+1;
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/video_gaussian_blur/video_gaussian_blur.srcs/sources_1/bd/system/ip/system_vga_gaussian_blur_0_0/synth/system_vga_gaussian_blur_0_0.vhd
|
1
|
5235
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_gaussian_blur:1.0
-- IP Revision: 5
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_gaussian_blur_0_0 IS
PORT (
en : IN STD_LOGIC;
clk_25 : IN STD_LOGIC;
active_in : IN STD_LOGIC;
hsync_in : IN STD_LOGIC;
vsync_in : IN STD_LOGIC;
xaddr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
active_out : OUT STD_LOGIC;
hsync_out : OUT STD_LOGIC;
vsync_out : OUT STD_LOGIC;
xaddr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb_out : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_gaussian_blur_0_0;
ARCHITECTURE system_vga_gaussian_blur_0_0_arch OF system_vga_gaussian_blur_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_gaussian_blur_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_gaussian_blur IS
GENERIC (
H_SIZE : INTEGER;
H_DELAY : INTEGER;
KERNEL : INTEGER
);
PORT (
en : IN STD_LOGIC;
clk_25 : IN STD_LOGIC;
active_in : IN STD_LOGIC;
hsync_in : IN STD_LOGIC;
vsync_in : IN STD_LOGIC;
xaddr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr_in : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb_in : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
active_out : OUT STD_LOGIC;
hsync_out : OUT STD_LOGIC;
vsync_out : OUT STD_LOGIC;
xaddr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
yaddr_out : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
rgb_out : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_gaussian_blur;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_gaussian_blur_0_0_arch: ARCHITECTURE IS "vga_gaussian_blur,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_gaussian_blur_0_0_arch : ARCHITECTURE IS "system_vga_gaussian_blur_0_0,vga_gaussian_blur,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_gaussian_blur_0_0_arch: ARCHITECTURE IS "system_vga_gaussian_blur_0_0,vga_gaussian_blur,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_gaussian_blur,x_ipVersion=1.0,x_ipCoreRevision=5,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,H_SIZE=640,H_DELAY=160,KERNEL=3}";
BEGIN
U0 : vga_gaussian_blur
GENERIC MAP (
H_SIZE => 640,
H_DELAY => 160,
KERNEL => 3
)
PORT MAP (
en => en,
clk_25 => clk_25,
active_in => active_in,
hsync_in => hsync_in,
vsync_in => vsync_in,
xaddr_in => xaddr_in,
yaddr_in => yaddr_in,
rgb_in => rgb_in,
active_out => active_out,
hsync_out => hsync_out,
vsync_out => vsync_out,
xaddr_out => xaddr_out,
yaddr_out => yaddr_out,
rgb_out => rgb_out
);
END system_vga_gaussian_blur_0_0_arch;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_inverter_0_0_1/synth/system_inverter_0_0.vhd
|
10
|
3216
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:inverter:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_inverter_0_0 IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END system_inverter_0_0;
ARCHITECTURE system_inverter_0_0_arch OF system_inverter_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_inverter_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT inverter IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END COMPONENT inverter;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_inverter_0_0_arch: ARCHITECTURE IS "inverter,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_inverter_0_0_arch : ARCHITECTURE IS "system_inverter_0_0,inverter,{}";
BEGIN
U0 : inverter
PORT MAP (
x => x,
x_not => x_not
);
END system_inverter_0_0_arch;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
general_ip/uint_to_ieee754_fp/uint_to_ieee754_fp.srcs/sources_1/new/uint_to_ieee754_fp.vhd
|
3
|
1596
|
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: uint_to_ieee754_fp - Structural
-- Description: Converts an unsigned integer into IEEE-754 floating point notation
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity uint_to_ieee754_fp is
generic(
WIDTH : integer := 10
);
port(
x : in std_logic_vector(WIDTH - 1 downto 0);
y : out std_logic_vector(31 downto 0)
);
end uint_to_ieee754_fp;
architecture Structural of uint_to_ieee754_fp is
signal exponent : std_logic_vector(7 downto 0);
signal mantissa : std_logic_vector(22 downto 0) := "00000000000000000000000";
begin
y(31) <= '0'; -- sign is always positive
y(30 downto 23) <= exponent;
y(22 downto 0) <= mantissa;
process(x)
variable x_exp : integer := 0;
begin
x_exp := -1;
-- find place of most significant '1'
for i in 0 to WIDTH - 1 loop
if x(i) = '1' then
x_exp := i;
end if;
end loop;
if x_exp >= 0 then
exponent <= std_logic_vector(to_signed(x_exp + 127, 8));
-- bit shift x into mantissa
mantissa(22 downto 22 - WIDTH + 1) <= std_logic_vector(unsigned(x) sll WIDTH - x_exp);
else
exponent <= x"00";
mantissa <= "00000000000000000000000";
end if;
end process;
end Structural;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_multiplier_0_0/affine_block_ieee754_fp_multiplier_0_0_stub.vhdl
|
1
|
1514
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 20 13:53:00 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/ZyboIP/general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_multiplier_0_0/affine_block_ieee754_fp_multiplier_0_0_stub.vhdl
-- Design : affine_block_ieee754_fp_multiplier_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity affine_block_ieee754_fp_multiplier_0_0 is
Port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end affine_block_ieee754_fp_multiplier_0_0;
architecture stub of affine_block_ieee754_fp_multiplier_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "x[31:0],y[31:0],z[31:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "ieee754_fp_multiplier,Vivado 2016.4";
begin
end;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
video_ip/vga_sync/vga_sync.srcs/sources_1/new/vga_sync.vhd
|
1
|
2947
|
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: vga_sync - Behavioral
-- Description: Create a sync signal for display pixel data
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vga_sync is
generic(
-- The default values are for 640x480
H_SIZE : integer := 640;
H_FRONT_DELAY : integer := 16;
H_BACK_DELAY : integer := 48;
H_RETRACE_DELAY : integer := 96;
V_SIZE : integer := 480;
V_FRONT_DELAY : integer := 10;
V_BACK_DELAY : integer := 33;
V_RETRACE_DELAY : integer := 2
);
port(
clk : in std_logic;
rst : in std_logic;
active : out std_logic := '0';
hsync : out std_logic := '0';
vsync : out std_logic := '0';
xaddr : out std_logic_vector(9 downto 0);
yaddr : out std_logic_vector(9 downto 0)
);
end vga_sync;
architecture Structural of vga_sync is
-- sync counters
signal v_count_reg : std_logic_vector(9 downto 0);
signal h_count_reg : std_logic_vector(9 downto 0);
begin
-- registers
process (clk, rst)
begin
if rst = '0' then
v_count_reg <= (others=>'0');
h_count_reg <= (others=>'0');
vsync <= '1';
hsync <= '1';
active <= '0';
else
if rising_edge(clk) then
-- Count the lines and rows
if h_count_reg = H_SIZE + H_FRONT_DELAY + H_BACK_DELAY + H_RETRACE_DELAY - 1 then
h_count_reg <= (others => '0');
if v_count_reg = V_SIZE + V_FRONT_DELAY + V_BACK_DELAY + V_RETRACE_DELAY - 1 then
v_count_reg <= (others => '0');
else
v_count_reg <= v_count_reg + 1;
end if;
else
h_count_reg <= h_count_reg + 1;
end if;
if v_count_reg < V_SIZE and h_count_reg < H_SIZE then
active <= '1';
else
active <= '0';
end if;
if h_count_reg > H_SIZE + H_FRONT_DELAY and h_count_reg <= H_SIZE + H_FRONT_DELAY + H_RETRACE_DELAY then
hsync <= '0';
else
hsync <= '1';
end if;
if v_count_reg >= V_SIZE + V_FRONT_DELAY and v_count_reg < V_SIZE + V_FRONT_DELAY + V_RETRACE_DELAY then
vsync <= '0';
else
vsync <= '1';
end if;
end if;
end if;
end process;
xaddr <= h_count_reg;
yaddr <= v_count_reg;
end Structural;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/video_passthrough/video_passthrough.srcs/sources_1/bd/system/ipshared/xilinx.com/zybo_hdmi_v1_0/tmds_encoder.vhd
|
6
|
4438
|
----------------------------------------------------------------------------------
-- Company: DBRSS
-- Engineer: Daniel Barcklow
-- Module: TOP level DVI-D
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Adapted by: Rob Taglang
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TMDS_encoder is
port(
clk : in std_logic;
d_in : in std_logic_vector(7 downto 0); -- 8 bit d_in to be encoded
C : in std_logic_vector(1 downto 0); -- control bits (2)
video_on : in std_logic; -- BLANKING, is video on?
encoded : out std_logic_vector(9 downto 0)); -- output encoded
end TMDS_encoder;
architecture Behavioral of TMDS_encoder is
signal xored : std_logic_vector(8 downto 0);
signal xnored : std_logic_vector(8 downto 0);
signal ones : std_logic_vector(3 downto 0);
signal q_m : std_logic_vector(8 downto 0);
signal q_m_inv : std_logic_vector(8 downto 0);
signal data_word_disparity : std_logic_vector(3 downto 0);
signal dc_bias : std_logic_vector(3 downto 0) := (others => '0');
begin
-- Perform FALSE<1> computations
xored(0) <= d_in(0);
xored(1) <= d_in(1) xor xored(0);
xored(2) <= d_in(2) xor xored(1);
xored(3) <= d_in(3) xor xored(2);
xored(4) <= d_in(4) xor xored(3);
xored(5) <= d_in(5) xor xored(4);
xored(6) <= d_in(6) xor xored(5);
xored(7) <= d_in(7) xor xored(6);
xored(8) <= '1';
-- Perform TRUE<1> computations
xnored(0) <= d_in(0);
xnored(1) <= d_in(1) xnor xnored(0);
xnored(2) <= d_in(2) xnor xnored(1);
xnored(3) <= d_in(3) xnor xnored(2);
xnored(4) <= d_in(4) xnor xnored(3);
xnored(5) <= d_in(5) xnor xnored(4);
xnored(6) <= d_in(6) xnor xnored(5);
xnored(7) <= d_in(7) xnor xnored(6);
xnored(8) <= '0';
-- count all 1's by adding them (0 won't contribute)
ones <= "0000" + d_in(0) + d_in(1) + d_in(2) + d_in(3)
+ d_in(4) + d_in(5) + d_in(6) + d_in(7);
-- decide on encoding
decision0: process(ones, d_in(0), xnored, xored)
begin
-- FIRST CHOICE DIAMOND (https://www.eewiki.net/pages/viewpage.action?pageId=36569119) <1>
if ones > 4 or (ones = 4 and d_in(0) = '0') then
q_m <= xnored;
q_m_inv <= NOT(xnored);
else
q_m <= xored;
q_m_inv <= NOT(xored);
end if;
end process decision0;
-- Work out the DC bias of the dataword;
data_word_disparity <= "1100" + q_m(0) + q_m(1) + q_m(2) + q_m(3)
+ q_m(4) + q_m(5) + q_m(6) + q_m(7);
-- Now work out what the output should be
process(clk)
begin
-- "DISPLAY ENABLE = 1"
if rising_edge(clk) then
if video_on = '0' then
-- In the control periods, all values have and have balanced bit count
case C is
when "00" => encoded <= "1101010100";
when "01" => encoded <= "0010101011";
when "10" => encoded <= "0101010100";
when others => encoded <= "1010101011";
end case;
dc_bias <= (others => '0');
else
-- Ones#(d) = 4 OR disparity = 0
if dc_bias = "00000" or data_word_disparity = 0 then
-- dataword has no disparity
if q_m(8) = '0' then
encoded <= "10" & q_m_inv(7 downto 0);
dc_bias <= dc_bias - data_word_disparity;
else
encoded <= "01" & q_m(7 downto 0);
dc_bias <= dc_bias + data_word_disparity;
end if;
elsif (dc_bias(3) = '0' and data_word_disparity(3) = '0') or
(dc_bias(3) = '1' and data_word_disparity(3) = '1') then
encoded <= '1' & q_m(8) & q_m_inv(7 downto 0);
dc_bias <= dc_bias + q_m(8) - data_word_disparity;
else
encoded <= '0' & q_m;
dc_bias <= dc_bias - q_m_inv(8) + data_word_disparity;
end if;
end if;
end if;
end process;
end Behavioral;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ipshared/737d/debounce.vhd
|
5
|
746
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity debounce is
port (
clk : in std_logic;
signal_in : in std_logic;
signal_out : out std_logic
);
end debounce;
architecture Behavioral of debounce is
signal c : unsigned(23 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
if signal_in = '1' then
if c = x"FFFFFF" then
signal_out <= '1';
else
signal_out <= '0';
end if;
c <= c + 1;
else
c <= (others => '0');
signal_out <= '0';
end if;
end if;
end process;
end Behavioral;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_clk_wiz_0_0_1/system_clk_wiz_0_0_sim_netlist.vhdl
|
1
|
7622
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 07:02:45 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_clk_wiz_0_0_1/system_clk_wiz_0_0_sim_netlist.vhdl
-- Design : system_clk_wiz_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz is
port (
clk_out1 : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz : entity is "system_clk_wiz_0_0_clk_wiz";
end system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz;
architecture STRUCTURE of system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz is
signal clk_in1_system_clk_wiz_0_0 : STD_LOGIC;
signal clk_out1_system_clk_wiz_0_0 : STD_LOGIC;
signal clkfbout_buf_system_clk_wiz_0_0 : STD_LOGIC;
signal clkfbout_system_clk_wiz_0_0 : STD_LOGIC;
signal reset_high : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_system_clk_wiz_0_0,
O => clkfbout_buf_system_clk_wiz_0_0
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1,
O => clk_in1_system_clk_wiz_0_0
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_out1_system_clk_wiz_0_0,
O => clk_out1
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 9.125000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 36.500000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_system_clk_wiz_0_0,
CLKFBOUT => clkfbout_system_clk_wiz_0_0,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_in1_system_clk_wiz_0_0,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_out1_system_clk_wiz_0_0,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => locked,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => reset_high
);
mmcm_adv_inst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => resetn,
O => reset_high
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clk_wiz_0_0 is
port (
clk_out1 : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_clk_wiz_0_0 : entity is true;
end system_clk_wiz_0_0;
architecture STRUCTURE of system_clk_wiz_0_0 is
begin
inst: entity work.system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1,
locked => locked,
resetn => resetn
);
end STRUCTURE;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0_sim_netlist.vhdl
|
1
|
196508
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed May 31 20:12:00 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0_sim_netlist.vhdl
-- Design : system_processing_system7_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_processing_system7_0_0_processing_system7_v5_5_processing_system7 is
port (
CAN0_PHY_TX : out STD_LOGIC;
CAN0_PHY_RX : in STD_LOGIC;
CAN1_PHY_TX : out STD_LOGIC;
CAN1_PHY_RX : in STD_LOGIC;
ENET0_GMII_TX_EN : out STD_LOGIC;
ENET0_GMII_TX_ER : out STD_LOGIC;
ENET0_MDIO_MDC : out STD_LOGIC;
ENET0_MDIO_O : out STD_LOGIC;
ENET0_MDIO_T : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET0_GMII_COL : in STD_LOGIC;
ENET0_GMII_CRS : in STD_LOGIC;
ENET0_GMII_RX_CLK : in STD_LOGIC;
ENET0_GMII_RX_DV : in STD_LOGIC;
ENET0_GMII_RX_ER : in STD_LOGIC;
ENET0_GMII_TX_CLK : in STD_LOGIC;
ENET0_MDIO_I : in STD_LOGIC;
ENET0_EXT_INTIN : in STD_LOGIC;
ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_TX_EN : out STD_LOGIC;
ENET1_GMII_TX_ER : out STD_LOGIC;
ENET1_MDIO_MDC : out STD_LOGIC;
ENET1_MDIO_O : out STD_LOGIC;
ENET1_MDIO_T : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET1_SOF_RX : out STD_LOGIC;
ENET1_SOF_TX : out STD_LOGIC;
ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_COL : in STD_LOGIC;
ENET1_GMII_CRS : in STD_LOGIC;
ENET1_GMII_RX_CLK : in STD_LOGIC;
ENET1_GMII_RX_DV : in STD_LOGIC;
ENET1_GMII_RX_ER : in STD_LOGIC;
ENET1_GMII_TX_CLK : in STD_LOGIC;
ENET1_MDIO_I : in STD_LOGIC;
ENET1_EXT_INTIN : in STD_LOGIC;
ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 );
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
PJTAG_TCK : in STD_LOGIC;
PJTAG_TMS : in STD_LOGIC;
PJTAG_TDI : in STD_LOGIC;
PJTAG_TDO : out STD_LOGIC;
SDIO0_CLK : out STD_LOGIC;
SDIO0_CLK_FB : in STD_LOGIC;
SDIO0_CMD_O : out STD_LOGIC;
SDIO0_CMD_I : in STD_LOGIC;
SDIO0_CMD_T : out STD_LOGIC;
SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_LED : out STD_LOGIC;
SDIO0_CDN : in STD_LOGIC;
SDIO0_WP : in STD_LOGIC;
SDIO0_BUSPOW : out STD_LOGIC;
SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SDIO1_CLK : out STD_LOGIC;
SDIO1_CLK_FB : in STD_LOGIC;
SDIO1_CMD_O : out STD_LOGIC;
SDIO1_CMD_I : in STD_LOGIC;
SDIO1_CMD_T : out STD_LOGIC;
SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_LED : out STD_LOGIC;
SDIO1_CDN : in STD_LOGIC;
SDIO1_WP : in STD_LOGIC;
SDIO1_BUSPOW : out STD_LOGIC;
SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SPI0_SCLK_I : in STD_LOGIC;
SPI0_SCLK_O : out STD_LOGIC;
SPI0_SCLK_T : out STD_LOGIC;
SPI0_MOSI_I : in STD_LOGIC;
SPI0_MOSI_O : out STD_LOGIC;
SPI0_MOSI_T : out STD_LOGIC;
SPI0_MISO_I : in STD_LOGIC;
SPI0_MISO_O : out STD_LOGIC;
SPI0_MISO_T : out STD_LOGIC;
SPI0_SS_I : in STD_LOGIC;
SPI0_SS_O : out STD_LOGIC;
SPI0_SS1_O : out STD_LOGIC;
SPI0_SS2_O : out STD_LOGIC;
SPI0_SS_T : out STD_LOGIC;
SPI1_SCLK_I : in STD_LOGIC;
SPI1_SCLK_O : out STD_LOGIC;
SPI1_SCLK_T : out STD_LOGIC;
SPI1_MOSI_I : in STD_LOGIC;
SPI1_MOSI_O : out STD_LOGIC;
SPI1_MOSI_T : out STD_LOGIC;
SPI1_MISO_I : in STD_LOGIC;
SPI1_MISO_O : out STD_LOGIC;
SPI1_MISO_T : out STD_LOGIC;
SPI1_SS_I : in STD_LOGIC;
SPI1_SS_O : out STD_LOGIC;
SPI1_SS1_O : out STD_LOGIC;
SPI1_SS2_O : out STD_LOGIC;
SPI1_SS_T : out STD_LOGIC;
UART0_DTRN : out STD_LOGIC;
UART0_RTSN : out STD_LOGIC;
UART0_TX : out STD_LOGIC;
UART0_CTSN : in STD_LOGIC;
UART0_DCDN : in STD_LOGIC;
UART0_DSRN : in STD_LOGIC;
UART0_RIN : in STD_LOGIC;
UART0_RX : in STD_LOGIC;
UART1_DTRN : out STD_LOGIC;
UART1_RTSN : out STD_LOGIC;
UART1_TX : out STD_LOGIC;
UART1_CTSN : in STD_LOGIC;
UART1_DCDN : in STD_LOGIC;
UART1_DSRN : in STD_LOGIC;
UART1_RIN : in STD_LOGIC;
UART1_RX : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
TTC0_CLK0_IN : in STD_LOGIC;
TTC0_CLK1_IN : in STD_LOGIC;
TTC0_CLK2_IN : in STD_LOGIC;
TTC1_WAVE0_OUT : out STD_LOGIC;
TTC1_WAVE1_OUT : out STD_LOGIC;
TTC1_WAVE2_OUT : out STD_LOGIC;
TTC1_CLK0_IN : in STD_LOGIC;
TTC1_CLK1_IN : in STD_LOGIC;
TTC1_CLK2_IN : in STD_LOGIC;
WDT_CLK_IN : in STD_LOGIC;
WDT_RST_OUT : out STD_LOGIC;
TRACE_CLK : in STD_LOGIC;
TRACE_CTL : out STD_LOGIC;
TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 );
TRACE_CLK_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB1_VBUS_PWRSELECT : out STD_LOGIC;
USB1_VBUS_PWRFAULT : in STD_LOGIC;
SRAM_INTIN : in STD_LOGIC;
M_AXI_GP0_ARESETN : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARESETN : out STD_LOGIC;
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARESETN : out STD_LOGIC;
S_AXI_GP0_ARREADY : out STD_LOGIC;
S_AXI_GP0_AWREADY : out STD_LOGIC;
S_AXI_GP0_BVALID : out STD_LOGIC;
S_AXI_GP0_RLAST : out STD_LOGIC;
S_AXI_GP0_RVALID : out STD_LOGIC;
S_AXI_GP0_WREADY : out STD_LOGIC;
S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_ACLK : in STD_LOGIC;
S_AXI_GP0_ARVALID : in STD_LOGIC;
S_AXI_GP0_AWVALID : in STD_LOGIC;
S_AXI_GP0_BREADY : in STD_LOGIC;
S_AXI_GP0_RREADY : in STD_LOGIC;
S_AXI_GP0_WLAST : in STD_LOGIC;
S_AXI_GP0_WVALID : in STD_LOGIC;
S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ARESETN : out STD_LOGIC;
S_AXI_GP1_ARREADY : out STD_LOGIC;
S_AXI_GP1_AWREADY : out STD_LOGIC;
S_AXI_GP1_BVALID : out STD_LOGIC;
S_AXI_GP1_RLAST : out STD_LOGIC;
S_AXI_GP1_RVALID : out STD_LOGIC;
S_AXI_GP1_WREADY : out STD_LOGIC;
S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ACLK : in STD_LOGIC;
S_AXI_GP1_ARVALID : in STD_LOGIC;
S_AXI_GP1_AWVALID : in STD_LOGIC;
S_AXI_GP1_BREADY : in STD_LOGIC;
S_AXI_GP1_RREADY : in STD_LOGIC;
S_AXI_GP1_WLAST : in STD_LOGIC;
S_AXI_GP1_WVALID : in STD_LOGIC;
S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_ACP_ARESETN : out STD_LOGIC;
S_AXI_ACP_ARREADY : out STD_LOGIC;
S_AXI_ACP_AWREADY : out STD_LOGIC;
S_AXI_ACP_BVALID : out STD_LOGIC;
S_AXI_ACP_RLAST : out STD_LOGIC;
S_AXI_ACP_RVALID : out STD_LOGIC;
S_AXI_ACP_WREADY : out STD_LOGIC;
S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_ACLK : in STD_LOGIC;
S_AXI_ACP_ARVALID : in STD_LOGIC;
S_AXI_ACP_AWVALID : in STD_LOGIC;
S_AXI_ACP_BREADY : in STD_LOGIC;
S_AXI_ACP_RREADY : in STD_LOGIC;
S_AXI_ACP_WLAST : in STD_LOGIC;
S_AXI_ACP_WVALID : in STD_LOGIC;
S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_ARESETN : out STD_LOGIC;
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_ARESETN : out STD_LOGIC;
S_AXI_HP1_ARREADY : out STD_LOGIC;
S_AXI_HP1_AWREADY : out STD_LOGIC;
S_AXI_HP1_BVALID : out STD_LOGIC;
S_AXI_HP1_RLAST : out STD_LOGIC;
S_AXI_HP1_RVALID : out STD_LOGIC;
S_AXI_HP1_WREADY : out STD_LOGIC;
S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_ACLK : in STD_LOGIC;
S_AXI_HP1_ARVALID : in STD_LOGIC;
S_AXI_HP1_AWVALID : in STD_LOGIC;
S_AXI_HP1_BREADY : in STD_LOGIC;
S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_RREADY : in STD_LOGIC;
S_AXI_HP1_WLAST : in STD_LOGIC;
S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_WVALID : in STD_LOGIC;
S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_ARESETN : out STD_LOGIC;
S_AXI_HP2_ARREADY : out STD_LOGIC;
S_AXI_HP2_AWREADY : out STD_LOGIC;
S_AXI_HP2_BVALID : out STD_LOGIC;
S_AXI_HP2_RLAST : out STD_LOGIC;
S_AXI_HP2_RVALID : out STD_LOGIC;
S_AXI_HP2_WREADY : out STD_LOGIC;
S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_ACLK : in STD_LOGIC;
S_AXI_HP2_ARVALID : in STD_LOGIC;
S_AXI_HP2_AWVALID : in STD_LOGIC;
S_AXI_HP2_BREADY : in STD_LOGIC;
S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_RREADY : in STD_LOGIC;
S_AXI_HP2_WLAST : in STD_LOGIC;
S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_WVALID : in STD_LOGIC;
S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_ARESETN : out STD_LOGIC;
S_AXI_HP3_ARREADY : out STD_LOGIC;
S_AXI_HP3_AWREADY : out STD_LOGIC;
S_AXI_HP3_BVALID : out STD_LOGIC;
S_AXI_HP3_RLAST : out STD_LOGIC;
S_AXI_HP3_RVALID : out STD_LOGIC;
S_AXI_HP3_WREADY : out STD_LOGIC;
S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_ACLK : in STD_LOGIC;
S_AXI_HP3_ARVALID : in STD_LOGIC;
S_AXI_HP3_AWVALID : in STD_LOGIC;
S_AXI_HP3_BREADY : in STD_LOGIC;
S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_RREADY : in STD_LOGIC;
S_AXI_HP3_WLAST : in STD_LOGIC;
S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_WVALID : in STD_LOGIC;
S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_P2F_DMAC_ABORT : out STD_LOGIC;
IRQ_P2F_DMAC0 : out STD_LOGIC;
IRQ_P2F_DMAC1 : out STD_LOGIC;
IRQ_P2F_DMAC2 : out STD_LOGIC;
IRQ_P2F_DMAC3 : out STD_LOGIC;
IRQ_P2F_DMAC4 : out STD_LOGIC;
IRQ_P2F_DMAC5 : out STD_LOGIC;
IRQ_P2F_DMAC6 : out STD_LOGIC;
IRQ_P2F_DMAC7 : out STD_LOGIC;
IRQ_P2F_SMC : out STD_LOGIC;
IRQ_P2F_QSPI : out STD_LOGIC;
IRQ_P2F_CTI : out STD_LOGIC;
IRQ_P2F_GPIO : out STD_LOGIC;
IRQ_P2F_USB0 : out STD_LOGIC;
IRQ_P2F_ENET0 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE0 : out STD_LOGIC;
IRQ_P2F_SDIO0 : out STD_LOGIC;
IRQ_P2F_I2C0 : out STD_LOGIC;
IRQ_P2F_SPI0 : out STD_LOGIC;
IRQ_P2F_UART0 : out STD_LOGIC;
IRQ_P2F_CAN0 : out STD_LOGIC;
IRQ_P2F_USB1 : out STD_LOGIC;
IRQ_P2F_ENET1 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE1 : out STD_LOGIC;
IRQ_P2F_SDIO1 : out STD_LOGIC;
IRQ_P2F_I2C1 : out STD_LOGIC;
IRQ_P2F_SPI1 : out STD_LOGIC;
IRQ_P2F_UART1 : out STD_LOGIC;
IRQ_P2F_CAN1 : out STD_LOGIC;
IRQ_F2P : in STD_LOGIC_VECTOR ( 1 downto 0 );
Core0_nFIQ : in STD_LOGIC;
Core0_nIRQ : in STD_LOGIC;
Core1_nFIQ : in STD_LOGIC;
Core1_nIRQ : in STD_LOGIC;
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA0_RSTN : out STD_LOGIC;
DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DAVALID : out STD_LOGIC;
DMA1_DRREADY : out STD_LOGIC;
DMA1_RSTN : out STD_LOGIC;
DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DAVALID : out STD_LOGIC;
DMA2_DRREADY : out STD_LOGIC;
DMA2_RSTN : out STD_LOGIC;
DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DAVALID : out STD_LOGIC;
DMA3_DRREADY : out STD_LOGIC;
DMA3_RSTN : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA1_ACLK : in STD_LOGIC;
DMA1_DAREADY : in STD_LOGIC;
DMA1_DRLAST : in STD_LOGIC;
DMA1_DRVALID : in STD_LOGIC;
DMA2_ACLK : in STD_LOGIC;
DMA2_DAREADY : in STD_LOGIC;
DMA2_DRLAST : in STD_LOGIC;
DMA2_DRVALID : in STD_LOGIC;
DMA3_ACLK : in STD_LOGIC;
DMA3_DAREADY : in STD_LOGIC;
DMA3_DRLAST : in STD_LOGIC;
DMA3_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK3 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLKTRIG3_N : in STD_LOGIC;
FCLK_CLKTRIG2_N : in STD_LOGIC;
FCLK_CLKTRIG1_N : in STD_LOGIC;
FCLK_CLKTRIG0_N : in STD_LOGIC;
FCLK_RESET3_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMD_TRACEIN_VALID : in STD_LOGIC;
FTMD_TRACEIN_CLK : in STD_LOGIC;
FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 );
FTMT_F2P_TRIG_0 : in STD_LOGIC;
FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
FTMT_F2P_TRIG_1 : in STD_LOGIC;
FTMT_F2P_TRIGACK_1 : out STD_LOGIC;
FTMT_F2P_TRIG_2 : in STD_LOGIC;
FTMT_F2P_TRIGACK_2 : out STD_LOGIC;
FTMT_F2P_TRIG_3 : in STD_LOGIC;
FTMT_F2P_TRIGACK_3 : out STD_LOGIC;
FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
FTMT_P2F_TRIG_0 : out STD_LOGIC;
FTMT_P2F_TRIGACK_1 : in STD_LOGIC;
FTMT_P2F_TRIG_1 : out STD_LOGIC;
FTMT_P2F_TRIGACK_2 : in STD_LOGIC;
FTMT_P2F_TRIG_2 : out STD_LOGIC;
FTMT_P2F_TRIGACK_3 : in STD_LOGIC;
FTMT_P2F_TRIG_3 : out STD_LOGIC;
FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 );
FPGA_IDLE_N : in STD_LOGIC;
EVENT_EVENTO : out STD_LOGIC;
EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_EVENTI : in STD_LOGIC;
DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 );
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "system_processing_system7_0_0.hwdef";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "processing_system7_v5_5_processing_system7";
attribute POWER : string;
attribute POWER of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={S_AXI_HP0} dataWidth={64} clockFreq={100} usageRate={0.5} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0;
end system_processing_system7_0_0_processing_system7_v5_5_processing_system7;
architecture STRUCTURE of system_processing_system7_0_0_processing_system7_v5_5_processing_system7 is
signal \<const0>\ : STD_LOGIC;
signal ENET0_MDIO_T_n : STD_LOGIC;
signal ENET1_MDIO_T_n : STD_LOGIC;
signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 );
signal I2C0_SCL_T_n : STD_LOGIC;
signal I2C0_SDA_T_n : STD_LOGIC;
signal I2C1_SCL_T_n : STD_LOGIC;
signal I2C1_SDA_T_n : STD_LOGIC;
signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal SDIO0_CMD_T_n : STD_LOGIC;
signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SDIO1_CMD_T_n : STD_LOGIC;
signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SPI0_MISO_T_n : STD_LOGIC;
signal SPI0_MOSI_T_n : STD_LOGIC;
signal SPI0_SCLK_T_n : STD_LOGIC;
signal SPI0_SS_T_n : STD_LOGIC;
signal SPI1_MISO_T_n : STD_LOGIC;
signal SPI1_MOSI_T_n : STD_LOGIC;
signal SPI1_SCLK_T_n : STD_LOGIC;
signal SPI1_SS_T_n : STD_LOGIC;
signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true";
signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true";
signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true";
signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true";
signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true";
signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true";
signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true";
signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true";
signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true";
signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true";
signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true";
signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true";
signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true";
signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true";
signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true";
signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true";
signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 );
signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal buffered_DDR_CAS_n : STD_LOGIC;
signal buffered_DDR_CKE : STD_LOGIC;
signal buffered_DDR_CS_n : STD_LOGIC;
signal buffered_DDR_Clk : STD_LOGIC;
signal buffered_DDR_Clk_n : STD_LOGIC;
signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DRSTB : STD_LOGIC;
signal buffered_DDR_ODT : STD_LOGIC;
signal buffered_DDR_RAS_n : STD_LOGIC;
signal buffered_DDR_VRN : STD_LOGIC;
signal buffered_DDR_VRP : STD_LOGIC;
signal buffered_DDR_WEB : STD_LOGIC;
signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal buffered_PS_CLK : STD_LOGIC;
signal buffered_PS_PORB : STD_LOGIC;
signal buffered_PS_SRSTB : STD_LOGIC;
signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS7_i : label is "PRIMITIVE";
attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
begin
ENET0_GMII_TXD(7) <= \<const0>\;
ENET0_GMII_TXD(6) <= \<const0>\;
ENET0_GMII_TXD(5) <= \<const0>\;
ENET0_GMII_TXD(4) <= \<const0>\;
ENET0_GMII_TXD(3) <= \<const0>\;
ENET0_GMII_TXD(2) <= \<const0>\;
ENET0_GMII_TXD(1) <= \<const0>\;
ENET0_GMII_TXD(0) <= \<const0>\;
ENET0_GMII_TX_EN <= \<const0>\;
ENET0_GMII_TX_ER <= \<const0>\;
ENET1_GMII_TXD(7) <= \<const0>\;
ENET1_GMII_TXD(6) <= \<const0>\;
ENET1_GMII_TXD(5) <= \<const0>\;
ENET1_GMII_TXD(4) <= \<const0>\;
ENET1_GMII_TXD(3) <= \<const0>\;
ENET1_GMII_TXD(2) <= \<const0>\;
ENET1_GMII_TXD(1) <= \<const0>\;
ENET1_GMII_TXD(0) <= \<const0>\;
ENET1_GMII_TX_EN <= \<const0>\;
ENET1_GMII_TX_ER <= \<const0>\;
M_AXI_GP0_ARSIZE(2) <= \<const0>\;
M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0);
M_AXI_GP0_AWSIZE(2) <= \<const0>\;
M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0);
M_AXI_GP1_ARSIZE(2) <= \<const0>\;
M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0);
M_AXI_GP1_AWSIZE(2) <= \<const0>\;
M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0);
PJTAG_TDO <= \<const0>\;
TRACE_CLK_OUT <= \<const0>\;
TRACE_CTL <= \TRACE_CTL_PIPE[0]\;
TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0);
DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CAS_n,
PAD => DDR_CAS_n
);
DDR_CKE_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CKE,
PAD => DDR_CKE
);
DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CS_n,
PAD => DDR_CS_n
);
DDR_Clk_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk,
PAD => DDR_Clk
);
DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk_n,
PAD => DDR_Clk_n
);
DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DRSTB,
PAD => DDR_DRSTB
);
DDR_ODT_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_ODT,
PAD => DDR_ODT
);
DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_RAS_n,
PAD => DDR_RAS_n
);
DDR_VRN_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRN,
PAD => DDR_VRN
);
DDR_VRP_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRP,
PAD => DDR_VRP
);
DDR_WEB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_WEB,
PAD => DDR_WEB
);
ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET0_MDIO_T_n,
O => ENET0_MDIO_T
);
ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET1_MDIO_T_n,
O => ENET1_MDIO_T
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(0),
O => GPIO_T(0)
);
\GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(10),
O => GPIO_T(10)
);
\GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(11),
O => GPIO_T(11)
);
\GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(12),
O => GPIO_T(12)
);
\GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(13),
O => GPIO_T(13)
);
\GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(14),
O => GPIO_T(14)
);
\GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(15),
O => GPIO_T(15)
);
\GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(16),
O => GPIO_T(16)
);
\GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(17),
O => GPIO_T(17)
);
\GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(18),
O => GPIO_T(18)
);
\GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(19),
O => GPIO_T(19)
);
\GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(1),
O => GPIO_T(1)
);
\GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(20),
O => GPIO_T(20)
);
\GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(21),
O => GPIO_T(21)
);
\GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(22),
O => GPIO_T(22)
);
\GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(23),
O => GPIO_T(23)
);
\GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(24),
O => GPIO_T(24)
);
\GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(25),
O => GPIO_T(25)
);
\GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(26),
O => GPIO_T(26)
);
\GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(27),
O => GPIO_T(27)
);
\GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(28),
O => GPIO_T(28)
);
\GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(29),
O => GPIO_T(29)
);
\GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(2),
O => GPIO_T(2)
);
\GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(30),
O => GPIO_T(30)
);
\GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(31),
O => GPIO_T(31)
);
\GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(32),
O => GPIO_T(32)
);
\GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(33),
O => GPIO_T(33)
);
\GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(34),
O => GPIO_T(34)
);
\GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(35),
O => GPIO_T(35)
);
\GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(36),
O => GPIO_T(36)
);
\GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(37),
O => GPIO_T(37)
);
\GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(38),
O => GPIO_T(38)
);
\GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(39),
O => GPIO_T(39)
);
\GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(3),
O => GPIO_T(3)
);
\GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(40),
O => GPIO_T(40)
);
\GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(41),
O => GPIO_T(41)
);
\GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(42),
O => GPIO_T(42)
);
\GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(43),
O => GPIO_T(43)
);
\GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(44),
O => GPIO_T(44)
);
\GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(45),
O => GPIO_T(45)
);
\GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(46),
O => GPIO_T(46)
);
\GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(47),
O => GPIO_T(47)
);
\GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(48),
O => GPIO_T(48)
);
\GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(49),
O => GPIO_T(49)
);
\GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(4),
O => GPIO_T(4)
);
\GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(50),
O => GPIO_T(50)
);
\GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(51),
O => GPIO_T(51)
);
\GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(52),
O => GPIO_T(52)
);
\GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(53),
O => GPIO_T(53)
);
\GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(54),
O => GPIO_T(54)
);
\GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(55),
O => GPIO_T(55)
);
\GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(56),
O => GPIO_T(56)
);
\GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(57),
O => GPIO_T(57)
);
\GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(58),
O => GPIO_T(58)
);
\GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(59),
O => GPIO_T(59)
);
\GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(5),
O => GPIO_T(5)
);
\GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(60),
O => GPIO_T(60)
);
\GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(61),
O => GPIO_T(61)
);
\GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(62),
O => GPIO_T(62)
);
\GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(63),
O => GPIO_T(63)
);
\GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(6),
O => GPIO_T(6)
);
\GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(7),
O => GPIO_T(7)
);
\GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(8),
O => GPIO_T(8)
);
\GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(9),
O => GPIO_T(9)
);
I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SCL_T_n,
O => I2C0_SCL_T
);
I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SDA_T_n,
O => I2C0_SDA_T
);
I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SCL_T_n,
O => I2C1_SCL_T
);
I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SDA_T_n,
O => I2C1_SDA_T
);
PS7_i: unisim.vcomponents.PS7
port map (
DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0),
DDRARB(3 downto 0) => DDR_ARB(3 downto 0),
DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0),
DDRCASB => buffered_DDR_CAS_n,
DDRCKE => buffered_DDR_CKE,
DDRCKN => buffered_DDR_Clk_n,
DDRCKP => buffered_DDR_Clk,
DDRCSB => buffered_DDR_CS_n,
DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0),
DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0),
DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0),
DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0),
DDRDRSTB => buffered_DDR_DRSTB,
DDRODT => buffered_DDR_ODT,
DDRRASB => buffered_DDR_RAS_n,
DDRVRN => buffered_DDR_VRN,
DDRVRP => buffered_DDR_VRP,
DDRWEB => buffered_DDR_WEB,
DMA0ACLK => DMA0_ACLK,
DMA0DAREADY => DMA0_DAREADY,
DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0),
DMA0DAVALID => DMA0_DAVALID,
DMA0DRLAST => DMA0_DRLAST,
DMA0DRREADY => DMA0_DRREADY,
DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0),
DMA0DRVALID => DMA0_DRVALID,
DMA0RSTN => DMA0_RSTN,
DMA1ACLK => DMA1_ACLK,
DMA1DAREADY => DMA1_DAREADY,
DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0),
DMA1DAVALID => DMA1_DAVALID,
DMA1DRLAST => DMA1_DRLAST,
DMA1DRREADY => DMA1_DRREADY,
DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0),
DMA1DRVALID => DMA1_DRVALID,
DMA1RSTN => DMA1_RSTN,
DMA2ACLK => DMA2_ACLK,
DMA2DAREADY => DMA2_DAREADY,
DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0),
DMA2DAVALID => DMA2_DAVALID,
DMA2DRLAST => DMA2_DRLAST,
DMA2DRREADY => DMA2_DRREADY,
DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0),
DMA2DRVALID => DMA2_DRVALID,
DMA2RSTN => DMA2_RSTN,
DMA3ACLK => DMA3_ACLK,
DMA3DAREADY => DMA3_DAREADY,
DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0),
DMA3DAVALID => DMA3_DAVALID,
DMA3DRLAST => DMA3_DRLAST,
DMA3DRREADY => DMA3_DRREADY,
DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0),
DMA3DRVALID => DMA3_DRVALID,
DMA3RSTN => DMA3_RSTN,
EMIOCAN0PHYRX => CAN0_PHY_RX,
EMIOCAN0PHYTX => CAN0_PHY_TX,
EMIOCAN1PHYRX => CAN1_PHY_RX,
EMIOCAN1PHYTX => CAN1_PHY_TX,
EMIOENET0EXTINTIN => ENET0_EXT_INTIN,
EMIOENET0GMIICOL => '0',
EMIOENET0GMIICRS => '0',
EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK,
EMIOENET0GMIIRXD(7 downto 0) => B"00000000",
EMIOENET0GMIIRXDV => '0',
EMIOENET0GMIIRXER => '0',
EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK,
EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED,
EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED,
EMIOENET0MDIOI => ENET0_MDIO_I,
EMIOENET0MDIOMDC => ENET0_MDIO_MDC,
EMIOENET0MDIOO => ENET0_MDIO_O,
EMIOENET0MDIOTN => ENET0_MDIO_T_n,
EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX,
EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX,
EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX,
EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX,
EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX,
EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX,
EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX,
EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX,
EMIOENET0SOFRX => ENET0_SOF_RX,
EMIOENET0SOFTX => ENET0_SOF_TX,
EMIOENET1EXTINTIN => ENET1_EXT_INTIN,
EMIOENET1GMIICOL => '0',
EMIOENET1GMIICRS => '0',
EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK,
EMIOENET1GMIIRXD(7 downto 0) => B"00000000",
EMIOENET1GMIIRXDV => '0',
EMIOENET1GMIIRXER => '0',
EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK,
EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED,
EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED,
EMIOENET1MDIOI => ENET1_MDIO_I,
EMIOENET1MDIOMDC => ENET1_MDIO_MDC,
EMIOENET1MDIOO => ENET1_MDIO_O,
EMIOENET1MDIOTN => ENET1_MDIO_T_n,
EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX,
EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX,
EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX,
EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX,
EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX,
EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX,
EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX,
EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX,
EMIOENET1SOFRX => ENET1_SOF_RX,
EMIOENET1SOFTX => ENET1_SOF_TX,
EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0),
EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0),
EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0),
EMIOI2C0SCLI => I2C0_SCL_I,
EMIOI2C0SCLO => I2C0_SCL_O,
EMIOI2C0SCLTN => I2C0_SCL_T_n,
EMIOI2C0SDAI => I2C0_SDA_I,
EMIOI2C0SDAO => I2C0_SDA_O,
EMIOI2C0SDATN => I2C0_SDA_T_n,
EMIOI2C1SCLI => I2C1_SCL_I,
EMIOI2C1SCLO => I2C1_SCL_O,
EMIOI2C1SCLTN => I2C1_SCL_T_n,
EMIOI2C1SDAI => I2C1_SDA_I,
EMIOI2C1SDAO => I2C1_SDA_O,
EMIOI2C1SDATN => I2C1_SDA_T_n,
EMIOPJTAGTCK => PJTAG_TCK,
EMIOPJTAGTDI => PJTAG_TDI,
EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED,
EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED,
EMIOPJTAGTMS => PJTAG_TMS,
EMIOSDIO0BUSPOW => SDIO0_BUSPOW,
EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0),
EMIOSDIO0CDN => SDIO0_CDN,
EMIOSDIO0CLK => SDIO0_CLK,
EMIOSDIO0CLKFB => SDIO0_CLK_FB,
EMIOSDIO0CMDI => SDIO0_CMD_I,
EMIOSDIO0CMDO => SDIO0_CMD_O,
EMIOSDIO0CMDTN => SDIO0_CMD_T_n,
EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0),
EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0),
EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0),
EMIOSDIO0LED => SDIO0_LED,
EMIOSDIO0WP => SDIO0_WP,
EMIOSDIO1BUSPOW => SDIO1_BUSPOW,
EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0),
EMIOSDIO1CDN => SDIO1_CDN,
EMIOSDIO1CLK => SDIO1_CLK,
EMIOSDIO1CLKFB => SDIO1_CLK_FB,
EMIOSDIO1CMDI => SDIO1_CMD_I,
EMIOSDIO1CMDO => SDIO1_CMD_O,
EMIOSDIO1CMDTN => SDIO1_CMD_T_n,
EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0),
EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0),
EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0),
EMIOSDIO1LED => SDIO1_LED,
EMIOSDIO1WP => SDIO1_WP,
EMIOSPI0MI => SPI0_MISO_I,
EMIOSPI0MO => SPI0_MOSI_O,
EMIOSPI0MOTN => SPI0_MOSI_T_n,
EMIOSPI0SCLKI => SPI0_SCLK_I,
EMIOSPI0SCLKO => SPI0_SCLK_O,
EMIOSPI0SCLKTN => SPI0_SCLK_T_n,
EMIOSPI0SI => SPI0_MOSI_I,
EMIOSPI0SO => SPI0_MISO_O,
EMIOSPI0SSIN => SPI0_SS_I,
EMIOSPI0SSNTN => SPI0_SS_T_n,
EMIOSPI0SSON(2) => SPI0_SS2_O,
EMIOSPI0SSON(1) => SPI0_SS1_O,
EMIOSPI0SSON(0) => SPI0_SS_O,
EMIOSPI0STN => SPI0_MISO_T_n,
EMIOSPI1MI => SPI1_MISO_I,
EMIOSPI1MO => SPI1_MOSI_O,
EMIOSPI1MOTN => SPI1_MOSI_T_n,
EMIOSPI1SCLKI => SPI1_SCLK_I,
EMIOSPI1SCLKO => SPI1_SCLK_O,
EMIOSPI1SCLKTN => SPI1_SCLK_T_n,
EMIOSPI1SI => SPI1_MOSI_I,
EMIOSPI1SO => SPI1_MISO_O,
EMIOSPI1SSIN => SPI1_SS_I,
EMIOSPI1SSNTN => SPI1_SS_T_n,
EMIOSPI1SSON(2) => SPI1_SS2_O,
EMIOSPI1SSON(1) => SPI1_SS1_O,
EMIOSPI1SSON(0) => SPI1_SS_O,
EMIOSPI1STN => SPI1_MISO_T_n,
EMIOSRAMINTIN => SRAM_INTIN,
EMIOTRACECLK => TRACE_CLK,
EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED,
EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0),
EMIOTTC0CLKI(2) => TTC0_CLK2_IN,
EMIOTTC0CLKI(1) => TTC0_CLK1_IN,
EMIOTTC0CLKI(0) => TTC0_CLK0_IN,
EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT,
EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT,
EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT,
EMIOTTC1CLKI(2) => TTC1_CLK2_IN,
EMIOTTC1CLKI(1) => TTC1_CLK1_IN,
EMIOTTC1CLKI(0) => TTC1_CLK0_IN,
EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT,
EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT,
EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT,
EMIOUART0CTSN => UART0_CTSN,
EMIOUART0DCDN => UART0_DCDN,
EMIOUART0DSRN => UART0_DSRN,
EMIOUART0DTRN => UART0_DTRN,
EMIOUART0RIN => UART0_RIN,
EMIOUART0RTSN => UART0_RTSN,
EMIOUART0RX => UART0_RX,
EMIOUART0TX => UART0_TX,
EMIOUART1CTSN => UART1_CTSN,
EMIOUART1DCDN => UART1_DCDN,
EMIOUART1DSRN => UART1_DSRN,
EMIOUART1DTRN => UART1_DTRN,
EMIOUART1RIN => UART1_RIN,
EMIOUART1RTSN => UART1_RTSN,
EMIOUART1RX => UART1_RX,
EMIOUART1TX => UART1_TX,
EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT,
EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT,
EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0),
EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT,
EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT,
EMIOWDTCLKI => WDT_CLK_IN,
EMIOWDTRSTO => WDT_RST_OUT,
EVENTEVENTI => EVENT_EVENTI,
EVENTEVENTO => EVENT_EVENTO,
EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0),
EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0),
FCLKCLK(3) => FCLK_CLK3,
FCLKCLK(2) => FCLK_CLK2,
FCLKCLK(1) => FCLK_CLK1,
FCLKCLK(0) => FCLK_CLK_unbuffered(0),
FCLKCLKTRIGN(3 downto 0) => B"0000",
FCLKRESETN(3) => FCLK_RESET3_N,
FCLKRESETN(2) => FCLK_RESET2_N,
FCLKRESETN(1) => FCLK_RESET1_N,
FCLKRESETN(0) => FCLK_RESET0_N,
FPGAIDLEN => FPGA_IDLE_N,
FTMDTRACEINATID(3 downto 0) => B"0000",
FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK,
FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000",
FTMDTRACEINVALID => '0',
FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0),
FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3,
FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2,
FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1,
FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0,
FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3,
FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2,
FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1,
FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0,
FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0),
FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3,
FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2,
FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1,
FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0,
FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3,
FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2,
FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1,
FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0,
IRQF2P(19) => Core1_nFIQ,
IRQF2P(18) => Core0_nFIQ,
IRQF2P(17) => Core1_nIRQ,
IRQF2P(16) => Core0_nIRQ,
IRQF2P(15 downto 2) => B"00000000000000",
IRQF2P(1 downto 0) => IRQ_F2P(1 downto 0),
IRQP2F(28) => IRQ_P2F_DMAC_ABORT,
IRQP2F(27) => IRQ_P2F_DMAC7,
IRQP2F(26) => IRQ_P2F_DMAC6,
IRQP2F(25) => IRQ_P2F_DMAC5,
IRQP2F(24) => IRQ_P2F_DMAC4,
IRQP2F(23) => IRQ_P2F_DMAC3,
IRQP2F(22) => IRQ_P2F_DMAC2,
IRQP2F(21) => IRQ_P2F_DMAC1,
IRQP2F(20) => IRQ_P2F_DMAC0,
IRQP2F(19) => IRQ_P2F_SMC,
IRQP2F(18) => IRQ_P2F_QSPI,
IRQP2F(17) => IRQ_P2F_CTI,
IRQP2F(16) => IRQ_P2F_GPIO,
IRQP2F(15) => IRQ_P2F_USB0,
IRQP2F(14) => IRQ_P2F_ENET0,
IRQP2F(13) => IRQ_P2F_ENET_WAKE0,
IRQP2F(12) => IRQ_P2F_SDIO0,
IRQP2F(11) => IRQ_P2F_I2C0,
IRQP2F(10) => IRQ_P2F_SPI0,
IRQP2F(9) => IRQ_P2F_UART0,
IRQP2F(8) => IRQ_P2F_CAN0,
IRQP2F(7) => IRQ_P2F_USB1,
IRQP2F(6) => IRQ_P2F_ENET1,
IRQP2F(5) => IRQ_P2F_ENET_WAKE1,
IRQP2F(4) => IRQ_P2F_SDIO1,
IRQP2F(3) => IRQ_P2F_I2C1,
IRQP2F(2) => IRQ_P2F_SPI1,
IRQP2F(1) => IRQ_P2F_UART1,
IRQP2F(0) => IRQ_P2F_CAN1,
MAXIGP0ACLK => M_AXI_GP0_ACLK,
MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
MAXIGP0ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
MAXIGP0ARESETN => M_AXI_GP0_ARESETN,
MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
MAXIGP0ARREADY => M_AXI_GP0_ARREADY,
MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0),
MAXIGP0ARVALID => M_AXI_GP0_ARVALID,
MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
MAXIGP0AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
MAXIGP0AWREADY => M_AXI_GP0_AWREADY,
MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0),
MAXIGP0AWVALID => M_AXI_GP0_AWVALID,
MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
MAXIGP0BREADY => M_AXI_GP0_BREADY,
MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
MAXIGP0BVALID => M_AXI_GP0_BVALID,
MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
MAXIGP0RLAST => M_AXI_GP0_RLAST,
MAXIGP0RREADY => M_AXI_GP0_RREADY,
MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
MAXIGP0RVALID => M_AXI_GP0_RVALID,
MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
MAXIGP0WLAST => M_AXI_GP0_WLAST,
MAXIGP0WREADY => M_AXI_GP0_WREADY,
MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
MAXIGP0WVALID => M_AXI_GP0_WVALID,
MAXIGP1ACLK => M_AXI_GP1_ACLK,
MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0),
MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0),
MAXIGP1ARCACHE(3 downto 0) => M_AXI_GP1_ARCACHE(3 downto 0),
MAXIGP1ARESETN => M_AXI_GP1_ARESETN,
MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0),
MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0),
MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0),
MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0),
MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0),
MAXIGP1ARREADY => M_AXI_GP1_ARREADY,
MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0),
MAXIGP1ARVALID => M_AXI_GP1_ARVALID,
MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0),
MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0),
MAXIGP1AWCACHE(3 downto 0) => M_AXI_GP1_AWCACHE(3 downto 0),
MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0),
MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0),
MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0),
MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0),
MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0),
MAXIGP1AWREADY => M_AXI_GP1_AWREADY,
MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0),
MAXIGP1AWVALID => M_AXI_GP1_AWVALID,
MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0),
MAXIGP1BREADY => M_AXI_GP1_BREADY,
MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0),
MAXIGP1BVALID => M_AXI_GP1_BVALID,
MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0),
MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0),
MAXIGP1RLAST => M_AXI_GP1_RLAST,
MAXIGP1RREADY => M_AXI_GP1_RREADY,
MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0),
MAXIGP1RVALID => M_AXI_GP1_RVALID,
MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0),
MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0),
MAXIGP1WLAST => M_AXI_GP1_WLAST,
MAXIGP1WREADY => M_AXI_GP1_WREADY,
MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0),
MAXIGP1WVALID => M_AXI_GP1_WVALID,
MIO(53 downto 0) => buffered_MIO(53 downto 0),
PSCLK => buffered_PS_CLK,
PSPORB => buffered_PS_PORB,
PSSRSTB => buffered_PS_SRSTB,
SAXIACPACLK => S_AXI_ACP_ACLK,
SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0),
SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0),
SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0),
SAXIACPARESETN => S_AXI_ACP_ARESETN,
SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0),
SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0),
SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0),
SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0),
SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0),
SAXIACPARREADY => S_AXI_ACP_ARREADY,
SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0),
SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0),
SAXIACPARVALID => S_AXI_ACP_ARVALID,
SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0),
SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0),
SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0),
SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0),
SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0),
SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0),
SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0),
SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0),
SAXIACPAWREADY => S_AXI_ACP_AWREADY,
SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0),
SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0),
SAXIACPAWVALID => S_AXI_ACP_AWVALID,
SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0),
SAXIACPBREADY => S_AXI_ACP_BREADY,
SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0),
SAXIACPBVALID => S_AXI_ACP_BVALID,
SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0),
SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0),
SAXIACPRLAST => S_AXI_ACP_RLAST,
SAXIACPRREADY => S_AXI_ACP_RREADY,
SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0),
SAXIACPRVALID => S_AXI_ACP_RVALID,
SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0),
SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0),
SAXIACPWLAST => S_AXI_ACP_WLAST,
SAXIACPWREADY => S_AXI_ACP_WREADY,
SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0),
SAXIACPWVALID => S_AXI_ACP_WVALID,
SAXIGP0ACLK => S_AXI_GP0_ACLK,
SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0),
SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0),
SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0),
SAXIGP0ARESETN => S_AXI_GP0_ARESETN,
SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0),
SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0),
SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0),
SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0),
SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0),
SAXIGP0ARREADY => S_AXI_GP0_ARREADY,
SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0),
SAXIGP0ARVALID => S_AXI_GP0_ARVALID,
SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0),
SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0),
SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0),
SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0),
SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0),
SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0),
SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0),
SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0),
SAXIGP0AWREADY => S_AXI_GP0_AWREADY,
SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0),
SAXIGP0AWVALID => S_AXI_GP0_AWVALID,
SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0),
SAXIGP0BREADY => S_AXI_GP0_BREADY,
SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0),
SAXIGP0BVALID => S_AXI_GP0_BVALID,
SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0),
SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0),
SAXIGP0RLAST => S_AXI_GP0_RLAST,
SAXIGP0RREADY => S_AXI_GP0_RREADY,
SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0),
SAXIGP0RVALID => S_AXI_GP0_RVALID,
SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0),
SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0),
SAXIGP0WLAST => S_AXI_GP0_WLAST,
SAXIGP0WREADY => S_AXI_GP0_WREADY,
SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0),
SAXIGP0WVALID => S_AXI_GP0_WVALID,
SAXIGP1ACLK => S_AXI_GP1_ACLK,
SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0),
SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0),
SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0),
SAXIGP1ARESETN => S_AXI_GP1_ARESETN,
SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0),
SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0),
SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0),
SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0),
SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0),
SAXIGP1ARREADY => S_AXI_GP1_ARREADY,
SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0),
SAXIGP1ARVALID => S_AXI_GP1_ARVALID,
SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0),
SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0),
SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0),
SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0),
SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0),
SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0),
SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0),
SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0),
SAXIGP1AWREADY => S_AXI_GP1_AWREADY,
SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0),
SAXIGP1AWVALID => S_AXI_GP1_AWVALID,
SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0),
SAXIGP1BREADY => S_AXI_GP1_BREADY,
SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0),
SAXIGP1BVALID => S_AXI_GP1_BVALID,
SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0),
SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0),
SAXIGP1RLAST => S_AXI_GP1_RLAST,
SAXIGP1RREADY => S_AXI_GP1_RREADY,
SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0),
SAXIGP1RVALID => S_AXI_GP1_RVALID,
SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0),
SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0),
SAXIGP1WLAST => S_AXI_GP1_WLAST,
SAXIGP1WREADY => S_AXI_GP1_WREADY,
SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0),
SAXIGP1WVALID => S_AXI_GP1_WVALID,
SAXIHP0ACLK => S_AXI_HP0_ACLK,
SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
SAXIHP0ARESETN => S_AXI_HP0_ARESETN,
SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
SAXIHP0ARREADY => S_AXI_HP0_ARREADY,
SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0),
SAXIHP0ARVALID => S_AXI_HP0_ARVALID,
SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
SAXIHP0AWREADY => S_AXI_HP0_AWREADY,
SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0),
SAXIHP0AWVALID => S_AXI_HP0_AWVALID,
SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
SAXIHP0BREADY => S_AXI_HP0_BREADY,
SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
SAXIHP0BVALID => S_AXI_HP0_BVALID,
SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0),
SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN,
SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
SAXIHP0RLAST => S_AXI_HP0_RLAST,
SAXIHP0RREADY => S_AXI_HP0_RREADY,
SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
SAXIHP0RVALID => S_AXI_HP0_RVALID,
SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0),
SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
SAXIHP0WLAST => S_AXI_HP0_WLAST,
SAXIHP0WREADY => S_AXI_HP0_WREADY,
SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN,
SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0),
SAXIHP0WVALID => S_AXI_HP0_WVALID,
SAXIHP1ACLK => S_AXI_HP1_ACLK,
SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0),
SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0),
SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0),
SAXIHP1ARESETN => S_AXI_HP1_ARESETN,
SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0),
SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0),
SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0),
SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0),
SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0),
SAXIHP1ARREADY => S_AXI_HP1_ARREADY,
SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0),
SAXIHP1ARVALID => S_AXI_HP1_ARVALID,
SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0),
SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0),
SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0),
SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0),
SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0),
SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0),
SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0),
SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0),
SAXIHP1AWREADY => S_AXI_HP1_AWREADY,
SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0),
SAXIHP1AWVALID => S_AXI_HP1_AWVALID,
SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0),
SAXIHP1BREADY => S_AXI_HP1_BREADY,
SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0),
SAXIHP1BVALID => S_AXI_HP1_BVALID,
SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0),
SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0),
SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0),
SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN,
SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0),
SAXIHP1RLAST => S_AXI_HP1_RLAST,
SAXIHP1RREADY => S_AXI_HP1_RREADY,
SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0),
SAXIHP1RVALID => S_AXI_HP1_RVALID,
SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0),
SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0),
SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0),
SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0),
SAXIHP1WLAST => S_AXI_HP1_WLAST,
SAXIHP1WREADY => S_AXI_HP1_WREADY,
SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN,
SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0),
SAXIHP1WVALID => S_AXI_HP1_WVALID,
SAXIHP2ACLK => S_AXI_HP2_ACLK,
SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0),
SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0),
SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0),
SAXIHP2ARESETN => S_AXI_HP2_ARESETN,
SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0),
SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0),
SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0),
SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0),
SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0),
SAXIHP2ARREADY => S_AXI_HP2_ARREADY,
SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0),
SAXIHP2ARVALID => S_AXI_HP2_ARVALID,
SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0),
SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0),
SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0),
SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0),
SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0),
SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0),
SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0),
SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0),
SAXIHP2AWREADY => S_AXI_HP2_AWREADY,
SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0),
SAXIHP2AWVALID => S_AXI_HP2_AWVALID,
SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0),
SAXIHP2BREADY => S_AXI_HP2_BREADY,
SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0),
SAXIHP2BVALID => S_AXI_HP2_BVALID,
SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0),
SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0),
SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0),
SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN,
SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0),
SAXIHP2RLAST => S_AXI_HP2_RLAST,
SAXIHP2RREADY => S_AXI_HP2_RREADY,
SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0),
SAXIHP2RVALID => S_AXI_HP2_RVALID,
SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0),
SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0),
SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0),
SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0),
SAXIHP2WLAST => S_AXI_HP2_WLAST,
SAXIHP2WREADY => S_AXI_HP2_WREADY,
SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN,
SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0),
SAXIHP2WVALID => S_AXI_HP2_WVALID,
SAXIHP3ACLK => S_AXI_HP3_ACLK,
SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0),
SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0),
SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0),
SAXIHP3ARESETN => S_AXI_HP3_ARESETN,
SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0),
SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0),
SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0),
SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0),
SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0),
SAXIHP3ARREADY => S_AXI_HP3_ARREADY,
SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0),
SAXIHP3ARVALID => S_AXI_HP3_ARVALID,
SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0),
SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0),
SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0),
SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0),
SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0),
SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0),
SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0),
SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0),
SAXIHP3AWREADY => S_AXI_HP3_AWREADY,
SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0),
SAXIHP3AWVALID => S_AXI_HP3_AWVALID,
SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0),
SAXIHP3BREADY => S_AXI_HP3_BREADY,
SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0),
SAXIHP3BVALID => S_AXI_HP3_BVALID,
SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0),
SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0),
SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0),
SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN,
SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0),
SAXIHP3RLAST => S_AXI_HP3_RLAST,
SAXIHP3RREADY => S_AXI_HP3_RREADY,
SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0),
SAXIHP3RVALID => S_AXI_HP3_RVALID,
SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0),
SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0),
SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0),
SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0),
SAXIHP3WLAST => S_AXI_HP3_WLAST,
SAXIHP3WREADY => S_AXI_HP3_WREADY,
SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN,
SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0),
SAXIHP3WVALID => S_AXI_HP3_WVALID
);
PS_CLK_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_CLK,
PAD => PS_CLK
);
PS_PORB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_PORB,
PAD => PS_PORB
);
PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_SRSTB,
PAD => PS_SRSTB
);
SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_CMD_T_n,
O => SDIO0_CMD_T
);
\SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(0),
O => SDIO0_DATA_T(0)
);
\SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(1),
O => SDIO0_DATA_T(1)
);
\SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(2),
O => SDIO0_DATA_T(2)
);
\SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(3),
O => SDIO0_DATA_T(3)
);
SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_CMD_T_n,
O => SDIO1_CMD_T
);
\SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(0),
O => SDIO1_DATA_T(0)
);
\SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(1),
O => SDIO1_DATA_T(1)
);
\SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(2),
O => SDIO1_DATA_T(2)
);
\SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(3),
O => SDIO1_DATA_T(3)
);
SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MISO_T_n,
O => SPI0_MISO_T
);
SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MOSI_T_n,
O => SPI0_MOSI_T
);
SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SCLK_T_n,
O => SPI0_SCLK_T
);
SPI0_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SS_T_n,
O => SPI0_SS_T
);
SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MISO_T_n,
O => SPI1_MISO_T
);
SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MOSI_T_n,
O => SPI1_MOSI_T
);
SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SCLK_T_n,
O => SPI1_SCLK_T
);
SPI1_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SS_T_n,
O => SPI1_SS_T
);
\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(0),
O => FCLK_CLK0
);
\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(0),
PAD => MIO(0)
);
\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(10),
PAD => MIO(10)
);
\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(11),
PAD => MIO(11)
);
\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(12),
PAD => MIO(12)
);
\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(13),
PAD => MIO(13)
);
\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(14),
PAD => MIO(14)
);
\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(15),
PAD => MIO(15)
);
\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(16),
PAD => MIO(16)
);
\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(17),
PAD => MIO(17)
);
\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(18),
PAD => MIO(18)
);
\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(19),
PAD => MIO(19)
);
\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(1),
PAD => MIO(1)
);
\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(20),
PAD => MIO(20)
);
\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(21),
PAD => MIO(21)
);
\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(22),
PAD => MIO(22)
);
\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(23),
PAD => MIO(23)
);
\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(24),
PAD => MIO(24)
);
\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(25),
PAD => MIO(25)
);
\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(26),
PAD => MIO(26)
);
\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(27),
PAD => MIO(27)
);
\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(28),
PAD => MIO(28)
);
\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(29),
PAD => MIO(29)
);
\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(2),
PAD => MIO(2)
);
\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(30),
PAD => MIO(30)
);
\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(31),
PAD => MIO(31)
);
\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(32),
PAD => MIO(32)
);
\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(33),
PAD => MIO(33)
);
\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(34),
PAD => MIO(34)
);
\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(35),
PAD => MIO(35)
);
\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(36),
PAD => MIO(36)
);
\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(37),
PAD => MIO(37)
);
\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(38),
PAD => MIO(38)
);
\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(39),
PAD => MIO(39)
);
\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(3),
PAD => MIO(3)
);
\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(40),
PAD => MIO(40)
);
\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(41),
PAD => MIO(41)
);
\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(42),
PAD => MIO(42)
);
\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(43),
PAD => MIO(43)
);
\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(44),
PAD => MIO(44)
);
\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(45),
PAD => MIO(45)
);
\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(46),
PAD => MIO(46)
);
\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(47),
PAD => MIO(47)
);
\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(48),
PAD => MIO(48)
);
\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(49),
PAD => MIO(49)
);
\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(4),
PAD => MIO(4)
);
\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(50),
PAD => MIO(50)
);
\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(51),
PAD => MIO(51)
);
\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(52),
PAD => MIO(52)
);
\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(53),
PAD => MIO(53)
);
\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(5),
PAD => MIO(5)
);
\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(6),
PAD => MIO(6)
);
\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(7),
PAD => MIO(7)
);
\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(8),
PAD => MIO(8)
);
\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(9),
PAD => MIO(9)
);
\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(0),
PAD => DDR_BankAddr(0)
);
\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(1),
PAD => DDR_BankAddr(1)
);
\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(2),
PAD => DDR_BankAddr(2)
);
\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(0),
PAD => DDR_Addr(0)
);
\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(10),
PAD => DDR_Addr(10)
);
\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(11),
PAD => DDR_Addr(11)
);
\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(12),
PAD => DDR_Addr(12)
);
\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(13),
PAD => DDR_Addr(13)
);
\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(14),
PAD => DDR_Addr(14)
);
\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(1),
PAD => DDR_Addr(1)
);
\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(2),
PAD => DDR_Addr(2)
);
\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(3),
PAD => DDR_Addr(3)
);
\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(4),
PAD => DDR_Addr(4)
);
\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(5),
PAD => DDR_Addr(5)
);
\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(6),
PAD => DDR_Addr(6)
);
\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(7),
PAD => DDR_Addr(7)
);
\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(8),
PAD => DDR_Addr(8)
);
\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(9),
PAD => DDR_Addr(9)
);
\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(0),
PAD => DDR_DM(0)
);
\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(1),
PAD => DDR_DM(1)
);
\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(2),
PAD => DDR_DM(2)
);
\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(3),
PAD => DDR_DM(3)
);
\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(0),
PAD => DDR_DQ(0)
);
\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(10),
PAD => DDR_DQ(10)
);
\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(11),
PAD => DDR_DQ(11)
);
\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(12),
PAD => DDR_DQ(12)
);
\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(13),
PAD => DDR_DQ(13)
);
\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(14),
PAD => DDR_DQ(14)
);
\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(15),
PAD => DDR_DQ(15)
);
\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(16),
PAD => DDR_DQ(16)
);
\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(17),
PAD => DDR_DQ(17)
);
\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(18),
PAD => DDR_DQ(18)
);
\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(19),
PAD => DDR_DQ(19)
);
\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(1),
PAD => DDR_DQ(1)
);
\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(20),
PAD => DDR_DQ(20)
);
\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(21),
PAD => DDR_DQ(21)
);
\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(22),
PAD => DDR_DQ(22)
);
\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(23),
PAD => DDR_DQ(23)
);
\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(24),
PAD => DDR_DQ(24)
);
\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(25),
PAD => DDR_DQ(25)
);
\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(26),
PAD => DDR_DQ(26)
);
\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(27),
PAD => DDR_DQ(27)
);
\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(28),
PAD => DDR_DQ(28)
);
\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(29),
PAD => DDR_DQ(29)
);
\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(2),
PAD => DDR_DQ(2)
);
\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(30),
PAD => DDR_DQ(30)
);
\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(31),
PAD => DDR_DQ(31)
);
\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(3),
PAD => DDR_DQ(3)
);
\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(4),
PAD => DDR_DQ(4)
);
\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(5),
PAD => DDR_DQ(5)
);
\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(6),
PAD => DDR_DQ(6)
);
\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(7),
PAD => DDR_DQ(7)
);
\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(8),
PAD => DDR_DQ(8)
);
\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(9),
PAD => DDR_DQ(9)
);
\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(0),
PAD => DDR_DQS_n(0)
);
\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(1),
PAD => DDR_DQS_n(1)
);
\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(2),
PAD => DDR_DQS_n(2)
);
\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(3),
PAD => DDR_DQS_n(3)
);
\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(0),
PAD => DDR_DQS(0)
);
\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(1),
PAD => DDR_DQS(1)
);
\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(2),
PAD => DDR_DQS(2)
);
\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(3),
PAD => DDR_DQS(3)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[0]\
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(1)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(1)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(0)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(1)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(0)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(0)
);
i_16: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(1)
);
i_17: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(0)
);
i_18: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(1)
);
i_19: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(0)
);
i_20: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(1)
);
i_21: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(0)
);
i_22: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(1)
);
i_23: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(0)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[7]\
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[6]\
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[5]\
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[4]\
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[3]\
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[2]\
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_processing_system7_0_0 is
port (
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_processing_system7_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_processing_system7_0_0 : entity is "system_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of system_processing_system7_0_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of system_processing_system7_0_0 : entity is "processing_system7_v5_5_processing_system7,Vivado 2016.4";
end system_processing_system7_0_0;
architecture STRUCTURE of system_processing_system7_0_0 is
signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of inst : label is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of inst : label is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of inst : label is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of inst : label is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of inst : label is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of inst : label is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of inst : label is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of inst : label is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of inst : label is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of inst : label is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 0;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 0;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of inst : label is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of inst : label is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 2;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of inst : label is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of inst : label is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of inst : label is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of inst : label is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of inst : label is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of inst : label is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of inst : label is 1;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of inst : label is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of inst : label is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of inst : label is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of inst : label is "system_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={S_AXI_HP0} dataWidth={64} clockFreq={100} usageRate={0.5} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
begin
inst: entity work.system_processing_system7_0_0_processing_system7_v5_5_processing_system7
port map (
CAN0_PHY_RX => '0',
CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED,
CAN1_PHY_RX => '0',
CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED,
Core0_nFIQ => '0',
Core0_nIRQ => '0',
Core1_nFIQ => '0',
Core1_nIRQ => '0',
DDR_ARB(3 downto 0) => B"0000",
DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0),
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM(3 downto 0) => DDR_DM(3 downto 0),
DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0),
DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0),
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_WEB => DDR_WEB,
DMA0_ACLK => '0',
DMA0_DAREADY => '0',
DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0),
DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED,
DMA0_DRLAST => '0',
DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED,
DMA0_DRTYPE(1 downto 0) => B"00",
DMA0_DRVALID => '0',
DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED,
DMA1_ACLK => '0',
DMA1_DAREADY => '0',
DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0),
DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED,
DMA1_DRLAST => '0',
DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED,
DMA1_DRTYPE(1 downto 0) => B"00",
DMA1_DRVALID => '0',
DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED,
DMA2_ACLK => '0',
DMA2_DAREADY => '0',
DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0),
DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED,
DMA2_DRLAST => '0',
DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED,
DMA2_DRTYPE(1 downto 0) => B"00",
DMA2_DRVALID => '0',
DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED,
DMA3_ACLK => '0',
DMA3_DAREADY => '0',
DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0),
DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED,
DMA3_DRLAST => '0',
DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED,
DMA3_DRTYPE(1 downto 0) => B"00",
DMA3_DRVALID => '0',
DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED,
ENET0_EXT_INTIN => '0',
ENET0_GMII_COL => '0',
ENET0_GMII_CRS => '0',
ENET0_GMII_RXD(7 downto 0) => B"00000000",
ENET0_GMII_RX_CLK => '0',
ENET0_GMII_RX_DV => '0',
ENET0_GMII_RX_ER => '0',
ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0),
ENET0_GMII_TX_CLK => '0',
ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED,
ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED,
ENET0_MDIO_I => '0',
ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED,
ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED,
ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED,
ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED,
ENET1_EXT_INTIN => '0',
ENET1_GMII_COL => '0',
ENET1_GMII_CRS => '0',
ENET1_GMII_RXD(7 downto 0) => B"00000000",
ENET1_GMII_RX_CLK => '0',
ENET1_GMII_RX_DV => '0',
ENET1_GMII_RX_ER => '0',
ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0),
ENET1_GMII_TX_CLK => '0',
ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED,
ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED,
ENET1_MDIO_I => '0',
ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED,
ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED,
ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED,
ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED,
ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED,
EVENT_EVENTI => '0',
EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED,
EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0),
EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0),
FCLK_CLK0 => FCLK_CLK0,
FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED,
FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED,
FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED,
FCLK_CLKTRIG0_N => '0',
FCLK_CLKTRIG1_N => '0',
FCLK_CLKTRIG2_N => '0',
FCLK_CLKTRIG3_N => '0',
FCLK_RESET0_N => FCLK_RESET0_N,
FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED,
FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED,
FPGA_IDLE_N => '0',
FTMD_TRACEIN_ATID(3 downto 0) => B"0000",
FTMD_TRACEIN_CLK => '0',
FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000",
FTMD_TRACEIN_VALID => '0',
FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000",
FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED,
FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED,
FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED,
FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED,
FTMT_F2P_TRIG_0 => '0',
FTMT_F2P_TRIG_1 => '0',
FTMT_F2P_TRIG_2 => '0',
FTMT_F2P_TRIG_3 => '0',
FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0),
FTMT_P2F_TRIGACK_0 => '0',
FTMT_P2F_TRIGACK_1 => '0',
FTMT_P2F_TRIGACK_2 => '0',
FTMT_P2F_TRIGACK_3 => '0',
FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED,
FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED,
FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED,
FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED,
GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0),
GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0),
I2C0_SCL_I => '0',
I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED,
I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED,
I2C0_SDA_I => '0',
I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED,
I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED,
I2C1_SCL_I => '0',
I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED,
I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED,
I2C1_SDA_I => '0',
I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED,
I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED,
IRQ_F2P(1 downto 0) => IRQ_F2P(1 downto 0),
IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED,
IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED,
IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED,
IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED,
IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED,
IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED,
IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED,
IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED,
IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED,
IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED,
IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED,
IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED,
IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED,
IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED,
IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED,
IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED,
IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED,
IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED,
IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED,
IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED,
IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED,
IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED,
IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED,
IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED,
IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED,
IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED,
IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED,
IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED,
IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED,
MIO(53 downto 0) => MIO(53 downto 0),
M_AXI_GP0_ACLK => M_AXI_GP0_ACLK,
M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED,
M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => M_AXI_GP0_WVALID,
M_AXI_GP1_ACLK => '0',
M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED,
M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARREADY => '0',
M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED,
M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWREADY => '0',
M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED,
M_AXI_GP1_BID(11 downto 0) => B"000000000000",
M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED,
M_AXI_GP1_BRESP(1 downto 0) => B"00",
M_AXI_GP1_BVALID => '0',
M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP1_RID(11 downto 0) => B"000000000000",
M_AXI_GP1_RLAST => '0',
M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED,
M_AXI_GP1_RRESP(1 downto 0) => B"00",
M_AXI_GP1_RVALID => '0',
M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0),
M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED,
M_AXI_GP1_WREADY => '0',
M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED,
PJTAG_TCK => '0',
PJTAG_TDI => '0',
PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED,
PJTAG_TMS => '0',
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED,
SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO0_CDN => '0',
SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED,
SDIO0_CLK_FB => '0',
SDIO0_CMD_I => '0',
SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED,
SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED,
SDIO0_DATA_I(3 downto 0) => B"0000",
SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0),
SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0),
SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED,
SDIO0_WP => '0',
SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED,
SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO1_CDN => '0',
SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED,
SDIO1_CLK_FB => '0',
SDIO1_CMD_I => '0',
SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED,
SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED,
SDIO1_DATA_I(3 downto 0) => B"0000",
SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0),
SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0),
SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED,
SDIO1_WP => '0',
SPI0_MISO_I => '0',
SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED,
SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED,
SPI0_MOSI_I => '0',
SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED,
SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED,
SPI0_SCLK_I => '0',
SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED,
SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED,
SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED,
SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED,
SPI0_SS_I => '0',
SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED,
SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED,
SPI1_MISO_I => '0',
SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED,
SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED,
SPI1_MOSI_I => '0',
SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED,
SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED,
SPI1_SCLK_I => '0',
SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED,
SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED,
SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED,
SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED,
SPI1_SS_I => '0',
SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED,
SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED,
SRAM_INTIN => '0',
S_AXI_ACP_ACLK => '0',
S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_ARBURST(1 downto 0) => B"00",
S_AXI_ACP_ARCACHE(3 downto 0) => B"0000",
S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED,
S_AXI_ACP_ARID(2 downto 0) => B"000",
S_AXI_ACP_ARLEN(3 downto 0) => B"0000",
S_AXI_ACP_ARLOCK(1 downto 0) => B"00",
S_AXI_ACP_ARPROT(2 downto 0) => B"000",
S_AXI_ACP_ARQOS(3 downto 0) => B"0000",
S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED,
S_AXI_ACP_ARSIZE(2 downto 0) => B"000",
S_AXI_ACP_ARUSER(4 downto 0) => B"00000",
S_AXI_ACP_ARVALID => '0',
S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_AWBURST(1 downto 0) => B"00",
S_AXI_ACP_AWCACHE(3 downto 0) => B"0000",
S_AXI_ACP_AWID(2 downto 0) => B"000",
S_AXI_ACP_AWLEN(3 downto 0) => B"0000",
S_AXI_ACP_AWLOCK(1 downto 0) => B"00",
S_AXI_ACP_AWPROT(2 downto 0) => B"000",
S_AXI_ACP_AWQOS(3 downto 0) => B"0000",
S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED,
S_AXI_ACP_AWSIZE(2 downto 0) => B"000",
S_AXI_ACP_AWUSER(4 downto 0) => B"00000",
S_AXI_ACP_AWVALID => '0',
S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0),
S_AXI_ACP_BREADY => '0',
S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED,
S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0),
S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0),
S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED,
S_AXI_ACP_RREADY => '0',
S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED,
S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_ACP_WID(2 downto 0) => B"000",
S_AXI_ACP_WLAST => '0',
S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED,
S_AXI_ACP_WSTRB(7 downto 0) => B"00000000",
S_AXI_ACP_WVALID => '0',
S_AXI_GP0_ACLK => '0',
S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_ARBURST(1 downto 0) => B"00",
S_AXI_GP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED,
S_AXI_GP0_ARID(5 downto 0) => B"000000",
S_AXI_GP0_ARLEN(3 downto 0) => B"0000",
S_AXI_GP0_ARLOCK(1 downto 0) => B"00",
S_AXI_GP0_ARPROT(2 downto 0) => B"000",
S_AXI_GP0_ARQOS(3 downto 0) => B"0000",
S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED,
S_AXI_GP0_ARSIZE(2 downto 0) => B"000",
S_AXI_GP0_ARVALID => '0',
S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_AWBURST(1 downto 0) => B"00",
S_AXI_GP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP0_AWID(5 downto 0) => B"000000",
S_AXI_GP0_AWLEN(3 downto 0) => B"0000",
S_AXI_GP0_AWLOCK(1 downto 0) => B"00",
S_AXI_GP0_AWPROT(2 downto 0) => B"000",
S_AXI_GP0_AWQOS(3 downto 0) => B"0000",
S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED,
S_AXI_GP0_AWSIZE(2 downto 0) => B"000",
S_AXI_GP0_AWVALID => '0',
S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0),
S_AXI_GP0_BREADY => '0',
S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED,
S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0),
S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED,
S_AXI_GP0_RREADY => '0',
S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED,
S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_WID(5 downto 0) => B"000000",
S_AXI_GP0_WLAST => '0',
S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED,
S_AXI_GP0_WSTRB(3 downto 0) => B"0000",
S_AXI_GP0_WVALID => '0',
S_AXI_GP1_ACLK => '0',
S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_ARBURST(1 downto 0) => B"00",
S_AXI_GP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED,
S_AXI_GP1_ARID(5 downto 0) => B"000000",
S_AXI_GP1_ARLEN(3 downto 0) => B"0000",
S_AXI_GP1_ARLOCK(1 downto 0) => B"00",
S_AXI_GP1_ARPROT(2 downto 0) => B"000",
S_AXI_GP1_ARQOS(3 downto 0) => B"0000",
S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED,
S_AXI_GP1_ARSIZE(2 downto 0) => B"000",
S_AXI_GP1_ARVALID => '0',
S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_AWBURST(1 downto 0) => B"00",
S_AXI_GP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP1_AWID(5 downto 0) => B"000000",
S_AXI_GP1_AWLEN(3 downto 0) => B"0000",
S_AXI_GP1_AWLOCK(1 downto 0) => B"00",
S_AXI_GP1_AWPROT(2 downto 0) => B"000",
S_AXI_GP1_AWQOS(3 downto 0) => B"0000",
S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED,
S_AXI_GP1_AWSIZE(2 downto 0) => B"000",
S_AXI_GP1_AWVALID => '0',
S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0),
S_AXI_GP1_BREADY => '0',
S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED,
S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0),
S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED,
S_AXI_GP1_RREADY => '0',
S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED,
S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_WID(5 downto 0) => B"000000",
S_AXI_GP1_WLAST => '0',
S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED,
S_AXI_GP1_WSTRB(3 downto 0) => B"0000",
S_AXI_GP1_WVALID => '0',
S_AXI_HP0_ACLK => S_AXI_HP0_ACLK,
S_AXI_HP0_ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
S_AXI_HP0_ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
S_AXI_HP0_ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED,
S_AXI_HP0_ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
S_AXI_HP0_ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
S_AXI_HP0_ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
S_AXI_HP0_ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
S_AXI_HP0_ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
S_AXI_HP0_ARREADY => S_AXI_HP0_ARREADY,
S_AXI_HP0_ARSIZE(2 downto 0) => S_AXI_HP0_ARSIZE(2 downto 0),
S_AXI_HP0_ARVALID => S_AXI_HP0_ARVALID,
S_AXI_HP0_AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
S_AXI_HP0_AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
S_AXI_HP0_AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
S_AXI_HP0_AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
S_AXI_HP0_AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
S_AXI_HP0_AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
S_AXI_HP0_AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
S_AXI_HP0_AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
S_AXI_HP0_AWREADY => S_AXI_HP0_AWREADY,
S_AXI_HP0_AWSIZE(2 downto 0) => S_AXI_HP0_AWSIZE(2 downto 0),
S_AXI_HP0_AWVALID => S_AXI_HP0_AWVALID,
S_AXI_HP0_BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
S_AXI_HP0_BREADY => S_AXI_HP0_BREADY,
S_AXI_HP0_BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
S_AXI_HP0_BVALID => S_AXI_HP0_BVALID,
S_AXI_HP0_RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
S_AXI_HP0_RLAST => S_AXI_HP0_RLAST,
S_AXI_HP0_RREADY => S_AXI_HP0_RREADY,
S_AXI_HP0_RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
S_AXI_HP0_RVALID => S_AXI_HP0_RVALID,
S_AXI_HP0_WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0),
S_AXI_HP0_WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
S_AXI_HP0_WLAST => S_AXI_HP0_WLAST,
S_AXI_HP0_WREADY => S_AXI_HP0_WREADY,
S_AXI_HP0_WRISSUECAP1_EN => S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0),
S_AXI_HP0_WVALID => S_AXI_HP0_WVALID,
S_AXI_HP1_ACLK => '0',
S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_ARBURST(1 downto 0) => B"00",
S_AXI_HP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED,
S_AXI_HP1_ARID(5 downto 0) => B"000000",
S_AXI_HP1_ARLEN(3 downto 0) => B"0000",
S_AXI_HP1_ARLOCK(1 downto 0) => B"00",
S_AXI_HP1_ARPROT(2 downto 0) => B"000",
S_AXI_HP1_ARQOS(3 downto 0) => B"0000",
S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED,
S_AXI_HP1_ARSIZE(2 downto 0) => B"000",
S_AXI_HP1_ARVALID => '0',
S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_AWBURST(1 downto 0) => B"00",
S_AXI_HP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP1_AWID(5 downto 0) => B"000000",
S_AXI_HP1_AWLEN(3 downto 0) => B"0000",
S_AXI_HP1_AWLOCK(1 downto 0) => B"00",
S_AXI_HP1_AWPROT(2 downto 0) => B"000",
S_AXI_HP1_AWQOS(3 downto 0) => B"0000",
S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED,
S_AXI_HP1_AWSIZE(2 downto 0) => B"000",
S_AXI_HP1_AWVALID => '0',
S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0),
S_AXI_HP1_BREADY => '0',
S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED,
S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP1_RDISSUECAP1_EN => '0',
S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0),
S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED,
S_AXI_HP1_RREADY => '0',
S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED,
S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP1_WID(5 downto 0) => B"000000",
S_AXI_HP1_WLAST => '0',
S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED,
S_AXI_HP1_WRISSUECAP1_EN => '0',
S_AXI_HP1_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP1_WVALID => '0',
S_AXI_HP2_ACLK => '0',
S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_ARBURST(1 downto 0) => B"00",
S_AXI_HP2_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED,
S_AXI_HP2_ARID(5 downto 0) => B"000000",
S_AXI_HP2_ARLEN(3 downto 0) => B"0000",
S_AXI_HP2_ARLOCK(1 downto 0) => B"00",
S_AXI_HP2_ARPROT(2 downto 0) => B"000",
S_AXI_HP2_ARQOS(3 downto 0) => B"0000",
S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED,
S_AXI_HP2_ARSIZE(2 downto 0) => B"000",
S_AXI_HP2_ARVALID => '0',
S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_AWBURST(1 downto 0) => B"00",
S_AXI_HP2_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP2_AWID(5 downto 0) => B"000000",
S_AXI_HP2_AWLEN(3 downto 0) => B"0000",
S_AXI_HP2_AWLOCK(1 downto 0) => B"00",
S_AXI_HP2_AWPROT(2 downto 0) => B"000",
S_AXI_HP2_AWQOS(3 downto 0) => B"0000",
S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED,
S_AXI_HP2_AWSIZE(2 downto 0) => B"000",
S_AXI_HP2_AWVALID => '0',
S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0),
S_AXI_HP2_BREADY => '0',
S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED,
S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP2_RDISSUECAP1_EN => '0',
S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0),
S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED,
S_AXI_HP2_RREADY => '0',
S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED,
S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP2_WID(5 downto 0) => B"000000",
S_AXI_HP2_WLAST => '0',
S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED,
S_AXI_HP2_WRISSUECAP1_EN => '0',
S_AXI_HP2_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP2_WVALID => '0',
S_AXI_HP3_ACLK => '0',
S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_ARBURST(1 downto 0) => B"00",
S_AXI_HP3_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED,
S_AXI_HP3_ARID(5 downto 0) => B"000000",
S_AXI_HP3_ARLEN(3 downto 0) => B"0000",
S_AXI_HP3_ARLOCK(1 downto 0) => B"00",
S_AXI_HP3_ARPROT(2 downto 0) => B"000",
S_AXI_HP3_ARQOS(3 downto 0) => B"0000",
S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED,
S_AXI_HP3_ARSIZE(2 downto 0) => B"000",
S_AXI_HP3_ARVALID => '0',
S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_AWBURST(1 downto 0) => B"00",
S_AXI_HP3_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP3_AWID(5 downto 0) => B"000000",
S_AXI_HP3_AWLEN(3 downto 0) => B"0000",
S_AXI_HP3_AWLOCK(1 downto 0) => B"00",
S_AXI_HP3_AWPROT(2 downto 0) => B"000",
S_AXI_HP3_AWQOS(3 downto 0) => B"0000",
S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED,
S_AXI_HP3_AWSIZE(2 downto 0) => B"000",
S_AXI_HP3_AWVALID => '0',
S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0),
S_AXI_HP3_BREADY => '0',
S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED,
S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP3_RDISSUECAP1_EN => '0',
S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0),
S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED,
S_AXI_HP3_RREADY => '0',
S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED,
S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP3_WID(5 downto 0) => B"000000",
S_AXI_HP3_WLAST => '0',
S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED,
S_AXI_HP3_WRISSUECAP1_EN => '0',
S_AXI_HP3_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP3_WVALID => '0',
TRACE_CLK => '0',
TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED,
TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED,
TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0),
TTC0_CLK0_IN => '0',
TTC0_CLK1_IN => '0',
TTC0_CLK2_IN => '0',
TTC0_WAVE0_OUT => TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT => TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT => TTC0_WAVE2_OUT,
TTC1_CLK0_IN => '0',
TTC1_CLK1_IN => '0',
TTC1_CLK2_IN => '0',
TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED,
TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED,
TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED,
UART0_CTSN => '0',
UART0_DCDN => '0',
UART0_DSRN => '0',
UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED,
UART0_RIN => '0',
UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED,
UART0_RX => '1',
UART0_TX => NLW_inst_UART0_TX_UNCONNECTED,
UART1_CTSN => '0',
UART1_DCDN => '0',
UART1_DSRN => '0',
UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED,
UART1_RIN => '0',
UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED,
UART1_RX => '1',
UART1_TX => NLW_inst_UART1_TX_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT,
USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT,
USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB1_VBUS_PWRFAULT => '0',
USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED,
WDT_CLK_IN => '0',
WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED
);
end STRUCTURE;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_util_vector_logic_0_0/synth/system_util_vector_logic_0_0.vhd
|
3
|
4126
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:util_vector_logic:2.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY util_vector_logic_v2_0;
USE util_vector_logic_v2_0.util_vector_logic;
ENTITY system_util_vector_logic_0_0 IS
PORT (
Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END system_util_vector_logic_0_0;
ARCHITECTURE system_util_vector_logic_0_0_arch OF system_util_vector_logic_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_util_vector_logic_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT util_vector_logic IS
GENERIC (
C_OPERATION : STRING;
C_SIZE : INTEGER
);
PORT (
Op1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Op2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
Res : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT util_vector_logic;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_util_vector_logic_0_0_arch: ARCHITECTURE IS "util_vector_logic,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_util_vector_logic_0_0_arch : ARCHITECTURE IS "system_util_vector_logic_0_0,util_vector_logic,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_util_vector_logic_0_0_arch: ARCHITECTURE IS "system_util_vector_logic_0_0,util_vector_logic,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=util_vector_logic,x_ipVersion=2.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_OPERATION=and,C_SIZE=1}";
BEGIN
U0 : util_vector_logic
GENERIC MAP (
C_OPERATION => "and",
C_SIZE => 1
)
PORT MAP (
Op1 => Op1,
Op2 => Op2,
Res => Res
);
END system_util_vector_logic_0_0_arch;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_vga_sync_ref_0_0/system_vga_sync_ref_0_0_sim_netlist.vhdl
|
3
|
70090
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:18:23 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_vga_sync_ref_0_0/system_vga_sync_ref_0_0_sim_netlist.vhdl
-- Design : system_vga_sync_ref_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_ref_0_0_vga_sync_ref is
port (
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
start : out STD_LOGIC;
active : out STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
vsync : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_sync_ref_0_0_vga_sync_ref : entity is "vga_sync_ref";
end system_vga_sync_ref_0_0_vga_sync_ref;
architecture STRUCTURE of system_vga_sync_ref_0_0_vga_sync_ref is
signal \^active\ : STD_LOGIC;
signal active_i_1_n_0 : STD_LOGIC;
signal active_i_2_n_0 : STD_LOGIC;
signal counter : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \counter[12]_i_3_n_0\ : STD_LOGIC;
signal \counter[12]_i_4_n_0\ : STD_LOGIC;
signal \counter[12]_i_5_n_0\ : STD_LOGIC;
signal \counter[12]_i_6_n_0\ : STD_LOGIC;
signal \counter[16]_i_3_n_0\ : STD_LOGIC;
signal \counter[16]_i_4_n_0\ : STD_LOGIC;
signal \counter[16]_i_5_n_0\ : STD_LOGIC;
signal \counter[16]_i_6_n_0\ : STD_LOGIC;
signal \counter[20]_i_3_n_0\ : STD_LOGIC;
signal \counter[20]_i_4_n_0\ : STD_LOGIC;
signal \counter[20]_i_5_n_0\ : STD_LOGIC;
signal \counter[20]_i_6_n_0\ : STD_LOGIC;
signal \counter[24]_i_3_n_0\ : STD_LOGIC;
signal \counter[24]_i_4_n_0\ : STD_LOGIC;
signal \counter[24]_i_5_n_0\ : STD_LOGIC;
signal \counter[24]_i_6_n_0\ : STD_LOGIC;
signal \counter[28]_i_3_n_0\ : STD_LOGIC;
signal \counter[28]_i_4_n_0\ : STD_LOGIC;
signal \counter[28]_i_5_n_0\ : STD_LOGIC;
signal \counter[28]_i_6_n_0\ : STD_LOGIC;
signal \counter[31]_i_10_n_0\ : STD_LOGIC;
signal \counter[31]_i_11_n_0\ : STD_LOGIC;
signal \counter[31]_i_12_n_0\ : STD_LOGIC;
signal \counter[31]_i_13_n_0\ : STD_LOGIC;
signal \counter[31]_i_14_n_0\ : STD_LOGIC;
signal \counter[31]_i_15_n_0\ : STD_LOGIC;
signal \counter[31]_i_16_n_0\ : STD_LOGIC;
signal \counter[31]_i_17_n_0\ : STD_LOGIC;
signal \counter[31]_i_18_n_0\ : STD_LOGIC;
signal \counter[31]_i_19_n_0\ : STD_LOGIC;
signal \counter[31]_i_1_n_0\ : STD_LOGIC;
signal \counter[31]_i_2_n_0\ : STD_LOGIC;
signal \counter[31]_i_4_n_0\ : STD_LOGIC;
signal \counter[31]_i_6_n_0\ : STD_LOGIC;
signal \counter[31]_i_7_n_0\ : STD_LOGIC;
signal \counter[31]_i_8_n_0\ : STD_LOGIC;
signal \counter[31]_i_9_n_0\ : STD_LOGIC;
signal \counter[4]_i_3_n_0\ : STD_LOGIC;
signal \counter[4]_i_4_n_0\ : STD_LOGIC;
signal \counter[4]_i_5_n_0\ : STD_LOGIC;
signal \counter[4]_i_6_n_0\ : STD_LOGIC;
signal \counter[8]_i_3_n_0\ : STD_LOGIC;
signal \counter[8]_i_4_n_0\ : STD_LOGIC;
signal \counter[8]_i_5_n_0\ : STD_LOGIC;
signal \counter[8]_i_6_n_0\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[12]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[16]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[20]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[24]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[28]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_2\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_3\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_5\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_6\ : STD_LOGIC;
signal \counter_reg[31]_i_5_n_7\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[4]_i_2_n_7\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_0\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_1\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_2\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_3\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_4\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_5\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_6\ : STD_LOGIC;
signal \counter_reg[8]_i_2_n_7\ : STD_LOGIC;
signal \h_count_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_2_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_5_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_6_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_7_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_8_n_0\ : STD_LOGIC;
signal \h_count_reg_reg__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_2_in : STD_LOGIC_VECTOR ( 31 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^start\ : STD_LOGIC;
signal start_i_1_n_0 : STD_LOGIC;
signal start_i_2_n_0 : STD_LOGIC;
signal start_i_3_n_0 : STD_LOGIC;
signal start_i_4_n_0 : STD_LOGIC;
signal start_i_5_n_0 : STD_LOGIC;
signal start_i_6_n_0 : STD_LOGIC;
signal \state[0]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_10_n_0\ : STD_LOGIC;
signal \state[1]_i_11_n_0\ : STD_LOGIC;
signal \state[1]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
signal \state[1]_i_4_n_0\ : STD_LOGIC;
signal \state[1]_i_5_n_0\ : STD_LOGIC;
signal \state[1]_i_6_n_0\ : STD_LOGIC;
signal \state[1]_i_7_n_0\ : STD_LOGIC;
signal \state[1]_i_8_n_0\ : STD_LOGIC;
signal \state[1]_i_9_n_0\ : STD_LOGIC;
signal \state_reg_n_0_[0]\ : STD_LOGIC;
signal \state_reg_n_0_[1]\ : STD_LOGIC;
signal \v_count_reg[9]_i_10_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_1_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_3_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_5_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_6_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_7_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_8_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_9_n_0\ : STD_LOGIC;
signal \v_count_reg_reg__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \NLW_counter_reg[31]_i_5_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_counter_reg[31]_i_5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \counter[0]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \counter[31]_i_15\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \counter[31]_i_18\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \h_count_reg[0]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \h_count_reg[1]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \h_count_reg[2]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \h_count_reg[3]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \h_count_reg[4]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[7]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \h_count_reg[8]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_7\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_8\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of start_i_3 : label is "soft_lutpair10";
attribute SOFT_HLUTNM of start_i_4 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of start_i_6 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \state[1]_i_10\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \v_count_reg[0]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \v_count_reg[1]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \v_count_reg[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[3]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[4]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \v_count_reg[7]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \v_count_reg[8]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_5\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_6\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_7\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_8\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_9\ : label is "soft_lutpair8";
begin
active <= \^active\;
start <= \^start\;
active_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000002FFFE"
)
port map (
I0 => \^active\,
I1 => active_i_2_n_0,
I2 => \v_count_reg[9]_i_1_n_0\,
I3 => start_i_2_n_0,
I4 => \state_reg_n_0_[0]\,
I5 => \counter[31]_i_1_n_0\,
O => active_i_1_n_0
);
active_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \v_count_reg[9]_i_6_n_0\,
I1 => counter(25),
I2 => counter(26),
I3 => counter(24),
I4 => \v_count_reg[9]_i_5_n_0\,
I5 => \counter[31]_i_7_n_0\,
O => active_i_2_n_0
);
active_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => active_i_1_n_0,
Q => \^active\,
R => '0'
);
\counter[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => counter(0),
O => p_2_in(0)
);
\counter[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[12]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(10)
);
\counter[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[12]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(11)
);
\counter[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[12]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(12)
);
\counter[12]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(12),
O => \counter[12]_i_3_n_0\
);
\counter[12]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(11),
O => \counter[12]_i_4_n_0\
);
\counter[12]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(10),
O => \counter[12]_i_5_n_0\
);
\counter[12]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(9),
O => \counter[12]_i_6_n_0\
);
\counter[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[16]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(13)
);
\counter[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[16]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(14)
);
\counter[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[16]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(15)
);
\counter[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[16]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(16)
);
\counter[16]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(16),
O => \counter[16]_i_3_n_0\
);
\counter[16]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(15),
O => \counter[16]_i_4_n_0\
);
\counter[16]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(14),
O => \counter[16]_i_5_n_0\
);
\counter[16]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(13),
O => \counter[16]_i_6_n_0\
);
\counter[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[20]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(17)
);
\counter[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[20]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(18)
);
\counter[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[20]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(19)
);
\counter[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[4]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(1)
);
\counter[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[20]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(20)
);
\counter[20]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(20),
O => \counter[20]_i_3_n_0\
);
\counter[20]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(19),
O => \counter[20]_i_4_n_0\
);
\counter[20]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(18),
O => \counter[20]_i_5_n_0\
);
\counter[20]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(17),
O => \counter[20]_i_6_n_0\
);
\counter[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[24]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(21)
);
\counter[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[24]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(22)
);
\counter[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[24]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(23)
);
\counter[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[24]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(24)
);
\counter[24]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(24),
O => \counter[24]_i_3_n_0\
);
\counter[24]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(23),
O => \counter[24]_i_4_n_0\
);
\counter[24]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(22),
O => \counter[24]_i_5_n_0\
);
\counter[24]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(21),
O => \counter[24]_i_6_n_0\
);
\counter[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[28]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(25)
);
\counter[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[28]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(26)
);
\counter[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[28]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(27)
);
\counter[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[28]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(28)
);
\counter[28]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(28),
O => \counter[28]_i_3_n_0\
);
\counter[28]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(27),
O => \counter[28]_i_4_n_0\
);
\counter[28]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(26),
O => \counter[28]_i_5_n_0\
);
\counter[28]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(25),
O => \counter[28]_i_6_n_0\
);
\counter[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[31]_i_5_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(29)
);
\counter[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[4]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(2)
);
\counter[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[31]_i_5_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(30)
);
\counter[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => vsync,
I1 => rst,
O => \counter[31]_i_1_n_0\
);
\counter[31]_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => counter(24),
I1 => counter(26),
I2 => counter(25),
O => \counter[31]_i_10_n_0\
);
\counter[31]_i_11\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(31),
O => \counter[31]_i_11_n_0\
);
\counter[31]_i_12\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(30),
O => \counter[31]_i_12_n_0\
);
\counter[31]_i_13\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(29),
O => \counter[31]_i_13_n_0\
);
\counter[31]_i_14\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => counter(17),
I1 => counter(16),
I2 => counter(19),
I3 => counter(18),
I4 => \v_count_reg[9]_i_10_n_0\,
I5 => \counter[31]_i_10_n_0\,
O => \counter[31]_i_14_n_0\
);
\counter[31]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => counter(31),
I1 => counter(30),
I2 => counter(29),
O => \counter[31]_i_15_n_0\
);
\counter[31]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF7FFFFFFFFFFF"
)
port map (
I0 => counter(2),
I1 => counter(1),
I2 => counter(0),
I3 => counter(3),
I4 => \state_reg_n_0_[1]\,
I5 => \state_reg_n_0_[0]\,
O => \counter[31]_i_16_n_0\
);
\counter[31]_i_17\: unisim.vcomponents.LUT4
generic map(
INIT => X"DFFF"
)
port map (
I0 => counter(4),
I1 => counter(8),
I2 => counter(6),
I3 => counter(5),
O => \counter[31]_i_17_n_0\
);
\counter[31]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => counter(10),
I1 => counter(11),
O => \counter[31]_i_18_n_0\
);
\counter[31]_i_19\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(15),
I1 => counter(14),
I2 => counter(13),
I3 => counter(12),
O => \counter[31]_i_19_n_0\
);
\counter[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \state_reg_n_0_[0]\,
I1 => \state_reg_n_0_[1]\,
O => \counter[31]_i_2_n_0\
);
\counter[31]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"4440404044404440"
)
port map (
I0 => \counter[31]_i_4_n_0\,
I1 => \counter_reg[31]_i_5_n_5\,
I2 => \counter[31]_i_6_n_0\,
I3 => \counter[31]_i_7_n_0\,
I4 => \counter[31]_i_8_n_0\,
I5 => \counter[31]_i_9_n_0\,
O => p_2_in(31)
);
\counter[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \v_count_reg[9]_i_6_n_0\,
I1 => start_i_5_n_0,
I2 => start_i_4_n_0,
I3 => \v_count_reg[9]_i_5_n_0\,
I4 => start_i_3_n_0,
I5 => \counter[31]_i_10_n_0\,
O => \counter[31]_i_4_n_0\
);
\counter[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFEFEFEFF"
)
port map (
I0 => \counter[31]_i_14_n_0\,
I1 => counter(28),
I2 => counter(27),
I3 => \state_reg_n_0_[1]\,
I4 => \state_reg_n_0_[0]\,
I5 => \counter[31]_i_15_n_0\,
O => \counter[31]_i_6_n_0\
);
\counter[31]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFEFF"
)
port map (
I0 => \counter[31]_i_16_n_0\,
I1 => \counter[31]_i_17_n_0\,
I2 => counter(7),
I3 => counter(9),
I4 => \counter[31]_i_18_n_0\,
I5 => \counter[31]_i_19_n_0\,
O => \counter[31]_i_7_n_0\
);
\counter[31]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFBFFF"
)
port map (
I0 => \h_count_reg[9]_i_5_n_0\,
I1 => counter(3),
I2 => counter(0),
I3 => counter(7),
I4 => counter(6),
I5 => \h_count_reg[9]_i_2_n_0\,
O => \counter[31]_i_8_n_0\
);
\counter[31]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \counter[31]_i_19_n_0\,
I1 => counter(10),
I2 => counter(11),
I3 => counter(8),
I4 => counter(9),
O => \counter[31]_i_9_n_0\
);
\counter[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[4]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(3)
);
\counter[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[4]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(4)
);
\counter[4]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(4),
O => \counter[4]_i_3_n_0\
);
\counter[4]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(3),
O => \counter[4]_i_4_n_0\
);
\counter[4]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(2),
O => \counter[4]_i_5_n_0\
);
\counter[4]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(1),
O => \counter[4]_i_6_n_0\
);
\counter[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[8]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(5)
);
\counter[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[8]_i_2_n_6\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(6)
);
\counter[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[8]_i_2_n_5\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(7)
);
\counter[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[8]_i_2_n_4\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(8)
);
\counter[8]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(8),
O => \counter[8]_i_3_n_0\
);
\counter[8]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(7),
O => \counter[8]_i_4_n_0\
);
\counter[8]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(6),
O => \counter[8]_i_5_n_0\
);
\counter[8]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => counter(5),
O => \counter[8]_i_6_n_0\
);
\counter[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EAEE0000"
)
port map (
I0 => \counter[31]_i_6_n_0\,
I1 => \counter[31]_i_7_n_0\,
I2 => \counter[31]_i_8_n_0\,
I3 => \counter[31]_i_9_n_0\,
I4 => \counter_reg[12]_i_2_n_7\,
I5 => \counter[31]_i_4_n_0\,
O => p_2_in(9)
);
\counter_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(0),
Q => counter(0),
R => \counter[31]_i_1_n_0\
);
\counter_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(10),
Q => counter(10),
R => \counter[31]_i_1_n_0\
);
\counter_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(11),
Q => counter(11),
R => \counter[31]_i_1_n_0\
);
\counter_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(12),
Q => counter(12),
R => \counter[31]_i_1_n_0\
);
\counter_reg[12]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[8]_i_2_n_0\,
CO(3) => \counter_reg[12]_i_2_n_0\,
CO(2) => \counter_reg[12]_i_2_n_1\,
CO(1) => \counter_reg[12]_i_2_n_2\,
CO(0) => \counter_reg[12]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[12]_i_2_n_4\,
O(2) => \counter_reg[12]_i_2_n_5\,
O(1) => \counter_reg[12]_i_2_n_6\,
O(0) => \counter_reg[12]_i_2_n_7\,
S(3) => \counter[12]_i_3_n_0\,
S(2) => \counter[12]_i_4_n_0\,
S(1) => \counter[12]_i_5_n_0\,
S(0) => \counter[12]_i_6_n_0\
);
\counter_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(13),
Q => counter(13),
R => \counter[31]_i_1_n_0\
);
\counter_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(14),
Q => counter(14),
R => \counter[31]_i_1_n_0\
);
\counter_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(15),
Q => counter(15),
R => \counter[31]_i_1_n_0\
);
\counter_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(16),
Q => counter(16),
R => \counter[31]_i_1_n_0\
);
\counter_reg[16]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[12]_i_2_n_0\,
CO(3) => \counter_reg[16]_i_2_n_0\,
CO(2) => \counter_reg[16]_i_2_n_1\,
CO(1) => \counter_reg[16]_i_2_n_2\,
CO(0) => \counter_reg[16]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[16]_i_2_n_4\,
O(2) => \counter_reg[16]_i_2_n_5\,
O(1) => \counter_reg[16]_i_2_n_6\,
O(0) => \counter_reg[16]_i_2_n_7\,
S(3) => \counter[16]_i_3_n_0\,
S(2) => \counter[16]_i_4_n_0\,
S(1) => \counter[16]_i_5_n_0\,
S(0) => \counter[16]_i_6_n_0\
);
\counter_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(17),
Q => counter(17),
R => \counter[31]_i_1_n_0\
);
\counter_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(18),
Q => counter(18),
R => \counter[31]_i_1_n_0\
);
\counter_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(19),
Q => counter(19),
R => \counter[31]_i_1_n_0\
);
\counter_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(1),
Q => counter(1),
R => \counter[31]_i_1_n_0\
);
\counter_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(20),
Q => counter(20),
R => \counter[31]_i_1_n_0\
);
\counter_reg[20]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[16]_i_2_n_0\,
CO(3) => \counter_reg[20]_i_2_n_0\,
CO(2) => \counter_reg[20]_i_2_n_1\,
CO(1) => \counter_reg[20]_i_2_n_2\,
CO(0) => \counter_reg[20]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[20]_i_2_n_4\,
O(2) => \counter_reg[20]_i_2_n_5\,
O(1) => \counter_reg[20]_i_2_n_6\,
O(0) => \counter_reg[20]_i_2_n_7\,
S(3) => \counter[20]_i_3_n_0\,
S(2) => \counter[20]_i_4_n_0\,
S(1) => \counter[20]_i_5_n_0\,
S(0) => \counter[20]_i_6_n_0\
);
\counter_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(21),
Q => counter(21),
R => \counter[31]_i_1_n_0\
);
\counter_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(22),
Q => counter(22),
R => \counter[31]_i_1_n_0\
);
\counter_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(23),
Q => counter(23),
R => \counter[31]_i_1_n_0\
);
\counter_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(24),
Q => counter(24),
R => \counter[31]_i_1_n_0\
);
\counter_reg[24]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[20]_i_2_n_0\,
CO(3) => \counter_reg[24]_i_2_n_0\,
CO(2) => \counter_reg[24]_i_2_n_1\,
CO(1) => \counter_reg[24]_i_2_n_2\,
CO(0) => \counter_reg[24]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[24]_i_2_n_4\,
O(2) => \counter_reg[24]_i_2_n_5\,
O(1) => \counter_reg[24]_i_2_n_6\,
O(0) => \counter_reg[24]_i_2_n_7\,
S(3) => \counter[24]_i_3_n_0\,
S(2) => \counter[24]_i_4_n_0\,
S(1) => \counter[24]_i_5_n_0\,
S(0) => \counter[24]_i_6_n_0\
);
\counter_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(25),
Q => counter(25),
R => \counter[31]_i_1_n_0\
);
\counter_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(26),
Q => counter(26),
R => \counter[31]_i_1_n_0\
);
\counter_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(27),
Q => counter(27),
R => \counter[31]_i_1_n_0\
);
\counter_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(28),
Q => counter(28),
R => \counter[31]_i_1_n_0\
);
\counter_reg[28]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[24]_i_2_n_0\,
CO(3) => \counter_reg[28]_i_2_n_0\,
CO(2) => \counter_reg[28]_i_2_n_1\,
CO(1) => \counter_reg[28]_i_2_n_2\,
CO(0) => \counter_reg[28]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[28]_i_2_n_4\,
O(2) => \counter_reg[28]_i_2_n_5\,
O(1) => \counter_reg[28]_i_2_n_6\,
O(0) => \counter_reg[28]_i_2_n_7\,
S(3) => \counter[28]_i_3_n_0\,
S(2) => \counter[28]_i_4_n_0\,
S(1) => \counter[28]_i_5_n_0\,
S(0) => \counter[28]_i_6_n_0\
);
\counter_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(29),
Q => counter(29),
R => \counter[31]_i_1_n_0\
);
\counter_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(2),
Q => counter(2),
R => \counter[31]_i_1_n_0\
);
\counter_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(30),
Q => counter(30),
R => \counter[31]_i_1_n_0\
);
\counter_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(31),
Q => counter(31),
R => \counter[31]_i_1_n_0\
);
\counter_reg[31]_i_5\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[28]_i_2_n_0\,
CO(3 downto 2) => \NLW_counter_reg[31]_i_5_CO_UNCONNECTED\(3 downto 2),
CO(1) => \counter_reg[31]_i_5_n_2\,
CO(0) => \counter_reg[31]_i_5_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \NLW_counter_reg[31]_i_5_O_UNCONNECTED\(3),
O(2) => \counter_reg[31]_i_5_n_5\,
O(1) => \counter_reg[31]_i_5_n_6\,
O(0) => \counter_reg[31]_i_5_n_7\,
S(3) => '0',
S(2) => \counter[31]_i_11_n_0\,
S(1) => \counter[31]_i_12_n_0\,
S(0) => \counter[31]_i_13_n_0\
);
\counter_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(3),
Q => counter(3),
R => \counter[31]_i_1_n_0\
);
\counter_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(4),
Q => counter(4),
R => \counter[31]_i_1_n_0\
);
\counter_reg[4]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \counter_reg[4]_i_2_n_0\,
CO(2) => \counter_reg[4]_i_2_n_1\,
CO(1) => \counter_reg[4]_i_2_n_2\,
CO(0) => \counter_reg[4]_i_2_n_3\,
CYINIT => counter(0),
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[4]_i_2_n_4\,
O(2) => \counter_reg[4]_i_2_n_5\,
O(1) => \counter_reg[4]_i_2_n_6\,
O(0) => \counter_reg[4]_i_2_n_7\,
S(3) => \counter[4]_i_3_n_0\,
S(2) => \counter[4]_i_4_n_0\,
S(1) => \counter[4]_i_5_n_0\,
S(0) => \counter[4]_i_6_n_0\
);
\counter_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(5),
Q => counter(5),
R => \counter[31]_i_1_n_0\
);
\counter_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(6),
Q => counter(6),
R => \counter[31]_i_1_n_0\
);
\counter_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(7),
Q => counter(7),
R => \counter[31]_i_1_n_0\
);
\counter_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(8),
Q => counter(8),
R => \counter[31]_i_1_n_0\
);
\counter_reg[8]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \counter_reg[4]_i_2_n_0\,
CO(3) => \counter_reg[8]_i_2_n_0\,
CO(2) => \counter_reg[8]_i_2_n_1\,
CO(1) => \counter_reg[8]_i_2_n_2\,
CO(0) => \counter_reg[8]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \counter_reg[8]_i_2_n_4\,
O(2) => \counter_reg[8]_i_2_n_5\,
O(1) => \counter_reg[8]_i_2_n_6\,
O(0) => \counter_reg[8]_i_2_n_7\,
S(3) => \counter[8]_i_3_n_0\,
S(2) => \counter[8]_i_4_n_0\,
S(1) => \counter[8]_i_5_n_0\,
S(0) => \counter[8]_i_6_n_0\
);
\counter_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \counter[31]_i_2_n_0\,
D => p_2_in(9),
Q => counter(9),
R => \counter[31]_i_1_n_0\
);
\h_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \h_count_reg_reg__0\(0),
O => \plusOp__0\(0)
);
\h_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \h_count_reg_reg__0\(0),
I1 => \h_count_reg_reg__0\(1),
O => \plusOp__0\(1)
);
\h_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \h_count_reg_reg__0\(2),
I1 => \h_count_reg_reg__0\(0),
I2 => \h_count_reg_reg__0\(1),
O => \plusOp__0\(2)
);
\h_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \h_count_reg_reg__0\(3),
I1 => \h_count_reg_reg__0\(1),
I2 => \h_count_reg_reg__0\(0),
I3 => \h_count_reg_reg__0\(2),
O => \plusOp__0\(3)
);
\h_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \h_count_reg_reg__0\(2),
I1 => \h_count_reg_reg__0\(0),
I2 => \h_count_reg_reg__0\(1),
I3 => \h_count_reg_reg__0\(3),
I4 => \h_count_reg_reg__0\(4),
O => \plusOp__0\(4)
);
\h_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \h_count_reg_reg__0\(5),
I1 => \h_count_reg_reg__0\(2),
I2 => \h_count_reg_reg__0\(0),
I3 => \h_count_reg_reg__0\(1),
I4 => \h_count_reg_reg__0\(3),
I5 => \h_count_reg_reg__0\(4),
O => \plusOp__0\(5)
);
\h_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \h_count_reg_reg__0\(6),
I1 => \h_count_reg[9]_i_7_n_0\,
I2 => \h_count_reg_reg__0\(5),
O => \plusOp__0\(6)
);
\h_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \h_count_reg_reg__0\(7),
I1 => \h_count_reg_reg__0\(5),
I2 => \h_count_reg[9]_i_7_n_0\,
I3 => \h_count_reg_reg__0\(6),
O => \plusOp__0\(7)
);
\h_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \h_count_reg_reg__0\(8),
I1 => \h_count_reg_reg__0\(6),
I2 => \h_count_reg[9]_i_7_n_0\,
I3 => \h_count_reg_reg__0\(5),
I4 => \h_count_reg_reg__0\(7),
O => \plusOp__0\(8)
);
\h_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDDDFDDDDDDDDD"
)
port map (
I0 => rst,
I1 => vsync,
I2 => \counter[31]_i_9_n_0\,
I3 => \h_count_reg[9]_i_4_n_0\,
I4 => \h_count_reg[9]_i_5_n_0\,
I5 => \h_count_reg[9]_i_6_n_0\,
O => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg[9]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \state_reg_n_0_[0]\,
I1 => \state_reg_n_0_[1]\,
O => \h_count_reg[9]_i_2_n_0\
);
\h_count_reg[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \h_count_reg_reg__0\(9),
I1 => \h_count_reg_reg__0\(7),
I2 => \h_count_reg_reg__0\(5),
I3 => \h_count_reg[9]_i_7_n_0\,
I4 => \h_count_reg_reg__0\(6),
I5 => \h_count_reg_reg__0\(8),
O => \plusOp__0\(9)
);
\h_count_reg[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FDFFFFFFFFFFFFFF"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => \state_reg_n_0_[0]\,
I2 => counter(6),
I3 => counter(7),
I4 => counter(0),
I5 => counter(3),
O => \h_count_reg[9]_i_4_n_0\
);
\h_count_reg[9]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => counter(1),
I1 => counter(2),
I2 => counter(4),
I3 => counter(5),
O => \h_count_reg[9]_i_5_n_0\
);
\h_count_reg[9]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \v_count_reg[9]_i_5_n_0\,
I1 => counter(24),
I2 => counter(26),
I3 => counter(25),
I4 => \v_count_reg[9]_i_10_n_0\,
I5 => \h_count_reg[9]_i_8_n_0\,
O => \h_count_reg[9]_i_6_n_0\
);
\h_count_reg[9]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => \h_count_reg_reg__0\(4),
I1 => \h_count_reg_reg__0\(3),
I2 => \h_count_reg_reg__0\(1),
I3 => \h_count_reg_reg__0\(0),
I4 => \h_count_reg_reg__0\(2),
O => \h_count_reg[9]_i_7_n_0\
);
\h_count_reg[9]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(17),
I1 => counter(16),
I2 => counter(19),
I3 => counter(18),
O => \h_count_reg[9]_i_8_n_0\
);
\h_count_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(0),
Q => \h_count_reg_reg__0\(0),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(1),
Q => \h_count_reg_reg__0\(1),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(2),
Q => \h_count_reg_reg__0\(2),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(3),
Q => \h_count_reg_reg__0\(3),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(4),
Q => \h_count_reg_reg__0\(4),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(5),
Q => \h_count_reg_reg__0\(5),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(6),
Q => \h_count_reg_reg__0\(6),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(7),
Q => \h_count_reg_reg__0\(7),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(8),
Q => \h_count_reg_reg__0\(8),
R => \h_count_reg[9]_i_1_n_0\
);
\h_count_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \h_count_reg[9]_i_2_n_0\,
D => \plusOp__0\(9),
Q => \h_count_reg_reg__0\(9),
R => \h_count_reg[9]_i_1_n_0\
);
start_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000220E0000"
)
port map (
I0 => \^start\,
I1 => start_i_2_n_0,
I2 => \state_reg_n_0_[0]\,
I3 => \state_reg_n_0_[1]\,
I4 => rst,
I5 => vsync,
O => start_i_1_n_0
);
start_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \h_count_reg[9]_i_6_n_0\,
I1 => start_i_3_n_0,
I2 => start_i_4_n_0,
I3 => start_i_5_n_0,
O => start_i_2_n_0
);
start_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(15),
I1 => counter(14),
I2 => counter(4),
I3 => counter(6),
O => start_i_3_n_0
);
start_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => counter(3),
I1 => counter(1),
I2 => counter(2),
I3 => counter(11),
I4 => start_i_6_n_0,
O => start_i_4_n_0
);
start_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF7"
)
port map (
I0 => counter(5),
I1 => counter(13),
I2 => counter(8),
I3 => counter(9),
I4 => \state_reg_n_0_[1]\,
I5 => \state_reg_n_0_[0]\,
O => start_i_5_n_0
);
start_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => counter(7),
I1 => counter(0),
I2 => counter(10),
I3 => counter(12),
O => start_i_6_n_0
);
start_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => start_i_1_n_0,
Q => \^start\,
R => '0'
);
\state[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FE560000"
)
port map (
I0 => \state_reg_n_0_[0]\,
I1 => \state[1]_i_2_n_0\,
I2 => start_i_2_n_0,
I3 => \state_reg_n_0_[1]\,
I4 => rst,
I5 => vsync,
O => \state[0]_i_1_n_0\
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000E6E2"
)
port map (
I0 => \state_reg_n_0_[1]\,
I1 => \state[1]_i_2_n_0\,
I2 => \state[1]_i_3_n_0\,
I3 => \state_reg_n_0_[0]\,
I4 => \state[1]_i_4_n_0\,
O => \state[1]_i_1_n_0\
);
\state[1]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => counter(2),
I1 => counter(1),
O => \state[1]_i_10_n_0\
);
\state[1]_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => counter(27),
I1 => counter(28),
O => \state[1]_i_11_n_0\
);
\state[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444F44444444"
)
port map (
I0 => \counter[31]_i_7_n_0\,
I1 => \h_count_reg[9]_i_6_n_0\,
I2 => \state[1]_i_5_n_0\,
I3 => \state[1]_i_6_n_0\,
I4 => \v_count_reg[9]_i_4_n_0\,
I5 => \state[1]_i_7_n_0\,
O => \state[1]_i_2_n_0\
);
\state[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => \v_count_reg[9]_i_7_n_0\,
I1 => \v_count_reg_reg__0\(9),
I2 => \v_count_reg_reg__0\(6),
I3 => \v_count_reg_reg__0\(5),
I4 => \v_count_reg_reg__0\(7),
I5 => \v_count_reg_reg__0\(8),
O => \state[1]_i_3_n_0\
);
\state[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAABAAAAAAAA"
)
port map (
I0 => \counter[31]_i_1_n_0\,
I1 => \state[1]_i_8_n_0\,
I2 => \state[1]_i_9_n_0\,
I3 => \state[1]_i_6_n_0\,
I4 => start_i_4_n_0,
I5 => \state[1]_i_7_n_0\,
O => \state[1]_i_4_n_0\
);
\state[1]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFB"
)
port map (
I0 => \state[1]_i_10_n_0\,
I1 => counter(7),
I2 => counter(5),
I3 => \h_count_reg[9]_i_2_n_0\,
I4 => \state[1]_i_9_n_0\,
I5 => \v_count_reg[9]_i_9_n_0\,
O => \state[1]_i_5_n_0\
);
\state[1]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => counter(25),
I1 => counter(26),
I2 => \state[1]_i_11_n_0\,
I3 => counter(16),
I4 => counter(31),
I5 => \v_count_reg[9]_i_8_n_0\,
O => \state[1]_i_6_n_0\
);
\state[1]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => counter(18),
I1 => counter(17),
I2 => counter(19),
I3 => \v_count_reg[9]_i_10_n_0\,
I4 => counter(24),
O => \state[1]_i_7_n_0\
);
\state[1]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF7"
)
port map (
I0 => counter(13),
I1 => counter(5),
I2 => \state_reg_n_0_[0]\,
I3 => \state_reg_n_0_[1]\,
I4 => counter(9),
I5 => counter(14),
O => \state[1]_i_8_n_0\
);
\state[1]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(30),
I1 => counter(29),
I2 => counter(4),
I3 => counter(8),
O => \state[1]_i_9_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \state[0]_i_1_n_0\,
Q => \state_reg_n_0_[0]\,
R => '0'
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => \state[1]_i_1_n_0\,
Q => \state_reg_n_0_[1]\,
R => '0'
);
\v_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \v_count_reg_reg__0\(0),
O => plusOp(0)
);
\v_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \v_count_reg_reg__0\(0),
I1 => \v_count_reg_reg__0\(1),
O => plusOp(1)
);
\v_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \v_count_reg_reg__0\(2),
I1 => \v_count_reg_reg__0\(0),
I2 => \v_count_reg_reg__0\(1),
O => plusOp(2)
);
\v_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \v_count_reg_reg__0\(3),
I1 => \v_count_reg_reg__0\(1),
I2 => \v_count_reg_reg__0\(0),
I3 => \v_count_reg_reg__0\(2),
O => plusOp(3)
);
\v_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \v_count_reg_reg__0\(4),
I1 => \v_count_reg_reg__0\(2),
I2 => \v_count_reg_reg__0\(0),
I3 => \v_count_reg_reg__0\(1),
I4 => \v_count_reg_reg__0\(3),
O => plusOp(4)
);
\v_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \v_count_reg_reg__0\(5),
I1 => \v_count_reg_reg__0\(3),
I2 => \v_count_reg_reg__0\(1),
I3 => \v_count_reg_reg__0\(0),
I4 => \v_count_reg_reg__0\(2),
I5 => \v_count_reg_reg__0\(4),
O => plusOp(5)
);
\v_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \v_count_reg_reg__0\(6),
I1 => \v_count_reg[9]_i_7_n_0\,
I2 => \v_count_reg_reg__0\(5),
O => plusOp(6)
);
\v_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \v_count_reg_reg__0\(7),
I1 => \v_count_reg_reg__0\(5),
I2 => \v_count_reg[9]_i_7_n_0\,
I3 => \v_count_reg_reg__0\(6),
O => plusOp(7)
);
\v_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A6AAAAAA"
)
port map (
I0 => \v_count_reg_reg__0\(8),
I1 => \v_count_reg_reg__0\(6),
I2 => \v_count_reg[9]_i_7_n_0\,
I3 => \v_count_reg_reg__0\(5),
I4 => \v_count_reg_reg__0\(7),
O => plusOp(8)
);
\v_count_reg[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => \v_count_reg[9]_i_3_n_0\,
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \v_count_reg[9]_i_5_n_0\,
I3 => \v_count_reg[9]_i_6_n_0\,
I4 => \state[1]_i_3_n_0\,
O => \v_count_reg[9]_i_1_n_0\
);
\v_count_reg[9]_i_10\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => counter(21),
I1 => counter(20),
I2 => counter(23),
I3 => counter(22),
O => \v_count_reg[9]_i_10_n_0\
);
\v_count_reg[9]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA6AAAAAAAAAAA"
)
port map (
I0 => \v_count_reg_reg__0\(9),
I1 => \v_count_reg_reg__0\(7),
I2 => \v_count_reg_reg__0\(8),
I3 => \v_count_reg_reg__0\(6),
I4 => \v_count_reg[9]_i_7_n_0\,
I5 => \v_count_reg_reg__0\(5),
O => plusOp(9)
);
\v_count_reg[9]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFB"
)
port map (
I0 => \v_count_reg[9]_i_8_n_0\,
I1 => counter(7),
I2 => counter(8),
I3 => \h_count_reg[9]_i_5_n_0\,
I4 => \v_count_reg[9]_i_9_n_0\,
I5 => \counter[31]_i_10_n_0\,
O => \v_count_reg[9]_i_3_n_0\
);
\v_count_reg[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => counter(11),
I1 => counter(10),
I2 => counter(9),
I3 => counter(14),
I4 => counter(12),
I5 => counter(13),
O => \v_count_reg[9]_i_4_n_0\
);
\v_count_reg[9]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => counter(28),
I1 => counter(27),
I2 => counter(29),
I3 => counter(30),
I4 => counter(31),
O => \v_count_reg[9]_i_5_n_0\
);
\v_count_reg[9]_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \v_count_reg[9]_i_10_n_0\,
I1 => counter(18),
I2 => counter(19),
I3 => counter(16),
I4 => counter(17),
O => \v_count_reg[9]_i_6_n_0\
);
\v_count_reg[9]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFFFFFF"
)
port map (
I0 => \v_count_reg_reg__0\(3),
I1 => \v_count_reg_reg__0\(1),
I2 => \v_count_reg_reg__0\(0),
I3 => \v_count_reg_reg__0\(2),
I4 => \v_count_reg_reg__0\(4),
O => \v_count_reg[9]_i_7_n_0\
);
\v_count_reg[9]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => counter(6),
I1 => counter(15),
O => \v_count_reg[9]_i_8_n_0\
);
\v_count_reg[9]_i_9\: unisim.vcomponents.LUT4
generic map(
INIT => X"FF7F"
)
port map (
I0 => counter(3),
I1 => counter(0),
I2 => \state_reg_n_0_[1]\,
I3 => \state_reg_n_0_[0]\,
O => \v_count_reg[9]_i_9_n_0\
);
\v_count_reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(0),
Q => \v_count_reg_reg__0\(0),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(1),
Q => \v_count_reg_reg__0\(1),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(2),
Q => \v_count_reg_reg__0\(2),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(3),
Q => \v_count_reg_reg__0\(3),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(4),
Q => \v_count_reg_reg__0\(4),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(5),
Q => \v_count_reg_reg__0\(5),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(6),
Q => \v_count_reg_reg__0\(6),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(7),
Q => \v_count_reg_reg__0\(7),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(8),
Q => \v_count_reg_reg__0\(8),
R => \counter[31]_i_1_n_0\
);
\v_count_reg_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => \v_count_reg[9]_i_1_n_0\,
D => plusOp(9),
Q => \v_count_reg_reg__0\(9),
R => \counter[31]_i_1_n_0\
);
\xaddr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(0),
Q => xaddr(0),
R => '0'
);
\xaddr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(1),
Q => xaddr(1),
R => '0'
);
\xaddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(2),
Q => xaddr(2),
R => '0'
);
\xaddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(3),
Q => xaddr(3),
R => '0'
);
\xaddr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(4),
Q => xaddr(4),
R => '0'
);
\xaddr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(5),
Q => xaddr(5),
R => '0'
);
\xaddr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(6),
Q => xaddr(6),
R => '0'
);
\xaddr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(7),
Q => xaddr(7),
R => '0'
);
\xaddr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(8),
Q => xaddr(8),
R => '0'
);
\xaddr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \h_count_reg_reg__0\(9),
Q => xaddr(9),
R => '0'
);
\yaddr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(0),
Q => yaddr(0),
R => '0'
);
\yaddr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(1),
Q => yaddr(1),
R => '0'
);
\yaddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(2),
Q => yaddr(2),
R => '0'
);
\yaddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(3),
Q => yaddr(3),
R => '0'
);
\yaddr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(4),
Q => yaddr(4),
R => '0'
);
\yaddr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(5),
Q => yaddr(5),
R => '0'
);
\yaddr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(6),
Q => yaddr(6),
R => '0'
);
\yaddr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(7),
Q => yaddr(7),
R => '0'
);
\yaddr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(8),
Q => yaddr(8),
R => '0'
);
\yaddr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \v_count_reg_reg__0\(9),
Q => yaddr(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_ref_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
start : out STD_LOGIC;
active : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_sync_ref_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_sync_ref_0_0 : entity is "system_vga_sync_ref_0_0,vga_sync_ref,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_sync_ref_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_sync_ref_0_0 : entity is "vga_sync_ref,Vivado 2016.4";
end system_vga_sync_ref_0_0;
architecture STRUCTURE of system_vga_sync_ref_0_0 is
begin
U0: entity work.system_vga_sync_ref_0_0_vga_sync_ref
port map (
active => active,
clk => clk,
rst => rst,
start => start,
vsync => vsync,
xaddr(9 downto 0) => xaddr(9 downto 0),
yaddr(9 downto 0) => yaddr(9 downto 0)
);
end STRUCTURE;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
video_ip/csi2_rx/csi2_rx.srcs/sources_1/imports/mipi-csi-rx/csi_rx_10bit_unpack.vhd
|
1
|
3705
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
--MIPI CSI-2 10bit pixel unpacker
--Copyright (C) 2016 David Shah
--Licensed under the MIT License
--This receives 32-bit words from the long video packet payload in; and unpacks them
--into 40 bits of output (which is only active - signified with the 'dout_valid' output -
--80% of the time). It is intended that the dout_valid signal drives the write enable for a linebuffer
--or FIFO.
--At the moment only MIPI 10bit RAW format is supported, other formats may be
--supported in the future (for 8bit you could simply bypass this entity)
entity csi_rx_10bit_unpack is
Port ( clock : in STD_LOGIC; --word clock in
reset : in STD_LOGIC; --synchronous active high reset
enable : in STD_LOGIC; --active high enable
data_in : in STD_LOGIC_VECTOR (31 downto 0); --packet payload in
din_valid : in STD_LOGIC; --payload in valid
data_out : out STD_LOGIC_VECTOR (39 downto 0); --unpacked data out
dout_valid : out STD_LOGIC); --data out valid (see above)
end csi_rx_10bit_unpack;
architecture Behavioral of csi_rx_10bit_unpack is
signal dout_int : std_logic_vector(39 downto 0);
signal bytes_int : std_logic_vector(31 downto 0);
signal byte_count_int : integer range 0 to 4;
signal dout_valid_int : std_logic;
signal dout_unpacked : std_logic_vector(39 downto 0);
signal dout_valid_up : std_logic;
--Unpack CSI packed 10-bit to 4 sequential 10-bit pixels
function mipi_unpack(packed : std_logic_vector)
return std_logic_vector is
variable result : std_logic_vector(39 downto 0);
begin
result(9 downto 0) := packed(7 downto 0) & packed(33 downto 32);
result(19 downto 10) := packed(15 downto 8) & packed(35 downto 34);
result(29 downto 20) := packed(23 downto 16) & packed(37 downto 36);
result(39 downto 30) := packed(31 downto 24) & packed(39 downto 38);
return result;
end mipi_unpack;
begin
process(clock, reset)
begin
if rising_edge(clock) then
if reset = '1' then
dout_int <= x"0000000000";
byte_count_int <= 0;
dout_valid_int <= '0';
elsif enable = '1' then
if din_valid = '1' then
--Behaviour is based on the number of bytes in the buffer
case byte_count_int is
when 0 =>
dout_int <= x"0000000000";
dout_valid_int <= '0';
bytes_int <= data_in;
byte_count_int <= 4;
when 1 =>
dout_int <= data_in & bytes_int(7 downto 0);
dout_valid_int <= '1';
bytes_int <= x"00000000";
byte_count_int <= 0;
when 2 =>
dout_int <= data_in(23 downto 0) & bytes_int(15 downto 0);
dout_valid_int <= '1';
bytes_int <= x"000000" & data_in(31 downto 24);
byte_count_int <= 1;
when 3 =>
dout_int <= data_in(15 downto 0) & bytes_int(23 downto 0);
dout_valid_int <= '1';
bytes_int <= x"0000" & data_in(31 downto 16);
byte_count_int <= 2;
when 4 =>
dout_int <= data_in(7 downto 0) & bytes_int(31 downto 0);
dout_valid_int <= '1';
bytes_int <= x"00" & data_in(31 downto 8);
byte_count_int <= 3;
end case;
else
byte_count_int <= 0;
dout_valid_int <= '0';
end if;
dout_unpacked <= mipi_unpack(dout_int);
dout_valid_up <= dout_valid_int;
data_out <= dout_unpacked;
dout_valid <= dout_valid_up;
end if;
end if;
end process;
end Behavioral;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0/system_ov7670_controller_0_0_sim_netlist.vhdl
|
1
|
70465
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue Jun 06 02:48:32 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0/system_ov7670_controller_0_0_sim_netlist.vhdl
-- Design : system_ov7670_controller_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_i2c_sender is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
sioc : out STD_LOGIC;
p_0_in : out STD_LOGIC;
\busy_sr_reg[1]_0\ : out STD_LOGIC;
siod : out STD_LOGIC;
\busy_sr_reg[31]_0\ : in STD_LOGIC;
clk : in STD_LOGIC;
p_1_in : in STD_LOGIC_VECTOR ( 0 to 0 );
DOADO : in STD_LOGIC_VECTOR ( 15 downto 0 );
\busy_sr_reg[31]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_controller_0_0_i2c_sender : entity is "i2c_sender";
end system_ov7670_controller_0_0_i2c_sender;
architecture STRUCTURE of system_ov7670_controller_0_0_i2c_sender is
signal busy_sr0 : STD_LOGIC;
signal \busy_sr[0]_i_3_n_0\ : STD_LOGIC;
signal \busy_sr[0]_i_5_n_0\ : STD_LOGIC;
signal \busy_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[11]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[1]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[20]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[21]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[23]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[24]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[25]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[26]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[28]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[29]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[2]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \busy_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \busy_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \^busy_sr_reg[1]_0\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[0]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \busy_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \data_sr[10]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[12]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[13]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[14]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[15]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[16]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[17]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[18]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[19]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[22]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[27]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[30]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[31]_i_2_n_0\ : STD_LOGIC;
signal \data_sr[3]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[4]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[5]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[6]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[7]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[8]_i_1_n_0\ : STD_LOGIC;
signal \data_sr[9]_i_1_n_0\ : STD_LOGIC;
signal \data_sr_reg_n_0_[10]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[11]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[12]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[13]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[14]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[15]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[16]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[17]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[18]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[19]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[1]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[20]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[21]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[22]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[23]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[24]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[25]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[26]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[27]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[28]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[29]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[2]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[30]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[31]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[3]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[4]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[5]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[6]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[7]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[8]\ : STD_LOGIC;
signal \data_sr_reg_n_0_[9]\ : STD_LOGIC;
signal \divider_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 6 );
signal \divider_reg__1\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^p_0_in\ : STD_LOGIC;
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal p_1_in_0 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal sioc_i_1_n_0 : STD_LOGIC;
signal sioc_i_2_n_0 : STD_LOGIC;
signal sioc_i_3_n_0 : STD_LOGIC;
signal sioc_i_4_n_0 : STD_LOGIC;
signal sioc_i_5_n_0 : STD_LOGIC;
signal siod_INST_0_i_1_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \busy_sr[0]_i_4\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \busy_sr[0]_i_5\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \busy_sr[10]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[11]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[12]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[13]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[14]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[15]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[16]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[17]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \busy_sr[18]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \busy_sr[19]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \busy_sr[20]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[21]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[22]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[23]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[24]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \busy_sr[25]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[26]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \busy_sr[27]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \busy_sr[28]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \busy_sr[29]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \busy_sr[2]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \busy_sr[30]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \busy_sr[31]_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \busy_sr[3]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \busy_sr[4]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \busy_sr[5]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \busy_sr[6]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \busy_sr[7]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \busy_sr[8]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \busy_sr[9]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \data_sr[10]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[12]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[13]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \data_sr[14]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \data_sr[15]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[16]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[17]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[18]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[19]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[31]_i_2\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \data_sr[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \data_sr[4]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \data_sr[5]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \data_sr[6]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \data_sr[7]_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \data_sr[8]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \data_sr[9]_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \divider[0]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[1]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \divider[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \divider[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \divider[6]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \divider[7]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of sioc_i_3 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of sioc_i_4 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of sioc_i_5 : label is "soft_lutpair3";
begin
\busy_sr_reg[1]_0\ <= \^busy_sr_reg[1]_0\;
p_0_in <= \^p_0_in\;
\busy_sr[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4000FFFF40004000"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
I2 => \divider_reg__0\(7),
I3 => \^p_0_in\,
I4 => \^busy_sr_reg[1]_0\,
I5 => p_1_in(0),
O => busy_sr0
);
\busy_sr[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \busy_sr[0]_i_3_n_0\
);
\busy_sr[0]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(3),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \busy_sr[0]_i_5_n_0\,
O => \^busy_sr_reg[1]_0\
);
\busy_sr[0]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \divider_reg__1\(5),
I1 => \divider_reg__1\(4),
I2 => \divider_reg__0\(7),
I3 => \divider_reg__0\(6),
O => \busy_sr[0]_i_5_n_0\
);
\busy_sr[10]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
O => \busy_sr[10]_i_1_n_0\
);
\busy_sr[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[10]\,
I1 => \^p_0_in\,
O => \busy_sr[11]_i_1_n_0\
);
\busy_sr[12]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
O => \busy_sr[12]_i_1_n_0\
);
\busy_sr[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
O => \busy_sr[13]_i_1_n_0\
);
\busy_sr[14]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
O => \busy_sr[14]_i_1_n_0\
);
\busy_sr[15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
O => \busy_sr[15]_i_1_n_0\
);
\busy_sr[16]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
O => \busy_sr[16]_i_1_n_0\
);
\busy_sr[17]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
O => \busy_sr[17]_i_1_n_0\
);
\busy_sr[18]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
O => \busy_sr[18]_i_1_n_0\
);
\busy_sr[19]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
O => \busy_sr[19]_i_1_n_0\
);
\busy_sr[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \^p_0_in\,
O => \busy_sr[1]_i_1_n_0\
);
\busy_sr[20]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(0),
I1 => \^p_0_in\,
O => \busy_sr[20]_i_1_n_0\
);
\busy_sr[21]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_1_in_0(1),
I1 => \^p_0_in\,
O => \busy_sr[21]_i_1_n_0\
);
\busy_sr[22]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[21]\,
I1 => \^p_0_in\,
O => \busy_sr[22]_i_1_n_0\
);
\busy_sr[23]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[22]\,
I1 => \^p_0_in\,
O => \busy_sr[23]_i_1_n_0\
);
\busy_sr[24]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[23]\,
I1 => \^p_0_in\,
O => \busy_sr[24]_i_1_n_0\
);
\busy_sr[25]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[24]\,
I1 => \^p_0_in\,
O => \busy_sr[25]_i_1_n_0\
);
\busy_sr[26]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[25]\,
I1 => \^p_0_in\,
O => \busy_sr[26]_i_1_n_0\
);
\busy_sr[27]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[26]\,
I1 => \^p_0_in\,
O => \busy_sr[27]_i_1_n_0\
);
\busy_sr[28]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[27]\,
I1 => \^p_0_in\,
O => \busy_sr[28]_i_1_n_0\
);
\busy_sr[29]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \^p_0_in\,
O => \busy_sr[29]_i_1_n_0\
);
\busy_sr[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[1]\,
I1 => \^p_0_in\,
O => \busy_sr[2]_i_1_n_0\
);
\busy_sr[30]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \^p_0_in\,
O => \busy_sr[30]_i_1_n_0\
);
\busy_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"22222222A2222222"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
I3 => \divider_reg__0\(7),
I4 => \divider_reg__0\(6),
I5 => \busy_sr[0]_i_3_n_0\,
O => \busy_sr[31]_i_1_n_0\
);
\busy_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^p_0_in\,
I1 => \busy_sr_reg_n_0_[30]\,
O => \busy_sr[31]_i_2_n_0\
);
\busy_sr[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
O => \busy_sr[3]_i_1_n_0\
);
\busy_sr[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
O => \busy_sr[4]_i_1_n_0\
);
\busy_sr[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
O => \busy_sr[5]_i_1_n_0\
);
\busy_sr[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
O => \busy_sr[6]_i_1_n_0\
);
\busy_sr[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
O => \busy_sr[7]_i_1_n_0\
);
\busy_sr[8]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
O => \busy_sr[8]_i_1_n_0\
);
\busy_sr[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \busy_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
O => \busy_sr[9]_i_1_n_0\
);
\busy_sr_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => p_1_in(0),
Q => \busy_sr_reg_n_0_[0]\,
R => '0'
);
\busy_sr_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[10]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[10]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[11]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[11]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[11]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[12]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[12]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[12]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[13]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[13]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[13]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[14]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[14]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[14]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[15]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[15]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[15]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[16]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[16]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[16]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[17]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[17]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[17]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[18]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[18]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[18]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[19]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[19]_i_1_n_0\,
Q => p_1_in_0(0),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[1]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[1]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[20]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[20]_i_1_n_0\,
Q => p_1_in_0(1),
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[21]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[21]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[21]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[22]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[22]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[22]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[23]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[23]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[23]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[24]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[24]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[24]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[25]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[25]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[25]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[26]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[26]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[26]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[27]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[27]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[27]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[28]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[28]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[28]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[29]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[29]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[29]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[2]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[2]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[30]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[30]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[30]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[31]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[31]_i_2_n_0\,
Q => \^p_0_in\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[3]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[3]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[4]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[4]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[5]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[5]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[6]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[6]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[7]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[7]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[8]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[8]\,
S => \busy_sr[31]_i_1_n_0\
);
\busy_sr_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => busy_sr0,
D => \busy_sr[9]_i_1_n_0\,
Q => \busy_sr_reg_n_0_[9]\,
S => \busy_sr[31]_i_1_n_0\
);
\data_sr[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[9]\,
I1 => \^p_0_in\,
I2 => DOADO(7),
O => \data_sr[10]_i_1_n_0\
);
\data_sr[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[11]\,
I1 => \^p_0_in\,
I2 => DOADO(8),
O => \data_sr[12]_i_1_n_0\
);
\data_sr[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[12]\,
I1 => \^p_0_in\,
I2 => DOADO(9),
O => \data_sr[13]_i_1_n_0\
);
\data_sr[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[13]\,
I1 => \^p_0_in\,
I2 => DOADO(10),
O => \data_sr[14]_i_1_n_0\
);
\data_sr[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[14]\,
I1 => \^p_0_in\,
I2 => DOADO(11),
O => \data_sr[15]_i_1_n_0\
);
\data_sr[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[15]\,
I1 => \^p_0_in\,
I2 => DOADO(12),
O => \data_sr[16]_i_1_n_0\
);
\data_sr[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[16]\,
I1 => \^p_0_in\,
I2 => DOADO(13),
O => \data_sr[17]_i_1_n_0\
);
\data_sr[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[17]\,
I1 => \^p_0_in\,
I2 => DOADO(14),
O => \data_sr[18]_i_1_n_0\
);
\data_sr[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[18]\,
I1 => \^p_0_in\,
I2 => DOADO(15),
O => \data_sr[19]_i_1_n_0\
);
\data_sr[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[22]\,
I1 => \data_sr_reg_n_0_[21]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[22]_i_1_n_0\
);
\data_sr[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[27]\,
I1 => \data_sr_reg_n_0_[26]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[27]_i_1_n_0\
);
\data_sr[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => p_1_in(0),
I1 => \^busy_sr_reg[1]_0\,
I2 => \^p_0_in\,
O => \data_sr[30]_i_1_n_0\
);
\data_sr[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFCFCFCFAACAAAAA"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => \data_sr_reg_n_0_[30]\,
I2 => \^p_0_in\,
I3 => \data_sr[31]_i_2_n_0\,
I4 => \divider_reg__0\(7),
I5 => \busy_sr_reg[31]_0\,
O => \data_sr[31]_i_1_n_0\
);
\data_sr[31]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \data_sr[31]_i_2_n_0\
);
\data_sr[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[2]\,
I1 => \^p_0_in\,
I2 => DOADO(0),
O => \data_sr[3]_i_1_n_0\
);
\data_sr[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[3]\,
I1 => \^p_0_in\,
I2 => DOADO(1),
O => \data_sr[4]_i_1_n_0\
);
\data_sr[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[4]\,
I1 => \^p_0_in\,
I2 => DOADO(2),
O => \data_sr[5]_i_1_n_0\
);
\data_sr[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[5]\,
I1 => \^p_0_in\,
I2 => DOADO(3),
O => \data_sr[6]_i_1_n_0\
);
\data_sr[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[6]\,
I1 => \^p_0_in\,
I2 => DOADO(4),
O => \data_sr[7]_i_1_n_0\
);
\data_sr[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[7]\,
I1 => \^p_0_in\,
I2 => DOADO(5),
O => \data_sr[8]_i_1_n_0\
);
\data_sr[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \data_sr_reg_n_0_[8]\,
I1 => \^p_0_in\,
I2 => DOADO(6),
O => \data_sr[9]_i_1_n_0\
);
\data_sr_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[10]_i_1_n_0\,
Q => \data_sr_reg_n_0_[10]\,
R => '0'
);
\data_sr_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[10]\,
Q => \data_sr_reg_n_0_[11]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[12]_i_1_n_0\,
Q => \data_sr_reg_n_0_[12]\,
R => '0'
);
\data_sr_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[13]_i_1_n_0\,
Q => \data_sr_reg_n_0_[13]\,
R => '0'
);
\data_sr_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[14]_i_1_n_0\,
Q => \data_sr_reg_n_0_[14]\,
R => '0'
);
\data_sr_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[15]_i_1_n_0\,
Q => \data_sr_reg_n_0_[15]\,
R => '0'
);
\data_sr_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[16]_i_1_n_0\,
Q => \data_sr_reg_n_0_[16]\,
R => '0'
);
\data_sr_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[17]_i_1_n_0\,
Q => \data_sr_reg_n_0_[17]\,
R => '0'
);
\data_sr_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[18]_i_1_n_0\,
Q => \data_sr_reg_n_0_[18]\,
R => '0'
);
\data_sr_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[19]_i_1_n_0\,
Q => \data_sr_reg_n_0_[19]\,
R => '0'
);
\data_sr_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \^p_0_in\,
Q => \data_sr_reg_n_0_[1]\,
R => '0'
);
\data_sr_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[19]\,
Q => \data_sr_reg_n_0_[20]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[20]\,
Q => \data_sr_reg_n_0_[21]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[22]_i_1_n_0\,
Q => \data_sr_reg_n_0_[22]\,
R => '0'
);
\data_sr_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[22]\,
Q => \data_sr_reg_n_0_[23]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[23]\,
Q => \data_sr_reg_n_0_[24]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[24]\,
Q => \data_sr_reg_n_0_[25]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[25]\,
Q => \data_sr_reg_n_0_[26]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[27]_i_1_n_0\,
Q => \data_sr_reg_n_0_[27]\,
R => '0'
);
\data_sr_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[27]\,
Q => \data_sr_reg_n_0_[28]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[28]\,
Q => \data_sr_reg_n_0_[29]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[1]\,
Q => \data_sr_reg_n_0_[2]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr_reg_n_0_[29]\,
Q => \data_sr_reg_n_0_[30]\,
R => \data_sr[30]_i_1_n_0\
);
\data_sr_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => '1',
D => \data_sr[31]_i_1_n_0\,
Q => \data_sr_reg_n_0_[31]\,
R => '0'
);
\data_sr_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[3]_i_1_n_0\,
Q => \data_sr_reg_n_0_[3]\,
R => '0'
);
\data_sr_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[4]_i_1_n_0\,
Q => \data_sr_reg_n_0_[4]\,
R => '0'
);
\data_sr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[5]_i_1_n_0\,
Q => \data_sr_reg_n_0_[5]\,
R => '0'
);
\data_sr_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[6]_i_1_n_0\,
Q => \data_sr_reg_n_0_[6]\,
R => '0'
);
\data_sr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[7]_i_1_n_0\,
Q => \data_sr_reg_n_0_[7]\,
R => '0'
);
\data_sr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[8]_i_1_n_0\,
Q => \data_sr_reg_n_0_[8]\,
R => '0'
);
\data_sr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => busy_sr0,
D => \data_sr[9]_i_1_n_0\,
Q => \data_sr_reg_n_0_[9]\,
R => '0'
);
\divider[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \divider_reg__1\(0),
O => \p_0_in__0\(0)
);
\divider[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__1\(0),
I1 => \divider_reg__1\(1),
O => \p_0_in__0\(1)
);
\divider[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \divider_reg__1\(1),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(2),
O => \p_0_in__0\(2)
);
\divider[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \divider_reg__1\(2),
I1 => \divider_reg__1\(0),
I2 => \divider_reg__1\(1),
I3 => \divider_reg__1\(3),
O => \p_0_in__0\(3)
);
\divider[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \divider_reg__1\(3),
I1 => \divider_reg__1\(1),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(2),
I4 => \divider_reg__1\(4),
O => \p_0_in__0\(4)
);
\divider[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \divider_reg__1\(4),
I1 => \divider_reg__1\(2),
I2 => \divider_reg__1\(0),
I3 => \divider_reg__1\(1),
I4 => \divider_reg__1\(3),
I5 => \divider_reg__1\(5),
O => \p_0_in__0\(5)
);
\divider[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \busy_sr[0]_i_3_n_0\,
I1 => \divider_reg__0\(6),
O => \p_0_in__0\(6)
);
\divider[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \busy_sr[0]_i_3_n_0\,
I2 => \divider_reg__0\(7),
O => \p_0_in__0\(7)
);
\divider_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(0),
Q => \divider_reg__1\(0),
R => '0'
);
\divider_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(1),
Q => \divider_reg__1\(1),
R => '0'
);
\divider_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(2),
Q => \divider_reg__1\(2),
R => '0'
);
\divider_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(3),
Q => \divider_reg__1\(3),
R => '0'
);
\divider_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(4),
Q => \divider_reg__1\(4),
R => '0'
);
\divider_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(5),
Q => \divider_reg__1\(5),
R => '0'
);
\divider_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(6),
Q => \divider_reg__0\(6),
R => '0'
);
\divider_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => \busy_sr_reg[31]_1\(0),
D => \p_0_in__0\(7),
Q => \divider_reg__0\(7),
R => '0'
);
sioc_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFCFFF8FFFFFFFF"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => sioc_i_2_n_0,
I2 => sioc_i_3_n_0,
I3 => \busy_sr_reg_n_0_[1]\,
I4 => sioc_i_4_n_0,
I5 => \^p_0_in\,
O => sioc_i_1_n_0
);
sioc_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \divider_reg__0\(6),
I1 => \divider_reg__0\(7),
O => sioc_i_2_n_0
);
sioc_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"A222"
)
port map (
I0 => sioc_i_5_n_0,
I1 => \busy_sr_reg_n_0_[30]\,
I2 => \divider_reg__0\(6),
I3 => \^p_0_in\,
O => sioc_i_3_n_0
);
sioc_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \busy_sr_reg_n_0_[29]\,
I1 => \busy_sr_reg_n_0_[2]\,
I2 => \^p_0_in\,
I3 => \busy_sr_reg_n_0_[30]\,
O => sioc_i_4_n_0
);
sioc_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \busy_sr_reg_n_0_[0]\,
I1 => \busy_sr_reg_n_0_[1]\,
I2 => \busy_sr_reg_n_0_[29]\,
I3 => \busy_sr_reg_n_0_[2]\,
O => sioc_i_5_n_0
);
sioc_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => sioc_i_1_n_0,
Q => sioc,
R => '0'
);
siod_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \data_sr_reg_n_0_[31]\,
I1 => siod_INST_0_i_1_n_0,
O => siod
);
siod_INST_0_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"B0BBB0BB0000B0BB"
)
port map (
I0 => \busy_sr_reg_n_0_[28]\,
I1 => \busy_sr_reg_n_0_[29]\,
I2 => p_1_in_0(0),
I3 => p_1_in_0(1),
I4 => \busy_sr_reg_n_0_[11]\,
I5 => \busy_sr_reg_n_0_[10]\,
O => siod_INST_0_i_1_n_0
);
taken_reg: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \busy_sr_reg[31]_0\,
Q => E(0),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_ov7670_registers is
port (
DOADO : out STD_LOGIC_VECTOR ( 15 downto 0 );
\divider_reg[7]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
config_finished : out STD_LOGIC;
taken_reg : out STD_LOGIC;
p_1_in : out STD_LOGIC_VECTOR ( 0 to 0 );
clk : in STD_LOGIC;
\divider_reg[2]\ : in STD_LOGIC;
p_0_in : in STD_LOGIC;
resend : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_controller_0_0_ov7670_registers : entity is "ov7670_registers";
end system_ov7670_controller_0_0_ov7670_registers;
architecture STRUCTURE of system_ov7670_controller_0_0_ov7670_registers is
signal \^doado\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal address : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \address_rep[0]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[1]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[2]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[3]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[4]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[5]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[6]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_1_n_0\ : STD_LOGIC;
signal \address_rep[7]_i_2_n_0\ : STD_LOGIC;
signal config_finished_INST_0_i_1_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_2_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_3_n_0 : STD_LOGIC;
signal config_finished_INST_0_i_4_n_0 : STD_LOGIC;
signal NLW_sreg_reg_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_sreg_reg_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_sreg_reg_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \address_reg[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg[7]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[0]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[1]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[2]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[3]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[4]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[5]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[6]\ : label is "no";
attribute equivalent_register_removal of \address_reg_rep[7]\ : label is "no";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \address_rep[1]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[2]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \address_rep[3]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[4]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \address_rep[6]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \address_rep[7]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \busy_sr[0]_i_2\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of config_finished_INST_0 : label is "soft_lutpair30";
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of sreg_reg : label is "INDEPENDENT";
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of sreg_reg : label is "p0_d16";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of sreg_reg : label is "{SYNTH-6 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of sreg_reg : label is 4096;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of sreg_reg : label is "U0/Inst_ov7670_registers/sreg";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of sreg_reg : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of sreg_reg : label is 1023;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of sreg_reg : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of sreg_reg : label is 15;
begin
DOADO(15 downto 0) <= \^doado\(15 downto 0);
\address_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => \address_reg__0\(0),
R => resend
);
\address_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => \address_reg__0\(1),
R => resend
);
\address_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => \address_reg__0\(2),
R => resend
);
\address_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => \address_reg__0\(3),
R => resend
);
\address_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => \address_reg__0\(4),
R => resend
);
\address_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => \address_reg__0\(5),
R => resend
);
\address_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => \address_reg__0\(6),
R => resend
);
\address_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => \address_reg__0\(7),
R => resend
);
\address_reg_rep[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[0]_i_1_n_0\,
Q => address(0),
R => resend
);
\address_reg_rep[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[1]_i_1_n_0\,
Q => address(1),
R => resend
);
\address_reg_rep[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[2]_i_1_n_0\,
Q => address(2),
R => resend
);
\address_reg_rep[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[3]_i_1_n_0\,
Q => address(3),
R => resend
);
\address_reg_rep[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[4]_i_1_n_0\,
Q => address(4),
R => resend
);
\address_reg_rep[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[5]_i_1_n_0\,
Q => address(5),
R => resend
);
\address_reg_rep[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[6]_i_1_n_0\,
Q => address(6),
R => resend
);
\address_reg_rep[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => E(0),
D => \address_rep[7]_i_1_n_0\,
Q => address(7),
R => resend
);
\address_rep[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \address_reg__0\(0),
O => \address_rep[0]_i_1_n_0\
);
\address_rep[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \address_reg__0\(0),
I1 => \address_reg__0\(1),
O => \address_rep[1]_i_1_n_0\
);
\address_rep[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \address_reg__0\(1),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(2),
O => \address_rep[2]_i_1_n_0\
);
\address_rep[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \address_reg__0\(2),
I1 => \address_reg__0\(0),
I2 => \address_reg__0\(1),
I3 => \address_reg__0\(3),
O => \address_rep[3]_i_1_n_0\
);
\address_rep[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \address_reg__0\(3),
I1 => \address_reg__0\(1),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(2),
I4 => \address_reg__0\(4),
O => \address_rep[4]_i_1_n_0\
);
\address_rep[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[5]_i_1_n_0\
);
\address_rep[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \address_rep[7]_i_2_n_0\,
I1 => \address_reg__0\(6),
O => \address_rep[6]_i_1_n_0\
);
\address_rep[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D2"
)
port map (
I0 => \address_reg__0\(6),
I1 => \address_rep[7]_i_2_n_0\,
I2 => \address_reg__0\(7),
O => \address_rep[7]_i_1_n_0\
);
\address_rep[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \address_reg__0\(4),
I1 => \address_reg__0\(2),
I2 => \address_reg__0\(0),
I3 => \address_reg__0\(1),
I4 => \address_reg__0\(3),
I5 => \address_reg__0\(5),
O => \address_rep[7]_i_2_n_0\
);
\busy_sr[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000FFFE"
)
port map (
I0 => config_finished_INST_0_i_4_n_0,
I1 => config_finished_INST_0_i_3_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_1_n_0,
I4 => p_0_in,
O => p_1_in(0)
);
config_finished_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
O => config_finished
);
config_finished_INST_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(5),
I1 => \^doado\(4),
I2 => \^doado\(7),
I3 => \^doado\(6),
O => config_finished_INST_0_i_1_n_0
);
config_finished_INST_0_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(1),
I1 => \^doado\(0),
I2 => \^doado\(3),
I3 => \^doado\(2),
O => config_finished_INST_0_i_2_n_0
);
config_finished_INST_0_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(13),
I1 => \^doado\(12),
I2 => \^doado\(15),
I3 => \^doado\(14),
O => config_finished_INST_0_i_3_n_0
);
config_finished_INST_0_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^doado\(9),
I1 => \^doado\(8),
I2 => \^doado\(11),
I3 => \^doado\(10),
O => config_finished_INST_0_i_4_n_0
);
\divider[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFE0000"
)
port map (
I0 => config_finished_INST_0_i_1_n_0,
I1 => config_finished_INST_0_i_2_n_0,
I2 => config_finished_INST_0_i_3_n_0,
I3 => config_finished_INST_0_i_4_n_0,
I4 => \divider_reg[2]\,
I5 => p_0_in,
O => \divider_reg[7]\(0)
);
sreg_reg: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"53295217510C50344F4014383A04401004008C003E000C001100120412801280",
INIT_01 => X"229121021E3716020F4B0E61030A1A7B190332A41861171111003DC0581E5440",
INIT_02 => X"90008F008E008D4F74106B4A69004E204D403C78392A3871371D350B330B2907",
INIT_03 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFB80AB382B20EB10CB0849A0096009100",
INIT_04 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_05 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_06 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_07 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_08 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_09 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0A => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0B => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0C => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0D => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0E => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 0
)
port map (
ADDRARDADDR(13 downto 12) => B"00",
ADDRARDADDR(11 downto 4) => address(7 downto 0),
ADDRARDADDR(3 downto 0) => B"0000",
ADDRBWRADDR(13 downto 0) => B"11111111111111",
CLKARDCLK => clk,
CLKBWRCLK => '0',
DIADI(15 downto 0) => B"1111111111111111",
DIBDI(15 downto 0) => B"1111111111111111",
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"11",
DOADO(15 downto 0) => \^doado\(15 downto 0),
DOBDO(15 downto 0) => NLW_sreg_reg_DOBDO_UNCONNECTED(15 downto 0),
DOPADOP(1 downto 0) => NLW_sreg_reg_DOPADOP_UNCONNECTED(1 downto 0),
DOPBDOP(1 downto 0) => NLW_sreg_reg_DOPBDOP_UNCONNECTED(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1 downto 0) => B"00",
WEBWE(3 downto 0) => B"0000"
);
taken_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000055555554"
)
port map (
I0 => p_0_in,
I1 => config_finished_INST_0_i_1_n_0,
I2 => config_finished_INST_0_i_2_n_0,
I3 => config_finished_INST_0_i_3_n_0,
I4 => config_finished_INST_0_i_4_n_0,
I5 => \divider_reg[2]\,
O => taken_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0_ov7670_controller is
port (
config_finished : out STD_LOGIC;
siod : out STD_LOGIC;
sioc : out STD_LOGIC;
resend : in STD_LOGIC;
clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_ov7670_controller_0_0_ov7670_controller : entity is "ov7670_controller";
end system_ov7670_controller_0_0_ov7670_controller;
architecture STRUCTURE of system_ov7670_controller_0_0_ov7670_controller is
signal Inst_i2c_sender_n_3 : STD_LOGIC;
signal Inst_ov7670_registers_n_16 : STD_LOGIC;
signal Inst_ov7670_registers_n_18 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 0 to 0 );
signal sreg_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
signal taken : STD_LOGIC;
begin
Inst_i2c_sender: entity work.system_ov7670_controller_0_0_i2c_sender
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
\busy_sr_reg[1]_0\ => Inst_i2c_sender_n_3,
\busy_sr_reg[31]_0\ => Inst_ov7670_registers_n_18,
\busy_sr_reg[31]_1\(0) => Inst_ov7670_registers_n_16,
clk => clk,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
sioc => sioc,
siod => siod
);
Inst_ov7670_registers: entity work.system_ov7670_controller_0_0_ov7670_registers
port map (
DOADO(15 downto 0) => sreg_reg(15 downto 0),
E(0) => taken,
clk => clk,
config_finished => config_finished,
\divider_reg[2]\ => Inst_i2c_sender_n_3,
\divider_reg[7]\(0) => Inst_ov7670_registers_n_16,
p_0_in => p_0_in,
p_1_in(0) => p_1_in(0),
resend => resend,
taken_reg => Inst_ov7670_registers_n_18
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_ov7670_controller_0_0 is
port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_ov7670_controller_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_ov7670_controller_0_0 : entity is "system_ov7670_controller_0_0,ov7670_controller,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_ov7670_controller_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_ov7670_controller_0_0 : entity is "ov7670_controller,Vivado 2016.4";
end system_ov7670_controller_0_0;
architecture STRUCTURE of system_ov7670_controller_0_0 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
pwdn <= \<const0>\;
reset <= \<const1>\;
xclk <= 'Z';
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.system_ov7670_controller_0_0_ov7670_controller
port map (
clk => clk,
config_finished => config_finished,
resend => resend,
sioc => sioc,
siod => siod
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
end STRUCTURE;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_debounce_0_0/system_debounce_0_0_stub.vhdl
|
1
|
1328
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:18:26 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_debounce_0_0/system_debounce_0_0_stub.vhdl
-- Design : system_debounce_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_debounce_0_0 is
Port (
clk : in STD_LOGIC;
signal_in : in STD_LOGIC;
signal_out : out STD_LOGIC
);
end system_debounce_0_0;
architecture stub of system_debounce_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,signal_in,signal_out";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "debounce,Vivado 2016.4";
begin
end;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_vga_buffer_1_0/system_vga_buffer_1_0_sim_netlist.vhdl
|
1
|
13896
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed May 24 17:28:31 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_vga_buffer_1_0 -prefix
-- system_vga_buffer_1_0_ system_vga_buffer_1_0_sim_netlist.vhdl
-- Design : system_vga_buffer_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_buffer_1_0_vga_buffer is
port (
data_r : out STD_LOGIC_VECTOR ( 23 downto 0 );
clk_w : in STD_LOGIC;
clk_r : in STD_LOGIC;
wen : in STD_LOGIC;
data_w : in STD_LOGIC_VECTOR ( 23 downto 0 );
x_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
end system_vga_buffer_1_0_vga_buffer;
architecture STRUCTURE of system_vga_buffer_1_0_vga_buffer is
signal addr_r : STD_LOGIC_VECTOR ( 9 downto 0 );
signal addr_w : STD_LOGIC_VECTOR ( 9 downto 0 );
signal c_addr_r : STD_LOGIC_VECTOR ( 9 downto 0 );
signal c_addr_w : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_data_reg_CASCADEOUTA_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_CASCADEOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_DBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_INJECTDBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_INJECTSBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_SBITERR_UNCONNECTED : STD_LOGIC;
signal NLW_data_reg_DOADO_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_data_reg_DOBDO_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 24 );
signal NLW_data_reg_DOPADOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_data_reg_DOPBDOP_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_data_reg_ECCPARITY_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_data_reg_RDADDRECC_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of data_reg : label is "INDEPENDENT";
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTA.DATA_BIT_LAYOUT\ of data_reg : label is "p0_d24";
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ : string;
attribute \MEM.PORTB.DATA_BIT_LAYOUT\ of data_reg : label is "p0_d24";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of data_reg : label is "{SYNTH-6 {cell *THIS*}}";
attribute RTL_RAM_BITS : integer;
attribute RTL_RAM_BITS of data_reg : label is 24576;
attribute RTL_RAM_NAME : string;
attribute RTL_RAM_NAME of data_reg : label is "data";
attribute bram_addr_begin : integer;
attribute bram_addr_begin of data_reg : label is 0;
attribute bram_addr_end : integer;
attribute bram_addr_end of data_reg : label is 1023;
attribute bram_slice_begin : integer;
attribute bram_slice_begin of data_reg : label is 0;
attribute bram_slice_end : integer;
attribute bram_slice_end of data_reg : label is 23;
begin
\addr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(0),
Q => addr_r(0),
R => '0'
);
\addr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(1),
Q => addr_r(1),
R => '0'
);
\addr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(2),
Q => addr_r(2),
R => '0'
);
\addr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(3),
Q => addr_r(3),
R => '0'
);
\addr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(4),
Q => addr_r(4),
R => '0'
);
\addr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(5),
Q => addr_r(5),
R => '0'
);
\addr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(6),
Q => addr_r(6),
R => '0'
);
\addr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(7),
Q => addr_r(7),
R => '0'
);
\addr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(8),
Q => addr_r(8),
R => '0'
);
\addr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => c_addr_r(9),
Q => addr_r(9),
R => '0'
);
\addr_w_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(0),
Q => addr_w(0),
R => '0'
);
\addr_w_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(1),
Q => addr_w(1),
R => '0'
);
\addr_w_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(2),
Q => addr_w(2),
R => '0'
);
\addr_w_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(3),
Q => addr_w(3),
R => '0'
);
\addr_w_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(4),
Q => addr_w(4),
R => '0'
);
\addr_w_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(5),
Q => addr_w(5),
R => '0'
);
\addr_w_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(6),
Q => addr_w(6),
R => '0'
);
\addr_w_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(7),
Q => addr_w(7),
R => '0'
);
\addr_w_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(8),
Q => addr_w(8),
R => '0'
);
\addr_w_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => c_addr_w(9),
Q => addr_w(9),
R => '0'
);
\c_addr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(0),
Q => c_addr_r(0),
R => '0'
);
\c_addr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(1),
Q => c_addr_r(1),
R => '0'
);
\c_addr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(2),
Q => c_addr_r(2),
R => '0'
);
\c_addr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(3),
Q => c_addr_r(3),
R => '0'
);
\c_addr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(4),
Q => c_addr_r(4),
R => '0'
);
\c_addr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(5),
Q => c_addr_r(5),
R => '0'
);
\c_addr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(6),
Q => c_addr_r(6),
R => '0'
);
\c_addr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(7),
Q => c_addr_r(7),
R => '0'
);
\c_addr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(8),
Q => c_addr_r(8),
R => '0'
);
\c_addr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_r,
CE => '1',
D => x_addr_r(9),
Q => c_addr_r(9),
R => '0'
);
\c_addr_w_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(0),
Q => c_addr_w(0),
R => '0'
);
\c_addr_w_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(1),
Q => c_addr_w(1),
R => '0'
);
\c_addr_w_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(2),
Q => c_addr_w(2),
R => '0'
);
\c_addr_w_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(3),
Q => c_addr_w(3),
R => '0'
);
\c_addr_w_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(4),
Q => c_addr_w(4),
R => '0'
);
\c_addr_w_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(5),
Q => c_addr_w(5),
R => '0'
);
\c_addr_w_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(6),
Q => c_addr_w(6),
R => '0'
);
\c_addr_w_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(7),
Q => c_addr_w(7),
R => '0'
);
\c_addr_w_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(8),
Q => c_addr_w(8),
R => '0'
);
\c_addr_w_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk_w,
CE => wen,
D => x_addr_w(9),
Q => c_addr_w(9),
R => '0'
);
data_reg: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INIT_A => X"000000000",
INIT_B => X"000000000",
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "RSTREG",
RSTREG_PRIORITY_B => "RSTREG",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "NO_CHANGE",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addr_w(9 downto 0),
ADDRARDADDR(4 downto 0) => B"11111",
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 5) => addr_r(9 downto 0),
ADDRBWRADDR(4 downto 0) => B"11111",
CASCADEINA => '1',
CASCADEINB => '1',
CASCADEOUTA => NLW_data_reg_CASCADEOUTA_UNCONNECTED,
CASCADEOUTB => NLW_data_reg_CASCADEOUTB_UNCONNECTED,
CLKARDCLK => clk_w,
CLKBWRCLK => clk_r,
DBITERR => NLW_data_reg_DBITERR_UNCONNECTED,
DIADI(31 downto 24) => B"00000000",
DIADI(23 downto 0) => data_w(23 downto 0),
DIBDI(31 downto 0) => B"00000000111111111111111111111111",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 0) => NLW_data_reg_DOADO_UNCONNECTED(31 downto 0),
DOBDO(31 downto 24) => NLW_data_reg_DOBDO_UNCONNECTED(31 downto 24),
DOBDO(23 downto 0) => data_r(23 downto 0),
DOPADOP(3 downto 0) => NLW_data_reg_DOPADOP_UNCONNECTED(3 downto 0),
DOPBDOP(3 downto 0) => NLW_data_reg_DOPBDOP_UNCONNECTED(3 downto 0),
ECCPARITY(7 downto 0) => NLW_data_reg_ECCPARITY_UNCONNECTED(7 downto 0),
ENARDEN => wen,
ENBWREN => '1',
INJECTDBITERR => NLW_data_reg_INJECTDBITERR_UNCONNECTED,
INJECTSBITERR => NLW_data_reg_INJECTSBITERR_UNCONNECTED,
RDADDRECC(8 downto 0) => NLW_data_reg_RDADDRECC_UNCONNECTED(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => NLW_data_reg_SBITERR_UNCONNECTED,
WEA(3 downto 0) => B"1111",
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_buffer_1_0 is
port (
clk_w : in STD_LOGIC;
clk_r : in STD_LOGIC;
wen : in STD_LOGIC;
x_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_w : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_r : in STD_LOGIC_VECTOR ( 9 downto 0 );
data_w : in STD_LOGIC_VECTOR ( 23 downto 0 );
data_r : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_buffer_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_buffer_1_0 : entity is "system_vga_buffer_1_0,vga_buffer,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_buffer_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_buffer_1_0 : entity is "vga_buffer,Vivado 2016.4";
end system_vga_buffer_1_0;
architecture STRUCTURE of system_vga_buffer_1_0 is
begin
U0: entity work.system_vga_buffer_1_0_vga_buffer
port map (
clk_r => clk_r,
clk_w => clk_w,
data_r(23 downto 0) => data_r(23 downto 0),
data_w(23 downto 0) => data_w(23 downto 0),
wen => wen,
x_addr_r(9 downto 0) => x_addr_r(9 downto 0),
x_addr_w(9 downto 0) => x_addr_w(9 downto 0)
);
end STRUCTURE;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_debounce_0_0/sim/system_debounce_0_0.vhd
|
4
|
3181
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:debounce:1.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_debounce_0_0 IS
PORT (
clk : IN STD_LOGIC;
signal_in : IN STD_LOGIC;
signal_out : OUT STD_LOGIC
);
END system_debounce_0_0;
ARCHITECTURE system_debounce_0_0_arch OF system_debounce_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_debounce_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT debounce IS
PORT (
clk : IN STD_LOGIC;
signal_in : IN STD_LOGIC;
signal_out : OUT STD_LOGIC
);
END COMPONENT debounce;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : debounce
PORT MAP (
clk => clk,
signal_in => signal_in,
signal_out => signal_out
);
END system_debounce_0_0_arch;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ipshared/e67f/ov7670_controller.vhd
|
2
|
2552
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: Controller for the OV760 camera - transfers registers to the
-- camera over an I2C like bus
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ov7670_controller is
port(
clk: in std_logic;
resend: in std_logic;
config_finished : out std_logic;
sioc: out std_logic;
siod: inout std_logic;
reset: out std_logic;
pwdn: out std_logic;
xclk: out std_logic
);
end ov7670_controller;
architecture Structural of ov7670_controller is
component ov7670_registers is
port(
clk: in std_logic;
resend: in std_logic;
advance: in std_logic;
command: out std_logic_vector(15 downto 0);
finished: out std_logic
);
end component;
component i2c_sender is
port (
clk: in std_logic;
siod: inout std_logic;
sioc: out std_logic;
taken: out std_logic;
send: in std_logic;
id: in std_logic_vector(7 downto 0);
reg: in std_logic_vector(7 downto 0);
value: in std_logic_vector(7 downto 0)
);
end component;
signal sys_clk : std_logic := '0';
signal command : std_logic_vector(15 downto 0);
signal finished : std_logic := '0';
signal taken : std_logic := '0';
signal send : std_logic;
constant camera_address : std_logic_vector(7 downto 0) := x"42"; -- 42"; -- Device write ID - see top of page 11 of data sheet
begin
config_finished <= finished;
send <= not finished;
Inst_i2c_sender: i2c_sender port map(
clk => clk,
taken => taken,
siod => siod,
sioc => sioc,
send => send,
id => camera_address,
reg => command(15 downto 8),
value => command(7 downto 0)
);
reset <= '1'; -- Normal mode
pwdn <= '0'; -- Power device up
xclk <= sys_clk;
Inst_ov7670_registers: ov7670_registers port map(
clk => clk,
advance => taken,
command => command,
finished => finished,
resend => resend
);
process(clk)
begin
if rising_edge(clk) then
sys_clk <= not sys_clk;
end if;
end process;
end Structural;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ipshared/e67f/ov7670_controller.vhd
|
2
|
2552
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: Controller for the OV760 camera - transfers registers to the
-- camera over an I2C like bus
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ov7670_controller is
port(
clk: in std_logic;
resend: in std_logic;
config_finished : out std_logic;
sioc: out std_logic;
siod: inout std_logic;
reset: out std_logic;
pwdn: out std_logic;
xclk: out std_logic
);
end ov7670_controller;
architecture Structural of ov7670_controller is
component ov7670_registers is
port(
clk: in std_logic;
resend: in std_logic;
advance: in std_logic;
command: out std_logic_vector(15 downto 0);
finished: out std_logic
);
end component;
component i2c_sender is
port (
clk: in std_logic;
siod: inout std_logic;
sioc: out std_logic;
taken: out std_logic;
send: in std_logic;
id: in std_logic_vector(7 downto 0);
reg: in std_logic_vector(7 downto 0);
value: in std_logic_vector(7 downto 0)
);
end component;
signal sys_clk : std_logic := '0';
signal command : std_logic_vector(15 downto 0);
signal finished : std_logic := '0';
signal taken : std_logic := '0';
signal send : std_logic;
constant camera_address : std_logic_vector(7 downto 0) := x"42"; -- 42"; -- Device write ID - see top of page 11 of data sheet
begin
config_finished <= finished;
send <= not finished;
Inst_i2c_sender: i2c_sender port map(
clk => clk,
taken => taken,
siod => siod,
sioc => sioc,
send => send,
id => camera_address,
reg => command(15 downto 8),
value => command(7 downto 0)
);
reset <= '1'; -- Normal mode
pwdn <= '0'; -- Power device up
xclk <= sys_clk;
Inst_ov7670_registers: ov7670_registers port map(
clk => clk,
advance => taken,
command => command,
finished => finished,
resend => resend
);
process(clk)
begin
if rising_edge(clk) then
sys_clk <= not sys_clk;
end if;
end process;
end Structural;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
video_ip/rgb888_mux_2/rgb888_mux_2.srcs/sources_1/new/rgb888_mux_2.vhd
|
2
|
615
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity rgb888_mux_2 is
port (
clk : in std_logic;
sel : in std_logic;
rgb888_0 : in std_logic_vector(23 downto 0);
rgb888_1 : in std_logic_vector(23 downto 0);
rgb888 : out std_logic_vector(23 downto 0)
);
end rgb888_mux_2;
architecture Behavioral of rgb888_mux_2 is
begin
process(clk)
begin
if rising_edge(clk) then
if sel = '0' then
rgb888 <= rgb888_0;
else
rgb888 <= rgb888_1;
end if;
end if;
end process;
end Behavioral;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ipshared/7279/vga_buffer.vhd
|
6
|
1583
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity vga_buffer is
generic (
SIZE_POW2 : integer := 6
);
port (
clk_w : in std_logic;
clk_r : in std_logic;
wen : in std_logic;
x_addr_w : in std_logic_vector(9 downto 0);
y_addr_w : in std_logic_vector(9 downto 0);
x_addr_r : in std_logic_vector(9 downto 0);
y_addr_r : in std_logic_vector(9 downto 0);
data_w : in std_logic_vector(23 downto 0);
data_r : out std_logic_vector(23 downto 0)
);
end vga_buffer;
architecture Behavioral of vga_buffer is
type DATA_BUFFER is array (2**SIZE_POW2 - 1 downto 0) of std_logic_vector(23 downto 0);
signal data : DATA_BUFFER;
signal c_addr_w, c_addr_r : std_logic_vector(19 downto 0);
signal addr_w, addr_r : std_logic_vector(SIZE_POW2 - 1 downto 0);
begin
process(clk_w)
begin
if rising_edge(clk_w) then
if wen = '1' then
c_addr_w(9 downto 0) <= x_addr_w;
c_addr_w(19 downto 10) <= y_addr_w;
addr_w <= c_addr_w(SIZE_POW2 - 1 downto 0);
data(to_integer(unsigned(addr_w))) <= data_w;
end if;
end if;
end process;
process(clk_r)
begin
if rising_edge(clk_r) then
c_addr_r(9 downto 0) <= x_addr_r;
c_addr_r(19 downto 10) <= y_addr_r;
addr_r <= c_addr_r(SIZE_POW2 - 1 downto 0);
data_r <= data(to_integer(unsigned(addr_r)));
end if;
end process;
end Behavioral;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
video_ip/vga_buffer/vga_buffer.srcs/sources_1/new/vga_buffer.vhd
|
6
|
1583
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity vga_buffer is
generic (
SIZE_POW2 : integer := 6
);
port (
clk_w : in std_logic;
clk_r : in std_logic;
wen : in std_logic;
x_addr_w : in std_logic_vector(9 downto 0);
y_addr_w : in std_logic_vector(9 downto 0);
x_addr_r : in std_logic_vector(9 downto 0);
y_addr_r : in std_logic_vector(9 downto 0);
data_w : in std_logic_vector(23 downto 0);
data_r : out std_logic_vector(23 downto 0)
);
end vga_buffer;
architecture Behavioral of vga_buffer is
type DATA_BUFFER is array (2**SIZE_POW2 - 1 downto 0) of std_logic_vector(23 downto 0);
signal data : DATA_BUFFER;
signal c_addr_w, c_addr_r : std_logic_vector(19 downto 0);
signal addr_w, addr_r : std_logic_vector(SIZE_POW2 - 1 downto 0);
begin
process(clk_w)
begin
if rising_edge(clk_w) then
if wen = '1' then
c_addr_w(9 downto 0) <= x_addr_w;
c_addr_w(19 downto 10) <= y_addr_w;
addr_w <= c_addr_w(SIZE_POW2 - 1 downto 0);
data(to_integer(unsigned(addr_w))) <= data_w;
end if;
end if;
end process;
process(clk_r)
begin
if rising_edge(clk_r) then
c_addr_r(9 downto 0) <= x_addr_r;
c_addr_r(19 downto 10) <= y_addr_r;
addr_r <= c_addr_r(SIZE_POW2 - 1 downto 0);
data_r <= data(to_integer(unsigned(addr_r)));
end if;
end process;
end Behavioral;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_zed_vga_0_0/synth/system_zed_vga_0_0.vhd
|
2
|
3842
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:zed_vga:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_zed_vga_0_0 IS
PORT (
rgb565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
vga_r : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_g : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END system_zed_vga_0_0;
ARCHITECTURE system_zed_vga_0_0_arch OF system_zed_vga_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_zed_vga_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT zed_vga IS
PORT (
rgb565 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
vga_r : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_g : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
vga_b : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT zed_vga;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_zed_vga_0_0_arch: ARCHITECTURE IS "zed_vga,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_zed_vga_0_0_arch : ARCHITECTURE IS "system_zed_vga_0_0,zed_vga,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_zed_vga_0_0_arch: ARCHITECTURE IS "system_zed_vga_0_0,zed_vga,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=zed_vga,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : zed_vga
PORT MAP (
rgb565 => rgb565,
vga_r => vga_r,
vga_g => vga_g,
vga_b => vga_b
);
END system_zed_vga_0_0_arch;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_0_0/system_rgb565_to_rgb888_0_0_stub.vhdl
|
3
|
1432
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:17:13 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_0_0/system_rgb565_to_rgb888_0_0_stub.vhdl
-- Design : system_rgb565_to_rgb888_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_rgb565_to_rgb888_0_0 is
Port (
clk : in STD_LOGIC;
rgb_565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rgb_888 : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end system_rgb565_to_rgb888_0_0;
architecture stub of system_rgb565_to_rgb888_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,rgb_565[15:0],rgb_888[23:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "rgb565_to_rgb888,Vivado 2016.4";
begin
end;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_inverter_1_0/sim/system_inverter_1_0.vhd
|
3
|
2934
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:inverter:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_inverter_1_0 IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END system_inverter_1_0;
ARCHITECTURE system_inverter_1_0_arch OF system_inverter_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_inverter_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT inverter IS
PORT (
x : IN STD_LOGIC;
x_not : OUT STD_LOGIC
);
END COMPONENT inverter;
BEGIN
U0 : inverter
PORT MAP (
x => x,
x_not => x_not
);
END system_inverter_1_0_arch;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_ov7670_vga_0_1/synth/system_ov7670_vga_0_1.vhd
|
1
|
3723
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ov7670_vga:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_ov7670_vga_0_1 IS
PORT (
pclk : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END system_ov7670_vga_0_1;
ARCHITECTURE system_ov7670_vga_0_1_arch OF system_ov7670_vga_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ov7670_vga_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT ov7670_vga IS
PORT (
pclk : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
rgb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT ov7670_vga;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_ov7670_vga_0_1_arch: ARCHITECTURE IS "ov7670_vga,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_ov7670_vga_0_1_arch : ARCHITECTURE IS "system_ov7670_vga_0_1,ov7670_vga,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_ov7670_vga_0_1_arch: ARCHITECTURE IS "system_ov7670_vga_0_1,ov7670_vga,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=ov7670_vga,x_ipVersion=1.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : ov7670_vga
PORT MAP (
pclk => pclk,
data => data,
rgb => rgb
);
END system_ov7670_vga_0_1_arch;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/dma_example/dma_example.srcs/sources_1/bd/system/hdl/system_wrapper.vhd
|
1
|
3442
|
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Wed May 31 20:09:36 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system_wrapper.bd
--Design : system_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC
);
end system_wrapper;
architecture STRUCTURE of system_wrapper is
component system is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC
);
end component system;
begin
system_i: component system
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb
);
end STRUCTURE;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_processing_system7_0_0/system_processing_system7_0_0_stub.vhdl
|
1
|
5580
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 07:04:01 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_processing_system7_0_0 -prefix
-- system_processing_system7_0_0_ system_processing_system7_0_0_stub.vhdl
-- Design : system_processing_system7_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_processing_system7_0_0 is
Port (
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end system_processing_system7_0_0;
architecture stub of system_processing_system7_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2016.4";
begin
end;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/hdl/affine_block_wrapper.vhd
|
2
|
2020
|
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Mon Feb 20 13:51:56 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target affine_block_wrapper.bd
--Design : affine_block_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity affine_block_wrapper is
port (
a00 : in STD_LOGIC_VECTOR ( 31 downto 0 );
a01 : in STD_LOGIC_VECTOR ( 31 downto 0 );
a10 : in STD_LOGIC_VECTOR ( 31 downto 0 );
a11 : in STD_LOGIC_VECTOR ( 31 downto 0 );
x_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
y_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_out : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end affine_block_wrapper;
architecture STRUCTURE of affine_block_wrapper is
component affine_block is
port (
x_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
a00 : in STD_LOGIC_VECTOR ( 31 downto 0 );
a01 : in STD_LOGIC_VECTOR ( 31 downto 0 );
a10 : in STD_LOGIC_VECTOR ( 31 downto 0 );
a11 : in STD_LOGIC_VECTOR ( 31 downto 0 );
x_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
y_out : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component affine_block;
begin
affine_block_i: component affine_block
port map (
a00(31 downto 0) => a00(31 downto 0),
a01(31 downto 0) => a01(31 downto 0),
a10(31 downto 0) => a10(31 downto 0),
a11(31 downto 0) => a11(31 downto 0),
x_in(9 downto 0) => x_in(9 downto 0),
x_out(9 downto 0) => x_out(9 downto 0),
y_in(9 downto 0) => y_in(9 downto 0),
y_out(9 downto 0) => y_out(9 downto 0)
);
end STRUCTURE;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/affine_transform_demo/affine_transform_demo.srcs/sources_1/bd/system/ipshared/dbde/hdl/affine_block_wrapper.vhd
|
2
|
2020
|
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Mon Feb 20 13:51:56 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target affine_block_wrapper.bd
--Design : affine_block_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity affine_block_wrapper is
port (
a00 : in STD_LOGIC_VECTOR ( 31 downto 0 );
a01 : in STD_LOGIC_VECTOR ( 31 downto 0 );
a10 : in STD_LOGIC_VECTOR ( 31 downto 0 );
a11 : in STD_LOGIC_VECTOR ( 31 downto 0 );
x_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
y_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_out : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end affine_block_wrapper;
architecture STRUCTURE of affine_block_wrapper is
component affine_block is
port (
x_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
a00 : in STD_LOGIC_VECTOR ( 31 downto 0 );
a01 : in STD_LOGIC_VECTOR ( 31 downto 0 );
a10 : in STD_LOGIC_VECTOR ( 31 downto 0 );
a11 : in STD_LOGIC_VECTOR ( 31 downto 0 );
x_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
y_out : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component affine_block;
begin
affine_block_i: component affine_block
port map (
a00(31 downto 0) => a00(31 downto 0),
a01(31 downto 0) => a01(31 downto 0),
a10(31 downto 0) => a10(31 downto 0),
a11(31 downto 0) => a11(31 downto 0),
x_in(9 downto 0) => x_in(9 downto 0),
x_out(9 downto 0) => x_out(9 downto 0),
y_in(9 downto 0) => y_in(9 downto 0),
y_out(9 downto 0) => y_out(9 downto 0)
);
end STRUCTURE;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
general_ip/buffer_register/buffer_register.srcs/sources_1/new/buffer_register.vhd
|
4
|
583
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity buffer_register is
generic (
WIDTH : integer := 32
);
port (
clk : in std_logic;
val_in : in std_logic_vector(WIDTH - 1 downto 0);
val_out : out std_logic_vector(WIDTH - 1 downto 0)
);
end buffer_register;
architecture Behavioral of buffer_register is
begin
process(clk)
variable reg : std_logic_vector(WIDTH - 1 downto 0);
begin
if rising_edge(clk) then
reg := val_in;
val_out <= reg;
end if;
end process;
end Behavioral;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/hdl/system_wrapper.vhd
|
1
|
4756
|
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Mon Feb 27 19:47:32 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system_wrapper.bd
--Design : system_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
config_finished : out STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
hdmi_cec : in STD_LOGIC;
hdmi_hpd : in STD_LOGIC;
hdmi_out_en : out STD_LOGIC;
href : in STD_LOGIC;
pclk : in STD_LOGIC;
resend : in STD_LOGIC;
scl : out STD_LOGIC;
sda : inout STD_LOGIC;
tmds : out STD_LOGIC_VECTOR ( 3 downto 0 );
tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 );
vsync : in STD_LOGIC;
xclk : out STD_LOGIC
);
end system_wrapper;
architecture STRUCTURE of system_wrapper is
component system is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
pclk : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
hdmi_cec : in STD_LOGIC;
hdmi_hpd : in STD_LOGIC;
tmds : out STD_LOGIC_VECTOR ( 3 downto 0 );
tmdsb : out STD_LOGIC_VECTOR ( 3 downto 0 );
hdmi_out_en : out STD_LOGIC;
href : in STD_LOGIC;
vsync : in STD_LOGIC;
scl : out STD_LOGIC;
sda : inout STD_LOGIC;
xclk : out STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC
);
end component system;
begin
system_i: component system
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
config_finished => config_finished,
data(7 downto 0) => data(7 downto 0),
hdmi_cec => hdmi_cec,
hdmi_hpd => hdmi_hpd,
hdmi_out_en => hdmi_out_en,
href => href,
pclk => pclk,
resend => resend,
scl => scl,
sda => sda,
tmds(3 downto 0) => tmds(3 downto 0),
tmdsb(3 downto 0) => tmdsb(3 downto 0),
vsync => vsync,
xclk => xclk
);
end STRUCTURE;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ipshared/b35a/rgb888_to_g8.vhd
|
5
|
711
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity rgb888_to_g8 is
port (
clk : in std_logic;
rgb888 : in std_logic_vector(23 downto 0);
g8 : out std_logic_vector(7 downto 0)
);
end rgb888_to_g8;
architecture Behavioral of rgb888_to_g8 is
begin
process(clk)
variable r, g, b : integer := 0;
begin
if rising_edge(clk) then
r := to_integer(unsigned(rgb888(23 downto 16)));
g := to_integer(unsigned(rgb888(15 downto 8)));
b := to_integer(unsigned(rgb888(7 downto 0)));
g8 <= std_logic_vector(to_unsigned((r + g + b)/3, 8));
end if;
end process;
end Behavioral;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_vga_buffer_0_0/sim/system_vga_buffer_0_0.vhd
|
4
|
4004
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_buffer:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_buffer_0_0 IS
PORT (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
wen : IN STD_LOGIC;
x_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
data_w : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
data_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_buffer_0_0;
ARCHITECTURE system_vga_buffer_0_0_arch OF system_vga_buffer_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_buffer_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_buffer IS
GENERIC (
SIZE_POW2 : INTEGER
);
PORT (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
wen : IN STD_LOGIC;
x_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
data_w : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
data_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_buffer;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk_w: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : vga_buffer
GENERIC MAP (
SIZE_POW2 => 10
)
PORT MAP (
clk_w => clk_w,
clk_r => clk_r,
wen => wen,
x_addr_w => x_addr_w,
y_addr_w => y_addr_w,
x_addr_r => x_addr_r,
y_addr_r => y_addr_r,
data_w => data_w,
data_r => data_r
);
END system_vga_buffer_0_0_arch;
|
mit
|
ashikpoojari/Hardware-Security
|
DES CryptoCore/src/test_benches/DES_Encrypt_Testbench.vhd
|
2
|
5647
|
--******************************************************************************
-- Copyright (c) 2016 Vinayaka Jyothi
-- All rights reserved.
--
-- Permission is hereby granted, free of charge, to any person obtaining
-- a copy of this software and associated documentation files (the
-- "Software"), to deal in the Software without restriction, including
-- without limitation the rights to use, copy, modify, merge, publish,
-- distribute, sublicense, and/or sell copies of the Software, and to
-- permit persons to whom the Software is furnished to do so, subject
-- to the following conditions:
--
-- The above copyright notice and this permission notice shall be
-- included in all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-- OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
-- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
-- HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
-- WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-- DEALINGS IN THE SOFTWARE.
--******************************************************************************
--------------------------------------------------------------------------------
-- Company: VNIE ENTITIES
-- Designer: Vinayaka Jyothi
--
-- Create Date: 20:45:11 02/14/2017
-- Design Name:
-- Module Name: DES_ENCRYPT Testbench.vhd
-- Project Name: DES_Fully_Pipelined
-- Target Device:
-- Tool versions:
-- Description:
--
--
-- Dependencies: DES_Fully_Pipelined Design and txt_util.vhd
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
--------------------------------------------------------------------------------
LIBRARY ieee;
Use std.textio.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;
use work.txt_util.all;
ENTITY DES_testBench IS
END DES_testBench;
ARCHITECTURE behavior OF DES_testBench IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT DES_CRYPTO_CORE --desCryptoCore
PORT(
reset : IN std_logic;
EN : IN std_logic;
clk : IN std_logic;
DES_IN : IN std_logic_vector(63 downto 0);
USER_KEY : IN std_logic_vector(63 downto 0);
DES_OUT : OUT std_logic_vector(63 downto 0)
);
END COMPONENT;
COMPONENT DES IS
PORT(
PT : IN STD_LOGIC_VECTOR (63 DOWNTO 0);
KIN: IN STD_LOGIC_VECTOR (63 DOWNTO 0);
CT: OUT STD_LOGIC_VECTOR (63 DOWNTO 0);
RST: IN STD_LOGIC;
CLK: IN STD_LOGIC;
TEST_MODE: IN STD_LOGIC;
SCAN_OUT : OUT STD_LOGIC);
END COMPONENT;
--Inputs
signal reset : std_logic := '0';
signal EN : std_logic := '0';
signal clk : std_logic := '0';
signal DES_IN : std_logic_vector(63 downto 0) := (others => '0');
signal USER_KEY : std_logic_vector(63 downto 0) := (others => '0');
--Outputs
signal DES_OUT : std_logic_vector(63 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
signal ERROR,ERRORD: integer :=0;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: DES_CRYPTO_CORE PORT MAP (
reset => reset,
EN => EN,
clk => clk,
DES_IN => DES_IN,
USER_KEY => USER_KEY,
DES_OUT => DES_OUT
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
readcmd: process
file CryptoCore_TestVectors: TEXT;
variable file_line: Line;
variable test_vector_key_in: std_logic_vector (63 downto 0);
variable test_vector_din: std_logic_vector (63 downto 0);
variable test_vector_expected_dout : std_logic_vector (63 downto 0);
Begin
reset <= '1';
USER_KEY <= (others => '0');
DES_IN <= (others => '0');
En <= '1';
wait for 100*clk_period;
reset <= '0';
wait until rising_edge (clk);
reset <= '0';
wait for 100*clk_period;
reset <= '0';
wait until rising_edge (clk);
print ("DES Test#1 has begun.");
FILE_OPEN (CryptoCore_TestVectors, "../src/test_vectors/DES_TV_Triplets_NBS.txt", READ_MODE); --In case of problems, use absolute path
loop
If endfile (CryptoCore_TestVectors) then
exit;
End If;
readline (CryptoCore_TestVectors, file_line);
hread (file_line, test_vector_key_in);
hread (file_line, test_vector_din);
hread (file_line, test_vector_expected_dout);
USER_KEY <= test_vector_key_in;
-- din_vld_T <= '1'; --# When Designs have din and key valid use this
-- Key_vld <= '1';
DES_IN <= test_vector_din;
wait until rising_edge (clk);
-- din_vld_T <= '0';
-- wait until dout_rdy_T = '1'; --# When Designs have dout use this to get the result
wait for 20*clk_period; -- Currently DES takes 19 clock cycles to complete processing
wait until rising_edge (clk);
If DES_OUT /= test_vector_expected_dout then
print ("***ERROR: test vector failed to compare"); ERROR<=ERROR+1;
print ((" Expected PT: ") & hstr (test_vector_expected_dout (63 downto 0)) & (" Received PT: ") & hstr (DES_OUT (63 downto 0)));
End If;
End loop;
print ("Test#1 completed");
print ("");
print ("");
if ERROR=0 then
print ("All tests complete- PASS");
else
print (("All tests complete 4 Decrypt - FAIL --> Total ERRORS=") & integer'image(ERROR));
end if;
wait;
end process;
END;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ip/system_ov7670_controller_0_0/sim/system_ov7670_controller_0_0.vhd
|
5
|
3747
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ov7670_controller:1.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_ov7670_controller_0_0 IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END system_ov7670_controller_0_0;
ARCHITECTURE system_ov7670_controller_0_0_arch OF system_ov7670_controller_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ov7670_controller_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT ov7670_controller IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END COMPONENT ov7670_controller;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
BEGIN
U0 : ov7670_controller
PORT MAP (
clk => clk,
resend => resend,
config_finished => config_finished,
sioc => sioc,
siod => siod,
reset => reset,
pwdn => pwdn,
xclk => xclk
);
END system_ov7670_controller_0_0_arch;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_hdmi_test/zed_hdmi_test.srcs/sources_1/bd/system/ipshared/92f0/vga_color_test.vhd
|
8
|
3633
|
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: vga_color_test - Structural
-- Description: Generate a color test pattern
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga_color_test is
generic(
H_SIZE : integer := 640;
V_SIZE : integer := 480
);
port(
clk_25 : in std_logic;
xaddr : in std_logic_vector(9 downto 0);
yaddr : in std_logic_vector(9 downto 0);
rgb : out std_logic_vector(23 downto 0)
);
end vga_color_test;
architecture Structural of vga_color_test is
constant WHITE : std_logic_vector(23 downto 0) := x"FFFFFF";
constant BLACK : std_logic_vector(23 downto 0) := x"000000";
constant YELLOW : std_logic_vector(23 downto 0) := x"FFFF00";
constant CYAN : std_logic_vector(23 downto 0) := x"00FFFF";
constant GREEN : std_logic_vector(23 downto 0) := x"00FF00";
constant PINK : std_logic_vector(23 downto 0) := x"FF00FF";
constant RED : std_logic_vector(23 downto 0) := x"FF0000";
constant BLUE : std_logic_vector(23 downto 0) := x"0000FF";
constant DARK_BLUE : std_logic_vector(23 downto 0) := x"0000A0";
constant GRAY : std_logic_vector(23 downto 0) := x"808080";
constant LIGHT_GRAY : std_logic_vector(23 downto 0) := x"C0C0C0";
constant PURPLE : std_logic_vector(23 downto 0) := x"8000FF";
begin
process(clk_25)
variable x,y : integer;
begin
if rising_edge(clk_25) then
x := to_integer(unsigned(xaddr));
y := to_integer(unsigned(yaddr));
if y < (V_SIZE*2)/3 then
if x < (H_SIZE)/7 then
rgb <= WHITE;
elsif x < (H_SIZE*2)/7 then
rgb <= YELLOW;
elsif x < (H_SIZE*3)/7 then
rgb <= CYAN;
elsif x < (H_SIZE*4)/7 then
rgb <= GREEN;
elsif x < (H_SIZE*5)/7 then
rgb <= PINK;
elsif x < (H_SIZE*6)/7 then
rgb <= RED;
else
rgb <= BLUE;
end if;
elsif y < (V_SIZE*3)/4 then
if x < (H_SIZE)/7 then
rgb <= BLUE;
elsif x < (H_SIZE*2)/7 then
rgb <= BLACK;
elsif x < (H_SIZE*3)/7 then
rgb <= PINK;
elsif x < (H_SIZE*4)/7 then
rgb <= GRAY;
elsif x < (H_SIZE*5)/7 then
rgb <= CYAN;
elsif x < (H_SIZE*6)/7 then
rgb <= GRAY;
else
rgb <= WHITE;
end if;
else
if x < (H_SIZE)/6 then
rgb <= DARK_BLUE;
elsif x < (H_SIZE*2)/6 then
rgb <= WHITE;
elsif x < (H_SIZE*3)/6 then
rgb <= PURPLE;
elsif x < (H_SIZE*5)/7 then
rgb <= GRAY;
elsif x < (H_SIZE*6)/7 - (H_SIZE*2)/21 then
rgb <= BLACK;
elsif x < (H_SIZE*6)/7 - (H_SIZE)/21 then
rgb <= GRAY;
elsif x < (H_SIZE*6)/7 then
rgb <= LIGHT_GRAY;
else
rgb <= GRAY;
end if;
end if;
end if;
end process;
end Structural;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/video_gaussian_blur/video_gaussian_blur.srcs/sources_1/bd/system/ipshared/xilinx.com/vga_color_test_v1_0/vga_color_test.vhd
|
8
|
3633
|
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: vga_color_test - Structural
-- Description: Generate a color test pattern
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga_color_test is
generic(
H_SIZE : integer := 640;
V_SIZE : integer := 480
);
port(
clk_25 : in std_logic;
xaddr : in std_logic_vector(9 downto 0);
yaddr : in std_logic_vector(9 downto 0);
rgb : out std_logic_vector(23 downto 0)
);
end vga_color_test;
architecture Structural of vga_color_test is
constant WHITE : std_logic_vector(23 downto 0) := x"FFFFFF";
constant BLACK : std_logic_vector(23 downto 0) := x"000000";
constant YELLOW : std_logic_vector(23 downto 0) := x"FFFF00";
constant CYAN : std_logic_vector(23 downto 0) := x"00FFFF";
constant GREEN : std_logic_vector(23 downto 0) := x"00FF00";
constant PINK : std_logic_vector(23 downto 0) := x"FF00FF";
constant RED : std_logic_vector(23 downto 0) := x"FF0000";
constant BLUE : std_logic_vector(23 downto 0) := x"0000FF";
constant DARK_BLUE : std_logic_vector(23 downto 0) := x"0000A0";
constant GRAY : std_logic_vector(23 downto 0) := x"808080";
constant LIGHT_GRAY : std_logic_vector(23 downto 0) := x"C0C0C0";
constant PURPLE : std_logic_vector(23 downto 0) := x"8000FF";
begin
process(clk_25)
variable x,y : integer;
begin
if rising_edge(clk_25) then
x := to_integer(unsigned(xaddr));
y := to_integer(unsigned(yaddr));
if y < (V_SIZE*2)/3 then
if x < (H_SIZE)/7 then
rgb <= WHITE;
elsif x < (H_SIZE*2)/7 then
rgb <= YELLOW;
elsif x < (H_SIZE*3)/7 then
rgb <= CYAN;
elsif x < (H_SIZE*4)/7 then
rgb <= GREEN;
elsif x < (H_SIZE*5)/7 then
rgb <= PINK;
elsif x < (H_SIZE*6)/7 then
rgb <= RED;
else
rgb <= BLUE;
end if;
elsif y < (V_SIZE*3)/4 then
if x < (H_SIZE)/7 then
rgb <= BLUE;
elsif x < (H_SIZE*2)/7 then
rgb <= BLACK;
elsif x < (H_SIZE*3)/7 then
rgb <= PINK;
elsif x < (H_SIZE*4)/7 then
rgb <= GRAY;
elsif x < (H_SIZE*5)/7 then
rgb <= CYAN;
elsif x < (H_SIZE*6)/7 then
rgb <= GRAY;
else
rgb <= WHITE;
end if;
else
if x < (H_SIZE)/6 then
rgb <= DARK_BLUE;
elsif x < (H_SIZE*2)/6 then
rgb <= WHITE;
elsif x < (H_SIZE*3)/6 then
rgb <= PURPLE;
elsif x < (H_SIZE*5)/7 then
rgb <= GRAY;
elsif x < (H_SIZE*6)/7 - (H_SIZE*2)/21 then
rgb <= BLACK;
elsif x < (H_SIZE*6)/7 - (H_SIZE)/21 then
rgb <= GRAY;
elsif x < (H_SIZE*6)/7 then
rgb <= LIGHT_GRAY;
else
rgb <= GRAY;
end if;
end if;
end if;
end process;
end Structural;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_ov7670_controller_1_0/sim/system_ov7670_controller_1_0.vhd
|
2
|
3747
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ov7670_controller:1.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_ov7670_controller_1_0 IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END system_ov7670_controller_1_0;
ARCHITECTURE system_ov7670_controller_1_0_arch OF system_ov7670_controller_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ov7670_controller_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT ov7670_controller IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END COMPONENT ov7670_controller;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
BEGIN
U0 : ov7670_controller
PORT MAP (
clk => clk,
resend => resend,
config_finished => config_finished,
sioc => sioc,
siod => siod,
reset => reset,
pwdn => pwdn,
xclk => xclk
);
END system_ov7670_controller_1_0_arch;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ipshared/658b/ov7670_vga.vhd
|
2
|
1001
|
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Robert Taglang
--
-- Module Name: ov7670_vga - Structural
-- Description: The ov7670 can produce 8-bits of data - pclk runs two cycles to produce RGB565
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ov7670_vga is
port(
pclk : in std_logic;
data : in std_logic_vector(7 downto 0);
rgb : out std_logic_vector(15 downto 0)
);
end ov7670_vga;
architecture Structural of ov7670_vga is
begin
process(pclk)
variable cycle : std_logic := '0';
begin
if rising_edge(pclk) then
if cycle = '0' then
rgb(15 downto 8) <= data;
cycle := '1';
else
rgb(7 downto 0) <= data;
cycle := '0';
end if;
end if;
end process;
end Structural;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_buffer_register_0_0/synth/system_buffer_register_0_0.vhd
|
3
|
4059
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:buffer_register:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_buffer_register_0_0 IS
PORT (
clk : IN STD_LOGIC;
val_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
val_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_buffer_register_0_0;
ARCHITECTURE system_buffer_register_0_0_arch OF system_buffer_register_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_buffer_register_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT buffer_register IS
GENERIC (
WIDTH : INTEGER
);
PORT (
clk : IN STD_LOGIC;
val_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
val_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT buffer_register;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_buffer_register_0_0_arch: ARCHITECTURE IS "buffer_register,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_buffer_register_0_0_arch : ARCHITECTURE IS "system_buffer_register_0_0,buffer_register,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_buffer_register_0_0_arch: ARCHITECTURE IS "system_buffer_register_0_0,buffer_register,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=buffer_register,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,WIDTH=32}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : buffer_register
GENERIC MAP (
WIDTH => 32
)
PORT MAP (
clk => clk,
val_in => val_in,
val_out => val_out
);
END system_buffer_register_0_0_arch;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_inverter_0_0_1/system_inverter_0_0_stub.vhdl
|
1
|
1286
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 10:10:04 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_inverter_0_0_1/system_inverter_0_0_stub.vhdl
-- Design : system_inverter_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_inverter_0_0 is
Port (
x : in STD_LOGIC;
x_not : out STD_LOGIC
);
end system_inverter_0_0;
architecture stub of system_inverter_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "x,x_not";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "inverter,Vivado 2016.4";
begin
end;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/hdl/system_wrapper.vhd
|
1
|
2444
|
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Mon Jun 05 08:32:55 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system_wrapper.bd
--Design : system_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_wrapper is
port (
clk_100 : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
enable_nm : in STD_LOGIC;
hdmi_clk : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hsync : in STD_LOGIC;
pclk : in STD_LOGIC;
ready : out STD_LOGIC;
reset : in STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
vsync : in STD_LOGIC;
xclk : out STD_LOGIC
);
end system_wrapper;
architecture STRUCTURE of system_wrapper is
component system is
port (
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC;
ready : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
data : in STD_LOGIC_VECTOR ( 7 downto 0 );
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
xclk : out STD_LOGIC;
reset : in STD_LOGIC;
pclk : in STD_LOGIC;
clk_100 : in STD_LOGIC;
enable_nm : in STD_LOGIC
);
end component system;
begin
system_i: component system
port map (
clk_100 => clk_100,
data(7 downto 0) => data(7 downto 0),
enable_nm => enable_nm,
hdmi_clk => hdmi_clk,
hdmi_d(15 downto 0) => hdmi_d(15 downto 0),
hdmi_de => hdmi_de,
hdmi_hsync => hdmi_hsync,
hdmi_scl => hdmi_scl,
hdmi_sda => hdmi_sda,
hdmi_vsync => hdmi_vsync,
hsync => hsync,
pclk => pclk,
ready => ready,
reset => reset,
sioc => sioc,
siod => siod,
vsync => vsync,
xclk => xclk
);
end STRUCTURE;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_inverter_1_0/system_inverter_1_0_sim_netlist.vhdl
|
1
|
1828
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Wed Mar 01 09:52:04 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_inverter_1_0/system_inverter_1_0_sim_netlist.vhdl
-- Design : system_inverter_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_inverter_1_0 is
port (
x : in STD_LOGIC;
x_not : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_inverter_1_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_inverter_1_0 : entity is "system_inverter_1_0,inverter,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_inverter_1_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_inverter_1_0 : entity is "inverter,Vivado 2016.4";
end system_inverter_1_0;
architecture STRUCTURE of system_inverter_1_0 is
begin
x_not_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => x,
O => x_not
);
end STRUCTURE;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
video_ip/vga_axi_mem_buffer/vga_axi_mem_buffer_1.0/hdl/vga_axi_mem_buffer_v1_0_S_AXI.vhd
|
1
|
23860
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vga_axi_mem_buffer_v1_0_S_AXI is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of ID for for write address, write data, read address and read data
C_S_AXI_ID_WIDTH : integer := 1;
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 6;
-- Width of optional user defined signal in write address channel
C_S_AXI_AWUSER_WIDTH : integer := 0;
-- Width of optional user defined signal in read address channel
C_S_AXI_ARUSER_WIDTH : integer := 0;
-- Width of optional user defined signal in write data channel
C_S_AXI_WUSER_WIDTH : integer := 0;
-- Width of optional user defined signal in read data channel
C_S_AXI_RUSER_WIDTH : integer := 0;
-- Width of optional user defined signal in write response channel
C_S_AXI_BUSER_WIDTH : integer := 0
);
port (
-- Users to add ports here
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write Address ID
S_AXI_AWID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
-- Write address
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Burst length. The burst length gives the exact number of transfers in a burst
S_AXI_AWLEN : in std_logic_vector(7 downto 0);
-- Burst size. This signal indicates the size of each transfer in the burst
S_AXI_AWSIZE : in std_logic_vector(2 downto 0);
-- Burst type. The burst type and the size information,
-- determine how the address for each transfer within the burst is calculated.
S_AXI_AWBURST : in std_logic_vector(1 downto 0);
-- Lock type. Provides additional information about the
-- atomic characteristics of the transfer.
S_AXI_AWLOCK : in std_logic;
-- Memory type. This signal indicates how transactions
-- are required to progress through a system.
S_AXI_AWCACHE : in std_logic_vector(3 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Quality of Service, QoS identifier sent for each
-- write transaction.
S_AXI_AWQOS : in std_logic_vector(3 downto 0);
-- Region identifier. Permits a single physical interface
-- on a slave to be used for multiple logical interfaces.
S_AXI_AWREGION : in std_logic_vector(3 downto 0);
-- Optional User-defined signal in the write address channel.
S_AXI_AWUSER : in std_logic_vector(C_S_AXI_AWUSER_WIDTH-1 downto 0);
-- Write address valid. This signal indicates that
-- the channel is signaling valid write address and
-- control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that
-- the slave is ready to accept an address and associated
-- control signals.
S_AXI_AWREADY : out std_logic;
-- Write Data
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte
-- lanes hold valid data. There is one write strobe
-- bit for each eight bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write last. This signal indicates the last transfer
-- in a write burst.
S_AXI_WLAST : in std_logic;
-- Optional User-defined signal in the write data channel.
S_AXI_WUSER : in std_logic_vector(C_S_AXI_WUSER_WIDTH-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Response ID tag. This signal is the ID tag of the
-- write response.
S_AXI_BID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Optional User-defined signal in the write response channel.
S_AXI_BUSER : out std_logic_vector(C_S_AXI_BUSER_WIDTH-1 downto 0);
-- Write response valid. This signal indicates that the
-- channel is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address ID. This signal is the identification
-- tag for the read address group of signals.
S_AXI_ARID : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
-- Read address. This signal indicates the initial
-- address of a read burst transaction.
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Burst length. The burst length gives the exact number of transfers in a burst
S_AXI_ARLEN : in std_logic_vector(7 downto 0);
-- Burst size. This signal indicates the size of each transfer in the burst
S_AXI_ARSIZE : in std_logic_vector(2 downto 0);
-- Burst type. The burst type and the size information,
-- determine how the address for each transfer within the burst is calculated.
S_AXI_ARBURST : in std_logic_vector(1 downto 0);
-- Lock type. Provides additional information about the
-- atomic characteristics of the transfer.
S_AXI_ARLOCK : in std_logic;
-- Memory type. This signal indicates how transactions
-- are required to progress through a system.
S_AXI_ARCACHE : in std_logic_vector(3 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Quality of Service, QoS identifier sent for each
-- read transaction.
S_AXI_ARQOS : in std_logic_vector(3 downto 0);
-- Region identifier. Permits a single physical interface
-- on a slave to be used for multiple logical interfaces.
S_AXI_ARREGION : in std_logic_vector(3 downto 0);
-- Optional User-defined signal in the read address channel.
S_AXI_ARUSER : in std_logic_vector(C_S_AXI_ARUSER_WIDTH-1 downto 0);
-- Write address valid. This signal indicates that
-- the channel is signaling valid read address and
-- control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that
-- the slave is ready to accept an address and associated
-- control signals.
S_AXI_ARREADY : out std_logic;
-- Read ID tag. This signal is the identification tag
-- for the read data group of signals generated by the slave.
S_AXI_RID : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
-- Read Data
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of
-- the read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read last. This signal indicates the last transfer
-- in a read burst.
S_AXI_RLAST : out std_logic;
-- Optional User-defined signal in the read address channel.
S_AXI_RUSER : out std_logic_vector(C_S_AXI_RUSER_WIDTH-1 downto 0);
-- Read valid. This signal indicates that the channel
-- is signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic
);
end vga_axi_mem_buffer_v1_0_S_AXI;
architecture arch_imp of vga_axi_mem_buffer_v1_0_S_AXI is
-- AXI4FULL signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_buser : std_logic_vector(C_S_AXI_BUSER_WIDTH-1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rlast : std_logic;
signal axi_ruser : std_logic_vector(C_S_AXI_RUSER_WIDTH-1 downto 0);
signal axi_rvalid : std_logic;
-- aw_wrap_en determines wrap boundary and enables wrapping
signal aw_wrap_en : std_logic;
-- ar_wrap_en determines wrap boundary and enables wrapping
signal ar_wrap_en : std_logic;
-- aw_wrap_size is the size of the write transfer, the
-- write address wraps to a lower address if upper address
-- limit is reached
signal aw_wrap_size : integer;
-- ar_wrap_size is the size of the read transfer, the
-- read address wraps to a lower address if upper address
-- limit is reached
signal ar_wrap_size : integer;
-- The axi_awv_awr_flag flag marks the presence of write address valid
signal axi_awv_awr_flag : std_logic;
--The axi_arv_arr_flag flag marks the presence of read address valid
signal axi_arv_arr_flag : std_logic;
-- The axi_awlen_cntr internal write address counter to keep track of beats in a burst transaction
signal axi_awlen_cntr : std_logic_vector(7 downto 0);
--The axi_arlen_cntr internal read address counter to keep track of beats in a burst transaction
signal axi_arlen_cntr : std_logic_vector(7 downto 0);
signal axi_arburst : std_logic_vector(2-1 downto 0);
signal axi_awburst : std_logic_vector(2-1 downto 0);
signal axi_arlen : std_logic_vector(8-1 downto 0);
signal axi_awlen : std_logic_vector(8-1 downto 0);
--local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
--ADDR_LSB is used for addressing 32/64 bit registers/memories
--ADDR_LSB = 2 for 32 bits (n downto 2)
--ADDR_LSB = 3 for 42 bits (n downto 3)
constant ADDR_LSB : integer := (C_S_AXI_DATA_WIDTH/32)+ 1;
constant OPT_MEM_ADDR_BITS : integer := 3;
constant USER_NUM_MEM: integer := 1;
constant low : std_logic_vector (C_S_AXI_ADDR_WIDTH - 1 downto 0) := "000000";
------------------------------------------------
---- Signals for user logic memory space example
--------------------------------------------------
signal mem_address : std_logic_vector(OPT_MEM_ADDR_BITS downto 0);
signal mem_select : std_logic_vector(USER_NUM_MEM-1 downto 0);
type word_array is array (0 to USER_NUM_MEM-1) of std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal mem_data_out : word_array;
signal i : integer;
signal j : integer;
signal mem_byte_index : integer;
type BYTE_RAM_TYPE is array (0 to 15) of std_logic_vector(7 downto 0);
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BUSER <= axi_buser;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RLAST <= axi_rlast;
S_AXI_RUSER <= axi_ruser;
S_AXI_RVALID <= axi_rvalid;
S_AXI_BID <= S_AXI_AWID;
S_AXI_RID <= S_AXI_ARID;
aw_wrap_size <= ((C_S_AXI_DATA_WIDTH)/8 * to_integer(unsigned(axi_awlen)));
ar_wrap_size <= ((C_S_AXI_DATA_WIDTH)/8 * to_integer(unsigned(axi_arlen)));
aw_wrap_en <= '1' when (((axi_awaddr AND std_logic_vector(to_unsigned(aw_wrap_size,C_S_AXI_ADDR_WIDTH))) XOR std_logic_vector(to_unsigned(aw_wrap_size,C_S_AXI_ADDR_WIDTH))) = low) else '0';
ar_wrap_en <= '1' when (((axi_araddr AND std_logic_vector(to_unsigned(ar_wrap_size,C_S_AXI_ADDR_WIDTH))) XOR std_logic_vector(to_unsigned(ar_wrap_size,C_S_AXI_ADDR_WIDTH))) = low) else '0';
S_AXI_BUSER <= (others => '0');
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
axi_awv_awr_flag <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and axi_awv_awr_flag = '0' and axi_arv_arr_flag = '0') then
-- slave is ready to accept an address and
-- associated control signals
axi_awv_awr_flag <= '1'; -- used for generation of bresp() and bvalid
axi_awready <= '1';
elsif (S_AXI_WLAST = '1' and axi_wready = '1') then
-- preparing to accept next address after current write burst tx completion
axi_awv_awr_flag <= '0';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
axi_awburst <= (others => '0');
axi_awlen <= (others => '0');
axi_awlen_cntr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and axi_awv_awr_flag = '0') then
-- address latching
axi_awaddr <= S_AXI_AWADDR(C_S_AXI_ADDR_WIDTH - 1 downto 0); ---- start address of transfer
axi_awlen_cntr <= (others => '0');
axi_awburst <= S_AXI_AWBURST;
axi_awlen <= S_AXI_AWLEN;
elsif((axi_awlen_cntr <= axi_awlen) and axi_wready = '1' and S_AXI_WVALID = '1') then
axi_awlen_cntr <= std_logic_vector (unsigned(axi_awlen_cntr) + 1);
case (axi_awburst) is
when "00" => -- fixed burst
-- The write address for all the beats in the transaction are fixed
axi_awaddr <= axi_awaddr; ----for awsize = 4 bytes (010)
when "01" => --incremental burst
-- The write address for all the beats in the transaction are increments by awsize
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1);--awaddr aligned to 4 byte boundary
axi_awaddr(ADDR_LSB-1 downto 0) <= (others => '0'); ----for awsize = 4 bytes (010)
when "10" => --Wrapping burst
-- The write address wraps when the address reaches wrap boundary
if (aw_wrap_en = '1') then
axi_awaddr <= std_logic_vector (unsigned(axi_awaddr) - (to_unsigned(aw_wrap_size,C_S_AXI_ADDR_WIDTH)));
else
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1);--awaddr aligned to 4 byte boundary
axi_awaddr(ADDR_LSB-1 downto 0) <= (others => '0'); ----for awsize = 4 bytes (010)
end if;
when others => --reserved (incremental burst for example)
axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_awaddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1);--for awsize = 4 bytes (010)
axi_awaddr(ADDR_LSB-1 downto 0) <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and axi_awv_awr_flag = '1') then
axi_wready <= '1';
-- elsif (axi_awv_awr_flag = '0') then
elsif (S_AXI_WLAST = '1' and axi_wready = '1') then
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awv_awr_flag = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' and S_AXI_WLAST = '1' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then
--check if bready is asserted while bvalid is high)
axi_bvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_arv_arr_flag <= '0';
else
if (axi_arready = '0' and S_AXI_ARVALID = '1' and axi_awv_awr_flag = '0' and axi_arv_arr_flag = '0') then
axi_arready <= '1';
axi_arv_arr_flag <= '1';
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1' and (axi_arlen_cntr = axi_arlen)) then
-- preparing to accept next address after current read completion
axi_arv_arr_flag <= '0';
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_araddr latching
--This process is used to latch the address when both
--S_AXI_ARVALID and S_AXI_RVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_araddr <= (others => '0');
axi_arburst <= (others => '0');
axi_arlen <= (others => '0');
axi_arlen_cntr <= (others => '0');
axi_rlast <= '0';
else
if (axi_arready = '0' and S_AXI_ARVALID = '1' and axi_arv_arr_flag = '0') then
-- address latching
axi_araddr <= S_AXI_ARADDR(C_S_AXI_ADDR_WIDTH - 1 downto 0); ---- start address of transfer
axi_arlen_cntr <= (others => '0');
axi_rlast <= '0';
axi_arburst <= S_AXI_ARBURST;
axi_arlen <= S_AXI_ARLEN;
elsif((axi_arlen_cntr <= axi_arlen) and axi_rvalid = '1' and S_AXI_RREADY = '1') then
axi_arlen_cntr <= std_logic_vector (unsigned(axi_arlen_cntr) + 1);
axi_rlast <= '0';
case (axi_arburst) is
when "00" => -- fixed burst
-- The read address for all the beats in the transaction are fixed
axi_araddr <= axi_araddr; ----for arsize = 4 bytes (010)
when "01" => --incremental burst
-- The read address for all the beats in the transaction are increments by awsize
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1); --araddr aligned to 4 byte boundary
axi_araddr(ADDR_LSB-1 downto 0) <= (others => '0'); ----for awsize = 4 bytes (010)
when "10" => --Wrapping burst
-- The read address wraps when the address reaches wrap boundary
if (ar_wrap_en = '1') then
axi_araddr <= std_logic_vector (unsigned(axi_araddr) - (to_unsigned(ar_wrap_size,C_S_AXI_ADDR_WIDTH)));
else
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1); --araddr aligned to 4 byte boundary
axi_araddr(ADDR_LSB-1 downto 0) <= (others => '0'); ----for awsize = 4 bytes (010)
end if;
when others => --reserved (incremental burst for example)
axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB) <= std_logic_vector (unsigned(axi_araddr(C_S_AXI_ADDR_WIDTH - 1 downto ADDR_LSB)) + 1);--for arsize = 4 bytes (010)
axi_araddr(ADDR_LSB-1 downto 0) <= (others => '0');
end case;
elsif((axi_arlen_cntr = axi_arlen) and axi_rlast = '0' and axi_arv_arr_flag = '1') then
axi_rlast <= '1';
elsif (S_AXI_RREADY = '1') then
axi_rlast <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arv_arr_flag = '1' and axi_rvalid = '0') then
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- ------------------------------------------
-- -- Example code to access user logic memory region
-- ------------------------------------------
gen_mem_sel: if (USER_NUM_MEM >= 1) generate
begin
mem_select <= "1";
mem_address <= axi_araddr(ADDR_LSB+OPT_MEM_ADDR_BITS downto ADDR_LSB) when axi_arv_arr_flag = '1' else
axi_awaddr(ADDR_LSB+OPT_MEM_ADDR_BITS downto ADDR_LSB) when axi_awv_awr_flag = '1' else
(others => '0');
end generate gen_mem_sel;
-- implement Block RAM(s)
BRAM_GEN : for i in 0 to USER_NUM_MEM-1 generate
signal mem_rden : std_logic;
signal mem_wren : std_logic;
begin
mem_wren <= axi_wready and S_AXI_WVALID ;
mem_rden <= axi_arv_arr_flag ;
BYTE_BRAM_GEN : for mem_byte_index in 0 to (C_S_AXI_DATA_WIDTH/8-1) generate
signal byte_ram : BYTE_RAM_TYPE;
signal data_in : std_logic_vector(8-1 downto 0);
signal data_out : std_logic_vector(8-1 downto 0);
begin
--assigning 8 bit data
data_in <= S_AXI_WDATA((mem_byte_index*8+7) downto mem_byte_index*8);
data_out <= byte_ram(to_integer(unsigned(mem_address)));
BYTE_RAM_PROC : process( S_AXI_ACLK ) is
begin
if ( rising_edge (S_AXI_ACLK) ) then
if ( mem_wren = '1' and S_AXI_WSTRB(mem_byte_index) = '1' ) then
byte_ram(to_integer(unsigned(mem_address))) <= data_in;
end if;
end if;
end process BYTE_RAM_PROC;
process( S_AXI_ACLK ) is
begin
if ( rising_edge (S_AXI_ACLK) ) then
if ( mem_rden = '1') then
mem_data_out(i)((mem_byte_index*8+7) downto mem_byte_index*8) <= data_out;
end if;
end if;
end process;
end generate BYTE_BRAM_GEN;
end generate BRAM_GEN;
--Output register or memory read data
process(mem_data_out, axi_rvalid ) is
begin
if (axi_rvalid = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
axi_rdata <= mem_data_out(0); -- memory range 0 read data
else
axi_rdata <= (others => '0');
end if;
end process;
-- Add user logic here
-- User logic ends
end arch_imp;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
general_ip/svd_2x2/svd_2x2.srcs/sources_1/ip/arctan/hdl/c_addsub_v12_0_vh_rfs.vhd
|
3
|
402790
|
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`protect end_protected
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
general_ip/svd_2x2/svd_2x2.srcs/sources_1/ip/arctan/sim/arctan.vhd
|
1
|
7172
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
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-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:cordic:6.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY cordic_v6_0_11;
USE cordic_v6_0_11.cordic_v6_0_11;
ENTITY arctan IS
PORT (
aclk : IN STD_LOGIC;
s_axis_cartesian_tvalid : IN STD_LOGIC;
s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_dout_tvalid : OUT STD_LOGIC;
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END arctan;
ARCHITECTURE arctan_arch OF arctan IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF arctan_arch: ARCHITECTURE IS "yes";
COMPONENT cordic_v6_0_11 IS
GENERIC (
C_ARCHITECTURE : INTEGER;
C_CORDIC_FUNCTION : INTEGER;
C_COARSE_ROTATE : INTEGER;
C_DATA_FORMAT : INTEGER;
C_XDEVICEFAMILY : STRING;
C_HAS_ACLKEN : INTEGER;
C_HAS_ACLK : INTEGER;
C_HAS_S_AXIS_CARTESIAN : INTEGER;
C_HAS_S_AXIS_PHASE : INTEGER;
C_HAS_ARESETN : INTEGER;
C_INPUT_WIDTH : INTEGER;
C_ITERATIONS : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_PHASE_FORMAT : INTEGER;
C_PIPELINE_MODE : INTEGER;
C_PRECISION : INTEGER;
C_ROUND_MODE : INTEGER;
C_SCALE_COMP : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_HAS_S_AXIS_PHASE_TUSER : INTEGER;
C_HAS_S_AXIS_PHASE_TLAST : INTEGER;
C_S_AXIS_PHASE_TDATA_WIDTH : INTEGER;
C_S_AXIS_PHASE_TUSER_WIDTH : INTEGER;
C_HAS_S_AXIS_CARTESIAN_TUSER : INTEGER;
C_HAS_S_AXIS_CARTESIAN_TLAST : INTEGER;
C_S_AXIS_CARTESIAN_TDATA_WIDTH : INTEGER;
C_S_AXIS_CARTESIAN_TUSER_WIDTH : INTEGER;
C_M_AXIS_DOUT_TDATA_WIDTH : INTEGER;
C_M_AXIS_DOUT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_phase_tvalid : IN STD_LOGIC;
s_axis_phase_tready : OUT STD_LOGIC;
s_axis_phase_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_phase_tlast : IN STD_LOGIC;
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_cartesian_tvalid : IN STD_LOGIC;
s_axis_cartesian_tready : OUT STD_LOGIC;
s_axis_cartesian_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_cartesian_tlast : IN STD_LOGIC;
s_axis_cartesian_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_dout_tvalid : OUT STD_LOGIC;
m_axis_dout_tready : IN STD_LOGIC;
m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_dout_tlast : OUT STD_LOGIC;
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT cordic_v6_0_11;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_cartesian_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CARTESIAN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_cartesian_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CARTESIAN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_dout_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DOUT TDATA";
BEGIN
U0 : cordic_v6_0_11
GENERIC MAP (
C_ARCHITECTURE => 2,
C_CORDIC_FUNCTION => 3,
C_COARSE_ROTATE => 0,
C_DATA_FORMAT => 0,
C_XDEVICEFAMILY => "zynq",
C_HAS_ACLKEN => 0,
C_HAS_ACLK => 1,
C_HAS_S_AXIS_CARTESIAN => 1,
C_HAS_S_AXIS_PHASE => 0,
C_HAS_ARESETN => 0,
C_INPUT_WIDTH => 16,
C_ITERATIONS => 0,
C_OUTPUT_WIDTH => 16,
C_PHASE_FORMAT => 0,
C_PIPELINE_MODE => -2,
C_PRECISION => 0,
C_ROUND_MODE => 0,
C_SCALE_COMP => 0,
C_THROTTLE_SCHEME => 3,
C_TLAST_RESOLUTION => 0,
C_HAS_S_AXIS_PHASE_TUSER => 0,
C_HAS_S_AXIS_PHASE_TLAST => 0,
C_S_AXIS_PHASE_TDATA_WIDTH => 16,
C_S_AXIS_PHASE_TUSER_WIDTH => 1,
C_HAS_S_AXIS_CARTESIAN_TUSER => 0,
C_HAS_S_AXIS_CARTESIAN_TLAST => 0,
C_S_AXIS_CARTESIAN_TDATA_WIDTH => 32,
C_S_AXIS_CARTESIAN_TUSER_WIDTH => 1,
C_M_AXIS_DOUT_TDATA_WIDTH => 16,
C_M_AXIS_DOUT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_phase_tvalid => '0',
s_axis_phase_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_phase_tlast => '0',
s_axis_phase_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 16)),
s_axis_cartesian_tvalid => s_axis_cartesian_tvalid,
s_axis_cartesian_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_cartesian_tlast => '0',
s_axis_cartesian_tdata => s_axis_cartesian_tdata,
m_axis_dout_tvalid => m_axis_dout_tvalid,
m_axis_dout_tready => '0',
m_axis_dout_tdata => m_axis_dout_tdata
);
END arctan_arch;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_buffer_register_1_0/synth/system_buffer_register_1_0.vhd
|
2
|
4059
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:buffer_register:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_buffer_register_1_0 IS
PORT (
clk : IN STD_LOGIC;
val_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
val_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END system_buffer_register_1_0;
ARCHITECTURE system_buffer_register_1_0_arch OF system_buffer_register_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_buffer_register_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT buffer_register IS
GENERIC (
WIDTH : INTEGER
);
PORT (
clk : IN STD_LOGIC;
val_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
val_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT buffer_register;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_buffer_register_1_0_arch: ARCHITECTURE IS "buffer_register,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_buffer_register_1_0_arch : ARCHITECTURE IS "system_buffer_register_1_0,buffer_register,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_buffer_register_1_0_arch: ARCHITECTURE IS "system_buffer_register_1_0,buffer_register,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=buffer_register,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,WIDTH=32}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : buffer_register
GENERIC MAP (
WIDTH => 32
)
PORT MAP (
clk => clk,
val_in => val_in,
val_out => val_out
);
END system_buffer_register_1_0_arch;
|
mit
|
SoCdesign/audiomixer
|
ZedBoard_Linux_Design/hw/xps_proj/pcores/axi_spdif_tx_v1_00_a/hdl/vhdl/tx_encoder.vhd
|
3
|
20871
|
----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF project ----
---- http://www.opencores.org/cores/spdif_interface/ ----
---- ----
---- Description ----
---- SPDIF transmitter signal encoder. Reads out samples from the ----
---- sample buffer, assembles frames and subframes and encodes ----
---- serial data as bi-phase mark code. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Geir Drange, [email protected] ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tx_encoder is
generic (DATA_WIDTH: integer range 16 to 32 := 32);
port (
up_clk: in std_logic; -- clock
data_clk : in std_logic; -- data clock
resetn : in std_logic; -- resetn
conf_mode: in std_logic_vector(3 downto 0); -- sample format
conf_ratio: in std_logic_vector(7 downto 0); -- clock divider
conf_udaten: in std_logic_vector(1 downto 0); -- user data control
conf_chsten: in std_logic_vector(1 downto 0); -- ch. status control
conf_txdata: in std_logic; -- sample data enable
conf_txen: in std_logic; -- spdif signal enable
user_data_a: in std_logic_vector(191 downto 0); -- ch. a user data
user_data_b: in std_logic_vector(191 downto 0); -- ch. b user data
ch_stat_a: in std_logic_vector(191 downto 0); -- ch. a status
ch_stat_b: in std_logic_vector(191 downto 0); -- ch. b status
chstat_freq: in std_logic_vector(1 downto 0); -- sample freq.
chstat_gstat: in std_logic; -- generation status
chstat_preem: in std_logic; -- preemphasis status
chstat_copy: in std_logic; -- copyright bit
chstat_audio: in std_logic; -- data format
sample_data: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data
mem_rd: out std_logic; -- sample buffer read
channel: out std_logic;
spdif_tx_o: out std_logic);
end tx_encoder;
architecture rtl of tx_encoder is
signal spdif_clk_en, spdif_out : std_logic;
signal clk_cnt : integer range 0 to 511;
type buf_states is (IDLE, READ_CHA, READ_CHB, CHA_RDY, CHB_RDY);
signal bufctrl : buf_states;
signal cha_samp_ack, chb_samp_ack : std_logic;
type frame_states is (IDLE, BLOCK_START, CHANNEL_A, CHANNEL_B);
signal framest : frame_states;
signal frame_cnt : integer range 0 to 191;
signal bit_cnt, par_cnt : integer range 0 to 31;
signal inv_preamble, toggle, valid : std_logic;
signal def_user_data, def_ch_status : std_logic_vector(191 downto 0);
signal active_user_data, active_ch_status : std_logic_vector(191 downto 0);
signal audio : std_logic_vector(23 downto 0);
signal par_vector : std_logic_vector(26 downto 0);
signal send_audio, imem_rd : std_logic;
signal tick_counter : std_logic;
signal tick_counter_d1 : std_logic;
signal tick_counter_d2 : std_logic;
constant X_PREAMBLE : std_logic_vector(0 to 7) := "11100010";
constant Y_PREAMBLE : std_logic_vector(0 to 7) := "11100100";
constant Z_PREAMBLE : std_logic_vector(0 to 7) := "11101000";
function encode_bit (
signal bit_cnt : integer; -- sub-frame bit position
signal valid : std_logic; -- validity bit
signal frame_cnt : integer; -- frame counter
signal par_cnt : integer; -- parity counter
signal user_data : std_logic_vector(191 downto 0);
signal ch_status : std_logic_vector(191 downto 0);
signal audio : std_logic_vector(23 downto 0);
signal toggle : std_logic;
signal prev_spdif : std_logic) -- prev. value of spdif signal
return std_logic is
variable spdif, next_bit : std_logic;
begin
if bit_cnt > 3 and bit_cnt < 28 then -- audio part
next_bit := audio(bit_cnt - 4);
elsif bit_cnt = 28 then -- validity bit
next_bit := valid;
elsif bit_cnt = 29 then -- user data
next_bit := user_data(frame_cnt);
elsif bit_cnt = 30 then
next_bit := ch_status(frame_cnt); -- channel status
elsif bit_cnt = 31 then
if par_cnt mod 2 = 1 then
next_bit := '1';
else
next_bit := '0';
end if;
end if;
-- bi-phase mark encoding:
if next_bit = '0' then
if toggle = '0' then
spdif := not prev_spdif;
else
spdif := prev_spdif;
end if;
else
spdif := not prev_spdif;
end if;
return(spdif);
end encode_bit;
begin
-- SPDIF clock enable generation. The clock is a fraction of the data clock,
-- determined by the conf_ratio value.
DCLK : process (data_clk)
begin
if rising_edge(data_clk) then
tick_counter <= not tick_counter;
end if;
end process DCLK;
CGEN: process (up_clk)
begin
if rising_edge(up_clk) then
if resetn = '0' or conf_txen = '0' then
clk_cnt <= 0;
tick_counter_d1 <= '0';
tick_counter_d2 <= '0';
spdif_clk_en <= '0';
else
tick_counter_d1 <= tick_counter;
tick_counter_d2 <= tick_counter_d1;
spdif_clk_en <= '0';
if (tick_counter_d1 xor tick_counter_d2) = '1' then
if clk_cnt < to_integer(unsigned(conf_ratio)) then
clk_cnt <= clk_cnt + 1;
else
clk_cnt <= 0;
spdif_clk_en <= '1';
end if;
end if;
end if;
end if;
end process CGEN;
-- Sample memory read process. Enabled by the conf_txdata bit.
-- Buffer address is reset when disabled. Also generates events for
-- lower and upper buffer empty conditions
mem_rd <= imem_rd;
SRD: process (up_clk)
begin
if rising_edge(up_clk) then
if resetn = '0' or conf_txdata = '0' then
bufctrl <= IDLE;
imem_rd <= '0';
channel <= '0';
else
case bufctrl is
when IDLE =>
imem_rd <= '0';
if conf_txdata = '1' then
bufctrl <= READ_CHA;
imem_rd <='1';
end if;
when READ_CHA =>
channel <= '0';
imem_rd <= '0';
bufctrl <= CHA_RDY;
when CHA_RDY =>
if cha_samp_ack = '1' then
imem_rd <= '1';
bufctrl <= READ_CHB;
end if;
when READ_CHB =>
channel <= '1';
imem_rd <= '0';
bufctrl <= CHB_RDY;
when CHB_RDY =>
if chb_samp_ack = '1' then
imem_rd <= '1';
bufctrl <= READ_CHA;
end if;
when others =>
bufctrl <= IDLE;
end case;
end if;
end if;
end process SRD;
TXSYNC: process (data_clk)
begin
if (rising_edge(data_clk)) then
if resetn = '0' then
spdif_tx_o <= '0';
else
spdif_tx_o <= spdif_out;
end if;
end if;
end process TXSYNC;
-- State machine that generates sub-frames and blocks
FRST: process (up_clk)
begin
if rising_edge(up_clk) then
if resetn = '0' or conf_txen = '0' then
framest <= IDLE;
frame_cnt <= 0;
bit_cnt <= 0;
spdif_out <= '0';
inv_preamble <= '0';
toggle <= '0';
valid <= '1';
send_audio <= '0';
cha_samp_ack <= '0';
chb_samp_ack <= '0';
else
if spdif_clk_en = '1' then -- SPDIF clock is twice the bit rate
case framest is
when IDLE =>
bit_cnt <= 0;
frame_cnt <= 0;
inv_preamble <= '0';
toggle <= '0';
framest <= BLOCK_START;
when BLOCK_START => -- Start of channels status block/Ch. A
chb_samp_ack <= '0';
toggle <= not toggle; -- Each bit uses two clock enables,
if toggle = '1' then -- counted by the toggle bit.
if bit_cnt < 31 then
bit_cnt <= bit_cnt + 1;
else
bit_cnt <= 0;
if send_audio = '1' then
cha_samp_ack <= '1';
end if;
framest <= CHANNEL_B;
end if;
end if;
-- Block start uses preamble Z.
if bit_cnt < 4 then
if toggle = '0' then
spdif_out <= Z_PREAMBLE(2 * bit_cnt) xor inv_preamble;
else
spdif_out <= Z_PREAMBLE(2 * bit_cnt + 1) xor inv_preamble;
end if;
par_cnt <= 0;
elsif bit_cnt > 3 and bit_cnt <= 31 then
spdif_out <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
if bit_cnt = 31 then
inv_preamble <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
end if;
if toggle = '0' then
if bit_cnt > 3 and bit_cnt < 31 and
par_vector(bit_cnt - 4) = '1' then
par_cnt <= par_cnt + 1;
end if;
end if;
end if;
when CHANNEL_A => -- Sub-frame: channel A.
chb_samp_ack <= '0';
toggle <= not toggle;
if toggle = '1' then
if bit_cnt < 31 then
bit_cnt <= bit_cnt + 1;
else
bit_cnt <= 0;
if spdif_out = '1' then
inv_preamble <= '1';
else
inv_preamble <= '0';
end if;
if send_audio = '1' then
cha_samp_ack <= '1';
end if;
framest <= CHANNEL_B;
end if;
end if;
-- Channel A uses preable X.
if bit_cnt < 4 then
if toggle = '0' then
spdif_out <= X_PREAMBLE(2 * bit_cnt) xor inv_preamble;
else
spdif_out <= X_PREAMBLE(2 * bit_cnt + 1) xor inv_preamble;
end if;
par_cnt <= 0;
elsif bit_cnt > 3 and bit_cnt <= 31 then
spdif_out <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
if bit_cnt = 31 then
inv_preamble <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
end if;
if toggle = '0' then
if bit_cnt > 3 and bit_cnt < 31 and
par_vector(bit_cnt - 4) = '1' then
par_cnt <= par_cnt + 1;
end if;
end if;
end if;
when CHANNEL_B => -- Sub-frame: channel B.
cha_samp_ack <= '0';
toggle <= not toggle;
if toggle = '1' then
if bit_cnt < 31 then
bit_cnt <= bit_cnt + 1;
else
bit_cnt <= 0;
valid <= not conf_txdata;
if spdif_out = '1' then
inv_preamble <= '1';
else
inv_preamble <= '0';
end if;
send_audio <= conf_txdata; -- 1 if audio samples sohuld be sent
if send_audio = '1' then
chb_samp_ack <= '1';
end if;
if frame_cnt < 191 then -- One block is 192 frames
frame_cnt <= frame_cnt + 1;
framest <= CHANNEL_A;
else
frame_cnt <= 0;
framest <= BLOCK_START;
end if;
end if;
end if;
-- Channel B uses preable Y.
if bit_cnt < 4 then
if toggle = '0' then
spdif_out <= Y_PREAMBLE(2 * bit_cnt) xor inv_preamble;
else
spdif_out <= Y_PREAMBLE(2 * bit_cnt + 1) xor inv_preamble;
end if;
par_cnt <= 0;
elsif bit_cnt > 3 and bit_cnt <= 31 then
spdif_out <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
if bit_cnt = 31 then
inv_preamble <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
end if;
if toggle = '0' then
if bit_cnt > 3 and bit_cnt < 31 and
par_vector(bit_cnt - 4) = '1' then
par_cnt <= par_cnt + 1;
end if;
end if;
end if;
when others =>
framest <= IDLE;
end case;
end if;
end if;
end if;
end process FRST;
-- Audio data latching
DA32: if DATA_WIDTH = 32 generate
ALAT: process (up_clk)
begin
if rising_edge(up_clk) then
if send_audio = '0' then
audio(23 downto 0) <= (others => '0');
else
case to_integer(unsigned(conf_mode)) is
when 0 => -- 16 bit audio
audio(23 downto 8) <= sample_data(15 downto 0);
audio(7 downto 0) <= (others => '0');
when 1 => -- 17 bit audio
audio(23 downto 7) <= sample_data(16 downto 0);
audio(6 downto 0) <= (others => '0');
when 2 => -- 18 bit audio
audio(23 downto 6) <= sample_data(17 downto 0);
audio(5 downto 0) <= (others => '0');
when 3 => -- 19 bit audio
audio(23 downto 5) <= sample_data(18 downto 0);
audio(4 downto 0) <= (others => '0');
when 4 => -- 20 bit audio
audio(23 downto 4) <= sample_data(19 downto 0);
audio(3 downto 0) <= (others => '0');
when 5 => -- 21 bit audio
audio(23 downto 3) <= sample_data(20 downto 0);
audio(2 downto 0) <= (others => '0');
when 6 => -- 22 bit audio
audio(23 downto 2) <= sample_data(21 downto 0);
audio(1 downto 0) <= (others => '0');
when 7 => -- 23 bit audio
audio(23 downto 1) <= sample_data(22 downto 0);
audio(0) <= '0';
when 8 => -- 24 bit audio
audio(23 downto 0) <= sample_data(23 downto 0);
when others => -- unsupported modes
audio(23 downto 0) <= (others => '0');
end case;
end if;
end if;
end process ALAT;
end generate DA32;
DA16: if DATA_WIDTH = 16 generate
ALAT: process (up_clk)
begin
if rising_edge(up_clk) then
if send_audio = '0' then
audio(23 downto 0) <= (others => '0');
else
audio(23 downto 8) <= sample_data(15 downto 0);
audio(7 downto 0) <= (others => '0');
end if;
end if;
end process ALAT;
end generate DA16;
-- Parity vector. These bits are counted to generate even parity
par_vector(23 downto 0) <= audio(23 downto 0);
par_vector(24) <= valid;
par_vector(25) <= active_user_data(frame_cnt);
par_vector(26) <= active_ch_status(frame_cnt);
-- Channel status and user datat to be used if buffers are disabled.
-- User data is then all zero, while channel status bits are taken from
-- register TxChStat.
def_user_data(191 downto 0) <= (others => '0');
def_ch_status(0) <= '0'; -- consumer mode
def_ch_status(1) <= chstat_audio; -- audio bit
def_ch_status(2) <= chstat_copy; -- copy right
def_ch_status(5 downto 3) <= "000" when chstat_preem = '0'
else "001"; -- pre-emphasis
def_ch_status(7 downto 6) <= "00";
def_ch_status(14 downto 8) <= (others => '0');
def_ch_status(15) <= chstat_gstat; -- generation status
def_ch_status(23 downto 16) <= (others => '0');
def_ch_status(27 downto 24) <= "0000" when chstat_freq = "00" else
"0010" when chstat_freq = "01" else
"0011" when chstat_freq = "10" else
"0001";
def_ch_status(191 downto 28) <= (others => '0'); --191 28
-- Generate channel status vector based on configuration register setting.
active_ch_status <= ch_stat_a when conf_chsten = "01" else
ch_stat_a when conf_chsten = "10" and framest = CHANNEL_A else
ch_stat_b when conf_chsten = "10" and framest = CHANNEL_B else
def_ch_status;
-- Generate user data vector based on configuration register setting.
active_user_data <= user_data_a when conf_udaten = "01" else
user_data_a when conf_udaten = "10" and framest = CHANNEL_A else
user_data_b when conf_udaten = "10" and framest = CHANNEL_B else
def_user_data;
end rtl;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_vga_buffer_0_0/synth/system_vga_buffer_0_0.vhd
|
4
|
4630
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:vga_buffer:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_vga_buffer_0_0 IS
PORT (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
wen : IN STD_LOGIC;
x_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
data_w : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
data_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_vga_buffer_0_0;
ARCHITECTURE system_vga_buffer_0_0_arch OF system_vga_buffer_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_vga_buffer_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT vga_buffer IS
GENERIC (
SIZE_POW2 : INTEGER
);
PORT (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
wen : IN STD_LOGIC;
x_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_w : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
x_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y_addr_r : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
data_w : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
data_r : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT vga_buffer;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_vga_buffer_0_0_arch: ARCHITECTURE IS "vga_buffer,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_vga_buffer_0_0_arch : ARCHITECTURE IS "system_vga_buffer_0_0,vga_buffer,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_vga_buffer_0_0_arch: ARCHITECTURE IS "system_vga_buffer_0_0,vga_buffer,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=vga_buffer,x_ipVersion=1.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,SIZE_POW2=10}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk_w: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
U0 : vga_buffer
GENERIC MAP (
SIZE_POW2 => 10
)
PORT MAP (
clk_w => clk_w,
clk_r => clk_r,
wen => wen,
x_addr_w => x_addr_w,
y_addr_w => y_addr_w,
x_addr_r => x_addr_r,
y_addr_r => y_addr_r,
data_w => data_w,
data_r => data_r
);
END system_vga_buffer_0_0_arch;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_vga_transform_0_1/system_vga_transform_0_1_sim_netlist.vhdl
|
1
|
143471
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 14:49:03 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_vga_transform_0_1 -prefix
-- system_vga_transform_0_1_ system_vga_transform_0_1_sim_netlist.vhdl
-- Design : system_vga_transform_0_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_transform_0_1_vga_transform is
port (
x_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
rot_m01 : in STD_LOGIC_VECTOR ( 15 downto 0 );
y_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
rot_m00 : in STD_LOGIC_VECTOR ( 15 downto 0 );
x_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
clk : in STD_LOGIC;
rot_m11 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m10 : in STD_LOGIC_VECTOR ( 15 downto 0 );
enable : in STD_LOGIC;
t_x : in STD_LOGIC_VECTOR ( 9 downto 0 );
t_y : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
end system_vga_transform_0_1_vga_transform;
architecture STRUCTURE of system_vga_transform_0_1_vga_transform is
signal p_0_in : STD_LOGIC_VECTOR ( 9 downto 0 );
signal p_1_in : STD_LOGIC_VECTOR ( 23 downto 14 );
signal x_addr_out0 : STD_LOGIC_VECTOR ( 23 downto 14 );
signal \x_addr_out0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \x_addr_out0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \x_addr_out0_carry__0_n_0\ : STD_LOGIC;
signal \x_addr_out0_carry__0_n_1\ : STD_LOGIC;
signal \x_addr_out0_carry__0_n_2\ : STD_LOGIC;
signal \x_addr_out0_carry__0_n_3\ : STD_LOGIC;
signal \x_addr_out0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out0_carry__1_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out0_carry__1_n_3\ : STD_LOGIC;
signal x_addr_out0_carry_i_1_n_0 : STD_LOGIC;
signal x_addr_out0_carry_i_2_n_0 : STD_LOGIC;
signal x_addr_out0_carry_i_3_n_0 : STD_LOGIC;
signal x_addr_out0_carry_n_0 : STD_LOGIC;
signal x_addr_out0_carry_n_1 : STD_LOGIC;
signal x_addr_out0_carry_n_2 : STD_LOGIC;
signal x_addr_out0_carry_n_3 : STD_LOGIC;
signal \x_addr_out2_carry__0_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__0_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__0_i_3_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__0_i_4_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__0_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__0_n_1\ : STD_LOGIC;
signal \x_addr_out2_carry__0_n_2\ : STD_LOGIC;
signal \x_addr_out2_carry__0_n_3\ : STD_LOGIC;
signal \x_addr_out2_carry__1_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__1_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__1_i_3_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__1_i_4_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__1_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__1_n_1\ : STD_LOGIC;
signal \x_addr_out2_carry__1_n_2\ : STD_LOGIC;
signal \x_addr_out2_carry__1_n_3\ : STD_LOGIC;
signal \x_addr_out2_carry__2_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__2_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__2_i_3_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__2_i_4_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__2_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__2_n_1\ : STD_LOGIC;
signal \x_addr_out2_carry__2_n_2\ : STD_LOGIC;
signal \x_addr_out2_carry__2_n_3\ : STD_LOGIC;
signal \x_addr_out2_carry__3_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__3_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__3_i_3_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__3_i_4_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__3_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__3_n_1\ : STD_LOGIC;
signal \x_addr_out2_carry__3_n_2\ : STD_LOGIC;
signal \x_addr_out2_carry__3_n_3\ : STD_LOGIC;
signal \x_addr_out2_carry__4_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__4_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__4_i_3_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__4_i_4_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__4_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__4_n_1\ : STD_LOGIC;
signal \x_addr_out2_carry__4_n_2\ : STD_LOGIC;
signal \x_addr_out2_carry__4_n_3\ : STD_LOGIC;
signal \x_addr_out2_carry__5_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__5_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__5_i_3_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__5_i_4_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__5_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__5_n_1\ : STD_LOGIC;
signal \x_addr_out2_carry__5_n_2\ : STD_LOGIC;
signal \x_addr_out2_carry__5_n_3\ : STD_LOGIC;
signal \x_addr_out2_carry__6_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__6_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__6_i_3_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__6_i_4_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__6_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__6_n_1\ : STD_LOGIC;
signal \x_addr_out2_carry__6_n_2\ : STD_LOGIC;
signal \x_addr_out2_carry__6_n_3\ : STD_LOGIC;
signal \x_addr_out2_carry__7_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__7_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__7_i_3_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__7_i_4_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__7_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__7_n_1\ : STD_LOGIC;
signal \x_addr_out2_carry__7_n_2\ : STD_LOGIC;
signal \x_addr_out2_carry__7_n_3\ : STD_LOGIC;
signal \x_addr_out2_carry__8_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__8_i_2_n_0\ : STD_LOGIC;
signal \x_addr_out2_carry__8_n_3\ : STD_LOGIC;
signal x_addr_out2_carry_i_1_n_0 : STD_LOGIC;
signal x_addr_out2_carry_i_2_n_0 : STD_LOGIC;
signal x_addr_out2_carry_i_3_n_0 : STD_LOGIC;
signal x_addr_out2_carry_i_4_n_0 : STD_LOGIC;
signal x_addr_out2_carry_n_0 : STD_LOGIC;
signal x_addr_out2_carry_n_1 : STD_LOGIC;
signal x_addr_out2_carry_n_2 : STD_LOGIC;
signal x_addr_out2_carry_n_3 : STD_LOGIC;
signal \x_addr_out3__0_n_100\ : STD_LOGIC;
signal \x_addr_out3__0_n_101\ : STD_LOGIC;
signal \x_addr_out3__0_n_102\ : STD_LOGIC;
signal \x_addr_out3__0_n_103\ : STD_LOGIC;
signal \x_addr_out3__0_n_104\ : STD_LOGIC;
signal \x_addr_out3__0_n_105\ : STD_LOGIC;
signal \x_addr_out3__0_n_58\ : STD_LOGIC;
signal \x_addr_out3__0_n_59\ : STD_LOGIC;
signal \x_addr_out3__0_n_60\ : STD_LOGIC;
signal \x_addr_out3__0_n_61\ : STD_LOGIC;
signal \x_addr_out3__0_n_62\ : STD_LOGIC;
signal \x_addr_out3__0_n_63\ : STD_LOGIC;
signal \x_addr_out3__0_n_64\ : STD_LOGIC;
signal \x_addr_out3__0_n_65\ : STD_LOGIC;
signal \x_addr_out3__0_n_66\ : STD_LOGIC;
signal \x_addr_out3__0_n_67\ : STD_LOGIC;
signal \x_addr_out3__0_n_68\ : STD_LOGIC;
signal \x_addr_out3__0_n_69\ : STD_LOGIC;
signal \x_addr_out3__0_n_70\ : STD_LOGIC;
signal \x_addr_out3__0_n_71\ : STD_LOGIC;
signal \x_addr_out3__0_n_72\ : STD_LOGIC;
signal \x_addr_out3__0_n_73\ : STD_LOGIC;
signal \x_addr_out3__0_n_74\ : STD_LOGIC;
signal \x_addr_out3__0_n_75\ : STD_LOGIC;
signal \x_addr_out3__0_n_76\ : STD_LOGIC;
signal \x_addr_out3__0_n_77\ : STD_LOGIC;
signal \x_addr_out3__0_n_78\ : STD_LOGIC;
signal \x_addr_out3__0_n_79\ : STD_LOGIC;
signal \x_addr_out3__0_n_80\ : STD_LOGIC;
signal \x_addr_out3__0_n_81\ : STD_LOGIC;
signal \x_addr_out3__0_n_82\ : STD_LOGIC;
signal \x_addr_out3__0_n_83\ : STD_LOGIC;
signal \x_addr_out3__0_n_84\ : STD_LOGIC;
signal \x_addr_out3__0_n_85\ : STD_LOGIC;
signal \x_addr_out3__0_n_86\ : STD_LOGIC;
signal \x_addr_out3__0_n_87\ : STD_LOGIC;
signal \x_addr_out3__0_n_88\ : STD_LOGIC;
signal \x_addr_out3__0_n_89\ : STD_LOGIC;
signal \x_addr_out3__0_n_90\ : STD_LOGIC;
signal \x_addr_out3__0_n_91\ : STD_LOGIC;
signal \x_addr_out3__0_n_92\ : STD_LOGIC;
signal \x_addr_out3__0_n_93\ : STD_LOGIC;
signal \x_addr_out3__0_n_94\ : STD_LOGIC;
signal \x_addr_out3__0_n_95\ : STD_LOGIC;
signal \x_addr_out3__0_n_96\ : STD_LOGIC;
signal \x_addr_out3__0_n_97\ : STD_LOGIC;
signal \x_addr_out3__0_n_98\ : STD_LOGIC;
signal \x_addr_out3__0_n_99\ : STD_LOGIC;
signal \x_addr_out3__1_n_100\ : STD_LOGIC;
signal \x_addr_out3__1_n_101\ : STD_LOGIC;
signal \x_addr_out3__1_n_102\ : STD_LOGIC;
signal \x_addr_out3__1_n_103\ : STD_LOGIC;
signal \x_addr_out3__1_n_104\ : STD_LOGIC;
signal \x_addr_out3__1_n_105\ : STD_LOGIC;
signal \x_addr_out3__1_n_106\ : STD_LOGIC;
signal \x_addr_out3__1_n_107\ : STD_LOGIC;
signal \x_addr_out3__1_n_108\ : STD_LOGIC;
signal \x_addr_out3__1_n_109\ : STD_LOGIC;
signal \x_addr_out3__1_n_110\ : STD_LOGIC;
signal \x_addr_out3__1_n_111\ : STD_LOGIC;
signal \x_addr_out3__1_n_112\ : STD_LOGIC;
signal \x_addr_out3__1_n_113\ : STD_LOGIC;
signal \x_addr_out3__1_n_114\ : STD_LOGIC;
signal \x_addr_out3__1_n_115\ : STD_LOGIC;
signal \x_addr_out3__1_n_116\ : STD_LOGIC;
signal \x_addr_out3__1_n_117\ : STD_LOGIC;
signal \x_addr_out3__1_n_118\ : STD_LOGIC;
signal \x_addr_out3__1_n_119\ : STD_LOGIC;
signal \x_addr_out3__1_n_120\ : STD_LOGIC;
signal \x_addr_out3__1_n_121\ : STD_LOGIC;
signal \x_addr_out3__1_n_122\ : STD_LOGIC;
signal \x_addr_out3__1_n_123\ : STD_LOGIC;
signal \x_addr_out3__1_n_124\ : STD_LOGIC;
signal \x_addr_out3__1_n_125\ : STD_LOGIC;
signal \x_addr_out3__1_n_126\ : STD_LOGIC;
signal \x_addr_out3__1_n_127\ : STD_LOGIC;
signal \x_addr_out3__1_n_128\ : STD_LOGIC;
signal \x_addr_out3__1_n_129\ : STD_LOGIC;
signal \x_addr_out3__1_n_130\ : STD_LOGIC;
signal \x_addr_out3__1_n_131\ : STD_LOGIC;
signal \x_addr_out3__1_n_132\ : STD_LOGIC;
signal \x_addr_out3__1_n_133\ : STD_LOGIC;
signal \x_addr_out3__1_n_134\ : STD_LOGIC;
signal \x_addr_out3__1_n_135\ : STD_LOGIC;
signal \x_addr_out3__1_n_136\ : STD_LOGIC;
signal \x_addr_out3__1_n_137\ : STD_LOGIC;
signal \x_addr_out3__1_n_138\ : STD_LOGIC;
signal \x_addr_out3__1_n_139\ : STD_LOGIC;
signal \x_addr_out3__1_n_140\ : STD_LOGIC;
signal \x_addr_out3__1_n_141\ : STD_LOGIC;
signal \x_addr_out3__1_n_142\ : STD_LOGIC;
signal \x_addr_out3__1_n_143\ : STD_LOGIC;
signal \x_addr_out3__1_n_144\ : STD_LOGIC;
signal \x_addr_out3__1_n_145\ : STD_LOGIC;
signal \x_addr_out3__1_n_146\ : STD_LOGIC;
signal \x_addr_out3__1_n_147\ : STD_LOGIC;
signal \x_addr_out3__1_n_148\ : STD_LOGIC;
signal \x_addr_out3__1_n_149\ : STD_LOGIC;
signal \x_addr_out3__1_n_150\ : STD_LOGIC;
signal \x_addr_out3__1_n_151\ : STD_LOGIC;
signal \x_addr_out3__1_n_152\ : STD_LOGIC;
signal \x_addr_out3__1_n_153\ : STD_LOGIC;
signal \x_addr_out3__1_n_58\ : STD_LOGIC;
signal \x_addr_out3__1_n_59\ : STD_LOGIC;
signal \x_addr_out3__1_n_60\ : STD_LOGIC;
signal \x_addr_out3__1_n_61\ : STD_LOGIC;
signal \x_addr_out3__1_n_62\ : STD_LOGIC;
signal \x_addr_out3__1_n_63\ : STD_LOGIC;
signal \x_addr_out3__1_n_64\ : STD_LOGIC;
signal \x_addr_out3__1_n_65\ : STD_LOGIC;
signal \x_addr_out3__1_n_66\ : STD_LOGIC;
signal \x_addr_out3__1_n_67\ : STD_LOGIC;
signal \x_addr_out3__1_n_68\ : STD_LOGIC;
signal \x_addr_out3__1_n_69\ : STD_LOGIC;
signal \x_addr_out3__1_n_70\ : STD_LOGIC;
signal \x_addr_out3__1_n_71\ : STD_LOGIC;
signal \x_addr_out3__1_n_72\ : STD_LOGIC;
signal \x_addr_out3__1_n_73\ : STD_LOGIC;
signal \x_addr_out3__1_n_74\ : STD_LOGIC;
signal \x_addr_out3__1_n_75\ : STD_LOGIC;
signal \x_addr_out3__1_n_76\ : STD_LOGIC;
signal \x_addr_out3__1_n_77\ : STD_LOGIC;
signal \x_addr_out3__1_n_78\ : STD_LOGIC;
signal \x_addr_out3__1_n_79\ : STD_LOGIC;
signal \x_addr_out3__1_n_80\ : STD_LOGIC;
signal \x_addr_out3__1_n_81\ : STD_LOGIC;
signal \x_addr_out3__1_n_82\ : STD_LOGIC;
signal \x_addr_out3__1_n_83\ : STD_LOGIC;
signal \x_addr_out3__1_n_84\ : STD_LOGIC;
signal \x_addr_out3__1_n_85\ : STD_LOGIC;
signal \x_addr_out3__1_n_86\ : STD_LOGIC;
signal \x_addr_out3__1_n_87\ : STD_LOGIC;
signal \x_addr_out3__1_n_88\ : STD_LOGIC;
signal \x_addr_out3__1_n_89\ : STD_LOGIC;
signal \x_addr_out3__1_n_90\ : STD_LOGIC;
signal \x_addr_out3__1_n_91\ : STD_LOGIC;
signal \x_addr_out3__1_n_92\ : STD_LOGIC;
signal \x_addr_out3__1_n_93\ : STD_LOGIC;
signal \x_addr_out3__1_n_94\ : STD_LOGIC;
signal \x_addr_out3__1_n_95\ : STD_LOGIC;
signal \x_addr_out3__1_n_96\ : STD_LOGIC;
signal \x_addr_out3__1_n_97\ : STD_LOGIC;
signal \x_addr_out3__1_n_98\ : STD_LOGIC;
signal \x_addr_out3__1_n_99\ : STD_LOGIC;
signal \x_addr_out3__2_n_100\ : STD_LOGIC;
signal \x_addr_out3__2_n_101\ : STD_LOGIC;
signal \x_addr_out3__2_n_102\ : STD_LOGIC;
signal \x_addr_out3__2_n_103\ : STD_LOGIC;
signal \x_addr_out3__2_n_104\ : STD_LOGIC;
signal \x_addr_out3__2_n_105\ : STD_LOGIC;
signal \x_addr_out3__2_n_58\ : STD_LOGIC;
signal \x_addr_out3__2_n_59\ : STD_LOGIC;
signal \x_addr_out3__2_n_60\ : STD_LOGIC;
signal \x_addr_out3__2_n_61\ : STD_LOGIC;
signal \x_addr_out3__2_n_62\ : STD_LOGIC;
signal \x_addr_out3__2_n_63\ : STD_LOGIC;
signal \x_addr_out3__2_n_64\ : STD_LOGIC;
signal \x_addr_out3__2_n_65\ : STD_LOGIC;
signal \x_addr_out3__2_n_66\ : STD_LOGIC;
signal \x_addr_out3__2_n_67\ : STD_LOGIC;
signal \x_addr_out3__2_n_68\ : STD_LOGIC;
signal \x_addr_out3__2_n_69\ : STD_LOGIC;
signal \x_addr_out3__2_n_70\ : STD_LOGIC;
signal \x_addr_out3__2_n_71\ : STD_LOGIC;
signal \x_addr_out3__2_n_72\ : STD_LOGIC;
signal \x_addr_out3__2_n_73\ : STD_LOGIC;
signal \x_addr_out3__2_n_74\ : STD_LOGIC;
signal \x_addr_out3__2_n_75\ : STD_LOGIC;
signal \x_addr_out3__2_n_76\ : STD_LOGIC;
signal \x_addr_out3__2_n_77\ : STD_LOGIC;
signal \x_addr_out3__2_n_78\ : STD_LOGIC;
signal \x_addr_out3__2_n_79\ : STD_LOGIC;
signal \x_addr_out3__2_n_80\ : STD_LOGIC;
signal \x_addr_out3__2_n_81\ : STD_LOGIC;
signal \x_addr_out3__2_n_82\ : STD_LOGIC;
signal \x_addr_out3__2_n_83\ : STD_LOGIC;
signal \x_addr_out3__2_n_84\ : STD_LOGIC;
signal \x_addr_out3__2_n_85\ : STD_LOGIC;
signal \x_addr_out3__2_n_86\ : STD_LOGIC;
signal \x_addr_out3__2_n_87\ : STD_LOGIC;
signal \x_addr_out3__2_n_88\ : STD_LOGIC;
signal \x_addr_out3__2_n_89\ : STD_LOGIC;
signal \x_addr_out3__2_n_90\ : STD_LOGIC;
signal \x_addr_out3__2_n_91\ : STD_LOGIC;
signal \x_addr_out3__2_n_92\ : STD_LOGIC;
signal \x_addr_out3__2_n_93\ : STD_LOGIC;
signal \x_addr_out3__2_n_94\ : STD_LOGIC;
signal \x_addr_out3__2_n_95\ : STD_LOGIC;
signal \x_addr_out3__2_n_96\ : STD_LOGIC;
signal \x_addr_out3__2_n_97\ : STD_LOGIC;
signal \x_addr_out3__2_n_98\ : STD_LOGIC;
signal \x_addr_out3__2_n_99\ : STD_LOGIC;
signal x_addr_out3_n_100 : STD_LOGIC;
signal x_addr_out3_n_101 : STD_LOGIC;
signal x_addr_out3_n_102 : STD_LOGIC;
signal x_addr_out3_n_103 : STD_LOGIC;
signal x_addr_out3_n_104 : STD_LOGIC;
signal x_addr_out3_n_105 : STD_LOGIC;
signal x_addr_out3_n_106 : STD_LOGIC;
signal x_addr_out3_n_107 : STD_LOGIC;
signal x_addr_out3_n_108 : STD_LOGIC;
signal x_addr_out3_n_109 : STD_LOGIC;
signal x_addr_out3_n_110 : STD_LOGIC;
signal x_addr_out3_n_111 : STD_LOGIC;
signal x_addr_out3_n_112 : STD_LOGIC;
signal x_addr_out3_n_113 : STD_LOGIC;
signal x_addr_out3_n_114 : STD_LOGIC;
signal x_addr_out3_n_115 : STD_LOGIC;
signal x_addr_out3_n_116 : STD_LOGIC;
signal x_addr_out3_n_117 : STD_LOGIC;
signal x_addr_out3_n_118 : STD_LOGIC;
signal x_addr_out3_n_119 : STD_LOGIC;
signal x_addr_out3_n_120 : STD_LOGIC;
signal x_addr_out3_n_121 : STD_LOGIC;
signal x_addr_out3_n_122 : STD_LOGIC;
signal x_addr_out3_n_123 : STD_LOGIC;
signal x_addr_out3_n_124 : STD_LOGIC;
signal x_addr_out3_n_125 : STD_LOGIC;
signal x_addr_out3_n_126 : STD_LOGIC;
signal x_addr_out3_n_127 : STD_LOGIC;
signal x_addr_out3_n_128 : STD_LOGIC;
signal x_addr_out3_n_129 : STD_LOGIC;
signal x_addr_out3_n_130 : STD_LOGIC;
signal x_addr_out3_n_131 : STD_LOGIC;
signal x_addr_out3_n_132 : STD_LOGIC;
signal x_addr_out3_n_133 : STD_LOGIC;
signal x_addr_out3_n_134 : STD_LOGIC;
signal x_addr_out3_n_135 : STD_LOGIC;
signal x_addr_out3_n_136 : STD_LOGIC;
signal x_addr_out3_n_137 : STD_LOGIC;
signal x_addr_out3_n_138 : STD_LOGIC;
signal x_addr_out3_n_139 : STD_LOGIC;
signal x_addr_out3_n_140 : STD_LOGIC;
signal x_addr_out3_n_141 : STD_LOGIC;
signal x_addr_out3_n_142 : STD_LOGIC;
signal x_addr_out3_n_143 : STD_LOGIC;
signal x_addr_out3_n_144 : STD_LOGIC;
signal x_addr_out3_n_145 : STD_LOGIC;
signal x_addr_out3_n_146 : STD_LOGIC;
signal x_addr_out3_n_147 : STD_LOGIC;
signal x_addr_out3_n_148 : STD_LOGIC;
signal x_addr_out3_n_149 : STD_LOGIC;
signal x_addr_out3_n_150 : STD_LOGIC;
signal x_addr_out3_n_151 : STD_LOGIC;
signal x_addr_out3_n_152 : STD_LOGIC;
signal x_addr_out3_n_153 : STD_LOGIC;
signal x_addr_out3_n_58 : STD_LOGIC;
signal x_addr_out3_n_59 : STD_LOGIC;
signal x_addr_out3_n_60 : STD_LOGIC;
signal x_addr_out3_n_61 : STD_LOGIC;
signal x_addr_out3_n_62 : STD_LOGIC;
signal x_addr_out3_n_63 : STD_LOGIC;
signal x_addr_out3_n_64 : STD_LOGIC;
signal x_addr_out3_n_65 : STD_LOGIC;
signal x_addr_out3_n_66 : STD_LOGIC;
signal x_addr_out3_n_67 : STD_LOGIC;
signal x_addr_out3_n_68 : STD_LOGIC;
signal x_addr_out3_n_69 : STD_LOGIC;
signal x_addr_out3_n_70 : STD_LOGIC;
signal x_addr_out3_n_71 : STD_LOGIC;
signal x_addr_out3_n_72 : STD_LOGIC;
signal x_addr_out3_n_73 : STD_LOGIC;
signal x_addr_out3_n_74 : STD_LOGIC;
signal x_addr_out3_n_75 : STD_LOGIC;
signal x_addr_out3_n_76 : STD_LOGIC;
signal x_addr_out3_n_77 : STD_LOGIC;
signal x_addr_out3_n_78 : STD_LOGIC;
signal x_addr_out3_n_79 : STD_LOGIC;
signal x_addr_out3_n_80 : STD_LOGIC;
signal x_addr_out3_n_81 : STD_LOGIC;
signal x_addr_out3_n_82 : STD_LOGIC;
signal x_addr_out3_n_83 : STD_LOGIC;
signal x_addr_out3_n_84 : STD_LOGIC;
signal x_addr_out3_n_85 : STD_LOGIC;
signal x_addr_out3_n_86 : STD_LOGIC;
signal x_addr_out3_n_87 : STD_LOGIC;
signal x_addr_out3_n_88 : STD_LOGIC;
signal x_addr_out3_n_89 : STD_LOGIC;
signal x_addr_out3_n_90 : STD_LOGIC;
signal x_addr_out3_n_91 : STD_LOGIC;
signal x_addr_out3_n_92 : STD_LOGIC;
signal x_addr_out3_n_93 : STD_LOGIC;
signal x_addr_out3_n_94 : STD_LOGIC;
signal x_addr_out3_n_95 : STD_LOGIC;
signal x_addr_out3_n_96 : STD_LOGIC;
signal x_addr_out3_n_97 : STD_LOGIC;
signal x_addr_out3_n_98 : STD_LOGIC;
signal x_addr_out3_n_99 : STD_LOGIC;
signal \x_addr_out[0]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[1]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[2]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[3]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[4]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[5]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[6]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[7]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[8]_i_1_n_0\ : STD_LOGIC;
signal \x_addr_out[9]_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \y_addr_out0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \y_addr_out0_carry__0_n_0\ : STD_LOGIC;
signal \y_addr_out0_carry__0_n_1\ : STD_LOGIC;
signal \y_addr_out0_carry__0_n_2\ : STD_LOGIC;
signal \y_addr_out0_carry__0_n_3\ : STD_LOGIC;
signal \y_addr_out0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out0_carry__1_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out0_carry__1_n_3\ : STD_LOGIC;
signal y_addr_out0_carry_i_1_n_0 : STD_LOGIC;
signal y_addr_out0_carry_i_2_n_0 : STD_LOGIC;
signal y_addr_out0_carry_i_3_n_0 : STD_LOGIC;
signal y_addr_out0_carry_i_4_n_0 : STD_LOGIC;
signal y_addr_out0_carry_n_0 : STD_LOGIC;
signal y_addr_out0_carry_n_1 : STD_LOGIC;
signal y_addr_out0_carry_n_2 : STD_LOGIC;
signal y_addr_out0_carry_n_3 : STD_LOGIC;
signal y_addr_out2 : STD_LOGIC_VECTOR ( 37 downto 28 );
signal \y_addr_out2_carry__0_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__0_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__0_i_3_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__0_i_4_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__0_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__0_n_1\ : STD_LOGIC;
signal \y_addr_out2_carry__0_n_2\ : STD_LOGIC;
signal \y_addr_out2_carry__0_n_3\ : STD_LOGIC;
signal \y_addr_out2_carry__1_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__1_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__1_i_3_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__1_i_4_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__1_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__1_n_1\ : STD_LOGIC;
signal \y_addr_out2_carry__1_n_2\ : STD_LOGIC;
signal \y_addr_out2_carry__1_n_3\ : STD_LOGIC;
signal \y_addr_out2_carry__2_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__2_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__2_i_3_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__2_i_4_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__2_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__2_n_1\ : STD_LOGIC;
signal \y_addr_out2_carry__2_n_2\ : STD_LOGIC;
signal \y_addr_out2_carry__2_n_3\ : STD_LOGIC;
signal \y_addr_out2_carry__3_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__3_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__3_i_3_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__3_i_4_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__3_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__3_n_1\ : STD_LOGIC;
signal \y_addr_out2_carry__3_n_2\ : STD_LOGIC;
signal \y_addr_out2_carry__3_n_3\ : STD_LOGIC;
signal \y_addr_out2_carry__4_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__4_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__4_i_3_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__4_i_4_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__4_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__4_n_1\ : STD_LOGIC;
signal \y_addr_out2_carry__4_n_2\ : STD_LOGIC;
signal \y_addr_out2_carry__4_n_3\ : STD_LOGIC;
signal \y_addr_out2_carry__5_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__5_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__5_i_3_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__5_i_4_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__5_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__5_n_1\ : STD_LOGIC;
signal \y_addr_out2_carry__5_n_2\ : STD_LOGIC;
signal \y_addr_out2_carry__5_n_3\ : STD_LOGIC;
signal \y_addr_out2_carry__6_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__6_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__6_i_3_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__6_i_4_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__6_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__6_n_1\ : STD_LOGIC;
signal \y_addr_out2_carry__6_n_2\ : STD_LOGIC;
signal \y_addr_out2_carry__6_n_3\ : STD_LOGIC;
signal \y_addr_out2_carry__7_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__7_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__7_i_3_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__7_i_4_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__7_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__7_n_1\ : STD_LOGIC;
signal \y_addr_out2_carry__7_n_2\ : STD_LOGIC;
signal \y_addr_out2_carry__7_n_3\ : STD_LOGIC;
signal \y_addr_out2_carry__8_i_1_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__8_i_2_n_0\ : STD_LOGIC;
signal \y_addr_out2_carry__8_n_3\ : STD_LOGIC;
signal y_addr_out2_carry_i_1_n_0 : STD_LOGIC;
signal y_addr_out2_carry_i_2_n_0 : STD_LOGIC;
signal y_addr_out2_carry_i_3_n_0 : STD_LOGIC;
signal y_addr_out2_carry_i_4_n_0 : STD_LOGIC;
signal y_addr_out2_carry_n_0 : STD_LOGIC;
signal y_addr_out2_carry_n_1 : STD_LOGIC;
signal y_addr_out2_carry_n_2 : STD_LOGIC;
signal y_addr_out2_carry_n_3 : STD_LOGIC;
signal \y_addr_out3__0_n_100\ : STD_LOGIC;
signal \y_addr_out3__0_n_101\ : STD_LOGIC;
signal \y_addr_out3__0_n_102\ : STD_LOGIC;
signal \y_addr_out3__0_n_103\ : STD_LOGIC;
signal \y_addr_out3__0_n_104\ : STD_LOGIC;
signal \y_addr_out3__0_n_105\ : STD_LOGIC;
signal \y_addr_out3__0_n_58\ : STD_LOGIC;
signal \y_addr_out3__0_n_59\ : STD_LOGIC;
signal \y_addr_out3__0_n_60\ : STD_LOGIC;
signal \y_addr_out3__0_n_61\ : STD_LOGIC;
signal \y_addr_out3__0_n_62\ : STD_LOGIC;
signal \y_addr_out3__0_n_63\ : STD_LOGIC;
signal \y_addr_out3__0_n_64\ : STD_LOGIC;
signal \y_addr_out3__0_n_65\ : STD_LOGIC;
signal \y_addr_out3__0_n_66\ : STD_LOGIC;
signal \y_addr_out3__0_n_67\ : STD_LOGIC;
signal \y_addr_out3__0_n_68\ : STD_LOGIC;
signal \y_addr_out3__0_n_69\ : STD_LOGIC;
signal \y_addr_out3__0_n_70\ : STD_LOGIC;
signal \y_addr_out3__0_n_71\ : STD_LOGIC;
signal \y_addr_out3__0_n_72\ : STD_LOGIC;
signal \y_addr_out3__0_n_73\ : STD_LOGIC;
signal \y_addr_out3__0_n_74\ : STD_LOGIC;
signal \y_addr_out3__0_n_75\ : STD_LOGIC;
signal \y_addr_out3__0_n_76\ : STD_LOGIC;
signal \y_addr_out3__0_n_77\ : STD_LOGIC;
signal \y_addr_out3__0_n_78\ : STD_LOGIC;
signal \y_addr_out3__0_n_79\ : STD_LOGIC;
signal \y_addr_out3__0_n_80\ : STD_LOGIC;
signal \y_addr_out3__0_n_81\ : STD_LOGIC;
signal \y_addr_out3__0_n_82\ : STD_LOGIC;
signal \y_addr_out3__0_n_83\ : STD_LOGIC;
signal \y_addr_out3__0_n_84\ : STD_LOGIC;
signal \y_addr_out3__0_n_85\ : STD_LOGIC;
signal \y_addr_out3__0_n_86\ : STD_LOGIC;
signal \y_addr_out3__0_n_87\ : STD_LOGIC;
signal \y_addr_out3__0_n_88\ : STD_LOGIC;
signal \y_addr_out3__0_n_89\ : STD_LOGIC;
signal \y_addr_out3__0_n_90\ : STD_LOGIC;
signal \y_addr_out3__0_n_91\ : STD_LOGIC;
signal \y_addr_out3__0_n_92\ : STD_LOGIC;
signal \y_addr_out3__0_n_93\ : STD_LOGIC;
signal \y_addr_out3__0_n_94\ : STD_LOGIC;
signal \y_addr_out3__0_n_95\ : STD_LOGIC;
signal \y_addr_out3__0_n_96\ : STD_LOGIC;
signal \y_addr_out3__0_n_97\ : STD_LOGIC;
signal \y_addr_out3__0_n_98\ : STD_LOGIC;
signal \y_addr_out3__0_n_99\ : STD_LOGIC;
signal \y_addr_out3__1_n_100\ : STD_LOGIC;
signal \y_addr_out3__1_n_101\ : STD_LOGIC;
signal \y_addr_out3__1_n_102\ : STD_LOGIC;
signal \y_addr_out3__1_n_103\ : STD_LOGIC;
signal \y_addr_out3__1_n_104\ : STD_LOGIC;
signal \y_addr_out3__1_n_105\ : STD_LOGIC;
signal \y_addr_out3__1_n_106\ : STD_LOGIC;
signal \y_addr_out3__1_n_107\ : STD_LOGIC;
signal \y_addr_out3__1_n_108\ : STD_LOGIC;
signal \y_addr_out3__1_n_109\ : STD_LOGIC;
signal \y_addr_out3__1_n_110\ : STD_LOGIC;
signal \y_addr_out3__1_n_111\ : STD_LOGIC;
signal \y_addr_out3__1_n_112\ : STD_LOGIC;
signal \y_addr_out3__1_n_113\ : STD_LOGIC;
signal \y_addr_out3__1_n_114\ : STD_LOGIC;
signal \y_addr_out3__1_n_115\ : STD_LOGIC;
signal \y_addr_out3__1_n_116\ : STD_LOGIC;
signal \y_addr_out3__1_n_117\ : STD_LOGIC;
signal \y_addr_out3__1_n_118\ : STD_LOGIC;
signal \y_addr_out3__1_n_119\ : STD_LOGIC;
signal \y_addr_out3__1_n_120\ : STD_LOGIC;
signal \y_addr_out3__1_n_121\ : STD_LOGIC;
signal \y_addr_out3__1_n_122\ : STD_LOGIC;
signal \y_addr_out3__1_n_123\ : STD_LOGIC;
signal \y_addr_out3__1_n_124\ : STD_LOGIC;
signal \y_addr_out3__1_n_125\ : STD_LOGIC;
signal \y_addr_out3__1_n_126\ : STD_LOGIC;
signal \y_addr_out3__1_n_127\ : STD_LOGIC;
signal \y_addr_out3__1_n_128\ : STD_LOGIC;
signal \y_addr_out3__1_n_129\ : STD_LOGIC;
signal \y_addr_out3__1_n_130\ : STD_LOGIC;
signal \y_addr_out3__1_n_131\ : STD_LOGIC;
signal \y_addr_out3__1_n_132\ : STD_LOGIC;
signal \y_addr_out3__1_n_133\ : STD_LOGIC;
signal \y_addr_out3__1_n_134\ : STD_LOGIC;
signal \y_addr_out3__1_n_135\ : STD_LOGIC;
signal \y_addr_out3__1_n_136\ : STD_LOGIC;
signal \y_addr_out3__1_n_137\ : STD_LOGIC;
signal \y_addr_out3__1_n_138\ : STD_LOGIC;
signal \y_addr_out3__1_n_139\ : STD_LOGIC;
signal \y_addr_out3__1_n_140\ : STD_LOGIC;
signal \y_addr_out3__1_n_141\ : STD_LOGIC;
signal \y_addr_out3__1_n_142\ : STD_LOGIC;
signal \y_addr_out3__1_n_143\ : STD_LOGIC;
signal \y_addr_out3__1_n_144\ : STD_LOGIC;
signal \y_addr_out3__1_n_145\ : STD_LOGIC;
signal \y_addr_out3__1_n_146\ : STD_LOGIC;
signal \y_addr_out3__1_n_147\ : STD_LOGIC;
signal \y_addr_out3__1_n_148\ : STD_LOGIC;
signal \y_addr_out3__1_n_149\ : STD_LOGIC;
signal \y_addr_out3__1_n_150\ : STD_LOGIC;
signal \y_addr_out3__1_n_151\ : STD_LOGIC;
signal \y_addr_out3__1_n_152\ : STD_LOGIC;
signal \y_addr_out3__1_n_153\ : STD_LOGIC;
signal \y_addr_out3__1_n_58\ : STD_LOGIC;
signal \y_addr_out3__1_n_59\ : STD_LOGIC;
signal \y_addr_out3__1_n_60\ : STD_LOGIC;
signal \y_addr_out3__1_n_61\ : STD_LOGIC;
signal \y_addr_out3__1_n_62\ : STD_LOGIC;
signal \y_addr_out3__1_n_63\ : STD_LOGIC;
signal \y_addr_out3__1_n_64\ : STD_LOGIC;
signal \y_addr_out3__1_n_65\ : STD_LOGIC;
signal \y_addr_out3__1_n_66\ : STD_LOGIC;
signal \y_addr_out3__1_n_67\ : STD_LOGIC;
signal \y_addr_out3__1_n_68\ : STD_LOGIC;
signal \y_addr_out3__1_n_69\ : STD_LOGIC;
signal \y_addr_out3__1_n_70\ : STD_LOGIC;
signal \y_addr_out3__1_n_71\ : STD_LOGIC;
signal \y_addr_out3__1_n_72\ : STD_LOGIC;
signal \y_addr_out3__1_n_73\ : STD_LOGIC;
signal \y_addr_out3__1_n_74\ : STD_LOGIC;
signal \y_addr_out3__1_n_75\ : STD_LOGIC;
signal \y_addr_out3__1_n_76\ : STD_LOGIC;
signal \y_addr_out3__1_n_77\ : STD_LOGIC;
signal \y_addr_out3__1_n_78\ : STD_LOGIC;
signal \y_addr_out3__1_n_79\ : STD_LOGIC;
signal \y_addr_out3__1_n_80\ : STD_LOGIC;
signal \y_addr_out3__1_n_81\ : STD_LOGIC;
signal \y_addr_out3__1_n_82\ : STD_LOGIC;
signal \y_addr_out3__1_n_83\ : STD_LOGIC;
signal \y_addr_out3__1_n_84\ : STD_LOGIC;
signal \y_addr_out3__1_n_85\ : STD_LOGIC;
signal \y_addr_out3__1_n_86\ : STD_LOGIC;
signal \y_addr_out3__1_n_87\ : STD_LOGIC;
signal \y_addr_out3__1_n_88\ : STD_LOGIC;
signal \y_addr_out3__1_n_89\ : STD_LOGIC;
signal \y_addr_out3__1_n_90\ : STD_LOGIC;
signal \y_addr_out3__1_n_91\ : STD_LOGIC;
signal \y_addr_out3__1_n_92\ : STD_LOGIC;
signal \y_addr_out3__1_n_93\ : STD_LOGIC;
signal \y_addr_out3__1_n_94\ : STD_LOGIC;
signal \y_addr_out3__1_n_95\ : STD_LOGIC;
signal \y_addr_out3__1_n_96\ : STD_LOGIC;
signal \y_addr_out3__1_n_97\ : STD_LOGIC;
signal \y_addr_out3__1_n_98\ : STD_LOGIC;
signal \y_addr_out3__1_n_99\ : STD_LOGIC;
signal \y_addr_out3__2_n_100\ : STD_LOGIC;
signal \y_addr_out3__2_n_101\ : STD_LOGIC;
signal \y_addr_out3__2_n_102\ : STD_LOGIC;
signal \y_addr_out3__2_n_103\ : STD_LOGIC;
signal \y_addr_out3__2_n_104\ : STD_LOGIC;
signal \y_addr_out3__2_n_105\ : STD_LOGIC;
signal \y_addr_out3__2_n_58\ : STD_LOGIC;
signal \y_addr_out3__2_n_59\ : STD_LOGIC;
signal \y_addr_out3__2_n_60\ : STD_LOGIC;
signal \y_addr_out3__2_n_61\ : STD_LOGIC;
signal \y_addr_out3__2_n_62\ : STD_LOGIC;
signal \y_addr_out3__2_n_63\ : STD_LOGIC;
signal \y_addr_out3__2_n_64\ : STD_LOGIC;
signal \y_addr_out3__2_n_65\ : STD_LOGIC;
signal \y_addr_out3__2_n_66\ : STD_LOGIC;
signal \y_addr_out3__2_n_67\ : STD_LOGIC;
signal \y_addr_out3__2_n_68\ : STD_LOGIC;
signal \y_addr_out3__2_n_69\ : STD_LOGIC;
signal \y_addr_out3__2_n_70\ : STD_LOGIC;
signal \y_addr_out3__2_n_71\ : STD_LOGIC;
signal \y_addr_out3__2_n_72\ : STD_LOGIC;
signal \y_addr_out3__2_n_73\ : STD_LOGIC;
signal \y_addr_out3__2_n_74\ : STD_LOGIC;
signal \y_addr_out3__2_n_75\ : STD_LOGIC;
signal \y_addr_out3__2_n_76\ : STD_LOGIC;
signal \y_addr_out3__2_n_77\ : STD_LOGIC;
signal \y_addr_out3__2_n_78\ : STD_LOGIC;
signal \y_addr_out3__2_n_79\ : STD_LOGIC;
signal \y_addr_out3__2_n_80\ : STD_LOGIC;
signal \y_addr_out3__2_n_81\ : STD_LOGIC;
signal \y_addr_out3__2_n_82\ : STD_LOGIC;
signal \y_addr_out3__2_n_83\ : STD_LOGIC;
signal \y_addr_out3__2_n_84\ : STD_LOGIC;
signal \y_addr_out3__2_n_85\ : STD_LOGIC;
signal \y_addr_out3__2_n_86\ : STD_LOGIC;
signal \y_addr_out3__2_n_87\ : STD_LOGIC;
signal \y_addr_out3__2_n_88\ : STD_LOGIC;
signal \y_addr_out3__2_n_89\ : STD_LOGIC;
signal \y_addr_out3__2_n_90\ : STD_LOGIC;
signal \y_addr_out3__2_n_91\ : STD_LOGIC;
signal \y_addr_out3__2_n_92\ : STD_LOGIC;
signal \y_addr_out3__2_n_93\ : STD_LOGIC;
signal \y_addr_out3__2_n_94\ : STD_LOGIC;
signal \y_addr_out3__2_n_95\ : STD_LOGIC;
signal \y_addr_out3__2_n_96\ : STD_LOGIC;
signal \y_addr_out3__2_n_97\ : STD_LOGIC;
signal \y_addr_out3__2_n_98\ : STD_LOGIC;
signal \y_addr_out3__2_n_99\ : STD_LOGIC;
signal y_addr_out3_n_100 : STD_LOGIC;
signal y_addr_out3_n_101 : STD_LOGIC;
signal y_addr_out3_n_102 : STD_LOGIC;
signal y_addr_out3_n_103 : STD_LOGIC;
signal y_addr_out3_n_104 : STD_LOGIC;
signal y_addr_out3_n_105 : STD_LOGIC;
signal y_addr_out3_n_106 : STD_LOGIC;
signal y_addr_out3_n_107 : STD_LOGIC;
signal y_addr_out3_n_108 : STD_LOGIC;
signal y_addr_out3_n_109 : STD_LOGIC;
signal y_addr_out3_n_110 : STD_LOGIC;
signal y_addr_out3_n_111 : STD_LOGIC;
signal y_addr_out3_n_112 : STD_LOGIC;
signal y_addr_out3_n_113 : STD_LOGIC;
signal y_addr_out3_n_114 : STD_LOGIC;
signal y_addr_out3_n_115 : STD_LOGIC;
signal y_addr_out3_n_116 : STD_LOGIC;
signal y_addr_out3_n_117 : STD_LOGIC;
signal y_addr_out3_n_118 : STD_LOGIC;
signal y_addr_out3_n_119 : STD_LOGIC;
signal y_addr_out3_n_120 : STD_LOGIC;
signal y_addr_out3_n_121 : STD_LOGIC;
signal y_addr_out3_n_122 : STD_LOGIC;
signal y_addr_out3_n_123 : STD_LOGIC;
signal y_addr_out3_n_124 : STD_LOGIC;
signal y_addr_out3_n_125 : STD_LOGIC;
signal y_addr_out3_n_126 : STD_LOGIC;
signal y_addr_out3_n_127 : STD_LOGIC;
signal y_addr_out3_n_128 : STD_LOGIC;
signal y_addr_out3_n_129 : STD_LOGIC;
signal y_addr_out3_n_130 : STD_LOGIC;
signal y_addr_out3_n_131 : STD_LOGIC;
signal y_addr_out3_n_132 : STD_LOGIC;
signal y_addr_out3_n_133 : STD_LOGIC;
signal y_addr_out3_n_134 : STD_LOGIC;
signal y_addr_out3_n_135 : STD_LOGIC;
signal y_addr_out3_n_136 : STD_LOGIC;
signal y_addr_out3_n_137 : STD_LOGIC;
signal y_addr_out3_n_138 : STD_LOGIC;
signal y_addr_out3_n_139 : STD_LOGIC;
signal y_addr_out3_n_140 : STD_LOGIC;
signal y_addr_out3_n_141 : STD_LOGIC;
signal y_addr_out3_n_142 : STD_LOGIC;
signal y_addr_out3_n_143 : STD_LOGIC;
signal y_addr_out3_n_144 : STD_LOGIC;
signal y_addr_out3_n_145 : STD_LOGIC;
signal y_addr_out3_n_146 : STD_LOGIC;
signal y_addr_out3_n_147 : STD_LOGIC;
signal y_addr_out3_n_148 : STD_LOGIC;
signal y_addr_out3_n_149 : STD_LOGIC;
signal y_addr_out3_n_150 : STD_LOGIC;
signal y_addr_out3_n_151 : STD_LOGIC;
signal y_addr_out3_n_152 : STD_LOGIC;
signal y_addr_out3_n_153 : STD_LOGIC;
signal y_addr_out3_n_58 : STD_LOGIC;
signal y_addr_out3_n_59 : STD_LOGIC;
signal y_addr_out3_n_60 : STD_LOGIC;
signal y_addr_out3_n_61 : STD_LOGIC;
signal y_addr_out3_n_62 : STD_LOGIC;
signal y_addr_out3_n_63 : STD_LOGIC;
signal y_addr_out3_n_64 : STD_LOGIC;
signal y_addr_out3_n_65 : STD_LOGIC;
signal y_addr_out3_n_66 : STD_LOGIC;
signal y_addr_out3_n_67 : STD_LOGIC;
signal y_addr_out3_n_68 : STD_LOGIC;
signal y_addr_out3_n_69 : STD_LOGIC;
signal y_addr_out3_n_70 : STD_LOGIC;
signal y_addr_out3_n_71 : STD_LOGIC;
signal y_addr_out3_n_72 : STD_LOGIC;
signal y_addr_out3_n_73 : STD_LOGIC;
signal y_addr_out3_n_74 : STD_LOGIC;
signal y_addr_out3_n_75 : STD_LOGIC;
signal y_addr_out3_n_76 : STD_LOGIC;
signal y_addr_out3_n_77 : STD_LOGIC;
signal y_addr_out3_n_78 : STD_LOGIC;
signal y_addr_out3_n_79 : STD_LOGIC;
signal y_addr_out3_n_80 : STD_LOGIC;
signal y_addr_out3_n_81 : STD_LOGIC;
signal y_addr_out3_n_82 : STD_LOGIC;
signal y_addr_out3_n_83 : STD_LOGIC;
signal y_addr_out3_n_84 : STD_LOGIC;
signal y_addr_out3_n_85 : STD_LOGIC;
signal y_addr_out3_n_86 : STD_LOGIC;
signal y_addr_out3_n_87 : STD_LOGIC;
signal y_addr_out3_n_88 : STD_LOGIC;
signal y_addr_out3_n_89 : STD_LOGIC;
signal y_addr_out3_n_90 : STD_LOGIC;
signal y_addr_out3_n_91 : STD_LOGIC;
signal y_addr_out3_n_92 : STD_LOGIC;
signal y_addr_out3_n_93 : STD_LOGIC;
signal y_addr_out3_n_94 : STD_LOGIC;
signal y_addr_out3_n_95 : STD_LOGIC;
signal y_addr_out3_n_96 : STD_LOGIC;
signal y_addr_out3_n_97 : STD_LOGIC;
signal y_addr_out3_n_98 : STD_LOGIC;
signal y_addr_out3_n_99 : STD_LOGIC;
signal NLW_x_addr_out0_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_x_addr_out0_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_x_addr_out0_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_x_addr_out2_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_x_addr_out2_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_x_addr_out2_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_x_addr_out2_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_x_addr_out2_carry__3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_x_addr_out2_carry__4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_x_addr_out2_carry__5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_x_addr_out2_carry__8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_x_addr_out2_carry__8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_x_addr_out3_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_x_addr_out3_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_x_addr_out3_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_x_addr_out3_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_x_addr_out3_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_x_addr_out3_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_x_addr_out3_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_x_addr_out3_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_x_addr_out3_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_x_addr_out3__0_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__0_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__0_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__0_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__0_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__0_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__0_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_x_addr_out3__0_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_x_addr_out3__0_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_x_addr_out3__0_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_x_addr_out3__1_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__1_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__1_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__1_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__1_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__1_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__1_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_x_addr_out3__1_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_x_addr_out3__1_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_x_addr_out3__2_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__2_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__2_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__2_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__2_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__2_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_x_addr_out3__2_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_x_addr_out3__2_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_x_addr_out3__2_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_x_addr_out3__2_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_y_addr_out0_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_y_addr_out0_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_addr_out0_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_y_addr_out2_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_addr_out2_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_addr_out2_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_addr_out2_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_addr_out2_carry__3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_addr_out2_carry__4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_addr_out2_carry__5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_addr_out2_carry__8_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_y_addr_out2_carry__8_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_y_addr_out3_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_y_addr_out3_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_y_addr_out3_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_y_addr_out3_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_y_addr_out3_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_y_addr_out3_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_y_addr_out3_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_y_addr_out3_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_y_addr_out3_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_addr_out3__0_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__0_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__0_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__0_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__0_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__0_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__0_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_y_addr_out3__0_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_y_addr_out3__0_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_addr_out3__0_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_y_addr_out3__1_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__1_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__1_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__1_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__1_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__1_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__1_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_y_addr_out3__1_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_y_addr_out3__1_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_addr_out3__2_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__2_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__2_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__2_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__2_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__2_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_y_addr_out3__2_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_y_addr_out3__2_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_y_addr_out3__2_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_y_addr_out3__2_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of x_addr_out3 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \x_addr_out3__0\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \x_addr_out3__1\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \x_addr_out3__2\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \x_addr_out[1]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \x_addr_out[2]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \x_addr_out[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \x_addr_out[4]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \x_addr_out[5]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \x_addr_out[6]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \x_addr_out[7]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \x_addr_out[8]_i_1\ : label is "soft_lutpair3";
attribute METHODOLOGY_DRC_VIOS of y_addr_out3 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \y_addr_out3__0\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \y_addr_out3__1\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \y_addr_out3__2\ : label is "{SYNTH-13 {cell *THIS*}}";
begin
x_addr_out0_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => x_addr_out0_carry_n_0,
CO(2) => x_addr_out0_carry_n_1,
CO(1) => x_addr_out0_carry_n_2,
CO(0) => x_addr_out0_carry_n_3,
CYINIT => '0',
DI(3 downto 0) => p_1_in(17 downto 14),
O(3 downto 1) => x_addr_out0(17 downto 15),
O(0) => NLW_x_addr_out0_carry_O_UNCONNECTED(0),
S(3) => x_addr_out0_carry_i_1_n_0,
S(2) => x_addr_out0_carry_i_2_n_0,
S(1) => x_addr_out0_carry_i_3_n_0,
S(0) => x_addr_out0(14)
);
\x_addr_out0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => x_addr_out0_carry_n_0,
CO(3) => \x_addr_out0_carry__0_n_0\,
CO(2) => \x_addr_out0_carry__0_n_1\,
CO(1) => \x_addr_out0_carry__0_n_2\,
CO(0) => \x_addr_out0_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => p_1_in(21 downto 18),
O(3 downto 0) => x_addr_out0(21 downto 18),
S(3) => \x_addr_out0_carry__0_i_1_n_0\,
S(2) => \x_addr_out0_carry__0_i_2_n_0\,
S(1) => \x_addr_out0_carry__0_i_3_n_0\,
S(0) => \x_addr_out0_carry__0_i_4_n_0\
);
\x_addr_out0_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_1_in(21),
I1 => t_x(7),
O => \x_addr_out0_carry__0_i_1_n_0\
);
\x_addr_out0_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_1_in(20),
I1 => t_x(6),
O => \x_addr_out0_carry__0_i_2_n_0\
);
\x_addr_out0_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_1_in(19),
I1 => t_x(5),
O => \x_addr_out0_carry__0_i_3_n_0\
);
\x_addr_out0_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_1_in(18),
I1 => t_x(4),
O => \x_addr_out0_carry__0_i_4_n_0\
);
\x_addr_out0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \x_addr_out0_carry__0_n_0\,
CO(3 downto 1) => \NLW_x_addr_out0_carry__1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \x_addr_out0_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => p_1_in(22),
O(3 downto 2) => \NLW_x_addr_out0_carry__1_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => x_addr_out0(23 downto 22),
S(3 downto 2) => B"00",
S(1) => \x_addr_out0_carry__1_i_1_n_0\,
S(0) => \x_addr_out0_carry__1_i_2_n_0\
);
\x_addr_out0_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_1_in(23),
I1 => t_x(9),
O => \x_addr_out0_carry__1_i_1_n_0\
);
\x_addr_out0_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_1_in(22),
I1 => t_x(8),
O => \x_addr_out0_carry__1_i_2_n_0\
);
x_addr_out0_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_1_in(17),
I1 => t_x(3),
O => x_addr_out0_carry_i_1_n_0
);
x_addr_out0_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_1_in(16),
I1 => t_x(2),
O => x_addr_out0_carry_i_2_n_0
);
x_addr_out0_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_1_in(15),
I1 => t_x(1),
O => x_addr_out0_carry_i_3_n_0
);
x_addr_out0_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => p_1_in(14),
I1 => t_x(0),
O => x_addr_out0(14)
);
x_addr_out2_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => x_addr_out2_carry_n_0,
CO(2) => x_addr_out2_carry_n_1,
CO(1) => x_addr_out2_carry_n_2,
CO(0) => x_addr_out2_carry_n_3,
CYINIT => '0',
DI(3) => \x_addr_out3__1_n_102\,
DI(2) => \x_addr_out3__1_n_103\,
DI(1) => \x_addr_out3__1_n_104\,
DI(0) => \x_addr_out3__1_n_105\,
O(3 downto 0) => NLW_x_addr_out2_carry_O_UNCONNECTED(3 downto 0),
S(3) => x_addr_out2_carry_i_1_n_0,
S(2) => x_addr_out2_carry_i_2_n_0,
S(1) => x_addr_out2_carry_i_3_n_0,
S(0) => x_addr_out2_carry_i_4_n_0
);
\x_addr_out2_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => x_addr_out2_carry_n_0,
CO(3) => \x_addr_out2_carry__0_n_0\,
CO(2) => \x_addr_out2_carry__0_n_1\,
CO(1) => \x_addr_out2_carry__0_n_2\,
CO(0) => \x_addr_out2_carry__0_n_3\,
CYINIT => '0',
DI(3) => \x_addr_out3__1_n_98\,
DI(2) => \x_addr_out3__1_n_99\,
DI(1) => \x_addr_out3__1_n_100\,
DI(0) => \x_addr_out3__1_n_101\,
O(3 downto 0) => \NLW_x_addr_out2_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \x_addr_out2_carry__0_i_1_n_0\,
S(2) => \x_addr_out2_carry__0_i_2_n_0\,
S(1) => \x_addr_out2_carry__0_i_3_n_0\,
S(0) => \x_addr_out2_carry__0_i_4_n_0\
);
\x_addr_out2_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_98\,
I1 => x_addr_out3_n_98,
O => \x_addr_out2_carry__0_i_1_n_0\
);
\x_addr_out2_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_99\,
I1 => x_addr_out3_n_99,
O => \x_addr_out2_carry__0_i_2_n_0\
);
\x_addr_out2_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_100\,
I1 => x_addr_out3_n_100,
O => \x_addr_out2_carry__0_i_3_n_0\
);
\x_addr_out2_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_101\,
I1 => x_addr_out3_n_101,
O => \x_addr_out2_carry__0_i_4_n_0\
);
\x_addr_out2_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \x_addr_out2_carry__0_n_0\,
CO(3) => \x_addr_out2_carry__1_n_0\,
CO(2) => \x_addr_out2_carry__1_n_1\,
CO(1) => \x_addr_out2_carry__1_n_2\,
CO(0) => \x_addr_out2_carry__1_n_3\,
CYINIT => '0',
DI(3) => \x_addr_out3__1_n_94\,
DI(2) => \x_addr_out3__1_n_95\,
DI(1) => \x_addr_out3__1_n_96\,
DI(0) => \x_addr_out3__1_n_97\,
O(3 downto 0) => \NLW_x_addr_out2_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \x_addr_out2_carry__1_i_1_n_0\,
S(2) => \x_addr_out2_carry__1_i_2_n_0\,
S(1) => \x_addr_out2_carry__1_i_3_n_0\,
S(0) => \x_addr_out2_carry__1_i_4_n_0\
);
\x_addr_out2_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_94\,
I1 => x_addr_out3_n_94,
O => \x_addr_out2_carry__1_i_1_n_0\
);
\x_addr_out2_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_95\,
I1 => x_addr_out3_n_95,
O => \x_addr_out2_carry__1_i_2_n_0\
);
\x_addr_out2_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_96\,
I1 => x_addr_out3_n_96,
O => \x_addr_out2_carry__1_i_3_n_0\
);
\x_addr_out2_carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_97\,
I1 => x_addr_out3_n_97,
O => \x_addr_out2_carry__1_i_4_n_0\
);
\x_addr_out2_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \x_addr_out2_carry__1_n_0\,
CO(3) => \x_addr_out2_carry__2_n_0\,
CO(2) => \x_addr_out2_carry__2_n_1\,
CO(1) => \x_addr_out2_carry__2_n_2\,
CO(0) => \x_addr_out2_carry__2_n_3\,
CYINIT => '0',
DI(3) => \x_addr_out3__1_n_90\,
DI(2) => \x_addr_out3__1_n_91\,
DI(1) => \x_addr_out3__1_n_92\,
DI(0) => \x_addr_out3__1_n_93\,
O(3 downto 0) => \NLW_x_addr_out2_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \x_addr_out2_carry__2_i_1_n_0\,
S(2) => \x_addr_out2_carry__2_i_2_n_0\,
S(1) => \x_addr_out2_carry__2_i_3_n_0\,
S(0) => \x_addr_out2_carry__2_i_4_n_0\
);
\x_addr_out2_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_90\,
I1 => x_addr_out3_n_90,
O => \x_addr_out2_carry__2_i_1_n_0\
);
\x_addr_out2_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_91\,
I1 => x_addr_out3_n_91,
O => \x_addr_out2_carry__2_i_2_n_0\
);
\x_addr_out2_carry__2_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_92\,
I1 => x_addr_out3_n_92,
O => \x_addr_out2_carry__2_i_3_n_0\
);
\x_addr_out2_carry__2_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_93\,
I1 => x_addr_out3_n_93,
O => \x_addr_out2_carry__2_i_4_n_0\
);
\x_addr_out2_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \x_addr_out2_carry__2_n_0\,
CO(3) => \x_addr_out2_carry__3_n_0\,
CO(2) => \x_addr_out2_carry__3_n_1\,
CO(1) => \x_addr_out2_carry__3_n_2\,
CO(0) => \x_addr_out2_carry__3_n_3\,
CYINIT => '0',
DI(3) => \x_addr_out3__2_n_103\,
DI(2) => \x_addr_out3__2_n_104\,
DI(1) => \x_addr_out3__2_n_105\,
DI(0) => \x_addr_out3__1_n_89\,
O(3 downto 0) => \NLW_x_addr_out2_carry__3_O_UNCONNECTED\(3 downto 0),
S(3) => \x_addr_out2_carry__3_i_1_n_0\,
S(2) => \x_addr_out2_carry__3_i_2_n_0\,
S(1) => \x_addr_out2_carry__3_i_3_n_0\,
S(0) => \x_addr_out2_carry__3_i_4_n_0\
);
\x_addr_out2_carry__3_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_103\,
I1 => \x_addr_out3__0_n_103\,
O => \x_addr_out2_carry__3_i_1_n_0\
);
\x_addr_out2_carry__3_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_104\,
I1 => \x_addr_out3__0_n_104\,
O => \x_addr_out2_carry__3_i_2_n_0\
);
\x_addr_out2_carry__3_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_105\,
I1 => \x_addr_out3__0_n_105\,
O => \x_addr_out2_carry__3_i_3_n_0\
);
\x_addr_out2_carry__3_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_89\,
I1 => x_addr_out3_n_89,
O => \x_addr_out2_carry__3_i_4_n_0\
);
\x_addr_out2_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \x_addr_out2_carry__3_n_0\,
CO(3) => \x_addr_out2_carry__4_n_0\,
CO(2) => \x_addr_out2_carry__4_n_1\,
CO(1) => \x_addr_out2_carry__4_n_2\,
CO(0) => \x_addr_out2_carry__4_n_3\,
CYINIT => '0',
DI(3) => \x_addr_out3__2_n_99\,
DI(2) => \x_addr_out3__2_n_100\,
DI(1) => \x_addr_out3__2_n_101\,
DI(0) => \x_addr_out3__2_n_102\,
O(3 downto 0) => \NLW_x_addr_out2_carry__4_O_UNCONNECTED\(3 downto 0),
S(3) => \x_addr_out2_carry__4_i_1_n_0\,
S(2) => \x_addr_out2_carry__4_i_2_n_0\,
S(1) => \x_addr_out2_carry__4_i_3_n_0\,
S(0) => \x_addr_out2_carry__4_i_4_n_0\
);
\x_addr_out2_carry__4_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_99\,
I1 => \x_addr_out3__0_n_99\,
O => \x_addr_out2_carry__4_i_1_n_0\
);
\x_addr_out2_carry__4_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_100\,
I1 => \x_addr_out3__0_n_100\,
O => \x_addr_out2_carry__4_i_2_n_0\
);
\x_addr_out2_carry__4_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_101\,
I1 => \x_addr_out3__0_n_101\,
O => \x_addr_out2_carry__4_i_3_n_0\
);
\x_addr_out2_carry__4_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_102\,
I1 => \x_addr_out3__0_n_102\,
O => \x_addr_out2_carry__4_i_4_n_0\
);
\x_addr_out2_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \x_addr_out2_carry__4_n_0\,
CO(3) => \x_addr_out2_carry__5_n_0\,
CO(2) => \x_addr_out2_carry__5_n_1\,
CO(1) => \x_addr_out2_carry__5_n_2\,
CO(0) => \x_addr_out2_carry__5_n_3\,
CYINIT => '0',
DI(3) => \x_addr_out3__2_n_95\,
DI(2) => \x_addr_out3__2_n_96\,
DI(1) => \x_addr_out3__2_n_97\,
DI(0) => \x_addr_out3__2_n_98\,
O(3 downto 0) => \NLW_x_addr_out2_carry__5_O_UNCONNECTED\(3 downto 0),
S(3) => \x_addr_out2_carry__5_i_1_n_0\,
S(2) => \x_addr_out2_carry__5_i_2_n_0\,
S(1) => \x_addr_out2_carry__5_i_3_n_0\,
S(0) => \x_addr_out2_carry__5_i_4_n_0\
);
\x_addr_out2_carry__5_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_95\,
I1 => \x_addr_out3__0_n_95\,
O => \x_addr_out2_carry__5_i_1_n_0\
);
\x_addr_out2_carry__5_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_96\,
I1 => \x_addr_out3__0_n_96\,
O => \x_addr_out2_carry__5_i_2_n_0\
);
\x_addr_out2_carry__5_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_97\,
I1 => \x_addr_out3__0_n_97\,
O => \x_addr_out2_carry__5_i_3_n_0\
);
\x_addr_out2_carry__5_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_98\,
I1 => \x_addr_out3__0_n_98\,
O => \x_addr_out2_carry__5_i_4_n_0\
);
\x_addr_out2_carry__6\: unisim.vcomponents.CARRY4
port map (
CI => \x_addr_out2_carry__5_n_0\,
CO(3) => \x_addr_out2_carry__6_n_0\,
CO(2) => \x_addr_out2_carry__6_n_1\,
CO(1) => \x_addr_out2_carry__6_n_2\,
CO(0) => \x_addr_out2_carry__6_n_3\,
CYINIT => '0',
DI(3) => \x_addr_out3__2_n_91\,
DI(2) => \x_addr_out3__2_n_92\,
DI(1) => \x_addr_out3__2_n_93\,
DI(0) => \x_addr_out3__2_n_94\,
O(3 downto 0) => p_1_in(17 downto 14),
S(3) => \x_addr_out2_carry__6_i_1_n_0\,
S(2) => \x_addr_out2_carry__6_i_2_n_0\,
S(1) => \x_addr_out2_carry__6_i_3_n_0\,
S(0) => \x_addr_out2_carry__6_i_4_n_0\
);
\x_addr_out2_carry__6_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_91\,
I1 => \x_addr_out3__0_n_91\,
O => \x_addr_out2_carry__6_i_1_n_0\
);
\x_addr_out2_carry__6_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_92\,
I1 => \x_addr_out3__0_n_92\,
O => \x_addr_out2_carry__6_i_2_n_0\
);
\x_addr_out2_carry__6_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_93\,
I1 => \x_addr_out3__0_n_93\,
O => \x_addr_out2_carry__6_i_3_n_0\
);
\x_addr_out2_carry__6_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_94\,
I1 => \x_addr_out3__0_n_94\,
O => \x_addr_out2_carry__6_i_4_n_0\
);
\x_addr_out2_carry__7\: unisim.vcomponents.CARRY4
port map (
CI => \x_addr_out2_carry__6_n_0\,
CO(3) => \x_addr_out2_carry__7_n_0\,
CO(2) => \x_addr_out2_carry__7_n_1\,
CO(1) => \x_addr_out2_carry__7_n_2\,
CO(0) => \x_addr_out2_carry__7_n_3\,
CYINIT => '0',
DI(3) => \x_addr_out3__2_n_87\,
DI(2) => \x_addr_out3__2_n_88\,
DI(1) => \x_addr_out3__2_n_89\,
DI(0) => \x_addr_out3__2_n_90\,
O(3 downto 0) => p_1_in(21 downto 18),
S(3) => \x_addr_out2_carry__7_i_1_n_0\,
S(2) => \x_addr_out2_carry__7_i_2_n_0\,
S(1) => \x_addr_out2_carry__7_i_3_n_0\,
S(0) => \x_addr_out2_carry__7_i_4_n_0\
);
\x_addr_out2_carry__7_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_87\,
I1 => \x_addr_out3__0_n_87\,
O => \x_addr_out2_carry__7_i_1_n_0\
);
\x_addr_out2_carry__7_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_88\,
I1 => \x_addr_out3__0_n_88\,
O => \x_addr_out2_carry__7_i_2_n_0\
);
\x_addr_out2_carry__7_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_89\,
I1 => \x_addr_out3__0_n_89\,
O => \x_addr_out2_carry__7_i_3_n_0\
);
\x_addr_out2_carry__7_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_90\,
I1 => \x_addr_out3__0_n_90\,
O => \x_addr_out2_carry__7_i_4_n_0\
);
\x_addr_out2_carry__8\: unisim.vcomponents.CARRY4
port map (
CI => \x_addr_out2_carry__7_n_0\,
CO(3 downto 1) => \NLW_x_addr_out2_carry__8_CO_UNCONNECTED\(3 downto 1),
CO(0) => \x_addr_out2_carry__8_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \x_addr_out3__2_n_86\,
O(3 downto 2) => \NLW_x_addr_out2_carry__8_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => p_1_in(23 downto 22),
S(3 downto 2) => B"00",
S(1) => \x_addr_out2_carry__8_i_1_n_0\,
S(0) => \x_addr_out2_carry__8_i_2_n_0\
);
\x_addr_out2_carry__8_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_85\,
I1 => \x_addr_out3__0_n_85\,
O => \x_addr_out2_carry__8_i_1_n_0\
);
\x_addr_out2_carry__8_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__2_n_86\,
I1 => \x_addr_out3__0_n_86\,
O => \x_addr_out2_carry__8_i_2_n_0\
);
x_addr_out2_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_102\,
I1 => x_addr_out3_n_102,
O => x_addr_out2_carry_i_1_n_0
);
x_addr_out2_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_103\,
I1 => x_addr_out3_n_103,
O => x_addr_out2_carry_i_2_n_0
);
x_addr_out2_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_104\,
I1 => x_addr_out3_n_104,
O => x_addr_out2_carry_i_3_n_0
);
x_addr_out2_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \x_addr_out3__1_n_105\,
I1 => x_addr_out3_n_105,
O => x_addr_out2_carry_i_4_n_0
);
x_addr_out3: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29 downto 17) => B"0000000000000",
A(16 downto 14) => y_addr_in(2 downto 0),
A(13 downto 0) => B"00000000000000",
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_x_addr_out3_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => rot_m01(15),
B(16) => rot_m01(15),
B(15 downto 0) => rot_m01(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_x_addr_out3_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_x_addr_out3_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_x_addr_out3_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_x_addr_out3_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_x_addr_out3_OVERFLOW_UNCONNECTED,
P(47) => x_addr_out3_n_58,
P(46) => x_addr_out3_n_59,
P(45) => x_addr_out3_n_60,
P(44) => x_addr_out3_n_61,
P(43) => x_addr_out3_n_62,
P(42) => x_addr_out3_n_63,
P(41) => x_addr_out3_n_64,
P(40) => x_addr_out3_n_65,
P(39) => x_addr_out3_n_66,
P(38) => x_addr_out3_n_67,
P(37) => x_addr_out3_n_68,
P(36) => x_addr_out3_n_69,
P(35) => x_addr_out3_n_70,
P(34) => x_addr_out3_n_71,
P(33) => x_addr_out3_n_72,
P(32) => x_addr_out3_n_73,
P(31) => x_addr_out3_n_74,
P(30) => x_addr_out3_n_75,
P(29) => x_addr_out3_n_76,
P(28) => x_addr_out3_n_77,
P(27) => x_addr_out3_n_78,
P(26) => x_addr_out3_n_79,
P(25) => x_addr_out3_n_80,
P(24) => x_addr_out3_n_81,
P(23) => x_addr_out3_n_82,
P(22) => x_addr_out3_n_83,
P(21) => x_addr_out3_n_84,
P(20) => x_addr_out3_n_85,
P(19) => x_addr_out3_n_86,
P(18) => x_addr_out3_n_87,
P(17) => x_addr_out3_n_88,
P(16) => x_addr_out3_n_89,
P(15) => x_addr_out3_n_90,
P(14) => x_addr_out3_n_91,
P(13) => x_addr_out3_n_92,
P(12) => x_addr_out3_n_93,
P(11) => x_addr_out3_n_94,
P(10) => x_addr_out3_n_95,
P(9) => x_addr_out3_n_96,
P(8) => x_addr_out3_n_97,
P(7) => x_addr_out3_n_98,
P(6) => x_addr_out3_n_99,
P(5) => x_addr_out3_n_100,
P(4) => x_addr_out3_n_101,
P(3) => x_addr_out3_n_102,
P(2) => x_addr_out3_n_103,
P(1) => x_addr_out3_n_104,
P(0) => x_addr_out3_n_105,
PATTERNBDETECT => NLW_x_addr_out3_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_x_addr_out3_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47) => x_addr_out3_n_106,
PCOUT(46) => x_addr_out3_n_107,
PCOUT(45) => x_addr_out3_n_108,
PCOUT(44) => x_addr_out3_n_109,
PCOUT(43) => x_addr_out3_n_110,
PCOUT(42) => x_addr_out3_n_111,
PCOUT(41) => x_addr_out3_n_112,
PCOUT(40) => x_addr_out3_n_113,
PCOUT(39) => x_addr_out3_n_114,
PCOUT(38) => x_addr_out3_n_115,
PCOUT(37) => x_addr_out3_n_116,
PCOUT(36) => x_addr_out3_n_117,
PCOUT(35) => x_addr_out3_n_118,
PCOUT(34) => x_addr_out3_n_119,
PCOUT(33) => x_addr_out3_n_120,
PCOUT(32) => x_addr_out3_n_121,
PCOUT(31) => x_addr_out3_n_122,
PCOUT(30) => x_addr_out3_n_123,
PCOUT(29) => x_addr_out3_n_124,
PCOUT(28) => x_addr_out3_n_125,
PCOUT(27) => x_addr_out3_n_126,
PCOUT(26) => x_addr_out3_n_127,
PCOUT(25) => x_addr_out3_n_128,
PCOUT(24) => x_addr_out3_n_129,
PCOUT(23) => x_addr_out3_n_130,
PCOUT(22) => x_addr_out3_n_131,
PCOUT(21) => x_addr_out3_n_132,
PCOUT(20) => x_addr_out3_n_133,
PCOUT(19) => x_addr_out3_n_134,
PCOUT(18) => x_addr_out3_n_135,
PCOUT(17) => x_addr_out3_n_136,
PCOUT(16) => x_addr_out3_n_137,
PCOUT(15) => x_addr_out3_n_138,
PCOUT(14) => x_addr_out3_n_139,
PCOUT(13) => x_addr_out3_n_140,
PCOUT(12) => x_addr_out3_n_141,
PCOUT(11) => x_addr_out3_n_142,
PCOUT(10) => x_addr_out3_n_143,
PCOUT(9) => x_addr_out3_n_144,
PCOUT(8) => x_addr_out3_n_145,
PCOUT(7) => x_addr_out3_n_146,
PCOUT(6) => x_addr_out3_n_147,
PCOUT(5) => x_addr_out3_n_148,
PCOUT(4) => x_addr_out3_n_149,
PCOUT(3) => x_addr_out3_n_150,
PCOUT(2) => x_addr_out3_n_151,
PCOUT(1) => x_addr_out3_n_152,
PCOUT(0) => x_addr_out3_n_153,
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_x_addr_out3_UNDERFLOW_UNCONNECTED
);
\x_addr_out3__0\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => rot_m01(15),
A(28) => rot_m01(15),
A(27) => rot_m01(15),
A(26) => rot_m01(15),
A(25) => rot_m01(15),
A(24) => rot_m01(15),
A(23) => rot_m01(15),
A(22) => rot_m01(15),
A(21) => rot_m01(15),
A(20) => rot_m01(15),
A(19) => rot_m01(15),
A(18) => rot_m01(15),
A(17) => rot_m01(15),
A(16) => rot_m01(15),
A(15 downto 0) => rot_m01(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_x_addr_out3__0_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17 downto 7) => B"00000000000",
B(6 downto 0) => y_addr_in(9 downto 3),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_x_addr_out3__0_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_x_addr_out3__0_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_x_addr_out3__0_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_x_addr_out3__0_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"1010101",
OVERFLOW => \NLW_x_addr_out3__0_OVERFLOW_UNCONNECTED\,
P(47) => \x_addr_out3__0_n_58\,
P(46) => \x_addr_out3__0_n_59\,
P(45) => \x_addr_out3__0_n_60\,
P(44) => \x_addr_out3__0_n_61\,
P(43) => \x_addr_out3__0_n_62\,
P(42) => \x_addr_out3__0_n_63\,
P(41) => \x_addr_out3__0_n_64\,
P(40) => \x_addr_out3__0_n_65\,
P(39) => \x_addr_out3__0_n_66\,
P(38) => \x_addr_out3__0_n_67\,
P(37) => \x_addr_out3__0_n_68\,
P(36) => \x_addr_out3__0_n_69\,
P(35) => \x_addr_out3__0_n_70\,
P(34) => \x_addr_out3__0_n_71\,
P(33) => \x_addr_out3__0_n_72\,
P(32) => \x_addr_out3__0_n_73\,
P(31) => \x_addr_out3__0_n_74\,
P(30) => \x_addr_out3__0_n_75\,
P(29) => \x_addr_out3__0_n_76\,
P(28) => \x_addr_out3__0_n_77\,
P(27) => \x_addr_out3__0_n_78\,
P(26) => \x_addr_out3__0_n_79\,
P(25) => \x_addr_out3__0_n_80\,
P(24) => \x_addr_out3__0_n_81\,
P(23) => \x_addr_out3__0_n_82\,
P(22) => \x_addr_out3__0_n_83\,
P(21) => \x_addr_out3__0_n_84\,
P(20) => \x_addr_out3__0_n_85\,
P(19) => \x_addr_out3__0_n_86\,
P(18) => \x_addr_out3__0_n_87\,
P(17) => \x_addr_out3__0_n_88\,
P(16) => \x_addr_out3__0_n_89\,
P(15) => \x_addr_out3__0_n_90\,
P(14) => \x_addr_out3__0_n_91\,
P(13) => \x_addr_out3__0_n_92\,
P(12) => \x_addr_out3__0_n_93\,
P(11) => \x_addr_out3__0_n_94\,
P(10) => \x_addr_out3__0_n_95\,
P(9) => \x_addr_out3__0_n_96\,
P(8) => \x_addr_out3__0_n_97\,
P(7) => \x_addr_out3__0_n_98\,
P(6) => \x_addr_out3__0_n_99\,
P(5) => \x_addr_out3__0_n_100\,
P(4) => \x_addr_out3__0_n_101\,
P(3) => \x_addr_out3__0_n_102\,
P(2) => \x_addr_out3__0_n_103\,
P(1) => \x_addr_out3__0_n_104\,
P(0) => \x_addr_out3__0_n_105\,
PATTERNBDETECT => \NLW_x_addr_out3__0_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_x_addr_out3__0_PATTERNDETECT_UNCONNECTED\,
PCIN(47) => x_addr_out3_n_106,
PCIN(46) => x_addr_out3_n_107,
PCIN(45) => x_addr_out3_n_108,
PCIN(44) => x_addr_out3_n_109,
PCIN(43) => x_addr_out3_n_110,
PCIN(42) => x_addr_out3_n_111,
PCIN(41) => x_addr_out3_n_112,
PCIN(40) => x_addr_out3_n_113,
PCIN(39) => x_addr_out3_n_114,
PCIN(38) => x_addr_out3_n_115,
PCIN(37) => x_addr_out3_n_116,
PCIN(36) => x_addr_out3_n_117,
PCIN(35) => x_addr_out3_n_118,
PCIN(34) => x_addr_out3_n_119,
PCIN(33) => x_addr_out3_n_120,
PCIN(32) => x_addr_out3_n_121,
PCIN(31) => x_addr_out3_n_122,
PCIN(30) => x_addr_out3_n_123,
PCIN(29) => x_addr_out3_n_124,
PCIN(28) => x_addr_out3_n_125,
PCIN(27) => x_addr_out3_n_126,
PCIN(26) => x_addr_out3_n_127,
PCIN(25) => x_addr_out3_n_128,
PCIN(24) => x_addr_out3_n_129,
PCIN(23) => x_addr_out3_n_130,
PCIN(22) => x_addr_out3_n_131,
PCIN(21) => x_addr_out3_n_132,
PCIN(20) => x_addr_out3_n_133,
PCIN(19) => x_addr_out3_n_134,
PCIN(18) => x_addr_out3_n_135,
PCIN(17) => x_addr_out3_n_136,
PCIN(16) => x_addr_out3_n_137,
PCIN(15) => x_addr_out3_n_138,
PCIN(14) => x_addr_out3_n_139,
PCIN(13) => x_addr_out3_n_140,
PCIN(12) => x_addr_out3_n_141,
PCIN(11) => x_addr_out3_n_142,
PCIN(10) => x_addr_out3_n_143,
PCIN(9) => x_addr_out3_n_144,
PCIN(8) => x_addr_out3_n_145,
PCIN(7) => x_addr_out3_n_146,
PCIN(6) => x_addr_out3_n_147,
PCIN(5) => x_addr_out3_n_148,
PCIN(4) => x_addr_out3_n_149,
PCIN(3) => x_addr_out3_n_150,
PCIN(2) => x_addr_out3_n_151,
PCIN(1) => x_addr_out3_n_152,
PCIN(0) => x_addr_out3_n_153,
PCOUT(47 downto 0) => \NLW_x_addr_out3__0_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_x_addr_out3__0_UNDERFLOW_UNCONNECTED\
);
\x_addr_out3__1\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29 downto 17) => B"0000000000000",
A(16 downto 14) => x_addr_in(2 downto 0),
A(13 downto 0) => B"00000000000000",
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_x_addr_out3__1_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => rot_m00(15),
B(16) => rot_m00(15),
B(15 downto 0) => rot_m00(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_x_addr_out3__1_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_x_addr_out3__1_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_x_addr_out3__1_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_x_addr_out3__1_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => \NLW_x_addr_out3__1_OVERFLOW_UNCONNECTED\,
P(47) => \x_addr_out3__1_n_58\,
P(46) => \x_addr_out3__1_n_59\,
P(45) => \x_addr_out3__1_n_60\,
P(44) => \x_addr_out3__1_n_61\,
P(43) => \x_addr_out3__1_n_62\,
P(42) => \x_addr_out3__1_n_63\,
P(41) => \x_addr_out3__1_n_64\,
P(40) => \x_addr_out3__1_n_65\,
P(39) => \x_addr_out3__1_n_66\,
P(38) => \x_addr_out3__1_n_67\,
P(37) => \x_addr_out3__1_n_68\,
P(36) => \x_addr_out3__1_n_69\,
P(35) => \x_addr_out3__1_n_70\,
P(34) => \x_addr_out3__1_n_71\,
P(33) => \x_addr_out3__1_n_72\,
P(32) => \x_addr_out3__1_n_73\,
P(31) => \x_addr_out3__1_n_74\,
P(30) => \x_addr_out3__1_n_75\,
P(29) => \x_addr_out3__1_n_76\,
P(28) => \x_addr_out3__1_n_77\,
P(27) => \x_addr_out3__1_n_78\,
P(26) => \x_addr_out3__1_n_79\,
P(25) => \x_addr_out3__1_n_80\,
P(24) => \x_addr_out3__1_n_81\,
P(23) => \x_addr_out3__1_n_82\,
P(22) => \x_addr_out3__1_n_83\,
P(21) => \x_addr_out3__1_n_84\,
P(20) => \x_addr_out3__1_n_85\,
P(19) => \x_addr_out3__1_n_86\,
P(18) => \x_addr_out3__1_n_87\,
P(17) => \x_addr_out3__1_n_88\,
P(16) => \x_addr_out3__1_n_89\,
P(15) => \x_addr_out3__1_n_90\,
P(14) => \x_addr_out3__1_n_91\,
P(13) => \x_addr_out3__1_n_92\,
P(12) => \x_addr_out3__1_n_93\,
P(11) => \x_addr_out3__1_n_94\,
P(10) => \x_addr_out3__1_n_95\,
P(9) => \x_addr_out3__1_n_96\,
P(8) => \x_addr_out3__1_n_97\,
P(7) => \x_addr_out3__1_n_98\,
P(6) => \x_addr_out3__1_n_99\,
P(5) => \x_addr_out3__1_n_100\,
P(4) => \x_addr_out3__1_n_101\,
P(3) => \x_addr_out3__1_n_102\,
P(2) => \x_addr_out3__1_n_103\,
P(1) => \x_addr_out3__1_n_104\,
P(0) => \x_addr_out3__1_n_105\,
PATTERNBDETECT => \NLW_x_addr_out3__1_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_x_addr_out3__1_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47) => \x_addr_out3__1_n_106\,
PCOUT(46) => \x_addr_out3__1_n_107\,
PCOUT(45) => \x_addr_out3__1_n_108\,
PCOUT(44) => \x_addr_out3__1_n_109\,
PCOUT(43) => \x_addr_out3__1_n_110\,
PCOUT(42) => \x_addr_out3__1_n_111\,
PCOUT(41) => \x_addr_out3__1_n_112\,
PCOUT(40) => \x_addr_out3__1_n_113\,
PCOUT(39) => \x_addr_out3__1_n_114\,
PCOUT(38) => \x_addr_out3__1_n_115\,
PCOUT(37) => \x_addr_out3__1_n_116\,
PCOUT(36) => \x_addr_out3__1_n_117\,
PCOUT(35) => \x_addr_out3__1_n_118\,
PCOUT(34) => \x_addr_out3__1_n_119\,
PCOUT(33) => \x_addr_out3__1_n_120\,
PCOUT(32) => \x_addr_out3__1_n_121\,
PCOUT(31) => \x_addr_out3__1_n_122\,
PCOUT(30) => \x_addr_out3__1_n_123\,
PCOUT(29) => \x_addr_out3__1_n_124\,
PCOUT(28) => \x_addr_out3__1_n_125\,
PCOUT(27) => \x_addr_out3__1_n_126\,
PCOUT(26) => \x_addr_out3__1_n_127\,
PCOUT(25) => \x_addr_out3__1_n_128\,
PCOUT(24) => \x_addr_out3__1_n_129\,
PCOUT(23) => \x_addr_out3__1_n_130\,
PCOUT(22) => \x_addr_out3__1_n_131\,
PCOUT(21) => \x_addr_out3__1_n_132\,
PCOUT(20) => \x_addr_out3__1_n_133\,
PCOUT(19) => \x_addr_out3__1_n_134\,
PCOUT(18) => \x_addr_out3__1_n_135\,
PCOUT(17) => \x_addr_out3__1_n_136\,
PCOUT(16) => \x_addr_out3__1_n_137\,
PCOUT(15) => \x_addr_out3__1_n_138\,
PCOUT(14) => \x_addr_out3__1_n_139\,
PCOUT(13) => \x_addr_out3__1_n_140\,
PCOUT(12) => \x_addr_out3__1_n_141\,
PCOUT(11) => \x_addr_out3__1_n_142\,
PCOUT(10) => \x_addr_out3__1_n_143\,
PCOUT(9) => \x_addr_out3__1_n_144\,
PCOUT(8) => \x_addr_out3__1_n_145\,
PCOUT(7) => \x_addr_out3__1_n_146\,
PCOUT(6) => \x_addr_out3__1_n_147\,
PCOUT(5) => \x_addr_out3__1_n_148\,
PCOUT(4) => \x_addr_out3__1_n_149\,
PCOUT(3) => \x_addr_out3__1_n_150\,
PCOUT(2) => \x_addr_out3__1_n_151\,
PCOUT(1) => \x_addr_out3__1_n_152\,
PCOUT(0) => \x_addr_out3__1_n_153\,
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_x_addr_out3__1_UNDERFLOW_UNCONNECTED\
);
\x_addr_out3__2\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => rot_m00(15),
A(28) => rot_m00(15),
A(27) => rot_m00(15),
A(26) => rot_m00(15),
A(25) => rot_m00(15),
A(24) => rot_m00(15),
A(23) => rot_m00(15),
A(22) => rot_m00(15),
A(21) => rot_m00(15),
A(20) => rot_m00(15),
A(19) => rot_m00(15),
A(18) => rot_m00(15),
A(17) => rot_m00(15),
A(16) => rot_m00(15),
A(15 downto 0) => rot_m00(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_x_addr_out3__2_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17 downto 7) => B"00000000000",
B(6 downto 0) => x_addr_in(9 downto 3),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_x_addr_out3__2_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_x_addr_out3__2_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_x_addr_out3__2_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_x_addr_out3__2_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"1010101",
OVERFLOW => \NLW_x_addr_out3__2_OVERFLOW_UNCONNECTED\,
P(47) => \x_addr_out3__2_n_58\,
P(46) => \x_addr_out3__2_n_59\,
P(45) => \x_addr_out3__2_n_60\,
P(44) => \x_addr_out3__2_n_61\,
P(43) => \x_addr_out3__2_n_62\,
P(42) => \x_addr_out3__2_n_63\,
P(41) => \x_addr_out3__2_n_64\,
P(40) => \x_addr_out3__2_n_65\,
P(39) => \x_addr_out3__2_n_66\,
P(38) => \x_addr_out3__2_n_67\,
P(37) => \x_addr_out3__2_n_68\,
P(36) => \x_addr_out3__2_n_69\,
P(35) => \x_addr_out3__2_n_70\,
P(34) => \x_addr_out3__2_n_71\,
P(33) => \x_addr_out3__2_n_72\,
P(32) => \x_addr_out3__2_n_73\,
P(31) => \x_addr_out3__2_n_74\,
P(30) => \x_addr_out3__2_n_75\,
P(29) => \x_addr_out3__2_n_76\,
P(28) => \x_addr_out3__2_n_77\,
P(27) => \x_addr_out3__2_n_78\,
P(26) => \x_addr_out3__2_n_79\,
P(25) => \x_addr_out3__2_n_80\,
P(24) => \x_addr_out3__2_n_81\,
P(23) => \x_addr_out3__2_n_82\,
P(22) => \x_addr_out3__2_n_83\,
P(21) => \x_addr_out3__2_n_84\,
P(20) => \x_addr_out3__2_n_85\,
P(19) => \x_addr_out3__2_n_86\,
P(18) => \x_addr_out3__2_n_87\,
P(17) => \x_addr_out3__2_n_88\,
P(16) => \x_addr_out3__2_n_89\,
P(15) => \x_addr_out3__2_n_90\,
P(14) => \x_addr_out3__2_n_91\,
P(13) => \x_addr_out3__2_n_92\,
P(12) => \x_addr_out3__2_n_93\,
P(11) => \x_addr_out3__2_n_94\,
P(10) => \x_addr_out3__2_n_95\,
P(9) => \x_addr_out3__2_n_96\,
P(8) => \x_addr_out3__2_n_97\,
P(7) => \x_addr_out3__2_n_98\,
P(6) => \x_addr_out3__2_n_99\,
P(5) => \x_addr_out3__2_n_100\,
P(4) => \x_addr_out3__2_n_101\,
P(3) => \x_addr_out3__2_n_102\,
P(2) => \x_addr_out3__2_n_103\,
P(1) => \x_addr_out3__2_n_104\,
P(0) => \x_addr_out3__2_n_105\,
PATTERNBDETECT => \NLW_x_addr_out3__2_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_x_addr_out3__2_PATTERNDETECT_UNCONNECTED\,
PCIN(47) => \x_addr_out3__1_n_106\,
PCIN(46) => \x_addr_out3__1_n_107\,
PCIN(45) => \x_addr_out3__1_n_108\,
PCIN(44) => \x_addr_out3__1_n_109\,
PCIN(43) => \x_addr_out3__1_n_110\,
PCIN(42) => \x_addr_out3__1_n_111\,
PCIN(41) => \x_addr_out3__1_n_112\,
PCIN(40) => \x_addr_out3__1_n_113\,
PCIN(39) => \x_addr_out3__1_n_114\,
PCIN(38) => \x_addr_out3__1_n_115\,
PCIN(37) => \x_addr_out3__1_n_116\,
PCIN(36) => \x_addr_out3__1_n_117\,
PCIN(35) => \x_addr_out3__1_n_118\,
PCIN(34) => \x_addr_out3__1_n_119\,
PCIN(33) => \x_addr_out3__1_n_120\,
PCIN(32) => \x_addr_out3__1_n_121\,
PCIN(31) => \x_addr_out3__1_n_122\,
PCIN(30) => \x_addr_out3__1_n_123\,
PCIN(29) => \x_addr_out3__1_n_124\,
PCIN(28) => \x_addr_out3__1_n_125\,
PCIN(27) => \x_addr_out3__1_n_126\,
PCIN(26) => \x_addr_out3__1_n_127\,
PCIN(25) => \x_addr_out3__1_n_128\,
PCIN(24) => \x_addr_out3__1_n_129\,
PCIN(23) => \x_addr_out3__1_n_130\,
PCIN(22) => \x_addr_out3__1_n_131\,
PCIN(21) => \x_addr_out3__1_n_132\,
PCIN(20) => \x_addr_out3__1_n_133\,
PCIN(19) => \x_addr_out3__1_n_134\,
PCIN(18) => \x_addr_out3__1_n_135\,
PCIN(17) => \x_addr_out3__1_n_136\,
PCIN(16) => \x_addr_out3__1_n_137\,
PCIN(15) => \x_addr_out3__1_n_138\,
PCIN(14) => \x_addr_out3__1_n_139\,
PCIN(13) => \x_addr_out3__1_n_140\,
PCIN(12) => \x_addr_out3__1_n_141\,
PCIN(11) => \x_addr_out3__1_n_142\,
PCIN(10) => \x_addr_out3__1_n_143\,
PCIN(9) => \x_addr_out3__1_n_144\,
PCIN(8) => \x_addr_out3__1_n_145\,
PCIN(7) => \x_addr_out3__1_n_146\,
PCIN(6) => \x_addr_out3__1_n_147\,
PCIN(5) => \x_addr_out3__1_n_148\,
PCIN(4) => \x_addr_out3__1_n_149\,
PCIN(3) => \x_addr_out3__1_n_150\,
PCIN(2) => \x_addr_out3__1_n_151\,
PCIN(1) => \x_addr_out3__1_n_152\,
PCIN(0) => \x_addr_out3__1_n_153\,
PCOUT(47 downto 0) => \NLW_x_addr_out3__2_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_x_addr_out3__2_UNDERFLOW_UNCONNECTED\
);
\x_addr_out[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"66F0"
)
port map (
I0 => p_1_in(14),
I1 => t_x(0),
I2 => x_addr_in(0),
I3 => enable,
O => \x_addr_out[0]_i_1_n_0\
);
\x_addr_out[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x_addr_out0(15),
I1 => x_addr_in(1),
I2 => enable,
O => \x_addr_out[1]_i_1_n_0\
);
\x_addr_out[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x_addr_out0(16),
I1 => x_addr_in(2),
I2 => enable,
O => \x_addr_out[2]_i_1_n_0\
);
\x_addr_out[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x_addr_out0(17),
I1 => x_addr_in(3),
I2 => enable,
O => \x_addr_out[3]_i_1_n_0\
);
\x_addr_out[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x_addr_out0(18),
I1 => x_addr_in(4),
I2 => enable,
O => \x_addr_out[4]_i_1_n_0\
);
\x_addr_out[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x_addr_out0(19),
I1 => x_addr_in(5),
I2 => enable,
O => \x_addr_out[5]_i_1_n_0\
);
\x_addr_out[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x_addr_out0(20),
I1 => x_addr_in(6),
I2 => enable,
O => \x_addr_out[6]_i_1_n_0\
);
\x_addr_out[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x_addr_out0(21),
I1 => x_addr_in(7),
I2 => enable,
O => \x_addr_out[7]_i_1_n_0\
);
\x_addr_out[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x_addr_out0(22),
I1 => x_addr_in(8),
I2 => enable,
O => \x_addr_out[8]_i_1_n_0\
);
\x_addr_out[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => x_addr_out0(23),
I1 => x_addr_in(9),
I2 => enable,
O => \x_addr_out[9]_i_1_n_0\
);
\x_addr_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \x_addr_out[0]_i_1_n_0\,
Q => x_addr_out(0),
R => '0'
);
\x_addr_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \x_addr_out[1]_i_1_n_0\,
Q => x_addr_out(1),
R => '0'
);
\x_addr_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \x_addr_out[2]_i_1_n_0\,
Q => x_addr_out(2),
R => '0'
);
\x_addr_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \x_addr_out[3]_i_1_n_0\,
Q => x_addr_out(3),
R => '0'
);
\x_addr_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \x_addr_out[4]_i_1_n_0\,
Q => x_addr_out(4),
R => '0'
);
\x_addr_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \x_addr_out[5]_i_1_n_0\,
Q => x_addr_out(5),
R => '0'
);
\x_addr_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \x_addr_out[6]_i_1_n_0\,
Q => x_addr_out(6),
R => '0'
);
\x_addr_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \x_addr_out[7]_i_1_n_0\,
Q => x_addr_out(7),
R => '0'
);
\x_addr_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \x_addr_out[8]_i_1_n_0\,
Q => x_addr_out(8),
R => '0'
);
\x_addr_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => '1',
D => \x_addr_out[9]_i_1_n_0\,
Q => x_addr_out(9),
R => '0'
);
y_addr_out0_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => y_addr_out0_carry_n_0,
CO(2) => y_addr_out0_carry_n_1,
CO(1) => y_addr_out0_carry_n_2,
CO(0) => y_addr_out0_carry_n_3,
CYINIT => '0',
DI(3 downto 0) => y_addr_out2(31 downto 28),
O(3 downto 1) => p_0_in(3 downto 1),
O(0) => NLW_y_addr_out0_carry_O_UNCONNECTED(0),
S(3) => y_addr_out0_carry_i_1_n_0,
S(2) => y_addr_out0_carry_i_2_n_0,
S(1) => y_addr_out0_carry_i_3_n_0,
S(0) => y_addr_out0_carry_i_4_n_0
);
\y_addr_out0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => y_addr_out0_carry_n_0,
CO(3) => \y_addr_out0_carry__0_n_0\,
CO(2) => \y_addr_out0_carry__0_n_1\,
CO(1) => \y_addr_out0_carry__0_n_2\,
CO(0) => \y_addr_out0_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => y_addr_out2(35 downto 32),
O(3 downto 0) => p_0_in(7 downto 4),
S(3) => \y_addr_out0_carry__0_i_1_n_0\,
S(2) => \y_addr_out0_carry__0_i_2_n_0\,
S(1) => \y_addr_out0_carry__0_i_3_n_0\,
S(0) => \y_addr_out0_carry__0_i_4_n_0\
);
\y_addr_out0_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y_addr_out2(35),
I1 => t_y(7),
O => \y_addr_out0_carry__0_i_1_n_0\
);
\y_addr_out0_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y_addr_out2(34),
I1 => t_y(6),
O => \y_addr_out0_carry__0_i_2_n_0\
);
\y_addr_out0_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y_addr_out2(33),
I1 => t_y(5),
O => \y_addr_out0_carry__0_i_3_n_0\
);
\y_addr_out0_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y_addr_out2(32),
I1 => t_y(4),
O => \y_addr_out0_carry__0_i_4_n_0\
);
\y_addr_out0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \y_addr_out0_carry__0_n_0\,
CO(3 downto 1) => \NLW_y_addr_out0_carry__1_CO_UNCONNECTED\(3 downto 1),
CO(0) => \y_addr_out0_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => y_addr_out2(36),
O(3 downto 2) => \NLW_y_addr_out0_carry__1_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => p_0_in(9 downto 8),
S(3 downto 2) => B"00",
S(1) => \y_addr_out0_carry__1_i_1_n_0\,
S(0) => \y_addr_out0_carry__1_i_2_n_0\
);
\y_addr_out0_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y_addr_out2(37),
I1 => t_y(9),
O => \y_addr_out0_carry__1_i_1_n_0\
);
\y_addr_out0_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y_addr_out2(36),
I1 => t_y(8),
O => \y_addr_out0_carry__1_i_2_n_0\
);
y_addr_out0_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y_addr_out2(31),
I1 => t_y(3),
O => y_addr_out0_carry_i_1_n_0
);
y_addr_out0_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y_addr_out2(30),
I1 => t_y(2),
O => y_addr_out0_carry_i_2_n_0
);
y_addr_out0_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y_addr_out2(29),
I1 => t_y(1),
O => y_addr_out0_carry_i_3_n_0
);
y_addr_out0_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y_addr_out2(28),
I1 => t_y(0),
O => y_addr_out0_carry_i_4_n_0
);
y_addr_out2_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => y_addr_out2_carry_n_0,
CO(2) => y_addr_out2_carry_n_1,
CO(1) => y_addr_out2_carry_n_2,
CO(0) => y_addr_out2_carry_n_3,
CYINIT => '0',
DI(3) => \y_addr_out3__1_n_102\,
DI(2) => \y_addr_out3__1_n_103\,
DI(1) => \y_addr_out3__1_n_104\,
DI(0) => \y_addr_out3__1_n_105\,
O(3 downto 0) => NLW_y_addr_out2_carry_O_UNCONNECTED(3 downto 0),
S(3) => y_addr_out2_carry_i_1_n_0,
S(2) => y_addr_out2_carry_i_2_n_0,
S(1) => y_addr_out2_carry_i_3_n_0,
S(0) => y_addr_out2_carry_i_4_n_0
);
\y_addr_out2_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => y_addr_out2_carry_n_0,
CO(3) => \y_addr_out2_carry__0_n_0\,
CO(2) => \y_addr_out2_carry__0_n_1\,
CO(1) => \y_addr_out2_carry__0_n_2\,
CO(0) => \y_addr_out2_carry__0_n_3\,
CYINIT => '0',
DI(3) => \y_addr_out3__1_n_98\,
DI(2) => \y_addr_out3__1_n_99\,
DI(1) => \y_addr_out3__1_n_100\,
DI(0) => \y_addr_out3__1_n_101\,
O(3 downto 0) => \NLW_y_addr_out2_carry__0_O_UNCONNECTED\(3 downto 0),
S(3) => \y_addr_out2_carry__0_i_1_n_0\,
S(2) => \y_addr_out2_carry__0_i_2_n_0\,
S(1) => \y_addr_out2_carry__0_i_3_n_0\,
S(0) => \y_addr_out2_carry__0_i_4_n_0\
);
\y_addr_out2_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_98\,
I1 => y_addr_out3_n_98,
O => \y_addr_out2_carry__0_i_1_n_0\
);
\y_addr_out2_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_99\,
I1 => y_addr_out3_n_99,
O => \y_addr_out2_carry__0_i_2_n_0\
);
\y_addr_out2_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_100\,
I1 => y_addr_out3_n_100,
O => \y_addr_out2_carry__0_i_3_n_0\
);
\y_addr_out2_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_101\,
I1 => y_addr_out3_n_101,
O => \y_addr_out2_carry__0_i_4_n_0\
);
\y_addr_out2_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \y_addr_out2_carry__0_n_0\,
CO(3) => \y_addr_out2_carry__1_n_0\,
CO(2) => \y_addr_out2_carry__1_n_1\,
CO(1) => \y_addr_out2_carry__1_n_2\,
CO(0) => \y_addr_out2_carry__1_n_3\,
CYINIT => '0',
DI(3) => \y_addr_out3__1_n_94\,
DI(2) => \y_addr_out3__1_n_95\,
DI(1) => \y_addr_out3__1_n_96\,
DI(0) => \y_addr_out3__1_n_97\,
O(3 downto 0) => \NLW_y_addr_out2_carry__1_O_UNCONNECTED\(3 downto 0),
S(3) => \y_addr_out2_carry__1_i_1_n_0\,
S(2) => \y_addr_out2_carry__1_i_2_n_0\,
S(1) => \y_addr_out2_carry__1_i_3_n_0\,
S(0) => \y_addr_out2_carry__1_i_4_n_0\
);
\y_addr_out2_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_94\,
I1 => y_addr_out3_n_94,
O => \y_addr_out2_carry__1_i_1_n_0\
);
\y_addr_out2_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_95\,
I1 => y_addr_out3_n_95,
O => \y_addr_out2_carry__1_i_2_n_0\
);
\y_addr_out2_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_96\,
I1 => y_addr_out3_n_96,
O => \y_addr_out2_carry__1_i_3_n_0\
);
\y_addr_out2_carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_97\,
I1 => y_addr_out3_n_97,
O => \y_addr_out2_carry__1_i_4_n_0\
);
\y_addr_out2_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \y_addr_out2_carry__1_n_0\,
CO(3) => \y_addr_out2_carry__2_n_0\,
CO(2) => \y_addr_out2_carry__2_n_1\,
CO(1) => \y_addr_out2_carry__2_n_2\,
CO(0) => \y_addr_out2_carry__2_n_3\,
CYINIT => '0',
DI(3) => \y_addr_out3__1_n_90\,
DI(2) => \y_addr_out3__1_n_91\,
DI(1) => \y_addr_out3__1_n_92\,
DI(0) => \y_addr_out3__1_n_93\,
O(3 downto 0) => \NLW_y_addr_out2_carry__2_O_UNCONNECTED\(3 downto 0),
S(3) => \y_addr_out2_carry__2_i_1_n_0\,
S(2) => \y_addr_out2_carry__2_i_2_n_0\,
S(1) => \y_addr_out2_carry__2_i_3_n_0\,
S(0) => \y_addr_out2_carry__2_i_4_n_0\
);
\y_addr_out2_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_90\,
I1 => y_addr_out3_n_90,
O => \y_addr_out2_carry__2_i_1_n_0\
);
\y_addr_out2_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_91\,
I1 => y_addr_out3_n_91,
O => \y_addr_out2_carry__2_i_2_n_0\
);
\y_addr_out2_carry__2_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_92\,
I1 => y_addr_out3_n_92,
O => \y_addr_out2_carry__2_i_3_n_0\
);
\y_addr_out2_carry__2_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_93\,
I1 => y_addr_out3_n_93,
O => \y_addr_out2_carry__2_i_4_n_0\
);
\y_addr_out2_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \y_addr_out2_carry__2_n_0\,
CO(3) => \y_addr_out2_carry__3_n_0\,
CO(2) => \y_addr_out2_carry__3_n_1\,
CO(1) => \y_addr_out2_carry__3_n_2\,
CO(0) => \y_addr_out2_carry__3_n_3\,
CYINIT => '0',
DI(3) => \y_addr_out3__2_n_103\,
DI(2) => \y_addr_out3__2_n_104\,
DI(1) => \y_addr_out3__2_n_105\,
DI(0) => \y_addr_out3__1_n_89\,
O(3 downto 0) => \NLW_y_addr_out2_carry__3_O_UNCONNECTED\(3 downto 0),
S(3) => \y_addr_out2_carry__3_i_1_n_0\,
S(2) => \y_addr_out2_carry__3_i_2_n_0\,
S(1) => \y_addr_out2_carry__3_i_3_n_0\,
S(0) => \y_addr_out2_carry__3_i_4_n_0\
);
\y_addr_out2_carry__3_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_103\,
I1 => \y_addr_out3__0_n_103\,
O => \y_addr_out2_carry__3_i_1_n_0\
);
\y_addr_out2_carry__3_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_104\,
I1 => \y_addr_out3__0_n_104\,
O => \y_addr_out2_carry__3_i_2_n_0\
);
\y_addr_out2_carry__3_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_105\,
I1 => \y_addr_out3__0_n_105\,
O => \y_addr_out2_carry__3_i_3_n_0\
);
\y_addr_out2_carry__3_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_89\,
I1 => y_addr_out3_n_89,
O => \y_addr_out2_carry__3_i_4_n_0\
);
\y_addr_out2_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \y_addr_out2_carry__3_n_0\,
CO(3) => \y_addr_out2_carry__4_n_0\,
CO(2) => \y_addr_out2_carry__4_n_1\,
CO(1) => \y_addr_out2_carry__4_n_2\,
CO(0) => \y_addr_out2_carry__4_n_3\,
CYINIT => '0',
DI(3) => \y_addr_out3__2_n_99\,
DI(2) => \y_addr_out3__2_n_100\,
DI(1) => \y_addr_out3__2_n_101\,
DI(0) => \y_addr_out3__2_n_102\,
O(3 downto 0) => \NLW_y_addr_out2_carry__4_O_UNCONNECTED\(3 downto 0),
S(3) => \y_addr_out2_carry__4_i_1_n_0\,
S(2) => \y_addr_out2_carry__4_i_2_n_0\,
S(1) => \y_addr_out2_carry__4_i_3_n_0\,
S(0) => \y_addr_out2_carry__4_i_4_n_0\
);
\y_addr_out2_carry__4_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_99\,
I1 => \y_addr_out3__0_n_99\,
O => \y_addr_out2_carry__4_i_1_n_0\
);
\y_addr_out2_carry__4_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_100\,
I1 => \y_addr_out3__0_n_100\,
O => \y_addr_out2_carry__4_i_2_n_0\
);
\y_addr_out2_carry__4_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_101\,
I1 => \y_addr_out3__0_n_101\,
O => \y_addr_out2_carry__4_i_3_n_0\
);
\y_addr_out2_carry__4_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_102\,
I1 => \y_addr_out3__0_n_102\,
O => \y_addr_out2_carry__4_i_4_n_0\
);
\y_addr_out2_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \y_addr_out2_carry__4_n_0\,
CO(3) => \y_addr_out2_carry__5_n_0\,
CO(2) => \y_addr_out2_carry__5_n_1\,
CO(1) => \y_addr_out2_carry__5_n_2\,
CO(0) => \y_addr_out2_carry__5_n_3\,
CYINIT => '0',
DI(3) => \y_addr_out3__2_n_95\,
DI(2) => \y_addr_out3__2_n_96\,
DI(1) => \y_addr_out3__2_n_97\,
DI(0) => \y_addr_out3__2_n_98\,
O(3 downto 0) => \NLW_y_addr_out2_carry__5_O_UNCONNECTED\(3 downto 0),
S(3) => \y_addr_out2_carry__5_i_1_n_0\,
S(2) => \y_addr_out2_carry__5_i_2_n_0\,
S(1) => \y_addr_out2_carry__5_i_3_n_0\,
S(0) => \y_addr_out2_carry__5_i_4_n_0\
);
\y_addr_out2_carry__5_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_95\,
I1 => \y_addr_out3__0_n_95\,
O => \y_addr_out2_carry__5_i_1_n_0\
);
\y_addr_out2_carry__5_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_96\,
I1 => \y_addr_out3__0_n_96\,
O => \y_addr_out2_carry__5_i_2_n_0\
);
\y_addr_out2_carry__5_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_97\,
I1 => \y_addr_out3__0_n_97\,
O => \y_addr_out2_carry__5_i_3_n_0\
);
\y_addr_out2_carry__5_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_98\,
I1 => \y_addr_out3__0_n_98\,
O => \y_addr_out2_carry__5_i_4_n_0\
);
\y_addr_out2_carry__6\: unisim.vcomponents.CARRY4
port map (
CI => \y_addr_out2_carry__5_n_0\,
CO(3) => \y_addr_out2_carry__6_n_0\,
CO(2) => \y_addr_out2_carry__6_n_1\,
CO(1) => \y_addr_out2_carry__6_n_2\,
CO(0) => \y_addr_out2_carry__6_n_3\,
CYINIT => '0',
DI(3) => \y_addr_out3__2_n_91\,
DI(2) => \y_addr_out3__2_n_92\,
DI(1) => \y_addr_out3__2_n_93\,
DI(0) => \y_addr_out3__2_n_94\,
O(3 downto 0) => y_addr_out2(31 downto 28),
S(3) => \y_addr_out2_carry__6_i_1_n_0\,
S(2) => \y_addr_out2_carry__6_i_2_n_0\,
S(1) => \y_addr_out2_carry__6_i_3_n_0\,
S(0) => \y_addr_out2_carry__6_i_4_n_0\
);
\y_addr_out2_carry__6_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_91\,
I1 => \y_addr_out3__0_n_91\,
O => \y_addr_out2_carry__6_i_1_n_0\
);
\y_addr_out2_carry__6_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_92\,
I1 => \y_addr_out3__0_n_92\,
O => \y_addr_out2_carry__6_i_2_n_0\
);
\y_addr_out2_carry__6_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_93\,
I1 => \y_addr_out3__0_n_93\,
O => \y_addr_out2_carry__6_i_3_n_0\
);
\y_addr_out2_carry__6_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_94\,
I1 => \y_addr_out3__0_n_94\,
O => \y_addr_out2_carry__6_i_4_n_0\
);
\y_addr_out2_carry__7\: unisim.vcomponents.CARRY4
port map (
CI => \y_addr_out2_carry__6_n_0\,
CO(3) => \y_addr_out2_carry__7_n_0\,
CO(2) => \y_addr_out2_carry__7_n_1\,
CO(1) => \y_addr_out2_carry__7_n_2\,
CO(0) => \y_addr_out2_carry__7_n_3\,
CYINIT => '0',
DI(3) => \y_addr_out3__2_n_87\,
DI(2) => \y_addr_out3__2_n_88\,
DI(1) => \y_addr_out3__2_n_89\,
DI(0) => \y_addr_out3__2_n_90\,
O(3 downto 0) => y_addr_out2(35 downto 32),
S(3) => \y_addr_out2_carry__7_i_1_n_0\,
S(2) => \y_addr_out2_carry__7_i_2_n_0\,
S(1) => \y_addr_out2_carry__7_i_3_n_0\,
S(0) => \y_addr_out2_carry__7_i_4_n_0\
);
\y_addr_out2_carry__7_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_87\,
I1 => \y_addr_out3__0_n_87\,
O => \y_addr_out2_carry__7_i_1_n_0\
);
\y_addr_out2_carry__7_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_88\,
I1 => \y_addr_out3__0_n_88\,
O => \y_addr_out2_carry__7_i_2_n_0\
);
\y_addr_out2_carry__7_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_89\,
I1 => \y_addr_out3__0_n_89\,
O => \y_addr_out2_carry__7_i_3_n_0\
);
\y_addr_out2_carry__7_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_90\,
I1 => \y_addr_out3__0_n_90\,
O => \y_addr_out2_carry__7_i_4_n_0\
);
\y_addr_out2_carry__8\: unisim.vcomponents.CARRY4
port map (
CI => \y_addr_out2_carry__7_n_0\,
CO(3 downto 1) => \NLW_y_addr_out2_carry__8_CO_UNCONNECTED\(3 downto 1),
CO(0) => \y_addr_out2_carry__8_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \y_addr_out3__2_n_86\,
O(3 downto 2) => \NLW_y_addr_out2_carry__8_O_UNCONNECTED\(3 downto 2),
O(1 downto 0) => y_addr_out2(37 downto 36),
S(3 downto 2) => B"00",
S(1) => \y_addr_out2_carry__8_i_1_n_0\,
S(0) => \y_addr_out2_carry__8_i_2_n_0\
);
\y_addr_out2_carry__8_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_85\,
I1 => \y_addr_out3__0_n_85\,
O => \y_addr_out2_carry__8_i_1_n_0\
);
\y_addr_out2_carry__8_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__2_n_86\,
I1 => \y_addr_out3__0_n_86\,
O => \y_addr_out2_carry__8_i_2_n_0\
);
y_addr_out2_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_102\,
I1 => y_addr_out3_n_102,
O => y_addr_out2_carry_i_1_n_0
);
y_addr_out2_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_103\,
I1 => y_addr_out3_n_103,
O => y_addr_out2_carry_i_2_n_0
);
y_addr_out2_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_104\,
I1 => y_addr_out3_n_104,
O => y_addr_out2_carry_i_3_n_0
);
y_addr_out2_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \y_addr_out3__1_n_105\,
I1 => y_addr_out3_n_105,
O => y_addr_out2_carry_i_4_n_0
);
y_addr_out3: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29 downto 17) => B"0000000000000",
A(16 downto 14) => y_addr_in(2 downto 0),
A(13 downto 0) => B"00000000000000",
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_y_addr_out3_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => rot_m11(15),
B(16) => rot_m11(15),
B(15 downto 0) => rot_m11(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_y_addr_out3_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_y_addr_out3_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_y_addr_out3_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_y_addr_out3_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_y_addr_out3_OVERFLOW_UNCONNECTED,
P(47) => y_addr_out3_n_58,
P(46) => y_addr_out3_n_59,
P(45) => y_addr_out3_n_60,
P(44) => y_addr_out3_n_61,
P(43) => y_addr_out3_n_62,
P(42) => y_addr_out3_n_63,
P(41) => y_addr_out3_n_64,
P(40) => y_addr_out3_n_65,
P(39) => y_addr_out3_n_66,
P(38) => y_addr_out3_n_67,
P(37) => y_addr_out3_n_68,
P(36) => y_addr_out3_n_69,
P(35) => y_addr_out3_n_70,
P(34) => y_addr_out3_n_71,
P(33) => y_addr_out3_n_72,
P(32) => y_addr_out3_n_73,
P(31) => y_addr_out3_n_74,
P(30) => y_addr_out3_n_75,
P(29) => y_addr_out3_n_76,
P(28) => y_addr_out3_n_77,
P(27) => y_addr_out3_n_78,
P(26) => y_addr_out3_n_79,
P(25) => y_addr_out3_n_80,
P(24) => y_addr_out3_n_81,
P(23) => y_addr_out3_n_82,
P(22) => y_addr_out3_n_83,
P(21) => y_addr_out3_n_84,
P(20) => y_addr_out3_n_85,
P(19) => y_addr_out3_n_86,
P(18) => y_addr_out3_n_87,
P(17) => y_addr_out3_n_88,
P(16) => y_addr_out3_n_89,
P(15) => y_addr_out3_n_90,
P(14) => y_addr_out3_n_91,
P(13) => y_addr_out3_n_92,
P(12) => y_addr_out3_n_93,
P(11) => y_addr_out3_n_94,
P(10) => y_addr_out3_n_95,
P(9) => y_addr_out3_n_96,
P(8) => y_addr_out3_n_97,
P(7) => y_addr_out3_n_98,
P(6) => y_addr_out3_n_99,
P(5) => y_addr_out3_n_100,
P(4) => y_addr_out3_n_101,
P(3) => y_addr_out3_n_102,
P(2) => y_addr_out3_n_103,
P(1) => y_addr_out3_n_104,
P(0) => y_addr_out3_n_105,
PATTERNBDETECT => NLW_y_addr_out3_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_y_addr_out3_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47) => y_addr_out3_n_106,
PCOUT(46) => y_addr_out3_n_107,
PCOUT(45) => y_addr_out3_n_108,
PCOUT(44) => y_addr_out3_n_109,
PCOUT(43) => y_addr_out3_n_110,
PCOUT(42) => y_addr_out3_n_111,
PCOUT(41) => y_addr_out3_n_112,
PCOUT(40) => y_addr_out3_n_113,
PCOUT(39) => y_addr_out3_n_114,
PCOUT(38) => y_addr_out3_n_115,
PCOUT(37) => y_addr_out3_n_116,
PCOUT(36) => y_addr_out3_n_117,
PCOUT(35) => y_addr_out3_n_118,
PCOUT(34) => y_addr_out3_n_119,
PCOUT(33) => y_addr_out3_n_120,
PCOUT(32) => y_addr_out3_n_121,
PCOUT(31) => y_addr_out3_n_122,
PCOUT(30) => y_addr_out3_n_123,
PCOUT(29) => y_addr_out3_n_124,
PCOUT(28) => y_addr_out3_n_125,
PCOUT(27) => y_addr_out3_n_126,
PCOUT(26) => y_addr_out3_n_127,
PCOUT(25) => y_addr_out3_n_128,
PCOUT(24) => y_addr_out3_n_129,
PCOUT(23) => y_addr_out3_n_130,
PCOUT(22) => y_addr_out3_n_131,
PCOUT(21) => y_addr_out3_n_132,
PCOUT(20) => y_addr_out3_n_133,
PCOUT(19) => y_addr_out3_n_134,
PCOUT(18) => y_addr_out3_n_135,
PCOUT(17) => y_addr_out3_n_136,
PCOUT(16) => y_addr_out3_n_137,
PCOUT(15) => y_addr_out3_n_138,
PCOUT(14) => y_addr_out3_n_139,
PCOUT(13) => y_addr_out3_n_140,
PCOUT(12) => y_addr_out3_n_141,
PCOUT(11) => y_addr_out3_n_142,
PCOUT(10) => y_addr_out3_n_143,
PCOUT(9) => y_addr_out3_n_144,
PCOUT(8) => y_addr_out3_n_145,
PCOUT(7) => y_addr_out3_n_146,
PCOUT(6) => y_addr_out3_n_147,
PCOUT(5) => y_addr_out3_n_148,
PCOUT(4) => y_addr_out3_n_149,
PCOUT(3) => y_addr_out3_n_150,
PCOUT(2) => y_addr_out3_n_151,
PCOUT(1) => y_addr_out3_n_152,
PCOUT(0) => y_addr_out3_n_153,
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_y_addr_out3_UNDERFLOW_UNCONNECTED
);
\y_addr_out3__0\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => rot_m11(15),
A(28) => rot_m11(15),
A(27) => rot_m11(15),
A(26) => rot_m11(15),
A(25) => rot_m11(15),
A(24) => rot_m11(15),
A(23) => rot_m11(15),
A(22) => rot_m11(15),
A(21) => rot_m11(15),
A(20) => rot_m11(15),
A(19) => rot_m11(15),
A(18) => rot_m11(15),
A(17) => rot_m11(15),
A(16) => rot_m11(15),
A(15 downto 0) => rot_m11(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_y_addr_out3__0_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17 downto 7) => B"00000000000",
B(6 downto 0) => y_addr_in(9 downto 3),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_y_addr_out3__0_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_y_addr_out3__0_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_y_addr_out3__0_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_y_addr_out3__0_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"1010101",
OVERFLOW => \NLW_y_addr_out3__0_OVERFLOW_UNCONNECTED\,
P(47) => \y_addr_out3__0_n_58\,
P(46) => \y_addr_out3__0_n_59\,
P(45) => \y_addr_out3__0_n_60\,
P(44) => \y_addr_out3__0_n_61\,
P(43) => \y_addr_out3__0_n_62\,
P(42) => \y_addr_out3__0_n_63\,
P(41) => \y_addr_out3__0_n_64\,
P(40) => \y_addr_out3__0_n_65\,
P(39) => \y_addr_out3__0_n_66\,
P(38) => \y_addr_out3__0_n_67\,
P(37) => \y_addr_out3__0_n_68\,
P(36) => \y_addr_out3__0_n_69\,
P(35) => \y_addr_out3__0_n_70\,
P(34) => \y_addr_out3__0_n_71\,
P(33) => \y_addr_out3__0_n_72\,
P(32) => \y_addr_out3__0_n_73\,
P(31) => \y_addr_out3__0_n_74\,
P(30) => \y_addr_out3__0_n_75\,
P(29) => \y_addr_out3__0_n_76\,
P(28) => \y_addr_out3__0_n_77\,
P(27) => \y_addr_out3__0_n_78\,
P(26) => \y_addr_out3__0_n_79\,
P(25) => \y_addr_out3__0_n_80\,
P(24) => \y_addr_out3__0_n_81\,
P(23) => \y_addr_out3__0_n_82\,
P(22) => \y_addr_out3__0_n_83\,
P(21) => \y_addr_out3__0_n_84\,
P(20) => \y_addr_out3__0_n_85\,
P(19) => \y_addr_out3__0_n_86\,
P(18) => \y_addr_out3__0_n_87\,
P(17) => \y_addr_out3__0_n_88\,
P(16) => \y_addr_out3__0_n_89\,
P(15) => \y_addr_out3__0_n_90\,
P(14) => \y_addr_out3__0_n_91\,
P(13) => \y_addr_out3__0_n_92\,
P(12) => \y_addr_out3__0_n_93\,
P(11) => \y_addr_out3__0_n_94\,
P(10) => \y_addr_out3__0_n_95\,
P(9) => \y_addr_out3__0_n_96\,
P(8) => \y_addr_out3__0_n_97\,
P(7) => \y_addr_out3__0_n_98\,
P(6) => \y_addr_out3__0_n_99\,
P(5) => \y_addr_out3__0_n_100\,
P(4) => \y_addr_out3__0_n_101\,
P(3) => \y_addr_out3__0_n_102\,
P(2) => \y_addr_out3__0_n_103\,
P(1) => \y_addr_out3__0_n_104\,
P(0) => \y_addr_out3__0_n_105\,
PATTERNBDETECT => \NLW_y_addr_out3__0_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_y_addr_out3__0_PATTERNDETECT_UNCONNECTED\,
PCIN(47) => y_addr_out3_n_106,
PCIN(46) => y_addr_out3_n_107,
PCIN(45) => y_addr_out3_n_108,
PCIN(44) => y_addr_out3_n_109,
PCIN(43) => y_addr_out3_n_110,
PCIN(42) => y_addr_out3_n_111,
PCIN(41) => y_addr_out3_n_112,
PCIN(40) => y_addr_out3_n_113,
PCIN(39) => y_addr_out3_n_114,
PCIN(38) => y_addr_out3_n_115,
PCIN(37) => y_addr_out3_n_116,
PCIN(36) => y_addr_out3_n_117,
PCIN(35) => y_addr_out3_n_118,
PCIN(34) => y_addr_out3_n_119,
PCIN(33) => y_addr_out3_n_120,
PCIN(32) => y_addr_out3_n_121,
PCIN(31) => y_addr_out3_n_122,
PCIN(30) => y_addr_out3_n_123,
PCIN(29) => y_addr_out3_n_124,
PCIN(28) => y_addr_out3_n_125,
PCIN(27) => y_addr_out3_n_126,
PCIN(26) => y_addr_out3_n_127,
PCIN(25) => y_addr_out3_n_128,
PCIN(24) => y_addr_out3_n_129,
PCIN(23) => y_addr_out3_n_130,
PCIN(22) => y_addr_out3_n_131,
PCIN(21) => y_addr_out3_n_132,
PCIN(20) => y_addr_out3_n_133,
PCIN(19) => y_addr_out3_n_134,
PCIN(18) => y_addr_out3_n_135,
PCIN(17) => y_addr_out3_n_136,
PCIN(16) => y_addr_out3_n_137,
PCIN(15) => y_addr_out3_n_138,
PCIN(14) => y_addr_out3_n_139,
PCIN(13) => y_addr_out3_n_140,
PCIN(12) => y_addr_out3_n_141,
PCIN(11) => y_addr_out3_n_142,
PCIN(10) => y_addr_out3_n_143,
PCIN(9) => y_addr_out3_n_144,
PCIN(8) => y_addr_out3_n_145,
PCIN(7) => y_addr_out3_n_146,
PCIN(6) => y_addr_out3_n_147,
PCIN(5) => y_addr_out3_n_148,
PCIN(4) => y_addr_out3_n_149,
PCIN(3) => y_addr_out3_n_150,
PCIN(2) => y_addr_out3_n_151,
PCIN(1) => y_addr_out3_n_152,
PCIN(0) => y_addr_out3_n_153,
PCOUT(47 downto 0) => \NLW_y_addr_out3__0_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_y_addr_out3__0_UNDERFLOW_UNCONNECTED\
);
\y_addr_out3__1\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29 downto 17) => B"0000000000000",
A(16 downto 14) => x_addr_in(2 downto 0),
A(13 downto 0) => B"00000000000000",
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_y_addr_out3__1_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => rot_m10(15),
B(16) => rot_m10(15),
B(15 downto 0) => rot_m10(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_y_addr_out3__1_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_y_addr_out3__1_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_y_addr_out3__1_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_y_addr_out3__1_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => \NLW_y_addr_out3__1_OVERFLOW_UNCONNECTED\,
P(47) => \y_addr_out3__1_n_58\,
P(46) => \y_addr_out3__1_n_59\,
P(45) => \y_addr_out3__1_n_60\,
P(44) => \y_addr_out3__1_n_61\,
P(43) => \y_addr_out3__1_n_62\,
P(42) => \y_addr_out3__1_n_63\,
P(41) => \y_addr_out3__1_n_64\,
P(40) => \y_addr_out3__1_n_65\,
P(39) => \y_addr_out3__1_n_66\,
P(38) => \y_addr_out3__1_n_67\,
P(37) => \y_addr_out3__1_n_68\,
P(36) => \y_addr_out3__1_n_69\,
P(35) => \y_addr_out3__1_n_70\,
P(34) => \y_addr_out3__1_n_71\,
P(33) => \y_addr_out3__1_n_72\,
P(32) => \y_addr_out3__1_n_73\,
P(31) => \y_addr_out3__1_n_74\,
P(30) => \y_addr_out3__1_n_75\,
P(29) => \y_addr_out3__1_n_76\,
P(28) => \y_addr_out3__1_n_77\,
P(27) => \y_addr_out3__1_n_78\,
P(26) => \y_addr_out3__1_n_79\,
P(25) => \y_addr_out3__1_n_80\,
P(24) => \y_addr_out3__1_n_81\,
P(23) => \y_addr_out3__1_n_82\,
P(22) => \y_addr_out3__1_n_83\,
P(21) => \y_addr_out3__1_n_84\,
P(20) => \y_addr_out3__1_n_85\,
P(19) => \y_addr_out3__1_n_86\,
P(18) => \y_addr_out3__1_n_87\,
P(17) => \y_addr_out3__1_n_88\,
P(16) => \y_addr_out3__1_n_89\,
P(15) => \y_addr_out3__1_n_90\,
P(14) => \y_addr_out3__1_n_91\,
P(13) => \y_addr_out3__1_n_92\,
P(12) => \y_addr_out3__1_n_93\,
P(11) => \y_addr_out3__1_n_94\,
P(10) => \y_addr_out3__1_n_95\,
P(9) => \y_addr_out3__1_n_96\,
P(8) => \y_addr_out3__1_n_97\,
P(7) => \y_addr_out3__1_n_98\,
P(6) => \y_addr_out3__1_n_99\,
P(5) => \y_addr_out3__1_n_100\,
P(4) => \y_addr_out3__1_n_101\,
P(3) => \y_addr_out3__1_n_102\,
P(2) => \y_addr_out3__1_n_103\,
P(1) => \y_addr_out3__1_n_104\,
P(0) => \y_addr_out3__1_n_105\,
PATTERNBDETECT => \NLW_y_addr_out3__1_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_y_addr_out3__1_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47) => \y_addr_out3__1_n_106\,
PCOUT(46) => \y_addr_out3__1_n_107\,
PCOUT(45) => \y_addr_out3__1_n_108\,
PCOUT(44) => \y_addr_out3__1_n_109\,
PCOUT(43) => \y_addr_out3__1_n_110\,
PCOUT(42) => \y_addr_out3__1_n_111\,
PCOUT(41) => \y_addr_out3__1_n_112\,
PCOUT(40) => \y_addr_out3__1_n_113\,
PCOUT(39) => \y_addr_out3__1_n_114\,
PCOUT(38) => \y_addr_out3__1_n_115\,
PCOUT(37) => \y_addr_out3__1_n_116\,
PCOUT(36) => \y_addr_out3__1_n_117\,
PCOUT(35) => \y_addr_out3__1_n_118\,
PCOUT(34) => \y_addr_out3__1_n_119\,
PCOUT(33) => \y_addr_out3__1_n_120\,
PCOUT(32) => \y_addr_out3__1_n_121\,
PCOUT(31) => \y_addr_out3__1_n_122\,
PCOUT(30) => \y_addr_out3__1_n_123\,
PCOUT(29) => \y_addr_out3__1_n_124\,
PCOUT(28) => \y_addr_out3__1_n_125\,
PCOUT(27) => \y_addr_out3__1_n_126\,
PCOUT(26) => \y_addr_out3__1_n_127\,
PCOUT(25) => \y_addr_out3__1_n_128\,
PCOUT(24) => \y_addr_out3__1_n_129\,
PCOUT(23) => \y_addr_out3__1_n_130\,
PCOUT(22) => \y_addr_out3__1_n_131\,
PCOUT(21) => \y_addr_out3__1_n_132\,
PCOUT(20) => \y_addr_out3__1_n_133\,
PCOUT(19) => \y_addr_out3__1_n_134\,
PCOUT(18) => \y_addr_out3__1_n_135\,
PCOUT(17) => \y_addr_out3__1_n_136\,
PCOUT(16) => \y_addr_out3__1_n_137\,
PCOUT(15) => \y_addr_out3__1_n_138\,
PCOUT(14) => \y_addr_out3__1_n_139\,
PCOUT(13) => \y_addr_out3__1_n_140\,
PCOUT(12) => \y_addr_out3__1_n_141\,
PCOUT(11) => \y_addr_out3__1_n_142\,
PCOUT(10) => \y_addr_out3__1_n_143\,
PCOUT(9) => \y_addr_out3__1_n_144\,
PCOUT(8) => \y_addr_out3__1_n_145\,
PCOUT(7) => \y_addr_out3__1_n_146\,
PCOUT(6) => \y_addr_out3__1_n_147\,
PCOUT(5) => \y_addr_out3__1_n_148\,
PCOUT(4) => \y_addr_out3__1_n_149\,
PCOUT(3) => \y_addr_out3__1_n_150\,
PCOUT(2) => \y_addr_out3__1_n_151\,
PCOUT(1) => \y_addr_out3__1_n_152\,
PCOUT(0) => \y_addr_out3__1_n_153\,
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_y_addr_out3__1_UNDERFLOW_UNCONNECTED\
);
\y_addr_out3__2\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => rot_m10(15),
A(28) => rot_m10(15),
A(27) => rot_m10(15),
A(26) => rot_m10(15),
A(25) => rot_m10(15),
A(24) => rot_m10(15),
A(23) => rot_m10(15),
A(22) => rot_m10(15),
A(21) => rot_m10(15),
A(20) => rot_m10(15),
A(19) => rot_m10(15),
A(18) => rot_m10(15),
A(17) => rot_m10(15),
A(16) => rot_m10(15),
A(15 downto 0) => rot_m10(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_y_addr_out3__2_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17 downto 7) => B"00000000000",
B(6 downto 0) => x_addr_in(9 downto 3),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_y_addr_out3__2_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_y_addr_out3__2_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_y_addr_out3__2_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_y_addr_out3__2_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"1010101",
OVERFLOW => \NLW_y_addr_out3__2_OVERFLOW_UNCONNECTED\,
P(47) => \y_addr_out3__2_n_58\,
P(46) => \y_addr_out3__2_n_59\,
P(45) => \y_addr_out3__2_n_60\,
P(44) => \y_addr_out3__2_n_61\,
P(43) => \y_addr_out3__2_n_62\,
P(42) => \y_addr_out3__2_n_63\,
P(41) => \y_addr_out3__2_n_64\,
P(40) => \y_addr_out3__2_n_65\,
P(39) => \y_addr_out3__2_n_66\,
P(38) => \y_addr_out3__2_n_67\,
P(37) => \y_addr_out3__2_n_68\,
P(36) => \y_addr_out3__2_n_69\,
P(35) => \y_addr_out3__2_n_70\,
P(34) => \y_addr_out3__2_n_71\,
P(33) => \y_addr_out3__2_n_72\,
P(32) => \y_addr_out3__2_n_73\,
P(31) => \y_addr_out3__2_n_74\,
P(30) => \y_addr_out3__2_n_75\,
P(29) => \y_addr_out3__2_n_76\,
P(28) => \y_addr_out3__2_n_77\,
P(27) => \y_addr_out3__2_n_78\,
P(26) => \y_addr_out3__2_n_79\,
P(25) => \y_addr_out3__2_n_80\,
P(24) => \y_addr_out3__2_n_81\,
P(23) => \y_addr_out3__2_n_82\,
P(22) => \y_addr_out3__2_n_83\,
P(21) => \y_addr_out3__2_n_84\,
P(20) => \y_addr_out3__2_n_85\,
P(19) => \y_addr_out3__2_n_86\,
P(18) => \y_addr_out3__2_n_87\,
P(17) => \y_addr_out3__2_n_88\,
P(16) => \y_addr_out3__2_n_89\,
P(15) => \y_addr_out3__2_n_90\,
P(14) => \y_addr_out3__2_n_91\,
P(13) => \y_addr_out3__2_n_92\,
P(12) => \y_addr_out3__2_n_93\,
P(11) => \y_addr_out3__2_n_94\,
P(10) => \y_addr_out3__2_n_95\,
P(9) => \y_addr_out3__2_n_96\,
P(8) => \y_addr_out3__2_n_97\,
P(7) => \y_addr_out3__2_n_98\,
P(6) => \y_addr_out3__2_n_99\,
P(5) => \y_addr_out3__2_n_100\,
P(4) => \y_addr_out3__2_n_101\,
P(3) => \y_addr_out3__2_n_102\,
P(2) => \y_addr_out3__2_n_103\,
P(1) => \y_addr_out3__2_n_104\,
P(0) => \y_addr_out3__2_n_105\,
PATTERNBDETECT => \NLW_y_addr_out3__2_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_y_addr_out3__2_PATTERNDETECT_UNCONNECTED\,
PCIN(47) => \y_addr_out3__1_n_106\,
PCIN(46) => \y_addr_out3__1_n_107\,
PCIN(45) => \y_addr_out3__1_n_108\,
PCIN(44) => \y_addr_out3__1_n_109\,
PCIN(43) => \y_addr_out3__1_n_110\,
PCIN(42) => \y_addr_out3__1_n_111\,
PCIN(41) => \y_addr_out3__1_n_112\,
PCIN(40) => \y_addr_out3__1_n_113\,
PCIN(39) => \y_addr_out3__1_n_114\,
PCIN(38) => \y_addr_out3__1_n_115\,
PCIN(37) => \y_addr_out3__1_n_116\,
PCIN(36) => \y_addr_out3__1_n_117\,
PCIN(35) => \y_addr_out3__1_n_118\,
PCIN(34) => \y_addr_out3__1_n_119\,
PCIN(33) => \y_addr_out3__1_n_120\,
PCIN(32) => \y_addr_out3__1_n_121\,
PCIN(31) => \y_addr_out3__1_n_122\,
PCIN(30) => \y_addr_out3__1_n_123\,
PCIN(29) => \y_addr_out3__1_n_124\,
PCIN(28) => \y_addr_out3__1_n_125\,
PCIN(27) => \y_addr_out3__1_n_126\,
PCIN(26) => \y_addr_out3__1_n_127\,
PCIN(25) => \y_addr_out3__1_n_128\,
PCIN(24) => \y_addr_out3__1_n_129\,
PCIN(23) => \y_addr_out3__1_n_130\,
PCIN(22) => \y_addr_out3__1_n_131\,
PCIN(21) => \y_addr_out3__1_n_132\,
PCIN(20) => \y_addr_out3__1_n_133\,
PCIN(19) => \y_addr_out3__1_n_134\,
PCIN(18) => \y_addr_out3__1_n_135\,
PCIN(17) => \y_addr_out3__1_n_136\,
PCIN(16) => \y_addr_out3__1_n_137\,
PCIN(15) => \y_addr_out3__1_n_138\,
PCIN(14) => \y_addr_out3__1_n_139\,
PCIN(13) => \y_addr_out3__1_n_140\,
PCIN(12) => \y_addr_out3__1_n_141\,
PCIN(11) => \y_addr_out3__1_n_142\,
PCIN(10) => \y_addr_out3__1_n_143\,
PCIN(9) => \y_addr_out3__1_n_144\,
PCIN(8) => \y_addr_out3__1_n_145\,
PCIN(7) => \y_addr_out3__1_n_146\,
PCIN(6) => \y_addr_out3__1_n_147\,
PCIN(5) => \y_addr_out3__1_n_148\,
PCIN(4) => \y_addr_out3__1_n_149\,
PCIN(3) => \y_addr_out3__1_n_150\,
PCIN(2) => \y_addr_out3__1_n_151\,
PCIN(1) => \y_addr_out3__1_n_152\,
PCIN(0) => \y_addr_out3__1_n_153\,
PCOUT(47 downto 0) => \NLW_y_addr_out3__2_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_y_addr_out3__2_UNDERFLOW_UNCONNECTED\
);
\y_addr_out[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => y_addr_out2(28),
I1 => t_y(0),
O => p_0_in(0)
);
\y_addr_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => enable,
D => p_0_in(0),
Q => y_addr_out(0),
R => '0'
);
\y_addr_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => enable,
D => p_0_in(1),
Q => y_addr_out(1),
R => '0'
);
\y_addr_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => enable,
D => p_0_in(2),
Q => y_addr_out(2),
R => '0'
);
\y_addr_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => enable,
D => p_0_in(3),
Q => y_addr_out(3),
R => '0'
);
\y_addr_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => enable,
D => p_0_in(4),
Q => y_addr_out(4),
R => '0'
);
\y_addr_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => enable,
D => p_0_in(5),
Q => y_addr_out(5),
R => '0'
);
\y_addr_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => enable,
D => p_0_in(6),
Q => y_addr_out(6),
R => '0'
);
\y_addr_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => enable,
D => p_0_in(7),
Q => y_addr_out(7),
R => '0'
);
\y_addr_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => enable,
D => p_0_in(8),
Q => y_addr_out(8),
R => '0'
);
\y_addr_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => clk,
CE => enable,
D => p_0_in(9),
Q => y_addr_out(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_transform_0_1 is
port (
clk : in STD_LOGIC;
enable : in STD_LOGIC;
x_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_in : in STD_LOGIC_VECTOR ( 9 downto 0 );
rot_m00 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m01 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m10 : in STD_LOGIC_VECTOR ( 15 downto 0 );
rot_m11 : in STD_LOGIC_VECTOR ( 15 downto 0 );
t_x : in STD_LOGIC_VECTOR ( 9 downto 0 );
t_y : in STD_LOGIC_VECTOR ( 9 downto 0 );
x_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 );
y_addr_out : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_transform_0_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_transform_0_1 : entity is "system_vga_transform_0_1,vga_transform,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_transform_0_1 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_transform_0_1 : entity is "vga_transform,Vivado 2016.4";
end system_vga_transform_0_1;
architecture STRUCTURE of system_vga_transform_0_1 is
begin
U0: entity work.system_vga_transform_0_1_vga_transform
port map (
clk => clk,
enable => enable,
rot_m00(15 downto 0) => rot_m00(15 downto 0),
rot_m01(15 downto 0) => rot_m01(15 downto 0),
rot_m10(15 downto 0) => rot_m10(15 downto 0),
rot_m11(15 downto 0) => rot_m11(15 downto 0),
t_x(9 downto 0) => t_x(9 downto 0),
t_y(9 downto 0) => t_y(9 downto 0),
x_addr_in(9 downto 0) => x_addr_in(9 downto 0),
x_addr_out(9 downto 0) => x_addr_out(9 downto 0),
y_addr_in(9 downto 0) => y_addr_in(9 downto 0),
y_addr_out(9 downto 0) => y_addr_out(9 downto 0)
);
end STRUCTURE;
|
mit
|
CampbellGroup/fpga
|
ltc1450/clock/clock.vhd
|
1
|
805
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY signal_generator IS
PORT (clk : IN STD_LOGIC;
reset : IN STD_LOGIC; --unused
led: OUT STD_LOGIC;
clock_out : OUT STD_LOGIC);
END signal_generator;
ARCHITECTURE behavior of signal_generator IS
SIGNAL clk_sig : std_logic;
SIGNAL led_sig : std_logic;
BEGIN
PROCESS(clk)
VARIABLE count1 : integer;
VARIABLE count2 : integer;
BEGIN
IF rising_edge(clk) then
IF (count1=5) THEN
clk_sig<=NOT(clk_sig);
count1:=0;
ELSE
count1:=count1+1;
END IF;
IF (count2=24999999) THEN --((input clock)/2-1)
led_sig<=NOT(led_sig);
count2:=0;
ELSE
count2:=count2+1;
END IF;
END IF;
END PROCESS;
clock_out <= clk_sig;
led <= led_sig;
END behavior;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
general_ip/svd_2x2/svd_2x2.srcs/sources_1/ip/arctan/arctan_stub.vhdl
|
1
|
1454
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue May 30 11:58:28 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/general_ip/svd_2x2/svd_2x2.runs/arctan_synth_1/arctan_stub.vhdl
-- Design : arctan
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity arctan is
Port (
aclk : in STD_LOGIC;
s_axis_cartesian_tvalid : in STD_LOGIC;
s_axis_cartesian_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_dout_tvalid : out STD_LOGIC;
m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end arctan;
architecture stub of arctan is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_cartesian_tvalid,s_axis_cartesian_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[15:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "cordic_v6_0_11,Vivado 2016.4";
begin
end;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_ov7670_controller_1_0/system_ov7670_controller_1_0_stub.vhdl
|
1
|
1525
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Thu May 25 15:29:18 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_ov7670_controller_1_0 -prefix
-- system_ov7670_controller_1_0_ system_ov7670_controller_1_0_stub.vhdl
-- Design : system_ov7670_controller_1_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_ov7670_controller_1_0 is
Port (
clk : in STD_LOGIC;
resend : in STD_LOGIC;
config_finished : out STD_LOGIC;
sioc : out STD_LOGIC;
siod : inout STD_LOGIC;
reset : out STD_LOGIC;
pwdn : out STD_LOGIC;
xclk : out STD_LOGIC
);
end system_ov7670_controller_1_0;
architecture stub of system_ov7670_controller_1_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,resend,config_finished,sioc,siod,reset,pwdn,xclk";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "ov7670_controller,Vivado 2016.4";
begin
end;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_camera_hessian/zed_camera_hessian.srcs/sources_1/bd/system/ipshared/0b31/zed_hdmi.vhd
|
7
|
6019
|
----------------------------------------------------------------------------------
-- Authors: Mike Field <[email protected]>
-- Rob Taglang <[email protected]>
--
-- Create Date: 06:01:06 01/23/2013
-- Modified: 5/20/2017
--
-- Description:
-- Drive the ADV7511 HDMI encoder directly from the PL fabric.
-- Modified to fit modularly with other designs
--
-- Notes:
-- Technically, the ADV7511 supports rgb input formats, and it would
-- be really nice to be able to just drive that straight through.
-- Unfortunately, the pin mapping for hdmi_d maps to the [23-8] input
-- pins on the IC, and there is not rgb format that lies only in that
-- range of pins.
--
-- http://www.analog.com/media/en/technical-documentation/user-guides/ADV7511_Programming_Guide.pdf
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity zed_hdmi is
port(
clk : in std_logic;
clk_x2 : in std_logic;
clk_100 : in std_logic;
active : in std_logic;
hsync : in std_logic;
vsync : in std_logic;
rgb888 : in std_logic_vector(23 downto 0);
hdmi_clk : out std_logic;
hdmi_hsync : out std_logic;
hdmi_vsync : out std_logic;
hdmi_d : out std_logic_vector(15 downto 0);
hdmi_de : out std_logic;
hdmi_scl : out std_logic;
hdmi_sda : inout std_logic
);
end zed_hdmi;
architecture Behavioral of zed_hdmi is
component i2c_sender
port(
clk : IN std_logic;
resend : IN std_logic;
siod : INOUT std_logic;
sioc : OUT std_logic
);
end component;
signal hdmi_clk_bits : STD_LOGIC_VECTOR (1 downto 0);
signal edge : std_logic := '0';
signal edge_rb : std_logic := '0';
signal r, g, b : std_logic_vector(7 downto 0);
signal y, cr, cb : std_logic_vector(7 downto 0);
begin
-- there is a 16 bit interface into the HDMI transmitter, although I only use 8 bits
r <= rgb888(23 downto 16);
g <= rgb888(15 downto 8);
b <= rgb888(7 downto 0);
hdmi_d(7 downto 0) <= x"00";
process(clk_x2)
variable y_hold, cr_hold, cb_hold : std_logic_vector(7 downto 0);
begin
---------------------------------------------------------------------------
-- signal generation for the HDMI encoder
--
-- Transfer on rising edge of clock Y
-- on falling edge of clock Either Cr or Cb
----------------------------------------------------------------------------
if rising_edge(clk_x2) then
if edge = '0' then
edge <= '1';
hdmi_clk_bits <= "11";
if edge_rb = '0' then
-- lock in value from conversion
y_hold := y;
cr_hold := cr;
cb_hold := cb;
end if;
if active = '0' then
hdmi_d(15 downto 8) <= (others => '0');
hdmi_de <= '0';
edge_rb <= '0';
else
hdmi_d(15 downto 8) <= y_hold;
hdmi_de <= '1';
end if;
else
edge <= '0';
hdmi_clk_bits <= "00";
if active = '0' then
hdmi_d(15 downto 8) <= (others => '0');
hdmi_de <= '0';
edge_rb <= '0';
else
if edge_rb = '0' then
hdmi_d(15 downto 8) <= cr_hold;
edge_rb <= '1';
else
hdmi_d(15 downto 8) <= cb_hold;
edge_rb <= '0';
end if;
hdmi_de <= '1';
end if;
end if;
hdmi_hsync <= not hsync;
hdmi_vsync <= not vsync;
end if;
end process;
process (clk)
variable r_int, g_int, b_int, y_int, cr_int, cb_int : integer;
begin
if rising_edge(clk) then
-- color space conversion and clamping
r_int := to_integer(unsigned(r));
g_int := to_integer(unsigned(g));
b_int := to_integer(unsigned(b));
y_int := ((r_int * 77) / 256) + ((g_int * 150) / 256) + ((b_int * 29) / 256);
cr_int := ((r_int * 131) / 256) - ((g_int * 110) / 256) - ((b_int * 21) / 256) + 128;
cb_int := -((r_int * 44) / 256) - ((g_int * 87) / 256) + ((b_int * 131) / 256) + 128;
end if;
if falling_edge(clk) then
if y_int > 255 then
y <= (others => '1');
elsif y_int < 0 then
y <= (others => '0');
else
y <= std_logic_vector(to_unsigned(y_int, 8));
end if;
if cr_int > 255 then
cr <= (others => '1');
elsif cr_int < 0 then
cr <= (others => '0');
else
cr <= std_logic_vector(to_unsigned(cr_int, 8));
end if;
if cb_int > 255 then
cb <= (others => '1');
elsif cb_int < 0 then
cb <= (others => '0');
else
cb <= std_logic_vector(to_unsigned(cb_int, 8));
end if;
end if;
end process;
ODDR_inst : ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE", INIT => '0',SRTYPE => "SYNC")
port map (
Q => hdmi_clk,
C => clk_x2,
D1 => hdmi_clk_bits(0),
D2 => hdmi_clk_bits(1),
CE => '1', R => '0', S => '0'
);
Inst_i2c_sender: i2c_sender PORT MAP(
clk => clk_100,
resend => '0',
sioc => hdmi_scl,
siod => hdmi_sda
);
end Behavioral;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ipshared/0b31/zed_hdmi.vhd
|
7
|
6019
|
----------------------------------------------------------------------------------
-- Authors: Mike Field <[email protected]>
-- Rob Taglang <[email protected]>
--
-- Create Date: 06:01:06 01/23/2013
-- Modified: 5/20/2017
--
-- Description:
-- Drive the ADV7511 HDMI encoder directly from the PL fabric.
-- Modified to fit modularly with other designs
--
-- Notes:
-- Technically, the ADV7511 supports rgb input formats, and it would
-- be really nice to be able to just drive that straight through.
-- Unfortunately, the pin mapping for hdmi_d maps to the [23-8] input
-- pins on the IC, and there is not rgb format that lies only in that
-- range of pins.
--
-- http://www.analog.com/media/en/technical-documentation/user-guides/ADV7511_Programming_Guide.pdf
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity zed_hdmi is
port(
clk : in std_logic;
clk_x2 : in std_logic;
clk_100 : in std_logic;
active : in std_logic;
hsync : in std_logic;
vsync : in std_logic;
rgb888 : in std_logic_vector(23 downto 0);
hdmi_clk : out std_logic;
hdmi_hsync : out std_logic;
hdmi_vsync : out std_logic;
hdmi_d : out std_logic_vector(15 downto 0);
hdmi_de : out std_logic;
hdmi_scl : out std_logic;
hdmi_sda : inout std_logic
);
end zed_hdmi;
architecture Behavioral of zed_hdmi is
component i2c_sender
port(
clk : IN std_logic;
resend : IN std_logic;
siod : INOUT std_logic;
sioc : OUT std_logic
);
end component;
signal hdmi_clk_bits : STD_LOGIC_VECTOR (1 downto 0);
signal edge : std_logic := '0';
signal edge_rb : std_logic := '0';
signal r, g, b : std_logic_vector(7 downto 0);
signal y, cr, cb : std_logic_vector(7 downto 0);
begin
-- there is a 16 bit interface into the HDMI transmitter, although I only use 8 bits
r <= rgb888(23 downto 16);
g <= rgb888(15 downto 8);
b <= rgb888(7 downto 0);
hdmi_d(7 downto 0) <= x"00";
process(clk_x2)
variable y_hold, cr_hold, cb_hold : std_logic_vector(7 downto 0);
begin
---------------------------------------------------------------------------
-- signal generation for the HDMI encoder
--
-- Transfer on rising edge of clock Y
-- on falling edge of clock Either Cr or Cb
----------------------------------------------------------------------------
if rising_edge(clk_x2) then
if edge = '0' then
edge <= '1';
hdmi_clk_bits <= "11";
if edge_rb = '0' then
-- lock in value from conversion
y_hold := y;
cr_hold := cr;
cb_hold := cb;
end if;
if active = '0' then
hdmi_d(15 downto 8) <= (others => '0');
hdmi_de <= '0';
edge_rb <= '0';
else
hdmi_d(15 downto 8) <= y_hold;
hdmi_de <= '1';
end if;
else
edge <= '0';
hdmi_clk_bits <= "00";
if active = '0' then
hdmi_d(15 downto 8) <= (others => '0');
hdmi_de <= '0';
edge_rb <= '0';
else
if edge_rb = '0' then
hdmi_d(15 downto 8) <= cr_hold;
edge_rb <= '1';
else
hdmi_d(15 downto 8) <= cb_hold;
edge_rb <= '0';
end if;
hdmi_de <= '1';
end if;
end if;
hdmi_hsync <= not hsync;
hdmi_vsync <= not vsync;
end if;
end process;
process (clk)
variable r_int, g_int, b_int, y_int, cr_int, cb_int : integer;
begin
if rising_edge(clk) then
-- color space conversion and clamping
r_int := to_integer(unsigned(r));
g_int := to_integer(unsigned(g));
b_int := to_integer(unsigned(b));
y_int := ((r_int * 77) / 256) + ((g_int * 150) / 256) + ((b_int * 29) / 256);
cr_int := ((r_int * 131) / 256) - ((g_int * 110) / 256) - ((b_int * 21) / 256) + 128;
cb_int := -((r_int * 44) / 256) - ((g_int * 87) / 256) + ((b_int * 131) / 256) + 128;
end if;
if falling_edge(clk) then
if y_int > 255 then
y <= (others => '1');
elsif y_int < 0 then
y <= (others => '0');
else
y <= std_logic_vector(to_unsigned(y_int, 8));
end if;
if cr_int > 255 then
cr <= (others => '1');
elsif cr_int < 0 then
cr <= (others => '0');
else
cr <= std_logic_vector(to_unsigned(cr_int, 8));
end if;
if cb_int > 255 then
cb <= (others => '1');
elsif cb_int < 0 then
cb <= (others => '0');
else
cb <= std_logic_vector(to_unsigned(cb_int, 8));
end if;
end if;
end process;
ODDR_inst : ODDR
generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE", INIT => '0',SRTYPE => "SYNC")
port map (
Q => hdmi_clk,
C => clk_x2,
D1 => hdmi_clk_bits(0),
D2 => hdmi_clk_bits(1),
CE => '1', R => '0', S => '0'
);
Inst_i2c_sender: i2c_sender PORT MAP(
clk => clk_100,
resend => '0',
sioc => hdmi_scl,
siod => hdmi_sda
);
end Behavioral;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
video_ip/zed_hdmi/zed_hdmi.srcs/sources_1/new/src/colour_space_conversion.vhd
|
1
|
43843
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
-- Module Name: colour_space_conversion - Behavioral
--
-- Description: Convert the input pixel data into YCbCr 422 values
--
-- Feel free to use this how you see fit, and fix any errors you find :-)
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity colour_space_conversion is
Port ( clk : in STD_LOGIC;
r1_in : IN std_logic_vector(8 downto 0);
g1_in : IN std_logic_vector(8 downto 0);
b1_in : IN std_logic_vector(8 downto 0);
r2_in : IN std_logic_vector(8 downto 0);
g2_in : IN std_logic_vector(8 downto 0);
b2_in : IN std_logic_vector(8 downto 0);
pair_start_in: IN std_logic;
de_in : IN std_logic;
vsync_in : IN std_logic;
hsync_in : IN std_logic;
y_out : OUT std_logic_vector(7 downto 0);
c_out : OUT std_logic_vector(7 downto 0);
de_out : OUT std_logic;
hsync_out : OUT std_logic;
vsync_out : OUT std_logic
);
end colour_space_conversion;
architecture Behavioral of colour_space_conversion is
signal d_a : std_logic;
signal h_a : std_logic;
signal v_a : std_logic;
signal c1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
signal a_r1, a_g1, a_b1 : STD_LOGIC_VECTOR(29 DOWNTO 0);
signal b_r1, b_g1, b_b1 : STD_LOGIC_VECTOR(17 DOWNTO 0);
signal pc_r1, pc_g1, p_b1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
signal c2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
signal a_r2, a_g2 , a_b2 : STD_LOGIC_VECTOR(29 DOWNTO 0);
signal b_r2, b_g2, b_b2 : STD_LOGIC_VECTOR(17 DOWNTO 0);
signal pc_r2, pc_g2, p_b2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
signal hs_delay : STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
signal vs_delay : STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
signal de_delay : STD_LOGIC_VECTOR(3 DOWNTO 0) := (others => '0');
begin
-- y = ( 8432 * r + 16425 * g + 3176 * B) / 32768 + 16;
-- cb = (-4818 * r - 9527 * g + 14345 * B) / 32768 + 128;
-- cr = (14345 * r - 12045 * g - 2300 * B) / 32768 + 128;
c1 <= x"002000000000";
a_r1 <= "000000" & r1_in & x"000" & "000";
a_g1 <= "000000" & g1_in & x"000" & "000";
a_b1 <= "000000" & b1_in & x"000" & "000";
c2 <= x"010000000000";
a_r2 <= "000000" & r2_in & x"000" & "000";
a_g2 <= "000000" & g2_in & x"000" & "000";
a_b2 <= "000000" & b2_in & x"000" & "000";
b_r1 <= x"20F0"&"00";
b_g1 <= x"4029"&"00";
b_b1 <= x"0C68"&"00";
b_r2 <= x"ED2E"&"00" when pair_start_in = '1' else x"3809"&"00";
b_g2 <= x"DAC9"&"00" when pair_start_in = '1' else x"D0F3"&"00";
b_b2 <= x"3809"&"00" when pair_start_in = '1' else x"F704"&"00";
process(clk)
begin
if rising_edge(clk) then
hsync_out <= hs_delay(hs_delay'high);
vsync_out <= vs_delay(vs_delay'high);
de_out <= de_delay(de_delay'high);
de_delay <= de_delay(de_delay'high-1 downto 0) & de_in;
vs_delay <= vs_delay(de_delay'high-1 downto 0) & vsync_in;
hs_delay <= hs_delay(de_delay'high-1 downto 0) & hsync_in;
y_out <= p_b1(40 downto 33);
c_out <= p_b2(40 downto 33);
end if;
end process;
mult_r1 : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
USE_MULT => "MULTIPLY", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12")
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 0, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
ADREG => 0, -- Number of pipeline stages for pre-adder (0 or 1)
ALUMODEREG => 1, -- Number of pipeline stages for ALUMODE (0 or 1)
AREG => 0, -- Number of pipeline stages for A (0, 1 or 2)
BCASCREG => 0, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
BREG => 0, -- Number of pipeline stages for B (0, 1 or 2)
CARRYINREG => 1, -- Number of pipeline stages for CARRYIN (0 or 1)
CARRYINSELREG => 1, -- Number of pipeline stages for CARRYINSEL (0 or 1)
CREG => 0, -- Number of pipeline stages for C (0 or 1)
DREG => 0, -- Number of pipeline stages for D (0 or 1)
INMODEREG => 1, -- Number of pipeline stages for INMODE (0 or 1)
MREG => 1, -- Number of multiplier pipeline stages (0 or 1)
OPMODEREG => 1, -- Number of pipeline stages for OPMODE (0 or 1)
PREG => 1 -- Number of pipeline stages for P (0 or 1)
)
port map (
-- Cascade: 30-bit (each) output: Cascade Ports
ACOUT => open, -- 30-bit output: A port cascade output
BCOUT => open, -- 18-bit output: B port cascade output
CARRYCASCOUT => open, -- 1-bit output: Cascade carry output
MULTSIGNOUT => open, -- 1-bit output: Multiplier sign cascade output
PCOUT => PC_r1, -- 48-bit output: Cascade output
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => open, -- 1-bit output: Overflow in add/acc output
PATTERNBDETECT => open, -- 1-bit output: Pattern bar detect output
PATTERNDETECT => open, -- 1-bit output: Pattern detect output
UNDERFLOW => open, -- 1-bit output: Underflow in add/acc output
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => open, -- 4-bit output: Carry output
P => open, -- 48-bit output: Primary data output
-- Cascade: 30-bit (each) input: Cascade Ports
ACIN => (others => '0'), -- 30-bit input: A cascade data input
BCIN => (others => '0'), -- 18-bit input: B cascade input
CARRYCASCIN => '0', -- 1-bit input: Cascade carry input
MULTSIGNIN => '0', -- 1-bit input: Multiplier sign input
PCIN => (others => '0'), -- 48-bit input: P cascade input
-- Control: 4-bit (each) input: Control Inputs/Status Bits
CLK => CLK, -- 1-bit input: Clock input
ALUMODE => "0000", -- 4-bit input: ALU control input
CARRYINSEL => "000", -- 3-bit input: Carry select input
CEINMODE => '1', -- 1-bit input: Clock enable input for INMODEREG
INMODE => "00000", -- 5-bit input: INMODE control input
OPMODE => "0110101", -- 7-bit input: Operation mode input
RSTINMODE => '0', -- 1-bit input: Reset input for INMODEREG
-- Data: 30-bit (each) input: Data Ports
A => a_r1, -- 30-bit input: A data input
B => b_r1, -- 18-bit input: B data input
C => c1, -- 48-bit input: C data input
CARRYIN => '0', -- 1-bit input: Carry input signal
D => (others =>'0'), -- 25-bit input: D data input
-- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
CEA1 => '0', -- 1-bit input: Clock enable input for 1st stage AREG
CEA2 => '0', -- 1-bit input: Clock enable input for 2nd stage AREG
CEAD => '0', -- 1-bit input: Clock enable input for ADREG
CEALUMODE => '1', -- 1-bit input: Clock enable input for ALUMODE
CEB1 => '0', -- 1-bit input: Clock enable input for 1st stage BREG
CEB2 => '0', -- 1-bit input: Clock enable input for 2nd stage BREG
CEC => '0', -- 1-bit input: Clock enable input for CREG
CECARRYIN => '1', -- 1-bit input: Clock enable input for CARRYINREG
CECTRL => '1', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
CED => '0', -- 1-bit input: Clock enable input for DREG
CEM => '1', -- 1-bit input: Clock enable input for MREG
CEP => '1', -- 1-bit input: Clock enable input for PREG
RSTA => '0', -- 1-bit input: Reset input for AREG
RSTALLCARRYIN => '0', -- 1-bit input: Reset input for CARRYINREG
RSTALUMODE => '0', -- 1-bit input: Reset input for ALUMODEREG
RSTB => '0', -- 1-bit input: Reset input for BREG
RSTC => '0', -- 1-bit input: Reset input for CREG
RSTCTRL => '0', -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
RSTD => '0', -- 1-bit input: Reset input for DREG and ADREG
RSTM => '0', -- 1-bit input: Reset input for MREG
RSTP => '0' -- 1-bit input: Reset input for PREG
);
mult_g1 : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
USE_MULT => "MULTIPLY", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12")
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 1, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
ADREG => 0, -- Number of pipeline stages for pre-adder (0 or 1)
ALUMODEREG => 1, -- Number of pipeline stages for ALUMODE (0 or 1)
AREG => 1, -- Number of pipeline stages for A (0, 1 or 2)
BCASCREG => 1, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
BREG => 1, -- Number of pipeline stages for B (0, 1 or 2)
CARRYINREG => 1, -- Number of pipeline stages for CARRYIN (0 or 1)
CARRYINSELREG => 1, -- Number of pipeline stages for CARRYINSEL (0 or 1)
CREG => 0, -- Number of pipeline stages for C (0 or 1)
DREG => 0, -- Number of pipeline stages for D (0 or 1)
INMODEREG => 1, -- Number of pipeline stages for INMODE (0 or 1)
MREG => 1, -- Number of multiplier pipeline stages (0 or 1)
OPMODEREG => 1, -- Number of pipeline stages for OPMODE (0 or 1)
PREG => 1 -- Number of pipeline stages for P (0 or 1)
)
port map (
-- Cascade: 30-bit (each) input: Cascade Ports
ACOUT => open, -- 30-bit output: A port cascade output
BCOUT => open, -- 18-bit output: B port cascade output
CARRYCASCOUT => open, -- 1-bit output: Cascade carry output
MULTSIGNOUT => open, -- 1-bit output: Multiplier sign cascade output
PCOUT => PC_g1, -- 48-bit output: Cascade output
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => open, -- 1-bit output: Overflow in add/acc output
PATTERNBDETECT => open, -- 1-bit output: Pattern bar detect output
PATTERNDETECT => open, -- 1-bit output: Pattern detect output
UNDERFLOW => open, -- 1-bit output: Underflow in add/acc output
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => open, -- 4-bit output: Carry output
P => open, -- 48-bit output: Primary data output
-- Cascade: 30-bit (each) input: Cascade Ports
ACIN => (others => '0'), -- 30-bit input: A cascade data input
BCIN => (others => '0'), -- 18-bit input: B cascade input
CARRYCASCIN => '0', -- 1-bit input: Cascade carry input
MULTSIGNIN => '0', -- 1-bit input: Multiplier sign input
PCIN => pc_r1, -- 48-bit input: P cascade input
-- Control: 4-bit (each) input: Control Inputs/Status Bits
CLK => CLK, -- 1-bit input: Clock input
ALUMODE => "0000", -- 4-bit input: ALU control input
CARRYINSEL => "000", -- 3-bit input: Carry select input
CEINMODE => '1', -- 1-bit input: Clock enable input for INMODEREG
INMODE => "00000", -- 5-bit input: INMODE control input
OPMODE => "0010101", -- 7-bit input: Operation mode input
RSTINMODE => '0', -- 1-bit input: Reset input for INMODEREG
-- Data: 30-bit (each) input: Data Ports
A => a_g1, -- 30-bit input: A data input
B => b_g1, -- 18-bit input: B data input
C => (others =>'0'), -- 48-bit input: C data input
CARRYIN => '0', -- 1-bit input: Carry input signal
D => (others =>'0'), -- 25-bit input: D data input
-- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
CEA1 => '0', -- 1-bit input: Clock enable input for 1st stage AREG
CEA2 => '1', -- 1-bit input: Clock enable input for 2nd stage AREG
CEAD => '1', -- 1-bit input: Clock enable input for ADREG
CEALUMODE => '1', -- 1-bit input: Clock enable input for ALUMODE
CEB1 => '0', -- 1-bit input: Clock enable input for 1st stage BREG
CEB2 => '1', -- 1-bit input: Clock enable input for 2nd stage BREG
CEC => '0', -- 1-bit input: Clock enable input for CREG
CECARRYIN => '1', -- 1-bit input: Clock enable input for CARRYINREG
CECTRL => '1', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
CED => '0', -- 1-bit input: Clock enable input for DREG
CEM => '1', -- 1-bit input: Clock enable input for MREG
CEP => '1', -- 1-bit input: Clock enable input for PREG
RSTA => '0', -- 1-bit input: Reset input for AREG
RSTALLCARRYIN => '0', -- 1-bit input: Reset input for CARRYINREG
RSTALUMODE => '0', -- 1-bit input: Reset input for ALUMODEREG
RSTB => '0', -- 1-bit input: Reset input for BREG
RSTC => '0', -- 1-bit input: Reset input for CREG
RSTCTRL => '0', -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
RSTD => '0', -- 1-bit input: Reset input for DREG and ADREG
RSTM => '0', -- 1-bit input: Reset input for MREG
RSTP => '0' -- 1-bit input: Reset input for PREG
);
mult_b1 : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
USE_MULT => "MULTIPLY", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12")
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 2, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
ADREG => 0, -- Number of pipeline stages for pre-adder (0 or 1)
ALUMODEREG => 1, -- Number of pipeline stages for ALUMODE (0 or 1)
AREG => 2, -- Number of pipeline stages for A (0, 1 or 2)
BCASCREG => 1, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
BREG => 1, -- Number of pipeline stages for B (0, 1 or 2)
CARRYINREG => 1, -- Number of pipeline stages for CARRYIN (0 or 1)
CARRYINSELREG => 1, -- Number of pipeline stages for CARRYINSEL (0 or 1)
CREG => 0, -- Number of pipeline stages for C (0 or 1)
DREG => 0, -- Number of pipeline stages for D (0 or 1)
INMODEREG => 1, -- Number of pipeline stages for INMODE (0 or 1)
MREG => 1, -- Number of multiplier pipeline stages (0 or 1)
OPMODEREG => 1, -- Number of pipeline stages for OPMODE (0 or 1)
PREG => 1 -- Number of pipeline stages for P (0 or 1)
)
port map (
-- Cascade: 30-bit (each) output: Cascade Ports
ACOUT => open, -- 30-bit output: A port cascade output
BCOUT => open, -- 18-bit output: B port cascade output
CARRYCASCOUT => open, -- 1-bit output: Cascade carry output
MULTSIGNOUT => open, -- 1-bit output: Multiplier sign cascade output
PCOUT => open, -- 48-bit output: Cascade output
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => open, -- 1-bit output: Overflow in add/acc output
PATTERNBDETECT => open, -- 1-bit output: Pattern bar detect output
PATTERNDETECT => open, -- 1-bit output: Pattern detect output
UNDERFLOW => open, -- 1-bit output: Underflow in add/acc output
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => open, -- 4-bit output: Carry output
P => P_b1, -- 48-bit output: Primary data output
-- Cascade: 30-bit (each) input: Cascade Ports
ACIN => (others =>'0'), -- 30-bit input: A cascade data input
BCIN => (others =>'0'), -- 18-bit input: B cascade input
CARRYCASCIN => '0', -- 1-bit input: Cascade carry input
MULTSIGNIN => '0', -- 1-bit input: Multiplier sign input
PCIN => pc_g1, -- 48-bit input: P cascade input
-- Control: 4-bit (each) input: Control Inputs/Status Bits
CLK => CLK, -- 1-bit input: Clock input
ALUMODE => "0000", -- 4-bit input: ALU control input
CARRYINSEL => "000", -- 3-bit input: Carry select input
CEINMODE => '1', -- 1-bit input: Clock enable input for INMODEREG
INMODE => "00000", -- 5-bit input: INMODE control input
OPMODE => "0010101", -- 7-bit input: Operation mode input
RSTINMODE => '0', -- 1-bit input: Reset input for INMODEREG
-- Data: 30-bit (each) input: Data Ports
A => a_b1, -- 30-bit input: A data input
B => b_b1, -- 18-bit input: B data input
C => (others =>'0'), -- 48-bit input: C data input
CARRYIN => '0', -- 1-bit input: Carry input signal
D => (others =>'0'), -- 25-bit input: D data input
-- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
CEA1 => '1', -- 1-bit input: Clock enable input for 1st stage AREG
CEA2 => '1', -- 1-bit input: Clock enable input for 2nd stage AREG
CEAD => '0', -- 1-bit input: Clock enable input for ADREG
CEALUMODE => '1', -- 1-bit input: Clock enable input for ALUMODE
CEB1 => '0', -- 1-bit input: Clock enable input for 1st stage BREG
CEB2 => '1', -- 1-bit input: Clock enable input for 2nd stage BREG
CEC => '0', -- 1-bit input: Clock enable input for CREG
CECARRYIN => '1', -- 1-bit input: Clock enable input for CARRYINREG
CECTRL => '1', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
CED => '0', -- 1-bit input: Clock enable input for DREG
CEM => '1', -- 1-bit input: Clock enable input for MREG
CEP => '1', -- 1-bit input: Clock enable input for PREG
RSTA => '0', -- 1-bit input: Reset input for AREG
RSTALLCARRYIN => '0', -- 1-bit input: Reset input for CARRYINREG
RSTALUMODE => '0', -- 1-bit input: Reset input for ALUMODEREG
RSTB => '0', -- 1-bit input: Reset input for BREG
RSTC => '0', -- 1-bit input: Reset input for CREG
RSTCTRL => '0', -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
RSTD => '0', -- 1-bit input: Reset input for DREG and ADREG
RSTM => '0', -- 1-bit input: Reset input for MREG
RSTP => '0' -- 1-bit input: Reset input for PREG
);
-----------------------------------------
mult_r2 : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
USE_MULT => "MULTIPLY", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12")
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 0, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
ADREG => 0, -- Number of pipeline stages for pre-adder (0 or 1)
ALUMODEREG => 1, -- Number of pipeline stages for ALUMODE (0 or 1)
AREG => 0, -- Number of pipeline stages for A (0, 1 or 2)
BCASCREG => 0, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
BREG => 0, -- Number of pipeline stages for B (0, 1 or 2)
CARRYINREG => 1, -- Number of pipeline stages for CARRYIN (0 or 1)
CARRYINSELREG => 1, -- Number of pipeline stages for CARRYINSEL (0 or 1)
CREG => 0, -- Number of pipeline stages for C (0 or 1)
DREG => 0, -- Number of pipeline stages for D (0 or 1)
INMODEREG => 1, -- Number of pipeline stages for INMODE (0 or 1)
MREG => 1, -- Number of multiplier pipeline stages (0 or 1)
OPMODEREG => 1, -- Number of pipeline stages for OPMODE (0 or 1)
PREG => 1 -- Number of pipeline stages for P (0 or 1)
)
port map (
-- Cascade: 30-bit (each) output: Cascade Ports
ACOUT => open, -- 30-bit output: A port cascade output
BCOUT => open, -- 18-bit output: B port cascade output
CARRYCASCOUT => open, -- 1-bit output: Cascade carry output
MULTSIGNOUT => open, -- 1-bit output: Multiplier sign cascade output
PCOUT => PC_r2, -- 48-bit output: Cascade output
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => open, -- 1-bit output: Overflow in add/acc output
PATTERNBDETECT => open, -- 1-bit output: Pattern bar detect output
PATTERNDETECT => open, -- 1-bit output: Pattern detect output
UNDERFLOW => open, -- 1-bit output: Underflow in add/acc output
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => open, -- 4-bit output: Carry output
P => open, -- 48-bit output: Primary data output
-- Cascade: 30-bit (each) input: Cascade Ports
ACIN => (others => '0'), -- 30-bit input: A cascade data input
BCIN => (others => '0'), -- 18-bit input: B cascade input
CARRYCASCIN => '0', -- 1-bit input: Cascade carry input
MULTSIGNIN => '0', -- 1-bit input: Multiplier sign input
PCIN => (others => '0'), -- 48-bit input: P cascade input
-- Control: 4-bit (each) input: Control Inputs/Status Bits
CLK => CLK, -- 1-bit input: Clock input
ALUMODE => "0000", -- 4-bit input: ALU control input
CARRYINSEL => "000", -- 3-bit input: Carry select input
CEINMODE => '1', -- 1-bit input: Clock enable input for INMODEREG
INMODE => "00000", -- 5-bit input: INMODE control input
OPMODE => "0110101", -- 7-bit input: Operation mode input
RSTINMODE => '0', -- 1-bit input: Reset input for INMODEREG
-- Data: 30-bit (each) input: Data Ports
A => a_r2, -- 30-bit input: A data input
B => b_r2, -- 18-bit input: B data input
C => c2, -- 48-bit input: C data input
CARRYIN => '0', -- 1-bit input: Carry input signal
D => (others =>'0'), -- 25-bit input: D data input
-- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
CEA1 => '0', -- 1-bit input: Clock enable input for 1st stage AREG
CEA2 => '0', -- 1-bit input: Clock enable input for 2nd stage AREG
CEAD => '0', -- 1-bit input: Clock enable input for ADREG
CEALUMODE => '1', -- 1-bit input: Clock enable input for ALUMODE
CEB1 => '0', -- 1-bit input: Clock enable input for 1st stage BREG
CEB2 => '0', -- 1-bit input: Clock enable input for 2nd stage BREG
CEC => '0', -- 1-bit input: Clock enable input for CREG
CECARRYIN => '1', -- 1-bit input: Clock enable input for CARRYINREG
CECTRL => '1', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
CED => '0', -- 1-bit input: Clock enable input for DREG
CEM => '1', -- 1-bit input: Clock enable input for MREG
CEP => '1', -- 1-bit input: Clock enable input for PREG
RSTA => '0', -- 1-bit input: Reset input for AREG
RSTALLCARRYIN => '0', -- 1-bit input: Reset input for CARRYINREG
RSTALUMODE => '0', -- 1-bit input: Reset input for ALUMODEREG
RSTB => '0', -- 1-bit input: Reset input for BREG
RSTC => '0', -- 1-bit input: Reset input for CREG
RSTCTRL => '0', -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
RSTD => '0', -- 1-bit input: Reset input for DREG and ADREG
RSTM => '0', -- 1-bit input: Reset input for MREG
RSTP => '0' -- 1-bit input: Reset input for PREG
);
mult_g2 : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
USE_MULT => "MULTIPLY", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12")
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 1, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
ADREG => 0, -- Number of pipeline stages for pre-adder (0 or 1)
ALUMODEREG => 1, -- Number of pipeline stages for ALUMODE (0 or 1)
AREG => 1, -- Number of pipeline stages for A (0, 1 or 2)
BCASCREG => 1, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
BREG => 1, -- Number of pipeline stages for B (0, 1 or 2)
CARRYINREG => 1, -- Number of pipeline stages for CARRYIN (0 or 1)
CARRYINSELREG => 1, -- Number of pipeline stages for CARRYINSEL (0 or 1)
CREG => 0, -- Number of pipeline stages for C (0 or 1)
DREG => 0, -- Number of pipeline stages for D (0 or 1)
INMODEREG => 1, -- Number of pipeline stages for INMODE (0 or 1)
MREG => 1, -- Number of multiplier pipeline stages (0 or 1)
OPMODEREG => 1, -- Number of pipeline stages for OPMODE (0 or 1)
PREG => 1 -- Number of pipeline stages for P (0 or 1)
)
port map (
-- Cascade: 30-bit (each) output: Cascade Ports
ACOUT => open, -- 30-bit output: A port cascade output
BCOUT => open, -- 18-bit output: B port cascade output
CARRYCASCOUT => open, -- 1-bit output: Cascade carry output
MULTSIGNOUT => open, -- 1-bit output: Multiplier sign cascade output
PCOUT => PC_g2, -- 48-bit output: Cascade output
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => open, -- 1-bit output: Overflow in add/acc output
PATTERNBDETECT => open, -- 1-bit output: Pattern bar detect output
PATTERNDETECT => open, -- 1-bit output: Pattern detect output
UNDERFLOW => open, -- 1-bit output: Underflow in add/acc output
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => open, -- 4-bit output: Carry output
P => open, -- 48-bit output: Primary data output
-- Cascade: 30-bit (each) input: Cascade Ports
ACIN => (others=>'0'), -- 30-bit input: A cascade data input
BCIN => (others=>'0'), -- 18-bit input: B cascade input
CARRYCASCIN => '0', -- 1-bit input: Cascade carry input
MULTSIGNIN => '0', -- 1-bit input: Multiplier sign input
PCIN => pc_r2, -- 48-bit input: P cascade input
-- Control: 4-bit (each) input: Control Inputs/Status Bits
CLK => CLK, -- 1-bit input: Clock input
ALUMODE => "0000", -- 4-bit input: ALU control input
CARRYINSEL => "000", -- 3-bit input: Carry select input
CEINMODE => '1', -- 1-bit input: Clock enable input for INMODEREG
INMODE => "00000", -- 5-bit input: INMODE control input
OPMODE => "0010101", -- 7-bit input: Operation mode input
RSTINMODE => '0', -- 1-bit input: Reset input for INMODEREG
-- Data: 30-bit (each) input: Data Ports
A => a_g2, -- 30-bit input: A data input
B => b_g2, -- 18-bit input: B data input
C => (others =>'0'), -- 48-bit input: C data input
CARRYIN => '0', -- 1-bit input: Carry input signal
D => (others =>'0'), -- 25-bit input: D data input
-- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
CEA1 => '0', -- 1-bit input: Clock enable input for 1st stage AREG
CEA2 => '1', -- 1-bit input: Clock enable input for 2nd stage AREG
CEAD => '0', -- 1-bit input: Clock enable input for ADREG
CEALUMODE => '1', -- 1-bit input: Clock enable input for ALUMODE
CEB1 => '0', -- 1-bit input: Clock enable input for 1st stage BREG
CEB2 => '1', -- 1-bit input: Clock enable input for 2nd stage BREG
CEC => '0', -- 1-bit input: Clock enable input for CREG
CECARRYIN => '1', -- 1-bit input: Clock enable input for CARRYINREG
CECTRL => '1', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
CED => '0', -- 1-bit input: Clock enable input for DREG
CEM => '1', -- 1-bit input: Clock enable input for MREG
CEP => '1', -- 1-bit input: Clock enable input for PREG
RSTA => '0', -- 1-bit input: Reset input for AREG
RSTALLCARRYIN => '0', -- 1-bit input: Reset input for CARRYINREG
RSTALUMODE => '0', -- 1-bit input: Reset input for ALUMODEREG
RSTB => '0', -- 1-bit input: Reset input for BREG
RSTC => '0', -- 1-bit input: Reset input for CREG
RSTCTRL => '0', -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
RSTD => '0', -- 1-bit input: Reset input for DREG and ADREG
RSTM => '0', -- 1-bit input: Reset input for MREG
RSTP => '0' -- 1-bit input: Reset input for PREG
);
mult_b2 : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT", -- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
B_INPUT => "DIRECT", -- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
USE_DPORT => FALSE, -- Select D port usage (TRUE or FALSE)
USE_MULT => "MULTIPLY", -- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
USE_SIMD => "ONE48", -- SIMD selection ("ONE48", "TWO24", "FOUR12")
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET", -- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
MASK => X"3fffffffffff", -- 48-bit mask value for pattern detect (1=ignore)
PATTERN => X"000000000000", -- 48-bit pattern match for pattern detect
SEL_MASK => "MASK", -- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
SEL_PATTERN => "PATTERN", -- Select pattern value ("PATTERN" or "C")
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 2, -- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
ADREG => 0, -- Number of pipeline stages for pre-adder (0 or 1)
ALUMODEREG => 1, -- Number of pipeline stages for ALUMODE (0 or 1)
AREG => 2, -- Number of pipeline stages for A (0, 1 or 2)
BCASCREG => 2, -- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
BREG => 2, -- Number of pipeline stages for B (0, 1 or 2)
CARRYINREG => 1, -- Number of pipeline stages for CARRYIN (0 or 1)
CARRYINSELREG => 1, -- Number of pipeline stages for CARRYINSEL (0 or 1)
CREG => 0, -- Number of pipeline stages for C (0 or 1)
DREG => 0, -- Number of pipeline stages for D (0 or 1)
INMODEREG => 1, -- Number of pipeline stages for INMODE (0 or 1)
MREG => 1, -- Number of multiplier pipeline stages (0 or 1)
OPMODEREG => 1, -- Number of pipeline stages for OPMODE (0 or 1)
PREG => 1 -- Number of pipeline stages for P (0 or 1)
)
port map (
-- Cascade: 30-bit (each) output: Cascade Ports
ACOUT => open, -- 30-bit output: A port cascade output
BCOUT => open, -- 18-bit output: B port cascade output
CARRYCASCOUT => open, -- 1-bit output: Cascade carry output
MULTSIGNOUT => open, -- 1-bit output: Multiplier sign cascade output
PCOUT => open, -- 48-bit output: Cascade output
-- Control: 1-bit (each) output: Control Inputs/Status Bits
OVERFLOW => open, -- 1-bit output: Overflow in add/acc output
PATTERNBDETECT => open, -- 1-bit output: Pattern bar detect output
PATTERNDETECT => open, -- 1-bit output: Pattern detect output
UNDERFLOW => open, -- 1-bit output: Underflow in add/acc output
-- Data: 4-bit (each) output: Data Ports
CARRYOUT => open, -- 4-bit output: Carry output
P => P_b2, -- 48-bit output: Primary data output
-- Cascade: 30-bit (each) input: Cascade Ports
ACIN => (others =>'0'), -- 30-bit input: A cascade data input
BCIN => (others =>'0'), -- 18-bit input: B cascade input
CARRYCASCIN => '0', -- 1-bit input: Cascade carry input
MULTSIGNIN => '0', -- 1-bit input: Multiplier sign input
PCIN => pc_g2, -- 48-bit input: P cascade input
-- Control: 4-bit (each) input: Control Inputs/Status Bits
CLK => CLK, -- 1-bit input: Clock input
ALUMODE => "0000", -- 4-bit input: ALU control input
CARRYINSEL => "000", -- 3-bit input: Carry select input
CEINMODE => '1', -- 1-bit input: Clock enable input for INMODEREG
INMODE => "00000", -- 5-bit input: INMODE control input
OPMODE => "0010101", -- 7-bit input: Operation mode input
RSTINMODE => '0', -- 1-bit input: Reset input for INMODEREG
-- Data: 30-bit (each) input: Data Ports
A => a_b2, -- 30-bit input: A data input
B => b_b2, -- 18-bit input: B data input
C => (others =>'0'), -- 48-bit input: C data input
CARRYIN => '0', -- 1-bit input: Carry input signal
D => (others =>'0'), -- 25-bit input: D data input
-- Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
CEA1 => '1', -- 1-bit input: Clock enable input for 1st stage AREG
CEA2 => '1', -- 1-bit input: Clock enable input for 2nd stage AREG
CEAD => '0', -- 1-bit input: Clock enable input for ADREG
CEALUMODE => '1', -- 1-bit input: Clock enable input for ALUMODE
CEB1 => '1', -- 1-bit input: Clock enable input for 1st stage BREG
CEB2 => '1', -- 1-bit input: Clock enable input for 2nd stage BREG
CEC => '0', -- 1-bit input: Clock enable input for CREG
CECARRYIN => '1', -- 1-bit input: Clock enable input for CARRYINREG
CECTRL => '1', -- 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
CED => '0', -- 1-bit input: Clock enable input for DREG
CEM => '1', -- 1-bit input: Clock enable input for MREG
CEP => '1', -- 1-bit input: Clock enable input for PREG
RSTA => '0', -- 1-bit input: Reset input for AREG
RSTALLCARRYIN => '0', -- 1-bit input: Reset input for CARRYINREG
RSTALUMODE => '0', -- 1-bit input: Reset input for ALUMODEREG
RSTB => '0', -- 1-bit input: Reset input for BREG
RSTC => '0', -- 1-bit input: Reset input for CREG
RSTCTRL => '0', -- 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
RSTD => '0', -- 1-bit input: Reset input for DREG and ADREG
RSTM => '0', -- 1-bit input: Reset input for MREG
RSTP => '0' -- 1-bit input: Reset input for PREG
);
end Behavioral;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_transform_test/zed_transform_test.srcs/sources_1/bd/system/ip/system_buffer_register_1_0/system_buffer_register_1_0_stub.vhdl
|
1
|
1392
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Jun 04 17:33:00 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_buffer_register_1_0 -prefix
-- system_buffer_register_1_0_ system_buffer_register_0_0_stub.vhdl
-- Design : system_buffer_register_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_buffer_register_1_0 is
Port (
clk : in STD_LOGIC;
val_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
val_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end system_buffer_register_1_0;
architecture stub of system_buffer_register_1_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,val_in[31:0],val_out[31:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "buffer_register,Vivado 2016.4";
begin
end;
|
mit
|
ashikpoojari/Hardware-Security
|
DES CryptoCore/src/desxor1.vhd
|
2
|
475
|
library ieee;
use ieee.std_logic_1164.all;
entity desxor1 is port
(
e : in std_logic_vector(1 TO 48);
b1x,b2x,b3x,b4x,b5x,b6x,b7x,b8x
: out std_logic_vector (1 TO 6);
k : in std_logic_vector (1 TO 48)
);
end desxor1;
architecture behavior of desxor1 is
signal XX : std_logic_vector( 1 to 48);
begin
XX<=k xor e;
b1x<=XX(1 to 6);
b2x<=XX(7 to 12);
b3x<=XX(13 to 18);
b4x<=XX(19 to 24);
b5x<=XX(25 to 30);
b6x<=XX(31 to 36);
b7x<=XX(37 to 42);
b8x<=XX(43 to 48);
end behavior;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ipshared/8e0d/rgb565_to_rgb888.vhd
|
6
|
1494
|
----------------------------------------------------------------------------------
-- Company: Drexel University
-- Engineer: Rob Taglang
--
-- Module Name: rgb565_to_rgb888 - Structural
-- Description: Convert 16-bit rgb565 to 24-bit rgb888
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity rgb565_to_rgb888 is
port(
clk: in std_logic;
rgb_565: in std_logic_vector(15 downto 0);
rgb_888: out std_logic_vector(23 downto 0)
);
end rgb565_to_rgb888;
architecture Structural of rgb565_to_rgb888 is
signal red, green, blue: std_logic_vector(7 downto 0) := "00000000";
begin
red(4 downto 0) <= rgb_565(15 downto 11);
green(5 downto 0) <= rgb_565(10 downto 5);
blue(4 downto 0) <= rgb_565(4 downto 0);
process(clk)
variable r_1, r_2, g_1, g_2, b_1, b_2: unsigned(7 downto 0);
begin
if rising_edge(clk) then
r_1 := unsigned(red) sll 3;
r_2 := unsigned(red) srl 2;
g_1 := unsigned(green) sll 2;
g_2 := unsigned(green) srl 4;
b_1 := unsigned(blue) sll 3;
b_2 := unsigned(blue) sll 2;
rgb_888(23 downto 16) <= std_logic_vector(r_1 or r_2);
rgb_888(15 downto 8) <= std_logic_vector(g_1 or g_2);
rgb_888(7 downto 0) <= std_logic_vector(b_1 or b_1);
end if;
end process;
end Structural;
|
mit
|
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox
|
examples/zed_vga_test/zed_vga_test.srcs/sources_1/bd/system/ip/system_vga_sync_0_0/system_vga_sync_0_0_sim_netlist.vhdl
|
1
|
17575
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon May 08 23:35:07 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/ZyboIP/examples/zed_vga_test/zed_vga_test.srcs/sources_1/bd/system/ip/system_vga_sync_0_0/system_vga_sync_0_0_sim_netlist.vhdl
-- Design : system_vga_sync_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_0_0_vga_sync is
port (
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_vga_sync_0_0_vga_sync : entity is "vga_sync";
end system_vga_sync_0_0_vga_sync;
architecture STRUCTURE of system_vga_sync_0_0_vga_sync is
signal active0 : STD_LOGIC;
signal active_i_3_n_0 : STD_LOGIC;
signal clear : STD_LOGIC;
signal \h_count_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \h_count_reg[9]_i_2_n_0\ : STD_LOGIC;
signal hsync_i_1_n_0 : STD_LOGIC;
signal hsync_i_2_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal sel : STD_LOGIC;
signal \v_count_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \v_count_reg[6]_i_1_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_3_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \v_count_reg[9]_i_5_n_0\ : STD_LOGIC;
signal \^vsync\ : STD_LOGIC;
signal vsync_i_1_n_0 : STD_LOGIC;
signal vsync_i_2_n_0 : STD_LOGIC;
signal \^xaddr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \^yaddr\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of active_i_3 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \h_count_reg[1]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \h_count_reg[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \h_count_reg[3]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \h_count_reg[4]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \h_count_reg[6]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[7]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \h_count_reg[9]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of hsync_i_2 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \v_count_reg[1]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[3]_i_2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \v_count_reg[4]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \v_count_reg[6]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \v_count_reg[7]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \v_count_reg[8]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \v_count_reg[9]_i_5\ : label is "soft_lutpair0";
begin
vsync <= \^vsync\;
xaddr(9 downto 0) <= \^xaddr\(9 downto 0);
yaddr(9 downto 0) <= \^yaddr\(9 downto 0);
active_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0022002A"
)
port map (
I0 => active_i_3_n_0,
I1 => \^xaddr\(9),
I2 => \^xaddr\(7),
I3 => \^yaddr\(9),
I4 => \^xaddr\(8),
O => active0
);
active_i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rst,
O => clear
);
active_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \^yaddr\(6),
I1 => \^yaddr\(5),
I2 => \^yaddr\(7),
I3 => \^yaddr\(8),
O => active_i_3_n_0
);
active_reg: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
CLR => clear,
D => active0,
Q => active
);
\h_count_reg[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^xaddr\(0),
O => p_0_in(0)
);
\h_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^xaddr\(1),
I1 => \^xaddr\(0),
O => p_0_in(1)
);
\h_count_reg[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^xaddr\(1),
I1 => \^xaddr\(0),
I2 => \^xaddr\(2),
O => p_0_in(2)
);
\h_count_reg[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^xaddr\(3),
I1 => \^xaddr\(1),
I2 => \^xaddr\(0),
I3 => \^xaddr\(2),
O => p_0_in(3)
);
\h_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^xaddr\(4),
I1 => \^xaddr\(2),
I2 => \^xaddr\(0),
I3 => \^xaddr\(1),
I4 => \^xaddr\(3),
O => p_0_in(4)
);
\h_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"33332333CCCCCCCC"
)
port map (
I0 => \^xaddr\(6),
I1 => \^xaddr\(5),
I2 => \^xaddr\(8),
I3 => \^xaddr\(9),
I4 => \^xaddr\(7),
I5 => \h_count_reg[9]_i_2_n_0\,
O => p_0_in(5)
);
\h_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^xaddr\(6),
I1 => \^xaddr\(5),
I2 => \h_count_reg[9]_i_2_n_0\,
O => p_0_in(6)
);
\h_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^xaddr\(7),
I1 => \h_count_reg[9]_i_2_n_0\,
I2 => \^xaddr\(5),
I3 => \^xaddr\(6),
O => p_0_in(7)
);
\h_count_reg[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"3FFFFFF7C0000000"
)
port map (
I0 => \^xaddr\(9),
I1 => \h_count_reg[9]_i_2_n_0\,
I2 => \^xaddr\(5),
I3 => \^xaddr\(7),
I4 => \^xaddr\(6),
I5 => \^xaddr\(8),
O => \h_count_reg[8]_i_1_n_0\
);
\h_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7F80EF00FF00FF00"
)
port map (
I0 => \^xaddr\(6),
I1 => \^xaddr\(5),
I2 => \^xaddr\(8),
I3 => \^xaddr\(9),
I4 => \^xaddr\(7),
I5 => \h_count_reg[9]_i_2_n_0\,
O => p_0_in(9)
);
\h_count_reg[9]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => \^xaddr\(1),
I1 => \^xaddr\(0),
I2 => \^xaddr\(2),
I3 => \^xaddr\(4),
I4 => \^xaddr\(3),
O => \h_count_reg[9]_i_2_n_0\
);
\h_count_reg_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => clear,
D => p_0_in(0),
Q => \^xaddr\(0)
);
\h_count_reg_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => clear,
D => p_0_in(1),
Q => \^xaddr\(1)
);
\h_count_reg_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => clear,
D => p_0_in(2),
Q => \^xaddr\(2)
);
\h_count_reg_reg[3]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => clear,
D => p_0_in(3),
Q => \^xaddr\(3)
);
\h_count_reg_reg[4]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => clear,
D => p_0_in(4),
Q => \^xaddr\(4)
);
\h_count_reg_reg[5]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => clear,
D => p_0_in(5),
Q => \^xaddr\(5)
);
\h_count_reg_reg[6]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => clear,
D => p_0_in(6),
Q => \^xaddr\(6)
);
\h_count_reg_reg[7]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => clear,
D => p_0_in(7),
Q => \^xaddr\(7)
);
\h_count_reg_reg[8]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => clear,
D => \h_count_reg[8]_i_1_n_0\,
Q => \^xaddr\(8)
);
\h_count_reg_reg[9]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => '1',
CLR => clear,
D => p_0_in(9),
Q => \^xaddr\(9)
);
hsync_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFBFBFBFBFBFBFFF"
)
port map (
I0 => \^xaddr\(8),
I1 => \^xaddr\(9),
I2 => \^xaddr\(7),
I3 => hsync_i_2_n_0,
I4 => \^xaddr\(5),
I5 => \^xaddr\(6),
O => hsync_i_1_n_0
);
hsync_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA8"
)
port map (
I0 => \^xaddr\(4),
I1 => \^xaddr\(2),
I2 => \^xaddr\(3),
I3 => \^xaddr\(1),
I4 => \^xaddr\(0),
O => hsync_i_2_n_0
);
hsync_reg: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => hsync_i_1_n_0,
PRE => clear,
Q => hsync
);
\v_count_reg[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"5555555545555555"
)
port map (
I0 => \^yaddr\(0),
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \^yaddr\(9),
I3 => \^yaddr\(2),
I4 => \^yaddr\(3),
I5 => \^yaddr\(7),
O => \p_0_in__0\(0)
);
\v_count_reg[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^yaddr\(0),
I1 => \^yaddr\(1),
O => \p_0_in__0\(1)
);
\v_count_reg[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"55AA55AA45AA55AA"
)
port map (
I0 => \v_count_reg[3]_i_2_n_0\,
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \^yaddr\(9),
I3 => \^yaddr\(2),
I4 => \^yaddr\(3),
I5 => \^yaddr\(7),
O => \p_0_in__0\(2)
);
\v_count_reg[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"55FFAA0045FFAA00"
)
port map (
I0 => \v_count_reg[3]_i_2_n_0\,
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \^yaddr\(9),
I3 => \^yaddr\(2),
I4 => \^yaddr\(3),
I5 => \^yaddr\(7),
O => \p_0_in__0\(3)
);
\v_count_reg[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^yaddr\(0),
I1 => \^yaddr\(1),
O => \v_count_reg[3]_i_2_n_0\
);
\v_count_reg[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^yaddr\(4),
I1 => \^yaddr\(2),
I2 => \^yaddr\(3),
I3 => \^yaddr\(0),
I4 => \^yaddr\(1),
O => \p_0_in__0\(4)
);
\v_count_reg[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \^yaddr\(5),
I1 => \^yaddr\(1),
I2 => \^yaddr\(0),
I3 => \^yaddr\(3),
I4 => \^yaddr\(2),
I5 => \^yaddr\(4),
O => \p_0_in__0\(5)
);
\v_count_reg[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^yaddr\(6),
I1 => \v_count_reg[9]_i_5_n_0\,
I2 => \^yaddr\(5),
O => \v_count_reg[6]_i_1_n_0\
);
\v_count_reg[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^yaddr\(7),
I1 => \^yaddr\(5),
I2 => \v_count_reg[9]_i_5_n_0\,
I3 => \^yaddr\(6),
O => \p_0_in__0\(7)
);
\v_count_reg[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \^yaddr\(8),
I1 => \^yaddr\(6),
I2 => \v_count_reg[9]_i_5_n_0\,
I3 => \^yaddr\(5),
I4 => \^yaddr\(7),
O => \p_0_in__0\(8)
);
\v_count_reg[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000002000"
)
port map (
I0 => \h_count_reg[9]_i_2_n_0\,
I1 => \^xaddr\(7),
I2 => \^xaddr\(9),
I3 => \^xaddr\(8),
I4 => \^xaddr\(5),
I5 => \^xaddr\(6),
O => sel
);
\v_count_reg[9]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"D0D00DD0"
)
port map (
I0 => \v_count_reg[9]_i_3_n_0\,
I1 => \v_count_reg[9]_i_4_n_0\,
I2 => \^yaddr\(9),
I3 => \v_count_reg[9]_i_5_n_0\,
I4 => active_i_3_n_0,
O => \p_0_in__0\(9)
);
\v_count_reg[9]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \^yaddr\(9),
I1 => \^yaddr\(2),
I2 => \^yaddr\(3),
I3 => \^yaddr\(7),
O => \v_count_reg[9]_i_3_n_0\
);
\v_count_reg[9]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \^yaddr\(1),
I1 => \^yaddr\(0),
I2 => \^yaddr\(6),
I3 => \^yaddr\(8),
I4 => \^yaddr\(4),
I5 => \^yaddr\(5),
O => \v_count_reg[9]_i_4_n_0\
);
\v_count_reg[9]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"80000000"
)
port map (
I0 => \^yaddr\(4),
I1 => \^yaddr\(2),
I2 => \^yaddr\(3),
I3 => \^yaddr\(0),
I4 => \^yaddr\(1),
O => \v_count_reg[9]_i_5_n_0\
);
\v_count_reg_reg[0]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => clear,
D => \p_0_in__0\(0),
Q => \^yaddr\(0)
);
\v_count_reg_reg[1]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => clear,
D => \p_0_in__0\(1),
Q => \^yaddr\(1)
);
\v_count_reg_reg[2]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => clear,
D => \p_0_in__0\(2),
Q => \^yaddr\(2)
);
\v_count_reg_reg[3]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => clear,
D => \p_0_in__0\(3),
Q => \^yaddr\(3)
);
\v_count_reg_reg[4]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => clear,
D => \p_0_in__0\(4),
Q => \^yaddr\(4)
);
\v_count_reg_reg[5]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => clear,
D => \p_0_in__0\(5),
Q => \^yaddr\(5)
);
\v_count_reg_reg[6]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => clear,
D => \v_count_reg[6]_i_1_n_0\,
Q => \^yaddr\(6)
);
\v_count_reg_reg[7]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => clear,
D => \p_0_in__0\(7),
Q => \^yaddr\(7)
);
\v_count_reg_reg[8]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => clear,
D => \p_0_in__0\(8),
Q => \^yaddr\(8)
);
\v_count_reg_reg[9]\: unisim.vcomponents.FDCE
port map (
C => clk,
CE => sel,
CLR => clear,
D => \p_0_in__0\(9),
Q => \^yaddr\(9)
);
vsync_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"E0EE"
)
port map (
I0 => \^vsync\,
I1 => rst,
I2 => active_i_3_n_0,
I3 => vsync_i_2_n_0,
O => vsync_i_1_n_0
);
vsync_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0002000000000000"
)
port map (
I0 => \^yaddr\(1),
I1 => \^yaddr\(2),
I2 => \^yaddr\(4),
I3 => \^yaddr\(9),
I4 => rst,
I5 => \^yaddr\(3),
O => vsync_i_2_n_0
);
vsync_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk,
CE => '1',
D => vsync_i_1_n_0,
Q => \^vsync\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_vga_sync_0_0 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_vga_sync_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_vga_sync_0_0 : entity is "system_vga_sync_0_0,vga_sync,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_vga_sync_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_vga_sync_0_0 : entity is "vga_sync,Vivado 2016.4";
end system_vga_sync_0_0;
architecture STRUCTURE of system_vga_sync_0_0 is
begin
U0: entity work.system_vga_sync_0_0_vga_sync
port map (
active => active,
clk => clk,
hsync => hsync,
rst => rst,
vsync => vsync,
xaddr(9 downto 0) => xaddr(9 downto 0),
yaddr(9 downto 0) => yaddr(9 downto 0)
);
end STRUCTURE;
|
mit
|
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